drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     115
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "October 14, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          RX_STD_MAX_SIZE_5717 : 512)
 108 #define TG3_DEF_RX_RING_PENDING         200
 109 #define TG3_RX_JMB_RING_SIZE(tp) \
 110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 112          1024 : 256)
 113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 114 #define TG3_RSS_INDIR_TBL_SIZE          128
 115
 116 /* Do not place this n-ring entries value into the tp struct itself,
 117  * we really want to expose these constants to GCC so that modulo et
 118  * al.  operations are done with shifts and masks instead of with
 119  * hw multiply/modulo instructions.  Another solution would be to
 120  * replace things like '% foo' with '& (foo - 1)'.
 121  */
 122
 123 #define TG3_TX_RING_SIZE                512
 124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 125
 126 #define TG3_RX_STD_RING_BYTES(tp) \
 127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 128 #define TG3_RX_JMB_RING_BYTES(tp) \
 129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 130 #define TG3_RX_RCB_RING_BYTES(tp) \
 131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 133                                  TG3_TX_RING_SIZE)
 134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 135
 136 #define TG3_RX_DMA_ALIGN                16
 137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 138
 139 #define TG3_DMA_BYTE_ENAB               64
 140
 141 #define TG3_RX_STD_DMA_SZ               1536
 142 #define TG3_RX_JMB_DMA_SZ               9046
 143
 144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 145
 146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 148
 149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 151
 152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 154
 155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 156  * that are at least dword aligned when used in PCIX mode.  The driver
 157  * works around this bug by double copying the packet.  This workaround
 158  * is built into the normal double copy length check for efficiency.
 159  *
 160  * However, the double copy is only necessary on those architectures
 161  * where unaligned memory accesses are inefficient.  For those architectures
 162  * where unaligned memory accesses incur little penalty, we can reintegrate
 163  * the 5701 in the normal rx path.  Doing so saves a device structure
 164  * dereference by hardcoding the double copy threshold in place.
 165  */
 166 #define TG3_RX_COPY_THRESHOLD           256
 167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 169 #else
 170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 171 #endif
 172
 173 /* minimum number of free TX descriptors required to wake up TX process */
 174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 175
 176 #define TG3_RAW_IP_ALIGN 2
 177
 178 /* number of ETHTOOL_GSTATS u64's */
 179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 180
 181 #define TG3_NUM_TEST            6
 182
 183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 184
 185 #define FIRMWARE_TG3            "tigon/tg3.bin"
 186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 188
 189 static char version[] __devinitdata =
 190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 191
 192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 194 MODULE_LICENSE("GPL");
 195 MODULE_VERSION(DRV_MODULE_VERSION);
 196 MODULE_FIRMWARE(FIRMWARE_TG3);
 197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 199
 200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 201 module_param(tg3_debug, int, 0);
 202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 203
 204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 284         {}
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 288
 289 static const struct {
 290         const char string[ETH_GSTRING_LEN];
 291 } ethtool_stats_keys[TG3_NUM_STATS] = {
 292         { "rx_octets" },
 293         { "rx_fragments" },
 294         { "rx_ucast_packets" },
 295         { "rx_mcast_packets" },
 296         { "rx_bcast_packets" },
 297         { "rx_fcs_errors" },
 298         { "rx_align_errors" },
 299         { "rx_xon_pause_rcvd" },
 300         { "rx_xoff_pause_rcvd" },
 301         { "rx_mac_ctrl_rcvd" },
 302         { "rx_xoff_entered" },
 303         { "rx_frame_too_long_errors" },
 304         { "rx_jabbers" },
 305         { "rx_undersize_packets" },
 306         { "rx_in_length_errors" },
 307         { "rx_out_length_errors" },
 308         { "rx_64_or_less_octet_packets" },
 309         { "rx_65_to_127_octet_packets" },
 310         { "rx_128_to_255_octet_packets" },
 311         { "rx_256_to_511_octet_packets" },
 312         { "rx_512_to_1023_octet_packets" },
 313         { "rx_1024_to_1522_octet_packets" },
 314         { "rx_1523_to_2047_octet_packets" },
 315         { "rx_2048_to_4095_octet_packets" },
 316         { "rx_4096_to_8191_octet_packets" },
 317         { "rx_8192_to_9022_octet_packets" },
 318
 319         { "tx_octets" },
 320         { "tx_collisions" },
 321
 322         { "tx_xon_sent" },
 323         { "tx_xoff_sent" },
 324         { "tx_flow_control" },
 325         { "tx_mac_errors" },
 326         { "tx_single_collisions" },
 327         { "tx_mult_collisions" },
 328         { "tx_deferred" },
 329         { "tx_excessive_collisions" },
 330         { "tx_late_collisions" },
 331         { "tx_collide_2times" },
 332         { "tx_collide_3times" },
 333         { "tx_collide_4times" },
 334         { "tx_collide_5times" },
 335         { "tx_collide_6times" },
 336         { "tx_collide_7times" },
 337         { "tx_collide_8times" },
 338         { "tx_collide_9times" },
 339         { "tx_collide_10times" },
 340         { "tx_collide_11times" },
 341         { "tx_collide_12times" },
 342         { "tx_collide_13times" },
 343         { "tx_collide_14times" },
 344         { "tx_collide_15times" },
 345         { "tx_ucast_packets" },
 346         { "tx_mcast_packets" },
 347         { "tx_bcast_packets" },
 348         { "tx_carrier_sense_errors" },
 349         { "tx_discards" },
 350         { "tx_errors" },
 351
 352         { "dma_writeq_full" },
 353         { "dma_write_prioq_full" },
 354         { "rxbds_empty" },
 355         { "rx_discards" },
 356         { "rx_errors" },
 357         { "rx_threshold_hit" },
 358
 359         { "dma_readq_full" },
 360         { "dma_read_prioq_full" },
 361         { "tx_comp_queue_full" },
 362
 363         { "ring_set_send_prod_index" },
 364         { "ring_status_update" },
 365         { "nic_irqs" },
 366         { "nic_avoided_irqs" },
 367         { "nic_tx_threshold_hit" }
 368 };
 369
 370 static const struct {
 371         const char string[ETH_GSTRING_LEN];
 372 } ethtool_test_keys[TG3_NUM_TEST] = {
 373         { "nvram test     (online) " },
 374         { "link test      (online) " },
 375         { "register test  (offline)" },
 376         { "memory test    (offline)" },
 377         { "loopback test  (offline)" },
 378         { "interrupt test (offline)" },
 379 };
 380
 381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384 }
 385
 386 static u32 tg3_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->regs + off);
 389 }
 390
 391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         writel(val, tp->aperegs + off);
 394 }
 395
 396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 397 {
 398         return readl(tp->aperegs + off);
 399 }
 400
 401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409 }
 410
 411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         writel(val, tp->regs + off);
 414         readl(tp->regs + off);
 415 }
 416
 417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 430 {
 431         unsigned long flags;
 432
 433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 435                                        TG3_64BIT_REG_LOW, val);
 436                 return;
 437         }
 438         if (off == TG3_RX_STD_PROD_IDX_REG) {
 439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 440                                        TG3_64BIT_REG_LOW, val);
 441                 return;
 442         }
 443
 444         spin_lock_irqsave(&tp->indirect_lock, flags);
 445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 448
 449         /* In indirect mode when disabling interrupts, we also need
 450          * to clear the interrupt bit in the GRC local ctrl register.
 451          */
 452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 453             (val == 0x1)) {
 454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 456         }
 457 }
 458
 459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 460 {
 461         unsigned long flags;
 462         u32 val;
 463
 464         spin_lock_irqsave(&tp->indirect_lock, flags);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 468         return val;
 469 }
 470
 471 /* usec_wait specifies the wait time in usec when writing to certain registers
 472  * where it is unsafe to read back the register without some delay.
 473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 475  */
 476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 477 {
 478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 480                 /* Non-posted methods */
 481                 tp->write32(tp, off, val);
 482         else {
 483                 /* Posted method */
 484                 tg3_write32(tp, off, val);
 485                 if (usec_wait)
 486                         udelay(usec_wait);
 487                 tp->read32(tp, off);
 488         }
 489         /* Wait again after the read for the posted method to guarantee that
 490          * the wait time is met.
 491          */
 492         if (usec_wait)
 493                 udelay(usec_wait);
 494 }
 495
 496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         tp->write32_mbox(tp, off, val);
 499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 501                 tp->read32_mbox(tp, off);
 502 }
 503
 504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         void __iomem *mbox = tp->regs + off;
 507         writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 509                 writel(val, mbox);
 510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 511                 readl(mbox);
 512 }
 513
 514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 515 {
 516         return readl(tp->regs + off + GRCMBOX_BASE);
 517 }
 518
 519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 520 {
 521         writel(val, tp->regs + off + GRCMBOX_BASE);
 522 }
 523
 524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 529
 530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 533 #define tr32(reg)                       tp->read32(tp, reg)
 534
 535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 541                 return;
 542
 543         spin_lock_irqsave(&tp->indirect_lock, flags);
 544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 547
 548                 /* Always leave this as zero. */
 549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         } else {
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 553
 554                 /* Always leave this as zero. */
 555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 556         }
 557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 558 }
 559
 560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 561 {
 562         unsigned long flags;
 563
 564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 566                 *val = 0;
 567                 return;
 568         }
 569
 570         spin_lock_irqsave(&tp->indirect_lock, flags);
 571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 574
 575                 /* Always leave this as zero. */
 576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 577         } else {
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 580
 581                 /* Always leave this as zero. */
 582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 583         }
 584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 585 }
 586
 587 static void tg3_ape_lock_init(struct tg3 *tp)
 588 {
 589         int i;
 590         u32 regbase;
 591
 592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 593                 regbase = TG3_APE_LOCK_GRANT;
 594         else
 595                 regbase = TG3_APE_PER_LOCK_GRANT;
 596
 597         /* Make sure the driver hasn't any stale locks. */
 598         for (i = 0; i < 8; i++)
 599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 600 }
 601
 602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 603 {
 604         int i, off;
 605         int ret = 0;
 606         u32 status, req, gnt;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return 0;
 610
 611         switch (locknum) {
 612         case TG3_APE_LOCK_GRC:
 613         case TG3_APE_LOCK_MEM:
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 620                 req = TG3_APE_LOCK_REQ;
 621                 gnt = TG3_APE_LOCK_GRANT;
 622         } else {
 623                 req = TG3_APE_PER_LOCK_REQ;
 624                 gnt = TG3_APE_PER_LOCK_GRANT;
 625         }
 626
 627         off = 4 * locknum;
 628
 629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 630
 631         /* Wait for up to 1 millisecond to acquire lock. */
 632         for (i = 0; i < 100; i++) {
 633                 status = tg3_ape_read32(tp, gnt + off);
 634                 if (status == APE_LOCK_GRANT_DRIVER)
 635                         break;
 636                 udelay(10);
 637         }
 638
 639         if (status != APE_LOCK_GRANT_DRIVER) {
 640                 /* Revoke the lock request. */
 641                 tg3_ape_write32(tp, gnt + off,
 642                                 APE_LOCK_GRANT_DRIVER);
 643
 644                 ret = -EBUSY;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 651 {
 652         u32 gnt;
 653
 654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 655                 return;
 656
 657         switch (locknum) {
 658         case TG3_APE_LOCK_GRC:
 659         case TG3_APE_LOCK_MEM:
 660                 break;
 661         default:
 662                 return;
 663         }
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 gnt = TG3_APE_LOCK_GRANT;
 667         else
 668                 gnt = TG3_APE_PER_LOCK_GRANT;
 669
 670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 671 }
 672
 673 static void tg3_disable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tw32(TG3PCI_MISC_HOST_CTRL,
 678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 679         for (i = 0; i < tp->irq_max; i++)
 680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 681 }
 682
 683 static void tg3_enable_ints(struct tg3 *tp)
 684 {
 685         int i;
 686
 687         tp->irq_sync = 0;
 688         wmb();
 689
 690         tw32(TG3PCI_MISC_HOST_CTRL,
 691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 692
 693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 694         for (i = 0; i < tp->irq_cnt; i++) {
 695                 struct tg3_napi *tnapi = &tp->napi[i];
 696
 697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 700
 701                 tp->coal_now |= tnapi->coal_now;
 702         }
 703
 704         /* Force an initial interrupt */
 705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 708         else
 709                 tw32(HOSTCC_MODE, tp->coal_now);
 710
 711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 712 }
 713
 714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 715 {
 716         struct tg3 *tp = tnapi->tp;
 717         struct tg3_hw_status *sblk = tnapi->hw_status;
 718         unsigned int work_exists = 0;
 719
 720         /* check for phy events */
 721         if (!(tp->tg3_flags &
 722               (TG3_FLAG_USE_LINKCHG_REG |
 723                TG3_FLAG_POLL_SERDES))) {
 724                 if (sblk->status & SD_STATUS_LINK_CHG)
 725                         work_exists = 1;
 726         }
 727         /* check for RX/TX work to do */
 728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 730                 work_exists = 1;
 731
 732         return work_exists;
 733 }
 734
 735 /* tg3_int_reenable
 736  *  similar to tg3_enable_ints, but it accurately determines whether there
 737  *  is new work pending and can return without flushing the PIO write
 738  *  which reenables interrupts
 739  */
 740 static void tg3_int_reenable(struct tg3_napi *tnapi)
 741 {
 742         struct tg3 *tp = tnapi->tp;
 743
 744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 745         mmiowb();
 746
 747         /* When doing tagged status, this work check is unnecessary.
 748          * The last_tag we write above tells the chip which piece of
 749          * work we've completed.
 750          */
 751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 752             tg3_has_work(tnapi))
 753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 755 }
 756
 757 static void tg3_switch_clocks(struct tg3 *tp)
 758 {
 759         u32 clock_ctrl;
 760         u32 orig_clock_ctrl;
 761
 762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 764                 return;
 765
 766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 767
 768         orig_clock_ctrl = clock_ctrl;
 769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 770                        CLOCK_CTRL_CLKRUN_OENABLE |
 771                        0x1f);
 772         tp->pci_clock_ctrl = clock_ctrl;
 773
 774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 778                 }
 779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 781                             clock_ctrl |
 782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 783                             40);
 784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 786                             40);
 787         }
 788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 789 }
 790
 791 #define PHY_BUSY_LOOPS  5000
 792
 793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 794 {
 795         u32 frame_val;
 796         unsigned int loops;
 797         int ret;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         *val = 0x0;
 806
 807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 808                       MI_COM_PHY_ADDR_MASK);
 809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 810                       MI_COM_REG_ADDR_MASK);
 811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 812
 813         tw32_f(MAC_MI_COM, frame_val);
 814
 815         loops = PHY_BUSY_LOOPS;
 816         while (loops != 0) {
 817                 udelay(10);
 818                 frame_val = tr32(MAC_MI_COM);
 819
 820                 if ((frame_val & MI_COM_BUSY) == 0) {
 821                         udelay(5);
 822                         frame_val = tr32(MAC_MI_COM);
 823                         break;
 824                 }
 825                 loops -= 1;
 826         }
 827
 828         ret = -EBUSY;
 829         if (loops != 0) {
 830                 *val = frame_val & MI_COM_DATA_MASK;
 831                 ret = 0;
 832         }
 833
 834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 836                 udelay(80);
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 843 {
 844         u32 frame_val;
 845         unsigned int loops;
 846         int ret;
 847
 848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 850                 return 0;
 851
 852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 853                 tw32_f(MAC_MI_MODE,
 854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 855                 udelay(80);
 856         }
 857
 858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 859                       MI_COM_PHY_ADDR_MASK);
 860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 861                       MI_COM_REG_ADDR_MASK);
 862         frame_val |= (val & MI_COM_DATA_MASK);
 863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 864
 865         tw32_f(MAC_MI_COM, frame_val);
 866
 867         loops = PHY_BUSY_LOOPS;
 868         while (loops != 0) {
 869                 udelay(10);
 870                 frame_val = tr32(MAC_MI_COM);
 871                 if ((frame_val & MI_COM_BUSY) == 0) {
 872                         udelay(5);
 873                         frame_val = tr32(MAC_MI_COM);
 874                         break;
 875                 }
 876                 loops -= 1;
 877         }
 878
 879         ret = -EBUSY;
 880         if (loops != 0)
 881                 ret = 0;
 882
 883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 885                 udelay(80);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static int tg3_bmcr_reset(struct tg3 *tp)
 892 {
 893         u32 phy_control;
 894         int limit, err;
 895
 896         /* OK, reset it, and poll the BMCR_RESET bit until it
 897          * clears or we time out.
 898          */
 899         phy_control = BMCR_RESET;
 900         err = tg3_writephy(tp, MII_BMCR, phy_control);
 901         if (err != 0)
 902                 return -EBUSY;
 903
 904         limit = 5000;
 905         while (limit--) {
 906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 907                 if (err != 0)
 908                         return -EBUSY;
 909
 910                 if ((phy_control & BMCR_RESET) == 0) {
 911                         udelay(40);
 912                         break;
 913                 }
 914                 udelay(10);
 915         }
 916         if (limit < 0)
 917                 return -EBUSY;
 918
 919         return 0;
 920 }
 921
 922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 923 {
 924         struct tg3 *tp = bp->priv;
 925         u32 val;
 926
 927         spin_lock_bh(&tp->lock);
 928
 929         if (tg3_readphy(tp, reg, &val))
 930                 val = -EIO;
 931
 932         spin_unlock_bh(&tp->lock);
 933
 934         return val;
 935 }
 936
 937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 938 {
 939         struct tg3 *tp = bp->priv;
 940         u32 ret = 0;
 941
 942         spin_lock_bh(&tp->lock);
 943
 944         if (tg3_writephy(tp, reg, val))
 945                 ret = -EIO;
 946
 947         spin_unlock_bh(&tp->lock);
 948
 949         return ret;
 950 }
 951
 952 static int tg3_mdio_reset(struct mii_bus *bp)
 953 {
 954         return 0;
 955 }
 956
 957 static void tg3_mdio_config_5785(struct tg3 *tp)
 958 {
 959         u32 val;
 960         struct phy_device *phydev;
 961
 962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 964         case PHY_ID_BCM50610:
 965         case PHY_ID_BCM50610M:
 966                 val = MAC_PHYCFG2_50610_LED_MODES;
 967                 break;
 968         case PHY_ID_BCMAC131:
 969                 val = MAC_PHYCFG2_AC131_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8211C:
 972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 973                 break;
 974         case PHY_ID_RTL8201E:
 975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 982                 tw32(MAC_PHYCFG2, val);
 983
 984                 val = tr32(MAC_PHYCFG1);
 985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 988                 tw32(MAC_PHYCFG1, val);
 989
 990                 return;
 991         }
 992
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 995                        MAC_PHYCFG2_FMODE_MASK_MASK |
 996                        MAC_PHYCFG2_GMODE_MASK_MASK |
 997                        MAC_PHYCFG2_ACT_MASK_MASK   |
 998                        MAC_PHYCFG2_QUAL_MASK_MASK |
 999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
2732                         mac_mode |= MAC_MODE_APE_TX_EN |
2733                                     MAC_MODE_APE_RX_EN |
2734                                     MAC_MODE_TDE_ENABLE;
2735
2736                 tw32_f(MAC_MODE, mac_mode);
2737                 udelay(100);
2738
2739                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2740                 udelay(10);
2741         }
2742
2743         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2744             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2745              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2746                 u32 base_val;
2747
2748                 base_val = tp->pci_clock_ctrl;
2749                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2750                              CLOCK_CTRL_TXCLK_DISABLE);
2751
2752                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2753                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2754         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2755                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2756                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2757                 /* do nothing */
2758         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2759                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2760                 u32 newbits1, newbits2;
2761
2762                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2763                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2764                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2765                                     CLOCK_CTRL_TXCLK_DISABLE |
2766                                     CLOCK_CTRL_ALTCLK);
2767                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2768                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2769                         newbits1 = CLOCK_CTRL_625_CORE;
2770                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2771                 } else {
2772                         newbits1 = CLOCK_CTRL_ALTCLK;
2773                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2774                 }
2775
2776                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2777                             40);
2778
2779                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2780                             40);
2781
2782                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2783                         u32 newbits3;
2784
2785                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2786                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2787                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2788                                             CLOCK_CTRL_TXCLK_DISABLE |
2789                                             CLOCK_CTRL_44MHZ_CORE);
2790                         } else {
2791                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2792                         }
2793
2794                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2795                                     tp->pci_clock_ctrl | newbits3, 40);
2796                 }
2797         }
2798
2799         if (!(device_should_wake) &&
2800             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2801                 tg3_power_down_phy(tp, do_low_power);
2802
2803         tg3_frob_aux_power(tp);
2804
2805         /* Workaround for unstable PLL clock */
2806         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2807             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2808                 u32 val = tr32(0x7d00);
2809
2810                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2811                 tw32(0x7d00, val);
2812                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2813                         int err;
2814
2815                         err = tg3_nvram_lock(tp);
2816                         tg3_halt_cpu(tp, RX_CPU_BASE);
2817                         if (!err)
2818                                 tg3_nvram_unlock(tp);
2819                 }
2820         }
2821
2822         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2823
2824         if (device_should_wake)
2825                 pci_enable_wake(tp->pdev, state, true);
2826
2827         /* Finally, set the new power state. */
2828         pci_set_power_state(tp->pdev, state);
2829
2830         return 0;
2831 }
2832
2833 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2834 {
2835         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2836         case MII_TG3_AUX_STAT_10HALF:
2837                 *speed = SPEED_10;
2838                 *duplex = DUPLEX_HALF;
2839                 break;
2840
2841         case MII_TG3_AUX_STAT_10FULL:
2842                 *speed = SPEED_10;
2843                 *duplex = DUPLEX_FULL;
2844                 break;
2845
2846         case MII_TG3_AUX_STAT_100HALF:
2847                 *speed = SPEED_100;
2848                 *duplex = DUPLEX_HALF;
2849                 break;
2850
2851         case MII_TG3_AUX_STAT_100FULL:
2852                 *speed = SPEED_100;
2853                 *duplex = DUPLEX_FULL;
2854                 break;
2855
2856         case MII_TG3_AUX_STAT_1000HALF:
2857                 *speed = SPEED_1000;
2858                 *duplex = DUPLEX_HALF;
2859                 break;
2860
2861         case MII_TG3_AUX_STAT_1000FULL:
2862                 *speed = SPEED_1000;
2863                 *duplex = DUPLEX_FULL;
2864                 break;
2865
2866         default:
2867                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2868                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2869                                  SPEED_10;
2870                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2871                                   DUPLEX_HALF;
2872                         break;
2873                 }
2874                 *speed = SPEED_INVALID;
2875                 *duplex = DUPLEX_INVALID;
2876                 break;
2877         }
2878 }
2879
2880 static void tg3_phy_copper_begin(struct tg3 *tp)
2881 {
2882         u32 new_adv;
2883         int i;
2884
2885         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2886                 /* Entering low power mode.  Disable gigabit and
2887                  * 100baseT advertisements.
2888                  */
2889                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2890
2891                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2892                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2893                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2894                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2895
2896                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2897         } else if (tp->link_config.speed == SPEED_INVALID) {
2898                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2899                         tp->link_config.advertising &=
2900                                 ~(ADVERTISED_1000baseT_Half |
2901                                   ADVERTISED_1000baseT_Full);
2902
2903                 new_adv = ADVERTISE_CSMA;
2904                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2905                         new_adv |= ADVERTISE_10HALF;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2907                         new_adv |= ADVERTISE_10FULL;
2908                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2909                         new_adv |= ADVERTISE_100HALF;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2911                         new_adv |= ADVERTISE_100FULL;
2912
2913                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2914
2915                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                 if (tp->link_config.advertising &
2918                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2919                         new_adv = 0;
2920                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2921                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2924                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2925                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2926                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2927                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2928                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2929                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2930                 } else {
2931                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2932                 }
2933         } else {
2934                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2935                 new_adv |= ADVERTISE_CSMA;
2936
2937                 /* Asking for a specific link mode. */
2938                 if (tp->link_config.speed == SPEED_1000) {
2939                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2940
2941                         if (tp->link_config.duplex == DUPLEX_FULL)
2942                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2943                         else
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2945                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2946                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2947                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2948                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2949                 } else {
2950                         if (tp->link_config.speed == SPEED_100) {
2951                                 if (tp->link_config.duplex == DUPLEX_FULL)
2952                                         new_adv |= ADVERTISE_100FULL;
2953                                 else
2954                                         new_adv |= ADVERTISE_100HALF;
2955                         } else {
2956                                 if (tp->link_config.duplex == DUPLEX_FULL)
2957                                         new_adv |= ADVERTISE_10FULL;
2958                                 else
2959                                         new_adv |= ADVERTISE_10HALF;
2960                         }
2961                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2962
2963                         new_adv = 0;
2964                 }
2965
2966                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2967         }
2968
2969         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2970                 u32 val = 0;
2971
2972                 tw32(TG3_CPMU_EEE_MODE,
2973                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2974
2975                 /* Enable SM_DSP clock and tx 6dB coding. */
2976                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2977                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2978                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2980
2981                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2982                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2983                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2984                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2985                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2986
2987                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2988                         /* Advertise 100-BaseTX EEE ability */
2989                         if (tp->link_config.advertising &
2990                             (ADVERTISED_100baseT_Half |
2991                              ADVERTISED_100baseT_Full))
2992                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2993                         /* Advertise 1000-BaseT EEE ability */
2994                         if (tp->link_config.advertising &
2995                             (ADVERTISED_1000baseT_Half |
2996                              ADVERTISED_1000baseT_Full))
2997                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
2998                 }
2999                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3000
3001                 /* Turn off SM_DSP clock. */
3002                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3003                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3004                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3005         }
3006
3007         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3008             tp->link_config.speed != SPEED_INVALID) {
3009                 u32 bmcr, orig_bmcr;
3010
3011                 tp->link_config.active_speed = tp->link_config.speed;
3012                 tp->link_config.active_duplex = tp->link_config.duplex;
3013
3014                 bmcr = 0;
3015                 switch (tp->link_config.speed) {
3016                 default:
3017                 case SPEED_10:
3018                         break;
3019
3020                 case SPEED_100:
3021                         bmcr |= BMCR_SPEED100;
3022                         break;
3023
3024                 case SPEED_1000:
3025                         bmcr |= TG3_BMCR_SPEED1000;
3026                         break;
3027                 }
3028
3029                 if (tp->link_config.duplex == DUPLEX_FULL)
3030                         bmcr |= BMCR_FULLDPLX;
3031
3032                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3033                     (bmcr != orig_bmcr)) {
3034                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3035                         for (i = 0; i < 1500; i++) {
3036                                 u32 tmp;
3037
3038                                 udelay(10);
3039                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3040                                     tg3_readphy(tp, MII_BMSR, &tmp))
3041                                         continue;
3042                                 if (!(tmp & BMSR_LSTATUS)) {
3043                                         udelay(40);
3044                                         break;
3045                                 }
3046                         }
3047                         tg3_writephy(tp, MII_BMCR, bmcr);
3048                         udelay(40);
3049                 }
3050         } else {
3051                 tg3_writephy(tp, MII_BMCR,
3052                              BMCR_ANENABLE | BMCR_ANRESTART);
3053         }
3054 }
3055
3056 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3057 {
3058         int err;
3059
3060         /* Turn off tap power management. */
3061         /* Set Extended packet length bit */
3062         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3063
3064         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3065         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3066         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3067         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3068         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3069
3070         udelay(40);
3071
3072         return err;
3073 }
3074
3075 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3076 {
3077         u32 adv_reg, all_mask = 0;
3078
3079         if (mask & ADVERTISED_10baseT_Half)
3080                 all_mask |= ADVERTISE_10HALF;
3081         if (mask & ADVERTISED_10baseT_Full)
3082                 all_mask |= ADVERTISE_10FULL;
3083         if (mask & ADVERTISED_100baseT_Half)
3084                 all_mask |= ADVERTISE_100HALF;
3085         if (mask & ADVERTISED_100baseT_Full)
3086                 all_mask |= ADVERTISE_100FULL;
3087
3088         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3089                 return 0;
3090
3091         if ((adv_reg & all_mask) != all_mask)
3092                 return 0;
3093         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3094                 u32 tg3_ctrl;
3095
3096                 all_mask = 0;
3097                 if (mask & ADVERTISED_1000baseT_Half)
3098                         all_mask |= ADVERTISE_1000HALF;
3099                 if (mask & ADVERTISED_1000baseT_Full)
3100                         all_mask |= ADVERTISE_1000FULL;
3101
3102                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3103                         return 0;
3104
3105                 if ((tg3_ctrl & all_mask) != all_mask)
3106                         return 0;
3107         }
3108         return 1;
3109 }
3110
3111 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3112 {
3113         u32 curadv, reqadv;
3114
3115         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3116                 return 1;
3117
3118         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3119         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3120
3121         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3122                 if (curadv != reqadv)
3123                         return 0;
3124
3125                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3126                         tg3_readphy(tp, MII_LPA, rmtadv);
3127         } else {
3128                 /* Reprogram the advertisement register, even if it
3129                  * does not affect the current link.  If the link
3130                  * gets renegotiated in the future, we can save an
3131                  * additional renegotiation cycle by advertising
3132                  * it correctly in the first place.
3133                  */
3134                 if (curadv != reqadv) {
3135                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3136                                      ADVERTISE_PAUSE_ASYM);
3137                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3138                 }
3139         }
3140
3141         return 1;
3142 }
3143
3144 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3145 {
3146         int current_link_up;
3147         u32 bmsr, val;
3148         u32 lcl_adv, rmt_adv;
3149         u16 current_speed;
3150         u8 current_duplex;
3151         int i, err;
3152
3153         tw32(MAC_EVENT, 0);
3154
3155         tw32_f(MAC_STATUS,
3156              (MAC_STATUS_SYNC_CHANGED |
3157               MAC_STATUS_CFG_CHANGED |
3158               MAC_STATUS_MI_COMPLETION |
3159               MAC_STATUS_LNKSTATE_CHANGED));
3160         udelay(40);
3161
3162         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3163                 tw32_f(MAC_MI_MODE,
3164                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3165                 udelay(80);
3166         }
3167
3168         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3169
3170         /* Some third-party PHYs need to be reset on link going
3171          * down.
3172          */
3173         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3174              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3175              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3176             netif_carrier_ok(tp->dev)) {
3177                 tg3_readphy(tp, MII_BMSR, &bmsr);
3178                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3179                     !(bmsr & BMSR_LSTATUS))
3180                         force_reset = 1;
3181         }
3182         if (force_reset)
3183                 tg3_phy_reset(tp);
3184
3185         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3186                 tg3_readphy(tp, MII_BMSR, &bmsr);
3187                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3188                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3189                         bmsr = 0;
3190
3191                 if (!(bmsr & BMSR_LSTATUS)) {
3192                         err = tg3_init_5401phy_dsp(tp);
3193                         if (err)
3194                                 return err;
3195
3196                         tg3_readphy(tp, MII_BMSR, &bmsr);
3197                         for (i = 0; i < 1000; i++) {
3198                                 udelay(10);
3199                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3200                                     (bmsr & BMSR_LSTATUS)) {
3201                                         udelay(40);
3202                                         break;
3203                                 }
3204                         }
3205
3206                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3207                             TG3_PHY_REV_BCM5401_B0 &&
3208                             !(bmsr & BMSR_LSTATUS) &&
3209                             tp->link_config.active_speed == SPEED_1000) {
3210                                 err = tg3_phy_reset(tp);
3211                                 if (!err)
3212                                         err = tg3_init_5401phy_dsp(tp);
3213                                 if (err)
3214                                         return err;
3215                         }
3216                 }
3217         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3218                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3219                 /* 5701 {A0,B0} CRC bug workaround */
3220                 tg3_writephy(tp, 0x15, 0x0a75);
3221                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3222                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224         }
3225
3226         /* Clear pending interrupts... */
3227         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3228         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3229
3230         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3231                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3232         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3234
3235         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3236             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3237                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3238                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3239                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3240                 else
3241                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3242         }
3243
3244         current_link_up = 0;
3245         current_speed = SPEED_INVALID;
3246         current_duplex = DUPLEX_INVALID;
3247
3248         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3249                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3250                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3251                 if (!(val & (1 << 10))) {
3252                         val |= (1 << 10);
3253                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3254                         goto relink;
3255                 }
3256         }
3257
3258         bmsr = 0;
3259         for (i = 0; i < 100; i++) {
3260                 tg3_readphy(tp, MII_BMSR, &bmsr);
3261                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3262                     (bmsr & BMSR_LSTATUS))
3263                         break;
3264                 udelay(40);
3265         }
3266
3267         if (bmsr & BMSR_LSTATUS) {
3268                 u32 aux_stat, bmcr;
3269
3270                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3271                 for (i = 0; i < 2000; i++) {
3272                         udelay(10);
3273                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3274                             aux_stat)
3275                                 break;
3276                 }
3277
3278                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3279                                              &current_speed,
3280                                              &current_duplex);
3281
3282                 bmcr = 0;
3283                 for (i = 0; i < 200; i++) {
3284                         tg3_readphy(tp, MII_BMCR, &bmcr);
3285                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3286                                 continue;
3287                         if (bmcr && bmcr != 0x7fff)
3288                                 break;
3289                         udelay(10);
3290                 }
3291
3292                 lcl_adv = 0;
3293                 rmt_adv = 0;
3294
3295                 tp->link_config.active_speed = current_speed;
3296                 tp->link_config.active_duplex = current_duplex;
3297
3298                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3299                         if ((bmcr & BMCR_ANENABLE) &&
3300                             tg3_copper_is_advertising_all(tp,
3301                                                 tp->link_config.advertising)) {
3302                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3303                                                                   &rmt_adv))
3304                                         current_link_up = 1;
3305                         }
3306                 } else {
3307                         if (!(bmcr & BMCR_ANENABLE) &&
3308                             tp->link_config.speed == current_speed &&
3309                             tp->link_config.duplex == current_duplex &&
3310                             tp->link_config.flowctrl ==
3311                             tp->link_config.active_flowctrl) {
3312                                 current_link_up = 1;
3313                         }
3314                 }
3315
3316                 if (current_link_up == 1 &&
3317                     tp->link_config.active_duplex == DUPLEX_FULL)
3318                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3319         }
3320
3321 relink:
3322         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3323                 tg3_phy_copper_begin(tp);
3324
3325                 tg3_readphy(tp, MII_BMSR, &bmsr);
3326                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3327                     (bmsr & BMSR_LSTATUS))
3328                         current_link_up = 1;
3329         }
3330
3331         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3332         if (current_link_up == 1) {
3333                 if (tp->link_config.active_speed == SPEED_100 ||
3334                     tp->link_config.active_speed == SPEED_10)
3335                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3336                 else
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3338         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3339                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3340         else
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3342
3343         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3344         if (tp->link_config.active_duplex == DUPLEX_HALF)
3345                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3346
3347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3348                 if (current_link_up == 1 &&
3349                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3350                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3351                 else
3352                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3353         }
3354
3355         /* ??? Without this setting Netgear GA302T PHY does not
3356          * ??? send/receive packets...
3357          */
3358         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3359             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3360                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3361                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3362                 udelay(80);
3363         }
3364
3365         tw32_f(MAC_MODE, tp->mac_mode);
3366         udelay(40);
3367
3368         tg3_phy_eee_adjust(tp, current_link_up);
3369
3370         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3371                 /* Polled via timer. */
3372                 tw32_f(MAC_EVENT, 0);
3373         } else {
3374                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3375         }
3376         udelay(40);
3377
3378         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3379             current_link_up == 1 &&
3380             tp->link_config.active_speed == SPEED_1000 &&
3381             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3382              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3383                 udelay(120);
3384                 tw32_f(MAC_STATUS,
3385                      (MAC_STATUS_SYNC_CHANGED |
3386                       MAC_STATUS_CFG_CHANGED));
3387                 udelay(40);
3388                 tg3_write_mem(tp,
3389                               NIC_SRAM_FIRMWARE_MBOX,
3390                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3391         }
3392
3393         /* Prevent send BD corruption. */
3394         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3395                 u16 oldlnkctl, newlnkctl;
3396
3397                 pci_read_config_word(tp->pdev,
3398                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3399                                      &oldlnkctl);
3400                 if (tp->link_config.active_speed == SPEED_100 ||
3401                     tp->link_config.active_speed == SPEED_10)
3402                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3403                 else
3404                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 if (newlnkctl != oldlnkctl)
3406                         pci_write_config_word(tp->pdev,
3407                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3408                                               newlnkctl);
3409         }
3410
3411         if (current_link_up != netif_carrier_ok(tp->dev)) {
3412                 if (current_link_up)
3413                         netif_carrier_on(tp->dev);
3414                 else
3415                         netif_carrier_off(tp->dev);
3416                 tg3_link_report(tp);
3417         }
3418
3419         return 0;
3420 }
3421
3422 struct tg3_fiber_aneginfo {
3423         int state;
3424 #define ANEG_STATE_UNKNOWN              0
3425 #define ANEG_STATE_AN_ENABLE            1
3426 #define ANEG_STATE_RESTART_INIT         2
3427 #define ANEG_STATE_RESTART              3
3428 #define ANEG_STATE_DISABLE_LINK_OK      4
3429 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3430 #define ANEG_STATE_ABILITY_DETECT       6
3431 #define ANEG_STATE_ACK_DETECT_INIT      7
3432 #define ANEG_STATE_ACK_DETECT           8
3433 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3434 #define ANEG_STATE_COMPLETE_ACK         10
3435 #define ANEG_STATE_IDLE_DETECT_INIT     11
3436 #define ANEG_STATE_IDLE_DETECT          12
3437 #define ANEG_STATE_LINK_OK              13
3438 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3439 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3440
3441         u32 flags;
3442 #define MR_AN_ENABLE            0x00000001
3443 #define MR_RESTART_AN           0x00000002
3444 #define MR_AN_COMPLETE          0x00000004
3445 #define MR_PAGE_RX              0x00000008
3446 #define MR_NP_LOADED            0x00000010
3447 #define MR_TOGGLE_TX            0x00000020
3448 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3449 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3450 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3451 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3452 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3453 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3454 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3455 #define MR_TOGGLE_RX            0x00002000
3456 #define MR_NP_RX                0x00004000
3457
3458 #define MR_LINK_OK              0x80000000
3459
3460         unsigned long link_time, cur_time;
3461
3462         u32 ability_match_cfg;
3463         int ability_match_count;
3464
3465         char ability_match, idle_match, ack_match;
3466
3467         u32 txconfig, rxconfig;
3468 #define ANEG_CFG_NP             0x00000080
3469 #define ANEG_CFG_ACK            0x00000040
3470 #define ANEG_CFG_RF2            0x00000020
3471 #define ANEG_CFG_RF1            0x00000010
3472 #define ANEG_CFG_PS2            0x00000001
3473 #define ANEG_CFG_PS1            0x00008000
3474 #define ANEG_CFG_HD             0x00004000
3475 #define ANEG_CFG_FD             0x00002000
3476 #define ANEG_CFG_INVAL          0x00001f06
3477
3478 };
3479 #define ANEG_OK         0
3480 #define ANEG_DONE       1
3481 #define ANEG_TIMER_ENAB 2
3482 #define ANEG_FAILED     -1
3483
3484 #define ANEG_STATE_SETTLE_TIME  10000
3485
3486 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3487                                    struct tg3_fiber_aneginfo *ap)
3488 {
3489         u16 flowctrl;
3490         unsigned long delta;
3491         u32 rx_cfg_reg;
3492         int ret;
3493
3494         if (ap->state == ANEG_STATE_UNKNOWN) {
3495                 ap->rxconfig = 0;
3496                 ap->link_time = 0;
3497                 ap->cur_time = 0;
3498                 ap->ability_match_cfg = 0;
3499                 ap->ability_match_count = 0;
3500                 ap->ability_match = 0;
3501                 ap->idle_match = 0;
3502                 ap->ack_match = 0;
3503         }
3504         ap->cur_time++;
3505
3506         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3507                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3508
3509                 if (rx_cfg_reg != ap->ability_match_cfg) {
3510                         ap->ability_match_cfg = rx_cfg_reg;
3511                         ap->ability_match = 0;
3512                         ap->ability_match_count = 0;
3513                 } else {
3514                         if (++ap->ability_match_count > 1) {
3515                                 ap->ability_match = 1;
3516                                 ap->ability_match_cfg = rx_cfg_reg;
3517                         }
3518                 }
3519                 if (rx_cfg_reg & ANEG_CFG_ACK)
3520                         ap->ack_match = 1;
3521                 else
3522                         ap->ack_match = 0;
3523
3524                 ap->idle_match = 0;
3525         } else {
3526                 ap->idle_match = 1;
3527                 ap->ability_match_cfg = 0;
3528                 ap->ability_match_count = 0;
3529                 ap->ability_match = 0;
3530                 ap->ack_match = 0;
3531
3532                 rx_cfg_reg = 0;
3533         }
3534
3535         ap->rxconfig = rx_cfg_reg;
3536         ret = ANEG_OK;
3537
3538         switch (ap->state) {
3539         case ANEG_STATE_UNKNOWN:
3540                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3541                         ap->state = ANEG_STATE_AN_ENABLE;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_AN_ENABLE:
3545                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3546                 if (ap->flags & MR_AN_ENABLE) {
3547                         ap->link_time = 0;
3548                         ap->cur_time = 0;
3549                         ap->ability_match_cfg = 0;
3550                         ap->ability_match_count = 0;
3551                         ap->ability_match = 0;
3552                         ap->idle_match = 0;
3553                         ap->ack_match = 0;
3554
3555                         ap->state = ANEG_STATE_RESTART_INIT;
3556                 } else {
3557                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3558                 }
3559                 break;
3560
3561         case ANEG_STATE_RESTART_INIT:
3562                 ap->link_time = ap->cur_time;
3563                 ap->flags &= ~(MR_NP_LOADED);
3564                 ap->txconfig = 0;
3565                 tw32(MAC_TX_AUTO_NEG, 0);
3566                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3567                 tw32_f(MAC_MODE, tp->mac_mode);
3568                 udelay(40);
3569
3570                 ret = ANEG_TIMER_ENAB;
3571                 ap->state = ANEG_STATE_RESTART;
3572
3573                 /* fallthru */
3574         case ANEG_STATE_RESTART:
3575                 delta = ap->cur_time - ap->link_time;
3576                 if (delta > ANEG_STATE_SETTLE_TIME)
3577                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3578                 else
3579                         ret = ANEG_TIMER_ENAB;
3580                 break;
3581
3582         case ANEG_STATE_DISABLE_LINK_OK:
3583                 ret = ANEG_DONE;
3584                 break;
3585
3586         case ANEG_STATE_ABILITY_DETECT_INIT:
3587                 ap->flags &= ~(MR_TOGGLE_TX);
3588                 ap->txconfig = ANEG_CFG_FD;
3589                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3590                 if (flowctrl & ADVERTISE_1000XPAUSE)
3591                         ap->txconfig |= ANEG_CFG_PS1;
3592                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3593                         ap->txconfig |= ANEG_CFG_PS2;
3594                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3595                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3596                 tw32_f(MAC_MODE, tp->mac_mode);
3597                 udelay(40);
3598
3599                 ap->state = ANEG_STATE_ABILITY_DETECT;
3600                 break;
3601
3602         case ANEG_STATE_ABILITY_DETECT:
3603                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3604                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3605                 break;
3606
3607         case ANEG_STATE_ACK_DETECT_INIT:
3608                 ap->txconfig |= ANEG_CFG_ACK;
3609                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3610                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3611                 tw32_f(MAC_MODE, tp->mac_mode);
3612                 udelay(40);
3613
3614                 ap->state = ANEG_STATE_ACK_DETECT;
3615
3616                 /* fallthru */
3617         case ANEG_STATE_ACK_DETECT:
3618                 if (ap->ack_match != 0) {
3619                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3620                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3621                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3622                         } else {
3623                                 ap->state = ANEG_STATE_AN_ENABLE;
3624                         }
3625                 } else if (ap->ability_match != 0 &&
3626                            ap->rxconfig == 0) {
3627                         ap->state = ANEG_STATE_AN_ENABLE;
3628                 }
3629                 break;
3630
3631         case ANEG_STATE_COMPLETE_ACK_INIT:
3632                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3633                         ret = ANEG_FAILED;
3634                         break;
3635                 }
3636                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3637                                MR_LP_ADV_HALF_DUPLEX |
3638                                MR_LP_ADV_SYM_PAUSE |
3639                                MR_LP_ADV_ASYM_PAUSE |
3640                                MR_LP_ADV_REMOTE_FAULT1 |
3641                                MR_LP_ADV_REMOTE_FAULT2 |
3642                                MR_LP_ADV_NEXT_PAGE |
3643                                MR_TOGGLE_RX |
3644                                MR_NP_RX);
3645                 if (ap->rxconfig & ANEG_CFG_FD)
3646                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3647                 if (ap->rxconfig & ANEG_CFG_HD)
3648                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_PS1)
3650                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3651                 if (ap->rxconfig & ANEG_CFG_PS2)
3652                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_RF1)
3654                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3655                 if (ap->rxconfig & ANEG_CFG_RF2)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3657                 if (ap->rxconfig & ANEG_CFG_NP)
3658                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3659
3660                 ap->link_time = ap->cur_time;
3661
3662                 ap->flags ^= (MR_TOGGLE_TX);
3663                 if (ap->rxconfig & 0x0008)
3664                         ap->flags |= MR_TOGGLE_RX;
3665                 if (ap->rxconfig & ANEG_CFG_NP)
3666                         ap->flags |= MR_NP_RX;
3667                 ap->flags |= MR_PAGE_RX;
3668
3669                 ap->state = ANEG_STATE_COMPLETE_ACK;
3670                 ret = ANEG_TIMER_ENAB;
3671                 break;
3672
3673         case ANEG_STATE_COMPLETE_ACK:
3674                 if (ap->ability_match != 0 &&
3675                     ap->rxconfig == 0) {
3676                         ap->state = ANEG_STATE_AN_ENABLE;
3677                         break;
3678                 }
3679                 delta = ap->cur_time - ap->link_time;
3680                 if (delta > ANEG_STATE_SETTLE_TIME) {
3681                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3682                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3683                         } else {
3684                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3685                                     !(ap->flags & MR_NP_RX)) {
3686                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3687                                 } else {
3688                                         ret = ANEG_FAILED;
3689                                 }
3690                         }
3691                 }
3692                 break;
3693
3694         case ANEG_STATE_IDLE_DETECT_INIT:
3695                 ap->link_time = ap->cur_time;
3696                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3697                 tw32_f(MAC_MODE, tp->mac_mode);
3698                 udelay(40);
3699
3700                 ap->state = ANEG_STATE_IDLE_DETECT;
3701                 ret = ANEG_TIMER_ENAB;
3702                 break;
3703
3704         case ANEG_STATE_IDLE_DETECT:
3705                 if (ap->ability_match != 0 &&
3706                     ap->rxconfig == 0) {
3707                         ap->state = ANEG_STATE_AN_ENABLE;
3708                         break;
3709                 }
3710                 delta = ap->cur_time - ap->link_time;
3711                 if (delta > ANEG_STATE_SETTLE_TIME) {
3712                         /* XXX another gem from the Broadcom driver :( */
3713                         ap->state = ANEG_STATE_LINK_OK;
3714                 }
3715                 break;
3716
3717         case ANEG_STATE_LINK_OK:
3718                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3719                 ret = ANEG_DONE;
3720                 break;
3721
3722         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3723                 /* ??? unimplemented */
3724                 break;
3725
3726         case ANEG_STATE_NEXT_PAGE_WAIT:
3727                 /* ??? unimplemented */
3728                 break;
3729
3730         default:
3731                 ret = ANEG_FAILED;
3732                 break;
3733         }
3734
3735         return ret;
3736 }
3737
3738 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3739 {
3740         int res = 0;
3741         struct tg3_fiber_aneginfo aninfo;
3742         int status = ANEG_FAILED;
3743         unsigned int tick;
3744         u32 tmp;
3745
3746         tw32_f(MAC_TX_AUTO_NEG, 0);
3747
3748         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3749         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3750         udelay(40);
3751
3752         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3753         udelay(40);
3754
3755         memset(&aninfo, 0, sizeof(aninfo));
3756         aninfo.flags |= MR_AN_ENABLE;
3757         aninfo.state = ANEG_STATE_UNKNOWN;
3758         aninfo.cur_time = 0;
3759         tick = 0;
3760         while (++tick < 195000) {
3761                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3762                 if (status == ANEG_DONE || status == ANEG_FAILED)
3763                         break;
3764
3765                 udelay(1);
3766         }
3767
3768         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3769         tw32_f(MAC_MODE, tp->mac_mode);
3770         udelay(40);
3771
3772         *txflags = aninfo.txconfig;
3773         *rxflags = aninfo.flags;
3774
3775         if (status == ANEG_DONE &&
3776             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3777                              MR_LP_ADV_FULL_DUPLEX)))
3778                 res = 1;
3779
3780         return res;
3781 }
3782
3783 static void tg3_init_bcm8002(struct tg3 *tp)
3784 {
3785         u32 mac_status = tr32(MAC_STATUS);
3786         int i;
3787
3788         /* Reset when initting first time or we have a link. */
3789         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3790             !(mac_status & MAC_STATUS_PCS_SYNCED))
3791                 return;
3792
3793         /* Set PLL lock range. */
3794         tg3_writephy(tp, 0x16, 0x8007);
3795
3796         /* SW reset */
3797         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3798
3799         /* Wait for reset to complete. */
3800         /* XXX schedule_timeout() ... */
3801         for (i = 0; i < 500; i++)
3802                 udelay(10);
3803
3804         /* Config mode; select PMA/Ch 1 regs. */
3805         tg3_writephy(tp, 0x10, 0x8411);
3806
3807         /* Enable auto-lock and comdet, select txclk for tx. */
3808         tg3_writephy(tp, 0x11, 0x0a10);
3809
3810         tg3_writephy(tp, 0x18, 0x00a0);
3811         tg3_writephy(tp, 0x16, 0x41ff);
3812
3813         /* Assert and deassert POR. */
3814         tg3_writephy(tp, 0x13, 0x0400);
3815         udelay(40);
3816         tg3_writephy(tp, 0x13, 0x0000);
3817
3818         tg3_writephy(tp, 0x11, 0x0a50);
3819         udelay(40);
3820         tg3_writephy(tp, 0x11, 0x0a10);
3821
3822         /* Wait for signal to stabilize */
3823         /* XXX schedule_timeout() ... */
3824         for (i = 0; i < 15000; i++)
3825                 udelay(10);
3826
3827         /* Deselect the channel register so we can read the PHYID
3828          * later.
3829          */
3830         tg3_writephy(tp, 0x10, 0x8011);
3831 }
3832
3833 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3834 {
3835         u16 flowctrl;
3836         u32 sg_dig_ctrl, sg_dig_status;
3837         u32 serdes_cfg, expected_sg_dig_ctrl;
3838         int workaround, port_a;
3839         int current_link_up;
3840
3841         serdes_cfg = 0;
3842         expected_sg_dig_ctrl = 0;
3843         workaround = 0;
3844         port_a = 1;
3845         current_link_up = 0;
3846
3847         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3848             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3849                 workaround = 1;
3850                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3851                         port_a = 0;
3852
3853                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3854                 /* preserve bits 20-23 for voltage regulator */
3855                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3856         }
3857
3858         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3859
3860         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3861                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3862                         if (workaround) {
3863                                 u32 val = serdes_cfg;
3864
3865                                 if (port_a)
3866                                         val |= 0xc010000;
3867                                 else
3868                                         val |= 0x4010000;
3869                                 tw32_f(MAC_SERDES_CFG, val);
3870                         }
3871
3872                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3873                 }
3874                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3875                         tg3_setup_flow_control(tp, 0, 0);
3876                         current_link_up = 1;
3877                 }
3878                 goto out;
3879         }
3880
3881         /* Want auto-negotiation.  */
3882         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3883
3884         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3885         if (flowctrl & ADVERTISE_1000XPAUSE)
3886                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3887         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3888                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3889
3890         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3891                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3892                     tp->serdes_counter &&
3893                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3894                                     MAC_STATUS_RCVD_CFG)) ==
3895                      MAC_STATUS_PCS_SYNCED)) {
3896                         tp->serdes_counter--;
3897                         current_link_up = 1;
3898                         goto out;
3899                 }
3900 restart_autoneg:
3901                 if (workaround)
3902                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3903                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3904                 udelay(5);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3906
3907                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3908                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3909         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3910                                  MAC_STATUS_SIGNAL_DET)) {
3911                 sg_dig_status = tr32(SG_DIG_STATUS);
3912                 mac_status = tr32(MAC_STATUS);
3913
3914                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3915                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3916                         u32 local_adv = 0, remote_adv = 0;
3917
3918                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3919                                 local_adv |= ADVERTISE_1000XPAUSE;
3920                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3921                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3922
3923                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3924                                 remote_adv |= LPA_1000XPAUSE;
3925                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3926                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3927
3928                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3929                         current_link_up = 1;
3930                         tp->serdes_counter = 0;
3931                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3932                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3933                         if (tp->serdes_counter)
3934                                 tp->serdes_counter--;
3935                         else {
3936                                 if (workaround) {
3937                                         u32 val = serdes_cfg;
3938
3939                                         if (port_a)
3940                                                 val |= 0xc010000;
3941                                         else
3942                                                 val |= 0x4010000;
3943
3944                                         tw32_f(MAC_SERDES_CFG, val);
3945                                 }
3946
3947                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3948                                 udelay(40);
3949
3950                                 /* Link parallel detection - link is up */
3951                                 /* only if we have PCS_SYNC and not */
3952                                 /* receiving config code words */
3953                                 mac_status = tr32(MAC_STATUS);
3954                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3955                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3956                                         tg3_setup_flow_control(tp, 0, 0);
3957                                         current_link_up = 1;
3958                                         tp->phy_flags |=
3959                                                 TG3_PHYFLG_PARALLEL_DETECT;
3960                                         tp->serdes_counter =
3961                                                 SERDES_PARALLEL_DET_TIMEOUT;
3962                                 } else
3963                                         goto restart_autoneg;
3964                         }
3965                 }
3966         } else {
3967                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3968                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3969         }
3970
3971 out:
3972         return current_link_up;
3973 }
3974
3975 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3976 {
3977         int current_link_up = 0;
3978
3979         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3980                 goto out;
3981
3982         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3983                 u32 txflags, rxflags;
3984                 int i;
3985
3986                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3987                         u32 local_adv = 0, remote_adv = 0;
3988
3989                         if (txflags & ANEG_CFG_PS1)
3990                                 local_adv |= ADVERTISE_1000XPAUSE;
3991                         if (txflags & ANEG_CFG_PS2)
3992                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3993
3994                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3995                                 remote_adv |= LPA_1000XPAUSE;
3996                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3998
3999                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4000
4001                         current_link_up = 1;
4002                 }
4003                 for (i = 0; i < 30; i++) {
4004                         udelay(20);
4005                         tw32_f(MAC_STATUS,
4006                                (MAC_STATUS_SYNC_CHANGED |
4007                                 MAC_STATUS_CFG_CHANGED));
4008                         udelay(40);
4009                         if ((tr32(MAC_STATUS) &
4010                              (MAC_STATUS_SYNC_CHANGED |
4011                               MAC_STATUS_CFG_CHANGED)) == 0)
4012                                 break;
4013                 }
4014
4015                 mac_status = tr32(MAC_STATUS);
4016                 if (current_link_up == 0 &&
4017                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4018                     !(mac_status & MAC_STATUS_RCVD_CFG))
4019                         current_link_up = 1;
4020         } else {
4021                 tg3_setup_flow_control(tp, 0, 0);
4022
4023                 /* Forcing 1000FD link up. */
4024                 current_link_up = 1;
4025
4026                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4027                 udelay(40);
4028
4029                 tw32_f(MAC_MODE, tp->mac_mode);
4030                 udelay(40);
4031         }
4032
4033 out:
4034         return current_link_up;
4035 }
4036
4037 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4038 {
4039         u32 orig_pause_cfg;
4040         u16 orig_active_speed;
4041         u8 orig_active_duplex;
4042         u32 mac_status;
4043         int current_link_up;
4044         int i;
4045
4046         orig_pause_cfg = tp->link_config.active_flowctrl;
4047         orig_active_speed = tp->link_config.active_speed;
4048         orig_active_duplex = tp->link_config.active_duplex;
4049
4050         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4051             netif_carrier_ok(tp->dev) &&
4052             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4053                 mac_status = tr32(MAC_STATUS);
4054                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4055                                MAC_STATUS_SIGNAL_DET |
4056                                MAC_STATUS_CFG_CHANGED |
4057                                MAC_STATUS_RCVD_CFG);
4058                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4059                                    MAC_STATUS_SIGNAL_DET)) {
4060                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4061                                             MAC_STATUS_CFG_CHANGED));
4062                         return 0;
4063                 }
4064         }
4065
4066         tw32_f(MAC_TX_AUTO_NEG, 0);
4067
4068         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4069         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4070         tw32_f(MAC_MODE, tp->mac_mode);
4071         udelay(40);
4072
4073         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4074                 tg3_init_bcm8002(tp);
4075
4076         /* Enable link change event even when serdes polling.  */
4077         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4078         udelay(40);
4079
4080         current_link_up = 0;
4081         mac_status = tr32(MAC_STATUS);
4082
4083         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4084                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4085         else
4086                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4087
4088         tp->napi[0].hw_status->status =
4089                 (SD_STATUS_UPDATED |
4090                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4091
4092         for (i = 0; i < 100; i++) {
4093                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4094                                     MAC_STATUS_CFG_CHANGED));
4095                 udelay(5);
4096                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4097                                          MAC_STATUS_CFG_CHANGED |
4098                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4099                         break;
4100         }
4101
4102         mac_status = tr32(MAC_STATUS);
4103         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4104                 current_link_up = 0;
4105                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4106                     tp->serdes_counter == 0) {
4107                         tw32_f(MAC_MODE, (tp->mac_mode |
4108                                           MAC_MODE_SEND_CONFIGS));
4109                         udelay(1);
4110                         tw32_f(MAC_MODE, tp->mac_mode);
4111                 }
4112         }
4113
4114         if (current_link_up == 1) {
4115                 tp->link_config.active_speed = SPEED_1000;
4116                 tp->link_config.active_duplex = DUPLEX_FULL;
4117                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4118                                     LED_CTRL_LNKLED_OVERRIDE |
4119                                     LED_CTRL_1000MBPS_ON));
4120         } else {
4121                 tp->link_config.active_speed = SPEED_INVALID;
4122                 tp->link_config.active_duplex = DUPLEX_INVALID;
4123                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4124                                     LED_CTRL_LNKLED_OVERRIDE |
4125                                     LED_CTRL_TRAFFIC_OVERRIDE));
4126         }
4127
4128         if (current_link_up != netif_carrier_ok(tp->dev)) {
4129                 if (current_link_up)
4130                         netif_carrier_on(tp->dev);
4131                 else
4132                         netif_carrier_off(tp->dev);
4133                 tg3_link_report(tp);
4134         } else {
4135                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4136                 if (orig_pause_cfg != now_pause_cfg ||
4137                     orig_active_speed != tp->link_config.active_speed ||
4138                     orig_active_duplex != tp->link_config.active_duplex)
4139                         tg3_link_report(tp);
4140         }
4141
4142         return 0;
4143 }
4144
4145 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4146 {
4147         int current_link_up, err = 0;
4148         u32 bmsr, bmcr;
4149         u16 current_speed;
4150         u8 current_duplex;
4151         u32 local_adv, remote_adv;
4152
4153         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4154         tw32_f(MAC_MODE, tp->mac_mode);
4155         udelay(40);
4156
4157         tw32(MAC_EVENT, 0);
4158
4159         tw32_f(MAC_STATUS,
4160              (MAC_STATUS_SYNC_CHANGED |
4161               MAC_STATUS_CFG_CHANGED |
4162               MAC_STATUS_MI_COMPLETION |
4163               MAC_STATUS_LNKSTATE_CHANGED));
4164         udelay(40);
4165
4166         if (force_reset)
4167                 tg3_phy_reset(tp);
4168
4169         current_link_up = 0;
4170         current_speed = SPEED_INVALID;
4171         current_duplex = DUPLEX_INVALID;
4172
4173         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4176                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4177                         bmsr |= BMSR_LSTATUS;
4178                 else
4179                         bmsr &= ~BMSR_LSTATUS;
4180         }
4181
4182         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4183
4184         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4185             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4186                 /* do nothing, just check for link up at the end */
4187         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4188                 u32 adv, new_adv;
4189
4190                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4191                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4192                                   ADVERTISE_1000XPAUSE |
4193                                   ADVERTISE_1000XPSE_ASYM |
4194                                   ADVERTISE_SLCT);
4195
4196                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4197
4198                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4199                         new_adv |= ADVERTISE_1000XHALF;
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4201                         new_adv |= ADVERTISE_1000XFULL;
4202
4203                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4204                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4205                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4206                         tg3_writephy(tp, MII_BMCR, bmcr);
4207
4208                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4209                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4210                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4211
4212                         return err;
4213                 }
4214         } else {
4215                 u32 new_bmcr;
4216
4217                 bmcr &= ~BMCR_SPEED1000;
4218                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4219
4220                 if (tp->link_config.duplex == DUPLEX_FULL)
4221                         new_bmcr |= BMCR_FULLDPLX;
4222
4223                 if (new_bmcr != bmcr) {
4224                         /* BMCR_SPEED1000 is a reserved bit that needs
4225                          * to be set on write.
4226                          */
4227                         new_bmcr |= BMCR_SPEED1000;
4228
4229                         /* Force a linkdown */
4230                         if (netif_carrier_ok(tp->dev)) {
4231                                 u32 adv;
4232
4233                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4234                                 adv &= ~(ADVERTISE_1000XFULL |
4235                                          ADVERTISE_1000XHALF |
4236                                          ADVERTISE_SLCT);
4237                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4238                                 tg3_writephy(tp, MII_BMCR, bmcr |
4239                                                            BMCR_ANRESTART |
4240                                                            BMCR_ANENABLE);
4241                                 udelay(10);
4242                                 netif_carrier_off(tp->dev);
4243                         }
4244                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4245                         bmcr = new_bmcr;
4246                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4247                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4248                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4249                             ASIC_REV_5714) {
4250                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4251                                         bmsr |= BMSR_LSTATUS;
4252                                 else
4253                                         bmsr &= ~BMSR_LSTATUS;
4254                         }
4255                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4256                 }
4257         }
4258
4259         if (bmsr & BMSR_LSTATUS) {
4260                 current_speed = SPEED_1000;
4261                 current_link_up = 1;
4262                 if (bmcr & BMCR_FULLDPLX)
4263                         current_duplex = DUPLEX_FULL;
4264                 else
4265                         current_duplex = DUPLEX_HALF;
4266
4267                 local_adv = 0;
4268                 remote_adv = 0;
4269
4270                 if (bmcr & BMCR_ANENABLE) {
4271                         u32 common;
4272
4273                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4274                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4275                         common = local_adv & remote_adv;
4276                         if (common & (ADVERTISE_1000XHALF |
4277                                       ADVERTISE_1000XFULL)) {
4278                                 if (common & ADVERTISE_1000XFULL)
4279                                         current_duplex = DUPLEX_FULL;
4280                                 else
4281                                         current_duplex = DUPLEX_HALF;
4282                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4283                                 /* Link is up via parallel detect */
4284                         } else {
4285                                 current_link_up = 0;
4286                         }
4287                 }
4288         }
4289
4290         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4291                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4292
4293         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4294         if (tp->link_config.active_duplex == DUPLEX_HALF)
4295                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4296
4297         tw32_f(MAC_MODE, tp->mac_mode);
4298         udelay(40);
4299
4300         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4301
4302         tp->link_config.active_speed = current_speed;
4303         tp->link_config.active_duplex = current_duplex;
4304
4305         if (current_link_up != netif_carrier_ok(tp->dev)) {
4306                 if (current_link_up)
4307                         netif_carrier_on(tp->dev);
4308                 else {
4309                         netif_carrier_off(tp->dev);
4310                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4311                 }
4312                 tg3_link_report(tp);
4313         }
4314         return err;
4315 }
4316
4317 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4318 {
4319         if (tp->serdes_counter) {
4320                 /* Give autoneg time to complete. */
4321                 tp->serdes_counter--;
4322                 return;
4323         }
4324
4325         if (!netif_carrier_ok(tp->dev) &&
4326             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4327                 u32 bmcr;
4328
4329                 tg3_readphy(tp, MII_BMCR, &bmcr);
4330                 if (bmcr & BMCR_ANENABLE) {
4331                         u32 phy1, phy2;
4332
4333                         /* Select shadow register 0x1f */
4334                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4335                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4336
4337                         /* Select expansion interrupt status register */
4338                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4339                                          MII_TG3_DSP_EXP1_INT_STAT);
4340                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4341                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4342
4343                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4344                                 /* We have signal detect and not receiving
4345                                  * config code words, link is up by parallel
4346                                  * detection.
4347                                  */
4348
4349                                 bmcr &= ~BMCR_ANENABLE;
4350                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4351                                 tg3_writephy(tp, MII_BMCR, bmcr);
4352                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4353                         }
4354                 }
4355         } else if (netif_carrier_ok(tp->dev) &&
4356                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4357                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4358                 u32 phy2;
4359
4360                 /* Select expansion interrupt status register */
4361                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4362                                  MII_TG3_DSP_EXP1_INT_STAT);
4363                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4364                 if (phy2 & 0x20) {
4365                         u32 bmcr;
4366
4367                         /* Config code words received, turn on autoneg. */
4368                         tg3_readphy(tp, MII_BMCR, &bmcr);
4369                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4370
4371                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4372
4373                 }
4374         }
4375 }
4376
4377 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4378 {
4379         int err;
4380
4381         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4382                 err = tg3_setup_fiber_phy(tp, force_reset);
4383         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4384                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4385         else
4386                 err = tg3_setup_copper_phy(tp, force_reset);
4387
4388         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4389                 u32 val, scale;
4390
4391                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4392                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4393                         scale = 65;
4394                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4395                         scale = 6;
4396                 else
4397                         scale = 12;
4398
4399                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4400                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4401                 tw32(GRC_MISC_CFG, val);
4402         }
4403
4404         if (tp->link_config.active_speed == SPEED_1000 &&
4405             tp->link_config.active_duplex == DUPLEX_HALF)
4406                 tw32(MAC_TX_LENGTHS,
4407                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4408                       (6 << TX_LENGTHS_IPG_SHIFT) |
4409                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4410         else
4411                 tw32(MAC_TX_LENGTHS,
4412                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4413                       (6 << TX_LENGTHS_IPG_SHIFT) |
4414                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4415
4416         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4417                 if (netif_carrier_ok(tp->dev)) {
4418                         tw32(HOSTCC_STAT_COAL_TICKS,
4419                              tp->coal.stats_block_coalesce_usecs);
4420                 } else {
4421                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4422                 }
4423         }
4424
4425         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4426                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4427                 if (!netif_carrier_ok(tp->dev))
4428                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4429                               tp->pwrmgmt_thresh;
4430                 else
4431                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4432                 tw32(PCIE_PWR_MGMT_THRESH, val);
4433         }
4434
4435         return err;
4436 }
4437
4438 static inline int tg3_irq_sync(struct tg3 *tp)
4439 {
4440         return tp->irq_sync;
4441 }
4442
4443 /* This is called whenever we suspect that the system chipset is re-
4444  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4445  * is bogus tx completions. We try to recover by setting the
4446  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4447  * in the workqueue.
4448  */
4449 static void tg3_tx_recover(struct tg3 *tp)
4450 {
4451         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4452                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4453
4454         netdev_warn(tp->dev,
4455                     "The system may be re-ordering memory-mapped I/O "
4456                     "cycles to the network device, attempting to recover. "
4457                     "Please report the problem to the driver maintainer "
4458                     "and include system chipset information.\n");
4459
4460         spin_lock(&tp->lock);
4461         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4462         spin_unlock(&tp->lock);
4463 }
4464
4465 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4466 {
4467         /* Tell compiler to fetch tx indices from memory. */
4468         barrier();
4469         return tnapi->tx_pending -
4470                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4471 }
4472
4473 /* Tigon3 never reports partial packet sends.  So we do not
4474  * need special logic to handle SKBs that have not had all
4475  * of their frags sent yet, like SunGEM does.
4476  */
4477 static void tg3_tx(struct tg3_napi *tnapi)
4478 {
4479         struct tg3 *tp = tnapi->tp;
4480         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4481         u32 sw_idx = tnapi->tx_cons;
4482         struct netdev_queue *txq;
4483         int index = tnapi - tp->napi;
4484
4485         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4486                 index--;
4487
4488         txq = netdev_get_tx_queue(tp->dev, index);
4489
4490         while (sw_idx != hw_idx) {
4491                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4492                 struct sk_buff *skb = ri->skb;
4493                 int i, tx_bug = 0;
4494
4495                 if (unlikely(skb == NULL)) {
4496                         tg3_tx_recover(tp);
4497                         return;
4498                 }
4499
4500                 pci_unmap_single(tp->pdev,
4501                                  dma_unmap_addr(ri, mapping),
4502                                  skb_headlen(skb),
4503                                  PCI_DMA_TODEVICE);
4504
4505                 ri->skb = NULL;
4506
4507                 sw_idx = NEXT_TX(sw_idx);
4508
4509                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4510                         ri = &tnapi->tx_buffers[sw_idx];
4511                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4512                                 tx_bug = 1;
4513
4514                         pci_unmap_page(tp->pdev,
4515                                        dma_unmap_addr(ri, mapping),
4516                                        skb_shinfo(skb)->frags[i].size,
4517                                        PCI_DMA_TODEVICE);
4518                         sw_idx = NEXT_TX(sw_idx);
4519                 }
4520
4521                 dev_kfree_skb(skb);
4522
4523                 if (unlikely(tx_bug)) {
4524                         tg3_tx_recover(tp);
4525                         return;
4526                 }
4527         }
4528
4529         tnapi->tx_cons = sw_idx;
4530
4531         /* Need to make the tx_cons update visible to tg3_start_xmit()
4532          * before checking for netif_queue_stopped().  Without the
4533          * memory barrier, there is a small possibility that tg3_start_xmit()
4534          * will miss it and cause the queue to be stopped forever.
4535          */
4536         smp_mb();
4537
4538         if (unlikely(netif_tx_queue_stopped(txq) &&
4539                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4540                 __netif_tx_lock(txq, smp_processor_id());
4541                 if (netif_tx_queue_stopped(txq) &&
4542                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4543                         netif_tx_wake_queue(txq);
4544                 __netif_tx_unlock(txq);
4545         }
4546 }
4547
4548 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4549 {
4550         if (!ri->skb)
4551                 return;
4552
4553         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4554                          map_sz, PCI_DMA_FROMDEVICE);
4555         dev_kfree_skb_any(ri->skb);
4556         ri->skb = NULL;
4557 }
4558
4559 /* Returns size of skb allocated or < 0 on error.
4560  *
4561  * We only need to fill in the address because the other members
4562  * of the RX descriptor are invariant, see tg3_init_rings.
4563  *
4564  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4565  * posting buffers we only dirty the first cache line of the RX
4566  * descriptor (containing the address).  Whereas for the RX status
4567  * buffers the cpu only reads the last cacheline of the RX descriptor
4568  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4569  */
4570 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4571                             u32 opaque_key, u32 dest_idx_unmasked)
4572 {
4573         struct tg3_rx_buffer_desc *desc;
4574         struct ring_info *map;
4575         struct sk_buff *skb;
4576         dma_addr_t mapping;
4577         int skb_size, dest_idx;
4578
4579         switch (opaque_key) {
4580         case RXD_OPAQUE_RING_STD:
4581                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4582                 desc = &tpr->rx_std[dest_idx];
4583                 map = &tpr->rx_std_buffers[dest_idx];
4584                 skb_size = tp->rx_pkt_map_sz;
4585                 break;
4586
4587         case RXD_OPAQUE_RING_JUMBO:
4588                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4589                 desc = &tpr->rx_jmb[dest_idx].std;
4590                 map = &tpr->rx_jmb_buffers[dest_idx];
4591                 skb_size = TG3_RX_JMB_MAP_SZ;
4592                 break;
4593
4594         default:
4595                 return -EINVAL;
4596         }
4597
4598         /* Do not overwrite any of the map or rp information
4599          * until we are sure we can commit to a new buffer.
4600          *
4601          * Callers depend upon this behavior and assume that
4602          * we leave everything unchanged if we fail.
4603          */
4604         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4605         if (skb == NULL)
4606                 return -ENOMEM;
4607
4608         skb_reserve(skb, tp->rx_offset);
4609
4610         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4611                                  PCI_DMA_FROMDEVICE);
4612         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4613                 dev_kfree_skb(skb);
4614                 return -EIO;
4615         }
4616
4617         map->skb = skb;
4618         dma_unmap_addr_set(map, mapping, mapping);
4619
4620         desc->addr_hi = ((u64)mapping >> 32);
4621         desc->addr_lo = ((u64)mapping & 0xffffffff);
4622
4623         return skb_size;
4624 }
4625
4626 /* We only need to move over in the address because the other
4627  * members of the RX descriptor are invariant.  See notes above
4628  * tg3_alloc_rx_skb for full details.
4629  */
4630 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4631                            struct tg3_rx_prodring_set *dpr,
4632                            u32 opaque_key, int src_idx,
4633                            u32 dest_idx_unmasked)
4634 {
4635         struct tg3 *tp = tnapi->tp;
4636         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4637         struct ring_info *src_map, *dest_map;
4638         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4639         int dest_idx;
4640
4641         switch (opaque_key) {
4642         case RXD_OPAQUE_RING_STD:
4643                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4644                 dest_desc = &dpr->rx_std[dest_idx];
4645                 dest_map = &dpr->rx_std_buffers[dest_idx];
4646                 src_desc = &spr->rx_std[src_idx];
4647                 src_map = &spr->rx_std_buffers[src_idx];
4648                 break;
4649
4650         case RXD_OPAQUE_RING_JUMBO:
4651                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4652                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4653                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4654                 src_desc = &spr->rx_jmb[src_idx].std;
4655                 src_map = &spr->rx_jmb_buffers[src_idx];
4656                 break;
4657
4658         default:
4659                 return;
4660         }
4661
4662         dest_map->skb = src_map->skb;
4663         dma_unmap_addr_set(dest_map, mapping,
4664                            dma_unmap_addr(src_map, mapping));
4665         dest_desc->addr_hi = src_desc->addr_hi;
4666         dest_desc->addr_lo = src_desc->addr_lo;
4667
4668         /* Ensure that the update to the skb happens after the physical
4669          * addresses have been transferred to the new BD location.
4670          */
4671         smp_wmb();
4672
4673         src_map->skb = NULL;
4674 }
4675
4676 /* The RX ring scheme is composed of multiple rings which post fresh
4677  * buffers to the chip, and one special ring the chip uses to report
4678  * status back to the host.
4679  *
4680  * The special ring reports the status of received packets to the
4681  * host.  The chip does not write into the original descriptor the
4682  * RX buffer was obtained from.  The chip simply takes the original
4683  * descriptor as provided by the host, updates the status and length
4684  * field, then writes this into the next status ring entry.
4685  *
4686  * Each ring the host uses to post buffers to the chip is described
4687  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4688  * it is first placed into the on-chip ram.  When the packet's length
4689  * is known, it walks down the TG3_BDINFO entries to select the ring.
4690  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4691  * which is within the range of the new packet's length is chosen.
4692  *
4693  * The "separate ring for rx status" scheme may sound queer, but it makes
4694  * sense from a cache coherency perspective.  If only the host writes
4695  * to the buffer post rings, and only the chip writes to the rx status
4696  * rings, then cache lines never move beyond shared-modified state.
4697  * If both the host and chip were to write into the same ring, cache line
4698  * eviction could occur since both entities want it in an exclusive state.
4699  */
4700 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4701 {
4702         struct tg3 *tp = tnapi->tp;
4703         u32 work_mask, rx_std_posted = 0;
4704         u32 std_prod_idx, jmb_prod_idx;
4705         u32 sw_idx = tnapi->rx_rcb_ptr;
4706         u16 hw_idx;
4707         int received;
4708         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4709
4710         hw_idx = *(tnapi->rx_rcb_prod_idx);
4711         /*
4712          * We need to order the read of hw_idx and the read of
4713          * the opaque cookie.
4714          */
4715         rmb();
4716         work_mask = 0;
4717         received = 0;
4718         std_prod_idx = tpr->rx_std_prod_idx;
4719         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4720         while (sw_idx != hw_idx && budget > 0) {
4721                 struct ring_info *ri;
4722                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4723                 unsigned int len;
4724                 struct sk_buff *skb;
4725                 dma_addr_t dma_addr;
4726                 u32 opaque_key, desc_idx, *post_ptr;
4727                 bool hw_vlan __maybe_unused = false;
4728                 u16 vtag __maybe_unused = 0;
4729
4730                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4731                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4732                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4733                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4734                         dma_addr = dma_unmap_addr(ri, mapping);
4735                         skb = ri->skb;
4736                         post_ptr = &std_prod_idx;
4737                         rx_std_posted++;
4738                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4739                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4740                         dma_addr = dma_unmap_addr(ri, mapping);
4741                         skb = ri->skb;
4742                         post_ptr = &jmb_prod_idx;
4743                 } else
4744                         goto next_pkt_nopost;
4745
4746                 work_mask |= opaque_key;
4747
4748                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4749                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4750                 drop_it:
4751                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4752                                        desc_idx, *post_ptr);
4753                 drop_it_no_recycle:
4754                         /* Other statistics kept track of by card. */
4755                         tp->rx_dropped++;
4756                         goto next_pkt;
4757                 }
4758
4759                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4760                       ETH_FCS_LEN;
4761
4762                 if (len > TG3_RX_COPY_THRESH(tp)) {
4763                         int skb_size;
4764
4765                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4766                                                     *post_ptr);
4767                         if (skb_size < 0)
4768                                 goto drop_it;
4769
4770                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4771                                          PCI_DMA_FROMDEVICE);
4772
4773                         /* Ensure that the update to the skb happens
4774                          * after the usage of the old DMA mapping.
4775                          */
4776                         smp_wmb();
4777
4778                         ri->skb = NULL;
4779
4780                         skb_put(skb, len);
4781                 } else {
4782                         struct sk_buff *copy_skb;
4783
4784                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4785                                        desc_idx, *post_ptr);
4786
4787                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4788                                                     TG3_RAW_IP_ALIGN);
4789                         if (copy_skb == NULL)
4790                                 goto drop_it_no_recycle;
4791
4792                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4793                         skb_put(copy_skb, len);
4794                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4795                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4796                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797
4798                         /* We'll reuse the original ring buffer. */
4799                         skb = copy_skb;
4800                 }
4801
4802                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4803                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4804                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4805                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4806                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4807                 else
4808                         skb_checksum_none_assert(skb);
4809
4810                 skb->protocol = eth_type_trans(skb, tp->dev);
4811
4812                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4813                     skb->protocol != htons(ETH_P_8021Q)) {
4814                         dev_kfree_skb(skb);
4815                         goto drop_it_no_recycle;
4816                 }
4817
4818                 if (desc->type_flags & RXD_FLAG_VLAN &&
4819                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4820                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4821 #if TG3_VLAN_TAG_USED
4822                         if (tp->vlgrp)
4823                                 hw_vlan = true;
4824                         else
4825 #endif
4826                         {
4827                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4828                                                     __skb_push(skb, VLAN_HLEN);
4829
4830                                 memmove(ve, skb->data + VLAN_HLEN,
4831                                         ETH_ALEN * 2);
4832                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4833                                 ve->h_vlan_TCI = htons(vtag);
4834                         }
4835                 }
4836
4837 #if TG3_VLAN_TAG_USED
4838                 if (hw_vlan)
4839                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4840                 else
4841 #endif
4842                         napi_gro_receive(&tnapi->napi, skb);
4843
4844                 received++;
4845                 budget--;
4846
4847 next_pkt:
4848                 (*post_ptr)++;
4849
4850                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4851                         tpr->rx_std_prod_idx = std_prod_idx &
4852                                                tp->rx_std_ring_mask;
4853                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4854                                      tpr->rx_std_prod_idx);
4855                         work_mask &= ~RXD_OPAQUE_RING_STD;
4856                         rx_std_posted = 0;
4857                 }
4858 next_pkt_nopost:
4859                 sw_idx++;
4860                 sw_idx &= tp->rx_ret_ring_mask;
4861
4862                 /* Refresh hw_idx to see if there is new work */
4863                 if (sw_idx == hw_idx) {
4864                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4865                         rmb();
4866                 }
4867         }
4868
4869         /* ACK the status ring. */
4870         tnapi->rx_rcb_ptr = sw_idx;
4871         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4872
4873         /* Refill RX ring(s). */
4874         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4875                 if (work_mask & RXD_OPAQUE_RING_STD) {
4876                         tpr->rx_std_prod_idx = std_prod_idx &
4877                                                tp->rx_std_ring_mask;
4878                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4879                                      tpr->rx_std_prod_idx);
4880                 }
4881                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4882                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4883                                                tp->rx_jmb_ring_mask;
4884                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4885                                      tpr->rx_jmb_prod_idx);
4886                 }
4887                 mmiowb();
4888         } else if (work_mask) {
4889                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4890                  * updated before the producer indices can be updated.
4891                  */
4892                 smp_wmb();
4893
4894                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4895                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4896
4897                 if (tnapi != &tp->napi[1])
4898                         napi_schedule(&tp->napi[1].napi);
4899         }
4900
4901         return received;
4902 }
4903
4904 static void tg3_poll_link(struct tg3 *tp)
4905 {
4906         /* handle link change and other phy events */
4907         if (!(tp->tg3_flags &
4908               (TG3_FLAG_USE_LINKCHG_REG |
4909                TG3_FLAG_POLL_SERDES))) {
4910                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4911
4912                 if (sblk->status & SD_STATUS_LINK_CHG) {
4913                         sblk->status = SD_STATUS_UPDATED |
4914                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4915                         spin_lock(&tp->lock);
4916                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4917                                 tw32_f(MAC_STATUS,
4918                                      (MAC_STATUS_SYNC_CHANGED |
4919                                       MAC_STATUS_CFG_CHANGED |
4920                                       MAC_STATUS_MI_COMPLETION |
4921                                       MAC_STATUS_LNKSTATE_CHANGED));
4922                                 udelay(40);
4923                         } else
4924                                 tg3_setup_phy(tp, 0);
4925                         spin_unlock(&tp->lock);
4926                 }
4927         }
4928 }
4929
4930 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4931                                 struct tg3_rx_prodring_set *dpr,
4932                                 struct tg3_rx_prodring_set *spr)
4933 {
4934         u32 si, di, cpycnt, src_prod_idx;
4935         int i, err = 0;
4936
4937         while (1) {
4938                 src_prod_idx = spr->rx_std_prod_idx;
4939
4940                 /* Make sure updates to the rx_std_buffers[] entries and the
4941                  * standard producer index are seen in the correct order.
4942                  */
4943                 smp_rmb();
4944
4945                 if (spr->rx_std_cons_idx == src_prod_idx)
4946                         break;
4947
4948                 if (spr->rx_std_cons_idx < src_prod_idx)
4949                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4950                 else
4951                         cpycnt = tp->rx_std_ring_mask + 1 -
4952                                  spr->rx_std_cons_idx;
4953
4954                 cpycnt = min(cpycnt,
4955                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4956
4957                 si = spr->rx_std_cons_idx;
4958                 di = dpr->rx_std_prod_idx;
4959
4960                 for (i = di; i < di + cpycnt; i++) {
4961                         if (dpr->rx_std_buffers[i].skb) {
4962                                 cpycnt = i - di;
4963                                 err = -ENOSPC;
4964                                 break;
4965                         }
4966                 }
4967
4968                 if (!cpycnt)
4969                         break;
4970
4971                 /* Ensure that updates to the rx_std_buffers ring and the
4972                  * shadowed hardware producer ring from tg3_recycle_skb() are
4973                  * ordered correctly WRT the skb check above.
4974                  */
4975                 smp_rmb();
4976
4977                 memcpy(&dpr->rx_std_buffers[di],
4978                        &spr->rx_std_buffers[si],
4979                        cpycnt * sizeof(struct ring_info));
4980
4981                 for (i = 0; i < cpycnt; i++, di++, si++) {
4982                         struct tg3_rx_buffer_desc *sbd, *dbd;
4983                         sbd = &spr->rx_std[si];
4984                         dbd = &dpr->rx_std[di];
4985                         dbd->addr_hi = sbd->addr_hi;
4986                         dbd->addr_lo = sbd->addr_lo;
4987                 }
4988
4989                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4990                                        tp->rx_std_ring_mask;
4991                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993         }
4994
4995         while (1) {
4996                 src_prod_idx = spr->rx_jmb_prod_idx;
4997
4998                 /* Make sure updates to the rx_jmb_buffers[] entries and
4999                  * the jumbo producer index are seen in the correct order.
5000                  */
5001                 smp_rmb();
5002
5003                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5004                         break;
5005
5006                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5007                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5008                 else
5009                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5010                                  spr->rx_jmb_cons_idx;
5011
5012                 cpycnt = min(cpycnt,
5013                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5014
5015                 si = spr->rx_jmb_cons_idx;
5016                 di = dpr->rx_jmb_prod_idx;
5017
5018                 for (i = di; i < di + cpycnt; i++) {
5019                         if (dpr->rx_jmb_buffers[i].skb) {
5020                                 cpycnt = i - di;
5021                                 err = -ENOSPC;
5022                                 break;
5023                         }
5024                 }
5025
5026                 if (!cpycnt)
5027                         break;
5028
5029                 /* Ensure that updates to the rx_jmb_buffers ring and the
5030                  * shadowed hardware producer ring from tg3_recycle_skb() are
5031                  * ordered correctly WRT the skb check above.
5032                  */
5033                 smp_rmb();
5034
5035                 memcpy(&dpr->rx_jmb_buffers[di],
5036                        &spr->rx_jmb_buffers[si],
5037                        cpycnt * sizeof(struct ring_info));
5038
5039                 for (i = 0; i < cpycnt; i++, di++, si++) {
5040                         struct tg3_rx_buffer_desc *sbd, *dbd;
5041                         sbd = &spr->rx_jmb[si].std;
5042                         dbd = &dpr->rx_jmb[di].std;
5043                         dbd->addr_hi = sbd->addr_hi;
5044                         dbd->addr_lo = sbd->addr_lo;
5045                 }
5046
5047                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5048                                        tp->rx_jmb_ring_mask;
5049                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051         }
5052
5053         return err;
5054 }
5055
5056 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5057 {
5058         struct tg3 *tp = tnapi->tp;
5059
5060         /* run TX completion thread */
5061         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5062                 tg3_tx(tnapi);
5063                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5064                         return work_done;
5065         }
5066
5067         /* run RX thread, within the bounds set by NAPI.
5068          * All RX "locking" is done by ensuring outside
5069          * code synchronizes with tg3->napi.poll()
5070          */
5071         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5072                 work_done += tg3_rx(tnapi, budget - work_done);
5073
5074         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5075                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5076                 int i, err = 0;
5077                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5078                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5079
5080                 for (i = 1; i < tp->irq_cnt; i++)
5081                         err |= tg3_rx_prodring_xfer(tp, dpr,
5082                                                     &tp->napi[i].prodring);
5083
5084                 wmb();
5085
5086                 if (std_prod_idx != dpr->rx_std_prod_idx)
5087                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5088                                      dpr->rx_std_prod_idx);
5089
5090                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5091                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5092                                      dpr->rx_jmb_prod_idx);
5093
5094                 mmiowb();
5095
5096                 if (err)
5097                         tw32_f(HOSTCC_MODE, tp->coal_now);
5098         }
5099
5100         return work_done;
5101 }
5102
5103 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5104 {
5105         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5106         struct tg3 *tp = tnapi->tp;
5107         int work_done = 0;
5108         struct tg3_hw_status *sblk = tnapi->hw_status;
5109
5110         while (1) {
5111                 work_done = tg3_poll_work(tnapi, work_done, budget);
5112
5113                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5114                         goto tx_recovery;
5115
5116                 if (unlikely(work_done >= budget))
5117                         break;
5118
5119                 /* tp->last_tag is used in tg3_int_reenable() below
5120                  * to tell the hw how much work has been processed,
5121                  * so we must read it before checking for more work.
5122                  */
5123                 tnapi->last_tag = sblk->status_tag;
5124                 tnapi->last_irq_tag = tnapi->last_tag;
5125                 rmb();
5126
5127                 /* check for RX/TX work to do */
5128                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5129                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5130                         napi_complete(napi);
5131                         /* Reenable interrupts. */
5132                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5133                         mmiowb();
5134                         break;
5135                 }
5136         }
5137
5138         return work_done;
5139
5140 tx_recovery:
5141         /* work_done is guaranteed to be less than budget. */
5142         napi_complete(napi);
5143         schedule_work(&tp->reset_task);
5144         return work_done;
5145 }
5146
5147 static int tg3_poll(struct napi_struct *napi, int budget)
5148 {
5149         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5150         struct tg3 *tp = tnapi->tp;
5151         int work_done = 0;
5152         struct tg3_hw_status *sblk = tnapi->hw_status;
5153
5154         while (1) {
5155                 tg3_poll_link(tp);
5156
5157                 work_done = tg3_poll_work(tnapi, work_done, budget);
5158
5159                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5160                         goto tx_recovery;
5161
5162                 if (unlikely(work_done >= budget))
5163                         break;
5164
5165                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5166                         /* tp->last_tag is used in tg3_int_reenable() below
5167                          * to tell the hw how much work has been processed,
5168                          * so we must read it before checking for more work.
5169                          */
5170                         tnapi->last_tag = sblk->status_tag;
5171                         tnapi->last_irq_tag = tnapi->last_tag;
5172                         rmb();
5173                 } else
5174                         sblk->status &= ~SD_STATUS_UPDATED;
5175
5176                 if (likely(!tg3_has_work(tnapi))) {
5177                         napi_complete(napi);
5178                         tg3_int_reenable(tnapi);
5179                         break;
5180                 }
5181         }
5182
5183         return work_done;
5184
5185 tx_recovery:
5186         /* work_done is guaranteed to be less than budget. */
5187         napi_complete(napi);
5188         schedule_work(&tp->reset_task);
5189         return work_done;
5190 }
5191
5192 static void tg3_napi_disable(struct tg3 *tp)
5193 {
5194         int i;
5195
5196         for (i = tp->irq_cnt - 1; i >= 0; i--)
5197                 napi_disable(&tp->napi[i].napi);
5198 }
5199
5200 static void tg3_napi_enable(struct tg3 *tp)
5201 {
5202         int i;
5203
5204         for (i = 0; i < tp->irq_cnt; i++)
5205                 napi_enable(&tp->napi[i].napi);
5206 }
5207
5208 static void tg3_napi_init(struct tg3 *tp)
5209 {
5210         int i;
5211
5212         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5213         for (i = 1; i < tp->irq_cnt; i++)
5214                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5215 }
5216
5217 static void tg3_napi_fini(struct tg3 *tp)
5218 {
5219         int i;
5220
5221         for (i = 0; i < tp->irq_cnt; i++)
5222                 netif_napi_del(&tp->napi[i].napi);
5223 }
5224
5225 static inline void tg3_netif_stop(struct tg3 *tp)
5226 {
5227         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5228         tg3_napi_disable(tp);
5229         netif_tx_disable(tp->dev);
5230 }
5231
5232 static inline void tg3_netif_start(struct tg3 *tp)
5233 {
5234         /* NOTE: unconditional netif_tx_wake_all_queues is only
5235          * appropriate so long as all callers are assured to
5236          * have free tx slots (such as after tg3_init_hw)
5237          */
5238         netif_tx_wake_all_queues(tp->dev);
5239
5240         tg3_napi_enable(tp);
5241         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5242         tg3_enable_ints(tp);
5243 }
5244
5245 static void tg3_irq_quiesce(struct tg3 *tp)
5246 {
5247         int i;
5248
5249         BUG_ON(tp->irq_sync);
5250
5251         tp->irq_sync = 1;
5252         smp_mb();
5253
5254         for (i = 0; i < tp->irq_cnt; i++)
5255                 synchronize_irq(tp->napi[i].irq_vec);
5256 }
5257
5258 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5259  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5260  * with as well.  Most of the time, this is not necessary except when
5261  * shutting down the device.
5262  */
5263 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5264 {
5265         spin_lock_bh(&tp->lock);
5266         if (irq_sync)
5267                 tg3_irq_quiesce(tp);
5268 }
5269
5270 static inline void tg3_full_unlock(struct tg3 *tp)
5271 {
5272         spin_unlock_bh(&tp->lock);
5273 }
5274
5275 /* One-shot MSI handler - Chip automatically disables interrupt
5276  * after sending MSI so driver doesn't have to do it.
5277  */
5278 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5279 {
5280         struct tg3_napi *tnapi = dev_id;
5281         struct tg3 *tp = tnapi->tp;
5282
5283         prefetch(tnapi->hw_status);
5284         if (tnapi->rx_rcb)
5285                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5286
5287         if (likely(!tg3_irq_sync(tp)))
5288                 napi_schedule(&tnapi->napi);
5289
5290         return IRQ_HANDLED;
5291 }
5292
5293 /* MSI ISR - No need to check for interrupt sharing and no need to
5294  * flush status block and interrupt mailbox. PCI ordering rules
5295  * guarantee that MSI will arrive after the status block.
5296  */
5297 static irqreturn_t tg3_msi(int irq, void *dev_id)
5298 {
5299         struct tg3_napi *tnapi = dev_id;
5300         struct tg3 *tp = tnapi->tp;
5301
5302         prefetch(tnapi->hw_status);
5303         if (tnapi->rx_rcb)
5304                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5305         /*
5306          * Writing any value to intr-mbox-0 clears PCI INTA# and
5307          * chip-internal interrupt pending events.
5308          * Writing non-zero to intr-mbox-0 additional tells the
5309          * NIC to stop sending us irqs, engaging "in-intr-handler"
5310          * event coalescing.
5311          */
5312         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5313         if (likely(!tg3_irq_sync(tp)))
5314                 napi_schedule(&tnapi->napi);
5315
5316         return IRQ_RETVAL(1);
5317 }
5318
5319 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5320 {
5321         struct tg3_napi *tnapi = dev_id;
5322         struct tg3 *tp = tnapi->tp;
5323         struct tg3_hw_status *sblk = tnapi->hw_status;
5324         unsigned int handled = 1;
5325
5326         /* In INTx mode, it is possible for the interrupt to arrive at
5327          * the CPU before the status block posted prior to the interrupt.
5328          * Reading the PCI State register will confirm whether the
5329          * interrupt is ours and will flush the status block.
5330          */
5331         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5332                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5333                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5334                         handled = 0;
5335                         goto out;
5336                 }
5337         }
5338
5339         /*
5340          * Writing any value to intr-mbox-0 clears PCI INTA# and
5341          * chip-internal interrupt pending events.
5342          * Writing non-zero to intr-mbox-0 additional tells the
5343          * NIC to stop sending us irqs, engaging "in-intr-handler"
5344          * event coalescing.
5345          *
5346          * Flush the mailbox to de-assert the IRQ immediately to prevent
5347          * spurious interrupts.  The flush impacts performance but
5348          * excessive spurious interrupts can be worse in some cases.
5349          */
5350         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5351         if (tg3_irq_sync(tp))
5352                 goto out;
5353         sblk->status &= ~SD_STATUS_UPDATED;
5354         if (likely(tg3_has_work(tnapi))) {
5355                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5356                 napi_schedule(&tnapi->napi);
5357         } else {
5358                 /* No work, shared interrupt perhaps?  re-enable
5359                  * interrupts, and flush that PCI write
5360                  */
5361                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5362                                0x00000000);
5363         }
5364 out:
5365         return IRQ_RETVAL(handled);
5366 }
5367
5368 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5369 {
5370         struct tg3_napi *tnapi = dev_id;
5371         struct tg3 *tp = tnapi->tp;
5372         struct tg3_hw_status *sblk = tnapi->hw_status;
5373         unsigned int handled = 1;
5374
5375         /* In INTx mode, it is possible for the interrupt to arrive at
5376          * the CPU before the status block posted prior to the interrupt.
5377          * Reading the PCI State register will confirm whether the
5378          * interrupt is ours and will flush the status block.
5379          */
5380         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5381                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5382                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5383                         handled = 0;
5384                         goto out;
5385                 }
5386         }
5387
5388         /*
5389          * writing any value to intr-mbox-0 clears PCI INTA# and
5390          * chip-internal interrupt pending events.
5391          * writing non-zero to intr-mbox-0 additional tells the
5392          * NIC to stop sending us irqs, engaging "in-intr-handler"
5393          * event coalescing.
5394          *
5395          * Flush the mailbox to de-assert the IRQ immediately to prevent
5396          * spurious interrupts.  The flush impacts performance but
5397          * excessive spurious interrupts can be worse in some cases.
5398          */
5399         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5400
5401         /*
5402          * In a shared interrupt configuration, sometimes other devices'
5403          * interrupts will scream.  We record the current status tag here
5404          * so that the above check can report that the screaming interrupts
5405          * are unhandled.  Eventually they will be silenced.
5406          */
5407         tnapi->last_irq_tag = sblk->status_tag;
5408
5409         if (tg3_irq_sync(tp))
5410                 goto out;
5411
5412         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5413
5414         napi_schedule(&tnapi->napi);
5415
5416 out:
5417         return IRQ_RETVAL(handled);
5418 }
5419
5420 /* ISR for interrupt test */
5421 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5422 {
5423         struct tg3_napi *tnapi = dev_id;
5424         struct tg3 *tp = tnapi->tp;
5425         struct tg3_hw_status *sblk = tnapi->hw_status;
5426
5427         if ((sblk->status & SD_STATUS_UPDATED) ||
5428             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5429                 tg3_disable_ints(tp);
5430                 return IRQ_RETVAL(1);
5431         }
5432         return IRQ_RETVAL(0);
5433 }
5434
5435 static int tg3_init_hw(struct tg3 *, int);
5436 static int tg3_halt(struct tg3 *, int, int);
5437
5438 /* Restart hardware after configuration changes, self-test, etc.
5439  * Invoked with tp->lock held.
5440  */
5441 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5442         __releases(tp->lock)
5443         __acquires(tp->lock)
5444 {
5445         int err;
5446
5447         err = tg3_init_hw(tp, reset_phy);
5448         if (err) {
5449                 netdev_err(tp->dev,
5450                            "Failed to re-initialize device, aborting\n");
5451                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5452                 tg3_full_unlock(tp);
5453                 del_timer_sync(&tp->timer);
5454                 tp->irq_sync = 0;
5455                 tg3_napi_enable(tp);
5456                 dev_close(tp->dev);
5457                 tg3_full_lock(tp, 0);
5458         }
5459         return err;
5460 }
5461
5462 #ifdef CONFIG_NET_POLL_CONTROLLER
5463 static void tg3_poll_controller(struct net_device *dev)
5464 {
5465         int i;
5466         struct tg3 *tp = netdev_priv(dev);
5467
5468         for (i = 0; i < tp->irq_cnt; i++)
5469                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5470 }
5471 #endif
5472
5473 static void tg3_reset_task(struct work_struct *work)
5474 {
5475         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5476         int err;
5477         unsigned int restart_timer;
5478
5479         tg3_full_lock(tp, 0);
5480
5481         if (!netif_running(tp->dev)) {
5482                 tg3_full_unlock(tp);
5483                 return;
5484         }
5485
5486         tg3_full_unlock(tp);
5487
5488         tg3_phy_stop(tp);
5489
5490         tg3_netif_stop(tp);
5491
5492         tg3_full_lock(tp, 1);
5493
5494         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5495         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5496
5497         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5498                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5499                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5500                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5501                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5502         }
5503
5504         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5505         err = tg3_init_hw(tp, 1);
5506         if (err)
5507                 goto out;
5508
5509         tg3_netif_start(tp);
5510
5511         if (restart_timer)
5512                 mod_timer(&tp->timer, jiffies + 1);
5513
5514 out:
5515         tg3_full_unlock(tp);
5516
5517         if (!err)
5518                 tg3_phy_start(tp);
5519 }
5520
5521 static void tg3_dump_short_state(struct tg3 *tp)
5522 {
5523         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5524                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5525         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5526                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5527 }
5528
5529 static void tg3_tx_timeout(struct net_device *dev)
5530 {
5531         struct tg3 *tp = netdev_priv(dev);
5532
5533         if (netif_msg_tx_err(tp)) {
5534                 netdev_err(dev, "transmit timed out, resetting\n");
5535                 tg3_dump_short_state(tp);
5536         }
5537
5538         schedule_work(&tp->reset_task);
5539 }
5540
5541 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5542 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5543 {
5544         u32 base = (u32) mapping & 0xffffffff;
5545
5546         return (base > 0xffffdcc0) && (base + len + 8 < base);
5547 }
5548
5549 /* Test for DMA addresses > 40-bit */
5550 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5551                                           int len)
5552 {
5553 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5554         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5555                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5556         return 0;
5557 #else
5558         return 0;
5559 #endif
5560 }
5561
5562 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5563
5564 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5565 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5566                                        struct sk_buff *skb, u32 last_plus_one,
5567                                        u32 *start, u32 base_flags, u32 mss)
5568 {
5569         struct tg3 *tp = tnapi->tp;
5570         struct sk_buff *new_skb;
5571         dma_addr_t new_addr = 0;
5572         u32 entry = *start;
5573         int i, ret = 0;
5574
5575         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5576                 new_skb = skb_copy(skb, GFP_ATOMIC);
5577         else {
5578                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5579
5580                 new_skb = skb_copy_expand(skb,
5581                                           skb_headroom(skb) + more_headroom,
5582                                           skb_tailroom(skb), GFP_ATOMIC);
5583         }
5584
5585         if (!new_skb) {
5586                 ret = -1;
5587         } else {
5588                 /* New SKB is guaranteed to be linear. */
5589                 entry = *start;
5590                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5591                                           PCI_DMA_TODEVICE);
5592                 /* Make sure the mapping succeeded */
5593                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5594                         ret = -1;
5595                         dev_kfree_skb(new_skb);
5596                         new_skb = NULL;
5597
5598                 /* Make sure new skb does not cross any 4G boundaries.
5599                  * Drop the packet if it does.
5600                  */
5601                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5602                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5603                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5604                                          PCI_DMA_TODEVICE);
5605                         ret = -1;
5606                         dev_kfree_skb(new_skb);
5607                         new_skb = NULL;
5608                 } else {
5609                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5610                                     base_flags, 1 | (mss << 1));
5611                         *start = NEXT_TX(entry);
5612                 }
5613         }
5614
5615         /* Now clean up the sw ring entries. */
5616         i = 0;
5617         while (entry != last_plus_one) {
5618                 int len;
5619
5620                 if (i == 0)
5621                         len = skb_headlen(skb);
5622                 else
5623                         len = skb_shinfo(skb)->frags[i-1].size;
5624
5625                 pci_unmap_single(tp->pdev,
5626                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5627                                                 mapping),
5628                                  len, PCI_DMA_TODEVICE);
5629                 if (i == 0) {
5630                         tnapi->tx_buffers[entry].skb = new_skb;
5631                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5632                                            new_addr);
5633                 } else {
5634                         tnapi->tx_buffers[entry].skb = NULL;
5635                 }
5636                 entry = NEXT_TX(entry);
5637                 i++;
5638         }
5639
5640         dev_kfree_skb(skb);
5641
5642         return ret;
5643 }
5644
5645 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5646                         dma_addr_t mapping, int len, u32 flags,
5647                         u32 mss_and_is_end)
5648 {
5649         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5650         int is_end = (mss_and_is_end & 0x1);
5651         u32 mss = (mss_and_is_end >> 1);
5652         u32 vlan_tag = 0;
5653
5654         if (is_end)
5655                 flags |= TXD_FLAG_END;
5656         if (flags & TXD_FLAG_VLAN) {
5657                 vlan_tag = flags >> 16;
5658                 flags &= 0xffff;
5659         }
5660         vlan_tag |= (mss << TXD_MSS_SHIFT);
5661
5662         txd->addr_hi = ((u64) mapping >> 32);
5663         txd->addr_lo = ((u64) mapping & 0xffffffff);
5664         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5665         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5666 }
5667
5668 /* hard_start_xmit for devices that don't have any bugs and
5669  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5670  */
5671 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5672                                   struct net_device *dev)
5673 {
5674         struct tg3 *tp = netdev_priv(dev);
5675         u32 len, entry, base_flags, mss;
5676         dma_addr_t mapping;
5677         struct tg3_napi *tnapi;
5678         struct netdev_queue *txq;
5679         unsigned int i, last;
5680
5681         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5682         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5683         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5684                 tnapi++;
5685
5686         /* We are running in BH disabled context with netif_tx_lock
5687          * and TX reclaim runs via tp->napi.poll inside of a software
5688          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5689          * no IRQ context deadlocks to worry about either.  Rejoice!
5690          */
5691         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5692                 if (!netif_tx_queue_stopped(txq)) {
5693                         netif_tx_stop_queue(txq);
5694
5695                         /* This is a hard error, log it. */
5696                         netdev_err(dev,
5697                                    "BUG! Tx Ring full when queue awake!\n");
5698                 }
5699                 return NETDEV_TX_BUSY;
5700         }
5701
5702         entry = tnapi->tx_prod;
5703         base_flags = 0;
5704         mss = skb_shinfo(skb)->gso_size;
5705         if (mss) {
5706                 int tcp_opt_len, ip_tcp_len;
5707                 u32 hdrlen;
5708
5709                 if (skb_header_cloned(skb) &&
5710                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5711                         dev_kfree_skb(skb);
5712                         goto out_unlock;
5713                 }
5714
5715                 if (skb_is_gso_v6(skb)) {
5716                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5717                 } else {
5718                         struct iphdr *iph = ip_hdr(skb);
5719
5720                         tcp_opt_len = tcp_optlen(skb);
5721                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5722
5723                         iph->check = 0;
5724                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5725                         hdrlen = ip_tcp_len + tcp_opt_len;
5726                 }
5727
5728                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5729                         mss |= (hdrlen & 0xc) << 12;
5730                         if (hdrlen & 0x10)
5731                                 base_flags |= 0x00000010;
5732                         base_flags |= (hdrlen & 0x3e0) << 5;
5733                 } else
5734                         mss |= hdrlen << 9;
5735
5736                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5737                                TXD_FLAG_CPU_POST_DMA);
5738
5739                 tcp_hdr(skb)->check = 0;
5740
5741         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5742                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5743         }
5744
5745 #if TG3_VLAN_TAG_USED
5746         if (vlan_tx_tag_present(skb))
5747                 base_flags |= (TXD_FLAG_VLAN |
5748                                (vlan_tx_tag_get(skb) << 16));
5749 #endif
5750
5751         len = skb_headlen(skb);
5752
5753         /* Queue skb data, a.k.a. the main skb fragment. */
5754         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5755         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5756                 dev_kfree_skb(skb);
5757                 goto out_unlock;
5758         }
5759
5760         tnapi->tx_buffers[entry].skb = skb;
5761         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5762
5763         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5764             !mss && skb->len > ETH_DATA_LEN)
5765                 base_flags |= TXD_FLAG_JMB_PKT;
5766
5767         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5768                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5769
5770         entry = NEXT_TX(entry);
5771
5772         /* Now loop through additional data fragments, and queue them. */
5773         if (skb_shinfo(skb)->nr_frags > 0) {
5774                 last = skb_shinfo(skb)->nr_frags - 1;
5775                 for (i = 0; i <= last; i++) {
5776                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5777
5778                         len = frag->size;
5779                         mapping = pci_map_page(tp->pdev,
5780                                                frag->page,
5781                                                frag->page_offset,
5782                                                len, PCI_DMA_TODEVICE);
5783                         if (pci_dma_mapping_error(tp->pdev, mapping))
5784                                 goto dma_error;
5785
5786                         tnapi->tx_buffers[entry].skb = NULL;
5787                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5788                                            mapping);
5789
5790                         tg3_set_txd(tnapi, entry, mapping, len,
5791                                     base_flags, (i == last) | (mss << 1));
5792
5793                         entry = NEXT_TX(entry);
5794                 }
5795         }
5796
5797         /* Packets are ready, update Tx producer idx local and on card. */
5798         tw32_tx_mbox(tnapi->prodmbox, entry);
5799
5800         tnapi->tx_prod = entry;
5801         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5802                 netif_tx_stop_queue(txq);
5803
5804                 /* netif_tx_stop_queue() must be done before checking
5805                  * checking tx index in tg3_tx_avail() below, because in
5806                  * tg3_tx(), we update tx index before checking for
5807                  * netif_tx_queue_stopped().
5808                  */
5809                 smp_mb();
5810                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5811                         netif_tx_wake_queue(txq);
5812         }
5813
5814 out_unlock:
5815         mmiowb();
5816
5817         return NETDEV_TX_OK;
5818
5819 dma_error:
5820         last = i;
5821         entry = tnapi->tx_prod;
5822         tnapi->tx_buffers[entry].skb = NULL;
5823         pci_unmap_single(tp->pdev,
5824                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5825                          skb_headlen(skb),
5826                          PCI_DMA_TODEVICE);
5827         for (i = 0; i <= last; i++) {
5828                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5829                 entry = NEXT_TX(entry);
5830
5831                 pci_unmap_page(tp->pdev,
5832                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5833                                               mapping),
5834                                frag->size, PCI_DMA_TODEVICE);
5835         }
5836
5837         dev_kfree_skb(skb);
5838         return NETDEV_TX_OK;
5839 }
5840
5841 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5842                                           struct net_device *);
5843
5844 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5845  * TSO header is greater than 80 bytes.
5846  */
5847 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5848 {
5849         struct sk_buff *segs, *nskb;
5850         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5851
5852         /* Estimate the number of fragments in the worst case */
5853         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5854                 netif_stop_queue(tp->dev);
5855
5856                 /* netif_tx_stop_queue() must be done before checking
5857                  * checking tx index in tg3_tx_avail() below, because in
5858                  * tg3_tx(), we update tx index before checking for
5859                  * netif_tx_queue_stopped().
5860                  */
5861                 smp_mb();
5862                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5863                         return NETDEV_TX_BUSY;
5864
5865                 netif_wake_queue(tp->dev);
5866         }
5867
5868         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5869         if (IS_ERR(segs))
5870                 goto tg3_tso_bug_end;
5871
5872         do {
5873                 nskb = segs;
5874                 segs = segs->next;
5875                 nskb->next = NULL;
5876                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5877         } while (segs);
5878
5879 tg3_tso_bug_end:
5880         dev_kfree_skb(skb);
5881
5882         return NETDEV_TX_OK;
5883 }
5884
5885 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5886  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5887  */
5888 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5889                                           struct net_device *dev)
5890 {
5891         struct tg3 *tp = netdev_priv(dev);
5892         u32 len, entry, base_flags, mss;
5893         int would_hit_hwbug;
5894         dma_addr_t mapping;
5895         struct tg3_napi *tnapi;
5896         struct netdev_queue *txq;
5897         unsigned int i, last;
5898
5899         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5900         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5901         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5902                 tnapi++;
5903
5904         /* We are running in BH disabled context with netif_tx_lock
5905          * and TX reclaim runs via tp->napi.poll inside of a software
5906          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5907          * no IRQ context deadlocks to worry about either.  Rejoice!
5908          */
5909         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5910                 if (!netif_tx_queue_stopped(txq)) {
5911                         netif_tx_stop_queue(txq);
5912
5913                         /* This is a hard error, log it. */
5914                         netdev_err(dev,
5915                                    "BUG! Tx Ring full when queue awake!\n");
5916                 }
5917                 return NETDEV_TX_BUSY;
5918         }
5919
5920         entry = tnapi->tx_prod;
5921         base_flags = 0;
5922         if (skb->ip_summed == CHECKSUM_PARTIAL)
5923                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5924
5925         mss = skb_shinfo(skb)->gso_size;
5926         if (mss) {
5927                 struct iphdr *iph;
5928                 u32 tcp_opt_len, hdr_len;
5929
5930                 if (skb_header_cloned(skb) &&
5931                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5932                         dev_kfree_skb(skb);
5933                         goto out_unlock;
5934                 }
5935
5936                 iph = ip_hdr(skb);
5937                 tcp_opt_len = tcp_optlen(skb);
5938
5939                 if (skb_is_gso_v6(skb)) {
5940                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5941                 } else {
5942                         u32 ip_tcp_len;
5943
5944                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5945                         hdr_len = ip_tcp_len + tcp_opt_len;
5946
5947                         iph->check = 0;
5948                         iph->tot_len = htons(mss + hdr_len);
5949                 }
5950
5951                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5952                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5953                         return tg3_tso_bug(tp, skb);
5954
5955                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5956                                TXD_FLAG_CPU_POST_DMA);
5957
5958                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5959                         tcp_hdr(skb)->check = 0;
5960                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5961                 } else
5962                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5963                                                                  iph->daddr, 0,
5964                                                                  IPPROTO_TCP,
5965                                                                  0);
5966
5967                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5968                         mss |= (hdr_len & 0xc) << 12;
5969                         if (hdr_len & 0x10)
5970                                 base_flags |= 0x00000010;
5971                         base_flags |= (hdr_len & 0x3e0) << 5;
5972                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5973                         mss |= hdr_len << 9;
5974                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5975                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5976                         if (tcp_opt_len || iph->ihl > 5) {
5977                                 int tsflags;
5978
5979                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5980                                 mss |= (tsflags << 11);
5981                         }
5982                 } else {
5983                         if (tcp_opt_len || iph->ihl > 5) {
5984                                 int tsflags;
5985
5986                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5987                                 base_flags |= tsflags << 12;
5988                         }
5989                 }
5990         }
5991 #if TG3_VLAN_TAG_USED
5992         if (vlan_tx_tag_present(skb))
5993                 base_flags |= (TXD_FLAG_VLAN |
5994                                (vlan_tx_tag_get(skb) << 16));
5995 #endif
5996
5997         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5998             !mss && skb->len > ETH_DATA_LEN)
5999                 base_flags |= TXD_FLAG_JMB_PKT;
6000
6001         len = skb_headlen(skb);
6002
6003         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6004         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6005                 dev_kfree_skb(skb);
6006                 goto out_unlock;
6007         }
6008
6009         tnapi->tx_buffers[entry].skb = skb;
6010         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6011
6012         would_hit_hwbug = 0;
6013
6014         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6015                 would_hit_hwbug = 1;
6016
6017         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6018             tg3_4g_overflow_test(mapping, len))
6019                 would_hit_hwbug = 1;
6020
6021         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6022             tg3_40bit_overflow_test(tp, mapping, len))
6023                 would_hit_hwbug = 1;
6024
6025         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6026                 would_hit_hwbug = 1;
6027
6028         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6029                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6030
6031         entry = NEXT_TX(entry);
6032
6033         /* Now loop through additional data fragments, and queue them. */
6034         if (skb_shinfo(skb)->nr_frags > 0) {
6035                 last = skb_shinfo(skb)->nr_frags - 1;
6036                 for (i = 0; i <= last; i++) {
6037                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6038
6039                         len = frag->size;
6040                         mapping = pci_map_page(tp->pdev,
6041                                                frag->page,
6042                                                frag->page_offset,
6043                                                len, PCI_DMA_TODEVICE);
6044
6045                         tnapi->tx_buffers[entry].skb = NULL;
6046                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6047                                            mapping);
6048                         if (pci_dma_mapping_error(tp->pdev, mapping))
6049                                 goto dma_error;
6050
6051                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6052                             len <= 8)
6053                                 would_hit_hwbug = 1;
6054
6055                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6056                             tg3_4g_overflow_test(mapping, len))
6057                                 would_hit_hwbug = 1;
6058
6059                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6060                             tg3_40bit_overflow_test(tp, mapping, len))
6061                                 would_hit_hwbug = 1;
6062
6063                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6064                                 tg3_set_txd(tnapi, entry, mapping, len,
6065                                             base_flags, (i == last)|(mss << 1));
6066                         else
6067                                 tg3_set_txd(tnapi, entry, mapping, len,
6068                                             base_flags, (i == last));
6069
6070                         entry = NEXT_TX(entry);
6071                 }
6072         }
6073
6074         if (would_hit_hwbug) {
6075                 u32 last_plus_one = entry;
6076                 u32 start;
6077
6078                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6079                 start &= (TG3_TX_RING_SIZE - 1);
6080
6081                 /* If the workaround fails due to memory/mapping
6082                  * failure, silently drop this packet.
6083                  */
6084                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6085                                                 &start, base_flags, mss))
6086                         goto out_unlock;
6087
6088                 entry = start;
6089         }
6090
6091         /* Packets are ready, update Tx producer idx local and on card. */
6092         tw32_tx_mbox(tnapi->prodmbox, entry);
6093
6094         tnapi->tx_prod = entry;
6095         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6096                 netif_tx_stop_queue(txq);
6097
6098                 /* netif_tx_stop_queue() must be done before checking
6099                  * checking tx index in tg3_tx_avail() below, because in
6100                  * tg3_tx(), we update tx index before checking for
6101                  * netif_tx_queue_stopped().
6102                  */
6103                 smp_mb();
6104                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6105                         netif_tx_wake_queue(txq);
6106         }
6107
6108 out_unlock:
6109         mmiowb();
6110
6111         return NETDEV_TX_OK;
6112
6113 dma_error:
6114         last = i;
6115         entry = tnapi->tx_prod;
6116         tnapi->tx_buffers[entry].skb = NULL;
6117         pci_unmap_single(tp->pdev,
6118                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6119                          skb_headlen(skb),
6120                          PCI_DMA_TODEVICE);
6121         for (i = 0; i <= last; i++) {
6122                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6123                 entry = NEXT_TX(entry);
6124
6125                 pci_unmap_page(tp->pdev,
6126                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6127                                               mapping),
6128                                frag->size, PCI_DMA_TODEVICE);
6129         }
6130
6131         dev_kfree_skb(skb);
6132         return NETDEV_TX_OK;
6133 }
6134
6135 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6136                                int new_mtu)
6137 {
6138         dev->mtu = new_mtu;
6139
6140         if (new_mtu > ETH_DATA_LEN) {
6141                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6142                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6143                         ethtool_op_set_tso(dev, 0);
6144                 } else {
6145                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6146                 }
6147         } else {
6148                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6149                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6150                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6151         }
6152 }
6153
6154 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6155 {
6156         struct tg3 *tp = netdev_priv(dev);
6157         int err;
6158
6159         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6160                 return -EINVAL;
6161
6162         if (!netif_running(dev)) {
6163                 /* We'll just catch it later when the
6164                  * device is up'd.
6165                  */
6166                 tg3_set_mtu(dev, tp, new_mtu);
6167                 return 0;
6168         }
6169
6170         tg3_phy_stop(tp);
6171
6172         tg3_netif_stop(tp);
6173
6174         tg3_full_lock(tp, 1);
6175
6176         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6177
6178         tg3_set_mtu(dev, tp, new_mtu);
6179
6180         err = tg3_restart_hw(tp, 0);
6181
6182         if (!err)
6183                 tg3_netif_start(tp);
6184
6185         tg3_full_unlock(tp);
6186
6187         if (!err)
6188                 tg3_phy_start(tp);
6189
6190         return err;
6191 }
6192
6193 static void tg3_rx_prodring_free(struct tg3 *tp,
6194                                  struct tg3_rx_prodring_set *tpr)
6195 {
6196         int i;
6197
6198         if (tpr != &tp->napi[0].prodring) {
6199                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6200                      i = (i + 1) & tp->rx_std_ring_mask)
6201                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6202                                         tp->rx_pkt_map_sz);
6203
6204                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6205                         for (i = tpr->rx_jmb_cons_idx;
6206                              i != tpr->rx_jmb_prod_idx;
6207                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6208                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6209                                                 TG3_RX_JMB_MAP_SZ);
6210                         }
6211                 }
6212
6213                 return;
6214         }
6215
6216         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6217                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6218                                 tp->rx_pkt_map_sz);
6219
6220         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6221             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6222                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6223                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6224                                         TG3_RX_JMB_MAP_SZ);
6225         }
6226 }
6227
6228 /* Initialize rx rings for packet processing.
6229  *
6230  * The chip has been shut down and the driver detached from
6231  * the networking, so no interrupts or new tx packets will
6232  * end up in the driver.  tp->{tx,}lock are held and thus
6233  * we may not sleep.
6234  */
6235 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6236                                  struct tg3_rx_prodring_set *tpr)
6237 {
6238         u32 i, rx_pkt_dma_sz;
6239
6240         tpr->rx_std_cons_idx = 0;
6241         tpr->rx_std_prod_idx = 0;
6242         tpr->rx_jmb_cons_idx = 0;
6243         tpr->rx_jmb_prod_idx = 0;
6244
6245         if (tpr != &tp->napi[0].prodring) {
6246                 memset(&tpr->rx_std_buffers[0], 0,
6247                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6248                 if (tpr->rx_jmb_buffers)
6249                         memset(&tpr->rx_jmb_buffers[0], 0,
6250                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6251                 goto done;
6252         }
6253
6254         /* Zero out all descriptors. */
6255         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6256
6257         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6258         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6259             tp->dev->mtu > ETH_DATA_LEN)
6260                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6261         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6262
6263         /* Initialize invariants of the rings, we only set this
6264          * stuff once.  This works because the card does not
6265          * write into the rx buffer posting rings.
6266          */
6267         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6268                 struct tg3_rx_buffer_desc *rxd;
6269
6270                 rxd = &tpr->rx_std[i];
6271                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6272                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6273                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6274                                (i << RXD_OPAQUE_INDEX_SHIFT));
6275         }
6276
6277         /* Now allocate fresh SKBs for each rx ring. */
6278         for (i = 0; i < tp->rx_pending; i++) {
6279                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6280                         netdev_warn(tp->dev,
6281                                     "Using a smaller RX standard ring. Only "
6282                                     "%d out of %d buffers were allocated "
6283                                     "successfully\n", i, tp->rx_pending);
6284                         if (i == 0)
6285                                 goto initfail;
6286                         tp->rx_pending = i;
6287                         break;
6288                 }
6289         }
6290
6291         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6292             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6293                 goto done;
6294
6295         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6296
6297         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6298                 goto done;
6299
6300         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6301                 struct tg3_rx_buffer_desc *rxd;
6302
6303                 rxd = &tpr->rx_jmb[i].std;
6304                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6305                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6306                                   RXD_FLAG_JUMBO;
6307                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6308                        (i << RXD_OPAQUE_INDEX_SHIFT));
6309         }
6310
6311         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6312                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6313                         netdev_warn(tp->dev,
6314                                     "Using a smaller RX jumbo ring. Only %d "
6315                                     "out of %d buffers were allocated "
6316                                     "successfully\n", i, tp->rx_jumbo_pending);
6317                         if (i == 0)
6318                                 goto initfail;
6319                         tp->rx_jumbo_pending = i;
6320                         break;
6321                 }
6322         }
6323
6324 done:
6325         return 0;
6326
6327 initfail:
6328         tg3_rx_prodring_free(tp, tpr);
6329         return -ENOMEM;
6330 }
6331
6332 static void tg3_rx_prodring_fini(struct tg3 *tp,
6333                                  struct tg3_rx_prodring_set *tpr)
6334 {
6335         kfree(tpr->rx_std_buffers);
6336         tpr->rx_std_buffers = NULL;
6337         kfree(tpr->rx_jmb_buffers);
6338         tpr->rx_jmb_buffers = NULL;
6339         if (tpr->rx_std) {
6340                 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
6341                                   tpr->rx_std, tpr->rx_std_mapping);
6342                 tpr->rx_std = NULL;
6343         }
6344         if (tpr->rx_jmb) {
6345                 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
6346                                   tpr->rx_jmb, tpr->rx_jmb_mapping);
6347                 tpr->rx_jmb = NULL;
6348         }
6349 }
6350
6351 static int tg3_rx_prodring_init(struct tg3 *tp,
6352                                 struct tg3_rx_prodring_set *tpr)
6353 {
6354         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6355                                       GFP_KERNEL);
6356         if (!tpr->rx_std_buffers)
6357                 return -ENOMEM;
6358
6359         tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
6360                                          TG3_RX_STD_RING_BYTES(tp),
6361                                          &tpr->rx_std_mapping,
6362                                          GFP_KERNEL);
6363         if (!tpr->rx_std)
6364                 goto err_out;
6365
6366         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6367             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6368                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6369                                               GFP_KERNEL);
6370                 if (!tpr->rx_jmb_buffers)
6371                         goto err_out;
6372
6373                 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
6374                                                  TG3_RX_JMB_RING_BYTES(tp),
6375                                                  &tpr->rx_jmb_mapping,
6376                                                  GFP_KERNEL);
6377                 if (!tpr->rx_jmb)
6378                         goto err_out;
6379         }
6380
6381         return 0;
6382
6383 err_out:
6384         tg3_rx_prodring_fini(tp, tpr);
6385         return -ENOMEM;
6386 }
6387
6388 /* Free up pending packets in all rx/tx rings.
6389  *
6390  * The chip has been shut down and the driver detached from
6391  * the networking, so no interrupts or new tx packets will
6392  * end up in the driver.  tp->{tx,}lock is not held and we are not
6393  * in an interrupt context and thus may sleep.
6394  */
6395 static void tg3_free_rings(struct tg3 *tp)
6396 {
6397         int i, j;
6398
6399         for (j = 0; j < tp->irq_cnt; j++) {
6400                 struct tg3_napi *tnapi = &tp->napi[j];
6401
6402                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6403
6404                 if (!tnapi->tx_buffers)
6405                         continue;
6406
6407                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6408                         struct ring_info *txp;
6409                         struct sk_buff *skb;
6410                         unsigned int k;
6411
6412                         txp = &tnapi->tx_buffers[i];
6413                         skb = txp->skb;
6414
6415                         if (skb == NULL) {
6416                                 i++;
6417                                 continue;
6418                         }
6419
6420                         pci_unmap_single(tp->pdev,
6421                                          dma_unmap_addr(txp, mapping),
6422                                          skb_headlen(skb),
6423                                          PCI_DMA_TODEVICE);
6424                         txp->skb = NULL;
6425
6426                         i++;
6427
6428                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6429                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6430                                 pci_unmap_page(tp->pdev,
6431                                                dma_unmap_addr(txp, mapping),
6432                                                skb_shinfo(skb)->frags[k].size,
6433                                                PCI_DMA_TODEVICE);
6434                                 i++;
6435                         }
6436
6437                         dev_kfree_skb_any(skb);
6438                 }
6439         }
6440 }
6441
6442 /* Initialize tx/rx rings for packet processing.
6443  *
6444  * The chip has been shut down and the driver detached from
6445  * the networking, so no interrupts or new tx packets will
6446  * end up in the driver.  tp->{tx,}lock are held and thus
6447  * we may not sleep.
6448  */
6449 static int tg3_init_rings(struct tg3 *tp)
6450 {
6451         int i;
6452
6453         /* Free up all the SKBs. */
6454         tg3_free_rings(tp);
6455
6456         for (i = 0; i < tp->irq_cnt; i++) {
6457                 struct tg3_napi *tnapi = &tp->napi[i];
6458
6459                 tnapi->last_tag = 0;
6460                 tnapi->last_irq_tag = 0;
6461                 tnapi->hw_status->status = 0;
6462                 tnapi->hw_status->status_tag = 0;
6463                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6464
6465                 tnapi->tx_prod = 0;
6466                 tnapi->tx_cons = 0;
6467                 if (tnapi->tx_ring)
6468                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6469
6470                 tnapi->rx_rcb_ptr = 0;
6471                 if (tnapi->rx_rcb)
6472                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6473
6474                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6475                         tg3_free_rings(tp);
6476                         return -ENOMEM;
6477                 }
6478         }
6479
6480         return 0;
6481 }
6482
6483 /*
6484  * Must not be invoked with interrupt sources disabled and
6485  * the hardware shutdown down.
6486  */
6487 static void tg3_free_consistent(struct tg3 *tp)
6488 {
6489         int i;
6490
6491         for (i = 0; i < tp->irq_cnt; i++) {
6492                 struct tg3_napi *tnapi = &tp->napi[i];
6493
6494                 if (tnapi->tx_ring) {
6495                         dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
6496                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6497                         tnapi->tx_ring = NULL;
6498                 }
6499
6500                 kfree(tnapi->tx_buffers);
6501                 tnapi->tx_buffers = NULL;
6502
6503                 if (tnapi->rx_rcb) {
6504                         dma_free_coherent(&tp->pdev->dev,
6505                                           TG3_RX_RCB_RING_BYTES(tp),
6506                                           tnapi->rx_rcb,
6507                                           tnapi->rx_rcb_mapping);
6508                         tnapi->rx_rcb = NULL;
6509                 }
6510
6511                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6512
6513                 if (tnapi->hw_status) {
6514                         dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
6515                                           tnapi->hw_status,
6516                                           tnapi->status_mapping);
6517                         tnapi->hw_status = NULL;
6518                 }
6519         }
6520
6521         if (tp->hw_stats) {
6522                 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
6523                                   tp->hw_stats, tp->stats_mapping);
6524                 tp->hw_stats = NULL;
6525         }
6526 }
6527
6528 /*
6529  * Must not be invoked with interrupt sources disabled and
6530  * the hardware shutdown down.  Can sleep.
6531  */
6532 static int tg3_alloc_consistent(struct tg3 *tp)
6533 {
6534         int i;
6535
6536         tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev,
6537                                           sizeof(struct tg3_hw_stats),
6538                                           &tp->stats_mapping,
6539                                           GFP_KERNEL);
6540         if (!tp->hw_stats)
6541                 goto err_out;
6542
6543         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6544
6545         for (i = 0; i < tp->irq_cnt; i++) {
6546                 struct tg3_napi *tnapi = &tp->napi[i];
6547                 struct tg3_hw_status *sblk;
6548
6549                 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev,
6550                                                       TG3_HW_STATUS_SIZE,
6551                                                       &tnapi->status_mapping,
6552                                                       GFP_KERNEL);
6553                 if (!tnapi->hw_status)
6554                         goto err_out;
6555
6556                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6557                 sblk = tnapi->hw_status;
6558
6559                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6560                         goto err_out;
6561
6562                 /* If multivector TSS is enabled, vector 0 does not handle
6563                  * tx interrupts.  Don't allocate any resources for it.
6564                  */
6565                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6566                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6567                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6568                                                     TG3_TX_RING_SIZE,
6569                                                     GFP_KERNEL);
6570                         if (!tnapi->tx_buffers)
6571                                 goto err_out;
6572
6573                         tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
6574                                                             TG3_TX_RING_BYTES,
6575                                                         &tnapi->tx_desc_mapping,
6576                                                             GFP_KERNEL);
6577                         if (!tnapi->tx_ring)
6578                                 goto err_out;
6579                 }
6580
6581                 /*
6582                  * When RSS is enabled, the status block format changes
6583                  * slightly.  The "rx_jumbo_consumer", "reserved",
6584                  * and "rx_mini_consumer" members get mapped to the
6585                  * other three rx return ring producer indexes.
6586                  */
6587                 switch (i) {
6588                 default:
6589                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6590                         break;
6591                 case 2:
6592                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6593                         break;
6594                 case 3:
6595                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6596                         break;
6597                 case 4:
6598                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6599                         break;
6600                 }
6601
6602                 /*
6603                  * If multivector RSS is enabled, vector 0 does not handle
6604                  * rx or tx interrupts.  Don't allocate any resources for it.
6605                  */
6606                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6607                         continue;
6608
6609                 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev,
6610                                                    TG3_RX_RCB_RING_BYTES(tp),
6611                                                    &tnapi->rx_rcb_mapping,
6612                                                    GFP_KERNEL);
6613                 if (!tnapi->rx_rcb)
6614                         goto err_out;
6615
6616                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6617         }
6618
6619         return 0;
6620
6621 err_out:
6622         tg3_free_consistent(tp);
6623         return -ENOMEM;
6624 }
6625
6626 #define MAX_WAIT_CNT 1000
6627
6628 /* To stop a block, clear the enable bit and poll till it
6629  * clears.  tp->lock is held.
6630  */
6631 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6632 {
6633         unsigned int i;
6634         u32 val;
6635
6636         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6637                 switch (ofs) {
6638                 case RCVLSC_MODE:
6639                 case DMAC_MODE:
6640                 case MBFREE_MODE:
6641                 case BUFMGR_MODE:
6642                 case MEMARB_MODE:
6643                         /* We can't enable/disable these bits of the
6644                          * 5705/5750, just say success.
6645                          */
6646                         return 0;
6647
6648                 default:
6649                         break;
6650                 }
6651         }
6652
6653         val = tr32(ofs);
6654         val &= ~enable_bit;
6655         tw32_f(ofs, val);
6656
6657         for (i = 0; i < MAX_WAIT_CNT; i++) {
6658                 udelay(100);
6659                 val = tr32(ofs);
6660                 if ((val & enable_bit) == 0)
6661                         break;
6662         }
6663
6664         if (i == MAX_WAIT_CNT && !silent) {
6665                 dev_err(&tp->pdev->dev,
6666                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6667                         ofs, enable_bit);
6668                 return -ENODEV;
6669         }
6670
6671         return 0;
6672 }
6673
6674 /* tp->lock is held. */
6675 static int tg3_abort_hw(struct tg3 *tp, int silent)
6676 {
6677         int i, err;
6678
6679         tg3_disable_ints(tp);
6680
6681         tp->rx_mode &= ~RX_MODE_ENABLE;
6682         tw32_f(MAC_RX_MODE, tp->rx_mode);
6683         udelay(10);
6684
6685         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6686         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6687         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6688         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6689         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6690         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6691
6692         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6693         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6694         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6695         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6696         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6697         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6698         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6699
6700         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6701         tw32_f(MAC_MODE, tp->mac_mode);
6702         udelay(40);
6703
6704         tp->tx_mode &= ~TX_MODE_ENABLE;
6705         tw32_f(MAC_TX_MODE, tp->tx_mode);
6706
6707         for (i = 0; i < MAX_WAIT_CNT; i++) {
6708                 udelay(100);
6709                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6710                         break;
6711         }
6712         if (i >= MAX_WAIT_CNT) {
6713                 dev_err(&tp->pdev->dev,
6714                         "%s timed out, TX_MODE_ENABLE will not clear "
6715                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6716                 err |= -ENODEV;
6717         }
6718
6719         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6720         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6721         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6722
6723         tw32(FTQ_RESET, 0xffffffff);
6724         tw32(FTQ_RESET, 0x00000000);
6725
6726         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6727         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6728
6729         for (i = 0; i < tp->irq_cnt; i++) {
6730                 struct tg3_napi *tnapi = &tp->napi[i];
6731                 if (tnapi->hw_status)
6732                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6733         }
6734         if (tp->hw_stats)
6735                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6736
6737         return err;
6738 }
6739
6740 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6741 {
6742         int i;
6743         u32 apedata;
6744
6745         /* NCSI does not support APE events */
6746         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6747                 return;
6748
6749         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6750         if (apedata != APE_SEG_SIG_MAGIC)
6751                 return;
6752
6753         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6754         if (!(apedata & APE_FW_STATUS_READY))
6755                 return;
6756
6757         /* Wait for up to 1 millisecond for APE to service previous event. */
6758         for (i = 0; i < 10; i++) {
6759                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6760                         return;
6761
6762                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6763
6764                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6765                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6766                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6767
6768                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6769
6770                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6771                         break;
6772
6773                 udelay(100);
6774         }
6775
6776         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6777                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6778 }
6779
6780 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6781 {
6782         u32 event;
6783         u32 apedata;
6784
6785         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6786                 return;
6787
6788         switch (kind) {
6789         case RESET_KIND_INIT:
6790                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6791                                 APE_HOST_SEG_SIG_MAGIC);
6792                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6793                                 APE_HOST_SEG_LEN_MAGIC);
6794                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6795                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6796                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6797                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6798                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6799                                 APE_HOST_BEHAV_NO_PHYLOCK);
6800                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6801                                     TG3_APE_HOST_DRVR_STATE_START);
6802
6803                 event = APE_EVENT_STATUS_STATE_START;
6804                 break;
6805         case RESET_KIND_SHUTDOWN:
6806                 /* With the interface we are currently using,
6807                  * APE does not track driver state.  Wiping
6808                  * out the HOST SEGMENT SIGNATURE forces
6809                  * the APE to assume OS absent status.
6810                  */
6811                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6812
6813                 if (device_may_wakeup(&tp->pdev->dev) &&
6814                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6815                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6816                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6817                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6818                 } else
6819                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6820
6821                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6822
6823                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6824                 break;
6825         case RESET_KIND_SUSPEND:
6826                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6827                 break;
6828         default:
6829                 return;
6830         }
6831
6832         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6833
6834         tg3_ape_send_event(tp, event);
6835 }
6836
6837 /* tp->lock is held. */
6838 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6839 {
6840         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6841                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6842
6843         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6844                 switch (kind) {
6845                 case RESET_KIND_INIT:
6846                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6847                                       DRV_STATE_START);
6848                         break;
6849
6850                 case RESET_KIND_SHUTDOWN:
6851                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6852                                       DRV_STATE_UNLOAD);
6853                         break;
6854
6855                 case RESET_KIND_SUSPEND:
6856                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6857                                       DRV_STATE_SUSPEND);
6858                         break;
6859
6860                 default:
6861                         break;
6862                 }
6863         }
6864
6865         if (kind == RESET_KIND_INIT ||
6866             kind == RESET_KIND_SUSPEND)
6867                 tg3_ape_driver_state_change(tp, kind);
6868 }
6869
6870 /* tp->lock is held. */
6871 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6872 {
6873         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6874                 switch (kind) {
6875                 case RESET_KIND_INIT:
6876                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6877                                       DRV_STATE_START_DONE);
6878                         break;
6879
6880                 case RESET_KIND_SHUTDOWN:
6881                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6882                                       DRV_STATE_UNLOAD_DONE);
6883                         break;
6884
6885                 default:
6886                         break;
6887                 }
6888         }
6889
6890         if (kind == RESET_KIND_SHUTDOWN)
6891                 tg3_ape_driver_state_change(tp, kind);
6892 }
6893
6894 /* tp->lock is held. */
6895 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6896 {
6897         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6898                 switch (kind) {
6899                 case RESET_KIND_INIT:
6900                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6901                                       DRV_STATE_START);
6902                         break;
6903
6904                 case RESET_KIND_SHUTDOWN:
6905                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6906                                       DRV_STATE_UNLOAD);
6907                         break;
6908
6909                 case RESET_KIND_SUSPEND:
6910                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6911                                       DRV_STATE_SUSPEND);
6912                         break;
6913
6914                 default:
6915                         break;
6916                 }
6917         }
6918 }
6919
6920 static int tg3_poll_fw(struct tg3 *tp)
6921 {
6922         int i;
6923         u32 val;
6924
6925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6926                 /* Wait up to 20ms for init done. */
6927                 for (i = 0; i < 200; i++) {
6928                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6929                                 return 0;
6930                         udelay(100);
6931                 }
6932                 return -ENODEV;
6933         }
6934
6935         /* Wait for firmware initialization to complete. */
6936         for (i = 0; i < 100000; i++) {
6937                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6938                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6939                         break;
6940                 udelay(10);
6941         }
6942
6943         /* Chip might not be fitted with firmware.  Some Sun onboard
6944          * parts are configured like that.  So don't signal the timeout
6945          * of the above loop as an error, but do report the lack of
6946          * running firmware once.
6947          */
6948         if (i >= 100000 &&
6949             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6950                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6951
6952                 netdev_info(tp->dev, "No firmware running\n");
6953         }
6954
6955         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6956                 /* The 57765 A0 needs a little more
6957                  * time to do some important work.
6958                  */
6959                 mdelay(10);
6960         }
6961
6962         return 0;
6963 }
6964
6965 /* Save PCI command register before chip reset */
6966 static void tg3_save_pci_state(struct tg3 *tp)
6967 {
6968         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6969 }
6970
6971 /* Restore PCI state after chip reset */
6972 static void tg3_restore_pci_state(struct tg3 *tp)
6973 {
6974         u32 val;
6975
6976         /* Re-enable indirect register accesses. */
6977         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6978                                tp->misc_host_ctrl);
6979
6980         /* Set MAX PCI retry to zero. */
6981         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6982         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6983             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6984                 val |= PCISTATE_RETRY_SAME_DMA;
6985         /* Allow reads and writes to the APE register and memory space. */
6986         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6987                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6988                        PCISTATE_ALLOW_APE_SHMEM_WR |
6989                        PCISTATE_ALLOW_APE_PSPACE_WR;
6990         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6991
6992         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6993
6994         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6995                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6996                         pcie_set_readrq(tp->pdev, tp->pcie_readrq);
6997                 else {
6998                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6999                                               tp->pci_cacheline_sz);
7000                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
7001                                               tp->pci_lat_timer);
7002                 }
7003         }
7004
7005         /* Make sure PCI-X relaxed ordering bit is clear. */
7006         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7007                 u16 pcix_cmd;
7008
7009                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7010                                      &pcix_cmd);
7011                 pcix_cmd &= ~PCI_X_CMD_ERO;
7012                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7013                                       pcix_cmd);
7014         }
7015
7016         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7017
7018                 /* Chip reset on 5780 will reset MSI enable bit,
7019                  * so need to restore it.
7020                  */
7021                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7022                         u16 ctrl;
7023
7024                         pci_read_config_word(tp->pdev,
7025                                              tp->msi_cap + PCI_MSI_FLAGS,
7026                                              &ctrl);
7027                         pci_write_config_word(tp->pdev,
7028                                               tp->msi_cap + PCI_MSI_FLAGS,
7029                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7030                         val = tr32(MSGINT_MODE);
7031                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7032                 }
7033         }
7034 }
7035
7036 static void tg3_stop_fw(struct tg3 *);
7037
7038 /* tp->lock is held. */
7039 static int tg3_chip_reset(struct tg3 *tp)
7040 {
7041         u32 val;
7042         void (*write_op)(struct tg3 *, u32, u32);
7043         int i, err;
7044
7045         tg3_nvram_lock(tp);
7046
7047         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7048
7049         /* No matching tg3_nvram_unlock() after this because
7050          * chip reset below will undo the nvram lock.
7051          */
7052         tp->nvram_lock_cnt = 0;
7053
7054         /* GRC_MISC_CFG core clock reset will clear the memory
7055          * enable bit in PCI register 4 and the MSI enable bit
7056          * on some chips, so we save relevant registers here.
7057          */
7058         tg3_save_pci_state(tp);
7059
7060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7061             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7062                 tw32(GRC_FASTBOOT_PC, 0);
7063
7064         /*
7065          * We must avoid the readl() that normally takes place.
7066          * It locks machines, causes machine checks, and other
7067          * fun things.  So, temporarily disable the 5701
7068          * hardware workaround, while we do the reset.
7069          */
7070         write_op = tp->write32;
7071         if (write_op == tg3_write_flush_reg32)
7072                 tp->write32 = tg3_write32;
7073
7074         /* Prevent the irq handler from reading or writing PCI registers
7075          * during chip reset when the memory enable bit in the PCI command
7076          * register may be cleared.  The chip does not generate interrupt
7077          * at this time, but the irq handler may still be called due to irq
7078          * sharing or irqpoll.
7079          */
7080         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7081         for (i = 0; i < tp->irq_cnt; i++) {
7082                 struct tg3_napi *tnapi = &tp->napi[i];
7083                 if (tnapi->hw_status) {
7084                         tnapi->hw_status->status = 0;
7085                         tnapi->hw_status->status_tag = 0;
7086                 }
7087                 tnapi->last_tag = 0;
7088                 tnapi->last_irq_tag = 0;
7089         }
7090         smp_mb();
7091
7092         for (i = 0; i < tp->irq_cnt; i++)
7093                 synchronize_irq(tp->napi[i].irq_vec);
7094
7095         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7096                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7097                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7098         }
7099
7100         /* do the reset */
7101         val = GRC_MISC_CFG_CORECLK_RESET;
7102
7103         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7104                 /* Force PCIe 1.0a mode */
7105                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7106                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7107                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7108                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7109                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7110
7111                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7112                         tw32(GRC_MISC_CFG, (1 << 29));
7113                         val |= (1 << 29);
7114                 }
7115         }
7116
7117         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7118                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7119                 tw32(GRC_VCPU_EXT_CTRL,
7120                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7121         }
7122
7123         /* Manage gphy power for all CPMU absent PCIe devices. */
7124         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7125             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7126                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7127
7128         tw32(GRC_MISC_CFG, val);
7129
7130         /* restore 5701 hardware bug workaround write method */
7131         tp->write32 = write_op;
7132
7133         /* Unfortunately, we have to delay before the PCI read back.
7134          * Some 575X chips even will not respond to a PCI cfg access
7135          * when the reset command is given to the chip.
7136          *
7137          * How do these hardware designers expect things to work
7138          * properly if the PCI write is posted for a long period
7139          * of time?  It is always necessary to have some method by
7140          * which a register read back can occur to push the write
7141          * out which does the reset.
7142          *
7143          * For most tg3 variants the trick below was working.
7144          * Ho hum...
7145          */
7146         udelay(120);
7147
7148         /* Flush PCI posted writes.  The normal MMIO registers
7149          * are inaccessible at this time so this is the only
7150          * way to make this reliably (actually, this is no longer
7151          * the case, see above).  I tried to use indirect
7152          * register read/write but this upset some 5701 variants.
7153          */
7154         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7155
7156         udelay(120);
7157
7158         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7159                 u16 val16;
7160
7161                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7162                         int i;
7163                         u32 cfg_val;
7164
7165                         /* Wait for link training to complete.  */
7166                         for (i = 0; i < 5000; i++)
7167                                 udelay(100);
7168
7169                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7170                         pci_write_config_dword(tp->pdev, 0xc4,
7171                                                cfg_val | (1 << 15));
7172                 }
7173
7174                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7175                 pci_read_config_word(tp->pdev,
7176                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7177                                      &val16);
7178                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7179                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7180                 /*
7181                  * Older PCIe devices only support the 128 byte
7182                  * MPS setting.  Enforce the restriction.
7183                  */
7184                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7185                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7186                 pci_write_config_word(tp->pdev,
7187                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7188                                       val16);
7189
7190                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
7191
7192                 /* Clear error status */
7193                 pci_write_config_word(tp->pdev,
7194                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7195                                       PCI_EXP_DEVSTA_CED |
7196                                       PCI_EXP_DEVSTA_NFED |
7197                                       PCI_EXP_DEVSTA_FED |
7198                                       PCI_EXP_DEVSTA_URD);
7199         }
7200
7201         tg3_restore_pci_state(tp);
7202
7203         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7204
7205         val = 0;
7206         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7207                 val = tr32(MEMARB_MODE);
7208         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7209
7210         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7211                 tg3_stop_fw(tp);
7212                 tw32(0x5000, 0x400);
7213         }
7214
7215         tw32(GRC_MODE, tp->grc_mode);
7216
7217         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7218                 val = tr32(0xc4);
7219
7220                 tw32(0xc4, val | (1 << 15));
7221         }
7222
7223         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7224             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7225                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7226                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7227                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7228                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7229         }
7230
7231         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7232                 tp->mac_mode = MAC_MODE_APE_TX_EN |
7233                                MAC_MODE_APE_RX_EN |
7234                                MAC_MODE_TDE_ENABLE;
7235
7236         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7237                 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
7238                 val = tp->mac_mode;
7239         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7240                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
7241                 val = tp->mac_mode;
7242         } else
7243                 val = 0;
7244
7245         tw32_f(MAC_MODE, val);
7246         udelay(40);
7247
7248         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7249
7250         err = tg3_poll_fw(tp);
7251         if (err)
7252                 return err;
7253
7254         tg3_mdio_start(tp);
7255
7256         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7257             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7258             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7259             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7260                 val = tr32(0x7c00);
7261
7262                 tw32(0x7c00, val | (1 << 25));
7263         }
7264
7265         /* Reprobe ASF enable state.  */
7266         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7267         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7268         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7269         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7270                 u32 nic_cfg;
7271
7272                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7273                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7274                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7275                         tp->last_event_jiffies = jiffies;
7276                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7277                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7278                 }
7279         }
7280
7281         return 0;
7282 }
7283
7284 /* tp->lock is held. */
7285 static void tg3_stop_fw(struct tg3 *tp)
7286 {
7287         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7288            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7289                 /* Wait for RX cpu to ACK the previous event. */
7290                 tg3_wait_for_event_ack(tp);
7291
7292                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7293
7294                 tg3_generate_fw_event(tp);
7295
7296                 /* Wait for RX cpu to ACK this event. */
7297                 tg3_wait_for_event_ack(tp);
7298         }
7299 }
7300
7301 /* tp->lock is held. */
7302 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7303 {
7304         int err;
7305
7306         tg3_stop_fw(tp);
7307
7308         tg3_write_sig_pre_reset(tp, kind);
7309
7310         tg3_abort_hw(tp, silent);
7311         err = tg3_chip_reset(tp);
7312
7313         __tg3_set_mac_addr(tp, 0);
7314
7315         tg3_write_sig_legacy(tp, kind);
7316         tg3_write_sig_post_reset(tp, kind);
7317
7318         if (err)
7319                 return err;
7320
7321         return 0;
7322 }
7323
7324 #define RX_CPU_SCRATCH_BASE     0x30000
7325 #define RX_CPU_SCRATCH_SIZE     0x04000
7326 #define TX_CPU_SCRATCH_BASE     0x34000
7327 #define TX_CPU_SCRATCH_SIZE     0x04000
7328
7329 /* tp->lock is held. */
7330 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7331 {
7332         int i;
7333
7334         BUG_ON(offset == TX_CPU_BASE &&
7335             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7336
7337         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7338                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7339
7340                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7341                 return 0;
7342         }
7343         if (offset == RX_CPU_BASE) {
7344                 for (i = 0; i < 10000; i++) {
7345                         tw32(offset + CPU_STATE, 0xffffffff);
7346                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7347                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7348                                 break;
7349                 }
7350
7351                 tw32(offset + CPU_STATE, 0xffffffff);
7352                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7353                 udelay(10);
7354         } else {
7355                 for (i = 0; i < 10000; i++) {
7356                         tw32(offset + CPU_STATE, 0xffffffff);
7357                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7358                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7359                                 break;
7360                 }
7361         }
7362
7363         if (i >= 10000) {
7364                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7365                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7366                 return -ENODEV;
7367         }
7368
7369         /* Clear firmware's nvram arbitration. */
7370         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7371                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7372         return 0;
7373 }
7374
7375 struct fw_info {
7376         unsigned int fw_base;
7377         unsigned int fw_len;
7378         const __be32 *fw_data;
7379 };
7380
7381 /* tp->lock is held. */
7382 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7383                                  int cpu_scratch_size, struct fw_info *info)
7384 {
7385         int err, lock_err, i;
7386         void (*write_op)(struct tg3 *, u32, u32);
7387
7388         if (cpu_base == TX_CPU_BASE &&
7389             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7390                 netdev_err(tp->dev,
7391                            "%s: Trying to load TX cpu firmware which is 5705\n",
7392                            __func__);
7393                 return -EINVAL;
7394         }
7395
7396         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7397                 write_op = tg3_write_mem;
7398         else
7399                 write_op = tg3_write_indirect_reg32;
7400
7401         /* It is possible that bootcode is still loading at this point.
7402          * Get the nvram lock first before halting the cpu.
7403          */
7404         lock_err = tg3_nvram_lock(tp);
7405         err = tg3_halt_cpu(tp, cpu_base);
7406         if (!lock_err)
7407                 tg3_nvram_unlock(tp);
7408         if (err)
7409                 goto out;
7410
7411         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7412                 write_op(tp, cpu_scratch_base + i, 0);
7413         tw32(cpu_base + CPU_STATE, 0xffffffff);
7414         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7415         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7416                 write_op(tp, (cpu_scratch_base +
7417                               (info->fw_base & 0xffff) +
7418                               (i * sizeof(u32))),
7419                               be32_to_cpu(info->fw_data[i]));
7420
7421         err = 0;
7422
7423 out:
7424         return err;
7425 }
7426
7427 /* tp->lock is held. */
7428 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7429 {
7430         struct fw_info info;
7431         const __be32 *fw_data;
7432         int err, i;
7433
7434         fw_data = (void *)tp->fw->data;
7435
7436         /* Firmware blob starts with version numbers, followed by
7437            start address and length. We are setting complete length.
7438            length = end_address_of_bss - start_address_of_text.
7439            Remainder is the blob to be loaded contiguously
7440            from start address. */
7441
7442         info.fw_base = be32_to_cpu(fw_data[1]);
7443         info.fw_len = tp->fw->size - 12;
7444         info.fw_data = &fw_data[3];
7445
7446         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7447                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7448                                     &info);
7449         if (err)
7450                 return err;
7451
7452         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7453                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7454                                     &info);
7455         if (err)
7456                 return err;
7457
7458         /* Now startup only the RX cpu. */
7459         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7460         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7461
7462         for (i = 0; i < 5; i++) {
7463                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7464                         break;
7465                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7466                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7467                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7468                 udelay(1000);
7469         }
7470         if (i >= 5) {
7471                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7472                            "should be %08x\n", __func__,
7473                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7474                 return -ENODEV;
7475         }
7476         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7477         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7478
7479         return 0;
7480 }
7481
7482 /* 5705 needs a special version of the TSO firmware.  */
7483
7484 /* tp->lock is held. */
7485 static int tg3_load_tso_firmware(struct tg3 *tp)
7486 {
7487         struct fw_info info;
7488         const __be32 *fw_data;
7489         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7490         int err, i;
7491
7492         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7493                 return 0;
7494
7495         fw_data = (void *)tp->fw->data;
7496
7497         /* Firmware blob starts with version numbers, followed by
7498            start address and length. We are setting complete length.
7499            length = end_address_of_bss - start_address_of_text.
7500            Remainder is the blob to be loaded contiguously
7501            from start address. */
7502
7503         info.fw_base = be32_to_cpu(fw_data[1]);
7504         cpu_scratch_size = tp->fw_len;
7505         info.fw_len = tp->fw->size - 12;
7506         info.fw_data = &fw_data[3];
7507
7508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7509                 cpu_base = RX_CPU_BASE;
7510                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7511         } else {
7512                 cpu_base = TX_CPU_BASE;
7513                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7514                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7515         }
7516
7517         err = tg3_load_firmware_cpu(tp, cpu_base,
7518                                     cpu_scratch_base, cpu_scratch_size,
7519                                     &info);
7520         if (err)
7521                 return err;
7522
7523         /* Now startup the cpu. */
7524         tw32(cpu_base + CPU_STATE, 0xffffffff);
7525         tw32_f(cpu_base + CPU_PC, info.fw_base);
7526
7527         for (i = 0; i < 5; i++) {
7528                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7529                         break;
7530                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7531                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7532                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7533                 udelay(1000);
7534         }
7535         if (i >= 5) {
7536                 netdev_err(tp->dev,
7537                            "%s fails to set CPU PC, is %08x should be %08x\n",
7538                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7539                 return -ENODEV;
7540         }
7541         tw32(cpu_base + CPU_STATE, 0xffffffff);
7542         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7543         return 0;
7544 }
7545
7546
7547 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7548 {
7549         struct tg3 *tp = netdev_priv(dev);
7550         struct sockaddr *addr = p;
7551         int err = 0, skip_mac_1 = 0;
7552
7553         if (!is_valid_ether_addr(addr->sa_data))
7554                 return -EINVAL;
7555
7556         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7557
7558         if (!netif_running(dev))
7559                 return 0;
7560
7561         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7562                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7563
7564                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7565                 addr0_low = tr32(MAC_ADDR_0_LOW);
7566                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7567                 addr1_low = tr32(MAC_ADDR_1_LOW);
7568
7569                 /* Skip MAC addr 1 if ASF is using it. */
7570                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7571                     !(addr1_high == 0 && addr1_low == 0))
7572                         skip_mac_1 = 1;
7573         }
7574         spin_lock_bh(&tp->lock);
7575         __tg3_set_mac_addr(tp, skip_mac_1);
7576         spin_unlock_bh(&tp->lock);
7577
7578         return err;
7579 }
7580
7581 /* tp->lock is held. */
7582 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7583                            dma_addr_t mapping, u32 maxlen_flags,
7584                            u32 nic_addr)
7585 {
7586         tg3_write_mem(tp,
7587                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7588                       ((u64) mapping >> 32));
7589         tg3_write_mem(tp,
7590                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7591                       ((u64) mapping & 0xffffffff));
7592         tg3_write_mem(tp,
7593                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7594                        maxlen_flags);
7595
7596         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7597                 tg3_write_mem(tp,
7598                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7599                               nic_addr);
7600 }
7601
7602 static void __tg3_set_rx_mode(struct net_device *);
7603 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7604 {
7605         int i;
7606
7607         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7608                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7609                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7610                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7611         } else {
7612                 tw32(HOSTCC_TXCOL_TICKS, 0);
7613                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7614                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7615         }
7616
7617         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7618                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7619                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7620                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7621         } else {
7622                 tw32(HOSTCC_RXCOL_TICKS, 0);
7623                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7624                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7625         }
7626
7627         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7628                 u32 val = ec->stats_block_coalesce_usecs;
7629
7630                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7631                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7632
7633                 if (!netif_carrier_ok(tp->dev))
7634                         val = 0;
7635
7636                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7637         }
7638
7639         for (i = 0; i < tp->irq_cnt - 1; i++) {
7640                 u32 reg;
7641
7642                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7643                 tw32(reg, ec->rx_coalesce_usecs);
7644                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7645                 tw32(reg, ec->rx_max_coalesced_frames);
7646                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7647                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7648
7649                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7650                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7651                         tw32(reg, ec->tx_coalesce_usecs);
7652                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7653                         tw32(reg, ec->tx_max_coalesced_frames);
7654                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7655                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7656                 }
7657         }
7658
7659         for (; i < tp->irq_max - 1; i++) {
7660                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7661                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7662                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7663
7664                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7665                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7666                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7667                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7668                 }
7669         }
7670 }
7671
7672 /* tp->lock is held. */
7673 static void tg3_rings_reset(struct tg3 *tp)
7674 {
7675         int i;
7676         u32 stblk, txrcb, rxrcb, limit;
7677         struct tg3_napi *tnapi = &tp->napi[0];
7678
7679         /* Disable all transmit rings but the first. */
7680         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7681                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7682         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7683                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7684                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7685         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7686                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7687         else
7688                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7689
7690         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7691              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7692                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7693                               BDINFO_FLAGS_DISABLED);
7694
7695
7696         /* Disable all receive return rings but the first. */
7697         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7698             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7699                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7700         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7701                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7702         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7703                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7704                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7705         else
7706                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7707
7708         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7709              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7710                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7711                               BDINFO_FLAGS_DISABLED);
7712
7713         /* Disable interrupts */
7714         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7715
7716         /* Zero mailbox registers. */
7717         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7718                 for (i = 1; i < tp->irq_max; i++) {
7719                         tp->napi[i].tx_prod = 0;
7720                         tp->napi[i].tx_cons = 0;
7721                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7722                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7723                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7724                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7725                 }
7726                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7727                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7728         } else {
7729                 tp->napi[0].tx_prod = 0;
7730                 tp->napi[0].tx_cons = 0;
7731                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7732                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7733         }
7734
7735         /* Make sure the NIC-based send BD rings are disabled. */
7736         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7737                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7738                 for (i = 0; i < 16; i++)
7739                         tw32_tx_mbox(mbox + i * 8, 0);
7740         }
7741
7742         txrcb = NIC_SRAM_SEND_RCB;
7743         rxrcb = NIC_SRAM_RCV_RET_RCB;
7744
7745         /* Clear status block in ram. */
7746         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7747
7748         /* Set status block DMA address */
7749         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7750              ((u64) tnapi->status_mapping >> 32));
7751         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7752              ((u64) tnapi->status_mapping & 0xffffffff));
7753
7754         if (tnapi->tx_ring) {
7755                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7756                                (TG3_TX_RING_SIZE <<
7757                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7758                                NIC_SRAM_TX_BUFFER_DESC);
7759                 txrcb += TG3_BDINFO_SIZE;
7760         }
7761
7762         if (tnapi->rx_rcb) {
7763                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7764                                (tp->rx_ret_ring_mask + 1) <<
7765                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7766                 rxrcb += TG3_BDINFO_SIZE;
7767         }
7768
7769         stblk = HOSTCC_STATBLCK_RING1;
7770
7771         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7772                 u64 mapping = (u64)tnapi->status_mapping;
7773                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7774                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7775
7776                 /* Clear status block in ram. */
7777                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7778
7779                 if (tnapi->tx_ring) {
7780                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7781                                        (TG3_TX_RING_SIZE <<
7782                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7783                                        NIC_SRAM_TX_BUFFER_DESC);
7784                         txrcb += TG3_BDINFO_SIZE;
7785                 }
7786
7787                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7788                                ((tp->rx_ret_ring_mask + 1) <<
7789                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7790
7791                 stblk += 8;
7792                 rxrcb += TG3_BDINFO_SIZE;
7793         }
7794 }
7795
7796 /* tp->lock is held. */
7797 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7798 {
7799         u32 val, rdmac_mode;
7800         int i, err, limit;
7801         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7802
7803         tg3_disable_ints(tp);
7804
7805         tg3_stop_fw(tp);
7806
7807         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7808
7809         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7810                 tg3_abort_hw(tp, 1);
7811
7812         if (reset_phy)
7813                 tg3_phy_reset(tp);
7814
7815         err = tg3_chip_reset(tp);
7816         if (err)
7817                 return err;
7818
7819         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7820
7821         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7822                 val = tr32(TG3_CPMU_CTRL);
7823                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7824                 tw32(TG3_CPMU_CTRL, val);
7825
7826                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7827                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7828                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7829                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7830
7831                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7832                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7833                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7834                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7835
7836                 val = tr32(TG3_CPMU_HST_ACC);
7837                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7838                 val |= CPMU_HST_ACC_MACCLK_6_25;
7839                 tw32(TG3_CPMU_HST_ACC, val);
7840         }
7841
7842         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7843                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7844                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7845                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7846                 tw32(PCIE_PWR_MGMT_THRESH, val);
7847
7848                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7849                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7850
7851                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7852
7853                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7854                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7855         }
7856
7857         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7858                 u32 grc_mode = tr32(GRC_MODE);
7859
7860                 /* Access the lower 1K of PL PCIE block registers. */
7861                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7862                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7863
7864                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7865                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7866                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7867
7868                 tw32(GRC_MODE, grc_mode);
7869         }
7870
7871         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7872                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7873                         u32 grc_mode = tr32(GRC_MODE);
7874
7875                         /* Access the lower 1K of PL PCIE block registers. */
7876                         val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7877                         tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7878
7879                         val = tr32(TG3_PCIE_TLDLPL_PORT +
7880                                    TG3_PCIE_PL_LO_PHYCTL5);
7881                         tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7882                              val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7883
7884                         tw32(GRC_MODE, grc_mode);
7885                 }
7886
7887                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7888                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7889                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7890                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7891         }
7892
7893         /* Enable MAC control of LPI */
7894         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7895                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7896                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7897                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7898
7899                 tw32_f(TG3_CPMU_EEE_CTRL,
7900                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7901
7902                 tw32_f(TG3_CPMU_EEE_MODE,
7903                        TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7904                        TG3_CPMU_EEEMD_LPI_IN_TX |
7905                        TG3_CPMU_EEEMD_LPI_IN_RX |
7906                        TG3_CPMU_EEEMD_EEE_ENABLE);
7907         }
7908
7909         /* This works around an issue with Athlon chipsets on
7910          * B3 tigon3 silicon.  This bit has no effect on any
7911          * other revision.  But do not set this on PCI Express
7912          * chips and don't even touch the clocks if the CPMU is present.
7913          */
7914         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7915                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7916                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7917                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7918         }
7919
7920         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7921             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7922                 val = tr32(TG3PCI_PCISTATE);
7923                 val |= PCISTATE_RETRY_SAME_DMA;
7924                 tw32(TG3PCI_PCISTATE, val);
7925         }
7926
7927         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7928                 /* Allow reads and writes to the
7929                  * APE register and memory space.
7930                  */
7931                 val = tr32(TG3PCI_PCISTATE);
7932                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7933                        PCISTATE_ALLOW_APE_SHMEM_WR |
7934                        PCISTATE_ALLOW_APE_PSPACE_WR;
7935                 tw32(TG3PCI_PCISTATE, val);
7936         }
7937
7938         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7939                 /* Enable some hw fixes.  */
7940                 val = tr32(TG3PCI_MSI_DATA);
7941                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7942                 tw32(TG3PCI_MSI_DATA, val);
7943         }
7944
7945         /* Descriptor ring init may make accesses to the
7946          * NIC SRAM area to setup the TX descriptors, so we
7947          * can only do this after the hardware has been
7948          * successfully reset.
7949          */
7950         err = tg3_init_rings(tp);
7951         if (err)
7952                 return err;
7953
7954         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7955                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7956                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7957                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7958                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7959                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7960         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7961                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7962                 /* This value is determined during the probe time DMA
7963                  * engine test, tg3_test_dma.
7964                  */
7965                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7966         }
7967
7968         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7969                           GRC_MODE_4X_NIC_SEND_RINGS |
7970                           GRC_MODE_NO_TX_PHDR_CSUM |
7971                           GRC_MODE_NO_RX_PHDR_CSUM);
7972         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7973
7974         /* Pseudo-header checksum is done by hardware logic and not
7975          * the offload processers, so make the chip do the pseudo-
7976          * header checksums on receive.  For transmit it is more
7977          * convenient to do the pseudo-header checksum in software
7978          * as Linux does that on transmit for us in all cases.
7979          */
7980         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7981
7982         tw32(GRC_MODE,
7983              tp->grc_mode |
7984              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7985
7986         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7987         val = tr32(GRC_MISC_CFG);
7988         val &= ~0xff;
7989         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7990         tw32(GRC_MISC_CFG, val);
7991
7992         /* Initialize MBUF/DESC pool. */
7993         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7994                 /* Do nothing.  */
7995         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7996                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7997                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7998                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7999                 else
8000                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
8001                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
8002                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
8003         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8004                 int fw_len;
8005
8006                 fw_len = tp->fw_len;
8007                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
8008                 tw32(BUFMGR_MB_POOL_ADDR,
8009                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
8010                 tw32(BUFMGR_MB_POOL_SIZE,
8011                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8012         }
8013
8014         if (tp->dev->mtu <= ETH_DATA_LEN) {
8015                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8016                      tp->bufmgr_config.mbuf_read_dma_low_water);
8017                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8018                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8019                 tw32(BUFMGR_MB_HIGH_WATER,
8020                      tp->bufmgr_config.mbuf_high_water);
8021         } else {
8022                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8023                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8024                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8025                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8026                 tw32(BUFMGR_MB_HIGH_WATER,
8027                      tp->bufmgr_config.mbuf_high_water_jumbo);
8028         }
8029         tw32(BUFMGR_DMA_LOW_WATER,
8030              tp->bufmgr_config.dma_low_water);
8031         tw32(BUFMGR_DMA_HIGH_WATER,
8032              tp->bufmgr_config.dma_high_water);
8033
8034         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8035         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8036                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8037         tw32(BUFMGR_MODE, val);
8038         for (i = 0; i < 2000; i++) {
8039                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8040                         break;
8041                 udelay(10);
8042         }
8043         if (i >= 2000) {
8044                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8045                 return -ENODEV;
8046         }
8047
8048         /* Setup replenish threshold. */
8049         val = tp->rx_pending / 8;
8050         if (val == 0)
8051                 val = 1;
8052         else if (val > tp->rx_std_max_post)
8053                 val = tp->rx_std_max_post;
8054         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8055                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8056                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8057
8058                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8059                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8060         }
8061
8062         tw32(RCVBDI_STD_THRESH, val);
8063
8064         /* Initialize TG3_BDINFO's at:
8065          *  RCVDBDI_STD_BD:     standard eth size rx ring
8066          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8067          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8068          *
8069          * like so:
8070          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8071          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8072          *                              ring attribute flags
8073          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8074          *
8075          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8076          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8077          *
8078          * The size of each ring is fixed in the firmware, but the location is
8079          * configurable.
8080          */
8081         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8082              ((u64) tpr->rx_std_mapping >> 32));
8083         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8084              ((u64) tpr->rx_std_mapping & 0xffffffff));
8085         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8086             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8087                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8088                      NIC_SRAM_RX_BUFFER_DESC);
8089
8090         /* Disable the mini ring */
8091         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8092                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8093                      BDINFO_FLAGS_DISABLED);
8094
8095         /* Program the jumbo buffer descriptor ring control
8096          * blocks on those devices that have them.
8097          */
8098         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8099             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8100                 /* Setup replenish threshold. */
8101                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8102
8103                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8104                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8105                              ((u64) tpr->rx_jmb_mapping >> 32));
8106                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8107                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8108                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8109                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8110                              BDINFO_FLAGS_USE_EXT_RECV);
8111                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8112                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8113                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8114                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8115                 } else {
8116                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8117                              BDINFO_FLAGS_DISABLED);
8118                 }
8119
8120                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8122                                 val = RX_STD_MAX_SIZE_5705;
8123                         else
8124                                 val = RX_STD_MAX_SIZE_5717;
8125                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8126                         val |= (TG3_RX_STD_DMA_SZ << 2);
8127                 } else
8128                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8129         } else
8130                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8131
8132         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8133
8134         tpr->rx_std_prod_idx = tp->rx_pending;
8135         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8136
8137         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8138                           tp->rx_jumbo_pending : 0;
8139         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8140
8141         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8142                 tw32(STD_REPLENISH_LWM, 32);
8143                 tw32(JMB_REPLENISH_LWM, 16);
8144         }
8145
8146         tg3_rings_reset(tp);
8147
8148         /* Initialize MAC address and backoff seed. */
8149         __tg3_set_mac_addr(tp, 0);
8150
8151         /* MTU + ethernet header + FCS + optional VLAN tag */
8152         tw32(MAC_RX_MTU_SIZE,
8153              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8154
8155         /* The slot time is changed by tg3_setup_phy if we
8156          * run at gigabit with half duplex.
8157          */
8158         tw32(MAC_TX_LENGTHS,
8159              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8160              (6 << TX_LENGTHS_IPG_SHIFT) |
8161              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8162
8163         /* Receive rules. */
8164         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8165         tw32(RCVLPC_CONFIG, 0x0181);
8166
8167         /* Calculate RDMAC_MODE setting early, we need it to determine
8168          * the RCVLPC_STATE_ENABLE mask.
8169          */
8170         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8171                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8172                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8173                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8174                       RDMAC_MODE_LNGREAD_ENAB);
8175
8176         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
8177                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8178
8179         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8180             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8181             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8182                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8183                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8184                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8185
8186         /* If statement applies to 5705 and 5750 PCI devices only */
8187         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8188              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8189             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8190                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8191                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8192                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8193                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8194                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8195                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8196                 }
8197         }
8198
8199         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8200                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8201
8202         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8203                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8204
8205         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8206             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8207             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8208                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8209
8210         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8211             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8212             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8214             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8215                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8216                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8217                         val &= ~TG3_RDMA_RSRVCTRL_TXMRGN_MASK;
8218                         val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B;
8219                 }
8220                 tw32(TG3_RDMA_RSRVCTRL_REG,
8221                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8222         }
8223
8224         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8225                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8226                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8227                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8228                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8229         }
8230
8231         /* Receive/send statistics. */
8232         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8233                 val = tr32(RCVLPC_STATS_ENABLE);
8234                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8235                 tw32(RCVLPC_STATS_ENABLE, val);
8236         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8237                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8238                 val = tr32(RCVLPC_STATS_ENABLE);
8239                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8240                 tw32(RCVLPC_STATS_ENABLE, val);
8241         } else {
8242                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8243         }
8244         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8245         tw32(SNDDATAI_STATSENAB, 0xffffff);
8246         tw32(SNDDATAI_STATSCTRL,
8247              (SNDDATAI_SCTRL_ENABLE |
8248               SNDDATAI_SCTRL_FASTUPD));
8249
8250         /* Setup host coalescing engine. */
8251         tw32(HOSTCC_MODE, 0);
8252         for (i = 0; i < 2000; i++) {
8253                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8254                         break;
8255                 udelay(10);
8256         }
8257
8258         __tg3_set_coalesce(tp, &tp->coal);
8259
8260         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8261                 /* Status/statistics block address.  See tg3_timer,
8262                  * the tg3_periodic_fetch_stats call there, and
8263                  * tg3_get_stats to see how this works for 5705/5750 chips.
8264                  */
8265                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8266                      ((u64) tp->stats_mapping >> 32));
8267                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8268                      ((u64) tp->stats_mapping & 0xffffffff));
8269                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8270
8271                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8272
8273                 /* Clear statistics and status block memory areas */
8274                 for (i = NIC_SRAM_STATS_BLK;
8275                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8276                      i += sizeof(u32)) {
8277                         tg3_write_mem(tp, i, 0);
8278                         udelay(40);
8279                 }
8280         }
8281
8282         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8283
8284         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8285         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8286         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8287                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8288
8289         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8290                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8291                 /* reset to prevent losing 1st rx packet intermittently */
8292                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8293                 udelay(10);
8294         }
8295
8296         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8297                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8298         else
8299                 tp->mac_mode = 0;
8300         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8301                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8302         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8303             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8304             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8305                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8306         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8307         udelay(40);
8308
8309         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8310          * If TG3_FLG2_IS_NIC is zero, we should read the
8311          * register to preserve the GPIO settings for LOMs. The GPIOs,
8312          * whether used as inputs or outputs, are set by boot code after
8313          * reset.
8314          */
8315         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8316                 u32 gpio_mask;
8317
8318                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8319                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8320                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8321
8322                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8323                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8324                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8325
8326                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8327                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8328
8329                 tp->grc_local_ctrl &= ~gpio_mask;
8330                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8331
8332                 /* GPIO1 must be driven high for eeprom write protect */
8333                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8334                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8335                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8336         }
8337         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8338         udelay(100);
8339
8340         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8341                 val = tr32(MSGINT_MODE);
8342                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8343                 tw32(MSGINT_MODE, val);
8344         }
8345
8346         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8347                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8348                 udelay(40);
8349         }
8350
8351         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8352                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8353                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8354                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8355                WDMAC_MODE_LNGREAD_ENAB);
8356
8357         /* If statement applies to 5705 and 5750 PCI devices only */
8358         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8359              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8360             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8361                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8362                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8363                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8364                         /* nothing */
8365                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8366                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8367                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8368                         val |= WDMAC_MODE_RX_ACCEL;
8369                 }
8370         }
8371
8372         /* Enable host coalescing bug fix */
8373         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8374                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8375
8376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8377                 val |= WDMAC_MODE_BURST_ALL_DATA;
8378
8379         tw32_f(WDMAC_MODE, val);
8380         udelay(40);
8381
8382         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8383                 u16 pcix_cmd;
8384
8385                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8386                                      &pcix_cmd);
8387                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8388                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8389                         pcix_cmd |= PCI_X_CMD_READ_2K;
8390                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8391                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8392                         pcix_cmd |= PCI_X_CMD_READ_2K;
8393                 }
8394                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8395                                       pcix_cmd);
8396         }
8397
8398         tw32_f(RDMAC_MODE, rdmac_mode);
8399         udelay(40);
8400
8401         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8402         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8403                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8404
8405         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8406                 tw32(SNDDATAC_MODE,
8407                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8408         else
8409                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8410
8411         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8412         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8413         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8414         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8415             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8416                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8417         tw32(RCVDBDI_MODE, val);
8418         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8419         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8420                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8421         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8422         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8423                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8424         tw32(SNDBDI_MODE, val);
8425         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8426
8427         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8428                 err = tg3_load_5701_a0_firmware_fix(tp);
8429                 if (err)
8430                         return err;
8431         }
8432
8433         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8434                 err = tg3_load_tso_firmware(tp);
8435                 if (err)
8436                         return err;
8437         }
8438
8439         tp->tx_mode = TX_MODE_ENABLE;
8440         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8441             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8442                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8443         tw32_f(MAC_TX_MODE, tp->tx_mode);
8444         udelay(100);
8445
8446         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8447                 u32 reg = MAC_RSS_INDIR_TBL_0;
8448                 u8 *ent = (u8 *)&val;
8449
8450                 /* Setup the indirection table */
8451                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8452                         int idx = i % sizeof(val);
8453
8454                         ent[idx] = i % (tp->irq_cnt - 1);
8455                         if (idx == sizeof(val) - 1) {
8456                                 tw32(reg, val);
8457                                 reg += 4;
8458                         }
8459                 }
8460
8461                 /* Setup the "secret" hash key. */
8462                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8463                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8464                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8465                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8466                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8467                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8468                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8469                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8470                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8471                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8472         }
8473
8474         tp->rx_mode = RX_MODE_ENABLE;
8475         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8476                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8477
8478         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8479                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8480                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8481                                RX_MODE_RSS_IPV6_HASH_EN |
8482                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8483                                RX_MODE_RSS_IPV4_HASH_EN |
8484                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8485
8486         tw32_f(MAC_RX_MODE, tp->rx_mode);
8487         udelay(10);
8488
8489         tw32(MAC_LED_CTRL, tp->led_ctrl);
8490
8491         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8492         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8493                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8494                 udelay(10);
8495         }
8496         tw32_f(MAC_RX_MODE, tp->rx_mode);
8497         udelay(10);
8498
8499         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8500                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8501                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8502                         /* Set drive transmission level to 1.2V  */
8503                         /* only if the signal pre-emphasis bit is not set  */
8504                         val = tr32(MAC_SERDES_CFG);
8505                         val &= 0xfffff000;
8506                         val |= 0x880;
8507                         tw32(MAC_SERDES_CFG, val);
8508                 }
8509                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8510                         tw32(MAC_SERDES_CFG, 0x616000);
8511         }
8512
8513         /* Prevent chip from dropping frames when flow control
8514          * is enabled.
8515          */
8516         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8517                 val = 1;
8518         else
8519                 val = 2;
8520         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8521
8522         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8523             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8524                 /* Use hardware link auto-negotiation */
8525                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8526         }
8527
8528         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8529             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8530                 u32 tmp;
8531
8532                 tmp = tr32(SERDES_RX_CTRL);
8533                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8534                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8535                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8536                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8537         }
8538
8539         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8540                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8541                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8542                         tp->link_config.speed = tp->link_config.orig_speed;
8543                         tp->link_config.duplex = tp->link_config.orig_duplex;
8544                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8545                 }
8546
8547                 err = tg3_setup_phy(tp, 0);
8548                 if (err)
8549                         return err;
8550
8551                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8552                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8553                         u32 tmp;
8554
8555                         /* Clear CRC stats. */
8556                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8557                                 tg3_writephy(tp, MII_TG3_TEST1,
8558                                              tmp | MII_TG3_TEST1_CRC_EN);
8559                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8560                         }
8561                 }
8562         }
8563
8564         __tg3_set_rx_mode(tp->dev);
8565
8566         /* Initialize receive rules. */
8567         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8568         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8569         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8570         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8571
8572         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8573             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8574                 limit = 8;
8575         else
8576                 limit = 16;
8577         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8578                 limit -= 4;
8579         switch (limit) {
8580         case 16:
8581                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8582         case 15:
8583                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8584         case 14:
8585                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8586         case 13:
8587                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8588         case 12:
8589                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8590         case 11:
8591                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8592         case 10:
8593                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8594         case 9:
8595                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8596         case 8:
8597                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8598         case 7:
8599                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8600         case 6:
8601                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8602         case 5:
8603                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8604         case 4:
8605                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8606         case 3:
8607                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8608         case 2:
8609         case 1:
8610
8611         default:
8612                 break;
8613         }
8614
8615         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8616                 /* Write our heartbeat update interval to APE. */
8617                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8618                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8619
8620         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8621
8622         return 0;
8623 }
8624
8625 /* Called at device open time to get the chip ready for
8626  * packet processing.  Invoked with tp->lock held.
8627  */
8628 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8629 {
8630         tg3_switch_clocks(tp);
8631
8632         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8633
8634         return tg3_reset_hw(tp, reset_phy);
8635 }
8636
8637 #define TG3_STAT_ADD32(PSTAT, REG) \
8638 do {    u32 __val = tr32(REG); \
8639         (PSTAT)->low += __val; \
8640         if ((PSTAT)->low < __val) \
8641                 (PSTAT)->high += 1; \
8642 } while (0)
8643
8644 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8645 {
8646         struct tg3_hw_stats *sp = tp->hw_stats;
8647
8648         if (!netif_carrier_ok(tp->dev))
8649                 return;
8650
8651         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8652         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8653         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8654         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8655         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8656         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8657         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8658         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8659         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8660         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8661         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8662         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8663         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8664
8665         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8666         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8667         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8668         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8669         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8670         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8671         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8672         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8673         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8674         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8675         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8676         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8677         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8678         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8679
8680         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8681         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8682         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8683 }
8684
8685 static void tg3_timer(unsigned long __opaque)
8686 {
8687         struct tg3 *tp = (struct tg3 *) __opaque;
8688
8689         if (tp->irq_sync)
8690                 goto restart_timer;
8691
8692         spin_lock(&tp->lock);
8693
8694         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8695                 /* All of this garbage is because when using non-tagged
8696                  * IRQ status the mailbox/status_block protocol the chip
8697                  * uses with the cpu is race prone.
8698                  */
8699                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8700                         tw32(GRC_LOCAL_CTRL,
8701                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8702                 } else {
8703                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8704                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8705                 }
8706
8707                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8708                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8709                         spin_unlock(&tp->lock);
8710                         schedule_work(&tp->reset_task);
8711                         return;
8712                 }
8713         }
8714
8715         /* This part only runs once per second. */
8716         if (!--tp->timer_counter) {
8717                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8718                         tg3_periodic_fetch_stats(tp);
8719
8720                 if (tp->setlpicnt && !--tp->setlpicnt) {
8721                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8722                         tw32(TG3_CPMU_EEE_MODE,
8723                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8724                 }
8725
8726                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8727                         u32 mac_stat;
8728                         int phy_event;
8729
8730                         mac_stat = tr32(MAC_STATUS);
8731
8732                         phy_event = 0;
8733                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8734                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8735                                         phy_event = 1;
8736                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8737                                 phy_event = 1;
8738
8739                         if (phy_event)
8740                                 tg3_setup_phy(tp, 0);
8741                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8742                         u32 mac_stat = tr32(MAC_STATUS);
8743                         int need_setup = 0;
8744
8745                         if (netif_carrier_ok(tp->dev) &&
8746                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8747                                 need_setup = 1;
8748                         }
8749                         if (!netif_carrier_ok(tp->dev) &&
8750                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8751                                          MAC_STATUS_SIGNAL_DET))) {
8752                                 need_setup = 1;
8753                         }
8754                         if (need_setup) {
8755                                 if (!tp->serdes_counter) {
8756                                         tw32_f(MAC_MODE,
8757                                              (tp->mac_mode &
8758                                               ~MAC_MODE_PORT_MODE_MASK));
8759                                         udelay(40);
8760                                         tw32_f(MAC_MODE, tp->mac_mode);
8761                                         udelay(40);
8762                                 }
8763                                 tg3_setup_phy(tp, 0);
8764                         }
8765                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8766                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8767                         tg3_serdes_parallel_detect(tp);
8768                 }
8769
8770                 tp->timer_counter = tp->timer_multiplier;
8771         }
8772
8773         /* Heartbeat is only sent once every 2 seconds.
8774          *
8775          * The heartbeat is to tell the ASF firmware that the host
8776          * driver is still alive.  In the event that the OS crashes,
8777          * ASF needs to reset the hardware to free up the FIFO space
8778          * that may be filled with rx packets destined for the host.
8779          * If the FIFO is full, ASF will no longer function properly.
8780          *
8781          * Unintended resets have been reported on real time kernels
8782          * where the timer doesn't run on time.  Netpoll will also have
8783          * same problem.
8784          *
8785          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8786          * to check the ring condition when the heartbeat is expiring
8787          * before doing the reset.  This will prevent most unintended
8788          * resets.
8789          */
8790         if (!--tp->asf_counter) {
8791                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8792                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8793                         tg3_wait_for_event_ack(tp);
8794
8795                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8796                                       FWCMD_NICDRV_ALIVE3);
8797                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8798                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8799                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8800
8801                         tg3_generate_fw_event(tp);
8802                 }
8803                 tp->asf_counter = tp->asf_multiplier;
8804         }
8805
8806         spin_unlock(&tp->lock);
8807
8808 restart_timer:
8809         tp->timer.expires = jiffies + tp->timer_offset;
8810         add_timer(&tp->timer);
8811 }
8812
8813 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8814 {
8815         irq_handler_t fn;
8816         unsigned long flags;
8817         char *name;
8818         struct tg3_napi *tnapi = &tp->napi[irq_num];
8819
8820         if (tp->irq_cnt == 1)
8821                 name = tp->dev->name;
8822         else {
8823                 name = &tnapi->irq_lbl[0];
8824                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8825                 name[IFNAMSIZ-1] = 0;
8826         }
8827
8828         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8829                 fn = tg3_msi;
8830                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8831                         fn = tg3_msi_1shot;
8832                 flags = IRQF_SAMPLE_RANDOM;
8833         } else {
8834                 fn = tg3_interrupt;
8835                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8836                         fn = tg3_interrupt_tagged;
8837                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8838         }
8839
8840         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8841 }
8842
8843 static int tg3_test_interrupt(struct tg3 *tp)
8844 {
8845         struct tg3_napi *tnapi = &tp->napi[0];
8846         struct net_device *dev = tp->dev;
8847         int err, i, intr_ok = 0;
8848         u32 val;
8849
8850         if (!netif_running(dev))
8851                 return -ENODEV;
8852
8853         tg3_disable_ints(tp);
8854
8855         free_irq(tnapi->irq_vec, tnapi);
8856
8857         /*
8858          * Turn off MSI one shot mode.  Otherwise this test has no
8859          * observable way to know whether the interrupt was delivered.
8860          */
8861         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8862             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8863                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8864                 tw32(MSGINT_MODE, val);
8865         }
8866
8867         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8868                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8869         if (err)
8870                 return err;
8871
8872         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8873         tg3_enable_ints(tp);
8874
8875         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8876                tnapi->coal_now);
8877
8878         for (i = 0; i < 5; i++) {
8879                 u32 int_mbox, misc_host_ctrl;
8880
8881                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8882                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8883
8884                 if ((int_mbox != 0) ||
8885                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8886                         intr_ok = 1;
8887                         break;
8888                 }
8889
8890                 msleep(10);
8891         }
8892
8893         tg3_disable_ints(tp);
8894
8895         free_irq(tnapi->irq_vec, tnapi);
8896
8897         err = tg3_request_irq(tp, 0);
8898
8899         if (err)
8900                 return err;
8901
8902         if (intr_ok) {
8903                 /* Reenable MSI one shot mode. */
8904                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8905                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8906                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8907                         tw32(MSGINT_MODE, val);
8908                 }
8909                 return 0;
8910         }
8911
8912         return -EIO;
8913 }
8914
8915 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8916  * successfully restored
8917  */
8918 static int tg3_test_msi(struct tg3 *tp)
8919 {
8920         int err;
8921         u16 pci_cmd;
8922
8923         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8924                 return 0;
8925
8926         /* Turn off SERR reporting in case MSI terminates with Master
8927          * Abort.
8928          */
8929         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8930         pci_write_config_word(tp->pdev, PCI_COMMAND,
8931                               pci_cmd & ~PCI_COMMAND_SERR);
8932
8933         err = tg3_test_interrupt(tp);
8934
8935         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8936
8937         if (!err)
8938                 return 0;
8939
8940         /* other failures */
8941         if (err != -EIO)
8942                 return err;
8943
8944         /* MSI test failed, go back to INTx mode */
8945         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8946                     "to INTx mode. Please report this failure to the PCI "
8947                     "maintainer and include system chipset information\n");
8948
8949         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8950
8951         pci_disable_msi(tp->pdev);
8952
8953         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8954         tp->napi[0].irq_vec = tp->pdev->irq;
8955
8956         err = tg3_request_irq(tp, 0);
8957         if (err)
8958                 return err;
8959
8960         /* Need to reset the chip because the MSI cycle may have terminated
8961          * with Master Abort.
8962          */
8963         tg3_full_lock(tp, 1);
8964
8965         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8966         err = tg3_init_hw(tp, 1);
8967
8968         tg3_full_unlock(tp);
8969
8970         if (err)
8971                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8972
8973         return err;
8974 }
8975
8976 static int tg3_request_firmware(struct tg3 *tp)
8977 {
8978         const __be32 *fw_data;
8979
8980         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8981                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8982                            tp->fw_needed);
8983                 return -ENOENT;
8984         }
8985
8986         fw_data = (void *)tp->fw->data;
8987
8988         /* Firmware blob starts with version numbers, followed by
8989          * start address and _full_ length including BSS sections
8990          * (which must be longer than the actual data, of course
8991          */
8992
8993         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8994         if (tp->fw_len < (tp->fw->size - 12)) {
8995                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8996                            tp->fw_len, tp->fw_needed);
8997                 release_firmware(tp->fw);
8998                 tp->fw = NULL;
8999                 return -EINVAL;
9000         }
9001
9002         /* We no longer need firmware; we have it. */
9003         tp->fw_needed = NULL;
9004         return 0;
9005 }
9006
9007 static bool tg3_enable_msix(struct tg3 *tp)
9008 {
9009         int i, rc, cpus = num_online_cpus();
9010         struct msix_entry msix_ent[tp->irq_max];
9011
9012         if (cpus == 1)
9013                 /* Just fallback to the simpler MSI mode. */
9014                 return false;
9015
9016         /*
9017          * We want as many rx rings enabled as there are cpus.
9018          * The first MSIX vector only deals with link interrupts, etc,
9019          * so we add one to the number of vectors we are requesting.
9020          */
9021         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9022
9023         for (i = 0; i < tp->irq_max; i++) {
9024                 msix_ent[i].entry  = i;
9025                 msix_ent[i].vector = 0;
9026         }
9027
9028         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9029         if (rc < 0) {
9030                 return false;
9031         } else if (rc != 0) {
9032                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9033                         return false;
9034                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9035                               tp->irq_cnt, rc);
9036                 tp->irq_cnt = rc;
9037         }
9038
9039         for (i = 0; i < tp->irq_max; i++)
9040                 tp->napi[i].irq_vec = msix_ent[i].vector;
9041
9042         netif_set_real_num_tx_queues(tp->dev, 1);
9043         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9044         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9045                 pci_disable_msix(tp->pdev);
9046                 return false;
9047         }
9048
9049         if (tp->irq_cnt > 1) {
9050                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9051                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
9052                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
9053                         netif_set_real_num_tx_queues(tp->dev, tp->irq_cnt - 1);
9054                 }
9055         }
9056
9057         return true;
9058 }
9059
9060 static void tg3_ints_init(struct tg3 *tp)
9061 {
9062         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9063             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9064                 /* All MSI supporting chips should support tagged
9065                  * status.  Assert that this is the case.
9066                  */
9067                 netdev_warn(tp->dev,
9068                             "MSI without TAGGED_STATUS? Not using MSI\n");
9069                 goto defcfg;
9070         }
9071
9072         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9073                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9074         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9075                  pci_enable_msi(tp->pdev) == 0)
9076                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9077
9078         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9079                 u32 msi_mode = tr32(MSGINT_MODE);
9080                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9081                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9082                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9083         }
9084 defcfg:
9085         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9086                 tp->irq_cnt = 1;
9087                 tp->napi[0].irq_vec = tp->pdev->irq;
9088                 netif_set_real_num_tx_queues(tp->dev, 1);
9089                 netif_set_real_num_rx_queues(tp->dev, 1);
9090         }
9091 }
9092
9093 static void tg3_ints_fini(struct tg3 *tp)
9094 {
9095         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9096                 pci_disable_msix(tp->pdev);
9097         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9098                 pci_disable_msi(tp->pdev);
9099         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9100         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9101 }
9102
9103 static int tg3_open(struct net_device *dev)
9104 {
9105         struct tg3 *tp = netdev_priv(dev);
9106         int i, err;
9107
9108         if (tp->fw_needed) {
9109                 err = tg3_request_firmware(tp);
9110                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9111                         if (err)
9112                                 return err;
9113                 } else if (err) {
9114                         netdev_warn(tp->dev, "TSO capability disabled\n");
9115                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9116                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9117                         netdev_notice(tp->dev, "TSO capability restored\n");
9118                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9119                 }
9120         }
9121
9122         netif_carrier_off(tp->dev);
9123
9124         err = tg3_set_power_state(tp, PCI_D0);
9125         if (err)
9126                 return err;
9127
9128         tg3_full_lock(tp, 0);
9129
9130         tg3_disable_ints(tp);
9131         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9132
9133         tg3_full_unlock(tp);
9134
9135         /*
9136          * Setup interrupts first so we know how
9137          * many NAPI resources to allocate
9138          */
9139         tg3_ints_init(tp);
9140
9141         /* The placement of this call is tied
9142          * to the setup and use of Host TX descriptors.
9143          */
9144         err = tg3_alloc_consistent(tp);
9145         if (err)
9146                 goto err_out1;
9147
9148         tg3_napi_init(tp);
9149
9150         tg3_napi_enable(tp);
9151
9152         for (i = 0; i < tp->irq_cnt; i++) {
9153                 struct tg3_napi *tnapi = &tp->napi[i];
9154                 err = tg3_request_irq(tp, i);
9155                 if (err) {
9156                         for (i--; i >= 0; i--)
9157                                 free_irq(tnapi->irq_vec, tnapi);
9158                         break;
9159                 }
9160         }
9161
9162         if (err)
9163                 goto err_out2;
9164
9165         tg3_full_lock(tp, 0);
9166
9167         err = tg3_init_hw(tp, 1);
9168         if (err) {
9169                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9170                 tg3_free_rings(tp);
9171         } else {
9172                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9173                         tp->timer_offset = HZ;
9174                 else
9175                         tp->timer_offset = HZ / 10;
9176
9177                 BUG_ON(tp->timer_offset > HZ);
9178                 tp->timer_counter = tp->timer_multiplier =
9179                         (HZ / tp->timer_offset);
9180                 tp->asf_counter = tp->asf_multiplier =
9181                         ((HZ / tp->timer_offset) * 2);
9182
9183                 init_timer(&tp->timer);
9184                 tp->timer.expires = jiffies + tp->timer_offset;
9185                 tp->timer.data = (unsigned long) tp;
9186                 tp->timer.function = tg3_timer;
9187         }
9188
9189         tg3_full_unlock(tp);
9190
9191         if (err)
9192                 goto err_out3;
9193
9194         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9195                 err = tg3_test_msi(tp);
9196
9197                 if (err) {
9198                         tg3_full_lock(tp, 0);
9199                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9200                         tg3_free_rings(tp);
9201                         tg3_full_unlock(tp);
9202
9203                         goto err_out2;
9204                 }
9205
9206                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9207                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9208                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9209
9210                         tw32(PCIE_TRANSACTION_CFG,
9211                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9212                 }
9213         }
9214
9215         tg3_phy_start(tp);
9216
9217         tg3_full_lock(tp, 0);
9218
9219         add_timer(&tp->timer);
9220         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9221         tg3_enable_ints(tp);
9222
9223         tg3_full_unlock(tp);
9224
9225         netif_tx_start_all_queues(dev);
9226
9227         return 0;
9228
9229 err_out3:
9230         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9231                 struct tg3_napi *tnapi = &tp->napi[i];
9232                 free_irq(tnapi->irq_vec, tnapi);
9233         }
9234
9235 err_out2:
9236         tg3_napi_disable(tp);
9237         tg3_napi_fini(tp);
9238         tg3_free_consistent(tp);
9239
9240 err_out1:
9241         tg3_ints_fini(tp);
9242         return err;
9243 }
9244
9245 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9246                                                  struct rtnl_link_stats64 *);
9247 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9248
9249 static int tg3_close(struct net_device *dev)
9250 {
9251         int i;
9252         struct tg3 *tp = netdev_priv(dev);
9253
9254         tg3_napi_disable(tp);
9255         cancel_work_sync(&tp->reset_task);
9256
9257         netif_tx_stop_all_queues(dev);
9258
9259         del_timer_sync(&tp->timer);
9260
9261         tg3_phy_stop(tp);
9262
9263         tg3_full_lock(tp, 1);
9264
9265         tg3_disable_ints(tp);
9266
9267         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9268         tg3_free_rings(tp);
9269         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9270
9271         tg3_full_unlock(tp);
9272
9273         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9274                 struct tg3_napi *tnapi = &tp->napi[i];
9275                 free_irq(tnapi->irq_vec, tnapi);
9276         }
9277
9278         tg3_ints_fini(tp);
9279
9280         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9281
9282         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9283                sizeof(tp->estats_prev));
9284
9285         tg3_napi_fini(tp);
9286
9287         tg3_free_consistent(tp);
9288
9289         tg3_set_power_state(tp, PCI_D3hot);
9290
9291         netif_carrier_off(tp->dev);
9292
9293         return 0;
9294 }
9295
9296 static inline u64 get_stat64(tg3_stat64_t *val)
9297 {
9298        return ((u64)val->high << 32) | ((u64)val->low);
9299 }
9300
9301 static u64 calc_crc_errors(struct tg3 *tp)
9302 {
9303         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9304
9305         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9306             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9307              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9308                 u32 val;
9309
9310                 spin_lock_bh(&tp->lock);
9311                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9312                         tg3_writephy(tp, MII_TG3_TEST1,
9313                                      val | MII_TG3_TEST1_CRC_EN);
9314                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9315                 } else
9316                         val = 0;
9317                 spin_unlock_bh(&tp->lock);
9318
9319                 tp->phy_crc_errors += val;
9320
9321                 return tp->phy_crc_errors;
9322         }
9323
9324         return get_stat64(&hw_stats->rx_fcs_errors);
9325 }
9326
9327 #define ESTAT_ADD(member) \
9328         estats->member =        old_estats->member + \
9329                                 get_stat64(&hw_stats->member)
9330
9331 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9332 {
9333         struct tg3_ethtool_stats *estats = &tp->estats;
9334         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9335         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9336
9337         if (!hw_stats)
9338                 return old_estats;
9339
9340         ESTAT_ADD(rx_octets);
9341         ESTAT_ADD(rx_fragments);
9342         ESTAT_ADD(rx_ucast_packets);
9343         ESTAT_ADD(rx_mcast_packets);
9344         ESTAT_ADD(rx_bcast_packets);
9345         ESTAT_ADD(rx_fcs_errors);
9346         ESTAT_ADD(rx_align_errors);
9347         ESTAT_ADD(rx_xon_pause_rcvd);
9348         ESTAT_ADD(rx_xoff_pause_rcvd);
9349         ESTAT_ADD(rx_mac_ctrl_rcvd);
9350         ESTAT_ADD(rx_xoff_entered);
9351         ESTAT_ADD(rx_frame_too_long_errors);
9352         ESTAT_ADD(rx_jabbers);
9353         ESTAT_ADD(rx_undersize_packets);
9354         ESTAT_ADD(rx_in_length_errors);
9355         ESTAT_ADD(rx_out_length_errors);
9356         ESTAT_ADD(rx_64_or_less_octet_packets);
9357         ESTAT_ADD(rx_65_to_127_octet_packets);
9358         ESTAT_ADD(rx_128_to_255_octet_packets);
9359         ESTAT_ADD(rx_256_to_511_octet_packets);
9360         ESTAT_ADD(rx_512_to_1023_octet_packets);
9361         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9362         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9363         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9364         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9365         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9366
9367         ESTAT_ADD(tx_octets);
9368         ESTAT_ADD(tx_collisions);
9369         ESTAT_ADD(tx_xon_sent);
9370         ESTAT_ADD(tx_xoff_sent);
9371         ESTAT_ADD(tx_flow_control);
9372         ESTAT_ADD(tx_mac_errors);
9373         ESTAT_ADD(tx_single_collisions);
9374         ESTAT_ADD(tx_mult_collisions);
9375         ESTAT_ADD(tx_deferred);
9376         ESTAT_ADD(tx_excessive_collisions);
9377         ESTAT_ADD(tx_late_collisions);
9378         ESTAT_ADD(tx_collide_2times);
9379         ESTAT_ADD(tx_collide_3times);
9380         ESTAT_ADD(tx_collide_4times);
9381         ESTAT_ADD(tx_collide_5times);
9382         ESTAT_ADD(tx_collide_6times);
9383         ESTAT_ADD(tx_collide_7times);
9384         ESTAT_ADD(tx_collide_8times);
9385         ESTAT_ADD(tx_collide_9times);
9386         ESTAT_ADD(tx_collide_10times);
9387         ESTAT_ADD(tx_collide_11times);
9388         ESTAT_ADD(tx_collide_12times);
9389         ESTAT_ADD(tx_collide_13times);
9390         ESTAT_ADD(tx_collide_14times);
9391         ESTAT_ADD(tx_collide_15times);
9392         ESTAT_ADD(tx_ucast_packets);
9393         ESTAT_ADD(tx_mcast_packets);
9394         ESTAT_ADD(tx_bcast_packets);
9395         ESTAT_ADD(tx_carrier_sense_errors);
9396         ESTAT_ADD(tx_discards);
9397         ESTAT_ADD(tx_errors);
9398
9399         ESTAT_ADD(dma_writeq_full);
9400         ESTAT_ADD(dma_write_prioq_full);
9401         ESTAT_ADD(rxbds_empty);
9402         ESTAT_ADD(rx_discards);
9403         ESTAT_ADD(rx_errors);
9404         ESTAT_ADD(rx_threshold_hit);
9405
9406         ESTAT_ADD(dma_readq_full);
9407         ESTAT_ADD(dma_read_prioq_full);
9408         ESTAT_ADD(tx_comp_queue_full);
9409
9410         ESTAT_ADD(ring_set_send_prod_index);
9411         ESTAT_ADD(ring_status_update);
9412         ESTAT_ADD(nic_irqs);
9413         ESTAT_ADD(nic_avoided_irqs);
9414         ESTAT_ADD(nic_tx_threshold_hit);
9415
9416         return estats;
9417 }
9418
9419 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9420                                                  struct rtnl_link_stats64 *stats)
9421 {
9422         struct tg3 *tp = netdev_priv(dev);
9423         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9424         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9425
9426         if (!hw_stats)
9427                 return old_stats;
9428
9429         stats->rx_packets = old_stats->rx_packets +
9430                 get_stat64(&hw_stats->rx_ucast_packets) +
9431                 get_stat64(&hw_stats->rx_mcast_packets) +
9432                 get_stat64(&hw_stats->rx_bcast_packets);
9433
9434         stats->tx_packets = old_stats->tx_packets +
9435                 get_stat64(&hw_stats->tx_ucast_packets) +
9436                 get_stat64(&hw_stats->tx_mcast_packets) +
9437                 get_stat64(&hw_stats->tx_bcast_packets);
9438
9439         stats->rx_bytes = old_stats->rx_bytes +
9440                 get_stat64(&hw_stats->rx_octets);
9441         stats->tx_bytes = old_stats->tx_bytes +
9442                 get_stat64(&hw_stats->tx_octets);
9443
9444         stats->rx_errors = old_stats->rx_errors +
9445                 get_stat64(&hw_stats->rx_errors);
9446         stats->tx_errors = old_stats->tx_errors +
9447                 get_stat64(&hw_stats->tx_errors) +
9448                 get_stat64(&hw_stats->tx_mac_errors) +
9449                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9450                 get_stat64(&hw_stats->tx_discards);
9451
9452         stats->multicast = old_stats->multicast +
9453                 get_stat64(&hw_stats->rx_mcast_packets);
9454         stats->collisions = old_stats->collisions +
9455                 get_stat64(&hw_stats->tx_collisions);
9456
9457         stats->rx_length_errors = old_stats->rx_length_errors +
9458                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9459                 get_stat64(&hw_stats->rx_undersize_packets);
9460
9461         stats->rx_over_errors = old_stats->rx_over_errors +
9462                 get_stat64(&hw_stats->rxbds_empty);
9463         stats->rx_frame_errors = old_stats->rx_frame_errors +
9464                 get_stat64(&hw_stats->rx_align_errors);
9465         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9466                 get_stat64(&hw_stats->tx_discards);
9467         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9468                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9469
9470         stats->rx_crc_errors = old_stats->rx_crc_errors +
9471                 calc_crc_errors(tp);
9472
9473         stats->rx_missed_errors = old_stats->rx_missed_errors +
9474                 get_stat64(&hw_stats->rx_discards);
9475
9476         stats->rx_dropped = tp->rx_dropped;
9477
9478         return stats;
9479 }
9480
9481 static inline u32 calc_crc(unsigned char *buf, int len)
9482 {
9483         u32 reg;
9484         u32 tmp;
9485         int j, k;
9486
9487         reg = 0xffffffff;
9488
9489         for (j = 0; j < len; j++) {
9490                 reg ^= buf[j];
9491
9492                 for (k = 0; k < 8; k++) {
9493                         tmp = reg & 0x01;
9494
9495                         reg >>= 1;
9496
9497                         if (tmp)
9498                                 reg ^= 0xedb88320;
9499                 }
9500         }
9501
9502         return ~reg;
9503 }
9504
9505 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9506 {
9507         /* accept or reject all multicast frames */
9508         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9509         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9510         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9511         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9512 }
9513
9514 static void __tg3_set_rx_mode(struct net_device *dev)
9515 {
9516         struct tg3 *tp = netdev_priv(dev);
9517         u32 rx_mode;
9518
9519         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9520                                   RX_MODE_KEEP_VLAN_TAG);
9521
9522         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9523          * flag clear.
9524          */
9525 #if TG3_VLAN_TAG_USED
9526         if (!tp->vlgrp &&
9527             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9528                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9529 #else
9530         /* By definition, VLAN is disabled always in this
9531          * case.
9532          */
9533         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9534                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9535 #endif
9536
9537         if (dev->flags & IFF_PROMISC) {
9538                 /* Promiscuous mode. */
9539                 rx_mode |= RX_MODE_PROMISC;
9540         } else if (dev->flags & IFF_ALLMULTI) {
9541                 /* Accept all multicast. */
9542                 tg3_set_multi(tp, 1);
9543         } else if (netdev_mc_empty(dev)) {
9544                 /* Reject all multicast. */
9545                 tg3_set_multi(tp, 0);
9546         } else {
9547                 /* Accept one or more multicast(s). */
9548                 struct netdev_hw_addr *ha;
9549                 u32 mc_filter[4] = { 0, };
9550                 u32 regidx;
9551                 u32 bit;
9552                 u32 crc;
9553
9554                 netdev_for_each_mc_addr(ha, dev) {
9555                         crc = calc_crc(ha->addr, ETH_ALEN);
9556                         bit = ~crc & 0x7f;
9557                         regidx = (bit & 0x60) >> 5;
9558                         bit &= 0x1f;
9559                         mc_filter[regidx] |= (1 << bit);
9560                 }
9561
9562                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9563                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9564                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9565                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9566         }
9567
9568         if (rx_mode != tp->rx_mode) {
9569                 tp->rx_mode = rx_mode;
9570                 tw32_f(MAC_RX_MODE, rx_mode);
9571                 udelay(10);
9572         }
9573 }
9574
9575 static void tg3_set_rx_mode(struct net_device *dev)
9576 {
9577         struct tg3 *tp = netdev_priv(dev);
9578
9579         if (!netif_running(dev))
9580                 return;
9581
9582         tg3_full_lock(tp, 0);
9583         __tg3_set_rx_mode(dev);
9584         tg3_full_unlock(tp);
9585 }
9586
9587 #define TG3_REGDUMP_LEN         (32 * 1024)
9588
9589 static int tg3_get_regs_len(struct net_device *dev)
9590 {
9591         return TG3_REGDUMP_LEN;
9592 }
9593
9594 static void tg3_get_regs(struct net_device *dev,
9595                 struct ethtool_regs *regs, void *_p)
9596 {
9597         u32 *p = _p;
9598         struct tg3 *tp = netdev_priv(dev);
9599         u8 *orig_p = _p;
9600         int i;
9601
9602         regs->version = 0;
9603
9604         memset(p, 0, TG3_REGDUMP_LEN);
9605
9606         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9607                 return;
9608
9609         tg3_full_lock(tp, 0);
9610
9611 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9612 #define GET_REG32_LOOP(base, len)               \
9613 do {    p = (u32 *)(orig_p + (base));           \
9614         for (i = 0; i < len; i += 4)            \
9615                 __GET_REG32((base) + i);        \
9616 } while (0)
9617 #define GET_REG32_1(reg)                        \
9618 do {    p = (u32 *)(orig_p + (reg));            \
9619         __GET_REG32((reg));                     \
9620 } while (0)
9621
9622         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9623         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9624         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9625         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9626         GET_REG32_1(SNDDATAC_MODE);
9627         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9628         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9629         GET_REG32_1(SNDBDC_MODE);
9630         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9631         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9632         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9633         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9634         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9635         GET_REG32_1(RCVDCC_MODE);
9636         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9637         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9638         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9639         GET_REG32_1(MBFREE_MODE);
9640         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9641         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9642         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9643         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9644         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9645         GET_REG32_1(RX_CPU_MODE);
9646         GET_REG32_1(RX_CPU_STATE);
9647         GET_REG32_1(RX_CPU_PGMCTR);
9648         GET_REG32_1(RX_CPU_HWBKPT);
9649         GET_REG32_1(TX_CPU_MODE);
9650         GET_REG32_1(TX_CPU_STATE);
9651         GET_REG32_1(TX_CPU_PGMCTR);
9652         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9653         GET_REG32_LOOP(FTQ_RESET, 0x120);
9654         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9655         GET_REG32_1(DMAC_MODE);
9656         GET_REG32_LOOP(GRC_MODE, 0x4c);
9657         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9658                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9659
9660 #undef __GET_REG32
9661 #undef GET_REG32_LOOP
9662 #undef GET_REG32_1
9663
9664         tg3_full_unlock(tp);
9665 }
9666
9667 static int tg3_get_eeprom_len(struct net_device *dev)
9668 {
9669         struct tg3 *tp = netdev_priv(dev);
9670
9671         return tp->nvram_size;
9672 }
9673
9674 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9675 {
9676         struct tg3 *tp = netdev_priv(dev);
9677         int ret;
9678         u8  *pd;
9679         u32 i, offset, len, b_offset, b_count;
9680         __be32 val;
9681
9682         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9683                 return -EINVAL;
9684
9685         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9686                 return -EAGAIN;
9687
9688         offset = eeprom->offset;
9689         len = eeprom->len;
9690         eeprom->len = 0;
9691
9692         eeprom->magic = TG3_EEPROM_MAGIC;
9693
9694         if (offset & 3) {
9695                 /* adjustments to start on required 4 byte boundary */
9696                 b_offset = offset & 3;
9697                 b_count = 4 - b_offset;
9698                 if (b_count > len) {
9699                         /* i.e. offset=1 len=2 */
9700                         b_count = len;
9701                 }
9702                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9703                 if (ret)
9704                         return ret;
9705                 memcpy(data, ((char *)&val) + b_offset, b_count);
9706                 len -= b_count;
9707                 offset += b_count;
9708                 eeprom->len += b_count;
9709         }
9710
9711         /* read bytes upto the last 4 byte boundary */
9712         pd = &data[eeprom->len];
9713         for (i = 0; i < (len - (len & 3)); i += 4) {
9714                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9715                 if (ret) {
9716                         eeprom->len += i;
9717                         return ret;
9718                 }
9719                 memcpy(pd + i, &val, 4);
9720         }
9721         eeprom->len += i;
9722
9723         if (len & 3) {
9724                 /* read last bytes not ending on 4 byte boundary */
9725                 pd = &data[eeprom->len];
9726                 b_count = len & 3;
9727                 b_offset = offset + len - b_count;
9728                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9729                 if (ret)
9730                         return ret;
9731                 memcpy(pd, &val, b_count);
9732                 eeprom->len += b_count;
9733         }
9734         return 0;
9735 }
9736
9737 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9738
9739 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9740 {
9741         struct tg3 *tp = netdev_priv(dev);
9742         int ret;
9743         u32 offset, len, b_offset, odd_len;
9744         u8 *buf;
9745         __be32 start, end;
9746
9747         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9748                 return -EAGAIN;
9749
9750         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9751             eeprom->magic != TG3_EEPROM_MAGIC)
9752                 return -EINVAL;
9753
9754         offset = eeprom->offset;
9755         len = eeprom->len;
9756
9757         if ((b_offset = (offset & 3))) {
9758                 /* adjustments to start on required 4 byte boundary */
9759                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9760                 if (ret)
9761                         return ret;
9762                 len += b_offset;
9763                 offset &= ~3;
9764                 if (len < 4)
9765                         len = 4;
9766         }
9767
9768         odd_len = 0;
9769         if (len & 3) {
9770                 /* adjustments to end on required 4 byte boundary */
9771                 odd_len = 1;
9772                 len = (len + 3) & ~3;
9773                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9774                 if (ret)
9775                         return ret;
9776         }
9777
9778         buf = data;
9779         if (b_offset || odd_len) {
9780                 buf = kmalloc(len, GFP_KERNEL);
9781                 if (!buf)
9782                         return -ENOMEM;
9783                 if (b_offset)
9784                         memcpy(buf, &start, 4);
9785                 if (odd_len)
9786                         memcpy(buf+len-4, &end, 4);
9787                 memcpy(buf + b_offset, data, eeprom->len);
9788         }
9789
9790         ret = tg3_nvram_write_block(tp, offset, len, buf);
9791
9792         if (buf != data)
9793                 kfree(buf);
9794
9795         return ret;
9796 }
9797
9798 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9799 {
9800         struct tg3 *tp = netdev_priv(dev);
9801
9802         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9803                 struct phy_device *phydev;
9804                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9805                         return -EAGAIN;
9806                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9807                 return phy_ethtool_gset(phydev, cmd);
9808         }
9809
9810         cmd->supported = (SUPPORTED_Autoneg);
9811
9812         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9813                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9814                                    SUPPORTED_1000baseT_Full);
9815
9816         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9817                 cmd->supported |= (SUPPORTED_100baseT_Half |
9818                                   SUPPORTED_100baseT_Full |
9819                                   SUPPORTED_10baseT_Half |
9820                                   SUPPORTED_10baseT_Full |
9821                                   SUPPORTED_TP);
9822                 cmd->port = PORT_TP;
9823         } else {
9824                 cmd->supported |= SUPPORTED_FIBRE;
9825                 cmd->port = PORT_FIBRE;
9826         }
9827
9828         cmd->advertising = tp->link_config.advertising;
9829         if (netif_running(dev)) {
9830                 cmd->speed = tp->link_config.active_speed;
9831                 cmd->duplex = tp->link_config.active_duplex;
9832         } else {
9833                 cmd->speed = SPEED_INVALID;
9834                 cmd->duplex = DUPLEX_INVALID;
9835         }
9836         cmd->phy_address = tp->phy_addr;
9837         cmd->transceiver = XCVR_INTERNAL;
9838         cmd->autoneg = tp->link_config.autoneg;
9839         cmd->maxtxpkt = 0;
9840         cmd->maxrxpkt = 0;
9841         return 0;
9842 }
9843
9844 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9845 {
9846         struct tg3 *tp = netdev_priv(dev);
9847
9848         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9849                 struct phy_device *phydev;
9850                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9851                         return -EAGAIN;
9852                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9853                 return phy_ethtool_sset(phydev, cmd);
9854         }
9855
9856         if (cmd->autoneg != AUTONEG_ENABLE &&
9857             cmd->autoneg != AUTONEG_DISABLE)
9858                 return -EINVAL;
9859
9860         if (cmd->autoneg == AUTONEG_DISABLE &&
9861             cmd->duplex != DUPLEX_FULL &&
9862             cmd->duplex != DUPLEX_HALF)
9863                 return -EINVAL;
9864
9865         if (cmd->autoneg == AUTONEG_ENABLE) {
9866                 u32 mask = ADVERTISED_Autoneg |
9867                            ADVERTISED_Pause |
9868                            ADVERTISED_Asym_Pause;
9869
9870                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9871                         mask |= ADVERTISED_1000baseT_Half |
9872                                 ADVERTISED_1000baseT_Full;
9873
9874                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9875                         mask |= ADVERTISED_100baseT_Half |
9876                                 ADVERTISED_100baseT_Full |
9877                                 ADVERTISED_10baseT_Half |
9878                                 ADVERTISED_10baseT_Full |
9879                                 ADVERTISED_TP;
9880                 else
9881                         mask |= ADVERTISED_FIBRE;
9882
9883                 if (cmd->advertising & ~mask)
9884                         return -EINVAL;
9885
9886                 mask &= (ADVERTISED_1000baseT_Half |
9887                          ADVERTISED_1000baseT_Full |
9888                          ADVERTISED_100baseT_Half |
9889                          ADVERTISED_100baseT_Full |
9890                          ADVERTISED_10baseT_Half |
9891                          ADVERTISED_10baseT_Full);
9892
9893                 cmd->advertising &= mask;
9894         } else {
9895                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9896                         if (cmd->speed != SPEED_1000)
9897                                 return -EINVAL;
9898
9899                         if (cmd->duplex != DUPLEX_FULL)
9900                                 return -EINVAL;
9901                 } else {
9902                         if (cmd->speed != SPEED_100 &&
9903                             cmd->speed != SPEED_10)
9904                                 return -EINVAL;
9905                 }
9906         }
9907
9908         tg3_full_lock(tp, 0);
9909
9910         tp->link_config.autoneg = cmd->autoneg;
9911         if (cmd->autoneg == AUTONEG_ENABLE) {
9912                 tp->link_config.advertising = (cmd->advertising |
9913                                               ADVERTISED_Autoneg);
9914                 tp->link_config.speed = SPEED_INVALID;
9915                 tp->link_config.duplex = DUPLEX_INVALID;
9916         } else {
9917                 tp->link_config.advertising = 0;
9918                 tp->link_config.speed = cmd->speed;
9919                 tp->link_config.duplex = cmd->duplex;
9920         }
9921
9922         tp->link_config.orig_speed = tp->link_config.speed;
9923         tp->link_config.orig_duplex = tp->link_config.duplex;
9924         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9925
9926         if (netif_running(dev))
9927                 tg3_setup_phy(tp, 1);
9928
9929         tg3_full_unlock(tp);
9930
9931         return 0;
9932 }
9933
9934 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9935 {
9936         struct tg3 *tp = netdev_priv(dev);
9937
9938         strcpy(info->driver, DRV_MODULE_NAME);
9939         strcpy(info->version, DRV_MODULE_VERSION);
9940         strcpy(info->fw_version, tp->fw_ver);
9941         strcpy(info->bus_info, pci_name(tp->pdev));
9942 }
9943
9944 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9945 {
9946         struct tg3 *tp = netdev_priv(dev);
9947
9948         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9949             device_can_wakeup(&tp->pdev->dev))
9950                 wol->supported = WAKE_MAGIC;
9951         else
9952                 wol->supported = 0;
9953         wol->wolopts = 0;
9954         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9955             device_can_wakeup(&tp->pdev->dev))
9956                 wol->wolopts = WAKE_MAGIC;
9957         memset(&wol->sopass, 0, sizeof(wol->sopass));
9958 }
9959
9960 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9961 {
9962         struct tg3 *tp = netdev_priv(dev);
9963         struct device *dp = &tp->pdev->dev;
9964
9965         if (wol->wolopts & ~WAKE_MAGIC)
9966                 return -EINVAL;
9967         if ((wol->wolopts & WAKE_MAGIC) &&
9968             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9969                 return -EINVAL;
9970
9971         device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
9972
9973         spin_lock_bh(&tp->lock);
9974         if (device_may_wakeup(dp))
9975                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9976         else
9977                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9978         spin_unlock_bh(&tp->lock);
9979
9980
9981         return 0;
9982 }
9983
9984 static u32 tg3_get_msglevel(struct net_device *dev)
9985 {
9986         struct tg3 *tp = netdev_priv(dev);
9987         return tp->msg_enable;
9988 }
9989
9990 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9991 {
9992         struct tg3 *tp = netdev_priv(dev);
9993         tp->msg_enable = value;
9994 }
9995
9996 static int tg3_set_tso(struct net_device *dev, u32 value)
9997 {
9998         struct tg3 *tp = netdev_priv(dev);
9999
10000         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
10001                 if (value)
10002                         return -EINVAL;
10003                 return 0;
10004         }
10005         if ((dev->features & NETIF_F_IPV6_CSUM) &&
10006             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
10007              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
10008                 if (value) {
10009                         dev->features |= NETIF_F_TSO6;
10010                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
10011                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
10012                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
10013                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
10014                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
10015                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
10016                                 dev->features |= NETIF_F_TSO_ECN;
10017                 } else
10018                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
10019         }
10020         return ethtool_op_set_tso(dev, value);
10021 }
10022
10023 static int tg3_nway_reset(struct net_device *dev)
10024 {
10025         struct tg3 *tp = netdev_priv(dev);
10026         int r;
10027
10028         if (!netif_running(dev))
10029                 return -EAGAIN;
10030
10031         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10032                 return -EINVAL;
10033
10034         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10035                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10036                         return -EAGAIN;
10037                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10038         } else {
10039                 u32 bmcr;
10040
10041                 spin_lock_bh(&tp->lock);
10042                 r = -EINVAL;
10043                 tg3_readphy(tp, MII_BMCR, &bmcr);
10044                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10045                     ((bmcr & BMCR_ANENABLE) ||
10046                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10047                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10048                                                    BMCR_ANENABLE);
10049                         r = 0;
10050                 }
10051                 spin_unlock_bh(&tp->lock);
10052         }
10053
10054         return r;
10055 }
10056
10057 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10058 {
10059         struct tg3 *tp = netdev_priv(dev);
10060
10061         ering->rx_max_pending = tp->rx_std_ring_mask;
10062         ering->rx_mini_max_pending = 0;
10063         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10064                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10065         else
10066                 ering->rx_jumbo_max_pending = 0;
10067
10068         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10069
10070         ering->rx_pending = tp->rx_pending;
10071         ering->rx_mini_pending = 0;
10072         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10073                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10074         else
10075                 ering->rx_jumbo_pending = 0;
10076
10077         ering->tx_pending = tp->napi[0].tx_pending;
10078 }
10079
10080 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10081 {
10082         struct tg3 *tp = netdev_priv(dev);
10083         int i, irq_sync = 0, err = 0;
10084
10085         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10086             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10087             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10088             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10089             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10090              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10091                 return -EINVAL;
10092
10093         if (netif_running(dev)) {
10094                 tg3_phy_stop(tp);
10095                 tg3_netif_stop(tp);
10096                 irq_sync = 1;
10097         }
10098
10099         tg3_full_lock(tp, irq_sync);
10100
10101         tp->rx_pending = ering->rx_pending;
10102
10103         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10104             tp->rx_pending > 63)
10105                 tp->rx_pending = 63;
10106         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10107
10108         for (i = 0; i < tp->irq_max; i++)
10109                 tp->napi[i].tx_pending = ering->tx_pending;
10110
10111         if (netif_running(dev)) {
10112                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10113                 err = tg3_restart_hw(tp, 1);
10114                 if (!err)
10115                         tg3_netif_start(tp);
10116         }
10117
10118         tg3_full_unlock(tp);
10119
10120         if (irq_sync && !err)
10121                 tg3_phy_start(tp);
10122
10123         return err;
10124 }
10125
10126 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10127 {
10128         struct tg3 *tp = netdev_priv(dev);
10129
10130         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10131
10132         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10133                 epause->rx_pause = 1;
10134         else
10135                 epause->rx_pause = 0;
10136
10137         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10138                 epause->tx_pause = 1;
10139         else
10140                 epause->tx_pause = 0;
10141 }
10142
10143 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10144 {
10145         struct tg3 *tp = netdev_priv(dev);
10146         int err = 0;
10147
10148         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10149                 u32 newadv;
10150                 struct phy_device *phydev;
10151
10152                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10153
10154                 if (!(phydev->supported & SUPPORTED_Pause) ||
10155                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10156                      (epause->rx_pause != epause->tx_pause)))
10157                         return -EINVAL;
10158
10159                 tp->link_config.flowctrl = 0;
10160                 if (epause->rx_pause) {
10161                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10162
10163                         if (epause->tx_pause) {
10164                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10165                                 newadv = ADVERTISED_Pause;
10166                         } else
10167                                 newadv = ADVERTISED_Pause |
10168                                          ADVERTISED_Asym_Pause;
10169                 } else if (epause->tx_pause) {
10170                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10171                         newadv = ADVERTISED_Asym_Pause;
10172                 } else
10173                         newadv = 0;
10174
10175                 if (epause->autoneg)
10176                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10177                 else
10178                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10179
10180                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10181                         u32 oldadv = phydev->advertising &
10182                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10183                         if (oldadv != newadv) {
10184                                 phydev->advertising &=
10185                                         ~(ADVERTISED_Pause |
10186                                           ADVERTISED_Asym_Pause);
10187                                 phydev->advertising |= newadv;
10188                                 if (phydev->autoneg) {
10189                                         /*
10190                                          * Always renegotiate the link to
10191                                          * inform our link partner of our
10192                                          * flow control settings, even if the
10193                                          * flow control is forced.  Let
10194                                          * tg3_adjust_link() do the final
10195                                          * flow control setup.
10196                                          */
10197                                         return phy_start_aneg(phydev);
10198                                 }
10199                         }
10200
10201                         if (!epause->autoneg)
10202                                 tg3_setup_flow_control(tp, 0, 0);
10203                 } else {
10204                         tp->link_config.orig_advertising &=
10205                                         ~(ADVERTISED_Pause |
10206                                           ADVERTISED_Asym_Pause);
10207                         tp->link_config.orig_advertising |= newadv;
10208                 }
10209         } else {
10210                 int irq_sync = 0;
10211
10212                 if (netif_running(dev)) {
10213                         tg3_netif_stop(tp);
10214                         irq_sync = 1;
10215                 }
10216
10217                 tg3_full_lock(tp, irq_sync);
10218
10219                 if (epause->autoneg)
10220                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10221                 else
10222                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10223                 if (epause->rx_pause)
10224                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10225                 else
10226                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10227                 if (epause->tx_pause)
10228                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10229                 else
10230                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10231
10232                 if (netif_running(dev)) {
10233                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10234                         err = tg3_restart_hw(tp, 1);
10235                         if (!err)
10236                                 tg3_netif_start(tp);
10237                 }
10238
10239                 tg3_full_unlock(tp);
10240         }
10241
10242         return err;
10243 }
10244
10245 static u32 tg3_get_rx_csum(struct net_device *dev)
10246 {
10247         struct tg3 *tp = netdev_priv(dev);
10248         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10249 }
10250
10251 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10252 {
10253         struct tg3 *tp = netdev_priv(dev);
10254
10255         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10256                 if (data != 0)
10257                         return -EINVAL;
10258                 return 0;
10259         }
10260
10261         spin_lock_bh(&tp->lock);
10262         if (data)
10263                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10264         else
10265                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10266         spin_unlock_bh(&tp->lock);
10267
10268         return 0;
10269 }
10270
10271 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10272 {
10273         struct tg3 *tp = netdev_priv(dev);
10274
10275         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10276                 if (data != 0)
10277                         return -EINVAL;
10278                 return 0;
10279         }
10280
10281         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10282                 ethtool_op_set_tx_ipv6_csum(dev, data);
10283         else
10284                 ethtool_op_set_tx_csum(dev, data);
10285
10286         return 0;
10287 }
10288
10289 static int tg3_get_sset_count(struct net_device *dev, int sset)
10290 {
10291         switch (sset) {
10292         case ETH_SS_TEST:
10293                 return TG3_NUM_TEST;
10294         case ETH_SS_STATS:
10295                 return TG3_NUM_STATS;
10296         default:
10297                 return -EOPNOTSUPP;
10298         }
10299 }
10300
10301 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10302 {
10303         switch (stringset) {
10304         case ETH_SS_STATS:
10305                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10306                 break;
10307         case ETH_SS_TEST:
10308                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10309                 break;
10310         default:
10311                 WARN_ON(1);     /* we need a WARN() */
10312                 break;
10313         }
10314 }
10315
10316 static int tg3_phys_id(struct net_device *dev, u32 data)
10317 {
10318         struct tg3 *tp = netdev_priv(dev);
10319         int i;
10320
10321         if (!netif_running(tp->dev))
10322                 return -EAGAIN;
10323
10324         if (data == 0)
10325                 data = UINT_MAX / 2;
10326
10327         for (i = 0; i < (data * 2); i++) {
10328                 if ((i % 2) == 0)
10329                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10330                                            LED_CTRL_1000MBPS_ON |
10331                                            LED_CTRL_100MBPS_ON |
10332                                            LED_CTRL_10MBPS_ON |
10333                                            LED_CTRL_TRAFFIC_OVERRIDE |
10334                                            LED_CTRL_TRAFFIC_BLINK |
10335                                            LED_CTRL_TRAFFIC_LED);
10336
10337                 else
10338                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10339                                            LED_CTRL_TRAFFIC_OVERRIDE);
10340
10341                 if (msleep_interruptible(500))
10342                         break;
10343         }
10344         tw32(MAC_LED_CTRL, tp->led_ctrl);
10345         return 0;
10346 }
10347
10348 static void tg3_get_ethtool_stats(struct net_device *dev,
10349                                    struct ethtool_stats *estats, u64 *tmp_stats)
10350 {
10351         struct tg3 *tp = netdev_priv(dev);
10352         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10353 }
10354
10355 #define NVRAM_TEST_SIZE 0x100
10356 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10357 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10358 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10359 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10360 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10361
10362 static int tg3_test_nvram(struct tg3 *tp)
10363 {
10364         u32 csum, magic;
10365         __be32 *buf;
10366         int i, j, k, err = 0, size;
10367
10368         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10369                 return 0;
10370
10371         if (tg3_nvram_read(tp, 0, &magic) != 0)
10372                 return -EIO;
10373
10374         if (magic == TG3_EEPROM_MAGIC)
10375                 size = NVRAM_TEST_SIZE;
10376         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10377                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10378                     TG3_EEPROM_SB_FORMAT_1) {
10379                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10380                         case TG3_EEPROM_SB_REVISION_0:
10381                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10382                                 break;
10383                         case TG3_EEPROM_SB_REVISION_2:
10384                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10385                                 break;
10386                         case TG3_EEPROM_SB_REVISION_3:
10387                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10388                                 break;
10389                         default:
10390                                 return 0;
10391                         }
10392                 } else
10393                         return 0;
10394         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10395                 size = NVRAM_SELFBOOT_HW_SIZE;
10396         else
10397                 return -EIO;
10398
10399         buf = kmalloc(size, GFP_KERNEL);
10400         if (buf == NULL)
10401                 return -ENOMEM;
10402
10403         err = -EIO;
10404         for (i = 0, j = 0; i < size; i += 4, j++) {
10405                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10406                 if (err)
10407                         break;
10408         }
10409         if (i < size)
10410                 goto out;
10411
10412         /* Selfboot format */
10413         magic = be32_to_cpu(buf[0]);
10414         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10415             TG3_EEPROM_MAGIC_FW) {
10416                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10417
10418                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10419                     TG3_EEPROM_SB_REVISION_2) {
10420                         /* For rev 2, the csum doesn't include the MBA. */
10421                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10422                                 csum8 += buf8[i];
10423                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10424                                 csum8 += buf8[i];
10425                 } else {
10426                         for (i = 0; i < size; i++)
10427                                 csum8 += buf8[i];
10428                 }
10429
10430                 if (csum8 == 0) {
10431                         err = 0;
10432                         goto out;
10433                 }
10434
10435                 err = -EIO;
10436                 goto out;
10437         }
10438
10439         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10440             TG3_EEPROM_MAGIC_HW) {
10441                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10442                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10443                 u8 *buf8 = (u8 *) buf;
10444
10445                 /* Separate the parity bits and the data bytes.  */
10446                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10447                         if ((i == 0) || (i == 8)) {
10448                                 int l;
10449                                 u8 msk;
10450
10451                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10452                                         parity[k++] = buf8[i] & msk;
10453                                 i++;
10454                         } else if (i == 16) {
10455                                 int l;
10456                                 u8 msk;
10457
10458                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10459                                         parity[k++] = buf8[i] & msk;
10460                                 i++;
10461
10462                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10463                                         parity[k++] = buf8[i] & msk;
10464                                 i++;
10465                         }
10466                         data[j++] = buf8[i];
10467                 }
10468
10469                 err = -EIO;
10470                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10471                         u8 hw8 = hweight8(data[i]);
10472
10473                         if ((hw8 & 0x1) && parity[i])
10474                                 goto out;
10475                         else if (!(hw8 & 0x1) && !parity[i])
10476                                 goto out;
10477                 }
10478                 err = 0;
10479                 goto out;
10480         }
10481
10482         /* Bootstrap checksum at offset 0x10 */
10483         csum = calc_crc((unsigned char *) buf, 0x10);
10484         if (csum != be32_to_cpu(buf[0x10/4]))
10485                 goto out;
10486
10487         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10488         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10489         if (csum != be32_to_cpu(buf[0xfc/4]))
10490                 goto out;
10491
10492         err = 0;
10493
10494 out:
10495         kfree(buf);
10496         return err;
10497 }
10498
10499 #define TG3_SERDES_TIMEOUT_SEC  2
10500 #define TG3_COPPER_TIMEOUT_SEC  6
10501
10502 static int tg3_test_link(struct tg3 *tp)
10503 {
10504         int i, max;
10505
10506         if (!netif_running(tp->dev))
10507                 return -ENODEV;
10508
10509         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10510                 max = TG3_SERDES_TIMEOUT_SEC;
10511         else
10512                 max = TG3_COPPER_TIMEOUT_SEC;
10513
10514         for (i = 0; i < max; i++) {
10515                 if (netif_carrier_ok(tp->dev))
10516                         return 0;
10517
10518                 if (msleep_interruptible(1000))
10519                         break;
10520         }
10521
10522         return -EIO;
10523 }
10524
10525 /* Only test the commonly used registers */
10526 static int tg3_test_registers(struct tg3 *tp)
10527 {
10528         int i, is_5705, is_5750;
10529         u32 offset, read_mask, write_mask, val, save_val, read_val;
10530         static struct {
10531                 u16 offset;
10532                 u16 flags;
10533 #define TG3_FL_5705     0x1
10534 #define TG3_FL_NOT_5705 0x2
10535 #define TG3_FL_NOT_5788 0x4
10536 #define TG3_FL_NOT_5750 0x8
10537                 u32 read_mask;
10538                 u32 write_mask;
10539         } reg_tbl[] = {
10540                 /* MAC Control Registers */
10541                 { MAC_MODE, TG3_FL_NOT_5705,
10542                         0x00000000, 0x00ef6f8c },
10543                 { MAC_MODE, TG3_FL_5705,
10544                         0x00000000, 0x01ef6b8c },
10545                 { MAC_STATUS, TG3_FL_NOT_5705,
10546                         0x03800107, 0x00000000 },
10547                 { MAC_STATUS, TG3_FL_5705,
10548                         0x03800100, 0x00000000 },
10549                 { MAC_ADDR_0_HIGH, 0x0000,
10550                         0x00000000, 0x0000ffff },
10551                 { MAC_ADDR_0_LOW, 0x0000,
10552                         0x00000000, 0xffffffff },
10553                 { MAC_RX_MTU_SIZE, 0x0000,
10554                         0x00000000, 0x0000ffff },
10555                 { MAC_TX_MODE, 0x0000,
10556                         0x00000000, 0x00000070 },
10557                 { MAC_TX_LENGTHS, 0x0000,
10558                         0x00000000, 0x00003fff },
10559                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10560                         0x00000000, 0x000007fc },
10561                 { MAC_RX_MODE, TG3_FL_5705,
10562                         0x00000000, 0x000007dc },
10563                 { MAC_HASH_REG_0, 0x0000,
10564                         0x00000000, 0xffffffff },
10565                 { MAC_HASH_REG_1, 0x0000,
10566                         0x00000000, 0xffffffff },
10567                 { MAC_HASH_REG_2, 0x0000,
10568                         0x00000000, 0xffffffff },
10569                 { MAC_HASH_REG_3, 0x0000,
10570                         0x00000000, 0xffffffff },
10571
10572                 /* Receive Data and Receive BD Initiator Control Registers. */
10573                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10574                         0x00000000, 0xffffffff },
10575                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10576                         0x00000000, 0xffffffff },
10577                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10578                         0x00000000, 0x00000003 },
10579                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10580                         0x00000000, 0xffffffff },
10581                 { RCVDBDI_STD_BD+0, 0x0000,
10582                         0x00000000, 0xffffffff },
10583                 { RCVDBDI_STD_BD+4, 0x0000,
10584                         0x00000000, 0xffffffff },
10585                 { RCVDBDI_STD_BD+8, 0x0000,
10586                         0x00000000, 0xffff0002 },
10587                 { RCVDBDI_STD_BD+0xc, 0x0000,
10588                         0x00000000, 0xffffffff },
10589
10590                 /* Receive BD Initiator Control Registers. */
10591                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10592                         0x00000000, 0xffffffff },
10593                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10594                         0x00000000, 0x000003ff },
10595                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10596                         0x00000000, 0xffffffff },
10597
10598                 /* Host Coalescing Control Registers. */
10599                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10600                         0x00000000, 0x00000004 },
10601                 { HOSTCC_MODE, TG3_FL_5705,
10602                         0x00000000, 0x000000f6 },
10603                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10604                         0x00000000, 0xffffffff },
10605                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10606                         0x00000000, 0x000003ff },
10607                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10608                         0x00000000, 0xffffffff },
10609                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10610                         0x00000000, 0x000003ff },
10611                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10612                         0x00000000, 0xffffffff },
10613                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10614                         0x00000000, 0x000000ff },
10615                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10616                         0x00000000, 0xffffffff },
10617                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10618                         0x00000000, 0x000000ff },
10619                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10620                         0x00000000, 0xffffffff },
10621                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10622                         0x00000000, 0xffffffff },
10623                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10624                         0x00000000, 0xffffffff },
10625                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10626                         0x00000000, 0x000000ff },
10627                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10628                         0x00000000, 0xffffffff },
10629                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10630                         0x00000000, 0x000000ff },
10631                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10632                         0x00000000, 0xffffffff },
10633                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10634                         0x00000000, 0xffffffff },
10635                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10636                         0x00000000, 0xffffffff },
10637                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10638                         0x00000000, 0xffffffff },
10639                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10640                         0x00000000, 0xffffffff },
10641                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10642                         0xffffffff, 0x00000000 },
10643                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10644                         0xffffffff, 0x00000000 },
10645
10646                 /* Buffer Manager Control Registers. */
10647                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10648                         0x00000000, 0x007fff80 },
10649                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10650                         0x00000000, 0x007fffff },
10651                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10652                         0x00000000, 0x0000003f },
10653                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10654                         0x00000000, 0x000001ff },
10655                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10656                         0x00000000, 0x000001ff },
10657                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10658                         0xffffffff, 0x00000000 },
10659                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10660                         0xffffffff, 0x00000000 },
10661
10662                 /* Mailbox Registers */
10663                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10664                         0x00000000, 0x000001ff },
10665                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10666                         0x00000000, 0x000001ff },
10667                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10668                         0x00000000, 0x000007ff },
10669                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10670                         0x00000000, 0x000001ff },
10671
10672                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10673         };
10674
10675         is_5705 = is_5750 = 0;
10676         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10677                 is_5705 = 1;
10678                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10679                         is_5750 = 1;
10680         }
10681
10682         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10683                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10684                         continue;
10685
10686                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10687                         continue;
10688
10689                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10690                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10691                         continue;
10692
10693                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10694                         continue;
10695
10696                 offset = (u32) reg_tbl[i].offset;
10697                 read_mask = reg_tbl[i].read_mask;
10698                 write_mask = reg_tbl[i].write_mask;
10699
10700                 /* Save the original register content */
10701                 save_val = tr32(offset);
10702
10703                 /* Determine the read-only value. */
10704                 read_val = save_val & read_mask;
10705
10706                 /* Write zero to the register, then make sure the read-only bits
10707                  * are not changed and the read/write bits are all zeros.
10708                  */
10709                 tw32(offset, 0);
10710
10711                 val = tr32(offset);
10712
10713                 /* Test the read-only and read/write bits. */
10714                 if (((val & read_mask) != read_val) || (val & write_mask))
10715                         goto out;
10716
10717                 /* Write ones to all the bits defined by RdMask and WrMask, then
10718                  * make sure the read-only bits are not changed and the
10719                  * read/write bits are all ones.
10720                  */
10721                 tw32(offset, read_mask | write_mask);
10722
10723                 val = tr32(offset);
10724
10725                 /* Test the read-only bits. */
10726                 if ((val & read_mask) != read_val)
10727                         goto out;
10728
10729                 /* Test the read/write bits. */
10730                 if ((val & write_mask) != write_mask)
10731                         goto out;
10732
10733                 tw32(offset, save_val);
10734         }
10735
10736         return 0;
10737
10738 out:
10739         if (netif_msg_hw(tp))
10740                 netdev_err(tp->dev,
10741                            "Register test failed at offset %x\n", offset);
10742         tw32(offset, save_val);
10743         return -EIO;
10744 }
10745
10746 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10747 {
10748         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10749         int i;
10750         u32 j;
10751
10752         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10753                 for (j = 0; j < len; j += 4) {
10754                         u32 val;
10755
10756                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10757                         tg3_read_mem(tp, offset + j, &val);
10758                         if (val != test_pattern[i])
10759                                 return -EIO;
10760                 }
10761         }
10762         return 0;
10763 }
10764
10765 static int tg3_test_memory(struct tg3 *tp)
10766 {
10767         static struct mem_entry {
10768                 u32 offset;
10769                 u32 len;
10770         } mem_tbl_570x[] = {
10771                 { 0x00000000, 0x00b50},
10772                 { 0x00002000, 0x1c000},
10773                 { 0xffffffff, 0x00000}
10774         }, mem_tbl_5705[] = {
10775                 { 0x00000100, 0x0000c},
10776                 { 0x00000200, 0x00008},
10777                 { 0x00004000, 0x00800},
10778                 { 0x00006000, 0x01000},
10779                 { 0x00008000, 0x02000},
10780                 { 0x00010000, 0x0e000},
10781                 { 0xffffffff, 0x00000}
10782         }, mem_tbl_5755[] = {
10783                 { 0x00000200, 0x00008},
10784                 { 0x00004000, 0x00800},
10785                 { 0x00006000, 0x00800},
10786                 { 0x00008000, 0x02000},
10787                 { 0x00010000, 0x0c000},
10788                 { 0xffffffff, 0x00000}
10789         }, mem_tbl_5906[] = {
10790                 { 0x00000200, 0x00008},
10791                 { 0x00004000, 0x00400},
10792                 { 0x00006000, 0x00400},
10793                 { 0x00008000, 0x01000},
10794                 { 0x00010000, 0x01000},
10795                 { 0xffffffff, 0x00000}
10796         }, mem_tbl_5717[] = {
10797                 { 0x00000200, 0x00008},
10798                 { 0x00010000, 0x0a000},
10799                 { 0x00020000, 0x13c00},
10800                 { 0xffffffff, 0x00000}
10801         }, mem_tbl_57765[] = {
10802                 { 0x00000200, 0x00008},
10803                 { 0x00004000, 0x00800},
10804                 { 0x00006000, 0x09800},
10805                 { 0x00010000, 0x0a000},
10806                 { 0xffffffff, 0x00000}
10807         };
10808         struct mem_entry *mem_tbl;
10809         int err = 0;
10810         int i;
10811
10812         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10813             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10814                 mem_tbl = mem_tbl_5717;
10815         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10816                 mem_tbl = mem_tbl_57765;
10817         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10818                 mem_tbl = mem_tbl_5755;
10819         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10820                 mem_tbl = mem_tbl_5906;
10821         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10822                 mem_tbl = mem_tbl_5705;
10823         else
10824                 mem_tbl = mem_tbl_570x;
10825
10826         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10827                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10828                 if (err)
10829                         break;
10830         }
10831
10832         return err;
10833 }
10834
10835 #define TG3_MAC_LOOPBACK        0
10836 #define TG3_PHY_LOOPBACK        1
10837
10838 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10839 {
10840         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10841         u32 desc_idx, coal_now;
10842         struct sk_buff *skb, *rx_skb;
10843         u8 *tx_data;
10844         dma_addr_t map;
10845         int num_pkts, tx_len, rx_len, i, err;
10846         struct tg3_rx_buffer_desc *desc;
10847         struct tg3_napi *tnapi, *rnapi;
10848         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10849
10850         tnapi = &tp->napi[0];
10851         rnapi = &tp->napi[0];
10852         if (tp->irq_cnt > 1) {
10853                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10854                         rnapi = &tp->napi[1];
10855                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10856                         tnapi = &tp->napi[1];
10857         }
10858         coal_now = tnapi->coal_now | rnapi->coal_now;
10859
10860         if (loopback_mode == TG3_MAC_LOOPBACK) {
10861                 /* HW errata - mac loopback fails in some cases on 5780.
10862                  * Normal traffic and PHY loopback are not affected by
10863                  * errata.
10864                  */
10865                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10866                         return 0;
10867
10868                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10869                            MAC_MODE_PORT_INT_LPBACK;
10870                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10871                         mac_mode |= MAC_MODE_LINK_POLARITY;
10872                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10873                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10874                 else
10875                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10876                 tw32(MAC_MODE, mac_mode);
10877         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10878                 u32 val;
10879
10880                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10881                         tg3_phy_fet_toggle_apd(tp, false);
10882                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10883                 } else
10884                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10885
10886                 tg3_phy_toggle_automdix(tp, 0);
10887
10888                 tg3_writephy(tp, MII_BMCR, val);
10889                 udelay(40);
10890
10891                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10892                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10893                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10894                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10895                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10896                         /* The write needs to be flushed for the AC131 */
10897                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10898                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10899                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10900                 } else
10901                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10902
10903                 /* reset to prevent losing 1st rx packet intermittently */
10904                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10905                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10906                         udelay(10);
10907                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10908                 }
10909                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10910                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10911                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10912                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10913                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10914                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10915                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10916                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10917                 }
10918                 tw32(MAC_MODE, mac_mode);
10919         } else {
10920                 return -EINVAL;
10921         }
10922
10923         err = -EIO;
10924
10925         tx_len = 1514;
10926         skb = netdev_alloc_skb(tp->dev, tx_len);
10927         if (!skb)
10928                 return -ENOMEM;
10929
10930         tx_data = skb_put(skb, tx_len);
10931         memcpy(tx_data, tp->dev->dev_addr, 6);
10932         memset(tx_data + 6, 0x0, 8);
10933
10934         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10935
10936         for (i = 14; i < tx_len; i++)
10937                 tx_data[i] = (u8) (i & 0xff);
10938
10939         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10940         if (pci_dma_mapping_error(tp->pdev, map)) {
10941                 dev_kfree_skb(skb);
10942                 return -EIO;
10943         }
10944
10945         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10946                rnapi->coal_now);
10947
10948         udelay(10);
10949
10950         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10951
10952         num_pkts = 0;
10953
10954         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10955
10956         tnapi->tx_prod++;
10957         num_pkts++;
10958
10959         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10960         tr32_mailbox(tnapi->prodmbox);
10961
10962         udelay(10);
10963
10964         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10965         for (i = 0; i < 35; i++) {
10966                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10967                        coal_now);
10968
10969                 udelay(10);
10970
10971                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10972                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10973                 if ((tx_idx == tnapi->tx_prod) &&
10974                     (rx_idx == (rx_start_idx + num_pkts)))
10975                         break;
10976         }
10977
10978         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10979         dev_kfree_skb(skb);
10980
10981         if (tx_idx != tnapi->tx_prod)
10982                 goto out;
10983
10984         if (rx_idx != rx_start_idx + num_pkts)
10985                 goto out;
10986
10987         desc = &rnapi->rx_rcb[rx_start_idx];
10988         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10989         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10990         if (opaque_key != RXD_OPAQUE_RING_STD)
10991                 goto out;
10992
10993         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10994             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10995                 goto out;
10996
10997         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10998         if (rx_len != tx_len)
10999                 goto out;
11000
11001         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
11002
11003         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
11004         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
11005
11006         for (i = 14; i < tx_len; i++) {
11007                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
11008                         goto out;
11009         }
11010         err = 0;
11011
11012         /* tg3_free_rings will unmap and free the rx_skb */
11013 out:
11014         return err;
11015 }
11016
11017 #define TG3_MAC_LOOPBACK_FAILED         1
11018 #define TG3_PHY_LOOPBACK_FAILED         2
11019 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
11020                                          TG3_PHY_LOOPBACK_FAILED)
11021
11022 static int tg3_test_loopback(struct tg3 *tp)
11023 {
11024         int err = 0;
11025         u32 cpmuctrl = 0;
11026
11027         if (!netif_running(tp->dev))
11028                 return TG3_LOOPBACK_FAILED;
11029
11030         err = tg3_reset_hw(tp, 1);
11031         if (err)
11032                 return TG3_LOOPBACK_FAILED;
11033
11034         /* Turn off gphy autopowerdown. */
11035         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11036                 tg3_phy_toggle_apd(tp, false);
11037
11038         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11039                 int i;
11040                 u32 status;
11041
11042                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11043
11044                 /* Wait for up to 40 microseconds to acquire lock. */
11045                 for (i = 0; i < 4; i++) {
11046                         status = tr32(TG3_CPMU_MUTEX_GNT);
11047                         if (status == CPMU_MUTEX_GNT_DRIVER)
11048                                 break;
11049                         udelay(10);
11050                 }
11051
11052                 if (status != CPMU_MUTEX_GNT_DRIVER)
11053                         return TG3_LOOPBACK_FAILED;
11054
11055                 /* Turn off link-based power management. */
11056                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11057                 tw32(TG3_CPMU_CTRL,
11058                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11059                                   CPMU_CTRL_LINK_AWARE_MODE));
11060         }
11061
11062         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11063                 err |= TG3_MAC_LOOPBACK_FAILED;
11064
11065         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11066                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11067
11068                 /* Release the mutex */
11069                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11070         }
11071
11072         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11073             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11074                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11075                         err |= TG3_PHY_LOOPBACK_FAILED;
11076         }
11077
11078         /* Re-enable gphy autopowerdown. */
11079         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11080                 tg3_phy_toggle_apd(tp, true);
11081
11082         return err;
11083 }
11084
11085 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11086                           u64 *data)
11087 {
11088         struct tg3 *tp = netdev_priv(dev);
11089
11090         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11091                 tg3_set_power_state(tp, PCI_D0);
11092
11093         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11094
11095         if (tg3_test_nvram(tp) != 0) {
11096                 etest->flags |= ETH_TEST_FL_FAILED;
11097                 data[0] = 1;
11098         }
11099         if (tg3_test_link(tp) != 0) {
11100                 etest->flags |= ETH_TEST_FL_FAILED;
11101                 data[1] = 1;
11102         }
11103         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11104                 int err, err2 = 0, irq_sync = 0;
11105
11106                 if (netif_running(dev)) {
11107                         tg3_phy_stop(tp);
11108                         tg3_netif_stop(tp);
11109                         irq_sync = 1;
11110                 }
11111
11112                 tg3_full_lock(tp, irq_sync);
11113
11114                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11115                 err = tg3_nvram_lock(tp);
11116                 tg3_halt_cpu(tp, RX_CPU_BASE);
11117                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11118                         tg3_halt_cpu(tp, TX_CPU_BASE);
11119                 if (!err)
11120                         tg3_nvram_unlock(tp);
11121
11122                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11123                         tg3_phy_reset(tp);
11124
11125                 if (tg3_test_registers(tp) != 0) {
11126                         etest->flags |= ETH_TEST_FL_FAILED;
11127                         data[2] = 1;
11128                 }
11129                 if (tg3_test_memory(tp) != 0) {
11130                         etest->flags |= ETH_TEST_FL_FAILED;
11131                         data[3] = 1;
11132                 }
11133                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11134                         etest->flags |= ETH_TEST_FL_FAILED;
11135
11136                 tg3_full_unlock(tp);
11137
11138                 if (tg3_test_interrupt(tp) != 0) {
11139                         etest->flags |= ETH_TEST_FL_FAILED;
11140                         data[5] = 1;
11141                 }
11142
11143                 tg3_full_lock(tp, 0);
11144
11145                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11146                 if (netif_running(dev)) {
11147                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11148                         err2 = tg3_restart_hw(tp, 1);
11149                         if (!err2)
11150                                 tg3_netif_start(tp);
11151                 }
11152
11153                 tg3_full_unlock(tp);
11154
11155                 if (irq_sync && !err2)
11156                         tg3_phy_start(tp);
11157         }
11158         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11159                 tg3_set_power_state(tp, PCI_D3hot);
11160
11161 }
11162
11163 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11164 {
11165         struct mii_ioctl_data *data = if_mii(ifr);
11166         struct tg3 *tp = netdev_priv(dev);
11167         int err;
11168
11169         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11170                 struct phy_device *phydev;
11171                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11172                         return -EAGAIN;
11173                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11174                 return phy_mii_ioctl(phydev, ifr, cmd);
11175         }
11176
11177         switch (cmd) {
11178         case SIOCGMIIPHY:
11179                 data->phy_id = tp->phy_addr;
11180
11181                 /* fallthru */
11182         case SIOCGMIIREG: {
11183                 u32 mii_regval;
11184
11185                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11186                         break;                  /* We have no PHY */
11187
11188                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11189                         return -EAGAIN;
11190
11191                 spin_lock_bh(&tp->lock);
11192                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11193                 spin_unlock_bh(&tp->lock);
11194
11195                 data->val_out = mii_regval;
11196
11197                 return err;
11198         }
11199
11200         case SIOCSMIIREG:
11201                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11202                         break;                  /* We have no PHY */
11203
11204                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11205                         return -EAGAIN;
11206
11207                 spin_lock_bh(&tp->lock);
11208                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11209                 spin_unlock_bh(&tp->lock);
11210
11211                 return err;
11212
11213         default:
11214                 /* do nothing */
11215                 break;
11216         }
11217         return -EOPNOTSUPP;
11218 }
11219
11220 #if TG3_VLAN_TAG_USED
11221 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11222 {
11223         struct tg3 *tp = netdev_priv(dev);
11224
11225         if (!netif_running(dev)) {
11226                 tp->vlgrp = grp;
11227                 return;
11228         }
11229
11230         tg3_netif_stop(tp);
11231
11232         tg3_full_lock(tp, 0);
11233
11234         tp->vlgrp = grp;
11235
11236         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11237         __tg3_set_rx_mode(dev);
11238
11239         tg3_netif_start(tp);
11240
11241         tg3_full_unlock(tp);
11242 }
11243 #endif
11244
11245 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11246 {
11247         struct tg3 *tp = netdev_priv(dev);
11248
11249         memcpy(ec, &tp->coal, sizeof(*ec));
11250         return 0;
11251 }
11252
11253 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11254 {
11255         struct tg3 *tp = netdev_priv(dev);
11256         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11257         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11258
11259         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11260                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11261                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11262                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11263                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11264         }
11265
11266         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11267             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11268             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11269             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11270             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11271             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11272             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11273             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11274             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11275             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11276                 return -EINVAL;
11277
11278         /* No rx interrupts will be generated if both are zero */
11279         if ((ec->rx_coalesce_usecs == 0) &&
11280             (ec->rx_max_coalesced_frames == 0))
11281                 return -EINVAL;
11282
11283         /* No tx interrupts will be generated if both are zero */
11284         if ((ec->tx_coalesce_usecs == 0) &&
11285             (ec->tx_max_coalesced_frames == 0))
11286                 return -EINVAL;
11287
11288         /* Only copy relevant parameters, ignore all others. */
11289         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11290         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11291         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11292         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11293         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11294         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11295         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11296         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11297         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11298
11299         if (netif_running(dev)) {
11300                 tg3_full_lock(tp, 0);
11301                 __tg3_set_coalesce(tp, &tp->coal);
11302                 tg3_full_unlock(tp);
11303         }
11304         return 0;
11305 }
11306
11307 static const struct ethtool_ops tg3_ethtool_ops = {
11308         .get_settings           = tg3_get_settings,
11309         .set_settings           = tg3_set_settings,
11310         .get_drvinfo            = tg3_get_drvinfo,
11311         .get_regs_len           = tg3_get_regs_len,
11312         .get_regs               = tg3_get_regs,
11313         .get_wol                = tg3_get_wol,
11314         .set_wol                = tg3_set_wol,
11315         .get_msglevel           = tg3_get_msglevel,
11316         .set_msglevel           = tg3_set_msglevel,
11317         .nway_reset             = tg3_nway_reset,
11318         .get_link               = ethtool_op_get_link,
11319         .get_eeprom_len         = tg3_get_eeprom_len,
11320         .get_eeprom             = tg3_get_eeprom,
11321         .set_eeprom             = tg3_set_eeprom,
11322         .get_ringparam          = tg3_get_ringparam,
11323         .set_ringparam          = tg3_set_ringparam,
11324         .get_pauseparam         = tg3_get_pauseparam,
11325         .set_pauseparam         = tg3_set_pauseparam,
11326         .get_rx_csum            = tg3_get_rx_csum,
11327         .set_rx_csum            = tg3_set_rx_csum,
11328         .set_tx_csum            = tg3_set_tx_csum,
11329         .set_sg                 = ethtool_op_set_sg,
11330         .set_tso                = tg3_set_tso,
11331         .self_test              = tg3_self_test,
11332         .get_strings            = tg3_get_strings,
11333         .phys_id                = tg3_phys_id,
11334         .get_ethtool_stats      = tg3_get_ethtool_stats,
11335         .get_coalesce           = tg3_get_coalesce,
11336         .set_coalesce           = tg3_set_coalesce,
11337         .get_sset_count         = tg3_get_sset_count,
11338 };
11339
11340 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11341 {
11342         u32 cursize, val, magic;
11343
11344         tp->nvram_size = EEPROM_CHIP_SIZE;
11345
11346         if (tg3_nvram_read(tp, 0, &magic) != 0)
11347                 return;
11348
11349         if ((magic != TG3_EEPROM_MAGIC) &&
11350             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11351             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11352                 return;
11353
11354         /*
11355          * Size the chip by reading offsets at increasing powers of two.
11356          * When we encounter our validation signature, we know the addressing
11357          * has wrapped around, and thus have our chip size.
11358          */
11359         cursize = 0x10;
11360
11361         while (cursize < tp->nvram_size) {
11362                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11363                         return;
11364
11365                 if (val == magic)
11366                         break;
11367
11368                 cursize <<= 1;
11369         }
11370
11371         tp->nvram_size = cursize;
11372 }
11373
11374 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11375 {
11376         u32 val;
11377
11378         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11379             tg3_nvram_read(tp, 0, &val) != 0)
11380                 return;
11381
11382         /* Selfboot format */
11383         if (val != TG3_EEPROM_MAGIC) {
11384                 tg3_get_eeprom_size(tp);
11385                 return;
11386         }
11387
11388         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11389                 if (val != 0) {
11390                         /* This is confusing.  We want to operate on the
11391                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11392                          * call will read from NVRAM and byteswap the data
11393                          * according to the byteswapping settings for all
11394                          * other register accesses.  This ensures the data we
11395                          * want will always reside in the lower 16-bits.
11396                          * However, the data in NVRAM is in LE format, which
11397                          * means the data from the NVRAM read will always be
11398                          * opposite the endianness of the CPU.  The 16-bit
11399                          * byteswap then brings the data to CPU endianness.
11400                          */
11401                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11402                         return;
11403                 }
11404         }
11405         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11406 }
11407
11408 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11409 {
11410         u32 nvcfg1;
11411
11412         nvcfg1 = tr32(NVRAM_CFG1);
11413         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11414                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11415         } else {
11416                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11417                 tw32(NVRAM_CFG1, nvcfg1);
11418         }
11419
11420         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11421             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11422                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11423                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11424                         tp->nvram_jedecnum = JEDEC_ATMEL;
11425                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11426                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427                         break;
11428                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11429                         tp->nvram_jedecnum = JEDEC_ATMEL;
11430                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11431                         break;
11432                 case FLASH_VENDOR_ATMEL_EEPROM:
11433                         tp->nvram_jedecnum = JEDEC_ATMEL;
11434                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11435                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11436                         break;
11437                 case FLASH_VENDOR_ST:
11438                         tp->nvram_jedecnum = JEDEC_ST;
11439                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11440                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11441                         break;
11442                 case FLASH_VENDOR_SAIFUN:
11443                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11444                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11445                         break;
11446                 case FLASH_VENDOR_SST_SMALL:
11447                 case FLASH_VENDOR_SST_LARGE:
11448                         tp->nvram_jedecnum = JEDEC_SST;
11449                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11450                         break;
11451                 }
11452         } else {
11453                 tp->nvram_jedecnum = JEDEC_ATMEL;
11454                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11455                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11456         }
11457 }
11458
11459 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11460 {
11461         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11462         case FLASH_5752PAGE_SIZE_256:
11463                 tp->nvram_pagesize = 256;
11464                 break;
11465         case FLASH_5752PAGE_SIZE_512:
11466                 tp->nvram_pagesize = 512;
11467                 break;
11468         case FLASH_5752PAGE_SIZE_1K:
11469                 tp->nvram_pagesize = 1024;
11470                 break;
11471         case FLASH_5752PAGE_SIZE_2K:
11472                 tp->nvram_pagesize = 2048;
11473                 break;
11474         case FLASH_5752PAGE_SIZE_4K:
11475                 tp->nvram_pagesize = 4096;
11476                 break;
11477         case FLASH_5752PAGE_SIZE_264:
11478                 tp->nvram_pagesize = 264;
11479                 break;
11480         case FLASH_5752PAGE_SIZE_528:
11481                 tp->nvram_pagesize = 528;
11482                 break;
11483         }
11484 }
11485
11486 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11487 {
11488         u32 nvcfg1;
11489
11490         nvcfg1 = tr32(NVRAM_CFG1);
11491
11492         /* NVRAM protection for TPM */
11493         if (nvcfg1 & (1 << 27))
11494                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11495
11496         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11497         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11498         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11499                 tp->nvram_jedecnum = JEDEC_ATMEL;
11500                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11501                 break;
11502         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11503                 tp->nvram_jedecnum = JEDEC_ATMEL;
11504                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11505                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11506                 break;
11507         case FLASH_5752VENDOR_ST_M45PE10:
11508         case FLASH_5752VENDOR_ST_M45PE20:
11509         case FLASH_5752VENDOR_ST_M45PE40:
11510                 tp->nvram_jedecnum = JEDEC_ST;
11511                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11512                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11513                 break;
11514         }
11515
11516         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11517                 tg3_nvram_get_pagesize(tp, nvcfg1);
11518         } else {
11519                 /* For eeprom, set pagesize to maximum eeprom size */
11520                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11521
11522                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11523                 tw32(NVRAM_CFG1, nvcfg1);
11524         }
11525 }
11526
11527 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11528 {
11529         u32 nvcfg1, protect = 0;
11530
11531         nvcfg1 = tr32(NVRAM_CFG1);
11532
11533         /* NVRAM protection for TPM */
11534         if (nvcfg1 & (1 << 27)) {
11535                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11536                 protect = 1;
11537         }
11538
11539         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11540         switch (nvcfg1) {
11541         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11542         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11543         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11544         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11545                 tp->nvram_jedecnum = JEDEC_ATMEL;
11546                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11547                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11548                 tp->nvram_pagesize = 264;
11549                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11550                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11551                         tp->nvram_size = (protect ? 0x3e200 :
11552                                           TG3_NVRAM_SIZE_512KB);
11553                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11554                         tp->nvram_size = (protect ? 0x1f200 :
11555                                           TG3_NVRAM_SIZE_256KB);
11556                 else
11557                         tp->nvram_size = (protect ? 0x1f200 :
11558                                           TG3_NVRAM_SIZE_128KB);
11559                 break;
11560         case FLASH_5752VENDOR_ST_M45PE10:
11561         case FLASH_5752VENDOR_ST_M45PE20:
11562         case FLASH_5752VENDOR_ST_M45PE40:
11563                 tp->nvram_jedecnum = JEDEC_ST;
11564                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11565                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11566                 tp->nvram_pagesize = 256;
11567                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11568                         tp->nvram_size = (protect ?
11569                                           TG3_NVRAM_SIZE_64KB :
11570                                           TG3_NVRAM_SIZE_128KB);
11571                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11572                         tp->nvram_size = (protect ?
11573                                           TG3_NVRAM_SIZE_64KB :
11574                                           TG3_NVRAM_SIZE_256KB);
11575                 else
11576                         tp->nvram_size = (protect ?
11577                                           TG3_NVRAM_SIZE_128KB :
11578                                           TG3_NVRAM_SIZE_512KB);
11579                 break;
11580         }
11581 }
11582
11583 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11584 {
11585         u32 nvcfg1;
11586
11587         nvcfg1 = tr32(NVRAM_CFG1);
11588
11589         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11590         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11591         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11592         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11593         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11594                 tp->nvram_jedecnum = JEDEC_ATMEL;
11595                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11596                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11597
11598                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11599                 tw32(NVRAM_CFG1, nvcfg1);
11600                 break;
11601         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11602         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11603         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11604         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11605                 tp->nvram_jedecnum = JEDEC_ATMEL;
11606                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11607                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11608                 tp->nvram_pagesize = 264;
11609                 break;
11610         case FLASH_5752VENDOR_ST_M45PE10:
11611         case FLASH_5752VENDOR_ST_M45PE20:
11612         case FLASH_5752VENDOR_ST_M45PE40:
11613                 tp->nvram_jedecnum = JEDEC_ST;
11614                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11615                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11616                 tp->nvram_pagesize = 256;
11617                 break;
11618         }
11619 }
11620
11621 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11622 {
11623         u32 nvcfg1, protect = 0;
11624
11625         nvcfg1 = tr32(NVRAM_CFG1);
11626
11627         /* NVRAM protection for TPM */
11628         if (nvcfg1 & (1 << 27)) {
11629                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11630                 protect = 1;
11631         }
11632
11633         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11634         switch (nvcfg1) {
11635         case FLASH_5761VENDOR_ATMEL_ADB021D:
11636         case FLASH_5761VENDOR_ATMEL_ADB041D:
11637         case FLASH_5761VENDOR_ATMEL_ADB081D:
11638         case FLASH_5761VENDOR_ATMEL_ADB161D:
11639         case FLASH_5761VENDOR_ATMEL_MDB021D:
11640         case FLASH_5761VENDOR_ATMEL_MDB041D:
11641         case FLASH_5761VENDOR_ATMEL_MDB081D:
11642         case FLASH_5761VENDOR_ATMEL_MDB161D:
11643                 tp->nvram_jedecnum = JEDEC_ATMEL;
11644                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11645                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11646                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11647                 tp->nvram_pagesize = 256;
11648                 break;
11649         case FLASH_5761VENDOR_ST_A_M45PE20:
11650         case FLASH_5761VENDOR_ST_A_M45PE40:
11651         case FLASH_5761VENDOR_ST_A_M45PE80:
11652         case FLASH_5761VENDOR_ST_A_M45PE16:
11653         case FLASH_5761VENDOR_ST_M_M45PE20:
11654         case FLASH_5761VENDOR_ST_M_M45PE40:
11655         case FLASH_5761VENDOR_ST_M_M45PE80:
11656         case FLASH_5761VENDOR_ST_M_M45PE16:
11657                 tp->nvram_jedecnum = JEDEC_ST;
11658                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11659                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11660                 tp->nvram_pagesize = 256;
11661                 break;
11662         }
11663
11664         if (protect) {
11665                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11666         } else {
11667                 switch (nvcfg1) {
11668                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11669                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11670                 case FLASH_5761VENDOR_ST_A_M45PE16:
11671                 case FLASH_5761VENDOR_ST_M_M45PE16:
11672                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11673                         break;
11674                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11675                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11676                 case FLASH_5761VENDOR_ST_A_M45PE80:
11677                 case FLASH_5761VENDOR_ST_M_M45PE80:
11678                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11679                         break;
11680                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11681                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11682                 case FLASH_5761VENDOR_ST_A_M45PE40:
11683                 case FLASH_5761VENDOR_ST_M_M45PE40:
11684                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11685                         break;
11686                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11687                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11688                 case FLASH_5761VENDOR_ST_A_M45PE20:
11689                 case FLASH_5761VENDOR_ST_M_M45PE20:
11690                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11691                         break;
11692                 }
11693         }
11694 }
11695
11696 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11697 {
11698         tp->nvram_jedecnum = JEDEC_ATMEL;
11699         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11700         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11701 }
11702
11703 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11704 {
11705         u32 nvcfg1;
11706
11707         nvcfg1 = tr32(NVRAM_CFG1);
11708
11709         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11710         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11711         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11712                 tp->nvram_jedecnum = JEDEC_ATMEL;
11713                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11714                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11715
11716                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11717                 tw32(NVRAM_CFG1, nvcfg1);
11718                 return;
11719         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11720         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11721         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11722         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11723         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11724         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11725         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11726                 tp->nvram_jedecnum = JEDEC_ATMEL;
11727                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11728                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11729
11730                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11731                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11732                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11733                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11734                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11735                         break;
11736                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11737                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11738                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11739                         break;
11740                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11741                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11742                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11743                         break;
11744                 }
11745                 break;
11746         case FLASH_5752VENDOR_ST_M45PE10:
11747         case FLASH_5752VENDOR_ST_M45PE20:
11748         case FLASH_5752VENDOR_ST_M45PE40:
11749                 tp->nvram_jedecnum = JEDEC_ST;
11750                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11751                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11752
11753                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11754                 case FLASH_5752VENDOR_ST_M45PE10:
11755                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11756                         break;
11757                 case FLASH_5752VENDOR_ST_M45PE20:
11758                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11759                         break;
11760                 case FLASH_5752VENDOR_ST_M45PE40:
11761                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11762                         break;
11763                 }
11764                 break;
11765         default:
11766                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11767                 return;
11768         }
11769
11770         tg3_nvram_get_pagesize(tp, nvcfg1);
11771         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11772                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11773 }
11774
11775
11776 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11777 {
11778         u32 nvcfg1;
11779
11780         nvcfg1 = tr32(NVRAM_CFG1);
11781
11782         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11783         case FLASH_5717VENDOR_ATMEL_EEPROM:
11784         case FLASH_5717VENDOR_MICRO_EEPROM:
11785                 tp->nvram_jedecnum = JEDEC_ATMEL;
11786                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11787                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11788
11789                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11790                 tw32(NVRAM_CFG1, nvcfg1);
11791                 return;
11792         case FLASH_5717VENDOR_ATMEL_MDB011D:
11793         case FLASH_5717VENDOR_ATMEL_ADB011B:
11794         case FLASH_5717VENDOR_ATMEL_ADB011D:
11795         case FLASH_5717VENDOR_ATMEL_MDB021D:
11796         case FLASH_5717VENDOR_ATMEL_ADB021B:
11797         case FLASH_5717VENDOR_ATMEL_ADB021D:
11798         case FLASH_5717VENDOR_ATMEL_45USPT:
11799                 tp->nvram_jedecnum = JEDEC_ATMEL;
11800                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11801                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11802
11803                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11804                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11805                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11806                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11807                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11808                         break;
11809                 default:
11810                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11811                         break;
11812                 }
11813                 break;
11814         case FLASH_5717VENDOR_ST_M_M25PE10:
11815         case FLASH_5717VENDOR_ST_A_M25PE10:
11816         case FLASH_5717VENDOR_ST_M_M45PE10:
11817         case FLASH_5717VENDOR_ST_A_M45PE10:
11818         case FLASH_5717VENDOR_ST_M_M25PE20:
11819         case FLASH_5717VENDOR_ST_A_M25PE20:
11820         case FLASH_5717VENDOR_ST_M_M45PE20:
11821         case FLASH_5717VENDOR_ST_A_M45PE20:
11822         case FLASH_5717VENDOR_ST_25USPT:
11823         case FLASH_5717VENDOR_ST_45USPT:
11824                 tp->nvram_jedecnum = JEDEC_ST;
11825                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11826                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11827
11828                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11829                 case FLASH_5717VENDOR_ST_M_M25PE20:
11830                 case FLASH_5717VENDOR_ST_A_M25PE20:
11831                 case FLASH_5717VENDOR_ST_M_M45PE20:
11832                 case FLASH_5717VENDOR_ST_A_M45PE20:
11833                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11834                         break;
11835                 default:
11836                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11837                         break;
11838                 }
11839                 break;
11840         default:
11841                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11842                 return;
11843         }
11844
11845         tg3_nvram_get_pagesize(tp, nvcfg1);
11846         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11847                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11848 }
11849
11850 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11851 static void __devinit tg3_nvram_init(struct tg3 *tp)
11852 {
11853         tw32_f(GRC_EEPROM_ADDR,
11854              (EEPROM_ADDR_FSM_RESET |
11855               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11856                EEPROM_ADDR_CLKPERD_SHIFT)));
11857
11858         msleep(1);
11859
11860         /* Enable seeprom accesses. */
11861         tw32_f(GRC_LOCAL_CTRL,
11862              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11863         udelay(100);
11864
11865         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11866             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11867                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11868
11869                 if (tg3_nvram_lock(tp)) {
11870                         netdev_warn(tp->dev,
11871                                     "Cannot get nvram lock, %s failed\n",
11872                                     __func__);
11873                         return;
11874                 }
11875                 tg3_enable_nvram_access(tp);
11876
11877                 tp->nvram_size = 0;
11878
11879                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11880                         tg3_get_5752_nvram_info(tp);
11881                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11882                         tg3_get_5755_nvram_info(tp);
11883                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11884                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11885                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11886                         tg3_get_5787_nvram_info(tp);
11887                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11888                         tg3_get_5761_nvram_info(tp);
11889                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11890                         tg3_get_5906_nvram_info(tp);
11891                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11892                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11893                         tg3_get_57780_nvram_info(tp);
11894                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11895                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11896                         tg3_get_5717_nvram_info(tp);
11897                 else
11898                         tg3_get_nvram_info(tp);
11899
11900                 if (tp->nvram_size == 0)
11901                         tg3_get_nvram_size(tp);
11902
11903                 tg3_disable_nvram_access(tp);
11904                 tg3_nvram_unlock(tp);
11905
11906         } else {
11907                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11908
11909                 tg3_get_eeprom_size(tp);
11910         }
11911 }
11912
11913 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11914                                     u32 offset, u32 len, u8 *buf)
11915 {
11916         int i, j, rc = 0;
11917         u32 val;
11918
11919         for (i = 0; i < len; i += 4) {
11920                 u32 addr;
11921                 __be32 data;
11922
11923                 addr = offset + i;
11924
11925                 memcpy(&data, buf + i, 4);
11926
11927                 /*
11928                  * The SEEPROM interface expects the data to always be opposite
11929                  * the native endian format.  We accomplish this by reversing
11930                  * all the operations that would have been performed on the
11931                  * data from a call to tg3_nvram_read_be32().
11932                  */
11933                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11934
11935                 val = tr32(GRC_EEPROM_ADDR);
11936                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11937
11938                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11939                         EEPROM_ADDR_READ);
11940                 tw32(GRC_EEPROM_ADDR, val |
11941                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11942                         (addr & EEPROM_ADDR_ADDR_MASK) |
11943                         EEPROM_ADDR_START |
11944                         EEPROM_ADDR_WRITE);
11945
11946                 for (j = 0; j < 1000; j++) {
11947                         val = tr32(GRC_EEPROM_ADDR);
11948
11949                         if (val & EEPROM_ADDR_COMPLETE)
11950                                 break;
11951                         msleep(1);
11952                 }
11953                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11954                         rc = -EBUSY;
11955                         break;
11956                 }
11957         }
11958
11959         return rc;
11960 }
11961
11962 /* offset and length are dword aligned */
11963 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11964                 u8 *buf)
11965 {
11966         int ret = 0;
11967         u32 pagesize = tp->nvram_pagesize;
11968         u32 pagemask = pagesize - 1;
11969         u32 nvram_cmd;
11970         u8 *tmp;
11971
11972         tmp = kmalloc(pagesize, GFP_KERNEL);
11973         if (tmp == NULL)
11974                 return -ENOMEM;
11975
11976         while (len) {
11977                 int j;
11978                 u32 phy_addr, page_off, size;
11979
11980                 phy_addr = offset & ~pagemask;
11981
11982                 for (j = 0; j < pagesize; j += 4) {
11983                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11984                                                   (__be32 *) (tmp + j));
11985                         if (ret)
11986                                 break;
11987                 }
11988                 if (ret)
11989                         break;
11990
11991                 page_off = offset & pagemask;
11992                 size = pagesize;
11993                 if (len < size)
11994                         size = len;
11995
11996                 len -= size;
11997
11998                 memcpy(tmp + page_off, buf, size);
11999
12000                 offset = offset + (pagesize - page_off);
12001
12002                 tg3_enable_nvram_access(tp);
12003
12004                 /*
12005                  * Before we can erase the flash page, we need
12006                  * to issue a special "write enable" command.
12007                  */
12008                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12009
12010                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12011                         break;
12012
12013                 /* Erase the target page */
12014                 tw32(NVRAM_ADDR, phy_addr);
12015
12016                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
12017                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
12018
12019                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12020                         break;
12021
12022                 /* Issue another write enable to start the write. */
12023                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12024
12025                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12026                         break;
12027
12028                 for (j = 0; j < pagesize; j += 4) {
12029                         __be32 data;
12030
12031                         data = *((__be32 *) (tmp + j));
12032
12033                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12034
12035                         tw32(NVRAM_ADDR, phy_addr + j);
12036
12037                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12038                                 NVRAM_CMD_WR;
12039
12040                         if (j == 0)
12041                                 nvram_cmd |= NVRAM_CMD_FIRST;
12042                         else if (j == (pagesize - 4))
12043                                 nvram_cmd |= NVRAM_CMD_LAST;
12044
12045                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12046                                 break;
12047                 }
12048                 if (ret)
12049                         break;
12050         }
12051
12052         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12053         tg3_nvram_exec_cmd(tp, nvram_cmd);
12054
12055         kfree(tmp);
12056
12057         return ret;
12058 }
12059
12060 /* offset and length are dword aligned */
12061 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12062                 u8 *buf)
12063 {
12064         int i, ret = 0;
12065
12066         for (i = 0; i < len; i += 4, offset += 4) {
12067                 u32 page_off, phy_addr, nvram_cmd;
12068                 __be32 data;
12069
12070                 memcpy(&data, buf + i, 4);
12071                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12072
12073                 page_off = offset % tp->nvram_pagesize;
12074
12075                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12076
12077                 tw32(NVRAM_ADDR, phy_addr);
12078
12079                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12080
12081                 if (page_off == 0 || i == 0)
12082                         nvram_cmd |= NVRAM_CMD_FIRST;
12083                 if (page_off == (tp->nvram_pagesize - 4))
12084                         nvram_cmd |= NVRAM_CMD_LAST;
12085
12086                 if (i == (len - 4))
12087                         nvram_cmd |= NVRAM_CMD_LAST;
12088
12089                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12090                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12091                     (tp->nvram_jedecnum == JEDEC_ST) &&
12092                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12093
12094                         if ((ret = tg3_nvram_exec_cmd(tp,
12095                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12096                                 NVRAM_CMD_DONE)))
12097
12098                                 break;
12099                 }
12100                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12101                         /* We always do complete word writes to eeprom. */
12102                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12103                 }
12104
12105                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12106                         break;
12107         }
12108         return ret;
12109 }
12110
12111 /* offset and length are dword aligned */
12112 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12113 {
12114         int ret;
12115
12116         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12117                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12118                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12119                 udelay(40);
12120         }
12121
12122         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12123                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12124         } else {
12125                 u32 grc_mode;
12126
12127                 ret = tg3_nvram_lock(tp);
12128                 if (ret)
12129                         return ret;
12130
12131                 tg3_enable_nvram_access(tp);
12132                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12133                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12134                         tw32(NVRAM_WRITE1, 0x406);
12135
12136                 grc_mode = tr32(GRC_MODE);
12137                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12138
12139                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12140                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12141
12142                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12143                                 buf);
12144                 } else {
12145                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12146                                 buf);
12147                 }
12148
12149                 grc_mode = tr32(GRC_MODE);
12150                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12151
12152                 tg3_disable_nvram_access(tp);
12153                 tg3_nvram_unlock(tp);
12154         }
12155
12156         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12157                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12158                 udelay(40);
12159         }
12160
12161         return ret;
12162 }
12163
12164 struct subsys_tbl_ent {
12165         u16 subsys_vendor, subsys_devid;
12166         u32 phy_id;
12167 };
12168
12169 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12170         /* Broadcom boards. */
12171         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12172           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12173         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12174           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12175         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12176           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12177         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12178           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12179         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12180           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12181         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12182           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12183         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12184           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12185         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12186           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12187         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12188           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12189         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12190           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12191         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12192           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12193
12194         /* 3com boards. */
12195         { TG3PCI_SUBVENDOR_ID_3COM,
12196           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12197         { TG3PCI_SUBVENDOR_ID_3COM,
12198           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12199         { TG3PCI_SUBVENDOR_ID_3COM,
12200           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12201         { TG3PCI_SUBVENDOR_ID_3COM,
12202           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12203         { TG3PCI_SUBVENDOR_ID_3COM,
12204           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12205
12206         /* DELL boards. */
12207         { TG3PCI_SUBVENDOR_ID_DELL,
12208           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12209         { TG3PCI_SUBVENDOR_ID_DELL,
12210           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12211         { TG3PCI_SUBVENDOR_ID_DELL,
12212           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12213         { TG3PCI_SUBVENDOR_ID_DELL,
12214           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12215
12216         /* Compaq boards. */
12217         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12218           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12219         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12220           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12221         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12222           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12223         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12224           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12225         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12226           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12227
12228         /* IBM boards. */
12229         { TG3PCI_SUBVENDOR_ID_IBM,
12230           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12231 };
12232
12233 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12234 {
12235         int i;
12236
12237         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12238                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12239                      tp->pdev->subsystem_vendor) &&
12240                     (subsys_id_to_phy_id[i].subsys_devid ==
12241                      tp->pdev->subsystem_device))
12242                         return &subsys_id_to_phy_id[i];
12243         }
12244         return NULL;
12245 }
12246
12247 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12248 {
12249         u32 val;
12250         u16 pmcsr;
12251
12252         /* On some early chips the SRAM cannot be accessed in D3hot state,
12253          * so need make sure we're in D0.
12254          */
12255         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12256         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12257         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12258         msleep(1);
12259
12260         /* Make sure register accesses (indirect or otherwise)
12261          * will function correctly.
12262          */
12263         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12264                                tp->misc_host_ctrl);
12265
12266         /* The memory arbiter has to be enabled in order for SRAM accesses
12267          * to succeed.  Normally on powerup the tg3 chip firmware will make
12268          * sure it is enabled, but other entities such as system netboot
12269          * code might disable it.
12270          */
12271         val = tr32(MEMARB_MODE);
12272         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12273
12274         tp->phy_id = TG3_PHY_ID_INVALID;
12275         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12276
12277         /* Assume an onboard device and WOL capable by default.  */
12278         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12279
12280         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12281                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12282                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12283                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12284                 }
12285                 val = tr32(VCPU_CFGSHDW);
12286                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12287                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12288                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12289                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12290                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12291                 goto done;
12292         }
12293
12294         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12295         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12296                 u32 nic_cfg, led_cfg;
12297                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12298                 int eeprom_phy_serdes = 0;
12299
12300                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12301                 tp->nic_sram_data_cfg = nic_cfg;
12302
12303                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12304                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12305                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12306                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12307                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12308                     (ver > 0) && (ver < 0x100))
12309                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12310
12311                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12312                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12313
12314                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12315                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12316                         eeprom_phy_serdes = 1;
12317
12318                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12319                 if (nic_phy_id != 0) {
12320                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12321                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12322
12323                         eeprom_phy_id  = (id1 >> 16) << 10;
12324                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12325                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12326                 } else
12327                         eeprom_phy_id = 0;
12328
12329                 tp->phy_id = eeprom_phy_id;
12330                 if (eeprom_phy_serdes) {
12331                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12332                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12333                         else
12334                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12335                 }
12336
12337                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12338                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12339                                     SHASTA_EXT_LED_MODE_MASK);
12340                 else
12341                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12342
12343                 switch (led_cfg) {
12344                 default:
12345                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12346                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12347                         break;
12348
12349                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12350                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12351                         break;
12352
12353                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12354                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12355
12356                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12357                          * read on some older 5700/5701 bootcode.
12358                          */
12359                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12360                             ASIC_REV_5700 ||
12361                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12362                             ASIC_REV_5701)
12363                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12364
12365                         break;
12366
12367                 case SHASTA_EXT_LED_SHARED:
12368                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12369                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12370                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12371                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12372                                                  LED_CTRL_MODE_PHY_2);
12373                         break;
12374
12375                 case SHASTA_EXT_LED_MAC:
12376                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12377                         break;
12378
12379                 case SHASTA_EXT_LED_COMBO:
12380                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12381                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12382                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12383                                                  LED_CTRL_MODE_PHY_2);
12384                         break;
12385
12386                 }
12387
12388                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12389                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12390                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12391                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12392
12393                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12394                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12395
12396                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12397                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12398                         if ((tp->pdev->subsystem_vendor ==
12399                              PCI_VENDOR_ID_ARIMA) &&
12400                             (tp->pdev->subsystem_device == 0x205a ||
12401                              tp->pdev->subsystem_device == 0x2063))
12402                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12403                 } else {
12404                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12405                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12406                 }
12407
12408                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12409                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12410                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12411                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12412                 }
12413
12414                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12415                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12416                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12417
12418                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12419                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12420                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12421
12422                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12423                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12424                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12425
12426                 if (cfg2 & (1 << 17))
12427                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12428
12429                 /* serdes signal pre-emphasis in register 0x590 set by */
12430                 /* bootcode if bit 18 is set */
12431                 if (cfg2 & (1 << 18))
12432                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12433
12434                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12435                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12436                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12437                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12438
12439                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12440                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12441                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12442                         u32 cfg3;
12443
12444                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12445                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12446                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12447                 }
12448
12449                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12450                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12451                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12452                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12453                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12454                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12455         }
12456 done:
12457         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12458         device_set_wakeup_enable(&tp->pdev->dev,
12459                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12460 }
12461
12462 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12463 {
12464         int i;
12465         u32 val;
12466
12467         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12468         tw32(OTP_CTRL, cmd);
12469
12470         /* Wait for up to 1 ms for command to execute. */
12471         for (i = 0; i < 100; i++) {
12472                 val = tr32(OTP_STATUS);
12473                 if (val & OTP_STATUS_CMD_DONE)
12474                         break;
12475                 udelay(10);
12476         }
12477
12478         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12479 }
12480
12481 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12482  * configuration is a 32-bit value that straddles the alignment boundary.
12483  * We do two 32-bit reads and then shift and merge the results.
12484  */
12485 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12486 {
12487         u32 bhalf_otp, thalf_otp;
12488
12489         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12490
12491         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12492                 return 0;
12493
12494         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12495
12496         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12497                 return 0;
12498
12499         thalf_otp = tr32(OTP_READ_DATA);
12500
12501         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12502
12503         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12504                 return 0;
12505
12506         bhalf_otp = tr32(OTP_READ_DATA);
12507
12508         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12509 }
12510
12511 static int __devinit tg3_phy_probe(struct tg3 *tp)
12512 {
12513         u32 hw_phy_id_1, hw_phy_id_2;
12514         u32 hw_phy_id, hw_phy_id_masked;
12515         int err;
12516
12517         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12518                 return tg3_phy_init(tp);
12519
12520         /* Reading the PHY ID register can conflict with ASF
12521          * firmware access to the PHY hardware.
12522          */
12523         err = 0;
12524         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12525             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12526                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12527         } else {
12528                 /* Now read the physical PHY_ID from the chip and verify
12529                  * that it is sane.  If it doesn't look good, we fall back
12530                  * to either the hard-coded table based PHY_ID and failing
12531                  * that the value found in the eeprom area.
12532                  */
12533                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12534                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12535
12536                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12537                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12538                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12539
12540                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12541         }
12542
12543         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12544                 tp->phy_id = hw_phy_id;
12545                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12546                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12547                 else
12548                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12549         } else {
12550                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12551                         /* Do nothing, phy ID already set up in
12552                          * tg3_get_eeprom_hw_cfg().
12553                          */
12554                 } else {
12555                         struct subsys_tbl_ent *p;
12556
12557                         /* No eeprom signature?  Try the hardcoded
12558                          * subsys device table.
12559                          */
12560                         p = tg3_lookup_by_subsys(tp);
12561                         if (!p)
12562                                 return -ENODEV;
12563
12564                         tp->phy_id = p->phy_id;
12565                         if (!tp->phy_id ||
12566                             tp->phy_id == TG3_PHY_ID_BCM8002)
12567                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12568                 }
12569         }
12570
12571         if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12572             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12573              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12574                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12575
12576         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12577             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12578             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12579                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12580
12581                 tg3_readphy(tp, MII_BMSR, &bmsr);
12582                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12583                     (bmsr & BMSR_LSTATUS))
12584                         goto skip_phy_reset;
12585
12586                 err = tg3_phy_reset(tp);
12587                 if (err)
12588                         return err;
12589
12590                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12591                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12592                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12593                 tg3_ctrl = 0;
12594                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12595                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12596                                     MII_TG3_CTRL_ADV_1000_FULL);
12597                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12598                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12599                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12600                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12601                 }
12602
12603                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12604                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12605                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12606                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12607                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12608
12609                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12610                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12611
12612                         tg3_writephy(tp, MII_BMCR,
12613                                      BMCR_ANENABLE | BMCR_ANRESTART);
12614                 }
12615                 tg3_phy_set_wirespeed(tp);
12616
12617                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12618                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12619                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12620         }
12621
12622 skip_phy_reset:
12623         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12624                 err = tg3_init_5401phy_dsp(tp);
12625                 if (err)
12626                         return err;
12627
12628                 err = tg3_init_5401phy_dsp(tp);
12629         }
12630
12631         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12632                 tp->link_config.advertising =
12633                         (ADVERTISED_1000baseT_Half |
12634                          ADVERTISED_1000baseT_Full |
12635                          ADVERTISED_Autoneg |
12636                          ADVERTISED_FIBRE);
12637         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12638                 tp->link_config.advertising &=
12639                         ~(ADVERTISED_1000baseT_Half |
12640                           ADVERTISED_1000baseT_Full);
12641
12642         return err;
12643 }
12644
12645 static void __devinit tg3_read_vpd(struct tg3 *tp)
12646 {
12647         u8 *vpd_data;
12648         unsigned int block_end, rosize, len;
12649         int j, i = 0;
12650         u32 magic;
12651
12652         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12653             tg3_nvram_read(tp, 0x0, &magic))
12654                 goto out_no_vpd;
12655
12656         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12657         if (!vpd_data)
12658                 goto out_no_vpd;
12659
12660         if (magic == TG3_EEPROM_MAGIC) {
12661                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12662                         u32 tmp;
12663
12664                         /* The data is in little-endian format in NVRAM.
12665                          * Use the big-endian read routines to preserve
12666                          * the byte order as it exists in NVRAM.
12667                          */
12668                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12669                                 goto out_not_found;
12670
12671                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12672                 }
12673         } else {
12674                 ssize_t cnt;
12675                 unsigned int pos = 0;
12676
12677                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12678                         cnt = pci_read_vpd(tp->pdev, pos,
12679                                            TG3_NVM_VPD_LEN - pos,
12680                                            &vpd_data[pos]);
12681                         if (cnt == -ETIMEDOUT || -EINTR)
12682                                 cnt = 0;
12683                         else if (cnt < 0)
12684                                 goto out_not_found;
12685                 }
12686                 if (pos != TG3_NVM_VPD_LEN)
12687                         goto out_not_found;
12688         }
12689
12690         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12691                              PCI_VPD_LRDT_RO_DATA);
12692         if (i < 0)
12693                 goto out_not_found;
12694
12695         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12696         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12697         i += PCI_VPD_LRDT_TAG_SIZE;
12698
12699         if (block_end > TG3_NVM_VPD_LEN)
12700                 goto out_not_found;
12701
12702         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12703                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12704         if (j > 0) {
12705                 len = pci_vpd_info_field_size(&vpd_data[j]);
12706
12707                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12708                 if (j + len > block_end || len != 4 ||
12709                     memcmp(&vpd_data[j], "1028", 4))
12710                         goto partno;
12711
12712                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12713                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12714                 if (j < 0)
12715                         goto partno;
12716
12717                 len = pci_vpd_info_field_size(&vpd_data[j]);
12718
12719                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12720                 if (j + len > block_end)
12721                         goto partno;
12722
12723                 memcpy(tp->fw_ver, &vpd_data[j], len);
12724                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12725         }
12726
12727 partno:
12728         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12729                                       PCI_VPD_RO_KEYWORD_PARTNO);
12730         if (i < 0)
12731                 goto out_not_found;
12732
12733         len = pci_vpd_info_field_size(&vpd_data[i]);
12734
12735         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12736         if (len > TG3_BPN_SIZE ||
12737             (len + i) > TG3_NVM_VPD_LEN)
12738                 goto out_not_found;
12739
12740         memcpy(tp->board_part_number, &vpd_data[i], len);
12741
12742 out_not_found:
12743         kfree(vpd_data);
12744         if (tp->board_part_number[0])
12745                 return;
12746
12747 out_no_vpd:
12748         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12749                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12750                         strcpy(tp->board_part_number, "BCM5717");
12751                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12752                         strcpy(tp->board_part_number, "BCM5718");
12753                 else
12754                         goto nomatch;
12755         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12756                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12757                         strcpy(tp->board_part_number, "BCM57780");
12758                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12759                         strcpy(tp->board_part_number, "BCM57760");
12760                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12761                         strcpy(tp->board_part_number, "BCM57790");
12762                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12763                         strcpy(tp->board_part_number, "BCM57788");
12764                 else
12765                         goto nomatch;
12766         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12767                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12768                         strcpy(tp->board_part_number, "BCM57761");
12769                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12770                         strcpy(tp->board_part_number, "BCM57765");
12771                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12772                         strcpy(tp->board_part_number, "BCM57781");
12773                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12774                         strcpy(tp->board_part_number, "BCM57785");
12775                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12776                         strcpy(tp->board_part_number, "BCM57791");
12777                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12778                         strcpy(tp->board_part_number, "BCM57795");
12779                 else
12780                         goto nomatch;
12781         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12782                 strcpy(tp->board_part_number, "BCM95906");
12783         } else {
12784 nomatch:
12785                 strcpy(tp->board_part_number, "none");
12786         }
12787 }
12788
12789 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12790 {
12791         u32 val;
12792
12793         if (tg3_nvram_read(tp, offset, &val) ||
12794             (val & 0xfc000000) != 0x0c000000 ||
12795             tg3_nvram_read(tp, offset + 4, &val) ||
12796             val != 0)
12797                 return 0;
12798
12799         return 1;
12800 }
12801
12802 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12803 {
12804         u32 val, offset, start, ver_offset;
12805         int i, dst_off;
12806         bool newver = false;
12807
12808         if (tg3_nvram_read(tp, 0xc, &offset) ||
12809             tg3_nvram_read(tp, 0x4, &start))
12810                 return;
12811
12812         offset = tg3_nvram_logical_addr(tp, offset);
12813
12814         if (tg3_nvram_read(tp, offset, &val))
12815                 return;
12816
12817         if ((val & 0xfc000000) == 0x0c000000) {
12818                 if (tg3_nvram_read(tp, offset + 4, &val))
12819                         return;
12820
12821                 if (val == 0)
12822                         newver = true;
12823         }
12824
12825         dst_off = strlen(tp->fw_ver);
12826
12827         if (newver) {
12828                 if (TG3_VER_SIZE - dst_off < 16 ||
12829                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12830                         return;
12831
12832                 offset = offset + ver_offset - start;
12833                 for (i = 0; i < 16; i += 4) {
12834                         __be32 v;
12835                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12836                                 return;
12837
12838                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12839                 }
12840         } else {
12841                 u32 major, minor;
12842
12843                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12844                         return;
12845
12846                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12847                         TG3_NVM_BCVER_MAJSFT;
12848                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12849                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12850                          "v%d.%02d", major, minor);
12851         }
12852 }
12853
12854 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12855 {
12856         u32 val, major, minor;
12857
12858         /* Use native endian representation */
12859         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12860                 return;
12861
12862         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12863                 TG3_NVM_HWSB_CFG1_MAJSFT;
12864         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12865                 TG3_NVM_HWSB_CFG1_MINSFT;
12866
12867         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12868 }
12869
12870 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12871 {
12872         u32 offset, major, minor, build;
12873
12874         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12875
12876         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12877                 return;
12878
12879         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12880         case TG3_EEPROM_SB_REVISION_0:
12881                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12882                 break;
12883         case TG3_EEPROM_SB_REVISION_2:
12884                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12885                 break;
12886         case TG3_EEPROM_SB_REVISION_3:
12887                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12888                 break;
12889         case TG3_EEPROM_SB_REVISION_4:
12890                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12891                 break;
12892         case TG3_EEPROM_SB_REVISION_5:
12893                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12894                 break;
12895         case TG3_EEPROM_SB_REVISION_6:
12896                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12897                 break;
12898         default:
12899                 return;
12900         }
12901
12902         if (tg3_nvram_read(tp, offset, &val))
12903                 return;
12904
12905         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12906                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12907         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12908                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12909         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12910
12911         if (minor > 99 || build > 26)
12912                 return;
12913
12914         offset = strlen(tp->fw_ver);
12915         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12916                  " v%d.%02d", major, minor);
12917
12918         if (build > 0) {
12919                 offset = strlen(tp->fw_ver);
12920                 if (offset < TG3_VER_SIZE - 1)
12921                         tp->fw_ver[offset] = 'a' + build - 1;
12922         }
12923 }
12924
12925 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12926 {
12927         u32 val, offset, start;
12928         int i, vlen;
12929
12930         for (offset = TG3_NVM_DIR_START;
12931              offset < TG3_NVM_DIR_END;
12932              offset += TG3_NVM_DIRENT_SIZE) {
12933                 if (tg3_nvram_read(tp, offset, &val))
12934                         return;
12935
12936                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12937                         break;
12938         }
12939
12940         if (offset == TG3_NVM_DIR_END)
12941                 return;
12942
12943         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12944                 start = 0x08000000;
12945         else if (tg3_nvram_read(tp, offset - 4, &start))
12946                 return;
12947
12948         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12949             !tg3_fw_img_is_valid(tp, offset) ||
12950             tg3_nvram_read(tp, offset + 8, &val))
12951                 return;
12952
12953         offset += val - start;
12954
12955         vlen = strlen(tp->fw_ver);
12956
12957         tp->fw_ver[vlen++] = ',';
12958         tp->fw_ver[vlen++] = ' ';
12959
12960         for (i = 0; i < 4; i++) {
12961                 __be32 v;
12962                 if (tg3_nvram_read_be32(tp, offset, &v))
12963                         return;
12964
12965                 offset += sizeof(v);
12966
12967                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12968                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12969                         break;
12970                 }
12971
12972                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12973                 vlen += sizeof(v);
12974         }
12975 }
12976
12977 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12978 {
12979         int vlen;
12980         u32 apedata;
12981         char *fwtype;
12982
12983         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12984             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12985                 return;
12986
12987         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12988         if (apedata != APE_SEG_SIG_MAGIC)
12989                 return;
12990
12991         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12992         if (!(apedata & APE_FW_STATUS_READY))
12993                 return;
12994
12995         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12996
12997         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12998                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12999                 fwtype = "NCSI";
13000         } else {
13001                 fwtype = "DASH";
13002         }
13003
13004         vlen = strlen(tp->fw_ver);
13005
13006         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
13007                  fwtype,
13008                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
13009                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
13010                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
13011                  (apedata & APE_FW_VERSION_BLDMSK));
13012 }
13013
13014 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
13015 {
13016         u32 val;
13017         bool vpd_vers = false;
13018
13019         if (tp->fw_ver[0] != 0)
13020                 vpd_vers = true;
13021
13022         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
13023                 strcat(tp->fw_ver, "sb");
13024                 return;
13025         }
13026
13027         if (tg3_nvram_read(tp, 0, &val))
13028                 return;
13029
13030         if (val == TG3_EEPROM_MAGIC)
13031                 tg3_read_bc_ver(tp);
13032         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13033                 tg3_read_sb_ver(tp, val);
13034         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13035                 tg3_read_hwsb_ver(tp);
13036         else
13037                 return;
13038
13039         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13040              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13041                 goto done;
13042
13043         tg3_read_mgmtfw_ver(tp);
13044
13045 done:
13046         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13047 }
13048
13049 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13050
13051 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13052 {
13053 #if TG3_VLAN_TAG_USED
13054         dev->vlan_features |= flags;
13055 #endif
13056 }
13057
13058 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13059 {
13060         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13061             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13062                 return 4096;
13063         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13064                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13065                 return 1024;
13066         else
13067                 return 512;
13068 }
13069
13070 static int __devinit tg3_get_invariants(struct tg3 *tp)
13071 {
13072         static struct pci_device_id write_reorder_chipsets[] = {
13073                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13074                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13075                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13076                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13077                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13078                              PCI_DEVICE_ID_VIA_8385_0) },
13079                 { },
13080         };
13081         u32 misc_ctrl_reg;
13082         u32 pci_state_reg, grc_misc_cfg;
13083         u32 val;
13084         u16 pci_cmd;
13085         int err;
13086
13087         /* Force memory write invalidate off.  If we leave it on,
13088          * then on 5700_BX chips we have to enable a workaround.
13089          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13090          * to match the cacheline size.  The Broadcom driver have this
13091          * workaround but turns MWI off all the times so never uses
13092          * it.  This seems to suggest that the workaround is insufficient.
13093          */
13094         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13095         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13096         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13097
13098         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13099          * has the register indirect write enable bit set before
13100          * we try to access any of the MMIO registers.  It is also
13101          * critical that the PCI-X hw workaround situation is decided
13102          * before that as well.
13103          */
13104         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13105                               &misc_ctrl_reg);
13106
13107         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13108                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13109         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13110                 u32 prod_id_asic_rev;
13111
13112                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13113                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13114                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13115                         pci_read_config_dword(tp->pdev,
13116                                               TG3PCI_GEN2_PRODID_ASICREV,
13117                                               &prod_id_asic_rev);
13118                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13119                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13120                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13121                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13122                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13123                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13124                         pci_read_config_dword(tp->pdev,
13125                                               TG3PCI_GEN15_PRODID_ASICREV,
13126                                               &prod_id_asic_rev);
13127                 else
13128                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13129                                               &prod_id_asic_rev);
13130
13131                 tp->pci_chip_rev_id = prod_id_asic_rev;
13132         }
13133
13134         /* Wrong chip ID in 5752 A0. This code can be removed later
13135          * as A0 is not in production.
13136          */
13137         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13138                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13139
13140         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13141          * we need to disable memory and use config. cycles
13142          * only to access all registers. The 5702/03 chips
13143          * can mistakenly decode the special cycles from the
13144          * ICH chipsets as memory write cycles, causing corruption
13145          * of register and memory space. Only certain ICH bridges
13146          * will drive special cycles with non-zero data during the
13147          * address phase which can fall within the 5703's address
13148          * range. This is not an ICH bug as the PCI spec allows
13149          * non-zero address during special cycles. However, only
13150          * these ICH bridges are known to drive non-zero addresses
13151          * during special cycles.
13152          *
13153          * Since special cycles do not cross PCI bridges, we only
13154          * enable this workaround if the 5703 is on the secondary
13155          * bus of these ICH bridges.
13156          */
13157         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13158             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13159                 static struct tg3_dev_id {
13160                         u32     vendor;
13161                         u32     device;
13162                         u32     rev;
13163                 } ich_chipsets[] = {
13164                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13165                           PCI_ANY_ID },
13166                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13167                           PCI_ANY_ID },
13168                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13169                           0xa },
13170                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13171                           PCI_ANY_ID },
13172                         { },
13173                 };
13174                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13175                 struct pci_dev *bridge = NULL;
13176
13177                 while (pci_id->vendor != 0) {
13178                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13179                                                 bridge);
13180                         if (!bridge) {
13181                                 pci_id++;
13182                                 continue;
13183                         }
13184                         if (pci_id->rev != PCI_ANY_ID) {
13185                                 if (bridge->revision > pci_id->rev)
13186                                         continue;
13187                         }
13188                         if (bridge->subordinate &&
13189                             (bridge->subordinate->number ==
13190                              tp->pdev->bus->number)) {
13191
13192                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13193                                 pci_dev_put(bridge);
13194                                 break;
13195                         }
13196                 }
13197         }
13198
13199         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13200                 static struct tg3_dev_id {
13201                         u32     vendor;
13202                         u32     device;
13203                 } bridge_chipsets[] = {
13204                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13205                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13206                         { },
13207                 };
13208                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13209                 struct pci_dev *bridge = NULL;
13210
13211                 while (pci_id->vendor != 0) {
13212                         bridge = pci_get_device(pci_id->vendor,
13213                                                 pci_id->device,
13214                                                 bridge);
13215                         if (!bridge) {
13216                                 pci_id++;
13217                                 continue;
13218                         }
13219                         if (bridge->subordinate &&
13220                             (bridge->subordinate->number <=
13221                              tp->pdev->bus->number) &&
13222                             (bridge->subordinate->subordinate >=
13223                              tp->pdev->bus->number)) {
13224                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13225                                 pci_dev_put(bridge);
13226                                 break;
13227                         }
13228                 }
13229         }
13230
13231         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13232          * DMA addresses > 40-bit. This bridge may have other additional
13233          * 57xx devices behind it in some 4-port NIC designs for example.
13234          * Any tg3 device found behind the bridge will also need the 40-bit
13235          * DMA workaround.
13236          */
13237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13239                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13240                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13241                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13242         } else {
13243                 struct pci_dev *bridge = NULL;
13244
13245                 do {
13246                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13247                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13248                                                 bridge);
13249                         if (bridge && bridge->subordinate &&
13250                             (bridge->subordinate->number <=
13251                              tp->pdev->bus->number) &&
13252                             (bridge->subordinate->subordinate >=
13253                              tp->pdev->bus->number)) {
13254                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13255                                 pci_dev_put(bridge);
13256                                 break;
13257                         }
13258                 } while (bridge);
13259         }
13260
13261         /* Initialize misc host control in PCI block. */
13262         tp->misc_host_ctrl |= (misc_ctrl_reg &
13263                                MISC_HOST_CTRL_CHIPREV);
13264         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13265                                tp->misc_host_ctrl);
13266
13267         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13268             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13269             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13270                 tp->pdev_peer = tg3_find_peer(tp);
13271
13272         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13273             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13274             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13275                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13276
13277         /* Intentionally exclude ASIC_REV_5906 */
13278         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13279             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13280             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13281             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13283             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13284             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13285                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13286
13287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13288             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13289             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13290             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13291             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13292                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13293
13294         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13295             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13296                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13297
13298         /* 5700 B0 chips do not support checksumming correctly due
13299          * to hardware bugs.
13300          */
13301         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13302                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13303         else {
13304                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13305
13306                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13307                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13308                         features |= NETIF_F_IPV6_CSUM;
13309                 tp->dev->features |= features;
13310                 vlan_features_add(tp->dev, features);
13311         }
13312
13313         /* Determine TSO capabilities */
13314         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13315                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13316         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13317                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13318                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13319         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13320                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13321                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13322                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13323                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13324         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13325                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13326                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13327                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13328                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13329                         tp->fw_needed = FIRMWARE_TG3TSO5;
13330                 else
13331                         tp->fw_needed = FIRMWARE_TG3TSO;
13332         }
13333
13334         tp->irq_max = 1;
13335
13336         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13337                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13338                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13339                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13340                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13341                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13342                      tp->pdev_peer == tp->pdev))
13343                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13344
13345                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13346                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13347                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13348                 }
13349
13350                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13351                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13352                         tp->irq_max = TG3_IRQ_MAX_VECS;
13353                 }
13354         }
13355
13356         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13357             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13358             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13359                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13360         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13361                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13362                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13363         }
13364
13365         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13366                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13367
13368         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13369             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13370             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13371                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13372
13373         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13374                               &pci_state_reg);
13375
13376         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13377         if (tp->pcie_cap != 0) {
13378                 u16 lnkctl;
13379
13380                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13381
13382                 tp->pcie_readrq = 4096;
13383                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13384                         u16 word;
13385
13386                         pci_read_config_word(tp->pdev,
13387                                              tp->pcie_cap + PCI_EXP_LNKSTA,
13388                                              &word);
13389                         switch (word & PCI_EXP_LNKSTA_CLS) {
13390                         case PCI_EXP_LNKSTA_CLS_2_5GB:
13391                                 word &= PCI_EXP_LNKSTA_NLW;
13392                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13393                                 switch (word) {
13394                                 case 2:
13395                                         tp->pcie_readrq = 2048;
13396                                         break;
13397                                 case 4:
13398                                         tp->pcie_readrq = 1024;
13399                                         break;
13400                                 }
13401                                 break;
13402
13403                         case PCI_EXP_LNKSTA_CLS_5_0GB:
13404                                 word &= PCI_EXP_LNKSTA_NLW;
13405                                 word >>= PCI_EXP_LNKSTA_NLW_SHIFT;
13406                                 switch (word) {
13407                                 case 1:
13408                                         tp->pcie_readrq = 2048;
13409                                         break;
13410                                 case 2:
13411                                         tp->pcie_readrq = 1024;
13412                                         break;
13413                                 case 4:
13414                                         tp->pcie_readrq = 512;
13415                                         break;
13416                                 }
13417                         }
13418                 }
13419
13420                 pcie_set_readrq(tp->pdev, tp->pcie_readrq);
13421
13422                 pci_read_config_word(tp->pdev,
13423                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13424                                      &lnkctl);
13425                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13426                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13427                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13428                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13429                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13430                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13431                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13432                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13433                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13434                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13435                 }
13436         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13437                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13438         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13439                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13440                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13441                 if (!tp->pcix_cap) {
13442                         dev_err(&tp->pdev->dev,
13443                                 "Cannot find PCI-X capability, aborting\n");
13444                         return -EIO;
13445                 }
13446
13447                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13448                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13449         }
13450
13451         /* If we have an AMD 762 or VIA K8T800 chipset, write
13452          * reordering to the mailbox registers done by the host
13453          * controller can cause major troubles.  We read back from
13454          * every mailbox register write to force the writes to be
13455          * posted to the chip in order.
13456          */
13457         if (pci_dev_present(write_reorder_chipsets) &&
13458             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13459                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13460
13461         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13462                              &tp->pci_cacheline_sz);
13463         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13464                              &tp->pci_lat_timer);
13465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13466             tp->pci_lat_timer < 64) {
13467                 tp->pci_lat_timer = 64;
13468                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13469                                       tp->pci_lat_timer);
13470         }
13471
13472         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13473                 /* 5700 BX chips need to have their TX producer index
13474                  * mailboxes written twice to workaround a bug.
13475                  */
13476                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13477
13478                 /* If we are in PCI-X mode, enable register write workaround.
13479                  *
13480                  * The workaround is to use indirect register accesses
13481                  * for all chip writes not to mailbox registers.
13482                  */
13483                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13484                         u32 pm_reg;
13485
13486                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13487
13488                         /* The chip can have it's power management PCI config
13489                          * space registers clobbered due to this bug.
13490                          * So explicitly force the chip into D0 here.
13491                          */
13492                         pci_read_config_dword(tp->pdev,
13493                                               tp->pm_cap + PCI_PM_CTRL,
13494                                               &pm_reg);
13495                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13496                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13497                         pci_write_config_dword(tp->pdev,
13498                                                tp->pm_cap + PCI_PM_CTRL,
13499                                                pm_reg);
13500
13501                         /* Also, force SERR#/PERR# in PCI command. */
13502                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13503                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13504                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13505                 }
13506         }
13507
13508         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13509                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13510         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13511                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13512
13513         /* Chip-specific fixup from Broadcom driver */
13514         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13515             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13516                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13517                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13518         }
13519
13520         /* Default fast path register access methods */
13521         tp->read32 = tg3_read32;
13522         tp->write32 = tg3_write32;
13523         tp->read32_mbox = tg3_read32;
13524         tp->write32_mbox = tg3_write32;
13525         tp->write32_tx_mbox = tg3_write32;
13526         tp->write32_rx_mbox = tg3_write32;
13527
13528         /* Various workaround register access methods */
13529         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13530                 tp->write32 = tg3_write_indirect_reg32;
13531         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13532                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13533                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13534                 /*
13535                  * Back to back register writes can cause problems on these
13536                  * chips, the workaround is to read back all reg writes
13537                  * except those to mailbox regs.
13538                  *
13539                  * See tg3_write_indirect_reg32().
13540                  */
13541                 tp->write32 = tg3_write_flush_reg32;
13542         }
13543
13544         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13545             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13546                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13547                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13548                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13549         }
13550
13551         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13552                 tp->read32 = tg3_read_indirect_reg32;
13553                 tp->write32 = tg3_write_indirect_reg32;
13554                 tp->read32_mbox = tg3_read_indirect_mbox;
13555                 tp->write32_mbox = tg3_write_indirect_mbox;
13556                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13557                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13558
13559                 iounmap(tp->regs);
13560                 tp->regs = NULL;
13561
13562                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13563                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13564                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13565         }
13566         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13567                 tp->read32_mbox = tg3_read32_mbox_5906;
13568                 tp->write32_mbox = tg3_write32_mbox_5906;
13569                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13570                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13571         }
13572
13573         if (tp->write32 == tg3_write_indirect_reg32 ||
13574             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13575              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13576               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13577                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13578
13579         /* Get eeprom hw config before calling tg3_set_power_state().
13580          * In particular, the TG3_FLG2_IS_NIC flag must be
13581          * determined before calling tg3_set_power_state() so that
13582          * we know whether or not to switch out of Vaux power.
13583          * When the flag is set, it means that GPIO1 is used for eeprom
13584          * write protect and also implies that it is a LOM where GPIOs
13585          * are not used to switch power.
13586          */
13587         tg3_get_eeprom_hw_cfg(tp);
13588
13589         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13590                 /* Allow reads and writes to the
13591                  * APE register and memory space.
13592                  */
13593                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13594                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13595                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13596                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13597                                        pci_state_reg);
13598         }
13599
13600         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13601             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13602             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13603             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13604             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13605                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13606
13607         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13608          * GPIO1 driven high will bring 5700's external PHY out of reset.
13609          * It is also used as eeprom write protect on LOMs.
13610          */
13611         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13612         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13613             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13614                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13615                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13616         /* Unused GPIO3 must be driven as output on 5752 because there
13617          * are no pull-up resistors on unused GPIO pins.
13618          */
13619         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13620                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13621
13622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13623             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13624             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13625                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13626
13627         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13628             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13629                 /* Turn off the debug UART. */
13630                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13631                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13632                         /* Keep VMain power. */
13633                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13634                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13635         }
13636
13637         /* Force the chip into D0. */
13638         err = tg3_set_power_state(tp, PCI_D0);
13639         if (err) {
13640                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13641                 return err;
13642         }
13643
13644         /* Derive initial jumbo mode from MTU assigned in
13645          * ether_setup() via the alloc_etherdev() call
13646          */
13647         if (tp->dev->mtu > ETH_DATA_LEN &&
13648             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13649                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13650
13651         /* Determine WakeOnLan speed to use. */
13652         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13653             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13654             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13655             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13656                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13657         } else {
13658                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13659         }
13660
13661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13662                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13663
13664         /* A few boards don't want Ethernet@WireSpeed phy feature */
13665         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13666             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13667              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13668              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13669             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13671                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13672
13673         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13674             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13675                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13676         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13677                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13678
13679         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13680             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13681             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13682             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13683             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13684                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13685                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13686                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13687                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13688                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13689                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13690                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13691                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13692                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13693                 } else
13694                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13695         }
13696
13697         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13698             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13699                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13700                 if (tp->phy_otp == 0)
13701                         tp->phy_otp = TG3_OTP_DEFAULT;
13702         }
13703
13704         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13705                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13706         else
13707                 tp->mi_mode = MAC_MI_MODE_BASE;
13708
13709         tp->coalesce_mode = 0;
13710         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13711             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13712                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13713
13714         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13715             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13716                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13717
13718         err = tg3_mdio_init(tp);
13719         if (err)
13720                 return err;
13721
13722         /* Initialize data/descriptor byte/word swapping. */
13723         val = tr32(GRC_MODE);
13724         val &= GRC_MODE_HOST_STACKUP;
13725         tw32(GRC_MODE, val | tp->grc_mode);
13726
13727         tg3_switch_clocks(tp);
13728
13729         /* Clear this out for sanity. */
13730         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13731
13732         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13733                               &pci_state_reg);
13734         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13735             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13736                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13737
13738                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13739                     chiprevid == CHIPREV_ID_5701_B0 ||
13740                     chiprevid == CHIPREV_ID_5701_B2 ||
13741                     chiprevid == CHIPREV_ID_5701_B5) {
13742                         void __iomem *sram_base;
13743
13744                         /* Write some dummy words into the SRAM status block
13745                          * area, see if it reads back correctly.  If the return
13746                          * value is bad, force enable the PCIX workaround.
13747                          */
13748                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13749
13750                         writel(0x00000000, sram_base);
13751                         writel(0x00000000, sram_base + 4);
13752                         writel(0xffffffff, sram_base + 4);
13753                         if (readl(sram_base) != 0x00000000)
13754                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13755                 }
13756         }
13757
13758         udelay(50);
13759         tg3_nvram_init(tp);
13760
13761         grc_misc_cfg = tr32(GRC_MISC_CFG);
13762         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13763
13764         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13765             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13766              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13767                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13768
13769         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13770             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13771                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13772         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13773                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13774                                       HOSTCC_MODE_CLRTICK_TXBD);
13775
13776                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13777                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13778                                        tp->misc_host_ctrl);
13779         }
13780
13781         /* Preserve the APE MAC_MODE bits */
13782         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13783                 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13784         else
13785                 tp->mac_mode = TG3_DEF_MAC_MODE;
13786
13787         /* these are limited to 10/100 only */
13788         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13789              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13790             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13791              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13792              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13793               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13794               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13795             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13796              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13797               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13798               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13799             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13800             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13801             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13802             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13803                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13804
13805         err = tg3_phy_probe(tp);
13806         if (err) {
13807                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13808                 /* ... but do not return immediately ... */
13809                 tg3_mdio_fini(tp);
13810         }
13811
13812         tg3_read_vpd(tp);
13813         tg3_read_fw_ver(tp);
13814
13815         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13816                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13817         } else {
13818                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13819                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13820                 else
13821                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13822         }
13823
13824         /* 5700 {AX,BX} chips have a broken status block link
13825          * change bit implementation, so we must use the
13826          * status register in those cases.
13827          */
13828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13829                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13830         else
13831                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13832
13833         /* The led_ctrl is set during tg3_phy_probe, here we might
13834          * have to force the link status polling mechanism based
13835          * upon subsystem IDs.
13836          */
13837         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13838             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13839             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13840                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13841                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13842         }
13843
13844         /* For all SERDES we poll the MAC status register. */
13845         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13846                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13847         else
13848                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13849
13850         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13851         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13853             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13854                 tp->rx_offset -= NET_IP_ALIGN;
13855 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13856                 tp->rx_copy_thresh = ~(u16)0;
13857 #endif
13858         }
13859
13860         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13861         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13862         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13863
13864         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13865
13866         /* Increment the rx prod index on the rx std ring by at most
13867          * 8 for these chips to workaround hw errata.
13868          */
13869         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13870             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13871             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13872                 tp->rx_std_max_post = 8;
13873
13874         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13875                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13876                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13877
13878         return err;
13879 }
13880
13881 #ifdef CONFIG_SPARC
13882 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13883 {
13884         struct net_device *dev = tp->dev;
13885         struct pci_dev *pdev = tp->pdev;
13886         struct device_node *dp = pci_device_to_OF_node(pdev);
13887         const unsigned char *addr;
13888         int len;
13889
13890         addr = of_get_property(dp, "local-mac-address", &len);
13891         if (addr && len == 6) {
13892                 memcpy(dev->dev_addr, addr, 6);
13893                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13894                 return 0;
13895         }
13896         return -ENODEV;
13897 }
13898
13899 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13900 {
13901         struct net_device *dev = tp->dev;
13902
13903         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13904         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13905         return 0;
13906 }
13907 #endif
13908
13909 static int __devinit tg3_get_device_address(struct tg3 *tp)
13910 {
13911         struct net_device *dev = tp->dev;
13912         u32 hi, lo, mac_offset;
13913         int addr_ok = 0;
13914
13915 #ifdef CONFIG_SPARC
13916         if (!tg3_get_macaddr_sparc(tp))
13917                 return 0;
13918 #endif
13919
13920         mac_offset = 0x7c;
13921         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13922             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13923                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13924                         mac_offset = 0xcc;
13925                 if (tg3_nvram_lock(tp))
13926                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13927                 else
13928                         tg3_nvram_unlock(tp);
13929         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13930                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13931                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13932                         mac_offset = 0xcc;
13933                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13934                         mac_offset += 0x18c;
13935         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13936                 mac_offset = 0x10;
13937
13938         /* First try to get it from MAC address mailbox. */
13939         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13940         if ((hi >> 16) == 0x484b) {
13941                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13942                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13943
13944                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13945                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13946                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13947                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13948                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13949
13950                 /* Some old bootcode may report a 0 MAC address in SRAM */
13951                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13952         }
13953         if (!addr_ok) {
13954                 /* Next, try NVRAM. */
13955                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13956                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13957                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13958                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13959                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13960                 }
13961                 /* Finally just fetch it out of the MAC control regs. */
13962                 else {
13963                         hi = tr32(MAC_ADDR_0_HIGH);
13964                         lo = tr32(MAC_ADDR_0_LOW);
13965
13966                         dev->dev_addr[5] = lo & 0xff;
13967                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13968                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13969                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13970                         dev->dev_addr[1] = hi & 0xff;
13971                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13972                 }
13973         }
13974
13975         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13976 #ifdef CONFIG_SPARC
13977                 if (!tg3_get_default_macaddr_sparc(tp))
13978                         return 0;
13979 #endif
13980                 return -EINVAL;
13981         }
13982         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13983         return 0;
13984 }
13985
13986 #define BOUNDARY_SINGLE_CACHELINE       1
13987 #define BOUNDARY_MULTI_CACHELINE        2
13988
13989 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13990 {
13991         int cacheline_size;
13992         u8 byte;
13993         int goal;
13994
13995         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13996         if (byte == 0)
13997                 cacheline_size = 1024;
13998         else
13999                 cacheline_size = (int) byte * 4;
14000
14001         /* On 5703 and later chips, the boundary bits have no
14002          * effect.
14003          */
14004         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14005             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
14006             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
14007                 goto out;
14008
14009 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
14010         goal = BOUNDARY_MULTI_CACHELINE;
14011 #else
14012 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
14013         goal = BOUNDARY_SINGLE_CACHELINE;
14014 #else
14015         goal = 0;
14016 #endif
14017 #endif
14018
14019         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14020                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
14021                 goto out;
14022         }
14023
14024         if (!goal)
14025                 goto out;
14026
14027         /* PCI controllers on most RISC systems tend to disconnect
14028          * when a device tries to burst across a cache-line boundary.
14029          * Therefore, letting tg3 do so just wastes PCI bandwidth.
14030          *
14031          * Unfortunately, for PCI-E there are only limited
14032          * write-side controls for this, and thus for reads
14033          * we will still get the disconnects.  We'll also waste
14034          * these PCI cycles for both read and write for chips
14035          * other than 5700 and 5701 which do not implement the
14036          * boundary bits.
14037          */
14038         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
14039             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
14040                 switch (cacheline_size) {
14041                 case 16:
14042                 case 32:
14043                 case 64:
14044                 case 128:
14045                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14046                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
14047                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
14048                         } else {
14049                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14050                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14051                         }
14052                         break;
14053
14054                 case 256:
14055                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
14056                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
14057                         break;
14058
14059                 default:
14060                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
14061                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14062                         break;
14063                 }
14064         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14065                 switch (cacheline_size) {
14066                 case 16:
14067                 case 32:
14068                 case 64:
14069                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14070                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14071                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14072                                 break;
14073                         }
14074                         /* fallthrough */
14075                 case 128:
14076                 default:
14077                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14078                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14079                         break;
14080                 }
14081         } else {
14082                 switch (cacheline_size) {
14083                 case 16:
14084                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14085                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14086                                         DMA_RWCTRL_WRITE_BNDRY_16);
14087                                 break;
14088                         }
14089                         /* fallthrough */
14090                 case 32:
14091                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14092                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14093                                         DMA_RWCTRL_WRITE_BNDRY_32);
14094                                 break;
14095                         }
14096                         /* fallthrough */
14097                 case 64:
14098                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14099                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14100                                         DMA_RWCTRL_WRITE_BNDRY_64);
14101                                 break;
14102                         }
14103                         /* fallthrough */
14104                 case 128:
14105                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14106                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14107                                         DMA_RWCTRL_WRITE_BNDRY_128);
14108                                 break;
14109                         }
14110                         /* fallthrough */
14111                 case 256:
14112                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14113                                 DMA_RWCTRL_WRITE_BNDRY_256);
14114                         break;
14115                 case 512:
14116                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14117                                 DMA_RWCTRL_WRITE_BNDRY_512);
14118                         break;
14119                 case 1024:
14120                 default:
14121                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14122                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14123                         break;
14124                 }
14125         }
14126
14127 out:
14128         return val;
14129 }
14130
14131 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14132 {
14133         struct tg3_internal_buffer_desc test_desc;
14134         u32 sram_dma_descs;
14135         int i, ret;
14136
14137         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14138
14139         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14140         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14141         tw32(RDMAC_STATUS, 0);
14142         tw32(WDMAC_STATUS, 0);
14143
14144         tw32(BUFMGR_MODE, 0);
14145         tw32(FTQ_RESET, 0);
14146
14147         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14148         test_desc.addr_lo = buf_dma & 0xffffffff;
14149         test_desc.nic_mbuf = 0x00002100;
14150         test_desc.len = size;
14151
14152         /*
14153          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14154          * the *second* time the tg3 driver was getting loaded after an
14155          * initial scan.
14156          *
14157          * Broadcom tells me:
14158          *   ...the DMA engine is connected to the GRC block and a DMA
14159          *   reset may affect the GRC block in some unpredictable way...
14160          *   The behavior of resets to individual blocks has not been tested.
14161          *
14162          * Broadcom noted the GRC reset will also reset all sub-components.
14163          */
14164         if (to_device) {
14165                 test_desc.cqid_sqid = (13 << 8) | 2;
14166
14167                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14168                 udelay(40);
14169         } else {
14170                 test_desc.cqid_sqid = (16 << 8) | 7;
14171
14172                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14173                 udelay(40);
14174         }
14175         test_desc.flags = 0x00000005;
14176
14177         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14178                 u32 val;
14179
14180                 val = *(((u32 *)&test_desc) + i);
14181                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14182                                        sram_dma_descs + (i * sizeof(u32)));
14183                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14184         }
14185         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14186
14187         if (to_device)
14188                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14189         else
14190                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14191
14192         ret = -ENODEV;
14193         for (i = 0; i < 40; i++) {
14194                 u32 val;
14195
14196                 if (to_device)
14197                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14198                 else
14199                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14200                 if ((val & 0xffff) == sram_dma_descs) {
14201                         ret = 0;
14202                         break;
14203                 }
14204
14205                 udelay(100);
14206         }
14207
14208         return ret;
14209 }
14210
14211 #define TEST_BUFFER_SIZE        0x2000
14212
14213 static int __devinit tg3_test_dma(struct tg3 *tp)
14214 {
14215         dma_addr_t buf_dma;
14216         u32 *buf, saved_dma_rwctrl;
14217         int ret = 0;
14218
14219         buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
14220                                  &buf_dma, GFP_KERNEL);
14221         if (!buf) {
14222                 ret = -ENOMEM;
14223                 goto out_nofree;
14224         }
14225
14226         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14227                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14228
14229         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14230
14231         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14232                 goto out;
14233
14234         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14235                 /* DMA read watermark not used on PCIE */
14236                 tp->dma_rwctrl |= 0x00180000;
14237         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14238                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14239                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14240                         tp->dma_rwctrl |= 0x003f0000;
14241                 else
14242                         tp->dma_rwctrl |= 0x003f000f;
14243         } else {
14244                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14245                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14246                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14247                         u32 read_water = 0x7;
14248
14249                         /* If the 5704 is behind the EPB bridge, we can
14250                          * do the less restrictive ONE_DMA workaround for
14251                          * better performance.
14252                          */
14253                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14254                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14255                                 tp->dma_rwctrl |= 0x8000;
14256                         else if (ccval == 0x6 || ccval == 0x7)
14257                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14258
14259                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14260                                 read_water = 4;
14261                         /* Set bit 23 to enable PCIX hw bug fix */
14262                         tp->dma_rwctrl |=
14263                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14264                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14265                                 (1 << 23);
14266                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14267                         /* 5780 always in PCIX mode */
14268                         tp->dma_rwctrl |= 0x00144000;
14269                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14270                         /* 5714 always in PCIX mode */
14271                         tp->dma_rwctrl |= 0x00148000;
14272                 } else {
14273                         tp->dma_rwctrl |= 0x001b000f;
14274                 }
14275         }
14276
14277         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14278             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14279                 tp->dma_rwctrl &= 0xfffffff0;
14280
14281         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14283                 /* Remove this if it causes problems for some boards. */
14284                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14285
14286                 /* On 5700/5701 chips, we need to set this bit.
14287                  * Otherwise the chip will issue cacheline transactions
14288                  * to streamable DMA memory with not all the byte
14289                  * enables turned on.  This is an error on several
14290                  * RISC PCI controllers, in particular sparc64.
14291                  *
14292                  * On 5703/5704 chips, this bit has been reassigned
14293                  * a different meaning.  In particular, it is used
14294                  * on those chips to enable a PCI-X workaround.
14295                  */
14296                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14297         }
14298
14299         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14300
14301 #if 0
14302         /* Unneeded, already done by tg3_get_invariants.  */
14303         tg3_switch_clocks(tp);
14304 #endif
14305
14306         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14307             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14308                 goto out;
14309
14310         /* It is best to perform DMA test with maximum write burst size
14311          * to expose the 5700/5701 write DMA bug.
14312          */
14313         saved_dma_rwctrl = tp->dma_rwctrl;
14314         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14315         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14316
14317         while (1) {
14318                 u32 *p = buf, i;
14319
14320                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14321                         p[i] = i;
14322
14323                 /* Send the buffer to the chip. */
14324                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14325                 if (ret) {
14326                         dev_err(&tp->pdev->dev,
14327                                 "%s: Buffer write failed. err = %d\n",
14328                                 __func__, ret);
14329                         break;
14330                 }
14331
14332 #if 0
14333                 /* validate data reached card RAM correctly. */
14334                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14335                         u32 val;
14336                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14337                         if (le32_to_cpu(val) != p[i]) {
14338                                 dev_err(&tp->pdev->dev,
14339                                         "%s: Buffer corrupted on device! "
14340                                         "(%d != %d)\n", __func__, val, i);
14341                                 /* ret = -ENODEV here? */
14342                         }
14343                         p[i] = 0;
14344                 }
14345 #endif
14346                 /* Now read it back. */
14347                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14348                 if (ret) {
14349                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14350                                 "err = %d\n", __func__, ret);
14351                         break;
14352                 }
14353
14354                 /* Verify it. */
14355                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14356                         if (p[i] == i)
14357                                 continue;
14358
14359                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14360                             DMA_RWCTRL_WRITE_BNDRY_16) {
14361                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14362                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14363                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14364                                 break;
14365                         } else {
14366                                 dev_err(&tp->pdev->dev,
14367                                         "%s: Buffer corrupted on read back! "
14368                                         "(%d != %d)\n", __func__, p[i], i);
14369                                 ret = -ENODEV;
14370                                 goto out;
14371                         }
14372                 }
14373
14374                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14375                         /* Success. */
14376                         ret = 0;
14377                         break;
14378                 }
14379         }
14380         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14381             DMA_RWCTRL_WRITE_BNDRY_16) {
14382                 static struct pci_device_id dma_wait_state_chipsets[] = {
14383                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14384                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14385                         { },
14386                 };
14387
14388                 /* DMA test passed without adjusting DMA boundary,
14389                  * now look for chipsets that are known to expose the
14390                  * DMA bug without failing the test.
14391                  */
14392                 if (pci_dev_present(dma_wait_state_chipsets)) {
14393                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14394                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14395                 } else {
14396                         /* Safe to use the calculated DMA boundary. */
14397                         tp->dma_rwctrl = saved_dma_rwctrl;
14398                 }
14399
14400                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14401         }
14402
14403 out:
14404         dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
14405 out_nofree:
14406         return ret;
14407 }
14408
14409 static void __devinit tg3_init_link_config(struct tg3 *tp)
14410 {
14411         tp->link_config.advertising =
14412                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14413                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14414                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14415                  ADVERTISED_Autoneg | ADVERTISED_MII);
14416         tp->link_config.speed = SPEED_INVALID;
14417         tp->link_config.duplex = DUPLEX_INVALID;
14418         tp->link_config.autoneg = AUTONEG_ENABLE;
14419         tp->link_config.active_speed = SPEED_INVALID;
14420         tp->link_config.active_duplex = DUPLEX_INVALID;
14421         tp->link_config.orig_speed = SPEED_INVALID;
14422         tp->link_config.orig_duplex = DUPLEX_INVALID;
14423         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14424 }
14425
14426 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14427 {
14428         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14429                 tp->bufmgr_config.mbuf_read_dma_low_water =
14430                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14431                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14432                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14433                 tp->bufmgr_config.mbuf_high_water =
14434                         DEFAULT_MB_HIGH_WATER_57765;
14435
14436                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14437                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14438                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14439                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14440                 tp->bufmgr_config.mbuf_high_water_jumbo =
14441                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14442         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14443                 tp->bufmgr_config.mbuf_read_dma_low_water =
14444                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14445                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14446                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14447                 tp->bufmgr_config.mbuf_high_water =
14448                         DEFAULT_MB_HIGH_WATER_5705;
14449                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14450                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14451                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14452                         tp->bufmgr_config.mbuf_high_water =
14453                                 DEFAULT_MB_HIGH_WATER_5906;
14454                 }
14455
14456                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14457                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14458                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14459                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14460                 tp->bufmgr_config.mbuf_high_water_jumbo =
14461                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14462         } else {
14463                 tp->bufmgr_config.mbuf_read_dma_low_water =
14464                         DEFAULT_MB_RDMA_LOW_WATER;
14465                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14466                         DEFAULT_MB_MACRX_LOW_WATER;
14467                 tp->bufmgr_config.mbuf_high_water =
14468                         DEFAULT_MB_HIGH_WATER;
14469
14470                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14471                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14472                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14473                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14474                 tp->bufmgr_config.mbuf_high_water_jumbo =
14475                         DEFAULT_MB_HIGH_WATER_JUMBO;
14476         }
14477
14478         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14479         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14480 }
14481
14482 static char * __devinit tg3_phy_string(struct tg3 *tp)
14483 {
14484         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14485         case TG3_PHY_ID_BCM5400:        return "5400";
14486         case TG3_PHY_ID_BCM5401:        return "5401";
14487         case TG3_PHY_ID_BCM5411:        return "5411";
14488         case TG3_PHY_ID_BCM5701:        return "5701";
14489         case TG3_PHY_ID_BCM5703:        return "5703";
14490         case TG3_PHY_ID_BCM5704:        return "5704";
14491         case TG3_PHY_ID_BCM5705:        return "5705";
14492         case TG3_PHY_ID_BCM5750:        return "5750";
14493         case TG3_PHY_ID_BCM5752:        return "5752";
14494         case TG3_PHY_ID_BCM5714:        return "5714";
14495         case TG3_PHY_ID_BCM5780:        return "5780";
14496         case TG3_PHY_ID_BCM5755:        return "5755";
14497         case TG3_PHY_ID_BCM5787:        return "5787";
14498         case TG3_PHY_ID_BCM5784:        return "5784";
14499         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14500         case TG3_PHY_ID_BCM5906:        return "5906";
14501         case TG3_PHY_ID_BCM5761:        return "5761";
14502         case TG3_PHY_ID_BCM5718C:       return "5718C";
14503         case TG3_PHY_ID_BCM5718S:       return "5718S";
14504         case TG3_PHY_ID_BCM57765:       return "57765";
14505         case TG3_PHY_ID_BCM5719C:       return "5719C";
14506         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14507         case 0:                 return "serdes";
14508         default:                return "unknown";
14509         }
14510 }
14511
14512 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14513 {
14514         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14515                 strcpy(str, "PCI Express");
14516                 return str;
14517         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14518                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14519
14520                 strcpy(str, "PCIX:");
14521
14522                 if ((clock_ctrl == 7) ||
14523                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14524                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14525                         strcat(str, "133MHz");
14526                 else if (clock_ctrl == 0)
14527                         strcat(str, "33MHz");
14528                 else if (clock_ctrl == 2)
14529                         strcat(str, "50MHz");
14530                 else if (clock_ctrl == 4)
14531                         strcat(str, "66MHz");
14532                 else if (clock_ctrl == 6)
14533                         strcat(str, "100MHz");
14534         } else {
14535                 strcpy(str, "PCI:");
14536                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14537                         strcat(str, "66MHz");
14538                 else
14539                         strcat(str, "33MHz");
14540         }
14541         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14542                 strcat(str, ":32-bit");
14543         else
14544                 strcat(str, ":64-bit");
14545         return str;
14546 }
14547
14548 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14549 {
14550         struct pci_dev *peer;
14551         unsigned int func, devnr = tp->pdev->devfn & ~7;
14552
14553         for (func = 0; func < 8; func++) {
14554                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14555                 if (peer && peer != tp->pdev)
14556                         break;
14557                 pci_dev_put(peer);
14558         }
14559         /* 5704 can be configured in single-port mode, set peer to
14560          * tp->pdev in that case.
14561          */
14562         if (!peer) {
14563                 peer = tp->pdev;
14564                 return peer;
14565         }
14566
14567         /*
14568          * We don't need to keep the refcount elevated; there's no way
14569          * to remove one half of this device without removing the other
14570          */
14571         pci_dev_put(peer);
14572
14573         return peer;
14574 }
14575
14576 static void __devinit tg3_init_coal(struct tg3 *tp)
14577 {
14578         struct ethtool_coalesce *ec = &tp->coal;
14579
14580         memset(ec, 0, sizeof(*ec));
14581         ec->cmd = ETHTOOL_GCOALESCE;
14582         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14583         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14584         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14585         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14586         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14587         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14588         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14589         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14590         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14591
14592         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14593                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14594                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14595                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14596                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14597                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14598         }
14599
14600         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14601                 ec->rx_coalesce_usecs_irq = 0;
14602                 ec->tx_coalesce_usecs_irq = 0;
14603                 ec->stats_block_coalesce_usecs = 0;
14604         }
14605 }
14606
14607 static const struct net_device_ops tg3_netdev_ops = {
14608         .ndo_open               = tg3_open,
14609         .ndo_stop               = tg3_close,
14610         .ndo_start_xmit         = tg3_start_xmit,
14611         .ndo_get_stats64        = tg3_get_stats64,
14612         .ndo_validate_addr      = eth_validate_addr,
14613         .ndo_set_multicast_list = tg3_set_rx_mode,
14614         .ndo_set_mac_address    = tg3_set_mac_addr,
14615         .ndo_do_ioctl           = tg3_ioctl,
14616         .ndo_tx_timeout         = tg3_tx_timeout,
14617         .ndo_change_mtu         = tg3_change_mtu,
14618 #if TG3_VLAN_TAG_USED
14619         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14620 #endif
14621 #ifdef CONFIG_NET_POLL_CONTROLLER
14622         .ndo_poll_controller    = tg3_poll_controller,
14623 #endif
14624 };
14625
14626 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14627         .ndo_open               = tg3_open,
14628         .ndo_stop               = tg3_close,
14629         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14630         .ndo_get_stats64        = tg3_get_stats64,
14631         .ndo_validate_addr      = eth_validate_addr,
14632         .ndo_set_multicast_list = tg3_set_rx_mode,
14633         .ndo_set_mac_address    = tg3_set_mac_addr,
14634         .ndo_do_ioctl           = tg3_ioctl,
14635         .ndo_tx_timeout         = tg3_tx_timeout,
14636         .ndo_change_mtu         = tg3_change_mtu,
14637 #if TG3_VLAN_TAG_USED
14638         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14639 #endif
14640 #ifdef CONFIG_NET_POLL_CONTROLLER
14641         .ndo_poll_controller    = tg3_poll_controller,
14642 #endif
14643 };
14644
14645 static int __devinit tg3_init_one(struct pci_dev *pdev,
14646                                   const struct pci_device_id *ent)
14647 {
14648         struct net_device *dev;
14649         struct tg3 *tp;
14650         int i, err, pm_cap;
14651         u32 sndmbx, rcvmbx, intmbx;
14652         char str[40];
14653         u64 dma_mask, persist_dma_mask;
14654
14655         printk_once(KERN_INFO "%s\n", version);
14656
14657         err = pci_enable_device(pdev);
14658         if (err) {
14659                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14660                 return err;
14661         }
14662
14663         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14664         if (err) {
14665                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14666                 goto err_out_disable_pdev;
14667         }
14668
14669         pci_set_master(pdev);
14670
14671         /* Find power-management capability. */
14672         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14673         if (pm_cap == 0) {
14674                 dev_err(&pdev->dev,
14675                         "Cannot find Power Management capability, aborting\n");
14676                 err = -EIO;
14677                 goto err_out_free_res;
14678         }
14679
14680         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14681         if (!dev) {
14682                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14683                 err = -ENOMEM;
14684                 goto err_out_free_res;
14685         }
14686
14687         SET_NETDEV_DEV(dev, &pdev->dev);
14688
14689 #if TG3_VLAN_TAG_USED
14690         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14691 #endif
14692
14693         tp = netdev_priv(dev);
14694         tp->pdev = pdev;
14695         tp->dev = dev;
14696         tp->pm_cap = pm_cap;
14697         tp->rx_mode = TG3_DEF_RX_MODE;
14698         tp->tx_mode = TG3_DEF_TX_MODE;
14699
14700         if (tg3_debug > 0)
14701                 tp->msg_enable = tg3_debug;
14702         else
14703                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14704
14705         /* The word/byte swap controls here control register access byte
14706          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14707          * setting below.
14708          */
14709         tp->misc_host_ctrl =
14710                 MISC_HOST_CTRL_MASK_PCI_INT |
14711                 MISC_HOST_CTRL_WORD_SWAP |
14712                 MISC_HOST_CTRL_INDIR_ACCESS |
14713                 MISC_HOST_CTRL_PCISTATE_RW;
14714
14715         /* The NONFRM (non-frame) byte/word swap controls take effect
14716          * on descriptor entries, anything which isn't packet data.
14717          *
14718          * The StrongARM chips on the board (one for tx, one for rx)
14719          * are running in big-endian mode.
14720          */
14721         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14722                         GRC_MODE_WSWAP_NONFRM_DATA);
14723 #ifdef __BIG_ENDIAN
14724         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14725 #endif
14726         spin_lock_init(&tp->lock);
14727         spin_lock_init(&tp->indirect_lock);
14728         INIT_WORK(&tp->reset_task, tg3_reset_task);
14729
14730         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14731         if (!tp->regs) {
14732                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14733                 err = -ENOMEM;
14734                 goto err_out_free_dev;
14735         }
14736
14737         tg3_init_link_config(tp);
14738
14739         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14740         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14741
14742         dev->ethtool_ops = &tg3_ethtool_ops;
14743         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14744         dev->irq = pdev->irq;
14745
14746         err = tg3_get_invariants(tp);
14747         if (err) {
14748                 dev_err(&pdev->dev,
14749                         "Problem fetching invariants of chip, aborting\n");
14750                 goto err_out_iounmap;
14751         }
14752
14753         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14754             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14755             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14756                 dev->netdev_ops = &tg3_netdev_ops;
14757         else
14758                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14759
14760
14761         /* The EPB bridge inside 5714, 5715, and 5780 and any
14762          * device behind the EPB cannot support DMA addresses > 40-bit.
14763          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14764          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14765          * do DMA address check in tg3_start_xmit().
14766          */
14767         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14768                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14769         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14770                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14771 #ifdef CONFIG_HIGHMEM
14772                 dma_mask = DMA_BIT_MASK(64);
14773 #endif
14774         } else
14775                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14776
14777         /* Configure DMA attributes. */
14778         if (dma_mask > DMA_BIT_MASK(32)) {
14779                 err = pci_set_dma_mask(pdev, dma_mask);
14780                 if (!err) {
14781                         dev->features |= NETIF_F_HIGHDMA;
14782                         err = pci_set_consistent_dma_mask(pdev,
14783                                                           persist_dma_mask);
14784                         if (err < 0) {
14785                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14786                                         "DMA for consistent allocations\n");
14787                                 goto err_out_iounmap;
14788                         }
14789                 }
14790         }
14791         if (err || dma_mask == DMA_BIT_MASK(32)) {
14792                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14793                 if (err) {
14794                         dev_err(&pdev->dev,
14795                                 "No usable DMA configuration, aborting\n");
14796                         goto err_out_iounmap;
14797                 }
14798         }
14799
14800         tg3_init_bufmgr_config(tp);
14801
14802         /* Selectively allow TSO based on operating conditions */
14803         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14804             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14805                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14806         else {
14807                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14808                 tp->fw_needed = NULL;
14809         }
14810
14811         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14812                 tp->fw_needed = FIRMWARE_TG3;
14813
14814         /* TSO is on by default on chips that support hardware TSO.
14815          * Firmware TSO on older chips gives lower performance, so it
14816          * is off by default, but can be enabled using ethtool.
14817          */
14818         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14819             (dev->features & NETIF_F_IP_CSUM)) {
14820                 dev->features |= NETIF_F_TSO;
14821                 vlan_features_add(dev, NETIF_F_TSO);
14822         }
14823         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14824             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14825                 if (dev->features & NETIF_F_IPV6_CSUM) {
14826                         dev->features |= NETIF_F_TSO6;
14827                         vlan_features_add(dev, NETIF_F_TSO6);
14828                 }
14829                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14830                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14831                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14832                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14833                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14834                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14835                         dev->features |= NETIF_F_TSO_ECN;
14836                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14837                 }
14838         }
14839
14840         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14841             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14842             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14843                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14844                 tp->rx_pending = 63;
14845         }
14846
14847         err = tg3_get_device_address(tp);
14848         if (err) {
14849                 dev_err(&pdev->dev,
14850                         "Could not obtain valid ethernet address, aborting\n");
14851                 goto err_out_iounmap;
14852         }
14853
14854         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14855                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14856                 if (!tp->aperegs) {
14857                         dev_err(&pdev->dev,
14858                                 "Cannot map APE registers, aborting\n");
14859                         err = -ENOMEM;
14860                         goto err_out_iounmap;
14861                 }
14862
14863                 tg3_ape_lock_init(tp);
14864
14865                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14866                         tg3_read_dash_ver(tp);
14867         }
14868
14869         /*
14870          * Reset chip in case UNDI or EFI driver did not shutdown
14871          * DMA self test will enable WDMAC and we'll see (spurious)
14872          * pending DMA on the PCI bus at that point.
14873          */
14874         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14875             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14876                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14877                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14878         }
14879
14880         err = tg3_test_dma(tp);
14881         if (err) {
14882                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14883                 goto err_out_apeunmap;
14884         }
14885
14886         /* flow control autonegotiation is default behavior */
14887         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14888         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14889
14890         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14891         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14892         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14893         for (i = 0; i < tp->irq_max; i++) {
14894                 struct tg3_napi *tnapi = &tp->napi[i];
14895
14896                 tnapi->tp = tp;
14897                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14898
14899                 tnapi->int_mbox = intmbx;
14900                 if (i < 4)
14901                         intmbx += 0x8;
14902                 else
14903                         intmbx += 0x4;
14904
14905                 tnapi->consmbox = rcvmbx;
14906                 tnapi->prodmbox = sndmbx;
14907
14908                 if (i)
14909                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14910                 else
14911                         tnapi->coal_now = HOSTCC_MODE_NOW;
14912
14913                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14914                         break;
14915
14916                 /*
14917                  * If we support MSIX, we'll be using RSS.  If we're using
14918                  * RSS, the first vector only handles link interrupts and the
14919                  * remaining vectors handle rx and tx interrupts.  Reuse the
14920                  * mailbox values for the next iteration.  The values we setup
14921                  * above are still useful for the single vectored mode.
14922                  */
14923                 if (!i)
14924                         continue;
14925
14926                 rcvmbx += 0x8;
14927
14928                 if (sndmbx & 0x4)
14929                         sndmbx -= 0x4;
14930                 else
14931                         sndmbx += 0xc;
14932         }
14933
14934         tg3_init_coal(tp);
14935
14936         pci_set_drvdata(pdev, dev);
14937
14938         err = register_netdev(dev);
14939         if (err) {
14940                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14941                 goto err_out_apeunmap;
14942         }
14943
14944         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14945                     tp->board_part_number,
14946                     tp->pci_chip_rev_id,
14947                     tg3_bus_string(tp, str),
14948                     dev->dev_addr);
14949
14950         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14951                 struct phy_device *phydev;
14952                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14953                 netdev_info(dev,
14954                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14955                             phydev->drv->name, dev_name(&phydev->dev));
14956         } else {
14957                 char *ethtype;
14958
14959                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14960                         ethtype = "10/100Base-TX";
14961                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14962                         ethtype = "1000Base-SX";
14963                 else
14964                         ethtype = "10/100/1000Base-T";
14965
14966                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14967                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14968                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14969         }
14970
14971         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14972                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14973                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14974                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14975                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14976                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14977         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14978                     tp->dma_rwctrl,
14979                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14980                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14981
14982         return 0;
14983
14984 err_out_apeunmap:
14985         if (tp->aperegs) {
14986                 iounmap(tp->aperegs);
14987                 tp->aperegs = NULL;
14988         }
14989
14990 err_out_iounmap:
14991         if (tp->regs) {
14992                 iounmap(tp->regs);
14993                 tp->regs = NULL;
14994         }
14995
14996 err_out_free_dev:
14997         free_netdev(dev);
14998
14999 err_out_free_res:
15000         pci_release_regions(pdev);
15001
15002 err_out_disable_pdev:
15003         pci_disable_device(pdev);
15004         pci_set_drvdata(pdev, NULL);
15005         return err;
15006 }
15007
15008 static void __devexit tg3_remove_one(struct pci_dev *pdev)
15009 {
15010         struct net_device *dev = pci_get_drvdata(pdev);
15011
15012         if (dev) {
15013                 struct tg3 *tp = netdev_priv(dev);
15014
15015                 if (tp->fw)
15016                         release_firmware(tp->fw);
15017
15018                 flush_scheduled_work();
15019
15020                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
15021                         tg3_phy_fini(tp);
15022                         tg3_mdio_fini(tp);
15023                 }
15024
15025                 unregister_netdev(dev);
15026                 if (tp->aperegs) {
15027                         iounmap(tp->aperegs);
15028                         tp->aperegs = NULL;
15029                 }
15030                 if (tp->regs) {
15031                         iounmap(tp->regs);
15032                         tp->regs = NULL;
15033                 }
15034                 free_netdev(dev);
15035                 pci_release_regions(pdev);
15036                 pci_disable_device(pdev);
15037                 pci_set_drvdata(pdev, NULL);
15038         }
15039 }
15040
15041 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
15042 {
15043         struct net_device *dev = pci_get_drvdata(pdev);
15044         struct tg3 *tp = netdev_priv(dev);
15045         pci_power_t target_state;
15046         int err;
15047
15048         /* PCI register 4 needs to be saved whether netif_running() or not.
15049          * MSI address and data need to be saved if using MSI and
15050          * netif_running().
15051          */
15052         pci_save_state(pdev);
15053
15054         if (!netif_running(dev))
15055                 return 0;
15056
15057         flush_scheduled_work();
15058         tg3_phy_stop(tp);
15059         tg3_netif_stop(tp);
15060
15061         del_timer_sync(&tp->timer);
15062
15063         tg3_full_lock(tp, 1);
15064         tg3_disable_ints(tp);
15065         tg3_full_unlock(tp);
15066
15067         netif_device_detach(dev);
15068
15069         tg3_full_lock(tp, 0);
15070         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15071         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15072         tg3_full_unlock(tp);
15073
15074         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15075
15076         err = tg3_set_power_state(tp, target_state);
15077         if (err) {
15078                 int err2;
15079
15080                 tg3_full_lock(tp, 0);
15081
15082                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15083                 err2 = tg3_restart_hw(tp, 1);
15084                 if (err2)
15085                         goto out;
15086
15087                 tp->timer.expires = jiffies + tp->timer_offset;
15088                 add_timer(&tp->timer);
15089
15090                 netif_device_attach(dev);
15091                 tg3_netif_start(tp);
15092
15093 out:
15094                 tg3_full_unlock(tp);
15095
15096                 if (!err2)
15097                         tg3_phy_start(tp);
15098         }
15099
15100         return err;
15101 }
15102
15103 static int tg3_resume(struct pci_dev *pdev)
15104 {
15105         struct net_device *dev = pci_get_drvdata(pdev);
15106         struct tg3 *tp = netdev_priv(dev);
15107         int err;
15108
15109         pci_restore_state(tp->pdev);
15110
15111         if (!netif_running(dev))
15112                 return 0;
15113
15114         err = tg3_set_power_state(tp, PCI_D0);
15115         if (err)
15116                 return err;
15117
15118         netif_device_attach(dev);
15119
15120         tg3_full_lock(tp, 0);
15121
15122         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15123         err = tg3_restart_hw(tp, 1);
15124         if (err)
15125                 goto out;
15126
15127         tp->timer.expires = jiffies + tp->timer_offset;
15128         add_timer(&tp->timer);
15129
15130         tg3_netif_start(tp);
15131
15132 out:
15133         tg3_full_unlock(tp);
15134
15135         if (!err)
15136                 tg3_phy_start(tp);
15137
15138         return err;
15139 }
15140
15141 static struct pci_driver tg3_driver = {
15142         .name           = DRV_MODULE_NAME,
15143         .id_table       = tg3_pci_tbl,
15144         .probe          = tg3_init_one,
15145         .remove         = __devexit_p(tg3_remove_one),
15146         .suspend        = tg3_suspend,
15147         .resume         = tg3_resume
15148 };
15149
15150 static int __init tg3_init(void)
15151 {
15152         return pci_register_driver(&tg3_driver);
15153 }
15154
15155 static void __exit tg3_cleanup(void)
15156 {
15157         pci_unregister_driver(&tg3_driver);
15158 }
15159
15160 module_init(tg3_init);
15161 module_exit(tg3_cleanup);