drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define DRV_MODULE_VERSION      "3.110"
  71 #define DRV_MODULE_RELDATE      "April 9, 2010"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104 #define TG3_RSS_INDIR_TBL_SIZE          128
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_RX_DMA_ALIGN                16
 130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 131
 132 #define TG3_DMA_BYTE_ENAB               64
 133
 134 #define TG3_RX_STD_DMA_SZ               1536
 135 #define TG3_RX_JMB_DMA_SZ               9046
 136
 137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 138
 139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 141
 142 #define TG3_RX_STD_BUFF_RING_SIZE \
 143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 144
 145 #define TG3_RX_JMB_BUFF_RING_SIZE \
 146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 147
 148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 149  * that are at least dword aligned when used in PCIX mode.  The driver
 150  * works around this bug by double copying the packet.  This workaround
 151  * is built into the normal double copy length check for efficiency.
 152  *
 153  * However, the double copy is only necessary on those architectures
 154  * where unaligned memory accesses are inefficient.  For those architectures
 155  * where unaligned memory accesses incur little penalty, we can reintegrate
 156  * the 5701 in the normal rx path.  Doing so saves a device structure
 157  * dereference by hardcoding the double copy threshold in place.
 158  */
 159 #define TG3_RX_COPY_THRESHOLD           256
 160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 162 #else
 163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 164 #endif
 165
 166 /* minimum number of free TX descriptors required to wake up TX process */
 167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 168
 169 #define TG3_RAW_IP_ALIGN 2
 170
 171 /* number of ETHTOOL_GSTATS u64's */
 172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 173
 174 #define TG3_NUM_TEST            6
 175
 176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 177
 178 #define FIRMWARE_TG3            "tigon/tg3.bin"
 179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 181
 182 static char version[] __devinitdata =
 183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 184
 185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 187 MODULE_LICENSE("GPL");
 188 MODULE_VERSION(DRV_MODULE_VERSION);
 189 MODULE_FIRMWARE(FIRMWARE_TG3);
 190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 192
 193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 194 module_param(tg3_debug, int, 0);
 195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 196
 197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 280         {}
 281 };
 282
 283 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 284
 285 static const struct {
 286         const char string[ETH_GSTRING_LEN];
 287 } ethtool_stats_keys[TG3_NUM_STATS] = {
 288         { "rx_octets" },
 289         { "rx_fragments" },
 290         { "rx_ucast_packets" },
 291         { "rx_mcast_packets" },
 292         { "rx_bcast_packets" },
 293         { "rx_fcs_errors" },
 294         { "rx_align_errors" },
 295         { "rx_xon_pause_rcvd" },
 296         { "rx_xoff_pause_rcvd" },
 297         { "rx_mac_ctrl_rcvd" },
 298         { "rx_xoff_entered" },
 299         { "rx_frame_too_long_errors" },
 300         { "rx_jabbers" },
 301         { "rx_undersize_packets" },
 302         { "rx_in_length_errors" },
 303         { "rx_out_length_errors" },
 304         { "rx_64_or_less_octet_packets" },
 305         { "rx_65_to_127_octet_packets" },
 306         { "rx_128_to_255_octet_packets" },
 307         { "rx_256_to_511_octet_packets" },
 308         { "rx_512_to_1023_octet_packets" },
 309         { "rx_1024_to_1522_octet_packets" },
 310         { "rx_1523_to_2047_octet_packets" },
 311         { "rx_2048_to_4095_octet_packets" },
 312         { "rx_4096_to_8191_octet_packets" },
 313         { "rx_8192_to_9022_octet_packets" },
 314
 315         { "tx_octets" },
 316         { "tx_collisions" },
 317
 318         { "tx_xon_sent" },
 319         { "tx_xoff_sent" },
 320         { "tx_flow_control" },
 321         { "tx_mac_errors" },
 322         { "tx_single_collisions" },
 323         { "tx_mult_collisions" },
 324         { "tx_deferred" },
 325         { "tx_excessive_collisions" },
 326         { "tx_late_collisions" },
 327         { "tx_collide_2times" },
 328         { "tx_collide_3times" },
 329         { "tx_collide_4times" },
 330         { "tx_collide_5times" },
 331         { "tx_collide_6times" },
 332         { "tx_collide_7times" },
 333         { "tx_collide_8times" },
 334         { "tx_collide_9times" },
 335         { "tx_collide_10times" },
 336         { "tx_collide_11times" },
 337         { "tx_collide_12times" },
 338         { "tx_collide_13times" },
 339         { "tx_collide_14times" },
 340         { "tx_collide_15times" },
 341         { "tx_ucast_packets" },
 342         { "tx_mcast_packets" },
 343         { "tx_bcast_packets" },
 344         { "tx_carrier_sense_errors" },
 345         { "tx_discards" },
 346         { "tx_errors" },
 347
 348         { "dma_writeq_full" },
 349         { "dma_write_prioq_full" },
 350         { "rxbds_empty" },
 351         { "rx_discards" },
 352         { "rx_errors" },
 353         { "rx_threshold_hit" },
 354
 355         { "dma_readq_full" },
 356         { "dma_read_prioq_full" },
 357         { "tx_comp_queue_full" },
 358
 359         { "ring_set_send_prod_index" },
 360         { "ring_status_update" },
 361         { "nic_irqs" },
 362         { "nic_avoided_irqs" },
 363         { "nic_tx_threshold_hit" }
 364 };
 365
 366 static const struct {
 367         const char string[ETH_GSTRING_LEN];
 368 } ethtool_test_keys[TG3_NUM_TEST] = {
 369         { "nvram test     (online) " },
 370         { "link test      (online) " },
 371         { "register test  (offline)" },
 372         { "memory test    (offline)" },
 373         { "loopback test  (offline)" },
 374         { "interrupt test (offline)" },
 375 };
 376
 377 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         writel(val, tp->regs + off);
 380 }
 381
 382 static u32 tg3_read32(struct tg3 *tp, u32 off)
 383 {
 384         return readl(tp->regs + off);
 385 }
 386
 387 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->aperegs + off);
 390 }
 391
 392 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 393 {
 394         return readl(tp->aperegs + off);
 395 }
 396
 397 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 398 {
 399         unsigned long flags;
 400
 401         spin_lock_irqsave(&tp->indirect_lock, flags);
 402         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 404         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 405 }
 406
 407 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 408 {
 409         writel(val, tp->regs + off);
 410         readl(tp->regs + off);
 411 }
 412
 413 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 414 {
 415         unsigned long flags;
 416         u32 val;
 417
 418         spin_lock_irqsave(&tp->indirect_lock, flags);
 419         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 420         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 421         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 422         return val;
 423 }
 424
 425 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 426 {
 427         unsigned long flags;
 428
 429         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 431                                        TG3_64BIT_REG_LOW, val);
 432                 return;
 433         }
 434         if (off == TG3_RX_STD_PROD_IDX_REG) {
 435                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 436                                        TG3_64BIT_REG_LOW, val);
 437                 return;
 438         }
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444
 445         /* In indirect mode when disabling interrupts, we also need
 446          * to clear the interrupt bit in the GRC local ctrl register.
 447          */
 448         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 449             (val == 0x1)) {
 450                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 451                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 452         }
 453 }
 454
 455 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 456 {
 457         unsigned long flags;
 458         u32 val;
 459
 460         spin_lock_irqsave(&tp->indirect_lock, flags);
 461         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 462         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 463         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 464         return val;
 465 }
 466
 467 /* usec_wait specifies the wait time in usec when writing to certain registers
 468  * where it is unsafe to read back the register without some delay.
 469  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 470  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 471  */
 472 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 473 {
 474         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 475             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 476                 /* Non-posted methods */
 477                 tp->write32(tp, off, val);
 478         else {
 479                 /* Posted method */
 480                 tg3_write32(tp, off, val);
 481                 if (usec_wait)
 482                         udelay(usec_wait);
 483                 tp->read32(tp, off);
 484         }
 485         /* Wait again after the read for the posted method to guarantee that
 486          * the wait time is met.
 487          */
 488         if (usec_wait)
 489                 udelay(usec_wait);
 490 }
 491
 492 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 493 {
 494         tp->write32_mbox(tp, off, val);
 495         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 496             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 497                 tp->read32_mbox(tp, off);
 498 }
 499
 500 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 501 {
 502         void __iomem *mbox = tp->regs + off;
 503         writel(val, mbox);
 504         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 505                 writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 507                 readl(mbox);
 508 }
 509
 510 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 511 {
 512         return readl(tp->regs + off + GRCMBOX_BASE);
 513 }
 514
 515 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 516 {
 517         writel(val, tp->regs + off + GRCMBOX_BASE);
 518 }
 519
 520 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 521 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 522 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 523 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 524 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 525
 526 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 527 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 528 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 529 #define tr32(reg)                       tp->read32(tp, reg)
 530
 531 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 532 {
 533         unsigned long flags;
 534
 535         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 536             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 537                 return;
 538
 539         spin_lock_irqsave(&tp->indirect_lock, flags);
 540         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 543
 544                 /* Always leave this as zero. */
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 546         } else {
 547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 548                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 549
 550                 /* Always leave this as zero. */
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 552         }
 553         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 554 }
 555
 556 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 557 {
 558         unsigned long flags;
 559
 560         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 561             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 562                 *val = 0;
 563                 return;
 564         }
 565
 566         spin_lock_irqsave(&tp->indirect_lock, flags);
 567         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 569                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 570
 571                 /* Always leave this as zero. */
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 573         } else {
 574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 575                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 576
 577                 /* Always leave this as zero. */
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 579         }
 580         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 581 }
 582
 583 static void tg3_ape_lock_init(struct tg3 *tp)
 584 {
 585         int i;
 586         u32 regbase;
 587
 588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 589                 regbase = TG3_APE_LOCK_GRANT;
 590         else
 591                 regbase = TG3_APE_PER_LOCK_GRANT;
 592
 593         /* Make sure the driver hasn't any stale locks. */
 594         for (i = 0; i < 8; i++)
 595                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 596 }
 597
 598 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 599 {
 600         int i, off;
 601         int ret = 0;
 602         u32 status, req, gnt;
 603
 604         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 605                 return 0;
 606
 607         switch (locknum) {
 608         case TG3_APE_LOCK_GRC:
 609         case TG3_APE_LOCK_MEM:
 610                 break;
 611         default:
 612                 return -EINVAL;
 613         }
 614
 615         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 616                 req = TG3_APE_LOCK_REQ;
 617                 gnt = TG3_APE_LOCK_GRANT;
 618         } else {
 619                 req = TG3_APE_PER_LOCK_REQ;
 620                 gnt = TG3_APE_PER_LOCK_GRANT;
 621         }
 622
 623         off = 4 * locknum;
 624
 625         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 626
 627         /* Wait for up to 1 millisecond to acquire lock. */
 628         for (i = 0; i < 100; i++) {
 629                 status = tg3_ape_read32(tp, gnt + off);
 630                 if (status == APE_LOCK_GRANT_DRIVER)
 631                         break;
 632                 udelay(10);
 633         }
 634
 635         if (status != APE_LOCK_GRANT_DRIVER) {
 636                 /* Revoke the lock request. */
 637                 tg3_ape_write32(tp, gnt + off,
 638                                 APE_LOCK_GRANT_DRIVER);
 639
 640                 ret = -EBUSY;
 641         }
 642
 643         return ret;
 644 }
 645
 646 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 647 {
 648         u32 gnt;
 649
 650         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 651                 return;
 652
 653         switch (locknum) {
 654         case TG3_APE_LOCK_GRC:
 655         case TG3_APE_LOCK_MEM:
 656                 break;
 657         default:
 658                 return;
 659         }
 660
 661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 662                 gnt = TG3_APE_LOCK_GRANT;
 663         else
 664                 gnt = TG3_APE_PER_LOCK_GRANT;
 665
 666         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 667 }
 668
 669 static void tg3_disable_ints(struct tg3 *tp)
 670 {
 671         int i;
 672
 673         tw32(TG3PCI_MISC_HOST_CTRL,
 674              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 675         for (i = 0; i < tp->irq_max; i++)
 676                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 677 }
 678
 679 static void tg3_enable_ints(struct tg3 *tp)
 680 {
 681         int i;
 682
 683         tp->irq_sync = 0;
 684         wmb();
 685
 686         tw32(TG3PCI_MISC_HOST_CTRL,
 687              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 688
 689         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 690         for (i = 0; i < tp->irq_cnt; i++) {
 691                 struct tg3_napi *tnapi = &tp->napi[i];
 692
 693                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 694                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 695                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696
 697                 tp->coal_now |= tnapi->coal_now;
 698         }
 699
 700         /* Force an initial interrupt */
 701         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 702             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 703                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 704         else
 705                 tw32(HOSTCC_MODE, tp->coal_now);
 706
 707         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 708 }
 709
 710 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 711 {
 712         struct tg3 *tp = tnapi->tp;
 713         struct tg3_hw_status *sblk = tnapi->hw_status;
 714         unsigned int work_exists = 0;
 715
 716         /* check for phy events */
 717         if (!(tp->tg3_flags &
 718               (TG3_FLAG_USE_LINKCHG_REG |
 719                TG3_FLAG_POLL_SERDES))) {
 720                 if (sblk->status & SD_STATUS_LINK_CHG)
 721                         work_exists = 1;
 722         }
 723         /* check for RX/TX work to do */
 724         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 725             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 726                 work_exists = 1;
 727
 728         return work_exists;
 729 }
 730
 731 /* tg3_int_reenable
 732  *  similar to tg3_enable_ints, but it accurately determines whether there
 733  *  is new work pending and can return without flushing the PIO write
 734  *  which reenables interrupts
 735  */
 736 static void tg3_int_reenable(struct tg3_napi *tnapi)
 737 {
 738         struct tg3 *tp = tnapi->tp;
 739
 740         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 741         mmiowb();
 742
 743         /* When doing tagged status, this work check is unnecessary.
 744          * The last_tag we write above tells the chip which piece of
 745          * work we've completed.
 746          */
 747         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 748             tg3_has_work(tnapi))
 749                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 750                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 751 }
 752
 753 static void tg3_napi_disable(struct tg3 *tp)
 754 {
 755         int i;
 756
 757         for (i = tp->irq_cnt - 1; i >= 0; i--)
 758                 napi_disable(&tp->napi[i].napi);
 759 }
 760
 761 static void tg3_napi_enable(struct tg3 *tp)
 762 {
 763         int i;
 764
 765         for (i = 0; i < tp->irq_cnt; i++)
 766                 napi_enable(&tp->napi[i].napi);
 767 }
 768
 769 static inline void tg3_netif_stop(struct tg3 *tp)
 770 {
 771         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 772         tg3_napi_disable(tp);
 773         netif_tx_disable(tp->dev);
 774 }
 775
 776 static inline void tg3_netif_start(struct tg3 *tp)
 777 {
 778         /* NOTE: unconditional netif_tx_wake_all_queues is only
 779          * appropriate so long as all callers are assured to
 780          * have free tx slots (such as after tg3_init_hw)
 781          */
 782         netif_tx_wake_all_queues(tp->dev);
 783
 784         tg3_napi_enable(tp);
 785         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 786         tg3_enable_ints(tp);
 787 }
 788
 789 static void tg3_switch_clocks(struct tg3 *tp)
 790 {
 791         u32 clock_ctrl;
 792         u32 orig_clock_ctrl;
 793
 794         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 795             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 796                 return;
 797
 798         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 799
 800         orig_clock_ctrl = clock_ctrl;
 801         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 802                        CLOCK_CTRL_CLKRUN_OENABLE |
 803                        0x1f);
 804         tp->pci_clock_ctrl = clock_ctrl;
 805
 806         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 807                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 808                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 809                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 810                 }
 811         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 812                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 813                             clock_ctrl |
 814                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 815                             40);
 816                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 817                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 818                             40);
 819         }
 820         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 821 }
 822
 823 #define PHY_BUSY_LOOPS  5000
 824
 825 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 826 {
 827         u32 frame_val;
 828         unsigned int loops;
 829         int ret;
 830
 831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 832                 tw32_f(MAC_MI_MODE,
 833                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 834                 udelay(80);
 835         }
 836
 837         *val = 0x0;
 838
 839         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 840                       MI_COM_PHY_ADDR_MASK);
 841         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 842                       MI_COM_REG_ADDR_MASK);
 843         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 844
 845         tw32_f(MAC_MI_COM, frame_val);
 846
 847         loops = PHY_BUSY_LOOPS;
 848         while (loops != 0) {
 849                 udelay(10);
 850                 frame_val = tr32(MAC_MI_COM);
 851
 852                 if ((frame_val & MI_COM_BUSY) == 0) {
 853                         udelay(5);
 854                         frame_val = tr32(MAC_MI_COM);
 855                         break;
 856                 }
 857                 loops -= 1;
 858         }
 859
 860         ret = -EBUSY;
 861         if (loops != 0) {
 862                 *val = frame_val & MI_COM_DATA_MASK;
 863                 ret = 0;
 864         }
 865
 866         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 867                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 868                 udelay(80);
 869         }
 870
 871         return ret;
 872 }
 873
 874 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 875 {
 876         u32 frame_val;
 877         unsigned int loops;
 878         int ret;
 879
 880         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 881             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 882                 return 0;
 883
 884         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 885                 tw32_f(MAC_MI_MODE,
 886                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 887                 udelay(80);
 888         }
 889
 890         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 891                       MI_COM_PHY_ADDR_MASK);
 892         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 893                       MI_COM_REG_ADDR_MASK);
 894         frame_val |= (val & MI_COM_DATA_MASK);
 895         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 896
 897         tw32_f(MAC_MI_COM, frame_val);
 898
 899         loops = PHY_BUSY_LOOPS;
 900         while (loops != 0) {
 901                 udelay(10);
 902                 frame_val = tr32(MAC_MI_COM);
 903                 if ((frame_val & MI_COM_BUSY) == 0) {
 904                         udelay(5);
 905                         frame_val = tr32(MAC_MI_COM);
 906                         break;
 907                 }
 908                 loops -= 1;
 909         }
 910
 911         ret = -EBUSY;
 912         if (loops != 0)
 913                 ret = 0;
 914
 915         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 916                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 917                 udelay(80);
 918         }
 919
 920         return ret;
 921 }
 922
 923 static int tg3_bmcr_reset(struct tg3 *tp)
 924 {
 925         u32 phy_control;
 926         int limit, err;
 927
 928         /* OK, reset it, and poll the BMCR_RESET bit until it
 929          * clears or we time out.
 930          */
 931         phy_control = BMCR_RESET;
 932         err = tg3_writephy(tp, MII_BMCR, phy_control);
 933         if (err != 0)
 934                 return -EBUSY;
 935
 936         limit = 5000;
 937         while (limit--) {
 938                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 939                 if (err != 0)
 940                         return -EBUSY;
 941
 942                 if ((phy_control & BMCR_RESET) == 0) {
 943                         udelay(40);
 944                         break;
 945                 }
 946                 udelay(10);
 947         }
 948         if (limit < 0)
 949                 return -EBUSY;
 950
 951         return 0;
 952 }
 953
 954 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 955 {
 956         struct tg3 *tp = bp->priv;
 957         u32 val;
 958
 959         spin_lock_bh(&tp->lock);
 960
 961         if (tg3_readphy(tp, reg, &val))
 962                 val = -EIO;
 963
 964         spin_unlock_bh(&tp->lock);
 965
 966         return val;
 967 }
 968
 969 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 970 {
 971         struct tg3 *tp = bp->priv;
 972         u32 ret = 0;
 973
 974         spin_lock_bh(&tp->lock);
 975
 976         if (tg3_writephy(tp, reg, val))
 977                 ret = -EIO;
 978
 979         spin_unlock_bh(&tp->lock);
 980
 981         return ret;
 982 }
 983
 984 static int tg3_mdio_reset(struct mii_bus *bp)
 985 {
 986         return 0;
 987 }
 988
 989 static void tg3_mdio_config_5785(struct tg3 *tp)
 990 {
 991         u32 val;
 992         struct phy_device *phydev;
 993
 994         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 995         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 996         case PHY_ID_BCM50610:
 997         case PHY_ID_BCM50610M:
 998                 val = MAC_PHYCFG2_50610_LED_MODES;
 999                 break;
1000         case PHY_ID_BCMAC131:
1001                 val = MAC_PHYCFG2_AC131_LED_MODES;
1002                 break;
1003         case PHY_ID_RTL8211C:
1004                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1005                 break;
1006         case PHY_ID_RTL8201E:
1007                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1008                 break;
1009         default:
1010                 return;
1011         }
1012
1013         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1014                 tw32(MAC_PHYCFG2, val);
1015
1016                 val = tr32(MAC_PHYCFG1);
1017                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1018                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1019                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1020                 tw32(MAC_PHYCFG1, val);
1021
1022                 return;
1023         }
1024
1025         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1026                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1027                        MAC_PHYCFG2_FMODE_MASK_MASK |
1028                        MAC_PHYCFG2_GMODE_MASK_MASK |
1029                        MAC_PHYCFG2_ACT_MASK_MASK   |
1030                        MAC_PHYCFG2_QUAL_MASK_MASK |
1031                        MAC_PHYCFG2_INBAND_ENABLE;
1032
1033         tw32(MAC_PHYCFG2, val);
1034
1035         val = tr32(MAC_PHYCFG1);
1036         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1037                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1038         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1039                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1043         }
1044         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1045                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1046         tw32(MAC_PHYCFG1, val);
1047
1048         val = tr32(MAC_EXT_RGMII_MODE);
1049         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1050                  MAC_RGMII_MODE_RX_QUALITY |
1051                  MAC_RGMII_MODE_RX_ACTIVITY |
1052                  MAC_RGMII_MODE_RX_ENG_DET |
1053                  MAC_RGMII_MODE_TX_ENABLE |
1054                  MAC_RGMII_MODE_TX_LOWPWR |
1055                  MAC_RGMII_MODE_TX_RESET);
1056         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1057                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1058                         val |= MAC_RGMII_MODE_RX_INT_B |
1059                                MAC_RGMII_MODE_RX_QUALITY |
1060                                MAC_RGMII_MODE_RX_ACTIVITY |
1061                                MAC_RGMII_MODE_RX_ENG_DET;
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1063                         val |= MAC_RGMII_MODE_TX_ENABLE |
1064                                MAC_RGMII_MODE_TX_LOWPWR |
1065                                MAC_RGMII_MODE_TX_RESET;
1066         }
1067         tw32(MAC_EXT_RGMII_MODE, val);
1068 }
1069
1070 static void tg3_mdio_start(struct tg3 *tp)
1071 {
1072         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1073         tw32_f(MAC_MI_MODE, tp->mi_mode);
1074         udelay(80);
1075
1076         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1078                 tg3_mdio_config_5785(tp);
1079 }
1080
1081 static int tg3_mdio_init(struct tg3 *tp)
1082 {
1083         int i;
1084         u32 reg;
1085         struct phy_device *phydev;
1086
1087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1088                 u32 funcnum, is_serdes;
1089
1090                 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1091                 if (funcnum)
1092                         tp->phy_addr = 2;
1093                 else
1094                         tp->phy_addr = 1;
1095
1096                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1097                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1098                 else
1099                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1100                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1101                 if (is_serdes)
1102                         tp->phy_addr += 7;
1103         } else
1104                 tp->phy_addr = TG3_PHY_MII_ADDR;
1105
1106         tg3_mdio_start(tp);
1107
1108         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1109             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1110                 return 0;
1111
1112         tp->mdio_bus = mdiobus_alloc();
1113         if (tp->mdio_bus == NULL)
1114                 return -ENOMEM;
1115
1116         tp->mdio_bus->name     = "tg3 mdio bus";
1117         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1118                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1119         tp->mdio_bus->priv     = tp;
1120         tp->mdio_bus->parent   = &tp->pdev->dev;
1121         tp->mdio_bus->read     = &tg3_mdio_read;
1122         tp->mdio_bus->write    = &tg3_mdio_write;
1123         tp->mdio_bus->reset    = &tg3_mdio_reset;
1124         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1125         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1126
1127         for (i = 0; i < PHY_MAX_ADDR; i++)
1128                 tp->mdio_bus->irq[i] = PHY_POLL;
1129
1130         /* The bus registration will look for all the PHYs on the mdio bus.
1131          * Unfortunately, it does not ensure the PHY is powered up before
1132          * accessing the PHY ID registers.  A chip reset is the
1133          * quickest way to bring the device back to an operational state..
1134          */
1135         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1136                 tg3_bmcr_reset(tp);
1137
1138         i = mdiobus_register(tp->mdio_bus);
1139         if (i) {
1140                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1141                 mdiobus_free(tp->mdio_bus);
1142                 return i;
1143         }
1144
1145         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1146
1147         if (!phydev || !phydev->drv) {
1148                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1149                 mdiobus_unregister(tp->mdio_bus);
1150                 mdiobus_free(tp->mdio_bus);
1151                 return -ENODEV;
1152         }
1153
1154         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1155         case PHY_ID_BCM57780:
1156                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1157                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1158                 break;
1159         case PHY_ID_BCM50610:
1160         case PHY_ID_BCM50610M:
1161                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1162                                      PHY_BRCM_RX_REFCLK_UNUSED |
1163                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1164                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1165                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1166                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1167                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1168                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1169                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1170                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1171                 /* fallthru */
1172         case PHY_ID_RTL8211C:
1173                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1174                 break;
1175         case PHY_ID_RTL8201E:
1176         case PHY_ID_BCMAC131:
1177                 phydev->interface = PHY_INTERFACE_MODE_MII;
1178                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1179                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1180                 break;
1181         }
1182
1183         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1184
1185         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1186                 tg3_mdio_config_5785(tp);
1187
1188         return 0;
1189 }
1190
1191 static void tg3_mdio_fini(struct tg3 *tp)
1192 {
1193         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1194                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1195                 mdiobus_unregister(tp->mdio_bus);
1196                 mdiobus_free(tp->mdio_bus);
1197         }
1198 }
1199
1200 /* tp->lock is held. */
1201 static inline void tg3_generate_fw_event(struct tg3 *tp)
1202 {
1203         u32 val;
1204
1205         val = tr32(GRC_RX_CPU_EVENT);
1206         val |= GRC_RX_CPU_DRIVER_EVENT;
1207         tw32_f(GRC_RX_CPU_EVENT, val);
1208
1209         tp->last_event_jiffies = jiffies;
1210 }
1211
1212 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1213
1214 /* tp->lock is held. */
1215 static void tg3_wait_for_event_ack(struct tg3 *tp)
1216 {
1217         int i;
1218         unsigned int delay_cnt;
1219         long time_remain;
1220
1221         /* If enough time has passed, no wait is necessary. */
1222         time_remain = (long)(tp->last_event_jiffies + 1 +
1223                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1224                       (long)jiffies;
1225         if (time_remain < 0)
1226                 return;
1227
1228         /* Check if we can shorten the wait time. */
1229         delay_cnt = jiffies_to_usecs(time_remain);
1230         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1231                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1232         delay_cnt = (delay_cnt >> 3) + 1;
1233
1234         for (i = 0; i < delay_cnt; i++) {
1235                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1236                         break;
1237                 udelay(8);
1238         }
1239 }
1240
1241 /* tp->lock is held. */
1242 static void tg3_ump_link_report(struct tg3 *tp)
1243 {
1244         u32 reg;
1245         u32 val;
1246
1247         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1248             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1249                 return;
1250
1251         tg3_wait_for_event_ack(tp);
1252
1253         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1254
1255         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1256
1257         val = 0;
1258         if (!tg3_readphy(tp, MII_BMCR, &reg))
1259                 val = reg << 16;
1260         if (!tg3_readphy(tp, MII_BMSR, &reg))
1261                 val |= (reg & 0xffff);
1262         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1263
1264         val = 0;
1265         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1266                 val = reg << 16;
1267         if (!tg3_readphy(tp, MII_LPA, &reg))
1268                 val |= (reg & 0xffff);
1269         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1270
1271         val = 0;
1272         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1273                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1274                         val = reg << 16;
1275                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1276                         val |= (reg & 0xffff);
1277         }
1278         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1279
1280         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1281                 val = reg << 16;
1282         else
1283                 val = 0;
1284         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1285
1286         tg3_generate_fw_event(tp);
1287 }
1288
1289 static void tg3_link_report(struct tg3 *tp)
1290 {
1291         if (!netif_carrier_ok(tp->dev)) {
1292                 netif_info(tp, link, tp->dev, "Link is down\n");
1293                 tg3_ump_link_report(tp);
1294         } else if (netif_msg_link(tp)) {
1295                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1296                             (tp->link_config.active_speed == SPEED_1000 ?
1297                              1000 :
1298                              (tp->link_config.active_speed == SPEED_100 ?
1299                               100 : 10)),
1300                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1301                              "full" : "half"));
1302
1303                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1304                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1305                             "on" : "off",
1306                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1307                             "on" : "off");
1308                 tg3_ump_link_report(tp);
1309         }
1310 }
1311
1312 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1313 {
1314         u16 miireg;
1315
1316         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1317                 miireg = ADVERTISE_PAUSE_CAP;
1318         else if (flow_ctrl & FLOW_CTRL_TX)
1319                 miireg = ADVERTISE_PAUSE_ASYM;
1320         else if (flow_ctrl & FLOW_CTRL_RX)
1321                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1322         else
1323                 miireg = 0;
1324
1325         return miireg;
1326 }
1327
1328 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1329 {
1330         u16 miireg;
1331
1332         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1333                 miireg = ADVERTISE_1000XPAUSE;
1334         else if (flow_ctrl & FLOW_CTRL_TX)
1335                 miireg = ADVERTISE_1000XPSE_ASYM;
1336         else if (flow_ctrl & FLOW_CTRL_RX)
1337                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1338         else
1339                 miireg = 0;
1340
1341         return miireg;
1342 }
1343
1344 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1345 {
1346         u8 cap = 0;
1347
1348         if (lcladv & ADVERTISE_1000XPAUSE) {
1349                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1350                         if (rmtadv & LPA_1000XPAUSE)
1351                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1352                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1353                                 cap = FLOW_CTRL_RX;
1354                 } else {
1355                         if (rmtadv & LPA_1000XPAUSE)
1356                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1357                 }
1358         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1359                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1360                         cap = FLOW_CTRL_TX;
1361         }
1362
1363         return cap;
1364 }
1365
1366 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1367 {
1368         u8 autoneg;
1369         u8 flowctrl = 0;
1370         u32 old_rx_mode = tp->rx_mode;
1371         u32 old_tx_mode = tp->tx_mode;
1372
1373         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1374                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1375         else
1376                 autoneg = tp->link_config.autoneg;
1377
1378         if (autoneg == AUTONEG_ENABLE &&
1379             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1380                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1381                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1382                 else
1383                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1384         } else
1385                 flowctrl = tp->link_config.flowctrl;
1386
1387         tp->link_config.active_flowctrl = flowctrl;
1388
1389         if (flowctrl & FLOW_CTRL_RX)
1390                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1391         else
1392                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1393
1394         if (old_rx_mode != tp->rx_mode)
1395                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1396
1397         if (flowctrl & FLOW_CTRL_TX)
1398                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1399         else
1400                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1401
1402         if (old_tx_mode != tp->tx_mode)
1403                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1404 }
1405
1406 static void tg3_adjust_link(struct net_device *dev)
1407 {
1408         u8 oldflowctrl, linkmesg = 0;
1409         u32 mac_mode, lcl_adv, rmt_adv;
1410         struct tg3 *tp = netdev_priv(dev);
1411         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1412
1413         spin_lock_bh(&tp->lock);
1414
1415         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1416                                     MAC_MODE_HALF_DUPLEX);
1417
1418         oldflowctrl = tp->link_config.active_flowctrl;
1419
1420         if (phydev->link) {
1421                 lcl_adv = 0;
1422                 rmt_adv = 0;
1423
1424                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1425                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1426                 else if (phydev->speed == SPEED_1000 ||
1427                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1428                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1429                 else
1430                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1431
1432                 if (phydev->duplex == DUPLEX_HALF)
1433                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1434                 else {
1435                         lcl_adv = tg3_advert_flowctrl_1000T(
1436                                   tp->link_config.flowctrl);
1437
1438                         if (phydev->pause)
1439                                 rmt_adv = LPA_PAUSE_CAP;
1440                         if (phydev->asym_pause)
1441                                 rmt_adv |= LPA_PAUSE_ASYM;
1442                 }
1443
1444                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1445         } else
1446                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1447
1448         if (mac_mode != tp->mac_mode) {
1449                 tp->mac_mode = mac_mode;
1450                 tw32_f(MAC_MODE, tp->mac_mode);
1451                 udelay(40);
1452         }
1453
1454         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1455                 if (phydev->speed == SPEED_10)
1456                         tw32(MAC_MI_STAT,
1457                              MAC_MI_STAT_10MBPS_MODE |
1458                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1459                 else
1460                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1461         }
1462
1463         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1464                 tw32(MAC_TX_LENGTHS,
1465                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1466                       (6 << TX_LENGTHS_IPG_SHIFT) |
1467                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1468         else
1469                 tw32(MAC_TX_LENGTHS,
1470                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1471                       (6 << TX_LENGTHS_IPG_SHIFT) |
1472                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1473
1474         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1475             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1476             phydev->speed != tp->link_config.active_speed ||
1477             phydev->duplex != tp->link_config.active_duplex ||
1478             oldflowctrl != tp->link_config.active_flowctrl)
1479                 linkmesg = 1;
1480
1481         tp->link_config.active_speed = phydev->speed;
1482         tp->link_config.active_duplex = phydev->duplex;
1483
1484         spin_unlock_bh(&tp->lock);
1485
1486         if (linkmesg)
1487                 tg3_link_report(tp);
1488 }
1489
1490 static int tg3_phy_init(struct tg3 *tp)
1491 {
1492         struct phy_device *phydev;
1493
1494         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1495                 return 0;
1496
1497         /* Bring the PHY back to a known state. */
1498         tg3_bmcr_reset(tp);
1499
1500         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1501
1502         /* Attach the MAC to the PHY. */
1503         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1504                              phydev->dev_flags, phydev->interface);
1505         if (IS_ERR(phydev)) {
1506                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1507                 return PTR_ERR(phydev);
1508         }
1509
1510         /* Mask with MAC supported features. */
1511         switch (phydev->interface) {
1512         case PHY_INTERFACE_MODE_GMII:
1513         case PHY_INTERFACE_MODE_RGMII:
1514                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1515                         phydev->supported &= (PHY_GBIT_FEATURES |
1516                                               SUPPORTED_Pause |
1517                                               SUPPORTED_Asym_Pause);
1518                         break;
1519                 }
1520                 /* fallthru */
1521         case PHY_INTERFACE_MODE_MII:
1522                 phydev->supported &= (PHY_BASIC_FEATURES |
1523                                       SUPPORTED_Pause |
1524                                       SUPPORTED_Asym_Pause);
1525                 break;
1526         default:
1527                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528                 return -EINVAL;
1529         }
1530
1531         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1532
1533         phydev->advertising = phydev->supported;
1534
1535         return 0;
1536 }
1537
1538 static void tg3_phy_start(struct tg3 *tp)
1539 {
1540         struct phy_device *phydev;
1541
1542         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1543                 return;
1544
1545         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1546
1547         if (tp->link_config.phy_is_low_power) {
1548                 tp->link_config.phy_is_low_power = 0;
1549                 phydev->speed = tp->link_config.orig_speed;
1550                 phydev->duplex = tp->link_config.orig_duplex;
1551                 phydev->autoneg = tp->link_config.orig_autoneg;
1552                 phydev->advertising = tp->link_config.orig_advertising;
1553         }
1554
1555         phy_start(phydev);
1556
1557         phy_start_aneg(phydev);
1558 }
1559
1560 static void tg3_phy_stop(struct tg3 *tp)
1561 {
1562         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1563                 return;
1564
1565         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1566 }
1567
1568 static void tg3_phy_fini(struct tg3 *tp)
1569 {
1570         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1571                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1572                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1573         }
1574 }
1575
1576 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1577 {
1578         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1579         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1580 }
1581
1582 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1583 {
1584         u32 phytest;
1585
1586         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1587                 u32 phy;
1588
1589                 tg3_writephy(tp, MII_TG3_FET_TEST,
1590                              phytest | MII_TG3_FET_SHADOW_EN);
1591                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1592                         if (enable)
1593                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1594                         else
1595                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1596                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1597                 }
1598                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1599         }
1600 }
1601
1602 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1603 {
1604         u32 reg;
1605
1606         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1607                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1608              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1609                 return;
1610
1611         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1612                 tg3_phy_fet_toggle_apd(tp, enable);
1613                 return;
1614         }
1615
1616         reg = MII_TG3_MISC_SHDW_WREN |
1617               MII_TG3_MISC_SHDW_SCR5_SEL |
1618               MII_TG3_MISC_SHDW_SCR5_LPED |
1619               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1620               MII_TG3_MISC_SHDW_SCR5_SDTL |
1621               MII_TG3_MISC_SHDW_SCR5_C125OE;
1622         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1623                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1624
1625         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1626
1627
1628         reg = MII_TG3_MISC_SHDW_WREN |
1629               MII_TG3_MISC_SHDW_APD_SEL |
1630               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1631         if (enable)
1632                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1633
1634         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1635 }
1636
1637 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1638 {
1639         u32 phy;
1640
1641         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1642             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1643                 return;
1644
1645         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1646                 u32 ephy;
1647
1648                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1649                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1650
1651                         tg3_writephy(tp, MII_TG3_FET_TEST,
1652                                      ephy | MII_TG3_FET_SHADOW_EN);
1653                         if (!tg3_readphy(tp, reg, &phy)) {
1654                                 if (enable)
1655                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1656                                 else
1657                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1658                                 tg3_writephy(tp, reg, phy);
1659                         }
1660                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1661                 }
1662         } else {
1663                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1664                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1665                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1666                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1667                         if (enable)
1668                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1669                         else
1670                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1671                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1672                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1673                 }
1674         }
1675 }
1676
1677 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1678 {
1679         u32 val;
1680
1681         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1682                 return;
1683
1684         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1685             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1686                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1687                              (val | (1 << 15) | (1 << 4)));
1688 }
1689
1690 static void tg3_phy_apply_otp(struct tg3 *tp)
1691 {
1692         u32 otp, phy;
1693
1694         if (!tp->phy_otp)
1695                 return;
1696
1697         otp = tp->phy_otp;
1698
1699         /* Enable SM_DSP clock and tx 6dB coding. */
1700         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1701               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1702               MII_TG3_AUXCTL_ACTL_TX_6DB;
1703         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1704
1705         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1706         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1707         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1708
1709         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1710               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1711         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1712
1713         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1714         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1715         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1716
1717         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1718         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1719
1720         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1722
1723         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1724               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1725         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1726
1727         /* Turn off SM_DSP clock. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_TX_6DB;
1730         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1731 }
1732
1733 static int tg3_wait_macro_done(struct tg3 *tp)
1734 {
1735         int limit = 100;
1736
1737         while (limit--) {
1738                 u32 tmp32;
1739
1740                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1741                         if ((tmp32 & 0x1000) == 0)
1742                                 break;
1743                 }
1744         }
1745         if (limit < 0)
1746                 return -EBUSY;
1747
1748         return 0;
1749 }
1750
1751 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1752 {
1753         static const u32 test_pat[4][6] = {
1754         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1755         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1756         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1757         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1758         };
1759         int chan;
1760
1761         for (chan = 0; chan < 4; chan++) {
1762                 int i;
1763
1764                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1765                              (chan * 0x2000) | 0x0200);
1766                 tg3_writephy(tp, 0x16, 0x0002);
1767
1768                 for (i = 0; i < 6; i++)
1769                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1770                                      test_pat[chan][i]);
1771
1772                 tg3_writephy(tp, 0x16, 0x0202);
1773                 if (tg3_wait_macro_done(tp)) {
1774                         *resetp = 1;
1775                         return -EBUSY;
1776                 }
1777
1778                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1779                              (chan * 0x2000) | 0x0200);
1780                 tg3_writephy(tp, 0x16, 0x0082);
1781                 if (tg3_wait_macro_done(tp)) {
1782                         *resetp = 1;
1783                         return -EBUSY;
1784                 }
1785
1786                 tg3_writephy(tp, 0x16, 0x0802);
1787                 if (tg3_wait_macro_done(tp)) {
1788                         *resetp = 1;
1789                         return -EBUSY;
1790                 }
1791
1792                 for (i = 0; i < 6; i += 2) {
1793                         u32 low, high;
1794
1795                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1796                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1797                             tg3_wait_macro_done(tp)) {
1798                                 *resetp = 1;
1799                                 return -EBUSY;
1800                         }
1801                         low &= 0x7fff;
1802                         high &= 0x000f;
1803                         if (low != test_pat[chan][i] ||
1804                             high != test_pat[chan][i+1]) {
1805                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1806                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1807                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1808
1809                                 return -EBUSY;
1810                         }
1811                 }
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1818 {
1819         int chan;
1820
1821         for (chan = 0; chan < 4; chan++) {
1822                 int i;
1823
1824                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1825                              (chan * 0x2000) | 0x0200);
1826                 tg3_writephy(tp, 0x16, 0x0002);
1827                 for (i = 0; i < 6; i++)
1828                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1829                 tg3_writephy(tp, 0x16, 0x0202);
1830                 if (tg3_wait_macro_done(tp))
1831                         return -EBUSY;
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1838 {
1839         u32 reg32, phy9_orig;
1840         int retries, do_phy_reset, err;
1841
1842         retries = 10;
1843         do_phy_reset = 1;
1844         do {
1845                 if (do_phy_reset) {
1846                         err = tg3_bmcr_reset(tp);
1847                         if (err)
1848                                 return err;
1849                         do_phy_reset = 0;
1850                 }
1851
1852                 /* Disable transmitter and interrupt.  */
1853                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1854                         continue;
1855
1856                 reg32 |= 0x3000;
1857                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1858
1859                 /* Set full-duplex, 1000 mbps.  */
1860                 tg3_writephy(tp, MII_BMCR,
1861                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1862
1863                 /* Set to master mode.  */
1864                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1865                         continue;
1866
1867                 tg3_writephy(tp, MII_TG3_CTRL,
1868                              (MII_TG3_CTRL_AS_MASTER |
1869                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1870
1871                 /* Enable SM_DSP_CLOCK and 6dB.  */
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1873
1874                 /* Block the PHY control access.  */
1875                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1876                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1877
1878                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1879                 if (!err)
1880                         break;
1881         } while (--retries);
1882
1883         err = tg3_phy_reset_chanpat(tp);
1884         if (err)
1885                 return err;
1886
1887         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1888         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1889
1890         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1891         tg3_writephy(tp, 0x16, 0x0000);
1892
1893         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1894             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1895                 /* Set Extended packet length bit for jumbo frames */
1896                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1897         } else {
1898                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1899         }
1900
1901         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1902
1903         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1904                 reg32 &= ~0x3000;
1905                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1906         } else if (!err)
1907                 err = -EBUSY;
1908
1909         return err;
1910 }
1911
1912 /* This will reset the tigon3 PHY if there is no valid
1913  * link unless the FORCE argument is non-zero.
1914  */
1915 static int tg3_phy_reset(struct tg3 *tp)
1916 {
1917         u32 cpmuctrl;
1918         u32 phy_status;
1919         int err;
1920
1921         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1922                 u32 val;
1923
1924                 val = tr32(GRC_MISC_CFG);
1925                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1926                 udelay(40);
1927         }
1928         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1929         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1930         if (err != 0)
1931                 return -EBUSY;
1932
1933         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1934                 netif_carrier_off(tp->dev);
1935                 tg3_link_report(tp);
1936         }
1937
1938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1940             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1941                 err = tg3_phy_reset_5703_4_5(tp);
1942                 if (err)
1943                         return err;
1944                 goto out;
1945         }
1946
1947         cpmuctrl = 0;
1948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1949             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1950                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1951                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1952                         tw32(TG3_CPMU_CTRL,
1953                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1954         }
1955
1956         err = tg3_bmcr_reset(tp);
1957         if (err)
1958                 return err;
1959
1960         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1961                 u32 phy;
1962
1963                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1964                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1965
1966                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1967         }
1968
1969         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1970             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1971                 u32 val;
1972
1973                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1974                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1975                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1976                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1977                         udelay(40);
1978                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1979                 }
1980         }
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1983             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1984                 return 0;
1985
1986         tg3_phy_apply_otp(tp);
1987
1988         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1989                 tg3_phy_toggle_apd(tp, true);
1990         else
1991                 tg3_phy_toggle_apd(tp, false);
1992
1993 out:
1994         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1996                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1997                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1998                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1999                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
2000                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2001         }
2002         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
2003                 tg3_writephy(tp, 0x1c, 0x8d68);
2004                 tg3_writephy(tp, 0x1c, 0x8d68);
2005         }
2006         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2007                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2012                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2013                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2014                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2015         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2016                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2017                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2018                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2020                         tg3_writephy(tp, MII_TG3_TEST1,
2021                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2022                 } else
2023                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2024                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2025         }
2026         /* Set Extended packet length bit (bit 14) on all chips that */
2027         /* support jumbo frames */
2028         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2029                 /* Cannot do read-modify-write on 5401 */
2030                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2031         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2032                 u32 phy_reg;
2033
2034                 /* Set bit 14 with read-modify-write to preserve other bits */
2035                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2036                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2037                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2038         }
2039
2040         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2041          * jumbo frames transmission.
2042          */
2043         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2044                 u32 phy_reg;
2045
2046                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2047                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2048                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2049         }
2050
2051         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2052                 /* adjust output voltage */
2053                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2054         }
2055
2056         tg3_phy_toggle_automdix(tp, 1);
2057         tg3_phy_set_wirespeed(tp);
2058         return 0;
2059 }
2060
2061 static void tg3_frob_aux_power(struct tg3 *tp)
2062 {
2063         struct tg3 *tp_peer = tp;
2064
2065         /* The GPIOs do something completely different on 57765. */
2066         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2068                 return;
2069
2070         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2071             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2073                 struct net_device *dev_peer;
2074
2075                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2076                 /* remove_one() may have been run on the peer. */
2077                 if (!dev_peer)
2078                         tp_peer = tp;
2079                 else
2080                         tp_peer = netdev_priv(dev_peer);
2081         }
2082
2083         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2084             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2085             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2086             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2087                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2088                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2089                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2090                                     (GRC_LCLCTRL_GPIO_OE0 |
2091                                      GRC_LCLCTRL_GPIO_OE1 |
2092                                      GRC_LCLCTRL_GPIO_OE2 |
2093                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2094                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2095                                     100);
2096                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2097                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2098                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2099                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2100                                              GRC_LCLCTRL_GPIO_OE1 |
2101                                              GRC_LCLCTRL_GPIO_OE2 |
2102                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2103                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2104                                              tp->grc_local_ctrl;
2105                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2106
2107                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2108                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2109
2110                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2111                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2112                 } else {
2113                         u32 no_gpio2;
2114                         u32 grc_local_ctrl = 0;
2115
2116                         if (tp_peer != tp &&
2117                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2118                                 return;
2119
2120                         /* Workaround to prevent overdrawing Amps. */
2121                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2122                             ASIC_REV_5714) {
2123                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2124                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2125                                             grc_local_ctrl, 100);
2126                         }
2127
2128                         /* On 5753 and variants, GPIO2 cannot be used. */
2129                         no_gpio2 = tp->nic_sram_data_cfg &
2130                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2131
2132                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2133                                          GRC_LCLCTRL_GPIO_OE1 |
2134                                          GRC_LCLCTRL_GPIO_OE2 |
2135                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2136                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2137                         if (no_gpio2) {
2138                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2139                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2140                         }
2141                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2142                                                     grc_local_ctrl, 100);
2143
2144                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2145
2146                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2147                                                     grc_local_ctrl, 100);
2148
2149                         if (!no_gpio2) {
2150                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2151                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2152                                             grc_local_ctrl, 100);
2153                         }
2154                 }
2155         } else {
2156                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2157                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2158                         if (tp_peer != tp &&
2159                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2160                                 return;
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     (GRC_LCLCTRL_GPIO_OE1 |
2164                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2165
2166                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2167                                     GRC_LCLCTRL_GPIO_OE1, 100);
2168
2169                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2170                                     (GRC_LCLCTRL_GPIO_OE1 |
2171                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2172                 }
2173         }
2174 }
2175
2176 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2177 {
2178         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2179                 return 1;
2180         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2181                 if (speed != SPEED_10)
2182                         return 1;
2183         } else if (speed == SPEED_10)
2184                 return 1;
2185
2186         return 0;
2187 }
2188
2189 static int tg3_setup_phy(struct tg3 *, int);
2190
2191 #define RESET_KIND_SHUTDOWN     0
2192 #define RESET_KIND_INIT         1
2193 #define RESET_KIND_SUSPEND      2
2194
2195 static void tg3_write_sig_post_reset(struct tg3 *, int);
2196 static int tg3_halt_cpu(struct tg3 *, u32);
2197
2198 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2199 {
2200         u32 val;
2201
2202         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2203                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2204                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2205                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2206
2207                         sg_dig_ctrl |=
2208                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2209                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2210                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2211                 }
2212                 return;
2213         }
2214
2215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2216                 tg3_bmcr_reset(tp);
2217                 val = tr32(GRC_MISC_CFG);
2218                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2219                 udelay(40);
2220                 return;
2221         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2222                 u32 phytest;
2223                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2224                         u32 phy;
2225
2226                         tg3_writephy(tp, MII_ADVERTISE, 0);
2227                         tg3_writephy(tp, MII_BMCR,
2228                                      BMCR_ANENABLE | BMCR_ANRESTART);
2229
2230                         tg3_writephy(tp, MII_TG3_FET_TEST,
2231                                      phytest | MII_TG3_FET_SHADOW_EN);
2232                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2233                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2234                                 tg3_writephy(tp,
2235                                              MII_TG3_FET_SHDW_AUXMODE4,
2236                                              phy);
2237                         }
2238                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2239                 }
2240                 return;
2241         } else if (do_low_power) {
2242                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2243                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2244
2245                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2246                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2247                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2248                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2249                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2250         }
2251
2252         /* The PHY should not be powered down on some chips because
2253          * of bugs.
2254          */
2255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2257             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2258              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2259                 return;
2260
2261         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2262             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2263                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2264                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2265                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2266                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2267         }
2268
2269         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2270 }
2271
2272 /* tp->lock is held. */
2273 static int tg3_nvram_lock(struct tg3 *tp)
2274 {
2275         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2276                 int i;
2277
2278                 if (tp->nvram_lock_cnt == 0) {
2279                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2280                         for (i = 0; i < 8000; i++) {
2281                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2282                                         break;
2283                                 udelay(20);
2284                         }
2285                         if (i == 8000) {
2286                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2287                                 return -ENODEV;
2288                         }
2289                 }
2290                 tp->nvram_lock_cnt++;
2291         }
2292         return 0;
2293 }
2294
2295 /* tp->lock is held. */
2296 static void tg3_nvram_unlock(struct tg3 *tp)
2297 {
2298         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2299                 if (tp->nvram_lock_cnt > 0)
2300                         tp->nvram_lock_cnt--;
2301                 if (tp->nvram_lock_cnt == 0)
2302                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2303         }
2304 }
2305
2306 /* tp->lock is held. */
2307 static void tg3_enable_nvram_access(struct tg3 *tp)
2308 {
2309         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2310             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2311                 u32 nvaccess = tr32(NVRAM_ACCESS);
2312
2313                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2314         }
2315 }
2316
2317 /* tp->lock is held. */
2318 static void tg3_disable_nvram_access(struct tg3 *tp)
2319 {
2320         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2321             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2322                 u32 nvaccess = tr32(NVRAM_ACCESS);
2323
2324                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2325         }
2326 }
2327
2328 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2329                                         u32 offset, u32 *val)
2330 {
2331         u32 tmp;
2332         int i;
2333
2334         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2335                 return -EINVAL;
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 1000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 msleep(1);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE))
2355                 return -EBUSY;
2356
2357         tmp = tr32(GRC_EEPROM_DATA);
2358
2359         /*
2360          * The data will always be opposite the native endian
2361          * format.  Perform a blind byteswap to compensate.
2362          */
2363         *val = swab32(tmp);
2364
2365         return 0;
2366 }
2367
2368 #define NVRAM_CMD_TIMEOUT 10000
2369
2370 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2371 {
2372         int i;
2373
2374         tw32(NVRAM_CMD, nvram_cmd);
2375         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2376                 udelay(10);
2377                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2378                         udelay(10);
2379                         break;
2380                 }
2381         }
2382
2383         if (i == NVRAM_CMD_TIMEOUT)
2384                 return -EBUSY;
2385
2386         return 0;
2387 }
2388
2389 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2390 {
2391         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2392             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2393             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2394            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2395             (tp->nvram_jedecnum == JEDEC_ATMEL))
2396
2397                 addr = ((addr / tp->nvram_pagesize) <<
2398                         ATMEL_AT45DB0X1B_PAGE_POS) +
2399                        (addr % tp->nvram_pagesize);
2400
2401         return addr;
2402 }
2403
2404 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2405 {
2406         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2407             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2408             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2409            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2410             (tp->nvram_jedecnum == JEDEC_ATMEL))
2411
2412                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2413                         tp->nvram_pagesize) +
2414                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2415
2416         return addr;
2417 }
2418
2419 /* NOTE: Data read in from NVRAM is byteswapped according to
2420  * the byteswapping settings for all other register accesses.
2421  * tg3 devices are BE devices, so on a BE machine, the data
2422  * returned will be exactly as it is seen in NVRAM.  On a LE
2423  * machine, the 32-bit value will be byteswapped.
2424  */
2425 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2426 {
2427         int ret;
2428
2429         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2430                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2431
2432         offset = tg3_nvram_phys_addr(tp, offset);
2433
2434         if (offset > NVRAM_ADDR_MSK)
2435                 return -EINVAL;
2436
2437         ret = tg3_nvram_lock(tp);
2438         if (ret)
2439                 return ret;
2440
2441         tg3_enable_nvram_access(tp);
2442
2443         tw32(NVRAM_ADDR, offset);
2444         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2445                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2446
2447         if (ret == 0)
2448                 *val = tr32(NVRAM_RDDATA);
2449
2450         tg3_disable_nvram_access(tp);
2451
2452         tg3_nvram_unlock(tp);
2453
2454         return ret;
2455 }
2456
2457 /* Ensures NVRAM data is in bytestream format. */
2458 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2459 {
2460         u32 v;
2461         int res = tg3_nvram_read(tp, offset, &v);
2462         if (!res)
2463                 *val = cpu_to_be32(v);
2464         return res;
2465 }
2466
2467 /* tp->lock is held. */
2468 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2469 {
2470         u32 addr_high, addr_low;
2471         int i;
2472
2473         addr_high = ((tp->dev->dev_addr[0] << 8) |
2474                      tp->dev->dev_addr[1]);
2475         addr_low = ((tp->dev->dev_addr[2] << 24) |
2476                     (tp->dev->dev_addr[3] << 16) |
2477                     (tp->dev->dev_addr[4] <<  8) |
2478                     (tp->dev->dev_addr[5] <<  0));
2479         for (i = 0; i < 4; i++) {
2480                 if (i == 1 && skip_mac_1)
2481                         continue;
2482                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2483                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2484         }
2485
2486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2488                 for (i = 0; i < 12; i++) {
2489                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2490                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2491                 }
2492         }
2493
2494         addr_high = (tp->dev->dev_addr[0] +
2495                      tp->dev->dev_addr[1] +
2496                      tp->dev->dev_addr[2] +
2497                      tp->dev->dev_addr[3] +
2498                      tp->dev->dev_addr[4] +
2499                      tp->dev->dev_addr[5]) &
2500                 TX_BACKOFF_SEED_MASK;
2501         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2502 }
2503
2504 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2505 {
2506         u32 misc_host_ctrl;
2507         bool device_should_wake, do_low_power;
2508
2509         /* Make sure register accesses (indirect or otherwise)
2510          * will function correctly.
2511          */
2512         pci_write_config_dword(tp->pdev,
2513                                TG3PCI_MISC_HOST_CTRL,
2514                                tp->misc_host_ctrl);
2515
2516         switch (state) {
2517         case PCI_D0:
2518                 pci_enable_wake(tp->pdev, state, false);
2519                 pci_set_power_state(tp->pdev, PCI_D0);
2520
2521                 /* Switch out of Vaux if it is a NIC */
2522                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2523                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2524
2525                 return 0;
2526
2527         case PCI_D1:
2528         case PCI_D2:
2529         case PCI_D3hot:
2530                 break;
2531
2532         default:
2533                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2534                            state);
2535                 return -EINVAL;
2536         }
2537
2538         /* Restore the CLKREQ setting. */
2539         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2540                 u16 lnkctl;
2541
2542                 pci_read_config_word(tp->pdev,
2543                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                      &lnkctl);
2545                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2546                 pci_write_config_word(tp->pdev,
2547                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2548                                       lnkctl);
2549         }
2550
2551         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2552         tw32(TG3PCI_MISC_HOST_CTRL,
2553              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2554
2555         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2556                              device_may_wakeup(&tp->pdev->dev) &&
2557                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2558
2559         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2560                 do_low_power = false;
2561                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2562                     !tp->link_config.phy_is_low_power) {
2563                         struct phy_device *phydev;
2564                         u32 phyid, advertising;
2565
2566                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2567
2568                         tp->link_config.phy_is_low_power = 1;
2569
2570                         tp->link_config.orig_speed = phydev->speed;
2571                         tp->link_config.orig_duplex = phydev->duplex;
2572                         tp->link_config.orig_autoneg = phydev->autoneg;
2573                         tp->link_config.orig_advertising = phydev->advertising;
2574
2575                         advertising = ADVERTISED_TP |
2576                                       ADVERTISED_Pause |
2577                                       ADVERTISED_Autoneg |
2578                                       ADVERTISED_10baseT_Half;
2579
2580                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2581                             device_should_wake) {
2582                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2583                                         advertising |=
2584                                                 ADVERTISED_100baseT_Half |
2585                                                 ADVERTISED_100baseT_Full |
2586                                                 ADVERTISED_10baseT_Full;
2587                                 else
2588                                         advertising |= ADVERTISED_10baseT_Full;
2589                         }
2590
2591                         phydev->advertising = advertising;
2592
2593                         phy_start_aneg(phydev);
2594
2595                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2596                         if (phyid != PHY_ID_BCMAC131) {
2597                                 phyid &= PHY_BCM_OUI_MASK;
2598                                 if (phyid == PHY_BCM_OUI_1 ||
2599                                     phyid == PHY_BCM_OUI_2 ||
2600                                     phyid == PHY_BCM_OUI_3)
2601                                         do_low_power = true;
2602                         }
2603                 }
2604         } else {
2605                 do_low_power = true;
2606
2607                 if (tp->link_config.phy_is_low_power == 0) {
2608                         tp->link_config.phy_is_low_power = 1;
2609                         tp->link_config.orig_speed = tp->link_config.speed;
2610                         tp->link_config.orig_duplex = tp->link_config.duplex;
2611                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2612                 }
2613
2614                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2615                         tp->link_config.speed = SPEED_10;
2616                         tp->link_config.duplex = DUPLEX_HALF;
2617                         tp->link_config.autoneg = AUTONEG_ENABLE;
2618                         tg3_setup_phy(tp, 0);
2619                 }
2620         }
2621
2622         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2623                 u32 val;
2624
2625                 val = tr32(GRC_VCPU_EXT_CTRL);
2626                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2627         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2628                 int i;
2629                 u32 val;
2630
2631                 for (i = 0; i < 200; i++) {
2632                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2633                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2634                                 break;
2635                         msleep(1);
2636                 }
2637         }
2638         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2639                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2640                                                      WOL_DRV_STATE_SHUTDOWN |
2641                                                      WOL_DRV_WOL |
2642                                                      WOL_SET_MAGIC_PKT);
2643
2644         if (device_should_wake) {
2645                 u32 mac_mode;
2646
2647                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2648                         if (do_low_power) {
2649                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2650                                 udelay(40);
2651                         }
2652
2653                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2654                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2655                         else
2656                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2657
2658                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2659                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2660                             ASIC_REV_5700) {
2661                                 u32 speed = (tp->tg3_flags &
2662                                              TG3_FLAG_WOL_SPEED_100MB) ?
2663                                              SPEED_100 : SPEED_10;
2664                                 if (tg3_5700_link_polarity(tp, speed))
2665                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2666                                 else
2667                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2668                         }
2669                 } else {
2670                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2671                 }
2672
2673                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2674                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2675
2676                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2677                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2678                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2679                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2680                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2681                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2682
2683                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2684                         mac_mode |= tp->mac_mode &
2685                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2686                         if (mac_mode & MAC_MODE_APE_TX_EN)
2687                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2688                 }
2689
2690                 tw32_f(MAC_MODE, mac_mode);
2691                 udelay(100);
2692
2693                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2694                 udelay(10);
2695         }
2696
2697         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2698             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2699              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2700                 u32 base_val;
2701
2702                 base_val = tp->pci_clock_ctrl;
2703                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2704                              CLOCK_CTRL_TXCLK_DISABLE);
2705
2706                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2707                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2708         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2709                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2710                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2711                 /* do nothing */
2712         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2713                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2714                 u32 newbits1, newbits2;
2715
2716                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2717                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2718                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2719                                     CLOCK_CTRL_TXCLK_DISABLE |
2720                                     CLOCK_CTRL_ALTCLK);
2721                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2722                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2723                         newbits1 = CLOCK_CTRL_625_CORE;
2724                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2725                 } else {
2726                         newbits1 = CLOCK_CTRL_ALTCLK;
2727                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2728                 }
2729
2730                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2731                             40);
2732
2733                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2734                             40);
2735
2736                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2737                         u32 newbits3;
2738
2739                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2740                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2741                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2742                                             CLOCK_CTRL_TXCLK_DISABLE |
2743                                             CLOCK_CTRL_44MHZ_CORE);
2744                         } else {
2745                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2746                         }
2747
2748                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2749                                     tp->pci_clock_ctrl | newbits3, 40);
2750                 }
2751         }
2752
2753         if (!(device_should_wake) &&
2754             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2755                 tg3_power_down_phy(tp, do_low_power);
2756
2757         tg3_frob_aux_power(tp);
2758
2759         /* Workaround for unstable PLL clock */
2760         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2761             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2762                 u32 val = tr32(0x7d00);
2763
2764                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2765                 tw32(0x7d00, val);
2766                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2767                         int err;
2768
2769                         err = tg3_nvram_lock(tp);
2770                         tg3_halt_cpu(tp, RX_CPU_BASE);
2771                         if (!err)
2772                                 tg3_nvram_unlock(tp);
2773                 }
2774         }
2775
2776         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2777
2778         if (device_should_wake)
2779                 pci_enable_wake(tp->pdev, state, true);
2780
2781         /* Finally, set the new power state. */
2782         pci_set_power_state(tp->pdev, state);
2783
2784         return 0;
2785 }
2786
2787 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2788 {
2789         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2790         case MII_TG3_AUX_STAT_10HALF:
2791                 *speed = SPEED_10;
2792                 *duplex = DUPLEX_HALF;
2793                 break;
2794
2795         case MII_TG3_AUX_STAT_10FULL:
2796                 *speed = SPEED_10;
2797                 *duplex = DUPLEX_FULL;
2798                 break;
2799
2800         case MII_TG3_AUX_STAT_100HALF:
2801                 *speed = SPEED_100;
2802                 *duplex = DUPLEX_HALF;
2803                 break;
2804
2805         case MII_TG3_AUX_STAT_100FULL:
2806                 *speed = SPEED_100;
2807                 *duplex = DUPLEX_FULL;
2808                 break;
2809
2810         case MII_TG3_AUX_STAT_1000HALF:
2811                 *speed = SPEED_1000;
2812                 *duplex = DUPLEX_HALF;
2813                 break;
2814
2815         case MII_TG3_AUX_STAT_1000FULL:
2816                 *speed = SPEED_1000;
2817                 *duplex = DUPLEX_FULL;
2818                 break;
2819
2820         default:
2821                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2822                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2823                                  SPEED_10;
2824                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2825                                   DUPLEX_HALF;
2826                         break;
2827                 }
2828                 *speed = SPEED_INVALID;
2829                 *duplex = DUPLEX_INVALID;
2830                 break;
2831         }
2832 }
2833
2834 static void tg3_phy_copper_begin(struct tg3 *tp)
2835 {
2836         u32 new_adv;
2837         int i;
2838
2839         if (tp->link_config.phy_is_low_power) {
2840                 /* Entering low power mode.  Disable gigabit and
2841                  * 100baseT advertisements.
2842                  */
2843                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2844
2845                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2846                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2847                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2848                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2849
2850                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2851         } else if (tp->link_config.speed == SPEED_INVALID) {
2852                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2853                         tp->link_config.advertising &=
2854                                 ~(ADVERTISED_1000baseT_Half |
2855                                   ADVERTISED_1000baseT_Full);
2856
2857                 new_adv = ADVERTISE_CSMA;
2858                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2859                         new_adv |= ADVERTISE_10HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2861                         new_adv |= ADVERTISE_10FULL;
2862                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2863                         new_adv |= ADVERTISE_100HALF;
2864                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2865                         new_adv |= ADVERTISE_100FULL;
2866
2867                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2868
2869                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2870
2871                 if (tp->link_config.advertising &
2872                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2873                         new_adv = 0;
2874                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2875                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2876                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2877                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2878                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2879                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2880                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2881                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2882                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2883                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2884                 } else {
2885                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2886                 }
2887         } else {
2888                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2889                 new_adv |= ADVERTISE_CSMA;
2890
2891                 /* Asking for a specific link mode. */
2892                 if (tp->link_config.speed == SPEED_1000) {
2893                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2894
2895                         if (tp->link_config.duplex == DUPLEX_FULL)
2896                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2897                         else
2898                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2899                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2900                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2901                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2902                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2903                 } else {
2904                         if (tp->link_config.speed == SPEED_100) {
2905                                 if (tp->link_config.duplex == DUPLEX_FULL)
2906                                         new_adv |= ADVERTISE_100FULL;
2907                                 else
2908                                         new_adv |= ADVERTISE_100HALF;
2909                         } else {
2910                                 if (tp->link_config.duplex == DUPLEX_FULL)
2911                                         new_adv |= ADVERTISE_10FULL;
2912                                 else
2913                                         new_adv |= ADVERTISE_10HALF;
2914                         }
2915                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2916
2917                         new_adv = 0;
2918                 }
2919
2920                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2921         }
2922
2923         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2924             tp->link_config.speed != SPEED_INVALID) {
2925                 u32 bmcr, orig_bmcr;
2926
2927                 tp->link_config.active_speed = tp->link_config.speed;
2928                 tp->link_config.active_duplex = tp->link_config.duplex;
2929
2930                 bmcr = 0;
2931                 switch (tp->link_config.speed) {
2932                 default:
2933                 case SPEED_10:
2934                         break;
2935
2936                 case SPEED_100:
2937                         bmcr |= BMCR_SPEED100;
2938                         break;
2939
2940                 case SPEED_1000:
2941                         bmcr |= TG3_BMCR_SPEED1000;
2942                         break;
2943                 }
2944
2945                 if (tp->link_config.duplex == DUPLEX_FULL)
2946                         bmcr |= BMCR_FULLDPLX;
2947
2948                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2949                     (bmcr != orig_bmcr)) {
2950                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2951                         for (i = 0; i < 1500; i++) {
2952                                 u32 tmp;
2953
2954                                 udelay(10);
2955                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2956                                     tg3_readphy(tp, MII_BMSR, &tmp))
2957                                         continue;
2958                                 if (!(tmp & BMSR_LSTATUS)) {
2959                                         udelay(40);
2960                                         break;
2961                                 }
2962                         }
2963                         tg3_writephy(tp, MII_BMCR, bmcr);
2964                         udelay(40);
2965                 }
2966         } else {
2967                 tg3_writephy(tp, MII_BMCR,
2968                              BMCR_ANENABLE | BMCR_ANRESTART);
2969         }
2970 }
2971
2972 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2973 {
2974         int err;
2975
2976         /* Turn off tap power management. */
2977         /* Set Extended packet length bit */
2978         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2979
2980         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2981         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2982
2983         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2984         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2985
2986         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2987         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2988
2989         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2990         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2991
2992         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2993         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2994
2995         udelay(40);
2996
2997         return err;
2998 }
2999
3000 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3001 {
3002         u32 adv_reg, all_mask = 0;
3003
3004         if (mask & ADVERTISED_10baseT_Half)
3005                 all_mask |= ADVERTISE_10HALF;
3006         if (mask & ADVERTISED_10baseT_Full)
3007                 all_mask |= ADVERTISE_10FULL;
3008         if (mask & ADVERTISED_100baseT_Half)
3009                 all_mask |= ADVERTISE_100HALF;
3010         if (mask & ADVERTISED_100baseT_Full)
3011                 all_mask |= ADVERTISE_100FULL;
3012
3013         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3014                 return 0;
3015
3016         if ((adv_reg & all_mask) != all_mask)
3017                 return 0;
3018         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3019                 u32 tg3_ctrl;
3020
3021                 all_mask = 0;
3022                 if (mask & ADVERTISED_1000baseT_Half)
3023                         all_mask |= ADVERTISE_1000HALF;
3024                 if (mask & ADVERTISED_1000baseT_Full)
3025                         all_mask |= ADVERTISE_1000FULL;
3026
3027                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3028                         return 0;
3029
3030                 if ((tg3_ctrl & all_mask) != all_mask)
3031                         return 0;
3032         }
3033         return 1;
3034 }
3035
3036 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3037 {
3038         u32 curadv, reqadv;
3039
3040         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3041                 return 1;
3042
3043         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3044         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3045
3046         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3047                 if (curadv != reqadv)
3048                         return 0;
3049
3050                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3051                         tg3_readphy(tp, MII_LPA, rmtadv);
3052         } else {
3053                 /* Reprogram the advertisement register, even if it
3054                  * does not affect the current link.  If the link
3055                  * gets renegotiated in the future, we can save an
3056                  * additional renegotiation cycle by advertising
3057                  * it correctly in the first place.
3058                  */
3059                 if (curadv != reqadv) {
3060                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3061                                      ADVERTISE_PAUSE_ASYM);
3062                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3063                 }
3064         }
3065
3066         return 1;
3067 }
3068
3069 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3070 {
3071         int current_link_up;
3072         u32 bmsr, dummy;
3073         u32 lcl_adv, rmt_adv;
3074         u16 current_speed;
3075         u8 current_duplex;
3076         int i, err;
3077
3078         tw32(MAC_EVENT, 0);
3079
3080         tw32_f(MAC_STATUS,
3081              (MAC_STATUS_SYNC_CHANGED |
3082               MAC_STATUS_CFG_CHANGED |
3083               MAC_STATUS_MI_COMPLETION |
3084               MAC_STATUS_LNKSTATE_CHANGED));
3085         udelay(40);
3086
3087         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3088                 tw32_f(MAC_MI_MODE,
3089                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3090                 udelay(80);
3091         }
3092
3093         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3094
3095         /* Some third-party PHYs need to be reset on link going
3096          * down.
3097          */
3098         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3099              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3100              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3101             netif_carrier_ok(tp->dev)) {
3102                 tg3_readphy(tp, MII_BMSR, &bmsr);
3103                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3104                     !(bmsr & BMSR_LSTATUS))
3105                         force_reset = 1;
3106         }
3107         if (force_reset)
3108                 tg3_phy_reset(tp);
3109
3110         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3111                 tg3_readphy(tp, MII_BMSR, &bmsr);
3112                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3113                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3114                         bmsr = 0;
3115
3116                 if (!(bmsr & BMSR_LSTATUS)) {
3117                         err = tg3_init_5401phy_dsp(tp);
3118                         if (err)
3119                                 return err;
3120
3121                         tg3_readphy(tp, MII_BMSR, &bmsr);
3122                         for (i = 0; i < 1000; i++) {
3123                                 udelay(10);
3124                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3125                                     (bmsr & BMSR_LSTATUS)) {
3126                                         udelay(40);
3127                                         break;
3128                                 }
3129                         }
3130
3131                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3132                             TG3_PHY_REV_BCM5401_B0 &&
3133                             !(bmsr & BMSR_LSTATUS) &&
3134                             tp->link_config.active_speed == SPEED_1000) {
3135                                 err = tg3_phy_reset(tp);
3136                                 if (!err)
3137                                         err = tg3_init_5401phy_dsp(tp);
3138                                 if (err)
3139                                         return err;
3140                         }
3141                 }
3142         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3143                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3144                 /* 5701 {A0,B0} CRC bug workaround */
3145                 tg3_writephy(tp, 0x15, 0x0a75);
3146                 tg3_writephy(tp, 0x1c, 0x8c68);
3147                 tg3_writephy(tp, 0x1c, 0x8d68);
3148                 tg3_writephy(tp, 0x1c, 0x8c68);
3149         }
3150
3151         /* Clear pending interrupts... */
3152         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3153         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3154
3155         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3156                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3157         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3158                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3159
3160         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3161             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3162                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3163                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3164                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3165                 else
3166                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3167         }
3168
3169         current_link_up = 0;
3170         current_speed = SPEED_INVALID;
3171         current_duplex = DUPLEX_INVALID;
3172
3173         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3174                 u32 val;
3175
3176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3177                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3178                 if (!(val & (1 << 10))) {
3179                         val |= (1 << 10);
3180                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3181                         goto relink;
3182                 }
3183         }
3184
3185         bmsr = 0;
3186         for (i = 0; i < 100; i++) {
3187                 tg3_readphy(tp, MII_BMSR, &bmsr);
3188                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3189                     (bmsr & BMSR_LSTATUS))
3190                         break;
3191                 udelay(40);
3192         }
3193
3194         if (bmsr & BMSR_LSTATUS) {
3195                 u32 aux_stat, bmcr;
3196
3197                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3198                 for (i = 0; i < 2000; i++) {
3199                         udelay(10);
3200                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3201                             aux_stat)
3202                                 break;
3203                 }
3204
3205                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3206                                              &current_speed,
3207                                              &current_duplex);
3208
3209                 bmcr = 0;
3210                 for (i = 0; i < 200; i++) {
3211                         tg3_readphy(tp, MII_BMCR, &bmcr);
3212                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3213                                 continue;
3214                         if (bmcr && bmcr != 0x7fff)
3215                                 break;
3216                         udelay(10);
3217                 }
3218
3219                 lcl_adv = 0;
3220                 rmt_adv = 0;
3221
3222                 tp->link_config.active_speed = current_speed;
3223                 tp->link_config.active_duplex = current_duplex;
3224
3225                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3226                         if ((bmcr & BMCR_ANENABLE) &&
3227                             tg3_copper_is_advertising_all(tp,
3228                                                 tp->link_config.advertising)) {
3229                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3230                                                                   &rmt_adv))
3231                                         current_link_up = 1;
3232                         }
3233                 } else {
3234                         if (!(bmcr & BMCR_ANENABLE) &&
3235                             tp->link_config.speed == current_speed &&
3236                             tp->link_config.duplex == current_duplex &&
3237                             tp->link_config.flowctrl ==
3238                             tp->link_config.active_flowctrl) {
3239                                 current_link_up = 1;
3240                         }
3241                 }
3242
3243                 if (current_link_up == 1 &&
3244                     tp->link_config.active_duplex == DUPLEX_FULL)
3245                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3246         }
3247
3248 relink:
3249         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3250                 u32 tmp;
3251
3252                 tg3_phy_copper_begin(tp);
3253
3254                 tg3_readphy(tp, MII_BMSR, &tmp);
3255                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3256                     (tmp & BMSR_LSTATUS))
3257                         current_link_up = 1;
3258         }
3259
3260         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3261         if (current_link_up == 1) {
3262                 if (tp->link_config.active_speed == SPEED_100 ||
3263                     tp->link_config.active_speed == SPEED_10)
3264                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3265                 else
3266                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3267         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3268                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3269         else
3270                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3271
3272         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3273         if (tp->link_config.active_duplex == DUPLEX_HALF)
3274                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3275
3276         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3277                 if (current_link_up == 1 &&
3278                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3279                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3280                 else
3281                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3282         }
3283
3284         /* ??? Without this setting Netgear GA302T PHY does not
3285          * ??? send/receive packets...
3286          */
3287         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3288             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3289                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3290                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3291                 udelay(80);
3292         }
3293
3294         tw32_f(MAC_MODE, tp->mac_mode);
3295         udelay(40);
3296
3297         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3298                 /* Polled via timer. */
3299                 tw32_f(MAC_EVENT, 0);
3300         } else {
3301                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3302         }
3303         udelay(40);
3304
3305         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3306             current_link_up == 1 &&
3307             tp->link_config.active_speed == SPEED_1000 &&
3308             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3309              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3310                 udelay(120);
3311                 tw32_f(MAC_STATUS,
3312                      (MAC_STATUS_SYNC_CHANGED |
3313                       MAC_STATUS_CFG_CHANGED));
3314                 udelay(40);
3315                 tg3_write_mem(tp,
3316                               NIC_SRAM_FIRMWARE_MBOX,
3317                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3318         }
3319
3320         /* Prevent send BD corruption. */
3321         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3322                 u16 oldlnkctl, newlnkctl;
3323
3324                 pci_read_config_word(tp->pdev,
3325                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3326                                      &oldlnkctl);
3327                 if (tp->link_config.active_speed == SPEED_100 ||
3328                     tp->link_config.active_speed == SPEED_10)
3329                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3330                 else
3331                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3332                 if (newlnkctl != oldlnkctl)
3333                         pci_write_config_word(tp->pdev,
3334                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3335                                               newlnkctl);
3336         }
3337
3338         if (current_link_up != netif_carrier_ok(tp->dev)) {
3339                 if (current_link_up)
3340                         netif_carrier_on(tp->dev);
3341                 else
3342                         netif_carrier_off(tp->dev);
3343                 tg3_link_report(tp);
3344         }
3345
3346         return 0;
3347 }
3348
3349 struct tg3_fiber_aneginfo {
3350         int state;
3351 #define ANEG_STATE_UNKNOWN              0
3352 #define ANEG_STATE_AN_ENABLE            1
3353 #define ANEG_STATE_RESTART_INIT         2
3354 #define ANEG_STATE_RESTART              3
3355 #define ANEG_STATE_DISABLE_LINK_OK      4
3356 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3357 #define ANEG_STATE_ABILITY_DETECT       6
3358 #define ANEG_STATE_ACK_DETECT_INIT      7
3359 #define ANEG_STATE_ACK_DETECT           8
3360 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3361 #define ANEG_STATE_COMPLETE_ACK         10
3362 #define ANEG_STATE_IDLE_DETECT_INIT     11
3363 #define ANEG_STATE_IDLE_DETECT          12
3364 #define ANEG_STATE_LINK_OK              13
3365 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3366 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3367
3368         u32 flags;
3369 #define MR_AN_ENABLE            0x00000001
3370 #define MR_RESTART_AN           0x00000002
3371 #define MR_AN_COMPLETE          0x00000004
3372 #define MR_PAGE_RX              0x00000008
3373 #define MR_NP_LOADED            0x00000010
3374 #define MR_TOGGLE_TX            0x00000020
3375 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3376 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3377 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3378 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3379 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3380 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3381 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3382 #define MR_TOGGLE_RX            0x00002000
3383 #define MR_NP_RX                0x00004000
3384
3385 #define MR_LINK_OK              0x80000000
3386
3387         unsigned long link_time, cur_time;
3388
3389         u32 ability_match_cfg;
3390         int ability_match_count;
3391
3392         char ability_match, idle_match, ack_match;
3393
3394         u32 txconfig, rxconfig;
3395 #define ANEG_CFG_NP             0x00000080
3396 #define ANEG_CFG_ACK            0x00000040
3397 #define ANEG_CFG_RF2            0x00000020
3398 #define ANEG_CFG_RF1            0x00000010
3399 #define ANEG_CFG_PS2            0x00000001
3400 #define ANEG_CFG_PS1            0x00008000
3401 #define ANEG_CFG_HD             0x00004000
3402 #define ANEG_CFG_FD             0x00002000
3403 #define ANEG_CFG_INVAL          0x00001f06
3404
3405 };
3406 #define ANEG_OK         0
3407 #define ANEG_DONE       1
3408 #define ANEG_TIMER_ENAB 2
3409 #define ANEG_FAILED     -1
3410
3411 #define ANEG_STATE_SETTLE_TIME  10000
3412
3413 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3414                                    struct tg3_fiber_aneginfo *ap)
3415 {
3416         u16 flowctrl;
3417         unsigned long delta;
3418         u32 rx_cfg_reg;
3419         int ret;
3420
3421         if (ap->state == ANEG_STATE_UNKNOWN) {
3422                 ap->rxconfig = 0;
3423                 ap->link_time = 0;
3424                 ap->cur_time = 0;
3425                 ap->ability_match_cfg = 0;
3426                 ap->ability_match_count = 0;
3427                 ap->ability_match = 0;
3428                 ap->idle_match = 0;
3429                 ap->ack_match = 0;
3430         }
3431         ap->cur_time++;
3432
3433         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3434                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3435
3436                 if (rx_cfg_reg != ap->ability_match_cfg) {
3437                         ap->ability_match_cfg = rx_cfg_reg;
3438                         ap->ability_match = 0;
3439                         ap->ability_match_count = 0;
3440                 } else {
3441                         if (++ap->ability_match_count > 1) {
3442                                 ap->ability_match = 1;
3443                                 ap->ability_match_cfg = rx_cfg_reg;
3444                         }
3445                 }
3446                 if (rx_cfg_reg & ANEG_CFG_ACK)
3447                         ap->ack_match = 1;
3448                 else
3449                         ap->ack_match = 0;
3450
3451                 ap->idle_match = 0;
3452         } else {
3453                 ap->idle_match = 1;
3454                 ap->ability_match_cfg = 0;
3455                 ap->ability_match_count = 0;
3456                 ap->ability_match = 0;
3457                 ap->ack_match = 0;
3458
3459                 rx_cfg_reg = 0;
3460         }
3461
3462         ap->rxconfig = rx_cfg_reg;
3463         ret = ANEG_OK;
3464
3465         switch (ap->state) {
3466         case ANEG_STATE_UNKNOWN:
3467                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3468                         ap->state = ANEG_STATE_AN_ENABLE;
3469
3470                 /* fallthru */
3471         case ANEG_STATE_AN_ENABLE:
3472                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3473                 if (ap->flags & MR_AN_ENABLE) {
3474                         ap->link_time = 0;
3475                         ap->cur_time = 0;
3476                         ap->ability_match_cfg = 0;
3477                         ap->ability_match_count = 0;
3478                         ap->ability_match = 0;
3479                         ap->idle_match = 0;
3480                         ap->ack_match = 0;
3481
3482                         ap->state = ANEG_STATE_RESTART_INIT;
3483                 } else {
3484                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3485                 }
3486                 break;
3487
3488         case ANEG_STATE_RESTART_INIT:
3489                 ap->link_time = ap->cur_time;
3490                 ap->flags &= ~(MR_NP_LOADED);
3491                 ap->txconfig = 0;
3492                 tw32(MAC_TX_AUTO_NEG, 0);
3493                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3494                 tw32_f(MAC_MODE, tp->mac_mode);
3495                 udelay(40);
3496
3497                 ret = ANEG_TIMER_ENAB;
3498                 ap->state = ANEG_STATE_RESTART;
3499
3500                 /* fallthru */
3501         case ANEG_STATE_RESTART:
3502                 delta = ap->cur_time - ap->link_time;
3503                 if (delta > ANEG_STATE_SETTLE_TIME)
3504                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3505                 else
3506                         ret = ANEG_TIMER_ENAB;
3507                 break;
3508
3509         case ANEG_STATE_DISABLE_LINK_OK:
3510                 ret = ANEG_DONE;
3511                 break;
3512
3513         case ANEG_STATE_ABILITY_DETECT_INIT:
3514                 ap->flags &= ~(MR_TOGGLE_TX);
3515                 ap->txconfig = ANEG_CFG_FD;
3516                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3517                 if (flowctrl & ADVERTISE_1000XPAUSE)
3518                         ap->txconfig |= ANEG_CFG_PS1;
3519                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3520                         ap->txconfig |= ANEG_CFG_PS2;
3521                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3522                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3523                 tw32_f(MAC_MODE, tp->mac_mode);
3524                 udelay(40);
3525
3526                 ap->state = ANEG_STATE_ABILITY_DETECT;
3527                 break;
3528
3529         case ANEG_STATE_ABILITY_DETECT:
3530                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3531                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3532                 break;
3533
3534         case ANEG_STATE_ACK_DETECT_INIT:
3535                 ap->txconfig |= ANEG_CFG_ACK;
3536                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3537                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3538                 tw32_f(MAC_MODE, tp->mac_mode);
3539                 udelay(40);
3540
3541                 ap->state = ANEG_STATE_ACK_DETECT;
3542
3543                 /* fallthru */
3544         case ANEG_STATE_ACK_DETECT:
3545                 if (ap->ack_match != 0) {
3546                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3547                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3548                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3549                         } else {
3550                                 ap->state = ANEG_STATE_AN_ENABLE;
3551                         }
3552                 } else if (ap->ability_match != 0 &&
3553                            ap->rxconfig == 0) {
3554                         ap->state = ANEG_STATE_AN_ENABLE;
3555                 }
3556                 break;
3557
3558         case ANEG_STATE_COMPLETE_ACK_INIT:
3559                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3560                         ret = ANEG_FAILED;
3561                         break;
3562                 }
3563                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3564                                MR_LP_ADV_HALF_DUPLEX |
3565                                MR_LP_ADV_SYM_PAUSE |
3566                                MR_LP_ADV_ASYM_PAUSE |
3567                                MR_LP_ADV_REMOTE_FAULT1 |
3568                                MR_LP_ADV_REMOTE_FAULT2 |
3569                                MR_LP_ADV_NEXT_PAGE |
3570                                MR_TOGGLE_RX |
3571                                MR_NP_RX);
3572                 if (ap->rxconfig & ANEG_CFG_FD)
3573                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3574                 if (ap->rxconfig & ANEG_CFG_HD)
3575                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3576                 if (ap->rxconfig & ANEG_CFG_PS1)
3577                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3578                 if (ap->rxconfig & ANEG_CFG_PS2)
3579                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3580                 if (ap->rxconfig & ANEG_CFG_RF1)
3581                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3582                 if (ap->rxconfig & ANEG_CFG_RF2)
3583                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3584                 if (ap->rxconfig & ANEG_CFG_NP)
3585                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3586
3587                 ap->link_time = ap->cur_time;
3588
3589                 ap->flags ^= (MR_TOGGLE_TX);
3590                 if (ap->rxconfig & 0x0008)
3591                         ap->flags |= MR_TOGGLE_RX;
3592                 if (ap->rxconfig & ANEG_CFG_NP)
3593                         ap->flags |= MR_NP_RX;
3594                 ap->flags |= MR_PAGE_RX;
3595
3596                 ap->state = ANEG_STATE_COMPLETE_ACK;
3597                 ret = ANEG_TIMER_ENAB;
3598                 break;
3599
3600         case ANEG_STATE_COMPLETE_ACK:
3601                 if (ap->ability_match != 0 &&
3602                     ap->rxconfig == 0) {
3603                         ap->state = ANEG_STATE_AN_ENABLE;
3604                         break;
3605                 }
3606                 delta = ap->cur_time - ap->link_time;
3607                 if (delta > ANEG_STATE_SETTLE_TIME) {
3608                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3609                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3610                         } else {
3611                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3612                                     !(ap->flags & MR_NP_RX)) {
3613                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3614                                 } else {
3615                                         ret = ANEG_FAILED;
3616                                 }
3617                         }
3618                 }
3619                 break;
3620
3621         case ANEG_STATE_IDLE_DETECT_INIT:
3622                 ap->link_time = ap->cur_time;
3623                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3624                 tw32_f(MAC_MODE, tp->mac_mode);
3625                 udelay(40);
3626
3627                 ap->state = ANEG_STATE_IDLE_DETECT;
3628                 ret = ANEG_TIMER_ENAB;
3629                 break;
3630
3631         case ANEG_STATE_IDLE_DETECT:
3632                 if (ap->ability_match != 0 &&
3633                     ap->rxconfig == 0) {
3634                         ap->state = ANEG_STATE_AN_ENABLE;
3635                         break;
3636                 }
3637                 delta = ap->cur_time - ap->link_time;
3638                 if (delta > ANEG_STATE_SETTLE_TIME) {
3639                         /* XXX another gem from the Broadcom driver :( */
3640                         ap->state = ANEG_STATE_LINK_OK;
3641                 }
3642                 break;
3643
3644         case ANEG_STATE_LINK_OK:
3645                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3646                 ret = ANEG_DONE;
3647                 break;
3648
3649         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3650                 /* ??? unimplemented */
3651                 break;
3652
3653         case ANEG_STATE_NEXT_PAGE_WAIT:
3654                 /* ??? unimplemented */
3655                 break;
3656
3657         default:
3658                 ret = ANEG_FAILED;
3659                 break;
3660         }
3661
3662         return ret;
3663 }
3664
3665 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3666 {
3667         int res = 0;
3668         struct tg3_fiber_aneginfo aninfo;
3669         int status = ANEG_FAILED;
3670         unsigned int tick;
3671         u32 tmp;
3672
3673         tw32_f(MAC_TX_AUTO_NEG, 0);
3674
3675         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3676         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3677         udelay(40);
3678
3679         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3680         udelay(40);
3681
3682         memset(&aninfo, 0, sizeof(aninfo));
3683         aninfo.flags |= MR_AN_ENABLE;
3684         aninfo.state = ANEG_STATE_UNKNOWN;
3685         aninfo.cur_time = 0;
3686         tick = 0;
3687         while (++tick < 195000) {
3688                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3689                 if (status == ANEG_DONE || status == ANEG_FAILED)
3690                         break;
3691
3692                 udelay(1);
3693         }
3694
3695         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3696         tw32_f(MAC_MODE, tp->mac_mode);
3697         udelay(40);
3698
3699         *txflags = aninfo.txconfig;
3700         *rxflags = aninfo.flags;
3701
3702         if (status == ANEG_DONE &&
3703             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3704                              MR_LP_ADV_FULL_DUPLEX)))
3705                 res = 1;
3706
3707         return res;
3708 }
3709
3710 static void tg3_init_bcm8002(struct tg3 *tp)
3711 {
3712         u32 mac_status = tr32(MAC_STATUS);
3713         int i;
3714
3715         /* Reset when initting first time or we have a link. */
3716         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3717             !(mac_status & MAC_STATUS_PCS_SYNCED))
3718                 return;
3719
3720         /* Set PLL lock range. */
3721         tg3_writephy(tp, 0x16, 0x8007);
3722
3723         /* SW reset */
3724         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3725
3726         /* Wait for reset to complete. */
3727         /* XXX schedule_timeout() ... */
3728         for (i = 0; i < 500; i++)
3729                 udelay(10);
3730
3731         /* Config mode; select PMA/Ch 1 regs. */
3732         tg3_writephy(tp, 0x10, 0x8411);
3733
3734         /* Enable auto-lock and comdet, select txclk for tx. */
3735         tg3_writephy(tp, 0x11, 0x0a10);
3736
3737         tg3_writephy(tp, 0x18, 0x00a0);
3738         tg3_writephy(tp, 0x16, 0x41ff);
3739
3740         /* Assert and deassert POR. */
3741         tg3_writephy(tp, 0x13, 0x0400);
3742         udelay(40);
3743         tg3_writephy(tp, 0x13, 0x0000);
3744
3745         tg3_writephy(tp, 0x11, 0x0a50);
3746         udelay(40);
3747         tg3_writephy(tp, 0x11, 0x0a10);
3748
3749         /* Wait for signal to stabilize */
3750         /* XXX schedule_timeout() ... */
3751         for (i = 0; i < 15000; i++)
3752                 udelay(10);
3753
3754         /* Deselect the channel register so we can read the PHYID
3755          * later.
3756          */
3757         tg3_writephy(tp, 0x10, 0x8011);
3758 }
3759
3760 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3761 {
3762         u16 flowctrl;
3763         u32 sg_dig_ctrl, sg_dig_status;
3764         u32 serdes_cfg, expected_sg_dig_ctrl;
3765         int workaround, port_a;
3766         int current_link_up;
3767
3768         serdes_cfg = 0;
3769         expected_sg_dig_ctrl = 0;
3770         workaround = 0;
3771         port_a = 1;
3772         current_link_up = 0;
3773
3774         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3775             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3776                 workaround = 1;
3777                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3778                         port_a = 0;
3779
3780                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3781                 /* preserve bits 20-23 for voltage regulator */
3782                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3783         }
3784
3785         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3786
3787         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3788                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3789                         if (workaround) {
3790                                 u32 val = serdes_cfg;
3791
3792                                 if (port_a)
3793                                         val |= 0xc010000;
3794                                 else
3795                                         val |= 0x4010000;
3796                                 tw32_f(MAC_SERDES_CFG, val);
3797                         }
3798
3799                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3800                 }
3801                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3802                         tg3_setup_flow_control(tp, 0, 0);
3803                         current_link_up = 1;
3804                 }
3805                 goto out;
3806         }
3807
3808         /* Want auto-negotiation.  */
3809         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3810
3811         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3812         if (flowctrl & ADVERTISE_1000XPAUSE)
3813                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3814         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3815                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3816
3817         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3818                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3819                     tp->serdes_counter &&
3820                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3821                                     MAC_STATUS_RCVD_CFG)) ==
3822                      MAC_STATUS_PCS_SYNCED)) {
3823                         tp->serdes_counter--;
3824                         current_link_up = 1;
3825                         goto out;
3826                 }
3827 restart_autoneg:
3828                 if (workaround)
3829                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3830                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3831                 udelay(5);
3832                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3833
3834                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3835                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3836         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3837                                  MAC_STATUS_SIGNAL_DET)) {
3838                 sg_dig_status = tr32(SG_DIG_STATUS);
3839                 mac_status = tr32(MAC_STATUS);
3840
3841                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3842                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3843                         u32 local_adv = 0, remote_adv = 0;
3844
3845                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3846                                 local_adv |= ADVERTISE_1000XPAUSE;
3847                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3848                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3849
3850                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3851                                 remote_adv |= LPA_1000XPAUSE;
3852                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3853                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3854
3855                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3856                         current_link_up = 1;
3857                         tp->serdes_counter = 0;
3858                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3859                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3860                         if (tp->serdes_counter)
3861                                 tp->serdes_counter--;
3862                         else {
3863                                 if (workaround) {
3864                                         u32 val = serdes_cfg;
3865
3866                                         if (port_a)
3867                                                 val |= 0xc010000;
3868                                         else
3869                                                 val |= 0x4010000;
3870
3871                                         tw32_f(MAC_SERDES_CFG, val);
3872                                 }
3873
3874                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                                 udelay(40);
3876
3877                                 /* Link parallel detection - link is up */
3878                                 /* only if we have PCS_SYNC and not */
3879                                 /* receiving config code words */
3880                                 mac_status = tr32(MAC_STATUS);
3881                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3882                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3883                                         tg3_setup_flow_control(tp, 0, 0);
3884                                         current_link_up = 1;
3885                                         tp->tg3_flags2 |=
3886                                                 TG3_FLG2_PARALLEL_DETECT;
3887                                         tp->serdes_counter =
3888                                                 SERDES_PARALLEL_DET_TIMEOUT;
3889                                 } else
3890                                         goto restart_autoneg;
3891                         }
3892                 }
3893         } else {
3894                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3895                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3896         }
3897
3898 out:
3899         return current_link_up;
3900 }
3901
3902 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3903 {
3904         int current_link_up = 0;
3905
3906         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3907                 goto out;
3908
3909         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3910                 u32 txflags, rxflags;
3911                 int i;
3912
3913                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3914                         u32 local_adv = 0, remote_adv = 0;
3915
3916                         if (txflags & ANEG_CFG_PS1)
3917                                 local_adv |= ADVERTISE_1000XPAUSE;
3918                         if (txflags & ANEG_CFG_PS2)
3919                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3920
3921                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3922                                 remote_adv |= LPA_1000XPAUSE;
3923                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3924                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3925
3926                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3927
3928                         current_link_up = 1;
3929                 }
3930                 for (i = 0; i < 30; i++) {
3931                         udelay(20);
3932                         tw32_f(MAC_STATUS,
3933                                (MAC_STATUS_SYNC_CHANGED |
3934                                 MAC_STATUS_CFG_CHANGED));
3935                         udelay(40);
3936                         if ((tr32(MAC_STATUS) &
3937                              (MAC_STATUS_SYNC_CHANGED |
3938                               MAC_STATUS_CFG_CHANGED)) == 0)
3939                                 break;
3940                 }
3941
3942                 mac_status = tr32(MAC_STATUS);
3943                 if (current_link_up == 0 &&
3944                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3945                     !(mac_status & MAC_STATUS_RCVD_CFG))
3946                         current_link_up = 1;
3947         } else {
3948                 tg3_setup_flow_control(tp, 0, 0);
3949
3950                 /* Forcing 1000FD link up. */
3951                 current_link_up = 1;
3952
3953                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3954                 udelay(40);
3955
3956                 tw32_f(MAC_MODE, tp->mac_mode);
3957                 udelay(40);
3958         }
3959
3960 out:
3961         return current_link_up;
3962 }
3963
3964 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3965 {
3966         u32 orig_pause_cfg;
3967         u16 orig_active_speed;
3968         u8 orig_active_duplex;
3969         u32 mac_status;
3970         int current_link_up;
3971         int i;
3972
3973         orig_pause_cfg = tp->link_config.active_flowctrl;
3974         orig_active_speed = tp->link_config.active_speed;
3975         orig_active_duplex = tp->link_config.active_duplex;
3976
3977         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3978             netif_carrier_ok(tp->dev) &&
3979             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3980                 mac_status = tr32(MAC_STATUS);
3981                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3982                                MAC_STATUS_SIGNAL_DET |
3983                                MAC_STATUS_CFG_CHANGED |
3984                                MAC_STATUS_RCVD_CFG);
3985                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3986                                    MAC_STATUS_SIGNAL_DET)) {
3987                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3988                                             MAC_STATUS_CFG_CHANGED));
3989                         return 0;
3990                 }
3991         }
3992
3993         tw32_f(MAC_TX_AUTO_NEG, 0);
3994
3995         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3996         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3997         tw32_f(MAC_MODE, tp->mac_mode);
3998         udelay(40);
3999
4000         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4001                 tg3_init_bcm8002(tp);
4002
4003         /* Enable link change event even when serdes polling.  */
4004         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4005         udelay(40);
4006
4007         current_link_up = 0;
4008         mac_status = tr32(MAC_STATUS);
4009
4010         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4011                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4012         else
4013                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4014
4015         tp->napi[0].hw_status->status =
4016                 (SD_STATUS_UPDATED |
4017                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4018
4019         for (i = 0; i < 100; i++) {
4020                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4021                                     MAC_STATUS_CFG_CHANGED));
4022                 udelay(5);
4023                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4024                                          MAC_STATUS_CFG_CHANGED |
4025                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4026                         break;
4027         }
4028
4029         mac_status = tr32(MAC_STATUS);
4030         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4031                 current_link_up = 0;
4032                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4033                     tp->serdes_counter == 0) {
4034                         tw32_f(MAC_MODE, (tp->mac_mode |
4035                                           MAC_MODE_SEND_CONFIGS));
4036                         udelay(1);
4037                         tw32_f(MAC_MODE, tp->mac_mode);
4038                 }
4039         }
4040
4041         if (current_link_up == 1) {
4042                 tp->link_config.active_speed = SPEED_1000;
4043                 tp->link_config.active_duplex = DUPLEX_FULL;
4044                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4045                                     LED_CTRL_LNKLED_OVERRIDE |
4046                                     LED_CTRL_1000MBPS_ON));
4047         } else {
4048                 tp->link_config.active_speed = SPEED_INVALID;
4049                 tp->link_config.active_duplex = DUPLEX_INVALID;
4050                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4051                                     LED_CTRL_LNKLED_OVERRIDE |
4052                                     LED_CTRL_TRAFFIC_OVERRIDE));
4053         }
4054
4055         if (current_link_up != netif_carrier_ok(tp->dev)) {
4056                 if (current_link_up)
4057                         netif_carrier_on(tp->dev);
4058                 else
4059                         netif_carrier_off(tp->dev);
4060                 tg3_link_report(tp);
4061         } else {
4062                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4063                 if (orig_pause_cfg != now_pause_cfg ||
4064                     orig_active_speed != tp->link_config.active_speed ||
4065                     orig_active_duplex != tp->link_config.active_duplex)
4066                         tg3_link_report(tp);
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4073 {
4074         int current_link_up, err = 0;
4075         u32 bmsr, bmcr;
4076         u16 current_speed;
4077         u8 current_duplex;
4078         u32 local_adv, remote_adv;
4079
4080         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4081         tw32_f(MAC_MODE, tp->mac_mode);
4082         udelay(40);
4083
4084         tw32(MAC_EVENT, 0);
4085
4086         tw32_f(MAC_STATUS,
4087              (MAC_STATUS_SYNC_CHANGED |
4088               MAC_STATUS_CFG_CHANGED |
4089               MAC_STATUS_MI_COMPLETION |
4090               MAC_STATUS_LNKSTATE_CHANGED));
4091         udelay(40);
4092
4093         if (force_reset)
4094                 tg3_phy_reset(tp);
4095
4096         current_link_up = 0;
4097         current_speed = SPEED_INVALID;
4098         current_duplex = DUPLEX_INVALID;
4099
4100         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4101         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4102         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4103                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4104                         bmsr |= BMSR_LSTATUS;
4105                 else
4106                         bmsr &= ~BMSR_LSTATUS;
4107         }
4108
4109         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4110
4111         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4112             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4113                 /* do nothing, just check for link up at the end */
4114         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4115                 u32 adv, new_adv;
4116
4117                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4118                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4119                                   ADVERTISE_1000XPAUSE |
4120                                   ADVERTISE_1000XPSE_ASYM |
4121                                   ADVERTISE_SLCT);
4122
4123                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4124
4125                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4126                         new_adv |= ADVERTISE_1000XHALF;
4127                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4128                         new_adv |= ADVERTISE_1000XFULL;
4129
4130                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4131                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4132                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4133                         tg3_writephy(tp, MII_BMCR, bmcr);
4134
4135                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4136                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4137                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4138
4139                         return err;
4140                 }
4141         } else {
4142                 u32 new_bmcr;
4143
4144                 bmcr &= ~BMCR_SPEED1000;
4145                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4146
4147                 if (tp->link_config.duplex == DUPLEX_FULL)
4148                         new_bmcr |= BMCR_FULLDPLX;
4149
4150                 if (new_bmcr != bmcr) {
4151                         /* BMCR_SPEED1000 is a reserved bit that needs
4152                          * to be set on write.
4153                          */
4154                         new_bmcr |= BMCR_SPEED1000;
4155
4156                         /* Force a linkdown */
4157                         if (netif_carrier_ok(tp->dev)) {
4158                                 u32 adv;
4159
4160                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4161                                 adv &= ~(ADVERTISE_1000XFULL |
4162                                          ADVERTISE_1000XHALF |
4163                                          ADVERTISE_SLCT);
4164                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4165                                 tg3_writephy(tp, MII_BMCR, bmcr |
4166                                                            BMCR_ANRESTART |
4167                                                            BMCR_ANENABLE);
4168                                 udelay(10);
4169                                 netif_carrier_off(tp->dev);
4170                         }
4171                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4172                         bmcr = new_bmcr;
4173                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4174                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4175                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4176                             ASIC_REV_5714) {
4177                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4178                                         bmsr |= BMSR_LSTATUS;
4179                                 else
4180                                         bmsr &= ~BMSR_LSTATUS;
4181                         }
4182                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4183                 }
4184         }
4185
4186         if (bmsr & BMSR_LSTATUS) {
4187                 current_speed = SPEED_1000;
4188                 current_link_up = 1;
4189                 if (bmcr & BMCR_FULLDPLX)
4190                         current_duplex = DUPLEX_FULL;
4191                 else
4192                         current_duplex = DUPLEX_HALF;
4193
4194                 local_adv = 0;
4195                 remote_adv = 0;
4196
4197                 if (bmcr & BMCR_ANENABLE) {
4198                         u32 common;
4199
4200                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4201                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4202                         common = local_adv & remote_adv;
4203                         if (common & (ADVERTISE_1000XHALF |
4204                                       ADVERTISE_1000XFULL)) {
4205                                 if (common & ADVERTISE_1000XFULL)
4206                                         current_duplex = DUPLEX_FULL;
4207                                 else
4208                                         current_duplex = DUPLEX_HALF;
4209                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4210                                 /* Link is up via parallel detect */
4211                         } else {
4212                                 current_link_up = 0;
4213                         }
4214                 }
4215         }
4216
4217         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4218                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4219
4220         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4221         if (tp->link_config.active_duplex == DUPLEX_HALF)
4222                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4223
4224         tw32_f(MAC_MODE, tp->mac_mode);
4225         udelay(40);
4226
4227         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4228
4229         tp->link_config.active_speed = current_speed;
4230         tp->link_config.active_duplex = current_duplex;
4231
4232         if (current_link_up != netif_carrier_ok(tp->dev)) {
4233                 if (current_link_up)
4234                         netif_carrier_on(tp->dev);
4235                 else {
4236                         netif_carrier_off(tp->dev);
4237                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4238                 }
4239                 tg3_link_report(tp);
4240         }
4241         return err;
4242 }
4243
4244 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4245 {
4246         if (tp->serdes_counter) {
4247                 /* Give autoneg time to complete. */
4248                 tp->serdes_counter--;
4249                 return;
4250         }
4251
4252         if (!netif_carrier_ok(tp->dev) &&
4253             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4254                 u32 bmcr;
4255
4256                 tg3_readphy(tp, MII_BMCR, &bmcr);
4257                 if (bmcr & BMCR_ANENABLE) {
4258                         u32 phy1, phy2;
4259
4260                         /* Select shadow register 0x1f */
4261                         tg3_writephy(tp, 0x1c, 0x7c00);
4262                         tg3_readphy(tp, 0x1c, &phy1);
4263
4264                         /* Select expansion interrupt status register */
4265                         tg3_writephy(tp, 0x17, 0x0f01);
4266                         tg3_readphy(tp, 0x15, &phy2);
4267                         tg3_readphy(tp, 0x15, &phy2);
4268
4269                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4270                                 /* We have signal detect and not receiving
4271                                  * config code words, link is up by parallel
4272                                  * detection.
4273                                  */
4274
4275                                 bmcr &= ~BMCR_ANENABLE;
4276                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4277                                 tg3_writephy(tp, MII_BMCR, bmcr);
4278                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4279                         }
4280                 }
4281         } else if (netif_carrier_ok(tp->dev) &&
4282                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4283                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4284                 u32 phy2;
4285
4286                 /* Select expansion interrupt status register */
4287                 tg3_writephy(tp, 0x17, 0x0f01);
4288                 tg3_readphy(tp, 0x15, &phy2);
4289                 if (phy2 & 0x20) {
4290                         u32 bmcr;
4291
4292                         /* Config code words received, turn on autoneg. */
4293                         tg3_readphy(tp, MII_BMCR, &bmcr);
4294                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4295
4296                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4297
4298                 }
4299         }
4300 }
4301
4302 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4303 {
4304         int err;
4305
4306         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4307                 err = tg3_setup_fiber_phy(tp, force_reset);
4308         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4309                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4310         else
4311                 err = tg3_setup_copper_phy(tp, force_reset);
4312
4313         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4314                 u32 val, scale;
4315
4316                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4317                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4318                         scale = 65;
4319                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4320                         scale = 6;
4321                 else
4322                         scale = 12;
4323
4324                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4325                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4326                 tw32(GRC_MISC_CFG, val);
4327         }
4328
4329         if (tp->link_config.active_speed == SPEED_1000 &&
4330             tp->link_config.active_duplex == DUPLEX_HALF)
4331                 tw32(MAC_TX_LENGTHS,
4332                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4333                       (6 << TX_LENGTHS_IPG_SHIFT) |
4334                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4335         else
4336                 tw32(MAC_TX_LENGTHS,
4337                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4338                       (6 << TX_LENGTHS_IPG_SHIFT) |
4339                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4340
4341         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4342                 if (netif_carrier_ok(tp->dev)) {
4343                         tw32(HOSTCC_STAT_COAL_TICKS,
4344                              tp->coal.stats_block_coalesce_usecs);
4345                 } else {
4346                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4347                 }
4348         }
4349
4350         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4351                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4352                 if (!netif_carrier_ok(tp->dev))
4353                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4354                               tp->pwrmgmt_thresh;
4355                 else
4356                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4357                 tw32(PCIE_PWR_MGMT_THRESH, val);
4358         }
4359
4360         return err;
4361 }
4362
4363 /* This is called whenever we suspect that the system chipset is re-
4364  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4365  * is bogus tx completions. We try to recover by setting the
4366  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4367  * in the workqueue.
4368  */
4369 static void tg3_tx_recover(struct tg3 *tp)
4370 {
4371         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4372                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4373
4374         netdev_warn(tp->dev,
4375                     "The system may be re-ordering memory-mapped I/O "
4376                     "cycles to the network device, attempting to recover. "
4377                     "Please report the problem to the driver maintainer "
4378                     "and include system chipset information.\n");
4379
4380         spin_lock(&tp->lock);
4381         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4382         spin_unlock(&tp->lock);
4383 }
4384
4385 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4386 {
4387         smp_mb();
4388         return tnapi->tx_pending -
4389                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4390 }
4391
4392 /* Tigon3 never reports partial packet sends.  So we do not
4393  * need special logic to handle SKBs that have not had all
4394  * of their frags sent yet, like SunGEM does.
4395  */
4396 static void tg3_tx(struct tg3_napi *tnapi)
4397 {
4398         struct tg3 *tp = tnapi->tp;
4399         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4400         u32 sw_idx = tnapi->tx_cons;
4401         struct netdev_queue *txq;
4402         int index = tnapi - tp->napi;
4403
4404         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4405                 index--;
4406
4407         txq = netdev_get_tx_queue(tp->dev, index);
4408
4409         while (sw_idx != hw_idx) {
4410                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4411                 struct sk_buff *skb = ri->skb;
4412                 int i, tx_bug = 0;
4413
4414                 if (unlikely(skb == NULL)) {
4415                         tg3_tx_recover(tp);
4416                         return;
4417                 }
4418
4419                 pci_unmap_single(tp->pdev,
4420                                  dma_unmap_addr(ri, mapping),
4421                                  skb_headlen(skb),
4422                                  PCI_DMA_TODEVICE);
4423
4424                 ri->skb = NULL;
4425
4426                 sw_idx = NEXT_TX(sw_idx);
4427
4428                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4429                         ri = &tnapi->tx_buffers[sw_idx];
4430                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4431                                 tx_bug = 1;
4432
4433                         pci_unmap_page(tp->pdev,
4434                                        dma_unmap_addr(ri, mapping),
4435                                        skb_shinfo(skb)->frags[i].size,
4436                                        PCI_DMA_TODEVICE);
4437                         sw_idx = NEXT_TX(sw_idx);
4438                 }
4439
4440                 dev_kfree_skb(skb);
4441
4442                 if (unlikely(tx_bug)) {
4443                         tg3_tx_recover(tp);
4444                         return;
4445                 }
4446         }
4447
4448         tnapi->tx_cons = sw_idx;
4449
4450         /* Need to make the tx_cons update visible to tg3_start_xmit()
4451          * before checking for netif_queue_stopped().  Without the
4452          * memory barrier, there is a small possibility that tg3_start_xmit()
4453          * will miss it and cause the queue to be stopped forever.
4454          */
4455         smp_mb();
4456
4457         if (unlikely(netif_tx_queue_stopped(txq) &&
4458                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4459                 __netif_tx_lock(txq, smp_processor_id());
4460                 if (netif_tx_queue_stopped(txq) &&
4461                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4462                         netif_tx_wake_queue(txq);
4463                 __netif_tx_unlock(txq);
4464         }
4465 }
4466
4467 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4468 {
4469         if (!ri->skb)
4470                 return;
4471
4472         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4473                          map_sz, PCI_DMA_FROMDEVICE);
4474         dev_kfree_skb_any(ri->skb);
4475         ri->skb = NULL;
4476 }
4477
4478 /* Returns size of skb allocated or < 0 on error.
4479  *
4480  * We only need to fill in the address because the other members
4481  * of the RX descriptor are invariant, see tg3_init_rings.
4482  *
4483  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4484  * posting buffers we only dirty the first cache line of the RX
4485  * descriptor (containing the address).  Whereas for the RX status
4486  * buffers the cpu only reads the last cacheline of the RX descriptor
4487  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4488  */
4489 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4490                             u32 opaque_key, u32 dest_idx_unmasked)
4491 {
4492         struct tg3_rx_buffer_desc *desc;
4493         struct ring_info *map, *src_map;
4494         struct sk_buff *skb;
4495         dma_addr_t mapping;
4496         int skb_size, dest_idx;
4497
4498         src_map = NULL;
4499         switch (opaque_key) {
4500         case RXD_OPAQUE_RING_STD:
4501                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4502                 desc = &tpr->rx_std[dest_idx];
4503                 map = &tpr->rx_std_buffers[dest_idx];
4504                 skb_size = tp->rx_pkt_map_sz;
4505                 break;
4506
4507         case RXD_OPAQUE_RING_JUMBO:
4508                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4509                 desc = &tpr->rx_jmb[dest_idx].std;
4510                 map = &tpr->rx_jmb_buffers[dest_idx];
4511                 skb_size = TG3_RX_JMB_MAP_SZ;
4512                 break;
4513
4514         default:
4515                 return -EINVAL;
4516         }
4517
4518         /* Do not overwrite any of the map or rp information
4519          * until we are sure we can commit to a new buffer.
4520          *
4521          * Callers depend upon this behavior and assume that
4522          * we leave everything unchanged if we fail.
4523          */
4524         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4525         if (skb == NULL)
4526                 return -ENOMEM;
4527
4528         skb_reserve(skb, tp->rx_offset);
4529
4530         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4531                                  PCI_DMA_FROMDEVICE);
4532         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4533                 dev_kfree_skb(skb);
4534                 return -EIO;
4535         }
4536
4537         map->skb = skb;
4538         dma_unmap_addr_set(map, mapping, mapping);
4539
4540         desc->addr_hi = ((u64)mapping >> 32);
4541         desc->addr_lo = ((u64)mapping & 0xffffffff);
4542
4543         return skb_size;
4544 }
4545
4546 /* We only need to move over in the address because the other
4547  * members of the RX descriptor are invariant.  See notes above
4548  * tg3_alloc_rx_skb for full details.
4549  */
4550 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4551                            struct tg3_rx_prodring_set *dpr,
4552                            u32 opaque_key, int src_idx,
4553                            u32 dest_idx_unmasked)
4554 {
4555         struct tg3 *tp = tnapi->tp;
4556         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4557         struct ring_info *src_map, *dest_map;
4558         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4559         int dest_idx;
4560
4561         switch (opaque_key) {
4562         case RXD_OPAQUE_RING_STD:
4563                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4564                 dest_desc = &dpr->rx_std[dest_idx];
4565                 dest_map = &dpr->rx_std_buffers[dest_idx];
4566                 src_desc = &spr->rx_std[src_idx];
4567                 src_map = &spr->rx_std_buffers[src_idx];
4568                 break;
4569
4570         case RXD_OPAQUE_RING_JUMBO:
4571                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4572                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4573                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4574                 src_desc = &spr->rx_jmb[src_idx].std;
4575                 src_map = &spr->rx_jmb_buffers[src_idx];
4576                 break;
4577
4578         default:
4579                 return;
4580         }
4581
4582         dest_map->skb = src_map->skb;
4583         dma_unmap_addr_set(dest_map, mapping,
4584                            dma_unmap_addr(src_map, mapping));
4585         dest_desc->addr_hi = src_desc->addr_hi;
4586         dest_desc->addr_lo = src_desc->addr_lo;
4587
4588         /* Ensure that the update to the skb happens after the physical
4589          * addresses have been transferred to the new BD location.
4590          */
4591         smp_wmb();
4592
4593         src_map->skb = NULL;
4594 }
4595
4596 /* The RX ring scheme is composed of multiple rings which post fresh
4597  * buffers to the chip, and one special ring the chip uses to report
4598  * status back to the host.
4599  *
4600  * The special ring reports the status of received packets to the
4601  * host.  The chip does not write into the original descriptor the
4602  * RX buffer was obtained from.  The chip simply takes the original
4603  * descriptor as provided by the host, updates the status and length
4604  * field, then writes this into the next status ring entry.
4605  *
4606  * Each ring the host uses to post buffers to the chip is described
4607  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4608  * it is first placed into the on-chip ram.  When the packet's length
4609  * is known, it walks down the TG3_BDINFO entries to select the ring.
4610  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4611  * which is within the range of the new packet's length is chosen.
4612  *
4613  * The "separate ring for rx status" scheme may sound queer, but it makes
4614  * sense from a cache coherency perspective.  If only the host writes
4615  * to the buffer post rings, and only the chip writes to the rx status
4616  * rings, then cache lines never move beyond shared-modified state.
4617  * If both the host and chip were to write into the same ring, cache line
4618  * eviction could occur since both entities want it in an exclusive state.
4619  */
4620 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4621 {
4622         struct tg3 *tp = tnapi->tp;
4623         u32 work_mask, rx_std_posted = 0;
4624         u32 std_prod_idx, jmb_prod_idx;
4625         u32 sw_idx = tnapi->rx_rcb_ptr;
4626         u16 hw_idx;
4627         int received;
4628         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4629
4630         hw_idx = *(tnapi->rx_rcb_prod_idx);
4631         /*
4632          * We need to order the read of hw_idx and the read of
4633          * the opaque cookie.
4634          */
4635         rmb();
4636         work_mask = 0;
4637         received = 0;
4638         std_prod_idx = tpr->rx_std_prod_idx;
4639         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4640         while (sw_idx != hw_idx && budget > 0) {
4641                 struct ring_info *ri;
4642                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4643                 unsigned int len;
4644                 struct sk_buff *skb;
4645                 dma_addr_t dma_addr;
4646                 u32 opaque_key, desc_idx, *post_ptr;
4647                 bool hw_vlan __maybe_unused = false;
4648                 u16 vtag __maybe_unused = 0;
4649
4650                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4651                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4652                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4653                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4654                         dma_addr = dma_unmap_addr(ri, mapping);
4655                         skb = ri->skb;
4656                         post_ptr = &std_prod_idx;
4657                         rx_std_posted++;
4658                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4659                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4660                         dma_addr = dma_unmap_addr(ri, mapping);
4661                         skb = ri->skb;
4662                         post_ptr = &jmb_prod_idx;
4663                 } else
4664                         goto next_pkt_nopost;
4665
4666                 work_mask |= opaque_key;
4667
4668                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4669                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4670                 drop_it:
4671                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4672                                        desc_idx, *post_ptr);
4673                 drop_it_no_recycle:
4674                         /* Other statistics kept track of by card. */
4675                         tp->net_stats.rx_dropped++;
4676                         goto next_pkt;
4677                 }
4678
4679                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4680                       ETH_FCS_LEN;
4681
4682                 if (len > TG3_RX_COPY_THRESH(tp)) {
4683                         int skb_size;
4684
4685                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4686                                                     *post_ptr);
4687                         if (skb_size < 0)
4688                                 goto drop_it;
4689
4690                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4691                                          PCI_DMA_FROMDEVICE);
4692
4693                         /* Ensure that the update to the skb happens
4694                          * after the usage of the old DMA mapping.
4695                          */
4696                         smp_wmb();
4697
4698                         ri->skb = NULL;
4699
4700                         skb_put(skb, len);
4701                 } else {
4702                         struct sk_buff *copy_skb;
4703
4704                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4705                                        desc_idx, *post_ptr);
4706
4707                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4708                                                     TG3_RAW_IP_ALIGN);
4709                         if (copy_skb == NULL)
4710                                 goto drop_it_no_recycle;
4711
4712                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4713                         skb_put(copy_skb, len);
4714                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4715                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4716                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4717
4718                         /* We'll reuse the original ring buffer. */
4719                         skb = copy_skb;
4720                 }
4721
4722                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4723                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4724                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4725                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4726                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4727                 else
4728                         skb->ip_summed = CHECKSUM_NONE;
4729
4730                 skb->protocol = eth_type_trans(skb, tp->dev);
4731
4732                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4733                     skb->protocol != htons(ETH_P_8021Q)) {
4734                         dev_kfree_skb(skb);
4735                         goto next_pkt;
4736                 }
4737
4738                 if (desc->type_flags & RXD_FLAG_VLAN &&
4739                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4740                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4741 #if TG3_VLAN_TAG_USED
4742                         if (tp->vlgrp)
4743                                 hw_vlan = true;
4744                         else
4745 #endif
4746                         {
4747                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4748                                                     __skb_push(skb, VLAN_HLEN);
4749
4750                                 memmove(ve, skb->data + VLAN_HLEN,
4751                                         ETH_ALEN * 2);
4752                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4753                                 ve->h_vlan_TCI = htons(vtag);
4754                         }
4755                 }
4756
4757 #if TG3_VLAN_TAG_USED
4758                 if (hw_vlan)
4759                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4760                 else
4761 #endif
4762                         napi_gro_receive(&tnapi->napi, skb);
4763
4764                 received++;
4765                 budget--;
4766
4767 next_pkt:
4768                 (*post_ptr)++;
4769
4770                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4771                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4772                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4773                                      tpr->rx_std_prod_idx);
4774                         work_mask &= ~RXD_OPAQUE_RING_STD;
4775                         rx_std_posted = 0;
4776                 }
4777 next_pkt_nopost:
4778                 sw_idx++;
4779                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4780
4781                 /* Refresh hw_idx to see if there is new work */
4782                 if (sw_idx == hw_idx) {
4783                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4784                         rmb();
4785                 }
4786         }
4787
4788         /* ACK the status ring. */
4789         tnapi->rx_rcb_ptr = sw_idx;
4790         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4791
4792         /* Refill RX ring(s). */
4793         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4794                 if (work_mask & RXD_OPAQUE_RING_STD) {
4795                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4796                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4797                                      tpr->rx_std_prod_idx);
4798                 }
4799                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4800                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4801                                                TG3_RX_JUMBO_RING_SIZE;
4802                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4803                                      tpr->rx_jmb_prod_idx);
4804                 }
4805                 mmiowb();
4806         } else if (work_mask) {
4807                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4808                  * updated before the producer indices can be updated.
4809                  */
4810                 smp_wmb();
4811
4812                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4813                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4814
4815                 if (tnapi != &tp->napi[1])
4816                         napi_schedule(&tp->napi[1].napi);
4817         }
4818
4819         return received;
4820 }
4821
4822 static void tg3_poll_link(struct tg3 *tp)
4823 {
4824         /* handle link change and other phy events */
4825         if (!(tp->tg3_flags &
4826               (TG3_FLAG_USE_LINKCHG_REG |
4827                TG3_FLAG_POLL_SERDES))) {
4828                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4829
4830                 if (sblk->status & SD_STATUS_LINK_CHG) {
4831                         sblk->status = SD_STATUS_UPDATED |
4832                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4833                         spin_lock(&tp->lock);
4834                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4835                                 tw32_f(MAC_STATUS,
4836                                      (MAC_STATUS_SYNC_CHANGED |
4837                                       MAC_STATUS_CFG_CHANGED |
4838                                       MAC_STATUS_MI_COMPLETION |
4839                                       MAC_STATUS_LNKSTATE_CHANGED));
4840                                 udelay(40);
4841                         } else
4842                                 tg3_setup_phy(tp, 0);
4843                         spin_unlock(&tp->lock);
4844                 }
4845         }
4846 }
4847
4848 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4849                                 struct tg3_rx_prodring_set *dpr,
4850                                 struct tg3_rx_prodring_set *spr)
4851 {
4852         u32 si, di, cpycnt, src_prod_idx;
4853         int i, err = 0;
4854
4855         while (1) {
4856                 src_prod_idx = spr->rx_std_prod_idx;
4857
4858                 /* Make sure updates to the rx_std_buffers[] entries and the
4859                  * standard producer index are seen in the correct order.
4860                  */
4861                 smp_rmb();
4862
4863                 if (spr->rx_std_cons_idx == src_prod_idx)
4864                         break;
4865
4866                 if (spr->rx_std_cons_idx < src_prod_idx)
4867                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4868                 else
4869                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4870
4871                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4872
4873                 si = spr->rx_std_cons_idx;
4874                 di = dpr->rx_std_prod_idx;
4875
4876                 for (i = di; i < di + cpycnt; i++) {
4877                         if (dpr->rx_std_buffers[i].skb) {
4878                                 cpycnt = i - di;
4879                                 err = -ENOSPC;
4880                                 break;
4881                         }
4882                 }
4883
4884                 if (!cpycnt)
4885                         break;
4886
4887                 /* Ensure that updates to the rx_std_buffers ring and the
4888                  * shadowed hardware producer ring from tg3_recycle_skb() are
4889                  * ordered correctly WRT the skb check above.
4890                  */
4891                 smp_rmb();
4892
4893                 memcpy(&dpr->rx_std_buffers[di],
4894                        &spr->rx_std_buffers[si],
4895                        cpycnt * sizeof(struct ring_info));
4896
4897                 for (i = 0; i < cpycnt; i++, di++, si++) {
4898                         struct tg3_rx_buffer_desc *sbd, *dbd;
4899                         sbd = &spr->rx_std[si];
4900                         dbd = &dpr->rx_std[di];
4901                         dbd->addr_hi = sbd->addr_hi;
4902                         dbd->addr_lo = sbd->addr_lo;
4903                 }
4904
4905                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4906                                        TG3_RX_RING_SIZE;
4907                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4908                                        TG3_RX_RING_SIZE;
4909         }
4910
4911         while (1) {
4912                 src_prod_idx = spr->rx_jmb_prod_idx;
4913
4914                 /* Make sure updates to the rx_jmb_buffers[] entries and
4915                  * the jumbo producer index are seen in the correct order.
4916                  */
4917                 smp_rmb();
4918
4919                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4920                         break;
4921
4922                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4923                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4924                 else
4925                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4926
4927                 cpycnt = min(cpycnt,
4928                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4929
4930                 si = spr->rx_jmb_cons_idx;
4931                 di = dpr->rx_jmb_prod_idx;
4932
4933                 for (i = di; i < di + cpycnt; i++) {
4934                         if (dpr->rx_jmb_buffers[i].skb) {
4935                                 cpycnt = i - di;
4936                                 err = -ENOSPC;
4937                                 break;
4938                         }
4939                 }
4940
4941                 if (!cpycnt)
4942                         break;
4943
4944                 /* Ensure that updates to the rx_jmb_buffers ring and the
4945                  * shadowed hardware producer ring from tg3_recycle_skb() are
4946                  * ordered correctly WRT the skb check above.
4947                  */
4948                 smp_rmb();
4949
4950                 memcpy(&dpr->rx_jmb_buffers[di],
4951                        &spr->rx_jmb_buffers[si],
4952                        cpycnt * sizeof(struct ring_info));
4953
4954                 for (i = 0; i < cpycnt; i++, di++, si++) {
4955                         struct tg3_rx_buffer_desc *sbd, *dbd;
4956                         sbd = &spr->rx_jmb[si].std;
4957                         dbd = &dpr->rx_jmb[di].std;
4958                         dbd->addr_hi = sbd->addr_hi;
4959                         dbd->addr_lo = sbd->addr_lo;
4960                 }
4961
4962                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4963                                        TG3_RX_JUMBO_RING_SIZE;
4964                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4965                                        TG3_RX_JUMBO_RING_SIZE;
4966         }
4967
4968         return err;
4969 }
4970
4971 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4972 {
4973         struct tg3 *tp = tnapi->tp;
4974
4975         /* run TX completion thread */
4976         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4977                 tg3_tx(tnapi);
4978                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4979                         return work_done;
4980         }
4981
4982         /* run RX thread, within the bounds set by NAPI.
4983          * All RX "locking" is done by ensuring outside
4984          * code synchronizes with tg3->napi.poll()
4985          */
4986         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4987                 work_done += tg3_rx(tnapi, budget - work_done);
4988
4989         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4990                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4991                 int i, err = 0;
4992                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4993                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4994
4995                 for (i = 1; i < tp->irq_cnt; i++)
4996                         err |= tg3_rx_prodring_xfer(tp, dpr,
4997                                                     tp->napi[i].prodring);
4998
4999                 wmb();
5000
5001                 if (std_prod_idx != dpr->rx_std_prod_idx)
5002                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5003                                      dpr->rx_std_prod_idx);
5004
5005                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5006                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5007                                      dpr->rx_jmb_prod_idx);
5008
5009                 mmiowb();
5010
5011                 if (err)
5012                         tw32_f(HOSTCC_MODE, tp->coal_now);
5013         }
5014
5015         return work_done;
5016 }
5017
5018 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5019 {
5020         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5021         struct tg3 *tp = tnapi->tp;
5022         int work_done = 0;
5023         struct tg3_hw_status *sblk = tnapi->hw_status;
5024
5025         while (1) {
5026                 work_done = tg3_poll_work(tnapi, work_done, budget);
5027
5028                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5029                         goto tx_recovery;
5030
5031                 if (unlikely(work_done >= budget))
5032                         break;
5033
5034                 /* tp->last_tag is used in tg3_int_reenable() below
5035                  * to tell the hw how much work has been processed,
5036                  * so we must read it before checking for more work.
5037                  */
5038                 tnapi->last_tag = sblk->status_tag;
5039                 tnapi->last_irq_tag = tnapi->last_tag;
5040                 rmb();
5041
5042                 /* check for RX/TX work to do */
5043                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5044                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5045                         napi_complete(napi);
5046                         /* Reenable interrupts. */
5047                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5048                         mmiowb();
5049                         break;
5050                 }
5051         }
5052
5053         return work_done;
5054
5055 tx_recovery:
5056         /* work_done is guaranteed to be less than budget. */
5057         napi_complete(napi);
5058         schedule_work(&tp->reset_task);
5059         return work_done;
5060 }
5061
5062 static int tg3_poll(struct napi_struct *napi, int budget)
5063 {
5064         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5065         struct tg3 *tp = tnapi->tp;
5066         int work_done = 0;
5067         struct tg3_hw_status *sblk = tnapi->hw_status;
5068
5069         while (1) {
5070                 tg3_poll_link(tp);
5071
5072                 work_done = tg3_poll_work(tnapi, work_done, budget);
5073
5074                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5075                         goto tx_recovery;
5076
5077                 if (unlikely(work_done >= budget))
5078                         break;
5079
5080                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5081                         /* tp->last_tag is used in tg3_int_reenable() below
5082                          * to tell the hw how much work has been processed,
5083                          * so we must read it before checking for more work.
5084                          */
5085                         tnapi->last_tag = sblk->status_tag;
5086                         tnapi->last_irq_tag = tnapi->last_tag;
5087                         rmb();
5088                 } else
5089                         sblk->status &= ~SD_STATUS_UPDATED;
5090
5091                 if (likely(!tg3_has_work(tnapi))) {
5092                         napi_complete(napi);
5093                         tg3_int_reenable(tnapi);
5094                         break;
5095                 }
5096         }
5097
5098         return work_done;
5099
5100 tx_recovery:
5101         /* work_done is guaranteed to be less than budget. */
5102         napi_complete(napi);
5103         schedule_work(&tp->reset_task);
5104         return work_done;
5105 }
5106
5107 static void tg3_irq_quiesce(struct tg3 *tp)
5108 {
5109         int i;
5110
5111         BUG_ON(tp->irq_sync);
5112
5113         tp->irq_sync = 1;
5114         smp_mb();
5115
5116         for (i = 0; i < tp->irq_cnt; i++)
5117                 synchronize_irq(tp->napi[i].irq_vec);
5118 }
5119
5120 static inline int tg3_irq_sync(struct tg3 *tp)
5121 {
5122         return tp->irq_sync;
5123 }
5124
5125 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5126  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5127  * with as well.  Most of the time, this is not necessary except when
5128  * shutting down the device.
5129  */
5130 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5131 {
5132         spin_lock_bh(&tp->lock);
5133         if (irq_sync)
5134                 tg3_irq_quiesce(tp);
5135 }
5136
5137 static inline void tg3_full_unlock(struct tg3 *tp)
5138 {
5139         spin_unlock_bh(&tp->lock);
5140 }
5141
5142 /* One-shot MSI handler - Chip automatically disables interrupt
5143  * after sending MSI so driver doesn't have to do it.
5144  */
5145 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5146 {
5147         struct tg3_napi *tnapi = dev_id;
5148         struct tg3 *tp = tnapi->tp;
5149
5150         prefetch(tnapi->hw_status);
5151         if (tnapi->rx_rcb)
5152                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5153
5154         if (likely(!tg3_irq_sync(tp)))
5155                 napi_schedule(&tnapi->napi);
5156
5157         return IRQ_HANDLED;
5158 }
5159
5160 /* MSI ISR - No need to check for interrupt sharing and no need to
5161  * flush status block and interrupt mailbox. PCI ordering rules
5162  * guarantee that MSI will arrive after the status block.
5163  */
5164 static irqreturn_t tg3_msi(int irq, void *dev_id)
5165 {
5166         struct tg3_napi *tnapi = dev_id;
5167         struct tg3 *tp = tnapi->tp;
5168
5169         prefetch(tnapi->hw_status);
5170         if (tnapi->rx_rcb)
5171                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5172         /*
5173          * Writing any value to intr-mbox-0 clears PCI INTA# and
5174          * chip-internal interrupt pending events.
5175          * Writing non-zero to intr-mbox-0 additional tells the
5176          * NIC to stop sending us irqs, engaging "in-intr-handler"
5177          * event coalescing.
5178          */
5179         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5180         if (likely(!tg3_irq_sync(tp)))
5181                 napi_schedule(&tnapi->napi);
5182
5183         return IRQ_RETVAL(1);
5184 }
5185
5186 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5187 {
5188         struct tg3_napi *tnapi = dev_id;
5189         struct tg3 *tp = tnapi->tp;
5190         struct tg3_hw_status *sblk = tnapi->hw_status;
5191         unsigned int handled = 1;
5192
5193         /* In INTx mode, it is possible for the interrupt to arrive at
5194          * the CPU before the status block posted prior to the interrupt.
5195          * Reading the PCI State register will confirm whether the
5196          * interrupt is ours and will flush the status block.
5197          */
5198         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5199                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5200                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5201                         handled = 0;
5202                         goto out;
5203                 }
5204         }
5205
5206         /*
5207          * Writing any value to intr-mbox-0 clears PCI INTA# and
5208          * chip-internal interrupt pending events.
5209          * Writing non-zero to intr-mbox-0 additional tells the
5210          * NIC to stop sending us irqs, engaging "in-intr-handler"
5211          * event coalescing.
5212          *
5213          * Flush the mailbox to de-assert the IRQ immediately to prevent
5214          * spurious interrupts.  The flush impacts performance but
5215          * excessive spurious interrupts can be worse in some cases.
5216          */
5217         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5218         if (tg3_irq_sync(tp))
5219                 goto out;
5220         sblk->status &= ~SD_STATUS_UPDATED;
5221         if (likely(tg3_has_work(tnapi))) {
5222                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5223                 napi_schedule(&tnapi->napi);
5224         } else {
5225                 /* No work, shared interrupt perhaps?  re-enable
5226                  * interrupts, and flush that PCI write
5227                  */
5228                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5229                                0x00000000);
5230         }
5231 out:
5232         return IRQ_RETVAL(handled);
5233 }
5234
5235 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5236 {
5237         struct tg3_napi *tnapi = dev_id;
5238         struct tg3 *tp = tnapi->tp;
5239         struct tg3_hw_status *sblk = tnapi->hw_status;
5240         unsigned int handled = 1;
5241
5242         /* In INTx mode, it is possible for the interrupt to arrive at
5243          * the CPU before the status block posted prior to the interrupt.
5244          * Reading the PCI State register will confirm whether the
5245          * interrupt is ours and will flush the status block.
5246          */
5247         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5248                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5249                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5250                         handled = 0;
5251                         goto out;
5252                 }
5253         }
5254
5255         /*
5256          * writing any value to intr-mbox-0 clears PCI INTA# and
5257          * chip-internal interrupt pending events.
5258          * writing non-zero to intr-mbox-0 additional tells the
5259          * NIC to stop sending us irqs, engaging "in-intr-handler"
5260          * event coalescing.
5261          *
5262          * Flush the mailbox to de-assert the IRQ immediately to prevent
5263          * spurious interrupts.  The flush impacts performance but
5264          * excessive spurious interrupts can be worse in some cases.
5265          */
5266         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5267
5268         /*
5269          * In a shared interrupt configuration, sometimes other devices'
5270          * interrupts will scream.  We record the current status tag here
5271          * so that the above check can report that the screaming interrupts
5272          * are unhandled.  Eventually they will be silenced.
5273          */
5274         tnapi->last_irq_tag = sblk->status_tag;
5275
5276         if (tg3_irq_sync(tp))
5277                 goto out;
5278
5279         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5280
5281         napi_schedule(&tnapi->napi);
5282
5283 out:
5284         return IRQ_RETVAL(handled);
5285 }
5286
5287 /* ISR for interrupt test */
5288 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5289 {
5290         struct tg3_napi *tnapi = dev_id;
5291         struct tg3 *tp = tnapi->tp;
5292         struct tg3_hw_status *sblk = tnapi->hw_status;
5293
5294         if ((sblk->status & SD_STATUS_UPDATED) ||
5295             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5296                 tg3_disable_ints(tp);
5297                 return IRQ_RETVAL(1);
5298         }
5299         return IRQ_RETVAL(0);
5300 }
5301
5302 static int tg3_init_hw(struct tg3 *, int);
5303 static int tg3_halt(struct tg3 *, int, int);
5304
5305 /* Restart hardware after configuration changes, self-test, etc.
5306  * Invoked with tp->lock held.
5307  */
5308 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5309         __releases(tp->lock)
5310         __acquires(tp->lock)
5311 {
5312         int err;
5313
5314         err = tg3_init_hw(tp, reset_phy);
5315         if (err) {
5316                 netdev_err(tp->dev,
5317                            "Failed to re-initialize device, aborting\n");
5318                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5319                 tg3_full_unlock(tp);
5320                 del_timer_sync(&tp->timer);
5321                 tp->irq_sync = 0;
5322                 tg3_napi_enable(tp);
5323                 dev_close(tp->dev);
5324                 tg3_full_lock(tp, 0);
5325         }
5326         return err;
5327 }
5328
5329 #ifdef CONFIG_NET_POLL_CONTROLLER
5330 static void tg3_poll_controller(struct net_device *dev)
5331 {
5332         int i;
5333         struct tg3 *tp = netdev_priv(dev);
5334
5335         for (i = 0; i < tp->irq_cnt; i++)
5336                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5337 }
5338 #endif
5339
5340 static void tg3_reset_task(struct work_struct *work)
5341 {
5342         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5343         int err;
5344         unsigned int restart_timer;
5345
5346         tg3_full_lock(tp, 0);
5347
5348         if (!netif_running(tp->dev)) {
5349                 tg3_full_unlock(tp);
5350                 return;
5351         }
5352
5353         tg3_full_unlock(tp);
5354
5355         tg3_phy_stop(tp);
5356
5357         tg3_netif_stop(tp);
5358
5359         tg3_full_lock(tp, 1);
5360
5361         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5362         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5363
5364         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5365                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5366                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5367                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5368                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5369         }
5370
5371         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5372         err = tg3_init_hw(tp, 1);
5373         if (err)
5374                 goto out;
5375
5376         tg3_netif_start(tp);
5377
5378         if (restart_timer)
5379                 mod_timer(&tp->timer, jiffies + 1);
5380
5381 out:
5382         tg3_full_unlock(tp);
5383
5384         if (!err)
5385                 tg3_phy_start(tp);
5386 }
5387
5388 static void tg3_dump_short_state(struct tg3 *tp)
5389 {
5390         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5391                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5392         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5393                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5394 }
5395
5396 static void tg3_tx_timeout(struct net_device *dev)
5397 {
5398         struct tg3 *tp = netdev_priv(dev);
5399
5400         if (netif_msg_tx_err(tp)) {
5401                 netdev_err(dev, "transmit timed out, resetting\n");
5402                 tg3_dump_short_state(tp);
5403         }
5404
5405         schedule_work(&tp->reset_task);
5406 }
5407
5408 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5409 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5410 {
5411         u32 base = (u32) mapping & 0xffffffff;
5412
5413         return ((base > 0xffffdcc0) &&
5414                 (base + len + 8 < base));
5415 }
5416
5417 /* Test for DMA addresses > 40-bit */
5418 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5419                                           int len)
5420 {
5421 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5422         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5423                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5424         return 0;
5425 #else
5426         return 0;
5427 #endif
5428 }
5429
5430 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5431
5432 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5433 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5434                                        struct sk_buff *skb, u32 last_plus_one,
5435                                        u32 *start, u32 base_flags, u32 mss)
5436 {
5437         struct tg3 *tp = tnapi->tp;
5438         struct sk_buff *new_skb;
5439         dma_addr_t new_addr = 0;
5440         u32 entry = *start;
5441         int i, ret = 0;
5442
5443         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5444                 new_skb = skb_copy(skb, GFP_ATOMIC);
5445         else {
5446                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5447
5448                 new_skb = skb_copy_expand(skb,
5449                                           skb_headroom(skb) + more_headroom,
5450                                           skb_tailroom(skb), GFP_ATOMIC);
5451         }
5452
5453         if (!new_skb) {
5454                 ret = -1;
5455         } else {
5456                 /* New SKB is guaranteed to be linear. */
5457                 entry = *start;
5458                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5459                                           PCI_DMA_TODEVICE);
5460                 /* Make sure the mapping succeeded */
5461                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5462                         ret = -1;
5463                         dev_kfree_skb(new_skb);
5464                         new_skb = NULL;
5465
5466                 /* Make sure new skb does not cross any 4G boundaries.
5467                  * Drop the packet if it does.
5468                  */
5469                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5470                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5471                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5472                                          PCI_DMA_TODEVICE);
5473                         ret = -1;
5474                         dev_kfree_skb(new_skb);
5475                         new_skb = NULL;
5476                 } else {
5477                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5478                                     base_flags, 1 | (mss << 1));
5479                         *start = NEXT_TX(entry);
5480                 }
5481         }
5482
5483         /* Now clean up the sw ring entries. */
5484         i = 0;
5485         while (entry != last_plus_one) {
5486                 int len;
5487
5488                 if (i == 0)
5489                         len = skb_headlen(skb);
5490                 else
5491                         len = skb_shinfo(skb)->frags[i-1].size;
5492
5493                 pci_unmap_single(tp->pdev,
5494                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5495                                                 mapping),
5496                                  len, PCI_DMA_TODEVICE);
5497                 if (i == 0) {
5498                         tnapi->tx_buffers[entry].skb = new_skb;
5499                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5500                                            new_addr);
5501                 } else {
5502                         tnapi->tx_buffers[entry].skb = NULL;
5503                 }
5504                 entry = NEXT_TX(entry);
5505                 i++;
5506         }
5507
5508         dev_kfree_skb(skb);
5509
5510         return ret;
5511 }
5512
5513 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5514                         dma_addr_t mapping, int len, u32 flags,
5515                         u32 mss_and_is_end)
5516 {
5517         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5518         int is_end = (mss_and_is_end & 0x1);
5519         u32 mss = (mss_and_is_end >> 1);
5520         u32 vlan_tag = 0;
5521
5522         if (is_end)
5523                 flags |= TXD_FLAG_END;
5524         if (flags & TXD_FLAG_VLAN) {
5525                 vlan_tag = flags >> 16;
5526                 flags &= 0xffff;
5527         }
5528         vlan_tag |= (mss << TXD_MSS_SHIFT);
5529
5530         txd->addr_hi = ((u64) mapping >> 32);
5531         txd->addr_lo = ((u64) mapping & 0xffffffff);
5532         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5533         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5534 }
5535
5536 /* hard_start_xmit for devices that don't have any bugs and
5537  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5538  */
5539 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5540                                   struct net_device *dev)
5541 {
5542         struct tg3 *tp = netdev_priv(dev);
5543         u32 len, entry, base_flags, mss;
5544         dma_addr_t mapping;
5545         struct tg3_napi *tnapi;
5546         struct netdev_queue *txq;
5547         unsigned int i, last;
5548
5549         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5550         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5551         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5552                 tnapi++;
5553
5554         /* We are running in BH disabled context with netif_tx_lock
5555          * and TX reclaim runs via tp->napi.poll inside of a software
5556          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5557          * no IRQ context deadlocks to worry about either.  Rejoice!
5558          */
5559         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5560                 if (!netif_tx_queue_stopped(txq)) {
5561                         netif_tx_stop_queue(txq);
5562
5563                         /* This is a hard error, log it. */
5564                         netdev_err(dev,
5565                                    "BUG! Tx Ring full when queue awake!\n");
5566                 }
5567                 return NETDEV_TX_BUSY;
5568         }
5569
5570         entry = tnapi->tx_prod;
5571         base_flags = 0;
5572         mss = 0;
5573         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5574                 int tcp_opt_len, ip_tcp_len;
5575                 u32 hdrlen;
5576
5577                 if (skb_header_cloned(skb) &&
5578                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5579                         dev_kfree_skb(skb);
5580                         goto out_unlock;
5581                 }
5582
5583                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5584                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5585                 else {
5586                         struct iphdr *iph = ip_hdr(skb);
5587
5588                         tcp_opt_len = tcp_optlen(skb);
5589                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5590
5591                         iph->check = 0;
5592                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5593                         hdrlen = ip_tcp_len + tcp_opt_len;
5594                 }
5595
5596                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5597                         mss |= (hdrlen & 0xc) << 12;
5598                         if (hdrlen & 0x10)
5599                                 base_flags |= 0x00000010;
5600                         base_flags |= (hdrlen & 0x3e0) << 5;
5601                 } else
5602                         mss |= hdrlen << 9;
5603
5604                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5605                                TXD_FLAG_CPU_POST_DMA);
5606
5607                 tcp_hdr(skb)->check = 0;
5608
5609         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5610                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5611         }
5612
5613 #if TG3_VLAN_TAG_USED
5614         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5615                 base_flags |= (TXD_FLAG_VLAN |
5616                                (vlan_tx_tag_get(skb) << 16));
5617 #endif
5618
5619         len = skb_headlen(skb);
5620
5621         /* Queue skb data, a.k.a. the main skb fragment. */
5622         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5623         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5624                 dev_kfree_skb(skb);
5625                 goto out_unlock;
5626         }
5627
5628         tnapi->tx_buffers[entry].skb = skb;
5629         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5630
5631         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5632             !mss && skb->len > ETH_DATA_LEN)
5633                 base_flags |= TXD_FLAG_JMB_PKT;
5634
5635         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5636                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5637
5638         entry = NEXT_TX(entry);
5639
5640         /* Now loop through additional data fragments, and queue them. */
5641         if (skb_shinfo(skb)->nr_frags > 0) {
5642                 last = skb_shinfo(skb)->nr_frags - 1;
5643                 for (i = 0; i <= last; i++) {
5644                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5645
5646                         len = frag->size;
5647                         mapping = pci_map_page(tp->pdev,
5648                                                frag->page,
5649                                                frag->page_offset,
5650                                                len, PCI_DMA_TODEVICE);
5651                         if (pci_dma_mapping_error(tp->pdev, mapping))
5652                                 goto dma_error;
5653
5654                         tnapi->tx_buffers[entry].skb = NULL;
5655                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5656                                            mapping);
5657
5658                         tg3_set_txd(tnapi, entry, mapping, len,
5659                                     base_flags, (i == last) | (mss << 1));
5660
5661                         entry = NEXT_TX(entry);
5662                 }
5663         }
5664
5665         /* Packets are ready, update Tx producer idx local and on card. */
5666         tw32_tx_mbox(tnapi->prodmbox, entry);
5667
5668         tnapi->tx_prod = entry;
5669         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5670                 netif_tx_stop_queue(txq);
5671                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5672                         netif_tx_wake_queue(txq);
5673         }
5674
5675 out_unlock:
5676         mmiowb();
5677
5678         return NETDEV_TX_OK;
5679
5680 dma_error:
5681         last = i;
5682         entry = tnapi->tx_prod;
5683         tnapi->tx_buffers[entry].skb = NULL;
5684         pci_unmap_single(tp->pdev,
5685                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5686                          skb_headlen(skb),
5687                          PCI_DMA_TODEVICE);
5688         for (i = 0; i <= last; i++) {
5689                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5690                 entry = NEXT_TX(entry);
5691
5692                 pci_unmap_page(tp->pdev,
5693                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5694                                               mapping),
5695                                frag->size, PCI_DMA_TODEVICE);
5696         }
5697
5698         dev_kfree_skb(skb);
5699         return NETDEV_TX_OK;
5700 }
5701
5702 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5703                                           struct net_device *);
5704
5705 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5706  * TSO header is greater than 80 bytes.
5707  */
5708 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5709 {
5710         struct sk_buff *segs, *nskb;
5711         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5712
5713         /* Estimate the number of fragments in the worst case */
5714         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5715                 netif_stop_queue(tp->dev);
5716                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5717                         return NETDEV_TX_BUSY;
5718
5719                 netif_wake_queue(tp->dev);
5720         }
5721
5722         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5723         if (IS_ERR(segs))
5724                 goto tg3_tso_bug_end;
5725
5726         do {
5727                 nskb = segs;
5728                 segs = segs->next;
5729                 nskb->next = NULL;
5730                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5731         } while (segs);
5732
5733 tg3_tso_bug_end:
5734         dev_kfree_skb(skb);
5735
5736         return NETDEV_TX_OK;
5737 }
5738
5739 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5740  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5741  */
5742 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5743                                           struct net_device *dev)
5744 {
5745         struct tg3 *tp = netdev_priv(dev);
5746         u32 len, entry, base_flags, mss;
5747         int would_hit_hwbug;
5748         dma_addr_t mapping;
5749         struct tg3_napi *tnapi;
5750         struct netdev_queue *txq;
5751         unsigned int i, last;
5752
5753         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5754         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5755         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5756                 tnapi++;
5757
5758         /* We are running in BH disabled context with netif_tx_lock
5759          * and TX reclaim runs via tp->napi.poll inside of a software
5760          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5761          * no IRQ context deadlocks to worry about either.  Rejoice!
5762          */
5763         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5764                 if (!netif_tx_queue_stopped(txq)) {
5765                         netif_tx_stop_queue(txq);
5766
5767                         /* This is a hard error, log it. */
5768                         netdev_err(dev,
5769                                    "BUG! Tx Ring full when queue awake!\n");
5770                 }
5771                 return NETDEV_TX_BUSY;
5772         }
5773
5774         entry = tnapi->tx_prod;
5775         base_flags = 0;
5776         if (skb->ip_summed == CHECKSUM_PARTIAL)
5777                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5778
5779         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5780                 struct iphdr *iph;
5781                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5782
5783                 if (skb_header_cloned(skb) &&
5784                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5785                         dev_kfree_skb(skb);
5786                         goto out_unlock;
5787                 }
5788
5789                 tcp_opt_len = tcp_optlen(skb);
5790                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5791
5792                 hdr_len = ip_tcp_len + tcp_opt_len;
5793                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5794                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5795                         return tg3_tso_bug(tp, skb);
5796
5797                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5798                                TXD_FLAG_CPU_POST_DMA);
5799
5800                 iph = ip_hdr(skb);
5801                 iph->check = 0;
5802                 iph->tot_len = htons(mss + hdr_len);
5803                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5804                         tcp_hdr(skb)->check = 0;
5805                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5806                 } else
5807                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5808                                                                  iph->daddr, 0,
5809                                                                  IPPROTO_TCP,
5810                                                                  0);
5811
5812                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5813                         mss |= (hdr_len & 0xc) << 12;
5814                         if (hdr_len & 0x10)
5815                                 base_flags |= 0x00000010;
5816                         base_flags |= (hdr_len & 0x3e0) << 5;
5817                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5818                         mss |= hdr_len << 9;
5819                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5820                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5821                         if (tcp_opt_len || iph->ihl > 5) {
5822                                 int tsflags;
5823
5824                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5825                                 mss |= (tsflags << 11);
5826                         }
5827                 } else {
5828                         if (tcp_opt_len || iph->ihl > 5) {
5829                                 int tsflags;
5830
5831                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5832                                 base_flags |= tsflags << 12;
5833                         }
5834                 }
5835         }
5836 #if TG3_VLAN_TAG_USED
5837         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5838                 base_flags |= (TXD_FLAG_VLAN |
5839                                (vlan_tx_tag_get(skb) << 16));
5840 #endif
5841
5842         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5843             !mss && skb->len > ETH_DATA_LEN)
5844                 base_flags |= TXD_FLAG_JMB_PKT;
5845
5846         len = skb_headlen(skb);
5847
5848         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5849         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5850                 dev_kfree_skb(skb);
5851                 goto out_unlock;
5852         }
5853
5854         tnapi->tx_buffers[entry].skb = skb;
5855         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5856
5857         would_hit_hwbug = 0;
5858
5859         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5860                 would_hit_hwbug = 1;
5861
5862         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5863             tg3_4g_overflow_test(mapping, len))
5864                 would_hit_hwbug = 1;
5865
5866         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5867             tg3_40bit_overflow_test(tp, mapping, len))
5868                 would_hit_hwbug = 1;
5869
5870         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5871                 would_hit_hwbug = 1;
5872
5873         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5874                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5875
5876         entry = NEXT_TX(entry);
5877
5878         /* Now loop through additional data fragments, and queue them. */
5879         if (skb_shinfo(skb)->nr_frags > 0) {
5880                 last = skb_shinfo(skb)->nr_frags - 1;
5881                 for (i = 0; i <= last; i++) {
5882                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5883
5884                         len = frag->size;
5885                         mapping = pci_map_page(tp->pdev,
5886                                                frag->page,
5887                                                frag->page_offset,
5888                                                len, PCI_DMA_TODEVICE);
5889
5890                         tnapi->tx_buffers[entry].skb = NULL;
5891                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5892                                            mapping);
5893                         if (pci_dma_mapping_error(tp->pdev, mapping))
5894                                 goto dma_error;
5895
5896                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5897                             len <= 8)
5898                                 would_hit_hwbug = 1;
5899
5900                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5901                             tg3_4g_overflow_test(mapping, len))
5902                                 would_hit_hwbug = 1;
5903
5904                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5905                             tg3_40bit_overflow_test(tp, mapping, len))
5906                                 would_hit_hwbug = 1;
5907
5908                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5909                                 tg3_set_txd(tnapi, entry, mapping, len,
5910                                             base_flags, (i == last)|(mss << 1));
5911                         else
5912                                 tg3_set_txd(tnapi, entry, mapping, len,
5913                                             base_flags, (i == last));
5914
5915                         entry = NEXT_TX(entry);
5916                 }
5917         }
5918
5919         if (would_hit_hwbug) {
5920                 u32 last_plus_one = entry;
5921                 u32 start;
5922
5923                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5924                 start &= (TG3_TX_RING_SIZE - 1);
5925
5926                 /* If the workaround fails due to memory/mapping
5927                  * failure, silently drop this packet.
5928                  */
5929                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5930                                                 &start, base_flags, mss))
5931                         goto out_unlock;
5932
5933                 entry = start;
5934         }
5935
5936         /* Packets are ready, update Tx producer idx local and on card. */
5937         tw32_tx_mbox(tnapi->prodmbox, entry);
5938
5939         tnapi->tx_prod = entry;
5940         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5941                 netif_tx_stop_queue(txq);
5942                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5943                         netif_tx_wake_queue(txq);
5944         }
5945
5946 out_unlock:
5947         mmiowb();
5948
5949         return NETDEV_TX_OK;
5950
5951 dma_error:
5952         last = i;
5953         entry = tnapi->tx_prod;
5954         tnapi->tx_buffers[entry].skb = NULL;
5955         pci_unmap_single(tp->pdev,
5956                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5957                          skb_headlen(skb),
5958                          PCI_DMA_TODEVICE);
5959         for (i = 0; i <= last; i++) {
5960                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5961                 entry = NEXT_TX(entry);
5962
5963                 pci_unmap_page(tp->pdev,
5964                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5965                                               mapping),
5966                                frag->size, PCI_DMA_TODEVICE);
5967         }
5968
5969         dev_kfree_skb(skb);
5970         return NETDEV_TX_OK;
5971 }
5972
5973 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5974                                int new_mtu)
5975 {
5976         dev->mtu = new_mtu;
5977
5978         if (new_mtu > ETH_DATA_LEN) {
5979                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5980                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5981                         ethtool_op_set_tso(dev, 0);
5982                 } else {
5983                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5984                 }
5985         } else {
5986                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5987                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5988                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5989         }
5990 }
5991
5992 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5993 {
5994         struct tg3 *tp = netdev_priv(dev);
5995         int err;
5996
5997         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5998                 return -EINVAL;
5999
6000         if (!netif_running(dev)) {
6001                 /* We'll just catch it later when the
6002                  * device is up'd.
6003                  */
6004                 tg3_set_mtu(dev, tp, new_mtu);
6005                 return 0;
6006         }
6007
6008         tg3_phy_stop(tp);
6009
6010         tg3_netif_stop(tp);
6011
6012         tg3_full_lock(tp, 1);
6013
6014         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6015
6016         tg3_set_mtu(dev, tp, new_mtu);
6017
6018         err = tg3_restart_hw(tp, 0);
6019
6020         if (!err)
6021                 tg3_netif_start(tp);
6022
6023         tg3_full_unlock(tp);
6024
6025         if (!err)
6026                 tg3_phy_start(tp);
6027
6028         return err;
6029 }
6030
6031 static void tg3_rx_prodring_free(struct tg3 *tp,
6032                                  struct tg3_rx_prodring_set *tpr)
6033 {
6034         int i;
6035
6036         if (tpr != &tp->prodring[0]) {
6037                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6038                      i = (i + 1) % TG3_RX_RING_SIZE)
6039                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6040                                         tp->rx_pkt_map_sz);
6041
6042                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6043                         for (i = tpr->rx_jmb_cons_idx;
6044                              i != tpr->rx_jmb_prod_idx;
6045                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6046                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6047                                                 TG3_RX_JMB_MAP_SZ);
6048                         }
6049                 }
6050
6051                 return;
6052         }
6053
6054         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6055                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6056                                 tp->rx_pkt_map_sz);
6057
6058         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6059                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6060                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6061                                         TG3_RX_JMB_MAP_SZ);
6062         }
6063 }
6064
6065 /* Initialize rx rings for packet processing.
6066  *
6067  * The chip has been shut down and the driver detached from
6068  * the networking, so no interrupts or new tx packets will
6069  * end up in the driver.  tp->{tx,}lock are held and thus
6070  * we may not sleep.
6071  */
6072 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6073                                  struct tg3_rx_prodring_set *tpr)
6074 {
6075         u32 i, rx_pkt_dma_sz;
6076
6077         tpr->rx_std_cons_idx = 0;
6078         tpr->rx_std_prod_idx = 0;
6079         tpr->rx_jmb_cons_idx = 0;
6080         tpr->rx_jmb_prod_idx = 0;
6081
6082         if (tpr != &tp->prodring[0]) {
6083                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6084                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6085                         memset(&tpr->rx_jmb_buffers[0], 0,
6086                                TG3_RX_JMB_BUFF_RING_SIZE);
6087                 goto done;
6088         }
6089
6090         /* Zero out all descriptors. */
6091         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6092
6093         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6094         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6095             tp->dev->mtu > ETH_DATA_LEN)
6096                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6097         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6098
6099         /* Initialize invariants of the rings, we only set this
6100          * stuff once.  This works because the card does not
6101          * write into the rx buffer posting rings.
6102          */
6103         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6104                 struct tg3_rx_buffer_desc *rxd;
6105
6106                 rxd = &tpr->rx_std[i];
6107                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6108                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6109                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6110                                (i << RXD_OPAQUE_INDEX_SHIFT));
6111         }
6112
6113         /* Now allocate fresh SKBs for each rx ring. */
6114         for (i = 0; i < tp->rx_pending; i++) {
6115                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6116                         netdev_warn(tp->dev,
6117                                     "Using a smaller RX standard ring. Only "
6118                                     "%d out of %d buffers were allocated "
6119                                     "successfully\n", i, tp->rx_pending);
6120                         if (i == 0)
6121                                 goto initfail;
6122                         tp->rx_pending = i;
6123                         break;
6124                 }
6125         }
6126
6127         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6128                 goto done;
6129
6130         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6131
6132         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6133                 goto done;
6134
6135         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6136                 struct tg3_rx_buffer_desc *rxd;
6137
6138                 rxd = &tpr->rx_jmb[i].std;
6139                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6140                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6141                                   RXD_FLAG_JUMBO;
6142                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6143                        (i << RXD_OPAQUE_INDEX_SHIFT));
6144         }
6145
6146         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6147                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6148                         netdev_warn(tp->dev,
6149                                     "Using a smaller RX jumbo ring. Only %d "
6150                                     "out of %d buffers were allocated "
6151                                     "successfully\n", i, tp->rx_jumbo_pending);
6152                         if (i == 0)
6153                                 goto initfail;
6154                         tp->rx_jumbo_pending = i;
6155                         break;
6156                 }
6157         }
6158
6159 done:
6160         return 0;
6161
6162 initfail:
6163         tg3_rx_prodring_free(tp, tpr);
6164         return -ENOMEM;
6165 }
6166
6167 static void tg3_rx_prodring_fini(struct tg3 *tp,
6168                                  struct tg3_rx_prodring_set *tpr)
6169 {
6170         kfree(tpr->rx_std_buffers);
6171         tpr->rx_std_buffers = NULL;
6172         kfree(tpr->rx_jmb_buffers);
6173         tpr->rx_jmb_buffers = NULL;
6174         if (tpr->rx_std) {
6175                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6176                                     tpr->rx_std, tpr->rx_std_mapping);
6177                 tpr->rx_std = NULL;
6178         }
6179         if (tpr->rx_jmb) {
6180                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6181                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6182                 tpr->rx_jmb = NULL;
6183         }
6184 }
6185
6186 static int tg3_rx_prodring_init(struct tg3 *tp,
6187                                 struct tg3_rx_prodring_set *tpr)
6188 {
6189         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6190         if (!tpr->rx_std_buffers)
6191                 return -ENOMEM;
6192
6193         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6194                                            &tpr->rx_std_mapping);
6195         if (!tpr->rx_std)
6196                 goto err_out;
6197
6198         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6199                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6200                                               GFP_KERNEL);
6201                 if (!tpr->rx_jmb_buffers)
6202                         goto err_out;
6203
6204                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6205                                                    TG3_RX_JUMBO_RING_BYTES,
6206                                                    &tpr->rx_jmb_mapping);
6207                 if (!tpr->rx_jmb)
6208                         goto err_out;
6209         }
6210
6211         return 0;
6212
6213 err_out:
6214         tg3_rx_prodring_fini(tp, tpr);
6215         return -ENOMEM;
6216 }
6217
6218 /* Free up pending packets in all rx/tx rings.
6219  *
6220  * The chip has been shut down and the driver detached from
6221  * the networking, so no interrupts or new tx packets will
6222  * end up in the driver.  tp->{tx,}lock is not held and we are not
6223  * in an interrupt context and thus may sleep.
6224  */
6225 static void tg3_free_rings(struct tg3 *tp)
6226 {
6227         int i, j;
6228
6229         for (j = 0; j < tp->irq_cnt; j++) {
6230                 struct tg3_napi *tnapi = &tp->napi[j];
6231
6232                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6233
6234                 if (!tnapi->tx_buffers)
6235                         continue;
6236
6237                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6238                         struct ring_info *txp;
6239                         struct sk_buff *skb;
6240                         unsigned int k;
6241
6242                         txp = &tnapi->tx_buffers[i];
6243                         skb = txp->skb;
6244
6245                         if (skb == NULL) {
6246                                 i++;
6247                                 continue;
6248                         }
6249
6250                         pci_unmap_single(tp->pdev,
6251                                          dma_unmap_addr(txp, mapping),
6252                                          skb_headlen(skb),
6253                                          PCI_DMA_TODEVICE);
6254                         txp->skb = NULL;
6255
6256                         i++;
6257
6258                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6259                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6260                                 pci_unmap_page(tp->pdev,
6261                                                dma_unmap_addr(txp, mapping),
6262                                                skb_shinfo(skb)->frags[k].size,
6263                                                PCI_DMA_TODEVICE);
6264                                 i++;
6265                         }
6266
6267                         dev_kfree_skb_any(skb);
6268                 }
6269         }
6270 }
6271
6272 /* Initialize tx/rx rings for packet processing.
6273  *
6274  * The chip has been shut down and the driver detached from
6275  * the networking, so no interrupts or new tx packets will
6276  * end up in the driver.  tp->{tx,}lock are held and thus
6277  * we may not sleep.
6278  */
6279 static int tg3_init_rings(struct tg3 *tp)
6280 {
6281         int i;
6282
6283         /* Free up all the SKBs. */
6284         tg3_free_rings(tp);
6285
6286         for (i = 0; i < tp->irq_cnt; i++) {
6287                 struct tg3_napi *tnapi = &tp->napi[i];
6288
6289                 tnapi->last_tag = 0;
6290                 tnapi->last_irq_tag = 0;
6291                 tnapi->hw_status->status = 0;
6292                 tnapi->hw_status->status_tag = 0;
6293                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6294
6295                 tnapi->tx_prod = 0;
6296                 tnapi->tx_cons = 0;
6297                 if (tnapi->tx_ring)
6298                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6299
6300                 tnapi->rx_rcb_ptr = 0;
6301                 if (tnapi->rx_rcb)
6302                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6303
6304                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6305                         tg3_free_rings(tp);
6306                         return -ENOMEM;
6307                 }
6308         }
6309
6310         return 0;
6311 }
6312
6313 /*
6314  * Must not be invoked with interrupt sources disabled and
6315  * the hardware shutdown down.
6316  */
6317 static void tg3_free_consistent(struct tg3 *tp)
6318 {
6319         int i;
6320
6321         for (i = 0; i < tp->irq_cnt; i++) {
6322                 struct tg3_napi *tnapi = &tp->napi[i];
6323
6324                 if (tnapi->tx_ring) {
6325                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6326                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6327                         tnapi->tx_ring = NULL;
6328                 }
6329
6330                 kfree(tnapi->tx_buffers);
6331                 tnapi->tx_buffers = NULL;
6332
6333                 if (tnapi->rx_rcb) {
6334                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6335                                             tnapi->rx_rcb,
6336                                             tnapi->rx_rcb_mapping);
6337                         tnapi->rx_rcb = NULL;
6338                 }
6339
6340                 if (tnapi->hw_status) {
6341                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6342                                             tnapi->hw_status,
6343                                             tnapi->status_mapping);
6344                         tnapi->hw_status = NULL;
6345                 }
6346         }
6347
6348         if (tp->hw_stats) {
6349                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6350                                     tp->hw_stats, tp->stats_mapping);
6351                 tp->hw_stats = NULL;
6352         }
6353
6354         for (i = 0; i < tp->irq_cnt; i++)
6355                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6356 }
6357
6358 /*
6359  * Must not be invoked with interrupt sources disabled and
6360  * the hardware shutdown down.  Can sleep.
6361  */
6362 static int tg3_alloc_consistent(struct tg3 *tp)
6363 {
6364         int i;
6365
6366         for (i = 0; i < tp->irq_cnt; i++) {
6367                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6368                         goto err_out;
6369         }
6370
6371         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6372                                             sizeof(struct tg3_hw_stats),
6373                                             &tp->stats_mapping);
6374         if (!tp->hw_stats)
6375                 goto err_out;
6376
6377         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6378
6379         for (i = 0; i < tp->irq_cnt; i++) {
6380                 struct tg3_napi *tnapi = &tp->napi[i];
6381                 struct tg3_hw_status *sblk;
6382
6383                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6384                                                         TG3_HW_STATUS_SIZE,
6385                                                         &tnapi->status_mapping);
6386                 if (!tnapi->hw_status)
6387                         goto err_out;
6388
6389                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6390                 sblk = tnapi->hw_status;
6391
6392                 /* If multivector TSS is enabled, vector 0 does not handle
6393                  * tx interrupts.  Don't allocate any resources for it.
6394                  */
6395                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6396                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6397                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6398                                                     TG3_TX_RING_SIZE,
6399                                                     GFP_KERNEL);
6400                         if (!tnapi->tx_buffers)
6401                                 goto err_out;
6402
6403                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6404                                                               TG3_TX_RING_BYTES,
6405                                                        &tnapi->tx_desc_mapping);
6406                         if (!tnapi->tx_ring)
6407                                 goto err_out;
6408                 }
6409
6410                 /*
6411                  * When RSS is enabled, the status block format changes
6412                  * slightly.  The "rx_jumbo_consumer", "reserved",
6413                  * and "rx_mini_consumer" members get mapped to the
6414                  * other three rx return ring producer indexes.
6415                  */
6416                 switch (i) {
6417                 default:
6418                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6419                         break;
6420                 case 2:
6421                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6422                         break;
6423                 case 3:
6424                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6425                         break;
6426                 case 4:
6427                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6428                         break;
6429                 }
6430
6431                 tnapi->prodring = &tp->prodring[i];
6432
6433                 /*
6434                  * If multivector RSS is enabled, vector 0 does not handle
6435                  * rx or tx interrupts.  Don't allocate any resources for it.
6436                  */
6437                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6438                         continue;
6439
6440                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6441                                                      TG3_RX_RCB_RING_BYTES(tp),
6442                                                      &tnapi->rx_rcb_mapping);
6443                 if (!tnapi->rx_rcb)
6444                         goto err_out;
6445
6446                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6447         }
6448
6449         return 0;
6450
6451 err_out:
6452         tg3_free_consistent(tp);
6453         return -ENOMEM;
6454 }
6455
6456 #define MAX_WAIT_CNT 1000
6457
6458 /* To stop a block, clear the enable bit and poll till it
6459  * clears.  tp->lock is held.
6460  */
6461 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6462 {
6463         unsigned int i;
6464         u32 val;
6465
6466         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6467                 switch (ofs) {
6468                 case RCVLSC_MODE:
6469                 case DMAC_MODE:
6470                 case MBFREE_MODE:
6471                 case BUFMGR_MODE:
6472                 case MEMARB_MODE:
6473                         /* We can't enable/disable these bits of the
6474                          * 5705/5750, just say success.
6475                          */
6476                         return 0;
6477
6478                 default:
6479                         break;
6480                 }
6481         }
6482
6483         val = tr32(ofs);
6484         val &= ~enable_bit;
6485         tw32_f(ofs, val);
6486
6487         for (i = 0; i < MAX_WAIT_CNT; i++) {
6488                 udelay(100);
6489                 val = tr32(ofs);
6490                 if ((val & enable_bit) == 0)
6491                         break;
6492         }
6493
6494         if (i == MAX_WAIT_CNT && !silent) {
6495                 dev_err(&tp->pdev->dev,
6496                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6497                         ofs, enable_bit);
6498                 return -ENODEV;
6499         }
6500
6501         return 0;
6502 }
6503
6504 /* tp->lock is held. */
6505 static int tg3_abort_hw(struct tg3 *tp, int silent)
6506 {
6507         int i, err;
6508
6509         tg3_disable_ints(tp);
6510
6511         tp->rx_mode &= ~RX_MODE_ENABLE;
6512         tw32_f(MAC_RX_MODE, tp->rx_mode);
6513         udelay(10);
6514
6515         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6516         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6517         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6518         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6519         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6521
6522         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6523         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6524         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6525         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6526         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6527         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6528         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6529
6530         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6531         tw32_f(MAC_MODE, tp->mac_mode);
6532         udelay(40);
6533
6534         tp->tx_mode &= ~TX_MODE_ENABLE;
6535         tw32_f(MAC_TX_MODE, tp->tx_mode);
6536
6537         for (i = 0; i < MAX_WAIT_CNT; i++) {
6538                 udelay(100);
6539                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6540                         break;
6541         }
6542         if (i >= MAX_WAIT_CNT) {
6543                 dev_err(&tp->pdev->dev,
6544                         "%s timed out, TX_MODE_ENABLE will not clear "
6545                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6546                 err |= -ENODEV;
6547         }
6548
6549         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6550         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6551         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6552
6553         tw32(FTQ_RESET, 0xffffffff);
6554         tw32(FTQ_RESET, 0x00000000);
6555
6556         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6557         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6558
6559         for (i = 0; i < tp->irq_cnt; i++) {
6560                 struct tg3_napi *tnapi = &tp->napi[i];
6561                 if (tnapi->hw_status)
6562                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6563         }
6564         if (tp->hw_stats)
6565                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6566
6567         return err;
6568 }
6569
6570 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6571 {
6572         int i;
6573         u32 apedata;
6574
6575         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6576         if (apedata != APE_SEG_SIG_MAGIC)
6577                 return;
6578
6579         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6580         if (!(apedata & APE_FW_STATUS_READY))
6581                 return;
6582
6583         /* Wait for up to 1 millisecond for APE to service previous event. */
6584         for (i = 0; i < 10; i++) {
6585                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6586                         return;
6587
6588                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6589
6590                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6591                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6592                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6593
6594                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6595
6596                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6597                         break;
6598
6599                 udelay(100);
6600         }
6601
6602         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6603                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6604 }
6605
6606 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6607 {
6608         u32 event;
6609         u32 apedata;
6610
6611         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6612                 return;
6613
6614         switch (kind) {
6615         case RESET_KIND_INIT:
6616                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6617                                 APE_HOST_SEG_SIG_MAGIC);
6618                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6619                                 APE_HOST_SEG_LEN_MAGIC);
6620                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6621                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6622                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6623                                 APE_HOST_DRIVER_ID_MAGIC);
6624                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6625                                 APE_HOST_BEHAV_NO_PHYLOCK);
6626
6627                 event = APE_EVENT_STATUS_STATE_START;
6628                 break;
6629         case RESET_KIND_SHUTDOWN:
6630                 /* With the interface we are currently using,
6631                  * APE does not track driver state.  Wiping
6632                  * out the HOST SEGMENT SIGNATURE forces
6633                  * the APE to assume OS absent status.
6634                  */
6635                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6636
6637                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6638                 break;
6639         case RESET_KIND_SUSPEND:
6640                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6641                 break;
6642         default:
6643                 return;
6644         }
6645
6646         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6647
6648         tg3_ape_send_event(tp, event);
6649 }
6650
6651 /* tp->lock is held. */
6652 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6653 {
6654         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6655                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6656
6657         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6658                 switch (kind) {
6659                 case RESET_KIND_INIT:
6660                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6661                                       DRV_STATE_START);
6662                         break;
6663
6664                 case RESET_KIND_SHUTDOWN:
6665                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6666                                       DRV_STATE_UNLOAD);
6667                         break;
6668
6669                 case RESET_KIND_SUSPEND:
6670                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6671                                       DRV_STATE_SUSPEND);
6672                         break;
6673
6674                 default:
6675                         break;
6676                 }
6677         }
6678
6679         if (kind == RESET_KIND_INIT ||
6680             kind == RESET_KIND_SUSPEND)
6681                 tg3_ape_driver_state_change(tp, kind);
6682 }
6683
6684 /* tp->lock is held. */
6685 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6686 {
6687         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6688                 switch (kind) {
6689                 case RESET_KIND_INIT:
6690                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6691                                       DRV_STATE_START_DONE);
6692                         break;
6693
6694                 case RESET_KIND_SHUTDOWN:
6695                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6696                                       DRV_STATE_UNLOAD_DONE);
6697                         break;
6698
6699                 default:
6700                         break;
6701                 }
6702         }
6703
6704         if (kind == RESET_KIND_SHUTDOWN)
6705                 tg3_ape_driver_state_change(tp, kind);
6706 }
6707
6708 /* tp->lock is held. */
6709 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6710 {
6711         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6712                 switch (kind) {
6713                 case RESET_KIND_INIT:
6714                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6715                                       DRV_STATE_START);
6716                         break;
6717
6718                 case RESET_KIND_SHUTDOWN:
6719                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6720                                       DRV_STATE_UNLOAD);
6721                         break;
6722
6723                 case RESET_KIND_SUSPEND:
6724                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6725                                       DRV_STATE_SUSPEND);
6726                         break;
6727
6728                 default:
6729                         break;
6730                 }
6731         }
6732 }
6733
6734 static int tg3_poll_fw(struct tg3 *tp)
6735 {
6736         int i;
6737         u32 val;
6738
6739         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6740                 /* Wait up to 20ms for init done. */
6741                 for (i = 0; i < 200; i++) {
6742                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6743                                 return 0;
6744                         udelay(100);
6745                 }
6746                 return -ENODEV;
6747         }
6748
6749         /* Wait for firmware initialization to complete. */
6750         for (i = 0; i < 100000; i++) {
6751                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6752                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6753                         break;
6754                 udelay(10);
6755         }
6756
6757         /* Chip might not be fitted with firmware.  Some Sun onboard
6758          * parts are configured like that.  So don't signal the timeout
6759          * of the above loop as an error, but do report the lack of
6760          * running firmware once.
6761          */
6762         if (i >= 100000 &&
6763             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6764                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6765
6766                 netdev_info(tp->dev, "No firmware running\n");
6767         }
6768
6769         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6770                 /* The 57765 A0 needs a little more
6771                  * time to do some important work.
6772                  */
6773                 mdelay(10);
6774         }
6775
6776         return 0;
6777 }
6778
6779 /* Save PCI command register before chip reset */
6780 static void tg3_save_pci_state(struct tg3 *tp)
6781 {
6782         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6783 }
6784
6785 /* Restore PCI state after chip reset */
6786 static void tg3_restore_pci_state(struct tg3 *tp)
6787 {
6788         u32 val;
6789
6790         /* Re-enable indirect register accesses. */
6791         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6792                                tp->misc_host_ctrl);
6793
6794         /* Set MAX PCI retry to zero. */
6795         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6796         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6797             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6798                 val |= PCISTATE_RETRY_SAME_DMA;
6799         /* Allow reads and writes to the APE register and memory space. */
6800         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6801                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6802                        PCISTATE_ALLOW_APE_SHMEM_WR |
6803                        PCISTATE_ALLOW_APE_PSPACE_WR;
6804         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6805
6806         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6807
6808         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6809                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6810                         pcie_set_readrq(tp->pdev, 4096);
6811                 else {
6812                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6813                                               tp->pci_cacheline_sz);
6814                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6815                                               tp->pci_lat_timer);
6816                 }
6817         }
6818
6819         /* Make sure PCI-X relaxed ordering bit is clear. */
6820         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6821                 u16 pcix_cmd;
6822
6823                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6824                                      &pcix_cmd);
6825                 pcix_cmd &= ~PCI_X_CMD_ERO;
6826                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6827                                       pcix_cmd);
6828         }
6829
6830         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6831
6832                 /* Chip reset on 5780 will reset MSI enable bit,
6833                  * so need to restore it.
6834                  */
6835                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6836                         u16 ctrl;
6837
6838                         pci_read_config_word(tp->pdev,
6839                                              tp->msi_cap + PCI_MSI_FLAGS,
6840                                              &ctrl);
6841                         pci_write_config_word(tp->pdev,
6842                                               tp->msi_cap + PCI_MSI_FLAGS,
6843                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6844                         val = tr32(MSGINT_MODE);
6845                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6846                 }
6847         }
6848 }
6849
6850 static void tg3_stop_fw(struct tg3 *);
6851
6852 /* tp->lock is held. */
6853 static int tg3_chip_reset(struct tg3 *tp)
6854 {
6855         u32 val;
6856         void (*write_op)(struct tg3 *, u32, u32);
6857         int i, err;
6858
6859         tg3_nvram_lock(tp);
6860
6861         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6862
6863         /* No matching tg3_nvram_unlock() after this because
6864          * chip reset below will undo the nvram lock.
6865          */
6866         tp->nvram_lock_cnt = 0;
6867
6868         /* GRC_MISC_CFG core clock reset will clear the memory
6869          * enable bit in PCI register 4 and the MSI enable bit
6870          * on some chips, so we save relevant registers here.
6871          */
6872         tg3_save_pci_state(tp);
6873
6874         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6875             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6876                 tw32(GRC_FASTBOOT_PC, 0);
6877
6878         /*
6879          * We must avoid the readl() that normally takes place.
6880          * It locks machines, causes machine checks, and other
6881          * fun things.  So, temporarily disable the 5701
6882          * hardware workaround, while we do the reset.
6883          */
6884         write_op = tp->write32;
6885         if (write_op == tg3_write_flush_reg32)
6886                 tp->write32 = tg3_write32;
6887
6888         /* Prevent the irq handler from reading or writing PCI registers
6889          * during chip reset when the memory enable bit in the PCI command
6890          * register may be cleared.  The chip does not generate interrupt
6891          * at this time, but the irq handler may still be called due to irq
6892          * sharing or irqpoll.
6893          */
6894         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6895         for (i = 0; i < tp->irq_cnt; i++) {
6896                 struct tg3_napi *tnapi = &tp->napi[i];
6897                 if (tnapi->hw_status) {
6898                         tnapi->hw_status->status = 0;
6899                         tnapi->hw_status->status_tag = 0;
6900                 }
6901                 tnapi->last_tag = 0;
6902                 tnapi->last_irq_tag = 0;
6903         }
6904         smp_mb();
6905
6906         for (i = 0; i < tp->irq_cnt; i++)
6907                 synchronize_irq(tp->napi[i].irq_vec);
6908
6909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6910                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6911                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6912         }
6913
6914         /* do the reset */
6915         val = GRC_MISC_CFG_CORECLK_RESET;
6916
6917         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6918                 if (tr32(0x7e2c) == 0x60) {
6919                         tw32(0x7e2c, 0x20);
6920                 }
6921                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6922                         tw32(GRC_MISC_CFG, (1 << 29));
6923                         val |= (1 << 29);
6924                 }
6925         }
6926
6927         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6928                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6929                 tw32(GRC_VCPU_EXT_CTRL,
6930                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6931         }
6932
6933         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6934                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6935         tw32(GRC_MISC_CFG, val);
6936
6937         /* restore 5701 hardware bug workaround write method */
6938         tp->write32 = write_op;
6939
6940         /* Unfortunately, we have to delay before the PCI read back.
6941          * Some 575X chips even will not respond to a PCI cfg access
6942          * when the reset command is given to the chip.
6943          *
6944          * How do these hardware designers expect things to work
6945          * properly if the PCI write is posted for a long period
6946          * of time?  It is always necessary to have some method by
6947          * which a register read back can occur to push the write
6948          * out which does the reset.
6949          *
6950          * For most tg3 variants the trick below was working.
6951          * Ho hum...
6952          */
6953         udelay(120);
6954
6955         /* Flush PCI posted writes.  The normal MMIO registers
6956          * are inaccessible at this time so this is the only
6957          * way to make this reliably (actually, this is no longer
6958          * the case, see above).  I tried to use indirect
6959          * register read/write but this upset some 5701 variants.
6960          */
6961         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6962
6963         udelay(120);
6964
6965         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6966                 u16 val16;
6967
6968                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6969                         int i;
6970                         u32 cfg_val;
6971
6972                         /* Wait for link training to complete.  */
6973                         for (i = 0; i < 5000; i++)
6974                                 udelay(100);
6975
6976                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6977                         pci_write_config_dword(tp->pdev, 0xc4,
6978                                                cfg_val | (1 << 15));
6979                 }
6980
6981                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6982                 pci_read_config_word(tp->pdev,
6983                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6984                                      &val16);
6985                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6986                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6987                 /*
6988                  * Older PCIe devices only support the 128 byte
6989                  * MPS setting.  Enforce the restriction.
6990                  */
6991                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6992                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6993                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6994                 pci_write_config_word(tp->pdev,
6995                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6996                                       val16);
6997
6998                 pcie_set_readrq(tp->pdev, 4096);
6999
7000                 /* Clear error status */
7001                 pci_write_config_word(tp->pdev,
7002                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7003                                       PCI_EXP_DEVSTA_CED |
7004                                       PCI_EXP_DEVSTA_NFED |
7005                                       PCI_EXP_DEVSTA_FED |
7006                                       PCI_EXP_DEVSTA_URD);
7007         }
7008
7009         tg3_restore_pci_state(tp);
7010
7011         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7012
7013         val = 0;
7014         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7015                 val = tr32(MEMARB_MODE);
7016         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7017
7018         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7019                 tg3_stop_fw(tp);
7020                 tw32(0x5000, 0x400);
7021         }
7022
7023         tw32(GRC_MODE, tp->grc_mode);
7024
7025         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7026                 val = tr32(0xc4);
7027
7028                 tw32(0xc4, val | (1 << 15));
7029         }
7030
7031         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7032             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7033                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7034                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7035                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7036                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7037         }
7038
7039         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7040                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7041                 tw32_f(MAC_MODE, tp->mac_mode);
7042         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7043                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7044                 tw32_f(MAC_MODE, tp->mac_mode);
7045         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7046                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7047                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7048                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7049                 tw32_f(MAC_MODE, tp->mac_mode);
7050         } else
7051                 tw32_f(MAC_MODE, 0);
7052         udelay(40);
7053
7054         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7055
7056         err = tg3_poll_fw(tp);
7057         if (err)
7058                 return err;
7059
7060         tg3_mdio_start(tp);
7061
7062         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7063                 u8 phy_addr;
7064
7065                 phy_addr = tp->phy_addr;
7066                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7067
7068                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7069                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7070                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7071                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7072                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7073                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7074                 udelay(10);
7075
7076                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7077                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7078                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7079                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7080                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7081                 udelay(10);
7082
7083                 tp->phy_addr = phy_addr;
7084         }
7085
7086         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7087             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7088             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7089             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7090             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7091                 val = tr32(0x7c00);
7092
7093                 tw32(0x7c00, val | (1 << 25));
7094         }
7095
7096         /* Reprobe ASF enable state.  */
7097         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7098         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7099         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7100         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7101                 u32 nic_cfg;
7102
7103                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7104                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7105                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7106                         tp->last_event_jiffies = jiffies;
7107                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7108                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7109                 }
7110         }
7111
7112         return 0;
7113 }
7114
7115 /* tp->lock is held. */
7116 static void tg3_stop_fw(struct tg3 *tp)
7117 {
7118         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7119            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7120                 /* Wait for RX cpu to ACK the previous event. */
7121                 tg3_wait_for_event_ack(tp);
7122
7123                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7124
7125                 tg3_generate_fw_event(tp);
7126
7127                 /* Wait for RX cpu to ACK this event. */
7128                 tg3_wait_for_event_ack(tp);
7129         }
7130 }
7131
7132 /* tp->lock is held. */
7133 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7134 {
7135         int err;
7136
7137         tg3_stop_fw(tp);
7138
7139         tg3_write_sig_pre_reset(tp, kind);
7140
7141         tg3_abort_hw(tp, silent);
7142         err = tg3_chip_reset(tp);
7143
7144         __tg3_set_mac_addr(tp, 0);
7145
7146         tg3_write_sig_legacy(tp, kind);
7147         tg3_write_sig_post_reset(tp, kind);
7148
7149         if (err)
7150                 return err;
7151
7152         return 0;
7153 }
7154
7155 #define RX_CPU_SCRATCH_BASE     0x30000
7156 #define RX_CPU_SCRATCH_SIZE     0x04000
7157 #define TX_CPU_SCRATCH_BASE     0x34000
7158 #define TX_CPU_SCRATCH_SIZE     0x04000
7159
7160 /* tp->lock is held. */
7161 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7162 {
7163         int i;
7164
7165         BUG_ON(offset == TX_CPU_BASE &&
7166             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7167
7168         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7169                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7170
7171                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7172                 return 0;
7173         }
7174         if (offset == RX_CPU_BASE) {
7175                 for (i = 0; i < 10000; i++) {
7176                         tw32(offset + CPU_STATE, 0xffffffff);
7177                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7178                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7179                                 break;
7180                 }
7181
7182                 tw32(offset + CPU_STATE, 0xffffffff);
7183                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7184                 udelay(10);
7185         } else {
7186                 for (i = 0; i < 10000; i++) {
7187                         tw32(offset + CPU_STATE, 0xffffffff);
7188                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7189                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7190                                 break;
7191                 }
7192         }
7193
7194         if (i >= 10000) {
7195                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7196                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7197                 return -ENODEV;
7198         }
7199
7200         /* Clear firmware's nvram arbitration. */
7201         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7202                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7203         return 0;
7204 }
7205
7206 struct fw_info {
7207         unsigned int fw_base;
7208         unsigned int fw_len;
7209         const __be32 *fw_data;
7210 };
7211
7212 /* tp->lock is held. */
7213 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7214                                  int cpu_scratch_size, struct fw_info *info)
7215 {
7216         int err, lock_err, i;
7217         void (*write_op)(struct tg3 *, u32, u32);
7218
7219         if (cpu_base == TX_CPU_BASE &&
7220             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7221                 netdev_err(tp->dev,
7222                            "%s: Trying to load TX cpu firmware which is 5705\n",
7223                            __func__);
7224                 return -EINVAL;
7225         }
7226
7227         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7228                 write_op = tg3_write_mem;
7229         else
7230                 write_op = tg3_write_indirect_reg32;
7231
7232         /* It is possible that bootcode is still loading at this point.
7233          * Get the nvram lock first before halting the cpu.
7234          */
7235         lock_err = tg3_nvram_lock(tp);
7236         err = tg3_halt_cpu(tp, cpu_base);
7237         if (!lock_err)
7238                 tg3_nvram_unlock(tp);
7239         if (err)
7240                 goto out;
7241
7242         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7243                 write_op(tp, cpu_scratch_base + i, 0);
7244         tw32(cpu_base + CPU_STATE, 0xffffffff);
7245         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7246         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7247                 write_op(tp, (cpu_scratch_base +
7248                               (info->fw_base & 0xffff) +
7249                               (i * sizeof(u32))),
7250                               be32_to_cpu(info->fw_data[i]));
7251
7252         err = 0;
7253
7254 out:
7255         return err;
7256 }
7257
7258 /* tp->lock is held. */
7259 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7260 {
7261         struct fw_info info;
7262         const __be32 *fw_data;
7263         int err, i;
7264
7265         fw_data = (void *)tp->fw->data;
7266
7267         /* Firmware blob starts with version numbers, followed by
7268            start address and length. We are setting complete length.
7269            length = end_address_of_bss - start_address_of_text.
7270            Remainder is the blob to be loaded contiguously
7271            from start address. */
7272
7273         info.fw_base = be32_to_cpu(fw_data[1]);
7274         info.fw_len = tp->fw->size - 12;
7275         info.fw_data = &fw_data[3];
7276
7277         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7278                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7279                                     &info);
7280         if (err)
7281                 return err;
7282
7283         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7284                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7285                                     &info);
7286         if (err)
7287                 return err;
7288
7289         /* Now startup only the RX cpu. */
7290         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7291         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7292
7293         for (i = 0; i < 5; i++) {
7294                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7295                         break;
7296                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7297                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7298                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7299                 udelay(1000);
7300         }
7301         if (i >= 5) {
7302                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7303                            "should be %08x\n", __func__,
7304                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7305                 return -ENODEV;
7306         }
7307         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7308         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7309
7310         return 0;
7311 }
7312
7313 /* 5705 needs a special version of the TSO firmware.  */
7314
7315 /* tp->lock is held. */
7316 static int tg3_load_tso_firmware(struct tg3 *tp)
7317 {
7318         struct fw_info info;
7319         const __be32 *fw_data;
7320         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7321         int err, i;
7322
7323         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7324                 return 0;
7325
7326         fw_data = (void *)tp->fw->data;
7327
7328         /* Firmware blob starts with version numbers, followed by
7329            start address and length. We are setting complete length.
7330            length = end_address_of_bss - start_address_of_text.
7331            Remainder is the blob to be loaded contiguously
7332            from start address. */
7333
7334         info.fw_base = be32_to_cpu(fw_data[1]);
7335         cpu_scratch_size = tp->fw_len;
7336         info.fw_len = tp->fw->size - 12;
7337         info.fw_data = &fw_data[3];
7338
7339         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7340                 cpu_base = RX_CPU_BASE;
7341                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7342         } else {
7343                 cpu_base = TX_CPU_BASE;
7344                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7345                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7346         }
7347
7348         err = tg3_load_firmware_cpu(tp, cpu_base,
7349                                     cpu_scratch_base, cpu_scratch_size,
7350                                     &info);
7351         if (err)
7352                 return err;
7353
7354         /* Now startup the cpu. */
7355         tw32(cpu_base + CPU_STATE, 0xffffffff);
7356         tw32_f(cpu_base + CPU_PC, info.fw_base);
7357
7358         for (i = 0; i < 5; i++) {
7359                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7360                         break;
7361                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7362                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7363                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7364                 udelay(1000);
7365         }
7366         if (i >= 5) {
7367                 netdev_err(tp->dev,
7368                            "%s fails to set CPU PC, is %08x should be %08x\n",
7369                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7370                 return -ENODEV;
7371         }
7372         tw32(cpu_base + CPU_STATE, 0xffffffff);
7373         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7374         return 0;
7375 }
7376
7377
7378 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7379 {
7380         struct tg3 *tp = netdev_priv(dev);
7381         struct sockaddr *addr = p;
7382         int err = 0, skip_mac_1 = 0;
7383
7384         if (!is_valid_ether_addr(addr->sa_data))
7385                 return -EINVAL;
7386
7387         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7388
7389         if (!netif_running(dev))
7390                 return 0;
7391
7392         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7393                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7394
7395                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7396                 addr0_low = tr32(MAC_ADDR_0_LOW);
7397                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7398                 addr1_low = tr32(MAC_ADDR_1_LOW);
7399
7400                 /* Skip MAC addr 1 if ASF is using it. */
7401                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7402                     !(addr1_high == 0 && addr1_low == 0))
7403                         skip_mac_1 = 1;
7404         }
7405         spin_lock_bh(&tp->lock);
7406         __tg3_set_mac_addr(tp, skip_mac_1);
7407         spin_unlock_bh(&tp->lock);
7408
7409         return err;
7410 }
7411
7412 /* tp->lock is held. */
7413 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7414                            dma_addr_t mapping, u32 maxlen_flags,
7415                            u32 nic_addr)
7416 {
7417         tg3_write_mem(tp,
7418                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7419                       ((u64) mapping >> 32));
7420         tg3_write_mem(tp,
7421                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7422                       ((u64) mapping & 0xffffffff));
7423         tg3_write_mem(tp,
7424                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7425                        maxlen_flags);
7426
7427         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7428                 tg3_write_mem(tp,
7429                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7430                               nic_addr);
7431 }
7432
7433 static void __tg3_set_rx_mode(struct net_device *);
7434 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7435 {
7436         int i;
7437
7438         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7439                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7440                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7441                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7442         } else {
7443                 tw32(HOSTCC_TXCOL_TICKS, 0);
7444                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7445                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7446         }
7447
7448         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7449                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7450                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7451                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7452         } else {
7453                 tw32(HOSTCC_RXCOL_TICKS, 0);
7454                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7455                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7456         }
7457
7458         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7459                 u32 val = ec->stats_block_coalesce_usecs;
7460
7461                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7462                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7463
7464                 if (!netif_carrier_ok(tp->dev))
7465                         val = 0;
7466
7467                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7468         }
7469
7470         for (i = 0; i < tp->irq_cnt - 1; i++) {
7471                 u32 reg;
7472
7473                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7474                 tw32(reg, ec->rx_coalesce_usecs);
7475                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7476                 tw32(reg, ec->rx_max_coalesced_frames);
7477                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7478                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7479
7480                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7481                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7482                         tw32(reg, ec->tx_coalesce_usecs);
7483                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7484                         tw32(reg, ec->tx_max_coalesced_frames);
7485                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7486                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7487                 }
7488         }
7489
7490         for (; i < tp->irq_max - 1; i++) {
7491                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7492                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7493                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7494
7495                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7496                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7497                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7498                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7499                 }
7500         }
7501 }
7502
7503 /* tp->lock is held. */
7504 static void tg3_rings_reset(struct tg3 *tp)
7505 {
7506         int i;
7507         u32 stblk, txrcb, rxrcb, limit;
7508         struct tg3_napi *tnapi = &tp->napi[0];
7509
7510         /* Disable all transmit rings but the first. */
7511         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7512                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7513         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7514                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7515         else
7516                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7517
7518         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7519              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7520                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7521                               BDINFO_FLAGS_DISABLED);
7522
7523
7524         /* Disable all receive return rings but the first. */
7525         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7526                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7527         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7528                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7530                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7531                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7532         else
7533                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7534
7535         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7536              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7537                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7538                               BDINFO_FLAGS_DISABLED);
7539
7540         /* Disable interrupts */
7541         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7542
7543         /* Zero mailbox registers. */
7544         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7545                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7546                         tp->napi[i].tx_prod = 0;
7547                         tp->napi[i].tx_cons = 0;
7548                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7549                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7550                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7551                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7552                 }
7553                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7554                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7555         } else {
7556                 tp->napi[0].tx_prod = 0;
7557                 tp->napi[0].tx_cons = 0;
7558                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7559                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7560         }
7561
7562         /* Make sure the NIC-based send BD rings are disabled. */
7563         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7564                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7565                 for (i = 0; i < 16; i++)
7566                         tw32_tx_mbox(mbox + i * 8, 0);
7567         }
7568
7569         txrcb = NIC_SRAM_SEND_RCB;
7570         rxrcb = NIC_SRAM_RCV_RET_RCB;
7571
7572         /* Clear status block in ram. */
7573         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7574
7575         /* Set status block DMA address */
7576         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7577              ((u64) tnapi->status_mapping >> 32));
7578         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7579              ((u64) tnapi->status_mapping & 0xffffffff));
7580
7581         if (tnapi->tx_ring) {
7582                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7583                                (TG3_TX_RING_SIZE <<
7584                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7585                                NIC_SRAM_TX_BUFFER_DESC);
7586                 txrcb += TG3_BDINFO_SIZE;
7587         }
7588
7589         if (tnapi->rx_rcb) {
7590                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7591                                (TG3_RX_RCB_RING_SIZE(tp) <<
7592                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7593                 rxrcb += TG3_BDINFO_SIZE;
7594         }
7595
7596         stblk = HOSTCC_STATBLCK_RING1;
7597
7598         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7599                 u64 mapping = (u64)tnapi->status_mapping;
7600                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7601                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7602
7603                 /* Clear status block in ram. */
7604                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7605
7606                 if (tnapi->tx_ring) {
7607                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7608                                        (TG3_TX_RING_SIZE <<
7609                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7610                                        NIC_SRAM_TX_BUFFER_DESC);
7611                         txrcb += TG3_BDINFO_SIZE;
7612                 }
7613
7614                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7615                                (TG3_RX_RCB_RING_SIZE(tp) <<
7616                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7617
7618                 stblk += 8;
7619                 rxrcb += TG3_BDINFO_SIZE;
7620         }
7621 }
7622
7623 /* tp->lock is held. */
7624 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7625 {
7626         u32 val, rdmac_mode;
7627         int i, err, limit;
7628         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7629
7630         tg3_disable_ints(tp);
7631
7632         tg3_stop_fw(tp);
7633
7634         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7635
7636         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7637                 tg3_abort_hw(tp, 1);
7638
7639         if (reset_phy)
7640                 tg3_phy_reset(tp);
7641
7642         err = tg3_chip_reset(tp);
7643         if (err)
7644                 return err;
7645
7646         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7647
7648         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7649                 val = tr32(TG3_CPMU_CTRL);
7650                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7651                 tw32(TG3_CPMU_CTRL, val);
7652
7653                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7654                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7655                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7656                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7657
7658                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7659                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7660                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7661                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7662
7663                 val = tr32(TG3_CPMU_HST_ACC);
7664                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7665                 val |= CPMU_HST_ACC_MACCLK_6_25;
7666                 tw32(TG3_CPMU_HST_ACC, val);
7667         }
7668
7669         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7670                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7671                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7672                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7673                 tw32(PCIE_PWR_MGMT_THRESH, val);
7674
7675                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7676                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7677
7678                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7679
7680                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7681                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7682         }
7683
7684         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7685                 u32 grc_mode = tr32(GRC_MODE);
7686
7687                 /* Access the lower 1K of PL PCIE block registers. */
7688                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7689                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7690
7691                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7692                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7693                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7694
7695                 tw32(GRC_MODE, grc_mode);
7696         }
7697
7698         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7699                 u32 grc_mode = tr32(GRC_MODE);
7700
7701                 /* Access the lower 1K of PL PCIE block registers. */
7702                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7703                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7704
7705                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7706                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7707                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7708
7709                 tw32(GRC_MODE, grc_mode);
7710
7711                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7712                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7713                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7714                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7715         }
7716
7717         /* This works around an issue with Athlon chipsets on
7718          * B3 tigon3 silicon.  This bit has no effect on any
7719          * other revision.  But do not set this on PCI Express
7720          * chips and don't even touch the clocks if the CPMU is present.
7721          */
7722         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7723                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7724                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7725                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7726         }
7727
7728         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7729             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7730                 val = tr32(TG3PCI_PCISTATE);
7731                 val |= PCISTATE_RETRY_SAME_DMA;
7732                 tw32(TG3PCI_PCISTATE, val);
7733         }
7734
7735         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7736                 /* Allow reads and writes to the
7737                  * APE register and memory space.
7738                  */
7739                 val = tr32(TG3PCI_PCISTATE);
7740                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7741                        PCISTATE_ALLOW_APE_SHMEM_WR |
7742                        PCISTATE_ALLOW_APE_PSPACE_WR;
7743                 tw32(TG3PCI_PCISTATE, val);
7744         }
7745
7746         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7747                 /* Enable some hw fixes.  */
7748                 val = tr32(TG3PCI_MSI_DATA);
7749                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7750                 tw32(TG3PCI_MSI_DATA, val);
7751         }
7752
7753         /* Descriptor ring init may make accesses to the
7754          * NIC SRAM area to setup the TX descriptors, so we
7755          * can only do this after the hardware has been
7756          * successfully reset.
7757          */
7758         err = tg3_init_rings(tp);
7759         if (err)
7760                 return err;
7761
7762         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7763             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7764                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7765                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7766                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7767                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7768                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7769         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7770                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7771                 /* This value is determined during the probe time DMA
7772                  * engine test, tg3_test_dma.
7773                  */
7774                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7775         }
7776
7777         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7778                           GRC_MODE_4X_NIC_SEND_RINGS |
7779                           GRC_MODE_NO_TX_PHDR_CSUM |
7780                           GRC_MODE_NO_RX_PHDR_CSUM);
7781         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7782
7783         /* Pseudo-header checksum is done by hardware logic and not
7784          * the offload processers, so make the chip do the pseudo-
7785          * header checksums on receive.  For transmit it is more
7786          * convenient to do the pseudo-header checksum in software
7787          * as Linux does that on transmit for us in all cases.
7788          */
7789         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7790
7791         tw32(GRC_MODE,
7792              tp->grc_mode |
7793              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7794
7795         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7796         val = tr32(GRC_MISC_CFG);
7797         val &= ~0xff;
7798         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7799         tw32(GRC_MISC_CFG, val);
7800
7801         /* Initialize MBUF/DESC pool. */
7802         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7803                 /* Do nothing.  */
7804         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7805                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7806                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7807                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7808                 else
7809                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7810                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7811                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7812         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7813                 int fw_len;
7814
7815                 fw_len = tp->fw_len;
7816                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7817                 tw32(BUFMGR_MB_POOL_ADDR,
7818                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7819                 tw32(BUFMGR_MB_POOL_SIZE,
7820                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7821         }
7822
7823         if (tp->dev->mtu <= ETH_DATA_LEN) {
7824                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7825                      tp->bufmgr_config.mbuf_read_dma_low_water);
7826                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7827                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7828                 tw32(BUFMGR_MB_HIGH_WATER,
7829                      tp->bufmgr_config.mbuf_high_water);
7830         } else {
7831                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7832                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7833                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7834                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7835                 tw32(BUFMGR_MB_HIGH_WATER,
7836                      tp->bufmgr_config.mbuf_high_water_jumbo);
7837         }
7838         tw32(BUFMGR_DMA_LOW_WATER,
7839              tp->bufmgr_config.dma_low_water);
7840         tw32(BUFMGR_DMA_HIGH_WATER,
7841              tp->bufmgr_config.dma_high_water);
7842
7843         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7844         for (i = 0; i < 2000; i++) {
7845                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7846                         break;
7847                 udelay(10);
7848         }
7849         if (i >= 2000) {
7850                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7851                 return -ENODEV;
7852         }
7853
7854         /* Setup replenish threshold. */
7855         val = tp->rx_pending / 8;
7856         if (val == 0)
7857                 val = 1;
7858         else if (val > tp->rx_std_max_post)
7859                 val = tp->rx_std_max_post;
7860         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7861                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7862                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7863
7864                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7865                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7866         }
7867
7868         tw32(RCVBDI_STD_THRESH, val);
7869
7870         /* Initialize TG3_BDINFO's at:
7871          *  RCVDBDI_STD_BD:     standard eth size rx ring
7872          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7873          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7874          *
7875          * like so:
7876          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7877          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7878          *                              ring attribute flags
7879          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7880          *
7881          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7882          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7883          *
7884          * The size of each ring is fixed in the firmware, but the location is
7885          * configurable.
7886          */
7887         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7888              ((u64) tpr->rx_std_mapping >> 32));
7889         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7890              ((u64) tpr->rx_std_mapping & 0xffffffff));
7891         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7892                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7893                      NIC_SRAM_RX_BUFFER_DESC);
7894
7895         /* Disable the mini ring */
7896         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7897                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7898                      BDINFO_FLAGS_DISABLED);
7899
7900         /* Program the jumbo buffer descriptor ring control
7901          * blocks on those devices that have them.
7902          */
7903         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7904             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7905                 /* Setup replenish threshold. */
7906                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7907
7908                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7909                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7910                              ((u64) tpr->rx_jmb_mapping >> 32));
7911                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7912                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7913                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7914                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7915                              BDINFO_FLAGS_USE_EXT_RECV);
7916                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7917                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7918                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7919                 } else {
7920                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7921                              BDINFO_FLAGS_DISABLED);
7922                 }
7923
7924                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7925                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7926                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7927                               (TG3_RX_STD_DMA_SZ << 2);
7928                 else
7929                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7930         } else
7931                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7932
7933         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7934
7935         tpr->rx_std_prod_idx = tp->rx_pending;
7936         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7937
7938         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7939                           tp->rx_jumbo_pending : 0;
7940         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7941
7942         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7943             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7944                 tw32(STD_REPLENISH_LWM, 32);
7945                 tw32(JMB_REPLENISH_LWM, 16);
7946         }
7947
7948         tg3_rings_reset(tp);
7949
7950         /* Initialize MAC address and backoff seed. */
7951         __tg3_set_mac_addr(tp, 0);
7952
7953         /* MTU + ethernet header + FCS + optional VLAN tag */
7954         tw32(MAC_RX_MTU_SIZE,
7955              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7956
7957         /* The slot time is changed by tg3_setup_phy if we
7958          * run at gigabit with half duplex.
7959          */
7960         tw32(MAC_TX_LENGTHS,
7961              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7962              (6 << TX_LENGTHS_IPG_SHIFT) |
7963              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7964
7965         /* Receive rules. */
7966         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7967         tw32(RCVLPC_CONFIG, 0x0181);
7968
7969         /* Calculate RDMAC_MODE setting early, we need it to determine
7970          * the RCVLPC_STATE_ENABLE mask.
7971          */
7972         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7973                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7974                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7975                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7976                       RDMAC_MODE_LNGREAD_ENAB);
7977
7978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7979                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7980
7981         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7982             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7984                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7985                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7986                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7987
7988         /* If statement applies to 5705 and 5750 PCI devices only */
7989         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7990              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7991             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7992                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7993                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7994                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7995                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7996                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7997                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7998                 }
7999         }
8000
8001         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8002                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8003
8004         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8005                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8006
8007         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8008             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8010                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8011
8012         /* Receive/send statistics. */
8013         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8014                 val = tr32(RCVLPC_STATS_ENABLE);
8015                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8016                 tw32(RCVLPC_STATS_ENABLE, val);
8017         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8018                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8019                 val = tr32(RCVLPC_STATS_ENABLE);
8020                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8021                 tw32(RCVLPC_STATS_ENABLE, val);
8022         } else {
8023                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8024         }
8025         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8026         tw32(SNDDATAI_STATSENAB, 0xffffff);
8027         tw32(SNDDATAI_STATSCTRL,
8028              (SNDDATAI_SCTRL_ENABLE |
8029               SNDDATAI_SCTRL_FASTUPD));
8030
8031         /* Setup host coalescing engine. */
8032         tw32(HOSTCC_MODE, 0);
8033         for (i = 0; i < 2000; i++) {
8034                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8035                         break;
8036                 udelay(10);
8037         }
8038
8039         __tg3_set_coalesce(tp, &tp->coal);
8040
8041         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8042                 /* Status/statistics block address.  See tg3_timer,
8043                  * the tg3_periodic_fetch_stats call there, and
8044                  * tg3_get_stats to see how this works for 5705/5750 chips.
8045                  */
8046                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8047                      ((u64) tp->stats_mapping >> 32));
8048                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8049                      ((u64) tp->stats_mapping & 0xffffffff));
8050                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8051
8052                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8053
8054                 /* Clear statistics and status block memory areas */
8055                 for (i = NIC_SRAM_STATS_BLK;
8056                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8057                      i += sizeof(u32)) {
8058                         tg3_write_mem(tp, i, 0);
8059                         udelay(40);
8060                 }
8061         }
8062
8063         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8064
8065         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8066         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8067         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8068                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8069
8070         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8071                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8072                 /* reset to prevent losing 1st rx packet intermittently */
8073                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8074                 udelay(10);
8075         }
8076
8077         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8078                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8079         else
8080                 tp->mac_mode = 0;
8081         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8082                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8083         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8084             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8085             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8086                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8087         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8088         udelay(40);
8089
8090         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8091          * If TG3_FLG2_IS_NIC is zero, we should read the
8092          * register to preserve the GPIO settings for LOMs. The GPIOs,
8093          * whether used as inputs or outputs, are set by boot code after
8094          * reset.
8095          */
8096         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8097                 u32 gpio_mask;
8098
8099                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8100                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8101                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8102
8103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8104                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8105                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8106
8107                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8108                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8109
8110                 tp->grc_local_ctrl &= ~gpio_mask;
8111                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8112
8113                 /* GPIO1 must be driven high for eeprom write protect */
8114                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8115                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8116                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8117         }
8118         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8119         udelay(100);
8120
8121         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8122                 val = tr32(MSGINT_MODE);
8123                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8124                 tw32(MSGINT_MODE, val);
8125         }
8126
8127         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8128                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8129                 udelay(40);
8130         }
8131
8132         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8133                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8134                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8135                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8136                WDMAC_MODE_LNGREAD_ENAB);
8137
8138         /* If statement applies to 5705 and 5750 PCI devices only */
8139         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8140              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8141             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8142                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8143                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8144                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8145                         /* nothing */
8146                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8147                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8148                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8149                         val |= WDMAC_MODE_RX_ACCEL;
8150                 }
8151         }
8152
8153         /* Enable host coalescing bug fix */
8154         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8155                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8156
8157         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8158                 val |= WDMAC_MODE_BURST_ALL_DATA;
8159
8160         tw32_f(WDMAC_MODE, val);
8161         udelay(40);
8162
8163         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8164                 u16 pcix_cmd;
8165
8166                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8167                                      &pcix_cmd);
8168                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8169                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8170                         pcix_cmd |= PCI_X_CMD_READ_2K;
8171                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8172                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8173                         pcix_cmd |= PCI_X_CMD_READ_2K;
8174                 }
8175                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8176                                       pcix_cmd);
8177         }
8178
8179         tw32_f(RDMAC_MODE, rdmac_mode);
8180         udelay(40);
8181
8182         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8183         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8184                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8185
8186         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8187                 tw32(SNDDATAC_MODE,
8188                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8189         else
8190                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8191
8192         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8193         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8194         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8195         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8196         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8197                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8198         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8199         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8200                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8201         tw32(SNDBDI_MODE, val);
8202         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8203
8204         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8205                 err = tg3_load_5701_a0_firmware_fix(tp);
8206                 if (err)
8207                         return err;
8208         }
8209
8210         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8211                 err = tg3_load_tso_firmware(tp);
8212                 if (err)
8213                         return err;
8214         }
8215
8216         tp->tx_mode = TX_MODE_ENABLE;
8217         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8218             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8219                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8220         tw32_f(MAC_TX_MODE, tp->tx_mode);
8221         udelay(100);
8222
8223         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8224                 u32 reg = MAC_RSS_INDIR_TBL_0;
8225                 u8 *ent = (u8 *)&val;
8226
8227                 /* Setup the indirection table */
8228                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8229                         int idx = i % sizeof(val);
8230
8231                         ent[idx] = (i % (tp->irq_cnt - 1)) + 1;
8232                         if (idx == sizeof(val) - 1) {
8233                                 tw32(reg, val);
8234                                 reg += 4;
8235                         }
8236                 }
8237
8238                 /* Setup the "secret" hash key. */
8239                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8240                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8241                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8242                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8243                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8244                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8245                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8246                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8247                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8248                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8249         }
8250
8251         tp->rx_mode = RX_MODE_ENABLE;
8252         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8253                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8254
8255         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8256                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8257                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8258                                RX_MODE_RSS_IPV6_HASH_EN |
8259                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8260                                RX_MODE_RSS_IPV4_HASH_EN |
8261                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8262
8263         tw32_f(MAC_RX_MODE, tp->rx_mode);
8264         udelay(10);
8265
8266         tw32(MAC_LED_CTRL, tp->led_ctrl);
8267
8268         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8269         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8270                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8271                 udelay(10);
8272         }
8273         tw32_f(MAC_RX_MODE, tp->rx_mode);
8274         udelay(10);
8275
8276         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8277                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8278                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8279                         /* Set drive transmission level to 1.2V  */
8280                         /* only if the signal pre-emphasis bit is not set  */
8281                         val = tr32(MAC_SERDES_CFG);
8282                         val &= 0xfffff000;
8283                         val |= 0x880;
8284                         tw32(MAC_SERDES_CFG, val);
8285                 }
8286                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8287                         tw32(MAC_SERDES_CFG, 0x616000);
8288         }
8289
8290         /* Prevent chip from dropping frames when flow control
8291          * is enabled.
8292          */
8293         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8294                 val = 1;
8295         else
8296                 val = 2;
8297         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8298
8299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8300             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8301                 /* Use hardware link auto-negotiation */
8302                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8303         }
8304
8305         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8306             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8307                 u32 tmp;
8308
8309                 tmp = tr32(SERDES_RX_CTRL);
8310                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8311                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8312                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8313                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8314         }
8315
8316         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8317                 if (tp->link_config.phy_is_low_power) {
8318                         tp->link_config.phy_is_low_power = 0;
8319                         tp->link_config.speed = tp->link_config.orig_speed;
8320                         tp->link_config.duplex = tp->link_config.orig_duplex;
8321                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8322                 }
8323
8324                 err = tg3_setup_phy(tp, 0);
8325                 if (err)
8326                         return err;
8327
8328                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8329                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8330                         u32 tmp;
8331
8332                         /* Clear CRC stats. */
8333                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8334                                 tg3_writephy(tp, MII_TG3_TEST1,
8335                                              tmp | MII_TG3_TEST1_CRC_EN);
8336                                 tg3_readphy(tp, 0x14, &tmp);
8337                         }
8338                 }
8339         }
8340
8341         __tg3_set_rx_mode(tp->dev);
8342
8343         /* Initialize receive rules. */
8344         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8345         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8346         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8347         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8348
8349         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8350             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8351                 limit = 8;
8352         else
8353                 limit = 16;
8354         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8355                 limit -= 4;
8356         switch (limit) {
8357         case 16:
8358                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8359         case 15:
8360                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8361         case 14:
8362                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8363         case 13:
8364                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8365         case 12:
8366                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8367         case 11:
8368                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8369         case 10:
8370                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8371         case 9:
8372                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8373         case 8:
8374                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8375         case 7:
8376                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8377         case 6:
8378                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8379         case 5:
8380                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8381         case 4:
8382                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8383         case 3:
8384                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8385         case 2:
8386         case 1:
8387
8388         default:
8389                 break;
8390         }
8391
8392         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8393                 /* Write our heartbeat update interval to APE. */
8394                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8395                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8396
8397         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8398
8399         return 0;
8400 }
8401
8402 /* Called at device open time to get the chip ready for
8403  * packet processing.  Invoked with tp->lock held.
8404  */
8405 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8406 {
8407         tg3_switch_clocks(tp);
8408
8409         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8410
8411         return tg3_reset_hw(tp, reset_phy);
8412 }
8413
8414 #define TG3_STAT_ADD32(PSTAT, REG) \
8415 do {    u32 __val = tr32(REG); \
8416         (PSTAT)->low += __val; \
8417         if ((PSTAT)->low < __val) \
8418                 (PSTAT)->high += 1; \
8419 } while (0)
8420
8421 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8422 {
8423         struct tg3_hw_stats *sp = tp->hw_stats;
8424
8425         if (!netif_carrier_ok(tp->dev))
8426                 return;
8427
8428         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8429         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8430         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8431         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8432         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8433         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8434         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8435         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8436         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8437         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8438         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8439         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8440         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8441
8442         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8443         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8444         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8445         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8446         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8447         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8448         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8449         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8450         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8451         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8452         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8453         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8454         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8455         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8456
8457         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8458         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8459         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8460 }
8461
8462 static void tg3_timer(unsigned long __opaque)
8463 {
8464         struct tg3 *tp = (struct tg3 *) __opaque;
8465
8466         if (tp->irq_sync)
8467                 goto restart_timer;
8468
8469         spin_lock(&tp->lock);
8470
8471         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8472                 /* All of this garbage is because when using non-tagged
8473                  * IRQ status the mailbox/status_block protocol the chip
8474                  * uses with the cpu is race prone.
8475                  */
8476                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8477                         tw32(GRC_LOCAL_CTRL,
8478                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8479                 } else {
8480                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8481                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8482                 }
8483
8484                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8485                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8486                         spin_unlock(&tp->lock);
8487                         schedule_work(&tp->reset_task);
8488                         return;
8489                 }
8490         }
8491
8492         /* This part only runs once per second. */
8493         if (!--tp->timer_counter) {
8494                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8495                         tg3_periodic_fetch_stats(tp);
8496
8497                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8498                         u32 mac_stat;
8499                         int phy_event;
8500
8501                         mac_stat = tr32(MAC_STATUS);
8502
8503                         phy_event = 0;
8504                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8505                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8506                                         phy_event = 1;
8507                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8508                                 phy_event = 1;
8509
8510                         if (phy_event)
8511                                 tg3_setup_phy(tp, 0);
8512                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8513                         u32 mac_stat = tr32(MAC_STATUS);
8514                         int need_setup = 0;
8515
8516                         if (netif_carrier_ok(tp->dev) &&
8517                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8518                                 need_setup = 1;
8519                         }
8520                         if (! netif_carrier_ok(tp->dev) &&
8521                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8522                                          MAC_STATUS_SIGNAL_DET))) {
8523                                 need_setup = 1;
8524                         }
8525                         if (need_setup) {
8526                                 if (!tp->serdes_counter) {
8527                                         tw32_f(MAC_MODE,
8528                                              (tp->mac_mode &
8529                                               ~MAC_MODE_PORT_MODE_MASK));
8530                                         udelay(40);
8531                                         tw32_f(MAC_MODE, tp->mac_mode);
8532                                         udelay(40);
8533                                 }
8534                                 tg3_setup_phy(tp, 0);
8535                         }
8536                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8537                            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8538                         tg3_serdes_parallel_detect(tp);
8539                 }
8540
8541                 tp->timer_counter = tp->timer_multiplier;
8542         }
8543
8544         /* Heartbeat is only sent once every 2 seconds.
8545          *
8546          * The heartbeat is to tell the ASF firmware that the host
8547          * driver is still alive.  In the event that the OS crashes,
8548          * ASF needs to reset the hardware to free up the FIFO space
8549          * that may be filled with rx packets destined for the host.
8550          * If the FIFO is full, ASF will no longer function properly.
8551          *
8552          * Unintended resets have been reported on real time kernels
8553          * where the timer doesn't run on time.  Netpoll will also have
8554          * same problem.
8555          *
8556          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8557          * to check the ring condition when the heartbeat is expiring
8558          * before doing the reset.  This will prevent most unintended
8559          * resets.
8560          */
8561         if (!--tp->asf_counter) {
8562                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8563                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8564                         tg3_wait_for_event_ack(tp);
8565
8566                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8567                                       FWCMD_NICDRV_ALIVE3);
8568                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8569                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8570                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8571
8572                         tg3_generate_fw_event(tp);
8573                 }
8574                 tp->asf_counter = tp->asf_multiplier;
8575         }
8576
8577         spin_unlock(&tp->lock);
8578
8579 restart_timer:
8580         tp->timer.expires = jiffies + tp->timer_offset;
8581         add_timer(&tp->timer);
8582 }
8583
8584 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8585 {
8586         irq_handler_t fn;
8587         unsigned long flags;
8588         char *name;
8589         struct tg3_napi *tnapi = &tp->napi[irq_num];
8590
8591         if (tp->irq_cnt == 1)
8592                 name = tp->dev->name;
8593         else {
8594                 name = &tnapi->irq_lbl[0];
8595                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8596                 name[IFNAMSIZ-1] = 0;
8597         }
8598
8599         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8600                 fn = tg3_msi;
8601                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8602                         fn = tg3_msi_1shot;
8603                 flags = IRQF_SAMPLE_RANDOM;
8604         } else {
8605                 fn = tg3_interrupt;
8606                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8607                         fn = tg3_interrupt_tagged;
8608                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8609         }
8610
8611         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8612 }
8613
8614 static int tg3_test_interrupt(struct tg3 *tp)
8615 {
8616         struct tg3_napi *tnapi = &tp->napi[0];
8617         struct net_device *dev = tp->dev;
8618         int err, i, intr_ok = 0;
8619         u32 val;
8620
8621         if (!netif_running(dev))
8622                 return -ENODEV;
8623
8624         tg3_disable_ints(tp);
8625
8626         free_irq(tnapi->irq_vec, tnapi);
8627
8628         /*
8629          * Turn off MSI one shot mode.  Otherwise this test has no
8630          * observable way to know whether the interrupt was delivered.
8631          */
8632         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8633              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8634             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8635                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8636                 tw32(MSGINT_MODE, val);
8637         }
8638
8639         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8640                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8641         if (err)
8642                 return err;
8643
8644         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8645         tg3_enable_ints(tp);
8646
8647         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8648                tnapi->coal_now);
8649
8650         for (i = 0; i < 5; i++) {
8651                 u32 int_mbox, misc_host_ctrl;
8652
8653                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8654                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8655
8656                 if ((int_mbox != 0) ||
8657                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8658                         intr_ok = 1;
8659                         break;
8660                 }
8661
8662                 msleep(10);
8663         }
8664
8665         tg3_disable_ints(tp);
8666
8667         free_irq(tnapi->irq_vec, tnapi);
8668
8669         err = tg3_request_irq(tp, 0);
8670
8671         if (err)
8672                 return err;
8673
8674         if (intr_ok) {
8675                 /* Reenable MSI one shot mode. */
8676                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8677                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8678                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8679                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8680                         tw32(MSGINT_MODE, val);
8681                 }
8682                 return 0;
8683         }
8684
8685         return -EIO;
8686 }
8687
8688 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8689  * successfully restored
8690  */
8691 static int tg3_test_msi(struct tg3 *tp)
8692 {
8693         int err;
8694         u16 pci_cmd;
8695
8696         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8697                 return 0;
8698
8699         /* Turn off SERR reporting in case MSI terminates with Master
8700          * Abort.
8701          */
8702         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8703         pci_write_config_word(tp->pdev, PCI_COMMAND,
8704                               pci_cmd & ~PCI_COMMAND_SERR);
8705
8706         err = tg3_test_interrupt(tp);
8707
8708         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8709
8710         if (!err)
8711                 return 0;
8712
8713         /* other failures */
8714         if (err != -EIO)
8715                 return err;
8716
8717         /* MSI test failed, go back to INTx mode */
8718         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8719                     "to INTx mode. Please report this failure to the PCI "
8720                     "maintainer and include system chipset information\n");
8721
8722         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8723
8724         pci_disable_msi(tp->pdev);
8725
8726         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8727         tp->napi[0].irq_vec = tp->pdev->irq;
8728
8729         err = tg3_request_irq(tp, 0);
8730         if (err)
8731                 return err;
8732
8733         /* Need to reset the chip because the MSI cycle may have terminated
8734          * with Master Abort.
8735          */
8736         tg3_full_lock(tp, 1);
8737
8738         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8739         err = tg3_init_hw(tp, 1);
8740
8741         tg3_full_unlock(tp);
8742
8743         if (err)
8744                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8745
8746         return err;
8747 }
8748
8749 static int tg3_request_firmware(struct tg3 *tp)
8750 {
8751         const __be32 *fw_data;
8752
8753         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8754                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8755                            tp->fw_needed);
8756                 return -ENOENT;
8757         }
8758
8759         fw_data = (void *)tp->fw->data;
8760
8761         /* Firmware blob starts with version numbers, followed by
8762          * start address and _full_ length including BSS sections
8763          * (which must be longer than the actual data, of course
8764          */
8765
8766         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8767         if (tp->fw_len < (tp->fw->size - 12)) {
8768                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8769                            tp->fw_len, tp->fw_needed);
8770                 release_firmware(tp->fw);
8771                 tp->fw = NULL;
8772                 return -EINVAL;
8773         }
8774
8775         /* We no longer need firmware; we have it. */
8776         tp->fw_needed = NULL;
8777         return 0;
8778 }
8779
8780 static bool tg3_enable_msix(struct tg3 *tp)
8781 {
8782         int i, rc, cpus = num_online_cpus();
8783         struct msix_entry msix_ent[tp->irq_max];
8784
8785         if (cpus == 1)
8786                 /* Just fallback to the simpler MSI mode. */
8787                 return false;
8788
8789         /*
8790          * We want as many rx rings enabled as there are cpus.
8791          * The first MSIX vector only deals with link interrupts, etc,
8792          * so we add one to the number of vectors we are requesting.
8793          */
8794         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8795
8796         for (i = 0; i < tp->irq_max; i++) {
8797                 msix_ent[i].entry  = i;
8798                 msix_ent[i].vector = 0;
8799         }
8800
8801         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8802         if (rc < 0) {
8803                 return false;
8804         } else if (rc != 0) {
8805                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8806                         return false;
8807                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8808                               tp->irq_cnt, rc);
8809                 tp->irq_cnt = rc;
8810         }
8811
8812         for (i = 0; i < tp->irq_max; i++)
8813                 tp->napi[i].irq_vec = msix_ent[i].vector;
8814
8815         tp->dev->real_num_tx_queues = 1;
8816         if (tp->irq_cnt > 1) {
8817                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8818
8819                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8820                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8821                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8822                 }
8823         }
8824
8825         return true;
8826 }
8827
8828 static void tg3_ints_init(struct tg3 *tp)
8829 {
8830         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8831             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8832                 /* All MSI supporting chips should support tagged
8833                  * status.  Assert that this is the case.
8834                  */
8835                 netdev_warn(tp->dev,
8836                             "MSI without TAGGED_STATUS? Not using MSI\n");
8837                 goto defcfg;
8838         }
8839
8840         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8841                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8842         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8843                  pci_enable_msi(tp->pdev) == 0)
8844                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8845
8846         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8847                 u32 msi_mode = tr32(MSGINT_MODE);
8848                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8849                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8850                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8851         }
8852 defcfg:
8853         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8854                 tp->irq_cnt = 1;
8855                 tp->napi[0].irq_vec = tp->pdev->irq;
8856                 tp->dev->real_num_tx_queues = 1;
8857         }
8858 }
8859
8860 static void tg3_ints_fini(struct tg3 *tp)
8861 {
8862         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8863                 pci_disable_msix(tp->pdev);
8864         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8865                 pci_disable_msi(tp->pdev);
8866         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8867         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8868 }
8869
8870 static int tg3_open(struct net_device *dev)
8871 {
8872         struct tg3 *tp = netdev_priv(dev);
8873         int i, err;
8874
8875         if (tp->fw_needed) {
8876                 err = tg3_request_firmware(tp);
8877                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8878                         if (err)
8879                                 return err;
8880                 } else if (err) {
8881                         netdev_warn(tp->dev, "TSO capability disabled\n");
8882                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8883                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8884                         netdev_notice(tp->dev, "TSO capability restored\n");
8885                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8886                 }
8887         }
8888
8889         netif_carrier_off(tp->dev);
8890
8891         err = tg3_set_power_state(tp, PCI_D0);
8892         if (err)
8893                 return err;
8894
8895         tg3_full_lock(tp, 0);
8896
8897         tg3_disable_ints(tp);
8898         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8899
8900         tg3_full_unlock(tp);
8901
8902         /*
8903          * Setup interrupts first so we know how
8904          * many NAPI resources to allocate
8905          */
8906         tg3_ints_init(tp);
8907
8908         /* The placement of this call is tied
8909          * to the setup and use of Host TX descriptors.
8910          */
8911         err = tg3_alloc_consistent(tp);
8912         if (err)
8913                 goto err_out1;
8914
8915         tg3_napi_enable(tp);
8916
8917         for (i = 0; i < tp->irq_cnt; i++) {
8918                 struct tg3_napi *tnapi = &tp->napi[i];
8919                 err = tg3_request_irq(tp, i);
8920                 if (err) {
8921                         for (i--; i >= 0; i--)
8922                                 free_irq(tnapi->irq_vec, tnapi);
8923                         break;
8924                 }
8925         }
8926
8927         if (err)
8928                 goto err_out2;
8929
8930         tg3_full_lock(tp, 0);
8931
8932         err = tg3_init_hw(tp, 1);
8933         if (err) {
8934                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8935                 tg3_free_rings(tp);
8936         } else {
8937                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8938                         tp->timer_offset = HZ;
8939                 else
8940                         tp->timer_offset = HZ / 10;
8941
8942                 BUG_ON(tp->timer_offset > HZ);
8943                 tp->timer_counter = tp->timer_multiplier =
8944                         (HZ / tp->timer_offset);
8945                 tp->asf_counter = tp->asf_multiplier =
8946                         ((HZ / tp->timer_offset) * 2);
8947
8948                 init_timer(&tp->timer);
8949                 tp->timer.expires = jiffies + tp->timer_offset;
8950                 tp->timer.data = (unsigned long) tp;
8951                 tp->timer.function = tg3_timer;
8952         }
8953
8954         tg3_full_unlock(tp);
8955
8956         if (err)
8957                 goto err_out3;
8958
8959         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8960                 err = tg3_test_msi(tp);
8961
8962                 if (err) {
8963                         tg3_full_lock(tp, 0);
8964                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8965                         tg3_free_rings(tp);
8966                         tg3_full_unlock(tp);
8967
8968                         goto err_out2;
8969                 }
8970
8971                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8972                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8973                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8974                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8975                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8976
8977                         tw32(PCIE_TRANSACTION_CFG,
8978                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8979                 }
8980         }
8981
8982         tg3_phy_start(tp);
8983
8984         tg3_full_lock(tp, 0);
8985
8986         add_timer(&tp->timer);
8987         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8988         tg3_enable_ints(tp);
8989
8990         tg3_full_unlock(tp);
8991
8992         netif_tx_start_all_queues(dev);
8993
8994         return 0;
8995
8996 err_out3:
8997         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8998                 struct tg3_napi *tnapi = &tp->napi[i];
8999                 free_irq(tnapi->irq_vec, tnapi);
9000         }
9001
9002 err_out2:
9003         tg3_napi_disable(tp);
9004         tg3_free_consistent(tp);
9005
9006 err_out1:
9007         tg3_ints_fini(tp);
9008         return err;
9009 }
9010
9011 static struct net_device_stats *tg3_get_stats(struct net_device *);
9012 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9013
9014 static int tg3_close(struct net_device *dev)
9015 {
9016         int i;
9017         struct tg3 *tp = netdev_priv(dev);
9018
9019         tg3_napi_disable(tp);
9020         cancel_work_sync(&tp->reset_task);
9021
9022         netif_tx_stop_all_queues(dev);
9023
9024         del_timer_sync(&tp->timer);
9025
9026         tg3_phy_stop(tp);
9027
9028         tg3_full_lock(tp, 1);
9029
9030         tg3_disable_ints(tp);
9031
9032         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9033         tg3_free_rings(tp);
9034         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9035
9036         tg3_full_unlock(tp);
9037
9038         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9039                 struct tg3_napi *tnapi = &tp->napi[i];
9040                 free_irq(tnapi->irq_vec, tnapi);
9041         }
9042
9043         tg3_ints_fini(tp);
9044
9045         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9046                sizeof(tp->net_stats_prev));
9047         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9048                sizeof(tp->estats_prev));
9049
9050         tg3_free_consistent(tp);
9051
9052         tg3_set_power_state(tp, PCI_D3hot);
9053
9054         netif_carrier_off(tp->dev);
9055
9056         return 0;
9057 }
9058
9059 static inline unsigned long get_stat64(tg3_stat64_t *val)
9060 {
9061         unsigned long ret;
9062
9063 #if (BITS_PER_LONG == 32)
9064         ret = val->low;
9065 #else
9066         ret = ((u64)val->high << 32) | ((u64)val->low);
9067 #endif
9068         return ret;
9069 }
9070
9071 static inline u64 get_estat64(tg3_stat64_t *val)
9072 {
9073        return ((u64)val->high << 32) | ((u64)val->low);
9074 }
9075
9076 static unsigned long calc_crc_errors(struct tg3 *tp)
9077 {
9078         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9079
9080         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9081             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9082              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9083                 u32 val;
9084
9085                 spin_lock_bh(&tp->lock);
9086                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9087                         tg3_writephy(tp, MII_TG3_TEST1,
9088                                      val | MII_TG3_TEST1_CRC_EN);
9089                         tg3_readphy(tp, 0x14, &val);
9090                 } else
9091                         val = 0;
9092                 spin_unlock_bh(&tp->lock);
9093
9094                 tp->phy_crc_errors += val;
9095
9096                 return tp->phy_crc_errors;
9097         }
9098
9099         return get_stat64(&hw_stats->rx_fcs_errors);
9100 }
9101
9102 #define ESTAT_ADD(member) \
9103         estats->member =        old_estats->member + \
9104                                 get_estat64(&hw_stats->member)
9105
9106 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9107 {
9108         struct tg3_ethtool_stats *estats = &tp->estats;
9109         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9110         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9111
9112         if (!hw_stats)
9113                 return old_estats;
9114
9115         ESTAT_ADD(rx_octets);
9116         ESTAT_ADD(rx_fragments);
9117         ESTAT_ADD(rx_ucast_packets);
9118         ESTAT_ADD(rx_mcast_packets);
9119         ESTAT_ADD(rx_bcast_packets);
9120         ESTAT_ADD(rx_fcs_errors);
9121         ESTAT_ADD(rx_align_errors);
9122         ESTAT_ADD(rx_xon_pause_rcvd);
9123         ESTAT_ADD(rx_xoff_pause_rcvd);
9124         ESTAT_ADD(rx_mac_ctrl_rcvd);
9125         ESTAT_ADD(rx_xoff_entered);
9126         ESTAT_ADD(rx_frame_too_long_errors);
9127         ESTAT_ADD(rx_jabbers);
9128         ESTAT_ADD(rx_undersize_packets);
9129         ESTAT_ADD(rx_in_length_errors);
9130         ESTAT_ADD(rx_out_length_errors);
9131         ESTAT_ADD(rx_64_or_less_octet_packets);
9132         ESTAT_ADD(rx_65_to_127_octet_packets);
9133         ESTAT_ADD(rx_128_to_255_octet_packets);
9134         ESTAT_ADD(rx_256_to_511_octet_packets);
9135         ESTAT_ADD(rx_512_to_1023_octet_packets);
9136         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9137         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9138         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9139         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9140         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9141
9142         ESTAT_ADD(tx_octets);
9143         ESTAT_ADD(tx_collisions);
9144         ESTAT_ADD(tx_xon_sent);
9145         ESTAT_ADD(tx_xoff_sent);
9146         ESTAT_ADD(tx_flow_control);
9147         ESTAT_ADD(tx_mac_errors);
9148         ESTAT_ADD(tx_single_collisions);
9149         ESTAT_ADD(tx_mult_collisions);
9150         ESTAT_ADD(tx_deferred);
9151         ESTAT_ADD(tx_excessive_collisions);
9152         ESTAT_ADD(tx_late_collisions);
9153         ESTAT_ADD(tx_collide_2times);
9154         ESTAT_ADD(tx_collide_3times);
9155         ESTAT_ADD(tx_collide_4times);
9156         ESTAT_ADD(tx_collide_5times);
9157         ESTAT_ADD(tx_collide_6times);
9158         ESTAT_ADD(tx_collide_7times);
9159         ESTAT_ADD(tx_collide_8times);
9160         ESTAT_ADD(tx_collide_9times);
9161         ESTAT_ADD(tx_collide_10times);
9162         ESTAT_ADD(tx_collide_11times);
9163         ESTAT_ADD(tx_collide_12times);
9164         ESTAT_ADD(tx_collide_13times);
9165         ESTAT_ADD(tx_collide_14times);
9166         ESTAT_ADD(tx_collide_15times);
9167         ESTAT_ADD(tx_ucast_packets);
9168         ESTAT_ADD(tx_mcast_packets);
9169         ESTAT_ADD(tx_bcast_packets);
9170         ESTAT_ADD(tx_carrier_sense_errors);
9171         ESTAT_ADD(tx_discards);
9172         ESTAT_ADD(tx_errors);
9173
9174         ESTAT_ADD(dma_writeq_full);
9175         ESTAT_ADD(dma_write_prioq_full);
9176         ESTAT_ADD(rxbds_empty);
9177         ESTAT_ADD(rx_discards);
9178         ESTAT_ADD(rx_errors);
9179         ESTAT_ADD(rx_threshold_hit);
9180
9181         ESTAT_ADD(dma_readq_full);
9182         ESTAT_ADD(dma_read_prioq_full);
9183         ESTAT_ADD(tx_comp_queue_full);
9184
9185         ESTAT_ADD(ring_set_send_prod_index);
9186         ESTAT_ADD(ring_status_update);
9187         ESTAT_ADD(nic_irqs);
9188         ESTAT_ADD(nic_avoided_irqs);
9189         ESTAT_ADD(nic_tx_threshold_hit);
9190
9191         return estats;
9192 }
9193
9194 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9195 {
9196         struct tg3 *tp = netdev_priv(dev);
9197         struct net_device_stats *stats = &tp->net_stats;
9198         struct net_device_stats *old_stats = &tp->net_stats_prev;
9199         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9200
9201         if (!hw_stats)
9202                 return old_stats;
9203
9204         stats->rx_packets = old_stats->rx_packets +
9205                 get_stat64(&hw_stats->rx_ucast_packets) +
9206                 get_stat64(&hw_stats->rx_mcast_packets) +
9207                 get_stat64(&hw_stats->rx_bcast_packets);
9208
9209         stats->tx_packets = old_stats->tx_packets +
9210                 get_stat64(&hw_stats->tx_ucast_packets) +
9211                 get_stat64(&hw_stats->tx_mcast_packets) +
9212                 get_stat64(&hw_stats->tx_bcast_packets);
9213
9214         stats->rx_bytes = old_stats->rx_bytes +
9215                 get_stat64(&hw_stats->rx_octets);
9216         stats->tx_bytes = old_stats->tx_bytes +
9217                 get_stat64(&hw_stats->tx_octets);
9218
9219         stats->rx_errors = old_stats->rx_errors +
9220                 get_stat64(&hw_stats->rx_errors);
9221         stats->tx_errors = old_stats->tx_errors +
9222                 get_stat64(&hw_stats->tx_errors) +
9223                 get_stat64(&hw_stats->tx_mac_errors) +
9224                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9225                 get_stat64(&hw_stats->tx_discards);
9226
9227         stats->multicast = old_stats->multicast +
9228                 get_stat64(&hw_stats->rx_mcast_packets);
9229         stats->collisions = old_stats->collisions +
9230                 get_stat64(&hw_stats->tx_collisions);
9231
9232         stats->rx_length_errors = old_stats->rx_length_errors +
9233                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9234                 get_stat64(&hw_stats->rx_undersize_packets);
9235
9236         stats->rx_over_errors = old_stats->rx_over_errors +
9237                 get_stat64(&hw_stats->rxbds_empty);
9238         stats->rx_frame_errors = old_stats->rx_frame_errors +
9239                 get_stat64(&hw_stats->rx_align_errors);
9240         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9241                 get_stat64(&hw_stats->tx_discards);
9242         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9243                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9244
9245         stats->rx_crc_errors = old_stats->rx_crc_errors +
9246                 calc_crc_errors(tp);
9247
9248         stats->rx_missed_errors = old_stats->rx_missed_errors +
9249                 get_stat64(&hw_stats->rx_discards);
9250
9251         return stats;
9252 }
9253
9254 static inline u32 calc_crc(unsigned char *buf, int len)
9255 {
9256         u32 reg;
9257         u32 tmp;
9258         int j, k;
9259
9260         reg = 0xffffffff;
9261
9262         for (j = 0; j < len; j++) {
9263                 reg ^= buf[j];
9264
9265                 for (k = 0; k < 8; k++) {
9266                         tmp = reg & 0x01;
9267
9268                         reg >>= 1;
9269
9270                         if (tmp)
9271                                 reg ^= 0xedb88320;
9272                 }
9273         }
9274
9275         return ~reg;
9276 }
9277
9278 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9279 {
9280         /* accept or reject all multicast frames */
9281         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9282         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9283         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9284         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9285 }
9286
9287 static void __tg3_set_rx_mode(struct net_device *dev)
9288 {
9289         struct tg3 *tp = netdev_priv(dev);
9290         u32 rx_mode;
9291
9292         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9293                                   RX_MODE_KEEP_VLAN_TAG);
9294
9295         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9296          * flag clear.
9297          */
9298 #if TG3_VLAN_TAG_USED
9299         if (!tp->vlgrp &&
9300             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9301                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9302 #else
9303         /* By definition, VLAN is disabled always in this
9304          * case.
9305          */
9306         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9307                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9308 #endif
9309
9310         if (dev->flags & IFF_PROMISC) {
9311                 /* Promiscuous mode. */
9312                 rx_mode |= RX_MODE_PROMISC;
9313         } else if (dev->flags & IFF_ALLMULTI) {
9314                 /* Accept all multicast. */
9315                 tg3_set_multi(tp, 1);
9316         } else if (netdev_mc_empty(dev)) {
9317                 /* Reject all multicast. */
9318                 tg3_set_multi(tp, 0);
9319         } else {
9320                 /* Accept one or more multicast(s). */
9321                 struct netdev_hw_addr *ha;
9322                 u32 mc_filter[4] = { 0, };
9323                 u32 regidx;
9324                 u32 bit;
9325                 u32 crc;
9326
9327                 netdev_for_each_mc_addr(ha, dev) {
9328                         crc = calc_crc(ha->addr, ETH_ALEN);
9329                         bit = ~crc & 0x7f;
9330                         regidx = (bit & 0x60) >> 5;
9331                         bit &= 0x1f;
9332                         mc_filter[regidx] |= (1 << bit);
9333                 }
9334
9335                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9336                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9337                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9338                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9339         }
9340
9341         if (rx_mode != tp->rx_mode) {
9342                 tp->rx_mode = rx_mode;
9343                 tw32_f(MAC_RX_MODE, rx_mode);
9344                 udelay(10);
9345         }
9346 }
9347
9348 static void tg3_set_rx_mode(struct net_device *dev)
9349 {
9350         struct tg3 *tp = netdev_priv(dev);
9351
9352         if (!netif_running(dev))
9353                 return;
9354
9355         tg3_full_lock(tp, 0);
9356         __tg3_set_rx_mode(dev);
9357         tg3_full_unlock(tp);
9358 }
9359
9360 #define TG3_REGDUMP_LEN         (32 * 1024)
9361
9362 static int tg3_get_regs_len(struct net_device *dev)
9363 {
9364         return TG3_REGDUMP_LEN;
9365 }
9366
9367 static void tg3_get_regs(struct net_device *dev,
9368                 struct ethtool_regs *regs, void *_p)
9369 {
9370         u32 *p = _p;
9371         struct tg3 *tp = netdev_priv(dev);
9372         u8 *orig_p = _p;
9373         int i;
9374
9375         regs->version = 0;
9376
9377         memset(p, 0, TG3_REGDUMP_LEN);
9378
9379         if (tp->link_config.phy_is_low_power)
9380                 return;
9381
9382         tg3_full_lock(tp, 0);
9383
9384 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9385 #define GET_REG32_LOOP(base,len)                \
9386 do {    p = (u32 *)(orig_p + (base));           \
9387         for (i = 0; i < len; i += 4)            \
9388                 __GET_REG32((base) + i);        \
9389 } while (0)
9390 #define GET_REG32_1(reg)                        \
9391 do {    p = (u32 *)(orig_p + (reg));            \
9392         __GET_REG32((reg));                     \
9393 } while (0)
9394
9395         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9396         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9397         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9398         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9399         GET_REG32_1(SNDDATAC_MODE);
9400         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9401         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9402         GET_REG32_1(SNDBDC_MODE);
9403         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9404         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9405         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9406         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9407         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9408         GET_REG32_1(RCVDCC_MODE);
9409         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9410         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9411         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9412         GET_REG32_1(MBFREE_MODE);
9413         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9414         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9415         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9416         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9417         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9418         GET_REG32_1(RX_CPU_MODE);
9419         GET_REG32_1(RX_CPU_STATE);
9420         GET_REG32_1(RX_CPU_PGMCTR);
9421         GET_REG32_1(RX_CPU_HWBKPT);
9422         GET_REG32_1(TX_CPU_MODE);
9423         GET_REG32_1(TX_CPU_STATE);
9424         GET_REG32_1(TX_CPU_PGMCTR);
9425         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9426         GET_REG32_LOOP(FTQ_RESET, 0x120);
9427         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9428         GET_REG32_1(DMAC_MODE);
9429         GET_REG32_LOOP(GRC_MODE, 0x4c);
9430         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9431                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9432
9433 #undef __GET_REG32
9434 #undef GET_REG32_LOOP
9435 #undef GET_REG32_1
9436
9437         tg3_full_unlock(tp);
9438 }
9439
9440 static int tg3_get_eeprom_len(struct net_device *dev)
9441 {
9442         struct tg3 *tp = netdev_priv(dev);
9443
9444         return tp->nvram_size;
9445 }
9446
9447 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9448 {
9449         struct tg3 *tp = netdev_priv(dev);
9450         int ret;
9451         u8  *pd;
9452         u32 i, offset, len, b_offset, b_count;
9453         __be32 val;
9454
9455         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9456                 return -EINVAL;
9457
9458         if (tp->link_config.phy_is_low_power)
9459                 return -EAGAIN;
9460
9461         offset = eeprom->offset;
9462         len = eeprom->len;
9463         eeprom->len = 0;
9464
9465         eeprom->magic = TG3_EEPROM_MAGIC;
9466
9467         if (offset & 3) {
9468                 /* adjustments to start on required 4 byte boundary */
9469                 b_offset = offset & 3;
9470                 b_count = 4 - b_offset;
9471                 if (b_count > len) {
9472                         /* i.e. offset=1 len=2 */
9473                         b_count = len;
9474                 }
9475                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9476                 if (ret)
9477                         return ret;
9478                 memcpy(data, ((char*)&val) + b_offset, b_count);
9479                 len -= b_count;
9480                 offset += b_count;
9481                 eeprom->len += b_count;
9482         }
9483
9484         /* read bytes upto the last 4 byte boundary */
9485         pd = &data[eeprom->len];
9486         for (i = 0; i < (len - (len & 3)); i += 4) {
9487                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9488                 if (ret) {
9489                         eeprom->len += i;
9490                         return ret;
9491                 }
9492                 memcpy(pd + i, &val, 4);
9493         }
9494         eeprom->len += i;
9495
9496         if (len & 3) {
9497                 /* read last bytes not ending on 4 byte boundary */
9498                 pd = &data[eeprom->len];
9499                 b_count = len & 3;
9500                 b_offset = offset + len - b_count;
9501                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9502                 if (ret)
9503                         return ret;
9504                 memcpy(pd, &val, b_count);
9505                 eeprom->len += b_count;
9506         }
9507         return 0;
9508 }
9509
9510 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9511
9512 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9513 {
9514         struct tg3 *tp = netdev_priv(dev);
9515         int ret;
9516         u32 offset, len, b_offset, odd_len;
9517         u8 *buf;
9518         __be32 start, end;
9519
9520         if (tp->link_config.phy_is_low_power)
9521                 return -EAGAIN;
9522
9523         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9524             eeprom->magic != TG3_EEPROM_MAGIC)
9525                 return -EINVAL;
9526
9527         offset = eeprom->offset;
9528         len = eeprom->len;
9529
9530         if ((b_offset = (offset & 3))) {
9531                 /* adjustments to start on required 4 byte boundary */
9532                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9533                 if (ret)
9534                         return ret;
9535                 len += b_offset;
9536                 offset &= ~3;
9537                 if (len < 4)
9538                         len = 4;
9539         }
9540
9541         odd_len = 0;
9542         if (len & 3) {
9543                 /* adjustments to end on required 4 byte boundary */
9544                 odd_len = 1;
9545                 len = (len + 3) & ~3;
9546                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9547                 if (ret)
9548                         return ret;
9549         }
9550
9551         buf = data;
9552         if (b_offset || odd_len) {
9553                 buf = kmalloc(len, GFP_KERNEL);
9554                 if (!buf)
9555                         return -ENOMEM;
9556                 if (b_offset)
9557                         memcpy(buf, &start, 4);
9558                 if (odd_len)
9559                         memcpy(buf+len-4, &end, 4);
9560                 memcpy(buf + b_offset, data, eeprom->len);
9561         }
9562
9563         ret = tg3_nvram_write_block(tp, offset, len, buf);
9564
9565         if (buf != data)
9566                 kfree(buf);
9567
9568         return ret;
9569 }
9570
9571 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9572 {
9573         struct tg3 *tp = netdev_priv(dev);
9574
9575         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9576                 struct phy_device *phydev;
9577                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9578                         return -EAGAIN;
9579                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9580                 return phy_ethtool_gset(phydev, cmd);
9581         }
9582
9583         cmd->supported = (SUPPORTED_Autoneg);
9584
9585         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9586                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9587                                    SUPPORTED_1000baseT_Full);
9588
9589         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9590                 cmd->supported |= (SUPPORTED_100baseT_Half |
9591                                   SUPPORTED_100baseT_Full |
9592                                   SUPPORTED_10baseT_Half |
9593                                   SUPPORTED_10baseT_Full |
9594                                   SUPPORTED_TP);
9595                 cmd->port = PORT_TP;
9596         } else {
9597                 cmd->supported |= SUPPORTED_FIBRE;
9598                 cmd->port = PORT_FIBRE;
9599         }
9600
9601         cmd->advertising = tp->link_config.advertising;
9602         if (netif_running(dev)) {
9603                 cmd->speed = tp->link_config.active_speed;
9604                 cmd->duplex = tp->link_config.active_duplex;
9605         }
9606         cmd->phy_address = tp->phy_addr;
9607         cmd->transceiver = XCVR_INTERNAL;
9608         cmd->autoneg = tp->link_config.autoneg;
9609         cmd->maxtxpkt = 0;
9610         cmd->maxrxpkt = 0;
9611         return 0;
9612 }
9613
9614 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9615 {
9616         struct tg3 *tp = netdev_priv(dev);
9617
9618         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9619                 struct phy_device *phydev;
9620                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9621                         return -EAGAIN;
9622                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9623                 return phy_ethtool_sset(phydev, cmd);
9624         }
9625
9626         if (cmd->autoneg != AUTONEG_ENABLE &&
9627             cmd->autoneg != AUTONEG_DISABLE)
9628                 return -EINVAL;
9629
9630         if (cmd->autoneg == AUTONEG_DISABLE &&
9631             cmd->duplex != DUPLEX_FULL &&
9632             cmd->duplex != DUPLEX_HALF)
9633                 return -EINVAL;
9634
9635         if (cmd->autoneg == AUTONEG_ENABLE) {
9636                 u32 mask = ADVERTISED_Autoneg |
9637                            ADVERTISED_Pause |
9638                            ADVERTISED_Asym_Pause;
9639
9640                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9641                         mask |= ADVERTISED_1000baseT_Half |
9642                                 ADVERTISED_1000baseT_Full;
9643
9644                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9645                         mask |= ADVERTISED_100baseT_Half |
9646                                 ADVERTISED_100baseT_Full |
9647                                 ADVERTISED_10baseT_Half |
9648                                 ADVERTISED_10baseT_Full |
9649                                 ADVERTISED_TP;
9650                 else
9651                         mask |= ADVERTISED_FIBRE;
9652
9653                 if (cmd->advertising & ~mask)
9654                         return -EINVAL;
9655
9656                 mask &= (ADVERTISED_1000baseT_Half |
9657                          ADVERTISED_1000baseT_Full |
9658                          ADVERTISED_100baseT_Half |
9659                          ADVERTISED_100baseT_Full |
9660                          ADVERTISED_10baseT_Half |
9661                          ADVERTISED_10baseT_Full);
9662
9663                 cmd->advertising &= mask;
9664         } else {
9665                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9666                         if (cmd->speed != SPEED_1000)
9667                                 return -EINVAL;
9668
9669                         if (cmd->duplex != DUPLEX_FULL)
9670                                 return -EINVAL;
9671                 } else {
9672                         if (cmd->speed != SPEED_100 &&
9673                             cmd->speed != SPEED_10)
9674                                 return -EINVAL;
9675                 }
9676         }
9677
9678         tg3_full_lock(tp, 0);
9679
9680         tp->link_config.autoneg = cmd->autoneg;
9681         if (cmd->autoneg == AUTONEG_ENABLE) {
9682                 tp->link_config.advertising = (cmd->advertising |
9683                                               ADVERTISED_Autoneg);
9684                 tp->link_config.speed = SPEED_INVALID;
9685                 tp->link_config.duplex = DUPLEX_INVALID;
9686         } else {
9687                 tp->link_config.advertising = 0;
9688                 tp->link_config.speed = cmd->speed;
9689                 tp->link_config.duplex = cmd->duplex;
9690         }
9691
9692         tp->link_config.orig_speed = tp->link_config.speed;
9693         tp->link_config.orig_duplex = tp->link_config.duplex;
9694         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9695
9696         if (netif_running(dev))
9697                 tg3_setup_phy(tp, 1);
9698
9699         tg3_full_unlock(tp);
9700
9701         return 0;
9702 }
9703
9704 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9705 {
9706         struct tg3 *tp = netdev_priv(dev);
9707
9708         strcpy(info->driver, DRV_MODULE_NAME);
9709         strcpy(info->version, DRV_MODULE_VERSION);
9710         strcpy(info->fw_version, tp->fw_ver);
9711         strcpy(info->bus_info, pci_name(tp->pdev));
9712 }
9713
9714 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9715 {
9716         struct tg3 *tp = netdev_priv(dev);
9717
9718         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9719             device_can_wakeup(&tp->pdev->dev))
9720                 wol->supported = WAKE_MAGIC;
9721         else
9722                 wol->supported = 0;
9723         wol->wolopts = 0;
9724         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9725             device_can_wakeup(&tp->pdev->dev))
9726                 wol->wolopts = WAKE_MAGIC;
9727         memset(&wol->sopass, 0, sizeof(wol->sopass));
9728 }
9729
9730 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9731 {
9732         struct tg3 *tp = netdev_priv(dev);
9733         struct device *dp = &tp->pdev->dev;
9734
9735         if (wol->wolopts & ~WAKE_MAGIC)
9736                 return -EINVAL;
9737         if ((wol->wolopts & WAKE_MAGIC) &&
9738             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9739                 return -EINVAL;
9740
9741         spin_lock_bh(&tp->lock);
9742         if (wol->wolopts & WAKE_MAGIC) {
9743                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9744                 device_set_wakeup_enable(dp, true);
9745         } else {
9746                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9747                 device_set_wakeup_enable(dp, false);
9748         }
9749         spin_unlock_bh(&tp->lock);
9750
9751         return 0;
9752 }
9753
9754 static u32 tg3_get_msglevel(struct net_device *dev)
9755 {
9756         struct tg3 *tp = netdev_priv(dev);
9757         return tp->msg_enable;
9758 }
9759
9760 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9761 {
9762         struct tg3 *tp = netdev_priv(dev);
9763         tp->msg_enable = value;
9764 }
9765
9766 static int tg3_set_tso(struct net_device *dev, u32 value)
9767 {
9768         struct tg3 *tp = netdev_priv(dev);
9769
9770         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9771                 if (value)
9772                         return -EINVAL;
9773                 return 0;
9774         }
9775         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9776             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9777              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9778                 if (value) {
9779                         dev->features |= NETIF_F_TSO6;
9780                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9781                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9782                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9783                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9784                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9785                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9786                                 dev->features |= NETIF_F_TSO_ECN;
9787                 } else
9788                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9789         }
9790         return ethtool_op_set_tso(dev, value);
9791 }
9792
9793 static int tg3_nway_reset(struct net_device *dev)
9794 {
9795         struct tg3 *tp = netdev_priv(dev);
9796         int r;
9797
9798         if (!netif_running(dev))
9799                 return -EAGAIN;
9800
9801         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9802                 return -EINVAL;
9803
9804         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9805                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9806                         return -EAGAIN;
9807                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9808         } else {
9809                 u32 bmcr;
9810
9811                 spin_lock_bh(&tp->lock);
9812                 r = -EINVAL;
9813                 tg3_readphy(tp, MII_BMCR, &bmcr);
9814                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9815                     ((bmcr & BMCR_ANENABLE) ||
9816                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9817                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9818                                                    BMCR_ANENABLE);
9819                         r = 0;
9820                 }
9821                 spin_unlock_bh(&tp->lock);
9822         }
9823
9824         return r;
9825 }
9826
9827 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9828 {
9829         struct tg3 *tp = netdev_priv(dev);
9830
9831         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9832         ering->rx_mini_max_pending = 0;
9833         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9834                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9835         else
9836                 ering->rx_jumbo_max_pending = 0;
9837
9838         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9839
9840         ering->rx_pending = tp->rx_pending;
9841         ering->rx_mini_pending = 0;
9842         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9843                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9844         else
9845                 ering->rx_jumbo_pending = 0;
9846
9847         ering->tx_pending = tp->napi[0].tx_pending;
9848 }
9849
9850 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9851 {
9852         struct tg3 *tp = netdev_priv(dev);
9853         int i, irq_sync = 0, err = 0;
9854
9855         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9856             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9857             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9858             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9859             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9860              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9861                 return -EINVAL;
9862
9863         if (netif_running(dev)) {
9864                 tg3_phy_stop(tp);
9865                 tg3_netif_stop(tp);
9866                 irq_sync = 1;
9867         }
9868
9869         tg3_full_lock(tp, irq_sync);
9870
9871         tp->rx_pending = ering->rx_pending;
9872
9873         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9874             tp->rx_pending > 63)
9875                 tp->rx_pending = 63;
9876         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9877
9878         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9879                 tp->napi[i].tx_pending = ering->tx_pending;
9880
9881         if (netif_running(dev)) {
9882                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9883                 err = tg3_restart_hw(tp, 1);
9884                 if (!err)
9885                         tg3_netif_start(tp);
9886         }
9887
9888         tg3_full_unlock(tp);
9889
9890         if (irq_sync && !err)
9891                 tg3_phy_start(tp);
9892
9893         return err;
9894 }
9895
9896 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9897 {
9898         struct tg3 *tp = netdev_priv(dev);
9899
9900         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9901
9902         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9903                 epause->rx_pause = 1;
9904         else
9905                 epause->rx_pause = 0;
9906
9907         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9908                 epause->tx_pause = 1;
9909         else
9910                 epause->tx_pause = 0;
9911 }
9912
9913 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9914 {
9915         struct tg3 *tp = netdev_priv(dev);
9916         int err = 0;
9917
9918         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9919                 u32 newadv;
9920                 struct phy_device *phydev;
9921
9922                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9923
9924                 if (!(phydev->supported & SUPPORTED_Pause) ||
9925                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9926                      ((epause->rx_pause && !epause->tx_pause) ||
9927                       (!epause->rx_pause && epause->tx_pause))))
9928                         return -EINVAL;
9929
9930                 tp->link_config.flowctrl = 0;
9931                 if (epause->rx_pause) {
9932                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9933
9934                         if (epause->tx_pause) {
9935                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9936                                 newadv = ADVERTISED_Pause;
9937                         } else
9938                                 newadv = ADVERTISED_Pause |
9939                                          ADVERTISED_Asym_Pause;
9940                 } else if (epause->tx_pause) {
9941                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9942                         newadv = ADVERTISED_Asym_Pause;
9943                 } else
9944                         newadv = 0;
9945
9946                 if (epause->autoneg)
9947                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9948                 else
9949                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9950
9951                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9952                         u32 oldadv = phydev->advertising &
9953                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9954                         if (oldadv != newadv) {
9955                                 phydev->advertising &=
9956                                         ~(ADVERTISED_Pause |
9957                                           ADVERTISED_Asym_Pause);
9958                                 phydev->advertising |= newadv;
9959                                 if (phydev->autoneg) {
9960                                         /*
9961                                          * Always renegotiate the link to
9962                                          * inform our link partner of our
9963                                          * flow control settings, even if the
9964                                          * flow control is forced.  Let
9965                                          * tg3_adjust_link() do the final
9966                                          * flow control setup.
9967                                          */
9968                                         return phy_start_aneg(phydev);
9969                                 }
9970                         }
9971
9972                         if (!epause->autoneg)
9973                                 tg3_setup_flow_control(tp, 0, 0);
9974                 } else {
9975                         tp->link_config.orig_advertising &=
9976                                         ~(ADVERTISED_Pause |
9977                                           ADVERTISED_Asym_Pause);
9978                         tp->link_config.orig_advertising |= newadv;
9979                 }
9980         } else {
9981                 int irq_sync = 0;
9982
9983                 if (netif_running(dev)) {
9984                         tg3_netif_stop(tp);
9985                         irq_sync = 1;
9986                 }
9987
9988                 tg3_full_lock(tp, irq_sync);
9989
9990                 if (epause->autoneg)
9991                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9992                 else
9993                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9994                 if (epause->rx_pause)
9995                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9996                 else
9997                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9998                 if (epause->tx_pause)
9999                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10000                 else
10001                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10002
10003                 if (netif_running(dev)) {
10004                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10005                         err = tg3_restart_hw(tp, 1);
10006                         if (!err)
10007                                 tg3_netif_start(tp);
10008                 }
10009
10010                 tg3_full_unlock(tp);
10011         }
10012
10013         return err;
10014 }
10015
10016 static u32 tg3_get_rx_csum(struct net_device *dev)
10017 {
10018         struct tg3 *tp = netdev_priv(dev);
10019         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10020 }
10021
10022 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10023 {
10024         struct tg3 *tp = netdev_priv(dev);
10025
10026         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10027                 if (data != 0)
10028                         return -EINVAL;
10029                 return 0;
10030         }
10031
10032         spin_lock_bh(&tp->lock);
10033         if (data)
10034                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10035         else
10036                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10037         spin_unlock_bh(&tp->lock);
10038
10039         return 0;
10040 }
10041
10042 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10043 {
10044         struct tg3 *tp = netdev_priv(dev);
10045
10046         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10047                 if (data != 0)
10048                         return -EINVAL;
10049                 return 0;
10050         }
10051
10052         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10053                 ethtool_op_set_tx_ipv6_csum(dev, data);
10054         else
10055                 ethtool_op_set_tx_csum(dev, data);
10056
10057         return 0;
10058 }
10059
10060 static int tg3_get_sset_count(struct net_device *dev, int sset)
10061 {
10062         switch (sset) {
10063         case ETH_SS_TEST:
10064                 return TG3_NUM_TEST;
10065         case ETH_SS_STATS:
10066                 return TG3_NUM_STATS;
10067         default:
10068                 return -EOPNOTSUPP;
10069         }
10070 }
10071
10072 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10073 {
10074         switch (stringset) {
10075         case ETH_SS_STATS:
10076                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10077                 break;
10078         case ETH_SS_TEST:
10079                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10080                 break;
10081         default:
10082                 WARN_ON(1);     /* we need a WARN() */
10083                 break;
10084         }
10085 }
10086
10087 static int tg3_phys_id(struct net_device *dev, u32 data)
10088 {
10089         struct tg3 *tp = netdev_priv(dev);
10090         int i;
10091
10092         if (!netif_running(tp->dev))
10093                 return -EAGAIN;
10094
10095         if (data == 0)
10096                 data = UINT_MAX / 2;
10097
10098         for (i = 0; i < (data * 2); i++) {
10099                 if ((i % 2) == 0)
10100                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10101                                            LED_CTRL_1000MBPS_ON |
10102                                            LED_CTRL_100MBPS_ON |
10103                                            LED_CTRL_10MBPS_ON |
10104                                            LED_CTRL_TRAFFIC_OVERRIDE |
10105                                            LED_CTRL_TRAFFIC_BLINK |
10106                                            LED_CTRL_TRAFFIC_LED);
10107
10108                 else
10109                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10110                                            LED_CTRL_TRAFFIC_OVERRIDE);
10111
10112                 if (msleep_interruptible(500))
10113                         break;
10114         }
10115         tw32(MAC_LED_CTRL, tp->led_ctrl);
10116         return 0;
10117 }
10118
10119 static void tg3_get_ethtool_stats(struct net_device *dev,
10120                                    struct ethtool_stats *estats, u64 *tmp_stats)
10121 {
10122         struct tg3 *tp = netdev_priv(dev);
10123         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10124 }
10125
10126 #define NVRAM_TEST_SIZE 0x100
10127 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10128 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10129 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10130 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10131 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10132
10133 static int tg3_test_nvram(struct tg3 *tp)
10134 {
10135         u32 csum, magic;
10136         __be32 *buf;
10137         int i, j, k, err = 0, size;
10138
10139         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10140                 return 0;
10141
10142         if (tg3_nvram_read(tp, 0, &magic) != 0)
10143                 return -EIO;
10144
10145         if (magic == TG3_EEPROM_MAGIC)
10146                 size = NVRAM_TEST_SIZE;
10147         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10148                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10149                     TG3_EEPROM_SB_FORMAT_1) {
10150                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10151                         case TG3_EEPROM_SB_REVISION_0:
10152                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10153                                 break;
10154                         case TG3_EEPROM_SB_REVISION_2:
10155                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10156                                 break;
10157                         case TG3_EEPROM_SB_REVISION_3:
10158                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10159                                 break;
10160                         default:
10161                                 return 0;
10162                         }
10163                 } else
10164                         return 0;
10165         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10166                 size = NVRAM_SELFBOOT_HW_SIZE;
10167         else
10168                 return -EIO;
10169
10170         buf = kmalloc(size, GFP_KERNEL);
10171         if (buf == NULL)
10172                 return -ENOMEM;
10173
10174         err = -EIO;
10175         for (i = 0, j = 0; i < size; i += 4, j++) {
10176                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10177                 if (err)
10178                         break;
10179         }
10180         if (i < size)
10181                 goto out;
10182
10183         /* Selfboot format */
10184         magic = be32_to_cpu(buf[0]);
10185         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10186             TG3_EEPROM_MAGIC_FW) {
10187                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10188
10189                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10190                     TG3_EEPROM_SB_REVISION_2) {
10191                         /* For rev 2, the csum doesn't include the MBA. */
10192                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10193                                 csum8 += buf8[i];
10194                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10195                                 csum8 += buf8[i];
10196                 } else {
10197                         for (i = 0; i < size; i++)
10198                                 csum8 += buf8[i];
10199                 }
10200
10201                 if (csum8 == 0) {
10202                         err = 0;
10203                         goto out;
10204                 }
10205
10206                 err = -EIO;
10207                 goto out;
10208         }
10209
10210         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10211             TG3_EEPROM_MAGIC_HW) {
10212                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10213                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10214                 u8 *buf8 = (u8 *) buf;
10215
10216                 /* Separate the parity bits and the data bytes.  */
10217                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10218                         if ((i == 0) || (i == 8)) {
10219                                 int l;
10220                                 u8 msk;
10221
10222                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10223                                         parity[k++] = buf8[i] & msk;
10224                                 i++;
10225                         } else if (i == 16) {
10226                                 int l;
10227                                 u8 msk;
10228
10229                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10230                                         parity[k++] = buf8[i] & msk;
10231                                 i++;
10232
10233                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10234                                         parity[k++] = buf8[i] & msk;
10235                                 i++;
10236                         }
10237                         data[j++] = buf8[i];
10238                 }
10239
10240                 err = -EIO;
10241                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10242                         u8 hw8 = hweight8(data[i]);
10243
10244                         if ((hw8 & 0x1) && parity[i])
10245                                 goto out;
10246                         else if (!(hw8 & 0x1) && !parity[i])
10247                                 goto out;
10248                 }
10249                 err = 0;
10250                 goto out;
10251         }
10252
10253         /* Bootstrap checksum at offset 0x10 */
10254         csum = calc_crc((unsigned char *) buf, 0x10);
10255         if (csum != be32_to_cpu(buf[0x10/4]))
10256                 goto out;
10257
10258         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10259         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10260         if (csum != be32_to_cpu(buf[0xfc/4]))
10261                 goto out;
10262
10263         err = 0;
10264
10265 out:
10266         kfree(buf);
10267         return err;
10268 }
10269
10270 #define TG3_SERDES_TIMEOUT_SEC  2
10271 #define TG3_COPPER_TIMEOUT_SEC  6
10272
10273 static int tg3_test_link(struct tg3 *tp)
10274 {
10275         int i, max;
10276
10277         if (!netif_running(tp->dev))
10278                 return -ENODEV;
10279
10280         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10281                 max = TG3_SERDES_TIMEOUT_SEC;
10282         else
10283                 max = TG3_COPPER_TIMEOUT_SEC;
10284
10285         for (i = 0; i < max; i++) {
10286                 if (netif_carrier_ok(tp->dev))
10287                         return 0;
10288
10289                 if (msleep_interruptible(1000))
10290                         break;
10291         }
10292
10293         return -EIO;
10294 }
10295
10296 /* Only test the commonly used registers */
10297 static int tg3_test_registers(struct tg3 *tp)
10298 {
10299         int i, is_5705, is_5750;
10300         u32 offset, read_mask, write_mask, val, save_val, read_val;
10301         static struct {
10302                 u16 offset;
10303                 u16 flags;
10304 #define TG3_FL_5705     0x1
10305 #define TG3_FL_NOT_5705 0x2
10306 #define TG3_FL_NOT_5788 0x4
10307 #define TG3_FL_NOT_5750 0x8
10308                 u32 read_mask;
10309                 u32 write_mask;
10310         } reg_tbl[] = {
10311                 /* MAC Control Registers */
10312                 { MAC_MODE, TG3_FL_NOT_5705,
10313                         0x00000000, 0x00ef6f8c },
10314                 { MAC_MODE, TG3_FL_5705,
10315                         0x00000000, 0x01ef6b8c },
10316                 { MAC_STATUS, TG3_FL_NOT_5705,
10317                         0x03800107, 0x00000000 },
10318                 { MAC_STATUS, TG3_FL_5705,
10319                         0x03800100, 0x00000000 },
10320                 { MAC_ADDR_0_HIGH, 0x0000,
10321                         0x00000000, 0x0000ffff },
10322                 { MAC_ADDR_0_LOW, 0x0000,
10323                         0x00000000, 0xffffffff },
10324                 { MAC_RX_MTU_SIZE, 0x0000,
10325                         0x00000000, 0x0000ffff },
10326                 { MAC_TX_MODE, 0x0000,
10327                         0x00000000, 0x00000070 },
10328                 { MAC_TX_LENGTHS, 0x0000,
10329                         0x00000000, 0x00003fff },
10330                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10331                         0x00000000, 0x000007fc },
10332                 { MAC_RX_MODE, TG3_FL_5705,
10333                         0x00000000, 0x000007dc },
10334                 { MAC_HASH_REG_0, 0x0000,
10335                         0x00000000, 0xffffffff },
10336                 { MAC_HASH_REG_1, 0x0000,
10337                         0x00000000, 0xffffffff },
10338                 { MAC_HASH_REG_2, 0x0000,
10339                         0x00000000, 0xffffffff },
10340                 { MAC_HASH_REG_3, 0x0000,
10341                         0x00000000, 0xffffffff },
10342
10343                 /* Receive Data and Receive BD Initiator Control Registers. */
10344                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10345                         0x00000000, 0xffffffff },
10346                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10347                         0x00000000, 0xffffffff },
10348                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10349                         0x00000000, 0x00000003 },
10350                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10351                         0x00000000, 0xffffffff },
10352                 { RCVDBDI_STD_BD+0, 0x0000,
10353                         0x00000000, 0xffffffff },
10354                 { RCVDBDI_STD_BD+4, 0x0000,
10355                         0x00000000, 0xffffffff },
10356                 { RCVDBDI_STD_BD+8, 0x0000,
10357                         0x00000000, 0xffff0002 },
10358                 { RCVDBDI_STD_BD+0xc, 0x0000,
10359                         0x00000000, 0xffffffff },
10360
10361                 /* Receive BD Initiator Control Registers. */
10362                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10363                         0x00000000, 0xffffffff },
10364                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10365                         0x00000000, 0x000003ff },
10366                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10367                         0x00000000, 0xffffffff },
10368
10369                 /* Host Coalescing Control Registers. */
10370                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10371                         0x00000000, 0x00000004 },
10372                 { HOSTCC_MODE, TG3_FL_5705,
10373                         0x00000000, 0x000000f6 },
10374                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10375                         0x00000000, 0xffffffff },
10376                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10377                         0x00000000, 0x000003ff },
10378                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10379                         0x00000000, 0xffffffff },
10380                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10381                         0x00000000, 0x000003ff },
10382                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10383                         0x00000000, 0xffffffff },
10384                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10385                         0x00000000, 0x000000ff },
10386                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10387                         0x00000000, 0xffffffff },
10388                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10389                         0x00000000, 0x000000ff },
10390                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10391                         0x00000000, 0xffffffff },
10392                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10395                         0x00000000, 0xffffffff },
10396                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10397                         0x00000000, 0x000000ff },
10398                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10399                         0x00000000, 0xffffffff },
10400                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10401                         0x00000000, 0x000000ff },
10402                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10403                         0x00000000, 0xffffffff },
10404                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10407                         0x00000000, 0xffffffff },
10408                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10409                         0x00000000, 0xffffffff },
10410                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10411                         0x00000000, 0xffffffff },
10412                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10413                         0xffffffff, 0x00000000 },
10414                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10415                         0xffffffff, 0x00000000 },
10416
10417                 /* Buffer Manager Control Registers. */
10418                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10419                         0x00000000, 0x007fff80 },
10420                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10421                         0x00000000, 0x007fffff },
10422                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10423                         0x00000000, 0x0000003f },
10424                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10425                         0x00000000, 0x000001ff },
10426                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10427                         0x00000000, 0x000001ff },
10428                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10429                         0xffffffff, 0x00000000 },
10430                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10431                         0xffffffff, 0x00000000 },
10432
10433                 /* Mailbox Registers */
10434                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10435                         0x00000000, 0x000001ff },
10436                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10437                         0x00000000, 0x000001ff },
10438                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10439                         0x00000000, 0x000007ff },
10440                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10441                         0x00000000, 0x000001ff },
10442
10443                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10444         };
10445
10446         is_5705 = is_5750 = 0;
10447         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10448                 is_5705 = 1;
10449                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10450                         is_5750 = 1;
10451         }
10452
10453         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10454                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10455                         continue;
10456
10457                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10458                         continue;
10459
10460                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10461                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10462                         continue;
10463
10464                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10465                         continue;
10466
10467                 offset = (u32) reg_tbl[i].offset;
10468                 read_mask = reg_tbl[i].read_mask;
10469                 write_mask = reg_tbl[i].write_mask;
10470
10471                 /* Save the original register content */
10472                 save_val = tr32(offset);
10473
10474                 /* Determine the read-only value. */
10475                 read_val = save_val & read_mask;
10476
10477                 /* Write zero to the register, then make sure the read-only bits
10478                  * are not changed and the read/write bits are all zeros.
10479                  */
10480                 tw32(offset, 0);
10481
10482                 val = tr32(offset);
10483
10484                 /* Test the read-only and read/write bits. */
10485                 if (((val & read_mask) != read_val) || (val & write_mask))
10486                         goto out;
10487
10488                 /* Write ones to all the bits defined by RdMask and WrMask, then
10489                  * make sure the read-only bits are not changed and the
10490                  * read/write bits are all ones.
10491                  */
10492                 tw32(offset, read_mask | write_mask);
10493
10494                 val = tr32(offset);
10495
10496                 /* Test the read-only bits. */
10497                 if ((val & read_mask) != read_val)
10498                         goto out;
10499
10500                 /* Test the read/write bits. */
10501                 if ((val & write_mask) != write_mask)
10502                         goto out;
10503
10504                 tw32(offset, save_val);
10505         }
10506
10507         return 0;
10508
10509 out:
10510         if (netif_msg_hw(tp))
10511                 netdev_err(tp->dev,
10512                            "Register test failed at offset %x\n", offset);
10513         tw32(offset, save_val);
10514         return -EIO;
10515 }
10516
10517 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10518 {
10519         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10520         int i;
10521         u32 j;
10522
10523         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10524                 for (j = 0; j < len; j += 4) {
10525                         u32 val;
10526
10527                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10528                         tg3_read_mem(tp, offset + j, &val);
10529                         if (val != test_pattern[i])
10530                                 return -EIO;
10531                 }
10532         }
10533         return 0;
10534 }
10535
10536 static int tg3_test_memory(struct tg3 *tp)
10537 {
10538         static struct mem_entry {
10539                 u32 offset;
10540                 u32 len;
10541         } mem_tbl_570x[] = {
10542                 { 0x00000000, 0x00b50},
10543                 { 0x00002000, 0x1c000},
10544                 { 0xffffffff, 0x00000}
10545         }, mem_tbl_5705[] = {
10546                 { 0x00000100, 0x0000c},
10547                 { 0x00000200, 0x00008},
10548                 { 0x00004000, 0x00800},
10549                 { 0x00006000, 0x01000},
10550                 { 0x00008000, 0x02000},
10551                 { 0x00010000, 0x0e000},
10552                 { 0xffffffff, 0x00000}
10553         }, mem_tbl_5755[] = {
10554                 { 0x00000200, 0x00008},
10555                 { 0x00004000, 0x00800},
10556                 { 0x00006000, 0x00800},
10557                 { 0x00008000, 0x02000},
10558                 { 0x00010000, 0x0c000},
10559                 { 0xffffffff, 0x00000}
10560         }, mem_tbl_5906[] = {
10561                 { 0x00000200, 0x00008},
10562                 { 0x00004000, 0x00400},
10563                 { 0x00006000, 0x00400},
10564                 { 0x00008000, 0x01000},
10565                 { 0x00010000, 0x01000},
10566                 { 0xffffffff, 0x00000}
10567         }, mem_tbl_5717[] = {
10568                 { 0x00000200, 0x00008},
10569                 { 0x00010000, 0x0a000},
10570                 { 0x00020000, 0x13c00},
10571                 { 0xffffffff, 0x00000}
10572         }, mem_tbl_57765[] = {
10573                 { 0x00000200, 0x00008},
10574                 { 0x00004000, 0x00800},
10575                 { 0x00006000, 0x09800},
10576                 { 0x00010000, 0x0a000},
10577                 { 0xffffffff, 0x00000}
10578         };
10579         struct mem_entry *mem_tbl;
10580         int err = 0;
10581         int i;
10582
10583         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10584                 mem_tbl = mem_tbl_5717;
10585         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10586                 mem_tbl = mem_tbl_57765;
10587         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10588                 mem_tbl = mem_tbl_5755;
10589         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10590                 mem_tbl = mem_tbl_5906;
10591         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10592                 mem_tbl = mem_tbl_5705;
10593         else
10594                 mem_tbl = mem_tbl_570x;
10595
10596         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10597                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10598                     mem_tbl[i].len)) != 0)
10599                         break;
10600         }
10601
10602         return err;
10603 }
10604
10605 #define TG3_MAC_LOOPBACK        0
10606 #define TG3_PHY_LOOPBACK        1
10607
10608 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10609 {
10610         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10611         u32 desc_idx, coal_now;
10612         struct sk_buff *skb, *rx_skb;
10613         u8 *tx_data;
10614         dma_addr_t map;
10615         int num_pkts, tx_len, rx_len, i, err;
10616         struct tg3_rx_buffer_desc *desc;
10617         struct tg3_napi *tnapi, *rnapi;
10618         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10619
10620         tnapi = &tp->napi[0];
10621         rnapi = &tp->napi[0];
10622         if (tp->irq_cnt > 1) {
10623                 rnapi = &tp->napi[1];
10624                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10625                         tnapi = &tp->napi[1];
10626         }
10627         coal_now = tnapi->coal_now | rnapi->coal_now;
10628
10629         if (loopback_mode == TG3_MAC_LOOPBACK) {
10630                 /* HW errata - mac loopback fails in some cases on 5780.
10631                  * Normal traffic and PHY loopback are not affected by
10632                  * errata.
10633                  */
10634                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10635                         return 0;
10636
10637                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10638                            MAC_MODE_PORT_INT_LPBACK;
10639                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10640                         mac_mode |= MAC_MODE_LINK_POLARITY;
10641                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10642                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10643                 else
10644                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10645                 tw32(MAC_MODE, mac_mode);
10646         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10647                 u32 val;
10648
10649                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10650                         tg3_phy_fet_toggle_apd(tp, false);
10651                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10652                 } else
10653                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10654
10655                 tg3_phy_toggle_automdix(tp, 0);
10656
10657                 tg3_writephy(tp, MII_BMCR, val);
10658                 udelay(40);
10659
10660                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10661                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10662                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10663                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10664                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10665                         /* The write needs to be flushed for the AC131 */
10666                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10667                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10668                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10669                 } else
10670                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10671
10672                 /* reset to prevent losing 1st rx packet intermittently */
10673                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10674                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10675                         udelay(10);
10676                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10677                 }
10678                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10679                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10680                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10681                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10682                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10683                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10684                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10685                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10686                 }
10687                 tw32(MAC_MODE, mac_mode);
10688         } else {
10689                 return -EINVAL;
10690         }
10691
10692         err = -EIO;
10693
10694         tx_len = 1514;
10695         skb = netdev_alloc_skb(tp->dev, tx_len);
10696         if (!skb)
10697                 return -ENOMEM;
10698
10699         tx_data = skb_put(skb, tx_len);
10700         memcpy(tx_data, tp->dev->dev_addr, 6);
10701         memset(tx_data + 6, 0x0, 8);
10702
10703         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10704
10705         for (i = 14; i < tx_len; i++)
10706                 tx_data[i] = (u8) (i & 0xff);
10707
10708         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10709         if (pci_dma_mapping_error(tp->pdev, map)) {
10710                 dev_kfree_skb(skb);
10711                 return -EIO;
10712         }
10713
10714         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10715                rnapi->coal_now);
10716
10717         udelay(10);
10718
10719         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10720
10721         num_pkts = 0;
10722
10723         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10724
10725         tnapi->tx_prod++;
10726         num_pkts++;
10727
10728         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10729         tr32_mailbox(tnapi->prodmbox);
10730
10731         udelay(10);
10732
10733         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10734         for (i = 0; i < 35; i++) {
10735                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10736                        coal_now);
10737
10738                 udelay(10);
10739
10740                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10741                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10742                 if ((tx_idx == tnapi->tx_prod) &&
10743                     (rx_idx == (rx_start_idx + num_pkts)))
10744                         break;
10745         }
10746
10747         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10748         dev_kfree_skb(skb);
10749
10750         if (tx_idx != tnapi->tx_prod)
10751                 goto out;
10752
10753         if (rx_idx != rx_start_idx + num_pkts)
10754                 goto out;
10755
10756         desc = &rnapi->rx_rcb[rx_start_idx];
10757         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10758         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10759         if (opaque_key != RXD_OPAQUE_RING_STD)
10760                 goto out;
10761
10762         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10763             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10764                 goto out;
10765
10766         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10767         if (rx_len != tx_len)
10768                 goto out;
10769
10770         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10771
10772         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10773         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10774
10775         for (i = 14; i < tx_len; i++) {
10776                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10777                         goto out;
10778         }
10779         err = 0;
10780
10781         /* tg3_free_rings will unmap and free the rx_skb */
10782 out:
10783         return err;
10784 }
10785
10786 #define TG3_MAC_LOOPBACK_FAILED         1
10787 #define TG3_PHY_LOOPBACK_FAILED         2
10788 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10789                                          TG3_PHY_LOOPBACK_FAILED)
10790
10791 static int tg3_test_loopback(struct tg3 *tp)
10792 {
10793         int err = 0;
10794         u32 cpmuctrl = 0;
10795
10796         if (!netif_running(tp->dev))
10797                 return TG3_LOOPBACK_FAILED;
10798
10799         err = tg3_reset_hw(tp, 1);
10800         if (err)
10801                 return TG3_LOOPBACK_FAILED;
10802
10803         /* Turn off gphy autopowerdown. */
10804         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10805                 tg3_phy_toggle_apd(tp, false);
10806
10807         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10808                 int i;
10809                 u32 status;
10810
10811                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10812
10813                 /* Wait for up to 40 microseconds to acquire lock. */
10814                 for (i = 0; i < 4; i++) {
10815                         status = tr32(TG3_CPMU_MUTEX_GNT);
10816                         if (status == CPMU_MUTEX_GNT_DRIVER)
10817                                 break;
10818                         udelay(10);
10819                 }
10820
10821                 if (status != CPMU_MUTEX_GNT_DRIVER)
10822                         return TG3_LOOPBACK_FAILED;
10823
10824                 /* Turn off link-based power management. */
10825                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10826                 tw32(TG3_CPMU_CTRL,
10827                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10828                                   CPMU_CTRL_LINK_AWARE_MODE));
10829         }
10830
10831         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10832                 err |= TG3_MAC_LOOPBACK_FAILED;
10833
10834         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10835                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10836
10837                 /* Release the mutex */
10838                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10839         }
10840
10841         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10842             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10843                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10844                         err |= TG3_PHY_LOOPBACK_FAILED;
10845         }
10846
10847         /* Re-enable gphy autopowerdown. */
10848         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10849                 tg3_phy_toggle_apd(tp, true);
10850
10851         return err;
10852 }
10853
10854 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10855                           u64 *data)
10856 {
10857         struct tg3 *tp = netdev_priv(dev);
10858
10859         if (tp->link_config.phy_is_low_power)
10860                 tg3_set_power_state(tp, PCI_D0);
10861
10862         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10863
10864         if (tg3_test_nvram(tp) != 0) {
10865                 etest->flags |= ETH_TEST_FL_FAILED;
10866                 data[0] = 1;
10867         }
10868         if (tg3_test_link(tp) != 0) {
10869                 etest->flags |= ETH_TEST_FL_FAILED;
10870                 data[1] = 1;
10871         }
10872         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10873                 int err, err2 = 0, irq_sync = 0;
10874
10875                 if (netif_running(dev)) {
10876                         tg3_phy_stop(tp);
10877                         tg3_netif_stop(tp);
10878                         irq_sync = 1;
10879                 }
10880
10881                 tg3_full_lock(tp, irq_sync);
10882
10883                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10884                 err = tg3_nvram_lock(tp);
10885                 tg3_halt_cpu(tp, RX_CPU_BASE);
10886                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10887                         tg3_halt_cpu(tp, TX_CPU_BASE);
10888                 if (!err)
10889                         tg3_nvram_unlock(tp);
10890
10891                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10892                         tg3_phy_reset(tp);
10893
10894                 if (tg3_test_registers(tp) != 0) {
10895                         etest->flags |= ETH_TEST_FL_FAILED;
10896                         data[2] = 1;
10897                 }
10898                 if (tg3_test_memory(tp) != 0) {
10899                         etest->flags |= ETH_TEST_FL_FAILED;
10900                         data[3] = 1;
10901                 }
10902                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10903                         etest->flags |= ETH_TEST_FL_FAILED;
10904
10905                 tg3_full_unlock(tp);
10906
10907                 if (tg3_test_interrupt(tp) != 0) {
10908                         etest->flags |= ETH_TEST_FL_FAILED;
10909                         data[5] = 1;
10910                 }
10911
10912                 tg3_full_lock(tp, 0);
10913
10914                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10915                 if (netif_running(dev)) {
10916                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10917                         err2 = tg3_restart_hw(tp, 1);
10918                         if (!err2)
10919                                 tg3_netif_start(tp);
10920                 }
10921
10922                 tg3_full_unlock(tp);
10923
10924                 if (irq_sync && !err2)
10925                         tg3_phy_start(tp);
10926         }
10927         if (tp->link_config.phy_is_low_power)
10928                 tg3_set_power_state(tp, PCI_D3hot);
10929
10930 }
10931
10932 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10933 {
10934         struct mii_ioctl_data *data = if_mii(ifr);
10935         struct tg3 *tp = netdev_priv(dev);
10936         int err;
10937
10938         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10939                 struct phy_device *phydev;
10940                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10941                         return -EAGAIN;
10942                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10943                 return phy_mii_ioctl(phydev, data, cmd);
10944         }
10945
10946         switch (cmd) {
10947         case SIOCGMIIPHY:
10948                 data->phy_id = tp->phy_addr;
10949
10950                 /* fallthru */
10951         case SIOCGMIIREG: {
10952                 u32 mii_regval;
10953
10954                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10955                         break;                  /* We have no PHY */
10956
10957                 if (tp->link_config.phy_is_low_power)
10958                         return -EAGAIN;
10959
10960                 spin_lock_bh(&tp->lock);
10961                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10962                 spin_unlock_bh(&tp->lock);
10963
10964                 data->val_out = mii_regval;
10965
10966                 return err;
10967         }
10968
10969         case SIOCSMIIREG:
10970                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10971                         break;                  /* We have no PHY */
10972
10973                 if (tp->link_config.phy_is_low_power)
10974                         return -EAGAIN;
10975
10976                 spin_lock_bh(&tp->lock);
10977                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10978                 spin_unlock_bh(&tp->lock);
10979
10980                 return err;
10981
10982         default:
10983                 /* do nothing */
10984                 break;
10985         }
10986         return -EOPNOTSUPP;
10987 }
10988
10989 #if TG3_VLAN_TAG_USED
10990 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10991 {
10992         struct tg3 *tp = netdev_priv(dev);
10993
10994         if (!netif_running(dev)) {
10995                 tp->vlgrp = grp;
10996                 return;
10997         }
10998
10999         tg3_netif_stop(tp);
11000
11001         tg3_full_lock(tp, 0);
11002
11003         tp->vlgrp = grp;
11004
11005         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11006         __tg3_set_rx_mode(dev);
11007
11008         tg3_netif_start(tp);
11009
11010         tg3_full_unlock(tp);
11011 }
11012 #endif
11013
11014 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11015 {
11016         struct tg3 *tp = netdev_priv(dev);
11017
11018         memcpy(ec, &tp->coal, sizeof(*ec));
11019         return 0;
11020 }
11021
11022 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11023 {
11024         struct tg3 *tp = netdev_priv(dev);
11025         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11026         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11027
11028         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11029                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11030                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11031                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11032                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11033         }
11034
11035         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11036             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11037             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11038             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11039             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11040             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11041             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11042             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11043             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11044             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11045                 return -EINVAL;
11046
11047         /* No rx interrupts will be generated if both are zero */
11048         if ((ec->rx_coalesce_usecs == 0) &&
11049             (ec->rx_max_coalesced_frames == 0))
11050                 return -EINVAL;
11051
11052         /* No tx interrupts will be generated if both are zero */
11053         if ((ec->tx_coalesce_usecs == 0) &&
11054             (ec->tx_max_coalesced_frames == 0))
11055                 return -EINVAL;
11056
11057         /* Only copy relevant parameters, ignore all others. */
11058         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11059         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11060         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11061         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11062         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11063         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11064         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11065         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11066         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11067
11068         if (netif_running(dev)) {
11069                 tg3_full_lock(tp, 0);
11070                 __tg3_set_coalesce(tp, &tp->coal);
11071                 tg3_full_unlock(tp);
11072         }
11073         return 0;
11074 }
11075
11076 static const struct ethtool_ops tg3_ethtool_ops = {
11077         .get_settings           = tg3_get_settings,
11078         .set_settings           = tg3_set_settings,
11079         .get_drvinfo            = tg3_get_drvinfo,
11080         .get_regs_len           = tg3_get_regs_len,
11081         .get_regs               = tg3_get_regs,
11082         .get_wol                = tg3_get_wol,
11083         .set_wol                = tg3_set_wol,
11084         .get_msglevel           = tg3_get_msglevel,
11085         .set_msglevel           = tg3_set_msglevel,
11086         .nway_reset             = tg3_nway_reset,
11087         .get_link               = ethtool_op_get_link,
11088         .get_eeprom_len         = tg3_get_eeprom_len,
11089         .get_eeprom             = tg3_get_eeprom,
11090         .set_eeprom             = tg3_set_eeprom,
11091         .get_ringparam          = tg3_get_ringparam,
11092         .set_ringparam          = tg3_set_ringparam,
11093         .get_pauseparam         = tg3_get_pauseparam,
11094         .set_pauseparam         = tg3_set_pauseparam,
11095         .get_rx_csum            = tg3_get_rx_csum,
11096         .set_rx_csum            = tg3_set_rx_csum,
11097         .set_tx_csum            = tg3_set_tx_csum,
11098         .set_sg                 = ethtool_op_set_sg,
11099         .set_tso                = tg3_set_tso,
11100         .self_test              = tg3_self_test,
11101         .get_strings            = tg3_get_strings,
11102         .phys_id                = tg3_phys_id,
11103         .get_ethtool_stats      = tg3_get_ethtool_stats,
11104         .get_coalesce           = tg3_get_coalesce,
11105         .set_coalesce           = tg3_set_coalesce,
11106         .get_sset_count         = tg3_get_sset_count,
11107 };
11108
11109 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11110 {
11111         u32 cursize, val, magic;
11112
11113         tp->nvram_size = EEPROM_CHIP_SIZE;
11114
11115         if (tg3_nvram_read(tp, 0, &magic) != 0)
11116                 return;
11117
11118         if ((magic != TG3_EEPROM_MAGIC) &&
11119             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11120             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11121                 return;
11122
11123         /*
11124          * Size the chip by reading offsets at increasing powers of two.
11125          * When we encounter our validation signature, we know the addressing
11126          * has wrapped around, and thus have our chip size.
11127          */
11128         cursize = 0x10;
11129
11130         while (cursize < tp->nvram_size) {
11131                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11132                         return;
11133
11134                 if (val == magic)
11135                         break;
11136
11137                 cursize <<= 1;
11138         }
11139
11140         tp->nvram_size = cursize;
11141 }
11142
11143 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11144 {
11145         u32 val;
11146
11147         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11148             tg3_nvram_read(tp, 0, &val) != 0)
11149                 return;
11150
11151         /* Selfboot format */
11152         if (val != TG3_EEPROM_MAGIC) {
11153                 tg3_get_eeprom_size(tp);
11154                 return;
11155         }
11156
11157         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11158                 if (val != 0) {
11159                         /* This is confusing.  We want to operate on the
11160                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11161                          * call will read from NVRAM and byteswap the data
11162                          * according to the byteswapping settings for all
11163                          * other register accesses.  This ensures the data we
11164                          * want will always reside in the lower 16-bits.
11165                          * However, the data in NVRAM is in LE format, which
11166                          * means the data from the NVRAM read will always be
11167                          * opposite the endianness of the CPU.  The 16-bit
11168                          * byteswap then brings the data to CPU endianness.
11169                          */
11170                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11171                         return;
11172                 }
11173         }
11174         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11175 }
11176
11177 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11178 {
11179         u32 nvcfg1;
11180
11181         nvcfg1 = tr32(NVRAM_CFG1);
11182         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11183                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11184         } else {
11185                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11186                 tw32(NVRAM_CFG1, nvcfg1);
11187         }
11188
11189         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11190             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11191                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11192                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11193                         tp->nvram_jedecnum = JEDEC_ATMEL;
11194                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11195                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11196                         break;
11197                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11198                         tp->nvram_jedecnum = JEDEC_ATMEL;
11199                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11200                         break;
11201                 case FLASH_VENDOR_ATMEL_EEPROM:
11202                         tp->nvram_jedecnum = JEDEC_ATMEL;
11203                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11204                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11205                         break;
11206                 case FLASH_VENDOR_ST:
11207                         tp->nvram_jedecnum = JEDEC_ST;
11208                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11209                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11210                         break;
11211                 case FLASH_VENDOR_SAIFUN:
11212                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11213                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11214                         break;
11215                 case FLASH_VENDOR_SST_SMALL:
11216                 case FLASH_VENDOR_SST_LARGE:
11217                         tp->nvram_jedecnum = JEDEC_SST;
11218                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11219                         break;
11220                 }
11221         } else {
11222                 tp->nvram_jedecnum = JEDEC_ATMEL;
11223                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11224                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11225         }
11226 }
11227
11228 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11229 {
11230         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11231         case FLASH_5752PAGE_SIZE_256:
11232                 tp->nvram_pagesize = 256;
11233                 break;
11234         case FLASH_5752PAGE_SIZE_512:
11235                 tp->nvram_pagesize = 512;
11236                 break;
11237         case FLASH_5752PAGE_SIZE_1K:
11238                 tp->nvram_pagesize = 1024;
11239                 break;
11240         case FLASH_5752PAGE_SIZE_2K:
11241                 tp->nvram_pagesize = 2048;
11242                 break;
11243         case FLASH_5752PAGE_SIZE_4K:
11244                 tp->nvram_pagesize = 4096;
11245                 break;
11246         case FLASH_5752PAGE_SIZE_264:
11247                 tp->nvram_pagesize = 264;
11248                 break;
11249         case FLASH_5752PAGE_SIZE_528:
11250                 tp->nvram_pagesize = 528;
11251                 break;
11252         }
11253 }
11254
11255 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11256 {
11257         u32 nvcfg1;
11258
11259         nvcfg1 = tr32(NVRAM_CFG1);
11260
11261         /* NVRAM protection for TPM */
11262         if (nvcfg1 & (1 << 27))
11263                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11264
11265         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11266         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11267         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11268                 tp->nvram_jedecnum = JEDEC_ATMEL;
11269                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11270                 break;
11271         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11272                 tp->nvram_jedecnum = JEDEC_ATMEL;
11273                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11274                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11275                 break;
11276         case FLASH_5752VENDOR_ST_M45PE10:
11277         case FLASH_5752VENDOR_ST_M45PE20:
11278         case FLASH_5752VENDOR_ST_M45PE40:
11279                 tp->nvram_jedecnum = JEDEC_ST;
11280                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11281                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11282                 break;
11283         }
11284
11285         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11286                 tg3_nvram_get_pagesize(tp, nvcfg1);
11287         } else {
11288                 /* For eeprom, set pagesize to maximum eeprom size */
11289                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11290
11291                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11292                 tw32(NVRAM_CFG1, nvcfg1);
11293         }
11294 }
11295
11296 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11297 {
11298         u32 nvcfg1, protect = 0;
11299
11300         nvcfg1 = tr32(NVRAM_CFG1);
11301
11302         /* NVRAM protection for TPM */
11303         if (nvcfg1 & (1 << 27)) {
11304                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11305                 protect = 1;
11306         }
11307
11308         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11309         switch (nvcfg1) {
11310         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11311         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11312         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11313         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11314                 tp->nvram_jedecnum = JEDEC_ATMEL;
11315                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11316                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11317                 tp->nvram_pagesize = 264;
11318                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11319                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11320                         tp->nvram_size = (protect ? 0x3e200 :
11321                                           TG3_NVRAM_SIZE_512KB);
11322                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11323                         tp->nvram_size = (protect ? 0x1f200 :
11324                                           TG3_NVRAM_SIZE_256KB);
11325                 else
11326                         tp->nvram_size = (protect ? 0x1f200 :
11327                                           TG3_NVRAM_SIZE_128KB);
11328                 break;
11329         case FLASH_5752VENDOR_ST_M45PE10:
11330         case FLASH_5752VENDOR_ST_M45PE20:
11331         case FLASH_5752VENDOR_ST_M45PE40:
11332                 tp->nvram_jedecnum = JEDEC_ST;
11333                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11334                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11335                 tp->nvram_pagesize = 256;
11336                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11337                         tp->nvram_size = (protect ?
11338                                           TG3_NVRAM_SIZE_64KB :
11339                                           TG3_NVRAM_SIZE_128KB);
11340                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11341                         tp->nvram_size = (protect ?
11342                                           TG3_NVRAM_SIZE_64KB :
11343                                           TG3_NVRAM_SIZE_256KB);
11344                 else
11345                         tp->nvram_size = (protect ?
11346                                           TG3_NVRAM_SIZE_128KB :
11347                                           TG3_NVRAM_SIZE_512KB);
11348                 break;
11349         }
11350 }
11351
11352 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11353 {
11354         u32 nvcfg1;
11355
11356         nvcfg1 = tr32(NVRAM_CFG1);
11357
11358         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11359         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11360         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11361         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11362         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11363                 tp->nvram_jedecnum = JEDEC_ATMEL;
11364                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11365                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11366
11367                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11368                 tw32(NVRAM_CFG1, nvcfg1);
11369                 break;
11370         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11371         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11372         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11373         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11374                 tp->nvram_jedecnum = JEDEC_ATMEL;
11375                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11376                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11377                 tp->nvram_pagesize = 264;
11378                 break;
11379         case FLASH_5752VENDOR_ST_M45PE10:
11380         case FLASH_5752VENDOR_ST_M45PE20:
11381         case FLASH_5752VENDOR_ST_M45PE40:
11382                 tp->nvram_jedecnum = JEDEC_ST;
11383                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11384                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11385                 tp->nvram_pagesize = 256;
11386                 break;
11387         }
11388 }
11389
11390 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11391 {
11392         u32 nvcfg1, protect = 0;
11393
11394         nvcfg1 = tr32(NVRAM_CFG1);
11395
11396         /* NVRAM protection for TPM */
11397         if (nvcfg1 & (1 << 27)) {
11398                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11399                 protect = 1;
11400         }
11401
11402         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11403         switch (nvcfg1) {
11404         case FLASH_5761VENDOR_ATMEL_ADB021D:
11405         case FLASH_5761VENDOR_ATMEL_ADB041D:
11406         case FLASH_5761VENDOR_ATMEL_ADB081D:
11407         case FLASH_5761VENDOR_ATMEL_ADB161D:
11408         case FLASH_5761VENDOR_ATMEL_MDB021D:
11409         case FLASH_5761VENDOR_ATMEL_MDB041D:
11410         case FLASH_5761VENDOR_ATMEL_MDB081D:
11411         case FLASH_5761VENDOR_ATMEL_MDB161D:
11412                 tp->nvram_jedecnum = JEDEC_ATMEL;
11413                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11414                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11415                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11416                 tp->nvram_pagesize = 256;
11417                 break;
11418         case FLASH_5761VENDOR_ST_A_M45PE20:
11419         case FLASH_5761VENDOR_ST_A_M45PE40:
11420         case FLASH_5761VENDOR_ST_A_M45PE80:
11421         case FLASH_5761VENDOR_ST_A_M45PE16:
11422         case FLASH_5761VENDOR_ST_M_M45PE20:
11423         case FLASH_5761VENDOR_ST_M_M45PE40:
11424         case FLASH_5761VENDOR_ST_M_M45PE80:
11425         case FLASH_5761VENDOR_ST_M_M45PE16:
11426                 tp->nvram_jedecnum = JEDEC_ST;
11427                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11428                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11429                 tp->nvram_pagesize = 256;
11430                 break;
11431         }
11432
11433         if (protect) {
11434                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11435         } else {
11436                 switch (nvcfg1) {
11437                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11438                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11439                 case FLASH_5761VENDOR_ST_A_M45PE16:
11440                 case FLASH_5761VENDOR_ST_M_M45PE16:
11441                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11442                         break;
11443                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11444                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11445                 case FLASH_5761VENDOR_ST_A_M45PE80:
11446                 case FLASH_5761VENDOR_ST_M_M45PE80:
11447                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11448                         break;
11449                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11450                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11451                 case FLASH_5761VENDOR_ST_A_M45PE40:
11452                 case FLASH_5761VENDOR_ST_M_M45PE40:
11453                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11454                         break;
11455                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11456                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11457                 case FLASH_5761VENDOR_ST_A_M45PE20:
11458                 case FLASH_5761VENDOR_ST_M_M45PE20:
11459                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11460                         break;
11461                 }
11462         }
11463 }
11464
11465 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11466 {
11467         tp->nvram_jedecnum = JEDEC_ATMEL;
11468         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11469         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11470 }
11471
11472 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11473 {
11474         u32 nvcfg1;
11475
11476         nvcfg1 = tr32(NVRAM_CFG1);
11477
11478         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11479         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11480         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11481                 tp->nvram_jedecnum = JEDEC_ATMEL;
11482                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11483                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11484
11485                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11486                 tw32(NVRAM_CFG1, nvcfg1);
11487                 return;
11488         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11489         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11490         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11491         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11492         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11493         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11494         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11495                 tp->nvram_jedecnum = JEDEC_ATMEL;
11496                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11497                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11498
11499                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11500                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11501                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11502                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11503                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11504                         break;
11505                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11506                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11507                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11508                         break;
11509                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11510                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11511                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11512                         break;
11513                 }
11514                 break;
11515         case FLASH_5752VENDOR_ST_M45PE10:
11516         case FLASH_5752VENDOR_ST_M45PE20:
11517         case FLASH_5752VENDOR_ST_M45PE40:
11518                 tp->nvram_jedecnum = JEDEC_ST;
11519                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11520                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11521
11522                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11523                 case FLASH_5752VENDOR_ST_M45PE10:
11524                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11525                         break;
11526                 case FLASH_5752VENDOR_ST_M45PE20:
11527                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11528                         break;
11529                 case FLASH_5752VENDOR_ST_M45PE40:
11530                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11531                         break;
11532                 }
11533                 break;
11534         default:
11535                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11536                 return;
11537         }
11538
11539         tg3_nvram_get_pagesize(tp, nvcfg1);
11540         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11541                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11542 }
11543
11544
11545 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11546 {
11547         u32 nvcfg1;
11548
11549         nvcfg1 = tr32(NVRAM_CFG1);
11550
11551         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11552         case FLASH_5717VENDOR_ATMEL_EEPROM:
11553         case FLASH_5717VENDOR_MICRO_EEPROM:
11554                 tp->nvram_jedecnum = JEDEC_ATMEL;
11555                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11556                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11557
11558                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11559                 tw32(NVRAM_CFG1, nvcfg1);
11560                 return;
11561         case FLASH_5717VENDOR_ATMEL_MDB011D:
11562         case FLASH_5717VENDOR_ATMEL_ADB011B:
11563         case FLASH_5717VENDOR_ATMEL_ADB011D:
11564         case FLASH_5717VENDOR_ATMEL_MDB021D:
11565         case FLASH_5717VENDOR_ATMEL_ADB021B:
11566         case FLASH_5717VENDOR_ATMEL_ADB021D:
11567         case FLASH_5717VENDOR_ATMEL_45USPT:
11568                 tp->nvram_jedecnum = JEDEC_ATMEL;
11569                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11570                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11571
11572                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11573                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11574                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11575                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11576                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11577                         break;
11578                 default:
11579                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11580                         break;
11581                 }
11582                 break;
11583         case FLASH_5717VENDOR_ST_M_M25PE10:
11584         case FLASH_5717VENDOR_ST_A_M25PE10:
11585         case FLASH_5717VENDOR_ST_M_M45PE10:
11586         case FLASH_5717VENDOR_ST_A_M45PE10:
11587         case FLASH_5717VENDOR_ST_M_M25PE20:
11588         case FLASH_5717VENDOR_ST_A_M25PE20:
11589         case FLASH_5717VENDOR_ST_M_M45PE20:
11590         case FLASH_5717VENDOR_ST_A_M45PE20:
11591         case FLASH_5717VENDOR_ST_25USPT:
11592         case FLASH_5717VENDOR_ST_45USPT:
11593                 tp->nvram_jedecnum = JEDEC_ST;
11594                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11595                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11596
11597                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11598                 case FLASH_5717VENDOR_ST_M_M25PE20:
11599                 case FLASH_5717VENDOR_ST_A_M25PE20:
11600                 case FLASH_5717VENDOR_ST_M_M45PE20:
11601                 case FLASH_5717VENDOR_ST_A_M45PE20:
11602                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11603                         break;
11604                 default:
11605                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11606                         break;
11607                 }
11608                 break;
11609         default:
11610                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11611                 return;
11612         }
11613
11614         tg3_nvram_get_pagesize(tp, nvcfg1);
11615         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11616                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11617 }
11618
11619 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11620 static void __devinit tg3_nvram_init(struct tg3 *tp)
11621 {
11622         tw32_f(GRC_EEPROM_ADDR,
11623              (EEPROM_ADDR_FSM_RESET |
11624               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11625                EEPROM_ADDR_CLKPERD_SHIFT)));
11626
11627         msleep(1);
11628
11629         /* Enable seeprom accesses. */
11630         tw32_f(GRC_LOCAL_CTRL,
11631              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11632         udelay(100);
11633
11634         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11635             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11636                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11637
11638                 if (tg3_nvram_lock(tp)) {
11639                         netdev_warn(tp->dev,
11640                                     "Cannot get nvram lock, %s failed\n",
11641                                     __func__);
11642                         return;
11643                 }
11644                 tg3_enable_nvram_access(tp);
11645
11646                 tp->nvram_size = 0;
11647
11648                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11649                         tg3_get_5752_nvram_info(tp);
11650                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11651                         tg3_get_5755_nvram_info(tp);
11652                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11653                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11654                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11655                         tg3_get_5787_nvram_info(tp);
11656                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11657                         tg3_get_5761_nvram_info(tp);
11658                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11659                         tg3_get_5906_nvram_info(tp);
11660                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11661                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11662                         tg3_get_57780_nvram_info(tp);
11663                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11664                         tg3_get_5717_nvram_info(tp);
11665                 else
11666                         tg3_get_nvram_info(tp);
11667
11668                 if (tp->nvram_size == 0)
11669                         tg3_get_nvram_size(tp);
11670
11671                 tg3_disable_nvram_access(tp);
11672                 tg3_nvram_unlock(tp);
11673
11674         } else {
11675                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11676
11677                 tg3_get_eeprom_size(tp);
11678         }
11679 }
11680
11681 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11682                                     u32 offset, u32 len, u8 *buf)
11683 {
11684         int i, j, rc = 0;
11685         u32 val;
11686
11687         for (i = 0; i < len; i += 4) {
11688                 u32 addr;
11689                 __be32 data;
11690
11691                 addr = offset + i;
11692
11693                 memcpy(&data, buf + i, 4);
11694
11695                 /*
11696                  * The SEEPROM interface expects the data to always be opposite
11697                  * the native endian format.  We accomplish this by reversing
11698                  * all the operations that would have been performed on the
11699                  * data from a call to tg3_nvram_read_be32().
11700                  */
11701                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11702
11703                 val = tr32(GRC_EEPROM_ADDR);
11704                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11705
11706                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11707                         EEPROM_ADDR_READ);
11708                 tw32(GRC_EEPROM_ADDR, val |
11709                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11710                         (addr & EEPROM_ADDR_ADDR_MASK) |
11711                         EEPROM_ADDR_START |
11712                         EEPROM_ADDR_WRITE);
11713
11714                 for (j = 0; j < 1000; j++) {
11715                         val = tr32(GRC_EEPROM_ADDR);
11716
11717                         if (val & EEPROM_ADDR_COMPLETE)
11718                                 break;
11719                         msleep(1);
11720                 }
11721                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11722                         rc = -EBUSY;
11723                         break;
11724                 }
11725         }
11726
11727         return rc;
11728 }
11729
11730 /* offset and length are dword aligned */
11731 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11732                 u8 *buf)
11733 {
11734         int ret = 0;
11735         u32 pagesize = tp->nvram_pagesize;
11736         u32 pagemask = pagesize - 1;
11737         u32 nvram_cmd;
11738         u8 *tmp;
11739
11740         tmp = kmalloc(pagesize, GFP_KERNEL);
11741         if (tmp == NULL)
11742                 return -ENOMEM;
11743
11744         while (len) {
11745                 int j;
11746                 u32 phy_addr, page_off, size;
11747
11748                 phy_addr = offset & ~pagemask;
11749
11750                 for (j = 0; j < pagesize; j += 4) {
11751                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11752                                                   (__be32 *) (tmp + j));
11753                         if (ret)
11754                                 break;
11755                 }
11756                 if (ret)
11757                         break;
11758
11759                 page_off = offset & pagemask;
11760                 size = pagesize;
11761                 if (len < size)
11762                         size = len;
11763
11764                 len -= size;
11765
11766                 memcpy(tmp + page_off, buf, size);
11767
11768                 offset = offset + (pagesize - page_off);
11769
11770                 tg3_enable_nvram_access(tp);
11771
11772                 /*
11773                  * Before we can erase the flash page, we need
11774                  * to issue a special "write enable" command.
11775                  */
11776                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11777
11778                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11779                         break;
11780
11781                 /* Erase the target page */
11782                 tw32(NVRAM_ADDR, phy_addr);
11783
11784                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11785                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11786
11787                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11788                         break;
11789
11790                 /* Issue another write enable to start the write. */
11791                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11792
11793                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11794                         break;
11795
11796                 for (j = 0; j < pagesize; j += 4) {
11797                         __be32 data;
11798
11799                         data = *((__be32 *) (tmp + j));
11800
11801                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11802
11803                         tw32(NVRAM_ADDR, phy_addr + j);
11804
11805                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11806                                 NVRAM_CMD_WR;
11807
11808                         if (j == 0)
11809                                 nvram_cmd |= NVRAM_CMD_FIRST;
11810                         else if (j == (pagesize - 4))
11811                                 nvram_cmd |= NVRAM_CMD_LAST;
11812
11813                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11814                                 break;
11815                 }
11816                 if (ret)
11817                         break;
11818         }
11819
11820         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11821         tg3_nvram_exec_cmd(tp, nvram_cmd);
11822
11823         kfree(tmp);
11824
11825         return ret;
11826 }
11827
11828 /* offset and length are dword aligned */
11829 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11830                 u8 *buf)
11831 {
11832         int i, ret = 0;
11833
11834         for (i = 0; i < len; i += 4, offset += 4) {
11835                 u32 page_off, phy_addr, nvram_cmd;
11836                 __be32 data;
11837
11838                 memcpy(&data, buf + i, 4);
11839                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11840
11841                 page_off = offset % tp->nvram_pagesize;
11842
11843                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11844
11845                 tw32(NVRAM_ADDR, phy_addr);
11846
11847                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11848
11849                 if (page_off == 0 || i == 0)
11850                         nvram_cmd |= NVRAM_CMD_FIRST;
11851                 if (page_off == (tp->nvram_pagesize - 4))
11852                         nvram_cmd |= NVRAM_CMD_LAST;
11853
11854                 if (i == (len - 4))
11855                         nvram_cmd |= NVRAM_CMD_LAST;
11856
11857                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11858                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11859                     (tp->nvram_jedecnum == JEDEC_ST) &&
11860                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11861
11862                         if ((ret = tg3_nvram_exec_cmd(tp,
11863                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11864                                 NVRAM_CMD_DONE)))
11865
11866                                 break;
11867                 }
11868                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11869                         /* We always do complete word writes to eeprom. */
11870                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11871                 }
11872
11873                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11874                         break;
11875         }
11876         return ret;
11877 }
11878
11879 /* offset and length are dword aligned */
11880 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11881 {
11882         int ret;
11883
11884         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11885                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11886                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11887                 udelay(40);
11888         }
11889
11890         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11891                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11892         } else {
11893                 u32 grc_mode;
11894
11895                 ret = tg3_nvram_lock(tp);
11896                 if (ret)
11897                         return ret;
11898
11899                 tg3_enable_nvram_access(tp);
11900                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11901                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11902                         tw32(NVRAM_WRITE1, 0x406);
11903
11904                 grc_mode = tr32(GRC_MODE);
11905                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11906
11907                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11908                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11909
11910                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11911                                 buf);
11912                 } else {
11913                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11914                                 buf);
11915                 }
11916
11917                 grc_mode = tr32(GRC_MODE);
11918                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11919
11920                 tg3_disable_nvram_access(tp);
11921                 tg3_nvram_unlock(tp);
11922         }
11923
11924         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11925                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11926                 udelay(40);
11927         }
11928
11929         return ret;
11930 }
11931
11932 struct subsys_tbl_ent {
11933         u16 subsys_vendor, subsys_devid;
11934         u32 phy_id;
11935 };
11936
11937 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11938         /* Broadcom boards. */
11939         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11941         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11943         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11945         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11947         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11949         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11951         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11953         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11954           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11957         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11958           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11959         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11960           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11961
11962         /* 3com boards. */
11963         { TG3PCI_SUBVENDOR_ID_3COM,
11964           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11965         { TG3PCI_SUBVENDOR_ID_3COM,
11966           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11967         { TG3PCI_SUBVENDOR_ID_3COM,
11968           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11969         { TG3PCI_SUBVENDOR_ID_3COM,
11970           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11971         { TG3PCI_SUBVENDOR_ID_3COM,
11972           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11973
11974         /* DELL boards. */
11975         { TG3PCI_SUBVENDOR_ID_DELL,
11976           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11977         { TG3PCI_SUBVENDOR_ID_DELL,
11978           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11979         { TG3PCI_SUBVENDOR_ID_DELL,
11980           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11981         { TG3PCI_SUBVENDOR_ID_DELL,
11982           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11983
11984         /* Compaq boards. */
11985         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11987         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11988           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11989         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11990           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11991         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11992           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11993         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11994           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11995
11996         /* IBM boards. */
11997         { TG3PCI_SUBVENDOR_ID_IBM,
11998           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11999 };
12000
12001 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12002 {
12003         int i;
12004
12005         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12006                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12007                      tp->pdev->subsystem_vendor) &&
12008                     (subsys_id_to_phy_id[i].subsys_devid ==
12009                      tp->pdev->subsystem_device))
12010                         return &subsys_id_to_phy_id[i];
12011         }
12012         return NULL;
12013 }
12014
12015 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12016 {
12017         u32 val;
12018         u16 pmcsr;
12019
12020         /* On some early chips the SRAM cannot be accessed in D3hot state,
12021          * so need make sure we're in D0.
12022          */
12023         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12024         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12025         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12026         msleep(1);
12027
12028         /* Make sure register accesses (indirect or otherwise)
12029          * will function correctly.
12030          */
12031         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12032                                tp->misc_host_ctrl);
12033
12034         /* The memory arbiter has to be enabled in order for SRAM accesses
12035          * to succeed.  Normally on powerup the tg3 chip firmware will make
12036          * sure it is enabled, but other entities such as system netboot
12037          * code might disable it.
12038          */
12039         val = tr32(MEMARB_MODE);
12040         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12041
12042         tp->phy_id = TG3_PHY_ID_INVALID;
12043         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12044
12045         /* Assume an onboard device and WOL capable by default.  */
12046         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12047
12048         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12049                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12050                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12051                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12052                 }
12053                 val = tr32(VCPU_CFGSHDW);
12054                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12055                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12056                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12057                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12058                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12059                 goto done;
12060         }
12061
12062         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12063         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12064                 u32 nic_cfg, led_cfg;
12065                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12066                 int eeprom_phy_serdes = 0;
12067
12068                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12069                 tp->nic_sram_data_cfg = nic_cfg;
12070
12071                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12072                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12073                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12074                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12075                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12076                     (ver > 0) && (ver < 0x100))
12077                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12078
12079                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12080                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12081
12082                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12083                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12084                         eeprom_phy_serdes = 1;
12085
12086                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12087                 if (nic_phy_id != 0) {
12088                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12089                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12090
12091                         eeprom_phy_id  = (id1 >> 16) << 10;
12092                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12093                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12094                 } else
12095                         eeprom_phy_id = 0;
12096
12097                 tp->phy_id = eeprom_phy_id;
12098                 if (eeprom_phy_serdes) {
12099                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12100                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12101                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12102                         else
12103                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12104                 }
12105
12106                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12107                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12108                                     SHASTA_EXT_LED_MODE_MASK);
12109                 else
12110                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12111
12112                 switch (led_cfg) {
12113                 default:
12114                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12115                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12116                         break;
12117
12118                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12119                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12120                         break;
12121
12122                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12123                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12124
12125                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12126                          * read on some older 5700/5701 bootcode.
12127                          */
12128                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12129                             ASIC_REV_5700 ||
12130                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12131                             ASIC_REV_5701)
12132                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12133
12134                         break;
12135
12136                 case SHASTA_EXT_LED_SHARED:
12137                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12138                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12139                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12140                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12141                                                  LED_CTRL_MODE_PHY_2);
12142                         break;
12143
12144                 case SHASTA_EXT_LED_MAC:
12145                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12146                         break;
12147
12148                 case SHASTA_EXT_LED_COMBO:
12149                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12150                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12151                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12152                                                  LED_CTRL_MODE_PHY_2);
12153                         break;
12154
12155                 }
12156
12157                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12158                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12159                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12160                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12161
12162                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12163                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12164
12165                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12166                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12167                         if ((tp->pdev->subsystem_vendor ==
12168                              PCI_VENDOR_ID_ARIMA) &&
12169                             (tp->pdev->subsystem_device == 0x205a ||
12170                              tp->pdev->subsystem_device == 0x2063))
12171                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12172                 } else {
12173                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12174                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12175                 }
12176
12177                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12178                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12179                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12180                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12181                 }
12182
12183                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12184                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12185                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12186
12187                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12188                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12189                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12190
12191                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12192                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12193                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12194
12195                 if (cfg2 & (1 << 17))
12196                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12197
12198                 /* serdes signal pre-emphasis in register 0x590 set by */
12199                 /* bootcode if bit 18 is set */
12200                 if (cfg2 & (1 << 18))
12201                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12202
12203                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12204                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12205                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12206                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12207
12208                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12209                         u32 cfg3;
12210
12211                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12212                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12213                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12214                 }
12215
12216                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12217                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12218                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12219                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12220                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12221                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12222         }
12223 done:
12224         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12225         device_set_wakeup_enable(&tp->pdev->dev,
12226                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12227 }
12228
12229 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12230 {
12231         int i;
12232         u32 val;
12233
12234         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12235         tw32(OTP_CTRL, cmd);
12236
12237         /* Wait for up to 1 ms for command to execute. */
12238         for (i = 0; i < 100; i++) {
12239                 val = tr32(OTP_STATUS);
12240                 if (val & OTP_STATUS_CMD_DONE)
12241                         break;
12242                 udelay(10);
12243         }
12244
12245         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12246 }
12247
12248 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12249  * configuration is a 32-bit value that straddles the alignment boundary.
12250  * We do two 32-bit reads and then shift and merge the results.
12251  */
12252 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12253 {
12254         u32 bhalf_otp, thalf_otp;
12255
12256         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12257
12258         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12259                 return 0;
12260
12261         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12262
12263         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12264                 return 0;
12265
12266         thalf_otp = tr32(OTP_READ_DATA);
12267
12268         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12269
12270         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12271                 return 0;
12272
12273         bhalf_otp = tr32(OTP_READ_DATA);
12274
12275         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12276 }
12277
12278 static int __devinit tg3_phy_probe(struct tg3 *tp)
12279 {
12280         u32 hw_phy_id_1, hw_phy_id_2;
12281         u32 hw_phy_id, hw_phy_id_masked;
12282         int err;
12283
12284         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12285                 return tg3_phy_init(tp);
12286
12287         /* Reading the PHY ID register can conflict with ASF
12288          * firmware access to the PHY hardware.
12289          */
12290         err = 0;
12291         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12292             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12293                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12294         } else {
12295                 /* Now read the physical PHY_ID from the chip and verify
12296                  * that it is sane.  If it doesn't look good, we fall back
12297                  * to either the hard-coded table based PHY_ID and failing
12298                  * that the value found in the eeprom area.
12299                  */
12300                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12301                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12302
12303                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12304                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12305                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12306
12307                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12308         }
12309
12310         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12311                 tp->phy_id = hw_phy_id;
12312                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12313                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12314                 else
12315                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12316         } else {
12317                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12318                         /* Do nothing, phy ID already set up in
12319                          * tg3_get_eeprom_hw_cfg().
12320                          */
12321                 } else {
12322                         struct subsys_tbl_ent *p;
12323
12324                         /* No eeprom signature?  Try the hardcoded
12325                          * subsys device table.
12326                          */
12327                         p = tg3_lookup_by_subsys(tp);
12328                         if (!p)
12329                                 return -ENODEV;
12330
12331                         tp->phy_id = p->phy_id;
12332                         if (!tp->phy_id ||
12333                             tp->phy_id == TG3_PHY_ID_BCM8002)
12334                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12335                 }
12336         }
12337
12338         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12339             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12340             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12341                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12342
12343                 tg3_readphy(tp, MII_BMSR, &bmsr);
12344                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12345                     (bmsr & BMSR_LSTATUS))
12346                         goto skip_phy_reset;
12347
12348                 err = tg3_phy_reset(tp);
12349                 if (err)
12350                         return err;
12351
12352                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12353                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12354                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12355                 tg3_ctrl = 0;
12356                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12357                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12358                                     MII_TG3_CTRL_ADV_1000_FULL);
12359                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12360                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12361                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12362                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12363                 }
12364
12365                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12366                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12367                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12368                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12369                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12370
12371                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12372                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12373
12374                         tg3_writephy(tp, MII_BMCR,
12375                                      BMCR_ANENABLE | BMCR_ANRESTART);
12376                 }
12377                 tg3_phy_set_wirespeed(tp);
12378
12379                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12380                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12381                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12382         }
12383
12384 skip_phy_reset:
12385         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12386                 err = tg3_init_5401phy_dsp(tp);
12387                 if (err)
12388                         return err;
12389
12390                 err = tg3_init_5401phy_dsp(tp);
12391         }
12392
12393         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12394                 tp->link_config.advertising =
12395                         (ADVERTISED_1000baseT_Half |
12396                          ADVERTISED_1000baseT_Full |
12397                          ADVERTISED_Autoneg |
12398                          ADVERTISED_FIBRE);
12399         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12400                 tp->link_config.advertising &=
12401                         ~(ADVERTISED_1000baseT_Half |
12402                           ADVERTISED_1000baseT_Full);
12403
12404         return err;
12405 }
12406
12407 static void __devinit tg3_read_vpd(struct tg3 *tp)
12408 {
12409         u8 vpd_data[TG3_NVM_VPD_LEN];
12410         unsigned int block_end, rosize, len;
12411         int j, i = 0;
12412         u32 magic;
12413
12414         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12415             tg3_nvram_read(tp, 0x0, &magic))
12416                 goto out_not_found;
12417
12418         if (magic == TG3_EEPROM_MAGIC) {
12419                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12420                         u32 tmp;
12421
12422                         /* The data is in little-endian format in NVRAM.
12423                          * Use the big-endian read routines to preserve
12424                          * the byte order as it exists in NVRAM.
12425                          */
12426                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12427                                 goto out_not_found;
12428
12429                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12430                 }
12431         } else {
12432                 ssize_t cnt;
12433                 unsigned int pos = 0;
12434
12435                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12436                         cnt = pci_read_vpd(tp->pdev, pos,
12437                                            TG3_NVM_VPD_LEN - pos,
12438                                            &vpd_data[pos]);
12439                         if (cnt == -ETIMEDOUT || -EINTR)
12440                                 cnt = 0;
12441                         else if (cnt < 0)
12442                                 goto out_not_found;
12443                 }
12444                 if (pos != TG3_NVM_VPD_LEN)
12445                         goto out_not_found;
12446         }
12447
12448         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12449                              PCI_VPD_LRDT_RO_DATA);
12450         if (i < 0)
12451                 goto out_not_found;
12452
12453         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12454         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12455         i += PCI_VPD_LRDT_TAG_SIZE;
12456
12457         if (block_end > TG3_NVM_VPD_LEN)
12458                 goto out_not_found;
12459
12460         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12461                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12462         if (j > 0) {
12463                 len = pci_vpd_info_field_size(&vpd_data[j]);
12464
12465                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12466                 if (j + len > block_end || len != 4 ||
12467                     memcmp(&vpd_data[j], "1028", 4))
12468                         goto partno;
12469
12470                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12471                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12472                 if (j < 0)
12473                         goto partno;
12474
12475                 len = pci_vpd_info_field_size(&vpd_data[j]);
12476
12477                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12478                 if (j + len > block_end)
12479                         goto partno;
12480
12481                 memcpy(tp->fw_ver, &vpd_data[j], len);
12482                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12483         }
12484
12485 partno:
12486         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12487                                       PCI_VPD_RO_KEYWORD_PARTNO);
12488         if (i < 0)
12489                 goto out_not_found;
12490
12491         len = pci_vpd_info_field_size(&vpd_data[i]);
12492
12493         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12494         if (len > TG3_BPN_SIZE ||
12495             (len + i) > TG3_NVM_VPD_LEN)
12496                 goto out_not_found;
12497
12498         memcpy(tp->board_part_number, &vpd_data[i], len);
12499
12500         return;
12501
12502 out_not_found:
12503         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12504                 strcpy(tp->board_part_number, "BCM95906");
12505         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12506                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12507                 strcpy(tp->board_part_number, "BCM57780");
12508         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12509                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12510                 strcpy(tp->board_part_number, "BCM57760");
12511         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12512                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12513                 strcpy(tp->board_part_number, "BCM57790");
12514         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12515                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12516                 strcpy(tp->board_part_number, "BCM57788");
12517         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12518                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12519                 strcpy(tp->board_part_number, "BCM57761");
12520         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12521                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12522                 strcpy(tp->board_part_number, "BCM57765");
12523         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12524                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12525                 strcpy(tp->board_part_number, "BCM57781");
12526         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12527                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12528                 strcpy(tp->board_part_number, "BCM57785");
12529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12530                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12531                 strcpy(tp->board_part_number, "BCM57791");
12532         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12533                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12534                 strcpy(tp->board_part_number, "BCM57795");
12535         else
12536                 strcpy(tp->board_part_number, "none");
12537 }
12538
12539 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12540 {
12541         u32 val;
12542
12543         if (tg3_nvram_read(tp, offset, &val) ||
12544             (val & 0xfc000000) != 0x0c000000 ||
12545             tg3_nvram_read(tp, offset + 4, &val) ||
12546             val != 0)
12547                 return 0;
12548
12549         return 1;
12550 }
12551
12552 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12553 {
12554         u32 val, offset, start, ver_offset;
12555         int i, dst_off;
12556         bool newver = false;
12557
12558         if (tg3_nvram_read(tp, 0xc, &offset) ||
12559             tg3_nvram_read(tp, 0x4, &start))
12560                 return;
12561
12562         offset = tg3_nvram_logical_addr(tp, offset);
12563
12564         if (tg3_nvram_read(tp, offset, &val))
12565                 return;
12566
12567         if ((val & 0xfc000000) == 0x0c000000) {
12568                 if (tg3_nvram_read(tp, offset + 4, &val))
12569                         return;
12570
12571                 if (val == 0)
12572                         newver = true;
12573         }
12574
12575         dst_off = strlen(tp->fw_ver);
12576
12577         if (newver) {
12578                 if (TG3_VER_SIZE - dst_off < 16 ||
12579                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12580                         return;
12581
12582                 offset = offset + ver_offset - start;
12583                 for (i = 0; i < 16; i += 4) {
12584                         __be32 v;
12585                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12586                                 return;
12587
12588                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12589                 }
12590         } else {
12591                 u32 major, minor;
12592
12593                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12594                         return;
12595
12596                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12597                         TG3_NVM_BCVER_MAJSFT;
12598                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12599                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12600                          "v%d.%02d", major, minor);
12601         }
12602 }
12603
12604 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12605 {
12606         u32 val, major, minor;
12607
12608         /* Use native endian representation */
12609         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12610                 return;
12611
12612         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12613                 TG3_NVM_HWSB_CFG1_MAJSFT;
12614         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12615                 TG3_NVM_HWSB_CFG1_MINSFT;
12616
12617         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12618 }
12619
12620 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12621 {
12622         u32 offset, major, minor, build;
12623
12624         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12625
12626         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12627                 return;
12628
12629         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12630         case TG3_EEPROM_SB_REVISION_0:
12631                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12632                 break;
12633         case TG3_EEPROM_SB_REVISION_2:
12634                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12635                 break;
12636         case TG3_EEPROM_SB_REVISION_3:
12637                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12638                 break;
12639         case TG3_EEPROM_SB_REVISION_4:
12640                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12641                 break;
12642         case TG3_EEPROM_SB_REVISION_5:
12643                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12644                 break;
12645         default:
12646                 return;
12647         }
12648
12649         if (tg3_nvram_read(tp, offset, &val))
12650                 return;
12651
12652         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12653                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12654         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12655                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12656         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12657
12658         if (minor > 99 || build > 26)
12659                 return;
12660
12661         offset = strlen(tp->fw_ver);
12662         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12663                  " v%d.%02d", major, minor);
12664
12665         if (build > 0) {
12666                 offset = strlen(tp->fw_ver);
12667                 if (offset < TG3_VER_SIZE - 1)
12668                         tp->fw_ver[offset] = 'a' + build - 1;
12669         }
12670 }
12671
12672 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12673 {
12674         u32 val, offset, start;
12675         int i, vlen;
12676
12677         for (offset = TG3_NVM_DIR_START;
12678              offset < TG3_NVM_DIR_END;
12679              offset += TG3_NVM_DIRENT_SIZE) {
12680                 if (tg3_nvram_read(tp, offset, &val))
12681                         return;
12682
12683                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12684                         break;
12685         }
12686
12687         if (offset == TG3_NVM_DIR_END)
12688                 return;
12689
12690         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12691                 start = 0x08000000;
12692         else if (tg3_nvram_read(tp, offset - 4, &start))
12693                 return;
12694
12695         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12696             !tg3_fw_img_is_valid(tp, offset) ||
12697             tg3_nvram_read(tp, offset + 8, &val))
12698                 return;
12699
12700         offset += val - start;
12701
12702         vlen = strlen(tp->fw_ver);
12703
12704         tp->fw_ver[vlen++] = ',';
12705         tp->fw_ver[vlen++] = ' ';
12706
12707         for (i = 0; i < 4; i++) {
12708                 __be32 v;
12709                 if (tg3_nvram_read_be32(tp, offset, &v))
12710                         return;
12711
12712                 offset += sizeof(v);
12713
12714                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12715                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12716                         break;
12717                 }
12718
12719                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12720                 vlen += sizeof(v);
12721         }
12722 }
12723
12724 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12725 {
12726         int vlen;
12727         u32 apedata;
12728
12729         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12730             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12731                 return;
12732
12733         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12734         if (apedata != APE_SEG_SIG_MAGIC)
12735                 return;
12736
12737         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12738         if (!(apedata & APE_FW_STATUS_READY))
12739                 return;
12740
12741         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12742
12743         vlen = strlen(tp->fw_ver);
12744
12745         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12746                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12747                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12748                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12749                  (apedata & APE_FW_VERSION_BLDMSK));
12750 }
12751
12752 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12753 {
12754         u32 val;
12755         bool vpd_vers = false;
12756
12757         if (tp->fw_ver[0] != 0)
12758                 vpd_vers = true;
12759
12760         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12761                 strcat(tp->fw_ver, "sb");
12762                 return;
12763         }
12764
12765         if (tg3_nvram_read(tp, 0, &val))
12766                 return;
12767
12768         if (val == TG3_EEPROM_MAGIC)
12769                 tg3_read_bc_ver(tp);
12770         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12771                 tg3_read_sb_ver(tp, val);
12772         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12773                 tg3_read_hwsb_ver(tp);
12774         else
12775                 return;
12776
12777         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12778              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12779                 goto done;
12780
12781         tg3_read_mgmtfw_ver(tp);
12782
12783 done:
12784         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12785 }
12786
12787 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12788
12789 static int __devinit tg3_get_invariants(struct tg3 *tp)
12790 {
12791         static struct pci_device_id write_reorder_chipsets[] = {
12792                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12793                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12794                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12795                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12796                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12797                              PCI_DEVICE_ID_VIA_8385_0) },
12798                 { },
12799         };
12800         u32 misc_ctrl_reg;
12801         u32 pci_state_reg, grc_misc_cfg;
12802         u32 val;
12803         u16 pci_cmd;
12804         int err;
12805
12806         /* Force memory write invalidate off.  If we leave it on,
12807          * then on 5700_BX chips we have to enable a workaround.
12808          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12809          * to match the cacheline size.  The Broadcom driver have this
12810          * workaround but turns MWI off all the times so never uses
12811          * it.  This seems to suggest that the workaround is insufficient.
12812          */
12813         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12814         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12815         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12816
12817         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12818          * has the register indirect write enable bit set before
12819          * we try to access any of the MMIO registers.  It is also
12820          * critical that the PCI-X hw workaround situation is decided
12821          * before that as well.
12822          */
12823         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12824                               &misc_ctrl_reg);
12825
12826         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12827                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12828         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12829                 u32 prod_id_asic_rev;
12830
12831                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12832                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12833                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12834                         pci_read_config_dword(tp->pdev,
12835                                               TG3PCI_GEN2_PRODID_ASICREV,
12836                                               &prod_id_asic_rev);
12837                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12838                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12839                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12840                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12841                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12842                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12843                         pci_read_config_dword(tp->pdev,
12844                                               TG3PCI_GEN15_PRODID_ASICREV,
12845                                               &prod_id_asic_rev);
12846                 else
12847                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12848                                               &prod_id_asic_rev);
12849
12850                 tp->pci_chip_rev_id = prod_id_asic_rev;
12851         }
12852
12853         /* Wrong chip ID in 5752 A0. This code can be removed later
12854          * as A0 is not in production.
12855          */
12856         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12857                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12858
12859         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12860          * we need to disable memory and use config. cycles
12861          * only to access all registers. The 5702/03 chips
12862          * can mistakenly decode the special cycles from the
12863          * ICH chipsets as memory write cycles, causing corruption
12864          * of register and memory space. Only certain ICH bridges
12865          * will drive special cycles with non-zero data during the
12866          * address phase which can fall within the 5703's address
12867          * range. This is not an ICH bug as the PCI spec allows
12868          * non-zero address during special cycles. However, only
12869          * these ICH bridges are known to drive non-zero addresses
12870          * during special cycles.
12871          *
12872          * Since special cycles do not cross PCI bridges, we only
12873          * enable this workaround if the 5703 is on the secondary
12874          * bus of these ICH bridges.
12875          */
12876         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12877             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12878                 static struct tg3_dev_id {
12879                         u32     vendor;
12880                         u32     device;
12881                         u32     rev;
12882                 } ich_chipsets[] = {
12883                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12884                           PCI_ANY_ID },
12885                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12886                           PCI_ANY_ID },
12887                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12888                           0xa },
12889                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12890                           PCI_ANY_ID },
12891                         { },
12892                 };
12893                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12894                 struct pci_dev *bridge = NULL;
12895
12896                 while (pci_id->vendor != 0) {
12897                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12898                                                 bridge);
12899                         if (!bridge) {
12900                                 pci_id++;
12901                                 continue;
12902                         }
12903                         if (pci_id->rev != PCI_ANY_ID) {
12904                                 if (bridge->revision > pci_id->rev)
12905                                         continue;
12906                         }
12907                         if (bridge->subordinate &&
12908                             (bridge->subordinate->number ==
12909                              tp->pdev->bus->number)) {
12910
12911                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12912                                 pci_dev_put(bridge);
12913                                 break;
12914                         }
12915                 }
12916         }
12917
12918         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12919                 static struct tg3_dev_id {
12920                         u32     vendor;
12921                         u32     device;
12922                 } bridge_chipsets[] = {
12923                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12924                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12925                         { },
12926                 };
12927                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12928                 struct pci_dev *bridge = NULL;
12929
12930                 while (pci_id->vendor != 0) {
12931                         bridge = pci_get_device(pci_id->vendor,
12932                                                 pci_id->device,
12933                                                 bridge);
12934                         if (!bridge) {
12935                                 pci_id++;
12936                                 continue;
12937                         }
12938                         if (bridge->subordinate &&
12939                             (bridge->subordinate->number <=
12940                              tp->pdev->bus->number) &&
12941                             (bridge->subordinate->subordinate >=
12942                              tp->pdev->bus->number)) {
12943                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12944                                 pci_dev_put(bridge);
12945                                 break;
12946                         }
12947                 }
12948         }
12949
12950         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12951          * DMA addresses > 40-bit. This bridge may have other additional
12952          * 57xx devices behind it in some 4-port NIC designs for example.
12953          * Any tg3 device found behind the bridge will also need the 40-bit
12954          * DMA workaround.
12955          */
12956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12957             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12958                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12959                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12960                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12961         } else {
12962                 struct pci_dev *bridge = NULL;
12963
12964                 do {
12965                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12966                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12967                                                 bridge);
12968                         if (bridge && bridge->subordinate &&
12969                             (bridge->subordinate->number <=
12970                              tp->pdev->bus->number) &&
12971                             (bridge->subordinate->subordinate >=
12972                              tp->pdev->bus->number)) {
12973                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12974                                 pci_dev_put(bridge);
12975                                 break;
12976                         }
12977                 } while (bridge);
12978         }
12979
12980         /* Initialize misc host control in PCI block. */
12981         tp->misc_host_ctrl |= (misc_ctrl_reg &
12982                                MISC_HOST_CTRL_CHIPREV);
12983         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12984                                tp->misc_host_ctrl);
12985
12986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12987             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12988             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12989                 tp->pdev_peer = tg3_find_peer(tp);
12990
12991         /* Intentionally exclude ASIC_REV_5906 */
12992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12994             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12996             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12997             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13000                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13001
13002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13005             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13006             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13007                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13008
13009         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13010             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13011                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13012
13013         /* 5700 B0 chips do not support checksumming correctly due
13014          * to hardware bugs.
13015          */
13016         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13017                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13018         else {
13019                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13020                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13021                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13022                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13023                 tp->dev->features |= NETIF_F_GRO;
13024         }
13025
13026         /* Determine TSO capabilities */
13027         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13029                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13030         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13031                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13032                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13033         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13034                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13035                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13036                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13037                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13038         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13039                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13040                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13041                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13042                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13043                         tp->fw_needed = FIRMWARE_TG3TSO5;
13044                 else
13045                         tp->fw_needed = FIRMWARE_TG3TSO;
13046         }
13047
13048         tp->irq_max = 1;
13049
13050         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13051                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13052                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13053                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13054                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13055                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13056                      tp->pdev_peer == tp->pdev))
13057                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13058
13059                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13060                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13061                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13062                 }
13063
13064                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13065                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13066                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13067                         tp->irq_max = TG3_IRQ_MAX_VECS;
13068                 }
13069         }
13070
13071         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13072             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13073                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13074         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13075                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13076                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13077         }
13078
13079         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13080             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13081                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13082
13083         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13084             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13085             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13086                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13087
13088         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13089                               &pci_state_reg);
13090
13091         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13092         if (tp->pcie_cap != 0) {
13093                 u16 lnkctl;
13094
13095                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13096
13097                 pcie_set_readrq(tp->pdev, 4096);
13098
13099                 pci_read_config_word(tp->pdev,
13100                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13101                                      &lnkctl);
13102                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13103                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13104                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13105                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13106                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13107                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13108                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13109                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13110                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13111                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13112                 }
13113         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13114                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13115         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13116                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13117                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13118                 if (!tp->pcix_cap) {
13119                         dev_err(&tp->pdev->dev,
13120                                 "Cannot find PCI-X capability, aborting\n");
13121                         return -EIO;
13122                 }
13123
13124                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13125                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13126         }
13127
13128         /* If we have an AMD 762 or VIA K8T800 chipset, write
13129          * reordering to the mailbox registers done by the host
13130          * controller can cause major troubles.  We read back from
13131          * every mailbox register write to force the writes to be
13132          * posted to the chip in order.
13133          */
13134         if (pci_dev_present(write_reorder_chipsets) &&
13135             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13136                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13137
13138         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13139                              &tp->pci_cacheline_sz);
13140         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13141                              &tp->pci_lat_timer);
13142         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13143             tp->pci_lat_timer < 64) {
13144                 tp->pci_lat_timer = 64;
13145                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13146                                       tp->pci_lat_timer);
13147         }
13148
13149         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13150                 /* 5700 BX chips need to have their TX producer index
13151                  * mailboxes written twice to workaround a bug.
13152                  */
13153                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13154
13155                 /* If we are in PCI-X mode, enable register write workaround.
13156                  *
13157                  * The workaround is to use indirect register accesses
13158                  * for all chip writes not to mailbox registers.
13159                  */
13160                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13161                         u32 pm_reg;
13162
13163                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13164
13165                         /* The chip can have it's power management PCI config
13166                          * space registers clobbered due to this bug.
13167                          * So explicitly force the chip into D0 here.
13168                          */
13169                         pci_read_config_dword(tp->pdev,
13170                                               tp->pm_cap + PCI_PM_CTRL,
13171                                               &pm_reg);
13172                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13173                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13174                         pci_write_config_dword(tp->pdev,
13175                                                tp->pm_cap + PCI_PM_CTRL,
13176                                                pm_reg);
13177
13178                         /* Also, force SERR#/PERR# in PCI command. */
13179                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13180                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13181                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13182                 }
13183         }
13184
13185         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13186                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13187         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13188                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13189
13190         /* Chip-specific fixup from Broadcom driver */
13191         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13192             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13193                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13194                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13195         }
13196
13197         /* Default fast path register access methods */
13198         tp->read32 = tg3_read32;
13199         tp->write32 = tg3_write32;
13200         tp->read32_mbox = tg3_read32;
13201         tp->write32_mbox = tg3_write32;
13202         tp->write32_tx_mbox = tg3_write32;
13203         tp->write32_rx_mbox = tg3_write32;
13204
13205         /* Various workaround register access methods */
13206         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13207                 tp->write32 = tg3_write_indirect_reg32;
13208         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13209                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13210                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13211                 /*
13212                  * Back to back register writes can cause problems on these
13213                  * chips, the workaround is to read back all reg writes
13214                  * except those to mailbox regs.
13215                  *
13216                  * See tg3_write_indirect_reg32().
13217                  */
13218                 tp->write32 = tg3_write_flush_reg32;
13219         }
13220
13221         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13222             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13223                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13224                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13225                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13226         }
13227
13228         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13229                 tp->read32 = tg3_read_indirect_reg32;
13230                 tp->write32 = tg3_write_indirect_reg32;
13231                 tp->read32_mbox = tg3_read_indirect_mbox;
13232                 tp->write32_mbox = tg3_write_indirect_mbox;
13233                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13234                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13235
13236                 iounmap(tp->regs);
13237                 tp->regs = NULL;
13238
13239                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13240                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13241                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13242         }
13243         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13244                 tp->read32_mbox = tg3_read32_mbox_5906;
13245                 tp->write32_mbox = tg3_write32_mbox_5906;
13246                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13247                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13248         }
13249
13250         if (tp->write32 == tg3_write_indirect_reg32 ||
13251             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13252              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13253               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13254                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13255
13256         /* Get eeprom hw config before calling tg3_set_power_state().
13257          * In particular, the TG3_FLG2_IS_NIC flag must be
13258          * determined before calling tg3_set_power_state() so that
13259          * we know whether or not to switch out of Vaux power.
13260          * When the flag is set, it means that GPIO1 is used for eeprom
13261          * write protect and also implies that it is a LOM where GPIOs
13262          * are not used to switch power.
13263          */
13264         tg3_get_eeprom_hw_cfg(tp);
13265
13266         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13267                 /* Allow reads and writes to the
13268                  * APE register and memory space.
13269                  */
13270                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13271                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13272                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13273                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13274                                        pci_state_reg);
13275         }
13276
13277         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13278             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13279             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13280             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13281             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13282             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13283                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13284
13285         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13286          * GPIO1 driven high will bring 5700's external PHY out of reset.
13287          * It is also used as eeprom write protect on LOMs.
13288          */
13289         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13290         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13291             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13292                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13293                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13294         /* Unused GPIO3 must be driven as output on 5752 because there
13295          * are no pull-up resistors on unused GPIO pins.
13296          */
13297         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13298                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13299
13300         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13301             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13302             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13303                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13304
13305         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13306             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13307                 /* Turn off the debug UART. */
13308                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13309                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13310                         /* Keep VMain power. */
13311                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13312                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13313         }
13314
13315         /* Force the chip into D0. */
13316         err = tg3_set_power_state(tp, PCI_D0);
13317         if (err) {
13318                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13319                 return err;
13320         }
13321
13322         /* Derive initial jumbo mode from MTU assigned in
13323          * ether_setup() via the alloc_etherdev() call
13324          */
13325         if (tp->dev->mtu > ETH_DATA_LEN &&
13326             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13327                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13328
13329         /* Determine WakeOnLan speed to use. */
13330         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13331             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13332             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13333             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13334                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13335         } else {
13336                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13337         }
13338
13339         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13340                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13341
13342         /* A few boards don't want Ethernet@WireSpeed phy feature */
13343         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13344             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13345              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13346              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13347             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13348             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13349                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13350
13351         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13352             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13353                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13354         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13355                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13356
13357         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13358             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13359             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13360             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13361             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13362             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13363                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13364                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13365                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13366                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13367                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13368                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13369                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13370                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13371                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13372                 } else
13373                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13374         }
13375
13376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13377             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13378                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13379                 if (tp->phy_otp == 0)
13380                         tp->phy_otp = TG3_OTP_DEFAULT;
13381         }
13382
13383         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13384                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13385         else
13386                 tp->mi_mode = MAC_MI_MODE_BASE;
13387
13388         tp->coalesce_mode = 0;
13389         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13390             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13391                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13392
13393         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13394             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13395                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13396
13397         err = tg3_mdio_init(tp);
13398         if (err)
13399                 return err;
13400
13401         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13402             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13403                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13404                 return -ENOTSUPP;
13405
13406         /* Initialize data/descriptor byte/word swapping. */
13407         val = tr32(GRC_MODE);
13408         val &= GRC_MODE_HOST_STACKUP;
13409         tw32(GRC_MODE, val | tp->grc_mode);
13410
13411         tg3_switch_clocks(tp);
13412
13413         /* Clear this out for sanity. */
13414         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13415
13416         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13417                               &pci_state_reg);
13418         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13419             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13420                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13421
13422                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13423                     chiprevid == CHIPREV_ID_5701_B0 ||
13424                     chiprevid == CHIPREV_ID_5701_B2 ||
13425                     chiprevid == CHIPREV_ID_5701_B5) {
13426                         void __iomem *sram_base;
13427
13428                         /* Write some dummy words into the SRAM status block
13429                          * area, see if it reads back correctly.  If the return
13430                          * value is bad, force enable the PCIX workaround.
13431                          */
13432                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13433
13434                         writel(0x00000000, sram_base);
13435                         writel(0x00000000, sram_base + 4);
13436                         writel(0xffffffff, sram_base + 4);
13437                         if (readl(sram_base) != 0x00000000)
13438                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13439                 }
13440         }
13441
13442         udelay(50);
13443         tg3_nvram_init(tp);
13444
13445         grc_misc_cfg = tr32(GRC_MISC_CFG);
13446         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13447
13448         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13449             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13450              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13451                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13452
13453         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13454             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13455                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13456         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13457                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13458                                       HOSTCC_MODE_CLRTICK_TXBD);
13459
13460                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13461                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13462                                        tp->misc_host_ctrl);
13463         }
13464
13465         /* Preserve the APE MAC_MODE bits */
13466         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13467                 tp->mac_mode = tr32(MAC_MODE) |
13468                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13469         else
13470                 tp->mac_mode = TG3_DEF_MAC_MODE;
13471
13472         /* these are limited to 10/100 only */
13473         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13474              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13475             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13476              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13477              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13478               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13479               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13480             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13481              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13482               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13483               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13484             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13485             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13486             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13487             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13488                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13489
13490         err = tg3_phy_probe(tp);
13491         if (err) {
13492                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13493                 /* ... but do not return immediately ... */
13494                 tg3_mdio_fini(tp);
13495         }
13496
13497         tg3_read_vpd(tp);
13498         tg3_read_fw_ver(tp);
13499
13500         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13501                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13502         } else {
13503                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13504                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13505                 else
13506                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13507         }
13508
13509         /* 5700 {AX,BX} chips have a broken status block link
13510          * change bit implementation, so we must use the
13511          * status register in those cases.
13512          */
13513         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13514                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13515         else
13516                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13517
13518         /* The led_ctrl is set during tg3_phy_probe, here we might
13519          * have to force the link status polling mechanism based
13520          * upon subsystem IDs.
13521          */
13522         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13523             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13524             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13525                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13526                                   TG3_FLAG_USE_LINKCHG_REG);
13527         }
13528
13529         /* For all SERDES we poll the MAC status register. */
13530         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13531                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13532         else
13533                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13534
13535         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13536         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13537         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13538             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13539                 tp->rx_offset -= NET_IP_ALIGN;
13540 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13541                 tp->rx_copy_thresh = ~(u16)0;
13542 #endif
13543         }
13544
13545         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13546
13547         /* Increment the rx prod index on the rx std ring by at most
13548          * 8 for these chips to workaround hw errata.
13549          */
13550         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13551             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13552             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13553                 tp->rx_std_max_post = 8;
13554
13555         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13556                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13557                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13558
13559         return err;
13560 }
13561
13562 #ifdef CONFIG_SPARC
13563 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13564 {
13565         struct net_device *dev = tp->dev;
13566         struct pci_dev *pdev = tp->pdev;
13567         struct device_node *dp = pci_device_to_OF_node(pdev);
13568         const unsigned char *addr;
13569         int len;
13570
13571         addr = of_get_property(dp, "local-mac-address", &len);
13572         if (addr && len == 6) {
13573                 memcpy(dev->dev_addr, addr, 6);
13574                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13575                 return 0;
13576         }
13577         return -ENODEV;
13578 }
13579
13580 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13581 {
13582         struct net_device *dev = tp->dev;
13583
13584         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13585         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13586         return 0;
13587 }
13588 #endif
13589
13590 static int __devinit tg3_get_device_address(struct tg3 *tp)
13591 {
13592         struct net_device *dev = tp->dev;
13593         u32 hi, lo, mac_offset;
13594         int addr_ok = 0;
13595
13596 #ifdef CONFIG_SPARC
13597         if (!tg3_get_macaddr_sparc(tp))
13598                 return 0;
13599 #endif
13600
13601         mac_offset = 0x7c;
13602         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13603             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13604                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13605                         mac_offset = 0xcc;
13606                 if (tg3_nvram_lock(tp))
13607                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13608                 else
13609                         tg3_nvram_unlock(tp);
13610         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13611                 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13612                         mac_offset = 0xcc;
13613         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13614                 mac_offset = 0x10;
13615
13616         /* First try to get it from MAC address mailbox. */
13617         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13618         if ((hi >> 16) == 0x484b) {
13619                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13620                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13621
13622                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13623                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13624                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13625                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13626                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13627
13628                 /* Some old bootcode may report a 0 MAC address in SRAM */
13629                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13630         }
13631         if (!addr_ok) {
13632                 /* Next, try NVRAM. */
13633                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13634                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13635                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13636                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13637                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13638                 }
13639                 /* Finally just fetch it out of the MAC control regs. */
13640                 else {
13641                         hi = tr32(MAC_ADDR_0_HIGH);
13642                         lo = tr32(MAC_ADDR_0_LOW);
13643
13644                         dev->dev_addr[5] = lo & 0xff;
13645                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13646                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13647                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13648                         dev->dev_addr[1] = hi & 0xff;
13649                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13650                 }
13651         }
13652
13653         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13654 #ifdef CONFIG_SPARC
13655                 if (!tg3_get_default_macaddr_sparc(tp))
13656                         return 0;
13657 #endif
13658                 return -EINVAL;
13659         }
13660         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13661         return 0;
13662 }
13663
13664 #define BOUNDARY_SINGLE_CACHELINE       1
13665 #define BOUNDARY_MULTI_CACHELINE        2
13666
13667 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13668 {
13669         int cacheline_size;
13670         u8 byte;
13671         int goal;
13672
13673         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13674         if (byte == 0)
13675                 cacheline_size = 1024;
13676         else
13677                 cacheline_size = (int) byte * 4;
13678
13679         /* On 5703 and later chips, the boundary bits have no
13680          * effect.
13681          */
13682         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13683             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13684             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13685                 goto out;
13686
13687 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13688         goal = BOUNDARY_MULTI_CACHELINE;
13689 #else
13690 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13691         goal = BOUNDARY_SINGLE_CACHELINE;
13692 #else
13693         goal = 0;
13694 #endif
13695 #endif
13696
13697         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13698             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13699                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13700                 goto out;
13701         }
13702
13703         if (!goal)
13704                 goto out;
13705
13706         /* PCI controllers on most RISC systems tend to disconnect
13707          * when a device tries to burst across a cache-line boundary.
13708          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13709          *
13710          * Unfortunately, for PCI-E there are only limited
13711          * write-side controls for this, and thus for reads
13712          * we will still get the disconnects.  We'll also waste
13713          * these PCI cycles for both read and write for chips
13714          * other than 5700 and 5701 which do not implement the
13715          * boundary bits.
13716          */
13717         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13718             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13719                 switch (cacheline_size) {
13720                 case 16:
13721                 case 32:
13722                 case 64:
13723                 case 128:
13724                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13725                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13726                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13727                         } else {
13728                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13729                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13730                         }
13731                         break;
13732
13733                 case 256:
13734                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13735                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13736                         break;
13737
13738                 default:
13739                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13740                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13741                         break;
13742                 }
13743         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13744                 switch (cacheline_size) {
13745                 case 16:
13746                 case 32:
13747                 case 64:
13748                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13749                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13750                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13751                                 break;
13752                         }
13753                         /* fallthrough */
13754                 case 128:
13755                 default:
13756                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13757                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13758                         break;
13759                 }
13760         } else {
13761                 switch (cacheline_size) {
13762                 case 16:
13763                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13764                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13765                                         DMA_RWCTRL_WRITE_BNDRY_16);
13766                                 break;
13767                         }
13768                         /* fallthrough */
13769                 case 32:
13770                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13771                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13772                                         DMA_RWCTRL_WRITE_BNDRY_32);
13773                                 break;
13774                         }
13775                         /* fallthrough */
13776                 case 64:
13777                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13778                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13779                                         DMA_RWCTRL_WRITE_BNDRY_64);
13780                                 break;
13781                         }
13782                         /* fallthrough */
13783                 case 128:
13784                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13785                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13786                                         DMA_RWCTRL_WRITE_BNDRY_128);
13787                                 break;
13788                         }
13789                         /* fallthrough */
13790                 case 256:
13791                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13792                                 DMA_RWCTRL_WRITE_BNDRY_256);
13793                         break;
13794                 case 512:
13795                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13796                                 DMA_RWCTRL_WRITE_BNDRY_512);
13797                         break;
13798                 case 1024:
13799                 default:
13800                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13801                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13802                         break;
13803                 }
13804         }
13805
13806 out:
13807         return val;
13808 }
13809
13810 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13811 {
13812         struct tg3_internal_buffer_desc test_desc;
13813         u32 sram_dma_descs;
13814         int i, ret;
13815
13816         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13817
13818         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13819         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13820         tw32(RDMAC_STATUS, 0);
13821         tw32(WDMAC_STATUS, 0);
13822
13823         tw32(BUFMGR_MODE, 0);
13824         tw32(FTQ_RESET, 0);
13825
13826         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13827         test_desc.addr_lo = buf_dma & 0xffffffff;
13828         test_desc.nic_mbuf = 0x00002100;
13829         test_desc.len = size;
13830
13831         /*
13832          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13833          * the *second* time the tg3 driver was getting loaded after an
13834          * initial scan.
13835          *
13836          * Broadcom tells me:
13837          *   ...the DMA engine is connected to the GRC block and a DMA
13838          *   reset may affect the GRC block in some unpredictable way...
13839          *   The behavior of resets to individual blocks has not been tested.
13840          *
13841          * Broadcom noted the GRC reset will also reset all sub-components.
13842          */
13843         if (to_device) {
13844                 test_desc.cqid_sqid = (13 << 8) | 2;
13845
13846                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13847                 udelay(40);
13848         } else {
13849                 test_desc.cqid_sqid = (16 << 8) | 7;
13850
13851                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13852                 udelay(40);
13853         }
13854         test_desc.flags = 0x00000005;
13855
13856         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13857                 u32 val;
13858
13859                 val = *(((u32 *)&test_desc) + i);
13860                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13861                                        sram_dma_descs + (i * sizeof(u32)));
13862                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13863         }
13864         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13865
13866         if (to_device)
13867                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13868         else
13869                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13870
13871         ret = -ENODEV;
13872         for (i = 0; i < 40; i++) {
13873                 u32 val;
13874
13875                 if (to_device)
13876                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13877                 else
13878                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13879                 if ((val & 0xffff) == sram_dma_descs) {
13880                         ret = 0;
13881                         break;
13882                 }
13883
13884                 udelay(100);
13885         }
13886
13887         return ret;
13888 }
13889
13890 #define TEST_BUFFER_SIZE        0x2000
13891
13892 static int __devinit tg3_test_dma(struct tg3 *tp)
13893 {
13894         dma_addr_t buf_dma;
13895         u32 *buf, saved_dma_rwctrl;
13896         int ret = 0;
13897
13898         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13899         if (!buf) {
13900                 ret = -ENOMEM;
13901                 goto out_nofree;
13902         }
13903
13904         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13905                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13906
13907         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13908
13909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13910             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13911                 goto out;
13912
13913         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13914                 /* DMA read watermark not used on PCIE */
13915                 tp->dma_rwctrl |= 0x00180000;
13916         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13917                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13918                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13919                         tp->dma_rwctrl |= 0x003f0000;
13920                 else
13921                         tp->dma_rwctrl |= 0x003f000f;
13922         } else {
13923                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13924                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13925                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13926                         u32 read_water = 0x7;
13927
13928                         /* If the 5704 is behind the EPB bridge, we can
13929                          * do the less restrictive ONE_DMA workaround for
13930                          * better performance.
13931                          */
13932                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13933                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13934                                 tp->dma_rwctrl |= 0x8000;
13935                         else if (ccval == 0x6 || ccval == 0x7)
13936                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13937
13938                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13939                                 read_water = 4;
13940                         /* Set bit 23 to enable PCIX hw bug fix */
13941                         tp->dma_rwctrl |=
13942                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13943                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13944                                 (1 << 23);
13945                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13946                         /* 5780 always in PCIX mode */
13947                         tp->dma_rwctrl |= 0x00144000;
13948                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13949                         /* 5714 always in PCIX mode */
13950                         tp->dma_rwctrl |= 0x00148000;
13951                 } else {
13952                         tp->dma_rwctrl |= 0x001b000f;
13953                 }
13954         }
13955
13956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13957             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13958                 tp->dma_rwctrl &= 0xfffffff0;
13959
13960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13961             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13962                 /* Remove this if it causes problems for some boards. */
13963                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13964
13965                 /* On 5700/5701 chips, we need to set this bit.
13966                  * Otherwise the chip will issue cacheline transactions
13967                  * to streamable DMA memory with not all the byte
13968                  * enables turned on.  This is an error on several
13969                  * RISC PCI controllers, in particular sparc64.
13970                  *
13971                  * On 5703/5704 chips, this bit has been reassigned
13972                  * a different meaning.  In particular, it is used
13973                  * on those chips to enable a PCI-X workaround.
13974                  */
13975                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13976         }
13977
13978         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13979
13980 #if 0
13981         /* Unneeded, already done by tg3_get_invariants.  */
13982         tg3_switch_clocks(tp);
13983 #endif
13984
13985         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13986             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13987                 goto out;
13988
13989         /* It is best to perform DMA test with maximum write burst size
13990          * to expose the 5700/5701 write DMA bug.
13991          */
13992         saved_dma_rwctrl = tp->dma_rwctrl;
13993         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13994         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13995
13996         while (1) {
13997                 u32 *p = buf, i;
13998
13999                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14000                         p[i] = i;
14001
14002                 /* Send the buffer to the chip. */
14003                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14004                 if (ret) {
14005                         dev_err(&tp->pdev->dev,
14006                                 "%s: Buffer write failed. err = %d\n",
14007                                 __func__, ret);
14008                         break;
14009                 }
14010
14011 #if 0
14012                 /* validate data reached card RAM correctly. */
14013                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14014                         u32 val;
14015                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14016                         if (le32_to_cpu(val) != p[i]) {
14017                                 dev_err(&tp->pdev->dev,
14018                                         "%s: Buffer corrupted on device! "
14019                                         "(%d != %d)\n", __func__, val, i);
14020                                 /* ret = -ENODEV here? */
14021                         }
14022                         p[i] = 0;
14023                 }
14024 #endif
14025                 /* Now read it back. */
14026                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14027                 if (ret) {
14028                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14029                                 "err = %d\n", __func__, ret);
14030                         break;
14031                 }
14032
14033                 /* Verify it. */
14034                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14035                         if (p[i] == i)
14036                                 continue;
14037
14038                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14039                             DMA_RWCTRL_WRITE_BNDRY_16) {
14040                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14041                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14042                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14043                                 break;
14044                         } else {
14045                                 dev_err(&tp->pdev->dev,
14046                                         "%s: Buffer corrupted on read back! "
14047                                         "(%d != %d)\n", __func__, p[i], i);
14048                                 ret = -ENODEV;
14049                                 goto out;
14050                         }
14051                 }
14052
14053                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14054                         /* Success. */
14055                         ret = 0;
14056                         break;
14057                 }
14058         }
14059         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14060             DMA_RWCTRL_WRITE_BNDRY_16) {
14061                 static struct pci_device_id dma_wait_state_chipsets[] = {
14062                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14063                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14064                         { },
14065                 };
14066
14067                 /* DMA test passed without adjusting DMA boundary,
14068                  * now look for chipsets that are known to expose the
14069                  * DMA bug without failing the test.
14070                  */
14071                 if (pci_dev_present(dma_wait_state_chipsets)) {
14072                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14073                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14074                 } else {
14075                         /* Safe to use the calculated DMA boundary. */
14076                         tp->dma_rwctrl = saved_dma_rwctrl;
14077                 }
14078
14079                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14080         }
14081
14082 out:
14083         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14084 out_nofree:
14085         return ret;
14086 }
14087
14088 static void __devinit tg3_init_link_config(struct tg3 *tp)
14089 {
14090         tp->link_config.advertising =
14091                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14092                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14093                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14094                  ADVERTISED_Autoneg | ADVERTISED_MII);
14095         tp->link_config.speed = SPEED_INVALID;
14096         tp->link_config.duplex = DUPLEX_INVALID;
14097         tp->link_config.autoneg = AUTONEG_ENABLE;
14098         tp->link_config.active_speed = SPEED_INVALID;
14099         tp->link_config.active_duplex = DUPLEX_INVALID;
14100         tp->link_config.phy_is_low_power = 0;
14101         tp->link_config.orig_speed = SPEED_INVALID;
14102         tp->link_config.orig_duplex = DUPLEX_INVALID;
14103         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14104 }
14105
14106 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14107 {
14108         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14109             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14110                 tp->bufmgr_config.mbuf_read_dma_low_water =
14111                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14112                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14113                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14114                 tp->bufmgr_config.mbuf_high_water =
14115                         DEFAULT_MB_HIGH_WATER_57765;
14116
14117                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14118                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14119                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14120                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14121                 tp->bufmgr_config.mbuf_high_water_jumbo =
14122                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14123         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14124                 tp->bufmgr_config.mbuf_read_dma_low_water =
14125                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14126                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14127                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14128                 tp->bufmgr_config.mbuf_high_water =
14129                         DEFAULT_MB_HIGH_WATER_5705;
14130                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14131                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14132                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14133                         tp->bufmgr_config.mbuf_high_water =
14134                                 DEFAULT_MB_HIGH_WATER_5906;
14135                 }
14136
14137                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14138                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14139                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14140                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14141                 tp->bufmgr_config.mbuf_high_water_jumbo =
14142                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14143         } else {
14144                 tp->bufmgr_config.mbuf_read_dma_low_water =
14145                         DEFAULT_MB_RDMA_LOW_WATER;
14146                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14147                         DEFAULT_MB_MACRX_LOW_WATER;
14148                 tp->bufmgr_config.mbuf_high_water =
14149                         DEFAULT_MB_HIGH_WATER;
14150
14151                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14152                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14153                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14154                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14155                 tp->bufmgr_config.mbuf_high_water_jumbo =
14156                         DEFAULT_MB_HIGH_WATER_JUMBO;
14157         }
14158
14159         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14160         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14161 }
14162
14163 static char * __devinit tg3_phy_string(struct tg3 *tp)
14164 {
14165         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14166         case TG3_PHY_ID_BCM5400:        return "5400";
14167         case TG3_PHY_ID_BCM5401:        return "5401";
14168         case TG3_PHY_ID_BCM5411:        return "5411";
14169         case TG3_PHY_ID_BCM5701:        return "5701";
14170         case TG3_PHY_ID_BCM5703:        return "5703";
14171         case TG3_PHY_ID_BCM5704:        return "5704";
14172         case TG3_PHY_ID_BCM5705:        return "5705";
14173         case TG3_PHY_ID_BCM5750:        return "5750";
14174         case TG3_PHY_ID_BCM5752:        return "5752";
14175         case TG3_PHY_ID_BCM5714:        return "5714";
14176         case TG3_PHY_ID_BCM5780:        return "5780";
14177         case TG3_PHY_ID_BCM5755:        return "5755";
14178         case TG3_PHY_ID_BCM5787:        return "5787";
14179         case TG3_PHY_ID_BCM5784:        return "5784";
14180         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14181         case TG3_PHY_ID_BCM5906:        return "5906";
14182         case TG3_PHY_ID_BCM5761:        return "5761";
14183         case TG3_PHY_ID_BCM5718C:       return "5718C";
14184         case TG3_PHY_ID_BCM5718S:       return "5718S";
14185         case TG3_PHY_ID_BCM57765:       return "57765";
14186         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14187         case 0:                 return "serdes";
14188         default:                return "unknown";
14189         }
14190 }
14191
14192 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14193 {
14194         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14195                 strcpy(str, "PCI Express");
14196                 return str;
14197         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14198                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14199
14200                 strcpy(str, "PCIX:");
14201
14202                 if ((clock_ctrl == 7) ||
14203                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14204                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14205                         strcat(str, "133MHz");
14206                 else if (clock_ctrl == 0)
14207                         strcat(str, "33MHz");
14208                 else if (clock_ctrl == 2)
14209                         strcat(str, "50MHz");
14210                 else if (clock_ctrl == 4)
14211                         strcat(str, "66MHz");
14212                 else if (clock_ctrl == 6)
14213                         strcat(str, "100MHz");
14214         } else {
14215                 strcpy(str, "PCI:");
14216                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14217                         strcat(str, "66MHz");
14218                 else
14219                         strcat(str, "33MHz");
14220         }
14221         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14222                 strcat(str, ":32-bit");
14223         else
14224                 strcat(str, ":64-bit");
14225         return str;
14226 }
14227
14228 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14229 {
14230         struct pci_dev *peer;
14231         unsigned int func, devnr = tp->pdev->devfn & ~7;
14232
14233         for (func = 0; func < 8; func++) {
14234                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14235                 if (peer && peer != tp->pdev)
14236                         break;
14237                 pci_dev_put(peer);
14238         }
14239         /* 5704 can be configured in single-port mode, set peer to
14240          * tp->pdev in that case.
14241          */
14242         if (!peer) {
14243                 peer = tp->pdev;
14244                 return peer;
14245         }
14246
14247         /*
14248          * We don't need to keep the refcount elevated; there's no way
14249          * to remove one half of this device without removing the other
14250          */
14251         pci_dev_put(peer);
14252
14253         return peer;
14254 }
14255
14256 static void __devinit tg3_init_coal(struct tg3 *tp)
14257 {
14258         struct ethtool_coalesce *ec = &tp->coal;
14259
14260         memset(ec, 0, sizeof(*ec));
14261         ec->cmd = ETHTOOL_GCOALESCE;
14262         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14263         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14264         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14265         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14266         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14267         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14268         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14269         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14270         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14271
14272         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14273                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14274                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14275                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14276                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14277                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14278         }
14279
14280         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14281                 ec->rx_coalesce_usecs_irq = 0;
14282                 ec->tx_coalesce_usecs_irq = 0;
14283                 ec->stats_block_coalesce_usecs = 0;
14284         }
14285 }
14286
14287 static const struct net_device_ops tg3_netdev_ops = {
14288         .ndo_open               = tg3_open,
14289         .ndo_stop               = tg3_close,
14290         .ndo_start_xmit         = tg3_start_xmit,
14291         .ndo_get_stats          = tg3_get_stats,
14292         .ndo_validate_addr      = eth_validate_addr,
14293         .ndo_set_multicast_list = tg3_set_rx_mode,
14294         .ndo_set_mac_address    = tg3_set_mac_addr,
14295         .ndo_do_ioctl           = tg3_ioctl,
14296         .ndo_tx_timeout         = tg3_tx_timeout,
14297         .ndo_change_mtu         = tg3_change_mtu,
14298 #if TG3_VLAN_TAG_USED
14299         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14300 #endif
14301 #ifdef CONFIG_NET_POLL_CONTROLLER
14302         .ndo_poll_controller    = tg3_poll_controller,
14303 #endif
14304 };
14305
14306 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14307         .ndo_open               = tg3_open,
14308         .ndo_stop               = tg3_close,
14309         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14310         .ndo_get_stats          = tg3_get_stats,
14311         .ndo_validate_addr      = eth_validate_addr,
14312         .ndo_set_multicast_list = tg3_set_rx_mode,
14313         .ndo_set_mac_address    = tg3_set_mac_addr,
14314         .ndo_do_ioctl           = tg3_ioctl,
14315         .ndo_tx_timeout         = tg3_tx_timeout,
14316         .ndo_change_mtu         = tg3_change_mtu,
14317 #if TG3_VLAN_TAG_USED
14318         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14319 #endif
14320 #ifdef CONFIG_NET_POLL_CONTROLLER
14321         .ndo_poll_controller    = tg3_poll_controller,
14322 #endif
14323 };
14324
14325 static int __devinit tg3_init_one(struct pci_dev *pdev,
14326                                   const struct pci_device_id *ent)
14327 {
14328         struct net_device *dev;
14329         struct tg3 *tp;
14330         int i, err, pm_cap;
14331         u32 sndmbx, rcvmbx, intmbx;
14332         char str[40];
14333         u64 dma_mask, persist_dma_mask;
14334
14335         printk_once(KERN_INFO "%s\n", version);
14336
14337         err = pci_enable_device(pdev);
14338         if (err) {
14339                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14340                 return err;
14341         }
14342
14343         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14344         if (err) {
14345                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14346                 goto err_out_disable_pdev;
14347         }
14348
14349         pci_set_master(pdev);
14350
14351         /* Find power-management capability. */
14352         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14353         if (pm_cap == 0) {
14354                 dev_err(&pdev->dev,
14355                         "Cannot find Power Management capability, aborting\n");
14356                 err = -EIO;
14357                 goto err_out_free_res;
14358         }
14359
14360         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14361         if (!dev) {
14362                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14363                 err = -ENOMEM;
14364                 goto err_out_free_res;
14365         }
14366
14367         SET_NETDEV_DEV(dev, &pdev->dev);
14368
14369 #if TG3_VLAN_TAG_USED
14370         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14371 #endif
14372
14373         tp = netdev_priv(dev);
14374         tp->pdev = pdev;
14375         tp->dev = dev;
14376         tp->pm_cap = pm_cap;
14377         tp->rx_mode = TG3_DEF_RX_MODE;
14378         tp->tx_mode = TG3_DEF_TX_MODE;
14379
14380         if (tg3_debug > 0)
14381                 tp->msg_enable = tg3_debug;
14382         else
14383                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14384
14385         /* The word/byte swap controls here control register access byte
14386          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14387          * setting below.
14388          */
14389         tp->misc_host_ctrl =
14390                 MISC_HOST_CTRL_MASK_PCI_INT |
14391                 MISC_HOST_CTRL_WORD_SWAP |
14392                 MISC_HOST_CTRL_INDIR_ACCESS |
14393                 MISC_HOST_CTRL_PCISTATE_RW;
14394
14395         /* The NONFRM (non-frame) byte/word swap controls take effect
14396          * on descriptor entries, anything which isn't packet data.
14397          *
14398          * The StrongARM chips on the board (one for tx, one for rx)
14399          * are running in big-endian mode.
14400          */
14401         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14402                         GRC_MODE_WSWAP_NONFRM_DATA);
14403 #ifdef __BIG_ENDIAN
14404         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14405 #endif
14406         spin_lock_init(&tp->lock);
14407         spin_lock_init(&tp->indirect_lock);
14408         INIT_WORK(&tp->reset_task, tg3_reset_task);
14409
14410         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14411         if (!tp->regs) {
14412                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14413                 err = -ENOMEM;
14414                 goto err_out_free_dev;
14415         }
14416
14417         tg3_init_link_config(tp);
14418
14419         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14420         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14421
14422         dev->ethtool_ops = &tg3_ethtool_ops;
14423         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14424         dev->irq = pdev->irq;
14425
14426         err = tg3_get_invariants(tp);
14427         if (err) {
14428                 dev_err(&pdev->dev,
14429                         "Problem fetching invariants of chip, aborting\n");
14430                 goto err_out_iounmap;
14431         }
14432
14433         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14434             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14435                 dev->netdev_ops = &tg3_netdev_ops;
14436         else
14437                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14438
14439
14440         /* The EPB bridge inside 5714, 5715, and 5780 and any
14441          * device behind the EPB cannot support DMA addresses > 40-bit.
14442          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14443          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14444          * do DMA address check in tg3_start_xmit().
14445          */
14446         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14447                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14448         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14449                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14450 #ifdef CONFIG_HIGHMEM
14451                 dma_mask = DMA_BIT_MASK(64);
14452 #endif
14453         } else
14454                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14455
14456         /* Configure DMA attributes. */
14457         if (dma_mask > DMA_BIT_MASK(32)) {
14458                 err = pci_set_dma_mask(pdev, dma_mask);
14459                 if (!err) {
14460                         dev->features |= NETIF_F_HIGHDMA;
14461                         err = pci_set_consistent_dma_mask(pdev,
14462                                                           persist_dma_mask);
14463                         if (err < 0) {
14464                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14465                                         "DMA for consistent allocations\n");
14466                                 goto err_out_iounmap;
14467                         }
14468                 }
14469         }
14470         if (err || dma_mask == DMA_BIT_MASK(32)) {
14471                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14472                 if (err) {
14473                         dev_err(&pdev->dev,
14474                                 "No usable DMA configuration, aborting\n");
14475                         goto err_out_iounmap;
14476                 }
14477         }
14478
14479         tg3_init_bufmgr_config(tp);
14480
14481         /* Selectively allow TSO based on operating conditions */
14482         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14483             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14484                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14485         else {
14486                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14487                 tp->fw_needed = NULL;
14488         }
14489
14490         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14491                 tp->fw_needed = FIRMWARE_TG3;
14492
14493         /* TSO is on by default on chips that support hardware TSO.
14494          * Firmware TSO on older chips gives lower performance, so it
14495          * is off by default, but can be enabled using ethtool.
14496          */
14497         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14498             (dev->features & NETIF_F_IP_CSUM))
14499                 dev->features |= NETIF_F_TSO;
14500
14501         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14502             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14503                 if (dev->features & NETIF_F_IPV6_CSUM)
14504                         dev->features |= NETIF_F_TSO6;
14505                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14506                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14507                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14508                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14509                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14510                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14511                         dev->features |= NETIF_F_TSO_ECN;
14512         }
14513
14514         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14515             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14516             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14517                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14518                 tp->rx_pending = 63;
14519         }
14520
14521         err = tg3_get_device_address(tp);
14522         if (err) {
14523                 dev_err(&pdev->dev,
14524                         "Could not obtain valid ethernet address, aborting\n");
14525                 goto err_out_iounmap;
14526         }
14527
14528         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14529                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14530                 if (!tp->aperegs) {
14531                         dev_err(&pdev->dev,
14532                                 "Cannot map APE registers, aborting\n");
14533                         err = -ENOMEM;
14534                         goto err_out_iounmap;
14535                 }
14536
14537                 tg3_ape_lock_init(tp);
14538
14539                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14540                         tg3_read_dash_ver(tp);
14541         }
14542
14543         /*
14544          * Reset chip in case UNDI or EFI driver did not shutdown
14545          * DMA self test will enable WDMAC and we'll see (spurious)
14546          * pending DMA on the PCI bus at that point.
14547          */
14548         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14549             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14550                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14551                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14552         }
14553
14554         err = tg3_test_dma(tp);
14555         if (err) {
14556                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14557                 goto err_out_apeunmap;
14558         }
14559
14560         /* flow control autonegotiation is default behavior */
14561         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14562         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14563
14564         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14565         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14566         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14567         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14568                 struct tg3_napi *tnapi = &tp->napi[i];
14569
14570                 tnapi->tp = tp;
14571                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14572
14573                 tnapi->int_mbox = intmbx;
14574                 if (i < 4)
14575                         intmbx += 0x8;
14576                 else
14577                         intmbx += 0x4;
14578
14579                 tnapi->consmbox = rcvmbx;
14580                 tnapi->prodmbox = sndmbx;
14581
14582                 if (i) {
14583                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14584                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14585                 } else {
14586                         tnapi->coal_now = HOSTCC_MODE_NOW;
14587                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14588                 }
14589
14590                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14591                         break;
14592
14593                 /*
14594                  * If we support MSIX, we'll be using RSS.  If we're using
14595                  * RSS, the first vector only handles link interrupts and the
14596                  * remaining vectors handle rx and tx interrupts.  Reuse the
14597                  * mailbox values for the next iteration.  The values we setup
14598                  * above are still useful for the single vectored mode.
14599                  */
14600                 if (!i)
14601                         continue;
14602
14603                 rcvmbx += 0x8;
14604
14605                 if (sndmbx & 0x4)
14606                         sndmbx -= 0x4;
14607                 else
14608                         sndmbx += 0xc;
14609         }
14610
14611         tg3_init_coal(tp);
14612
14613         pci_set_drvdata(pdev, dev);
14614
14615         err = register_netdev(dev);
14616         if (err) {
14617                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14618                 goto err_out_apeunmap;
14619         }
14620
14621         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14622                     tp->board_part_number,
14623                     tp->pci_chip_rev_id,
14624                     tg3_bus_string(tp, str),
14625                     dev->dev_addr);
14626
14627         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14628                 struct phy_device *phydev;
14629                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14630                 netdev_info(dev,
14631                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14632                             phydev->drv->name, dev_name(&phydev->dev));
14633         } else
14634                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14635                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14636                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14637                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14638                               "10/100/1000Base-T")),
14639                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14640
14641         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14642                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14643                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14644                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14645                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14646                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14647         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14648                     tp->dma_rwctrl,
14649                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14650                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14651
14652         return 0;
14653
14654 err_out_apeunmap:
14655         if (tp->aperegs) {
14656                 iounmap(tp->aperegs);
14657                 tp->aperegs = NULL;
14658         }
14659
14660 err_out_iounmap:
14661         if (tp->regs) {
14662                 iounmap(tp->regs);
14663                 tp->regs = NULL;
14664         }
14665
14666 err_out_free_dev:
14667         free_netdev(dev);
14668
14669 err_out_free_res:
14670         pci_release_regions(pdev);
14671
14672 err_out_disable_pdev:
14673         pci_disable_device(pdev);
14674         pci_set_drvdata(pdev, NULL);
14675         return err;
14676 }
14677
14678 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14679 {
14680         struct net_device *dev = pci_get_drvdata(pdev);
14681
14682         if (dev) {
14683                 struct tg3 *tp = netdev_priv(dev);
14684
14685                 if (tp->fw)
14686                         release_firmware(tp->fw);
14687
14688                 flush_scheduled_work();
14689
14690                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14691                         tg3_phy_fini(tp);
14692                         tg3_mdio_fini(tp);
14693                 }
14694
14695                 unregister_netdev(dev);
14696                 if (tp->aperegs) {
14697                         iounmap(tp->aperegs);
14698                         tp->aperegs = NULL;
14699                 }
14700                 if (tp->regs) {
14701                         iounmap(tp->regs);
14702                         tp->regs = NULL;
14703                 }
14704                 free_netdev(dev);
14705                 pci_release_regions(pdev);
14706                 pci_disable_device(pdev);
14707                 pci_set_drvdata(pdev, NULL);
14708         }
14709 }
14710
14711 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14712 {
14713         struct net_device *dev = pci_get_drvdata(pdev);
14714         struct tg3 *tp = netdev_priv(dev);
14715         pci_power_t target_state;
14716         int err;
14717
14718         /* PCI register 4 needs to be saved whether netif_running() or not.
14719          * MSI address and data need to be saved if using MSI and
14720          * netif_running().
14721          */
14722         pci_save_state(pdev);
14723
14724         if (!netif_running(dev))
14725                 return 0;
14726
14727         flush_scheduled_work();
14728         tg3_phy_stop(tp);
14729         tg3_netif_stop(tp);
14730
14731         del_timer_sync(&tp->timer);
14732
14733         tg3_full_lock(tp, 1);
14734         tg3_disable_ints(tp);
14735         tg3_full_unlock(tp);
14736
14737         netif_device_detach(dev);
14738
14739         tg3_full_lock(tp, 0);
14740         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14741         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14742         tg3_full_unlock(tp);
14743
14744         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14745
14746         err = tg3_set_power_state(tp, target_state);
14747         if (err) {
14748                 int err2;
14749
14750                 tg3_full_lock(tp, 0);
14751
14752                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14753                 err2 = tg3_restart_hw(tp, 1);
14754                 if (err2)
14755                         goto out;
14756
14757                 tp->timer.expires = jiffies + tp->timer_offset;
14758                 add_timer(&tp->timer);
14759
14760                 netif_device_attach(dev);
14761                 tg3_netif_start(tp);
14762
14763 out:
14764                 tg3_full_unlock(tp);
14765
14766                 if (!err2)
14767                         tg3_phy_start(tp);
14768         }
14769
14770         return err;
14771 }
14772
14773 static int tg3_resume(struct pci_dev *pdev)
14774 {
14775         struct net_device *dev = pci_get_drvdata(pdev);
14776         struct tg3 *tp = netdev_priv(dev);
14777         int err;
14778
14779         pci_restore_state(tp->pdev);
14780
14781         if (!netif_running(dev))
14782                 return 0;
14783
14784         err = tg3_set_power_state(tp, PCI_D0);
14785         if (err)
14786                 return err;
14787
14788         netif_device_attach(dev);
14789
14790         tg3_full_lock(tp, 0);
14791
14792         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14793         err = tg3_restart_hw(tp, 1);
14794         if (err)
14795                 goto out;
14796
14797         tp->timer.expires = jiffies + tp->timer_offset;
14798         add_timer(&tp->timer);
14799
14800         tg3_netif_start(tp);
14801
14802 out:
14803         tg3_full_unlock(tp);
14804
14805         if (!err)
14806                 tg3_phy_start(tp);
14807
14808         return err;
14809 }
14810
14811 static struct pci_driver tg3_driver = {
14812         .name           = DRV_MODULE_NAME,
14813         .id_table       = tg3_pci_tbl,
14814         .probe          = tg3_init_one,
14815         .remove         = __devexit_p(tg3_remove_one),
14816         .suspend        = tg3_suspend,
14817         .resume         = tg3_resume
14818 };
14819
14820 static int __init tg3_init(void)
14821 {
14822         return pci_register_driver(&tg3_driver);
14823 }
14824
14825 static void __exit tg3_cleanup(void)
14826 {
14827         pci_unregister_driver(&tg3_driver);
14828 }
14829
14830 module_init(tg3_init);
14831 module_exit(tg3_cleanup);