drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/brcmphy.h>
  37 #include <linux/if_vlan.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/prefetch.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/firmware.h>
  44
  45 #include <net/checksum.h>
  46 #include <net/ip.h>
  47
  48 #include <asm/system.h>
  49 #include <asm/io.h>
  50 #include <asm/byteorder.h>
  51 #include <asm/uaccess.h>
  52
  53 #ifdef CONFIG_SPARC
  54 #include <asm/idprom.h>
  55 #include <asm/prom.h>
  56 #endif
  57
  58 #define BAR_0   0
  59 #define BAR_2   2
  60
  61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  62 #define TG3_VLAN_TAG_USED 1
  63 #else
  64 #define TG3_VLAN_TAG_USED 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define DRV_MODULE_VERSION      "3.110"
  71 #define DRV_MODULE_RELDATE      "April 9, 2010"
  72
  73 #define TG3_DEF_MAC_MODE        0
  74 #define TG3_DEF_RX_MODE         0
  75 #define TG3_DEF_TX_MODE         0
  76 #define TG3_DEF_MSG_ENABLE        \
  77         (NETIF_MSG_DRV          | \
  78          NETIF_MSG_PROBE        | \
  79          NETIF_MSG_LINK         | \
  80          NETIF_MSG_TIMER        | \
  81          NETIF_MSG_IFDOWN       | \
  82          NETIF_MSG_IFUP         | \
  83          NETIF_MSG_RX_ERR       | \
  84          NETIF_MSG_TX_ERR)
  85
  86 /* length of time before we decide the hardware is borked,
  87  * and dev->tx_timeout() should be called to fix the problem
  88  */
  89 #define TG3_TX_TIMEOUT                  (5 * HZ)
  90
  91 /* hardware minimum and maximum for a single frame's data payload */
  92 #define TG3_MIN_MTU                     60
  93 #define TG3_MAX_MTU(tp) \
  94         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  95
  96 /* These numbers seem to be hard coded in the NIC firmware somehow.
  97  * You can't change the ring sizes, but you can change where you place
  98  * them in the NIC onboard memory.
  99  */
 100 #define TG3_RX_RING_SIZE                512
 101 #define TG3_DEF_RX_RING_PENDING         200
 102 #define TG3_RX_JUMBO_RING_SIZE          256
 103 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 104 #define TG3_RSS_INDIR_TBL_SIZE          128
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 114           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 115
 116 #define TG3_TX_RING_SIZE                512
 117 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 118
 119 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 120                                  TG3_RX_RING_SIZE)
 121 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 122                                  TG3_RX_JUMBO_RING_SIZE)
 123 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RCB_RING_SIZE(tp))
 125 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 126                                  TG3_TX_RING_SIZE)
 127 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 128
 129 #define TG3_RX_DMA_ALIGN                16
 130 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 131
 132 #define TG3_DMA_BYTE_ENAB               64
 133
 134 #define TG3_RX_STD_DMA_SZ               1536
 135 #define TG3_RX_JMB_DMA_SZ               9046
 136
 137 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 138
 139 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 140 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 141
 142 #define TG3_RX_STD_BUFF_RING_SIZE \
 143         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 144
 145 #define TG3_RX_JMB_BUFF_RING_SIZE \
 146         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 147
 148 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 149  * that are at least dword aligned when used in PCIX mode.  The driver
 150  * works around this bug by double copying the packet.  This workaround
 151  * is built into the normal double copy length check for efficiency.
 152  *
 153  * However, the double copy is only necessary on those architectures
 154  * where unaligned memory accesses are inefficient.  For those architectures
 155  * where unaligned memory accesses incur little penalty, we can reintegrate
 156  * the 5701 in the normal rx path.  Doing so saves a device structure
 157  * dereference by hardcoding the double copy threshold in place.
 158  */
 159 #define TG3_RX_COPY_THRESHOLD           256
 160 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 161         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 162 #else
 163         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 164 #endif
 165
 166 /* minimum number of free TX descriptors required to wake up TX process */
 167 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 168
 169 #define TG3_RAW_IP_ALIGN 2
 170
 171 /* number of ETHTOOL_GSTATS u64's */
 172 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 173
 174 #define TG3_NUM_TEST            6
 175
 176 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 177
 178 #define FIRMWARE_TG3            "tigon/tg3.bin"
 179 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 180 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 181
 182 static char version[] __devinitdata =
 183         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 184
 185 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 186 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 187 MODULE_LICENSE("GPL");
 188 MODULE_VERSION(DRV_MODULE_VERSION);
 189 MODULE_FIRMWARE(FIRMWARE_TG3);
 190 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 191 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 192
 193 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 194 module_param(tg3_debug, int, 0);
 195 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 196
 197 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 280         {}
 281 };
 282
 283 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 284
 285 static const struct {
 286         const char string[ETH_GSTRING_LEN];
 287 } ethtool_stats_keys[TG3_NUM_STATS] = {
 288         { "rx_octets" },
 289         { "rx_fragments" },
 290         { "rx_ucast_packets" },
 291         { "rx_mcast_packets" },
 292         { "rx_bcast_packets" },
 293         { "rx_fcs_errors" },
 294         { "rx_align_errors" },
 295         { "rx_xon_pause_rcvd" },
 296         { "rx_xoff_pause_rcvd" },
 297         { "rx_mac_ctrl_rcvd" },
 298         { "rx_xoff_entered" },
 299         { "rx_frame_too_long_errors" },
 300         { "rx_jabbers" },
 301         { "rx_undersize_packets" },
 302         { "rx_in_length_errors" },
 303         { "rx_out_length_errors" },
 304         { "rx_64_or_less_octet_packets" },
 305         { "rx_65_to_127_octet_packets" },
 306         { "rx_128_to_255_octet_packets" },
 307         { "rx_256_to_511_octet_packets" },
 308         { "rx_512_to_1023_octet_packets" },
 309         { "rx_1024_to_1522_octet_packets" },
 310         { "rx_1523_to_2047_octet_packets" },
 311         { "rx_2048_to_4095_octet_packets" },
 312         { "rx_4096_to_8191_octet_packets" },
 313         { "rx_8192_to_9022_octet_packets" },
 314
 315         { "tx_octets" },
 316         { "tx_collisions" },
 317
 318         { "tx_xon_sent" },
 319         { "tx_xoff_sent" },
 320         { "tx_flow_control" },
 321         { "tx_mac_errors" },
 322         { "tx_single_collisions" },
 323         { "tx_mult_collisions" },
 324         { "tx_deferred" },
 325         { "tx_excessive_collisions" },
 326         { "tx_late_collisions" },
 327         { "tx_collide_2times" },
 328         { "tx_collide_3times" },
 329         { "tx_collide_4times" },
 330         { "tx_collide_5times" },
 331         { "tx_collide_6times" },
 332         { "tx_collide_7times" },
 333         { "tx_collide_8times" },
 334         { "tx_collide_9times" },
 335         { "tx_collide_10times" },
 336         { "tx_collide_11times" },
 337         { "tx_collide_12times" },
 338         { "tx_collide_13times" },
 339         { "tx_collide_14times" },
 340         { "tx_collide_15times" },
 341         { "tx_ucast_packets" },
 342         { "tx_mcast_packets" },
 343         { "tx_bcast_packets" },
 344         { "tx_carrier_sense_errors" },
 345         { "tx_discards" },
 346         { "tx_errors" },
 347
 348         { "dma_writeq_full" },
 349         { "dma_write_prioq_full" },
 350         { "rxbds_empty" },
 351         { "rx_discards" },
 352         { "rx_errors" },
 353         { "rx_threshold_hit" },
 354
 355         { "dma_readq_full" },
 356         { "dma_read_prioq_full" },
 357         { "tx_comp_queue_full" },
 358
 359         { "ring_set_send_prod_index" },
 360         { "ring_status_update" },
 361         { "nic_irqs" },
 362         { "nic_avoided_irqs" },
 363         { "nic_tx_threshold_hit" }
 364 };
 365
 366 static const struct {
 367         const char string[ETH_GSTRING_LEN];
 368 } ethtool_test_keys[TG3_NUM_TEST] = {
 369         { "nvram test     (online) " },
 370         { "link test      (online) " },
 371         { "register test  (offline)" },
 372         { "memory test    (offline)" },
 373         { "loopback test  (offline)" },
 374         { "interrupt test (offline)" },
 375 };
 376
 377 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 378 {
 379         writel(val, tp->regs + off);
 380 }
 381
 382 static u32 tg3_read32(struct tg3 *tp, u32 off)
 383 {
 384         return readl(tp->regs + off);
 385 }
 386
 387 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 388 {
 389         writel(val, tp->aperegs + off);
 390 }
 391
 392 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 393 {
 394         return readl(tp->aperegs + off);
 395 }
 396
 397 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 398 {
 399         unsigned long flags;
 400
 401         spin_lock_irqsave(&tp->indirect_lock, flags);
 402         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 404         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 405 }
 406
 407 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 408 {
 409         writel(val, tp->regs + off);
 410         readl(tp->regs + off);
 411 }
 412
 413 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 414 {
 415         unsigned long flags;
 416         u32 val;
 417
 418         spin_lock_irqsave(&tp->indirect_lock, flags);
 419         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 420         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 421         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 422         return val;
 423 }
 424
 425 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 426 {
 427         unsigned long flags;
 428
 429         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 430                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 431                                        TG3_64BIT_REG_LOW, val);
 432                 return;
 433         }
 434         if (off == TG3_RX_STD_PROD_IDX_REG) {
 435                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 436                                        TG3_64BIT_REG_LOW, val);
 437                 return;
 438         }
 439
 440         spin_lock_irqsave(&tp->indirect_lock, flags);
 441         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 443         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 444
 445         /* In indirect mode when disabling interrupts, we also need
 446          * to clear the interrupt bit in the GRC local ctrl register.
 447          */
 448         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 449             (val == 0x1)) {
 450                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 451                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 452         }
 453 }
 454
 455 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 456 {
 457         unsigned long flags;
 458         u32 val;
 459
 460         spin_lock_irqsave(&tp->indirect_lock, flags);
 461         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 462         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 463         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 464         return val;
 465 }
 466
 467 /* usec_wait specifies the wait time in usec when writing to certain registers
 468  * where it is unsafe to read back the register without some delay.
 469  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 470  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 471  */
 472 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 473 {
 474         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 475             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 476                 /* Non-posted methods */
 477                 tp->write32(tp, off, val);
 478         else {
 479                 /* Posted method */
 480                 tg3_write32(tp, off, val);
 481                 if (usec_wait)
 482                         udelay(usec_wait);
 483                 tp->read32(tp, off);
 484         }
 485         /* Wait again after the read for the posted method to guarantee that
 486          * the wait time is met.
 487          */
 488         if (usec_wait)
 489                 udelay(usec_wait);
 490 }
 491
 492 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 493 {
 494         tp->write32_mbox(tp, off, val);
 495         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 496             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 497                 tp->read32_mbox(tp, off);
 498 }
 499
 500 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 501 {
 502         void __iomem *mbox = tp->regs + off;
 503         writel(val, mbox);
 504         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 505                 writel(val, mbox);
 506         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 507                 readl(mbox);
 508 }
 509
 510 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 511 {
 512         return readl(tp->regs + off + GRCMBOX_BASE);
 513 }
 514
 515 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 516 {
 517         writel(val, tp->regs + off + GRCMBOX_BASE);
 518 }
 519
 520 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 521 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 522 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 523 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 524 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 525
 526 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 527 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 528 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 529 #define tr32(reg)                       tp->read32(tp, reg)
 530
 531 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 532 {
 533         unsigned long flags;
 534
 535         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 536             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 537                 return;
 538
 539         spin_lock_irqsave(&tp->indirect_lock, flags);
 540         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 541                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 543
 544                 /* Always leave this as zero. */
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 546         } else {
 547                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 548                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 549
 550                 /* Always leave this as zero. */
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 552         }
 553         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 554 }
 555
 556 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 557 {
 558         unsigned long flags;
 559
 560         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 561             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 562                 *val = 0;
 563                 return;
 564         }
 565
 566         spin_lock_irqsave(&tp->indirect_lock, flags);
 567         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 568                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 569                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 570
 571                 /* Always leave this as zero. */
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 573         } else {
 574                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 575                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 576
 577                 /* Always leave this as zero. */
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 579         }
 580         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 581 }
 582
 583 static void tg3_ape_lock_init(struct tg3 *tp)
 584 {
 585         int i;
 586         u32 regbase;
 587
 588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 589                 regbase = TG3_APE_LOCK_GRANT;
 590         else
 591                 regbase = TG3_APE_PER_LOCK_GRANT;
 592
 593         /* Make sure the driver hasn't any stale locks. */
 594         for (i = 0; i < 8; i++)
 595                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 596 }
 597
 598 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 599 {
 600         int i, off;
 601         int ret = 0;
 602         u32 status, req, gnt;
 603
 604         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 605                 return 0;
 606
 607         switch (locknum) {
 608         case TG3_APE_LOCK_GRC:
 609         case TG3_APE_LOCK_MEM:
 610                 break;
 611         default:
 612                 return -EINVAL;
 613         }
 614
 615         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 616                 req = TG3_APE_LOCK_REQ;
 617                 gnt = TG3_APE_LOCK_GRANT;
 618         } else {
 619                 req = TG3_APE_PER_LOCK_REQ;
 620                 gnt = TG3_APE_PER_LOCK_GRANT;
 621         }
 622
 623         off = 4 * locknum;
 624
 625         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 626
 627         /* Wait for up to 1 millisecond to acquire lock. */
 628         for (i = 0; i < 100; i++) {
 629                 status = tg3_ape_read32(tp, gnt + off);
 630                 if (status == APE_LOCK_GRANT_DRIVER)
 631                         break;
 632                 udelay(10);
 633         }
 634
 635         if (status != APE_LOCK_GRANT_DRIVER) {
 636                 /* Revoke the lock request. */
 637                 tg3_ape_write32(tp, gnt + off,
 638                                 APE_LOCK_GRANT_DRIVER);
 639
 640                 ret = -EBUSY;
 641         }
 642
 643         return ret;
 644 }
 645
 646 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 647 {
 648         u32 gnt;
 649
 650         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 651                 return;
 652
 653         switch (locknum) {
 654         case TG3_APE_LOCK_GRC:
 655         case TG3_APE_LOCK_MEM:
 656                 break;
 657         default:
 658                 return;
 659         }
 660
 661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 662                 gnt = TG3_APE_LOCK_GRANT;
 663         else
 664                 gnt = TG3_APE_PER_LOCK_GRANT;
 665
 666         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 667 }
 668
 669 static void tg3_disable_ints(struct tg3 *tp)
 670 {
 671         int i;
 672
 673         tw32(TG3PCI_MISC_HOST_CTRL,
 674              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 675         for (i = 0; i < tp->irq_max; i++)
 676                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 677 }
 678
 679 static void tg3_enable_ints(struct tg3 *tp)
 680 {
 681         int i;
 682
 683         tp->irq_sync = 0;
 684         wmb();
 685
 686         tw32(TG3PCI_MISC_HOST_CTRL,
 687              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 688
 689         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 690         for (i = 0; i < tp->irq_cnt; i++) {
 691                 struct tg3_napi *tnapi = &tp->napi[i];
 692
 693                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 694                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 695                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 696
 697                 tp->coal_now |= tnapi->coal_now;
 698         }
 699
 700         /* Force an initial interrupt */
 701         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 702             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 703                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 704         else
 705                 tw32(HOSTCC_MODE, tp->coal_now);
 706
 707         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 708 }
 709
 710 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 711 {
 712         struct tg3 *tp = tnapi->tp;
 713         struct tg3_hw_status *sblk = tnapi->hw_status;
 714         unsigned int work_exists = 0;
 715
 716         /* check for phy events */
 717         if (!(tp->tg3_flags &
 718               (TG3_FLAG_USE_LINKCHG_REG |
 719                TG3_FLAG_POLL_SERDES))) {
 720                 if (sblk->status & SD_STATUS_LINK_CHG)
 721                         work_exists = 1;
 722         }
 723         /* check for RX/TX work to do */
 724         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 725             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 726                 work_exists = 1;
 727
 728         return work_exists;
 729 }
 730
 731 /* tg3_int_reenable
 732  *  similar to tg3_enable_ints, but it accurately determines whether there
 733  *  is new work pending and can return without flushing the PIO write
 734  *  which reenables interrupts
 735  */
 736 static void tg3_int_reenable(struct tg3_napi *tnapi)
 737 {
 738         struct tg3 *tp = tnapi->tp;
 739
 740         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 741         mmiowb();
 742
 743         /* When doing tagged status, this work check is unnecessary.
 744          * The last_tag we write above tells the chip which piece of
 745          * work we've completed.
 746          */
 747         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 748             tg3_has_work(tnapi))
 749                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 750                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 751 }
 752
 753 static void tg3_napi_disable(struct tg3 *tp)
 754 {
 755         int i;
 756
 757         for (i = tp->irq_cnt - 1; i >= 0; i--)
 758                 napi_disable(&tp->napi[i].napi);
 759 }
 760
 761 static void tg3_napi_enable(struct tg3 *tp)
 762 {
 763         int i;
 764
 765         for (i = 0; i < tp->irq_cnt; i++)
 766                 napi_enable(&tp->napi[i].napi);
 767 }
 768
 769 static inline void tg3_netif_stop(struct tg3 *tp)
 770 {
 771         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 772         tg3_napi_disable(tp);
 773         netif_tx_disable(tp->dev);
 774 }
 775
 776 static inline void tg3_netif_start(struct tg3 *tp)
 777 {
 778         /* NOTE: unconditional netif_tx_wake_all_queues is only
 779          * appropriate so long as all callers are assured to
 780          * have free tx slots (such as after tg3_init_hw)
 781          */
 782         netif_tx_wake_all_queues(tp->dev);
 783
 784         tg3_napi_enable(tp);
 785         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
 786         tg3_enable_ints(tp);
 787 }
 788
 789 static void tg3_switch_clocks(struct tg3 *tp)
 790 {
 791         u32 clock_ctrl;
 792         u32 orig_clock_ctrl;
 793
 794         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 795             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 796                 return;
 797
 798         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 799
 800         orig_clock_ctrl = clock_ctrl;
 801         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 802                        CLOCK_CTRL_CLKRUN_OENABLE |
 803                        0x1f);
 804         tp->pci_clock_ctrl = clock_ctrl;
 805
 806         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 807                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 808                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 809                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 810                 }
 811         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 812                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 813                             clock_ctrl |
 814                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 815                             40);
 816                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 817                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 818                             40);
 819         }
 820         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 821 }
 822
 823 #define PHY_BUSY_LOOPS  5000
 824
 825 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 826 {
 827         u32 frame_val;
 828         unsigned int loops;
 829         int ret;
 830
 831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 832                 tw32_f(MAC_MI_MODE,
 833                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 834                 udelay(80);
 835         }
 836
 837         *val = 0x0;
 838
 839         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 840                       MI_COM_PHY_ADDR_MASK);
 841         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 842                       MI_COM_REG_ADDR_MASK);
 843         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 844
 845         tw32_f(MAC_MI_COM, frame_val);
 846
 847         loops = PHY_BUSY_LOOPS;
 848         while (loops != 0) {
 849                 udelay(10);
 850                 frame_val = tr32(MAC_MI_COM);
 851
 852                 if ((frame_val & MI_COM_BUSY) == 0) {
 853                         udelay(5);
 854                         frame_val = tr32(MAC_MI_COM);
 855                         break;
 856                 }
 857                 loops -= 1;
 858         }
 859
 860         ret = -EBUSY;
 861         if (loops != 0) {
 862                 *val = frame_val & MI_COM_DATA_MASK;
 863                 ret = 0;
 864         }
 865
 866         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 867                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 868                 udelay(80);
 869         }
 870
 871         return ret;
 872 }
 873
 874 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 875 {
 876         u32 frame_val;
 877         unsigned int loops;
 878         int ret;
 879
 880         if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
 881             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 882                 return 0;
 883
 884         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 885                 tw32_f(MAC_MI_MODE,
 886                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 887                 udelay(80);
 888         }
 889
 890         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 891                       MI_COM_PHY_ADDR_MASK);
 892         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 893                       MI_COM_REG_ADDR_MASK);
 894         frame_val |= (val & MI_COM_DATA_MASK);
 895         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 896
 897         tw32_f(MAC_MI_COM, frame_val);
 898
 899         loops = PHY_BUSY_LOOPS;
 900         while (loops != 0) {
 901                 udelay(10);
 902                 frame_val = tr32(MAC_MI_COM);
 903                 if ((frame_val & MI_COM_BUSY) == 0) {
 904                         udelay(5);
 905                         frame_val = tr32(MAC_MI_COM);
 906                         break;
 907                 }
 908                 loops -= 1;
 909         }
 910
 911         ret = -EBUSY;
 912         if (loops != 0)
 913                 ret = 0;
 914
 915         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 916                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 917                 udelay(80);
 918         }
 919
 920         return ret;
 921 }
 922
 923 static int tg3_bmcr_reset(struct tg3 *tp)
 924 {
 925         u32 phy_control;
 926         int limit, err;
 927
 928         /* OK, reset it, and poll the BMCR_RESET bit until it
 929          * clears or we time out.
 930          */
 931         phy_control = BMCR_RESET;
 932         err = tg3_writephy(tp, MII_BMCR, phy_control);
 933         if (err != 0)
 934                 return -EBUSY;
 935
 936         limit = 5000;
 937         while (limit--) {
 938                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 939                 if (err != 0)
 940                         return -EBUSY;
 941
 942                 if ((phy_control & BMCR_RESET) == 0) {
 943                         udelay(40);
 944                         break;
 945                 }
 946                 udelay(10);
 947         }
 948         if (limit < 0)
 949                 return -EBUSY;
 950
 951         return 0;
 952 }
 953
 954 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 955 {
 956         struct tg3 *tp = bp->priv;
 957         u32 val;
 958
 959         spin_lock_bh(&tp->lock);
 960
 961         if (tg3_readphy(tp, reg, &val))
 962                 val = -EIO;
 963
 964         spin_unlock_bh(&tp->lock);
 965
 966         return val;
 967 }
 968
 969 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 970 {
 971         struct tg3 *tp = bp->priv;
 972         u32 ret = 0;
 973
 974         spin_lock_bh(&tp->lock);
 975
 976         if (tg3_writephy(tp, reg, val))
 977                 ret = -EIO;
 978
 979         spin_unlock_bh(&tp->lock);
 980
 981         return ret;
 982 }
 983
 984 static int tg3_mdio_reset(struct mii_bus *bp)
 985 {
 986         return 0;
 987 }
 988
 989 static void tg3_mdio_config_5785(struct tg3 *tp)
 990 {
 991         u32 val;
 992         struct phy_device *phydev;
 993
 994         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 995         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 996         case PHY_ID_BCM50610:
 997         case PHY_ID_BCM50610M:
 998                 val = MAC_PHYCFG2_50610_LED_MODES;
 999                 break;
1000         case PHY_ID_BCMAC131:
1001                 val = MAC_PHYCFG2_AC131_LED_MODES;
1002                 break;
1003         case PHY_ID_RTL8211C:
1004                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1005                 break;
1006         case PHY_ID_RTL8201E:
1007                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1008                 break;
1009         default:
1010                 return;
1011         }
1012
1013         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1014                 tw32(MAC_PHYCFG2, val);
1015
1016                 val = tr32(MAC_PHYCFG1);
1017                 val &= ~(MAC_PHYCFG1_RGMII_INT |
1018                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1019                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1020                 tw32(MAC_PHYCFG1, val);
1021
1022                 return;
1023         }
1024
1025         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
1026                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1027                        MAC_PHYCFG2_FMODE_MASK_MASK |
1028                        MAC_PHYCFG2_GMODE_MASK_MASK |
1029                        MAC_PHYCFG2_ACT_MASK_MASK   |
1030                        MAC_PHYCFG2_QUAL_MASK_MASK |
1031                        MAC_PHYCFG2_INBAND_ENABLE;
1032
1033         tw32(MAC_PHYCFG2, val);
1034
1035         val = tr32(MAC_PHYCFG1);
1036         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1037                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1038         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1039                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1040                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1041                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1042                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1043         }
1044         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1045                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1046         tw32(MAC_PHYCFG1, val);
1047
1048         val = tr32(MAC_EXT_RGMII_MODE);
1049         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1050                  MAC_RGMII_MODE_RX_QUALITY |
1051                  MAC_RGMII_MODE_RX_ACTIVITY |
1052                  MAC_RGMII_MODE_RX_ENG_DET |
1053                  MAC_RGMII_MODE_TX_ENABLE |
1054                  MAC_RGMII_MODE_TX_LOWPWR |
1055                  MAC_RGMII_MODE_TX_RESET);
1056         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1057                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1058                         val |= MAC_RGMII_MODE_RX_INT_B |
1059                                MAC_RGMII_MODE_RX_QUALITY |
1060                                MAC_RGMII_MODE_RX_ACTIVITY |
1061                                MAC_RGMII_MODE_RX_ENG_DET;
1062                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1063                         val |= MAC_RGMII_MODE_TX_ENABLE |
1064                                MAC_RGMII_MODE_TX_LOWPWR |
1065                                MAC_RGMII_MODE_TX_RESET;
1066         }
1067         tw32(MAC_EXT_RGMII_MODE, val);
1068 }
1069
1070 static void tg3_mdio_start(struct tg3 *tp)
1071 {
1072         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1073         tw32_f(MAC_MI_MODE, tp->mi_mode);
1074         udelay(80);
1075
1076         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1077             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1078                 tg3_mdio_config_5785(tp);
1079 }
1080
1081 static int tg3_mdio_init(struct tg3 *tp)
1082 {
1083         int i;
1084         u32 reg;
1085         struct phy_device *phydev;
1086
1087         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1088                 u32 is_serdes;
1089
1090                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1091
1092                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1093                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1094                 else
1095                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1096                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1097                 if (is_serdes)
1098                         tp->phy_addr += 7;
1099         } else
1100                 tp->phy_addr = TG3_PHY_MII_ADDR;
1101
1102         tg3_mdio_start(tp);
1103
1104         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1105             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1106                 return 0;
1107
1108         tp->mdio_bus = mdiobus_alloc();
1109         if (tp->mdio_bus == NULL)
1110                 return -ENOMEM;
1111
1112         tp->mdio_bus->name     = "tg3 mdio bus";
1113         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1114                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1115         tp->mdio_bus->priv     = tp;
1116         tp->mdio_bus->parent   = &tp->pdev->dev;
1117         tp->mdio_bus->read     = &tg3_mdio_read;
1118         tp->mdio_bus->write    = &tg3_mdio_write;
1119         tp->mdio_bus->reset    = &tg3_mdio_reset;
1120         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1121         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1122
1123         for (i = 0; i < PHY_MAX_ADDR; i++)
1124                 tp->mdio_bus->irq[i] = PHY_POLL;
1125
1126         /* The bus registration will look for all the PHYs on the mdio bus.
1127          * Unfortunately, it does not ensure the PHY is powered up before
1128          * accessing the PHY ID registers.  A chip reset is the
1129          * quickest way to bring the device back to an operational state..
1130          */
1131         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1132                 tg3_bmcr_reset(tp);
1133
1134         i = mdiobus_register(tp->mdio_bus);
1135         if (i) {
1136                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1137                 mdiobus_free(tp->mdio_bus);
1138                 return i;
1139         }
1140
1141         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1142
1143         if (!phydev || !phydev->drv) {
1144                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1145                 mdiobus_unregister(tp->mdio_bus);
1146                 mdiobus_free(tp->mdio_bus);
1147                 return -ENODEV;
1148         }
1149
1150         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1151         case PHY_ID_BCM57780:
1152                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1153                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1154                 break;
1155         case PHY_ID_BCM50610:
1156         case PHY_ID_BCM50610M:
1157                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1158                                      PHY_BRCM_RX_REFCLK_UNUSED |
1159                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1160                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1161                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1162                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1163                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1164                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1165                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1166                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1167                 /* fallthru */
1168         case PHY_ID_RTL8211C:
1169                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1170                 break;
1171         case PHY_ID_RTL8201E:
1172         case PHY_ID_BCMAC131:
1173                 phydev->interface = PHY_INTERFACE_MODE_MII;
1174                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1175                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1176                 break;
1177         }
1178
1179         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1180
1181         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1182                 tg3_mdio_config_5785(tp);
1183
1184         return 0;
1185 }
1186
1187 static void tg3_mdio_fini(struct tg3 *tp)
1188 {
1189         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1190                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1191                 mdiobus_unregister(tp->mdio_bus);
1192                 mdiobus_free(tp->mdio_bus);
1193         }
1194 }
1195
1196 /* tp->lock is held. */
1197 static inline void tg3_generate_fw_event(struct tg3 *tp)
1198 {
1199         u32 val;
1200
1201         val = tr32(GRC_RX_CPU_EVENT);
1202         val |= GRC_RX_CPU_DRIVER_EVENT;
1203         tw32_f(GRC_RX_CPU_EVENT, val);
1204
1205         tp->last_event_jiffies = jiffies;
1206 }
1207
1208 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1209
1210 /* tp->lock is held. */
1211 static void tg3_wait_for_event_ack(struct tg3 *tp)
1212 {
1213         int i;
1214         unsigned int delay_cnt;
1215         long time_remain;
1216
1217         /* If enough time has passed, no wait is necessary. */
1218         time_remain = (long)(tp->last_event_jiffies + 1 +
1219                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1220                       (long)jiffies;
1221         if (time_remain < 0)
1222                 return;
1223
1224         /* Check if we can shorten the wait time. */
1225         delay_cnt = jiffies_to_usecs(time_remain);
1226         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1227                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1228         delay_cnt = (delay_cnt >> 3) + 1;
1229
1230         for (i = 0; i < delay_cnt; i++) {
1231                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1232                         break;
1233                 udelay(8);
1234         }
1235 }
1236
1237 /* tp->lock is held. */
1238 static void tg3_ump_link_report(struct tg3 *tp)
1239 {
1240         u32 reg;
1241         u32 val;
1242
1243         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1244             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1245                 return;
1246
1247         tg3_wait_for_event_ack(tp);
1248
1249         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1250
1251         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1252
1253         val = 0;
1254         if (!tg3_readphy(tp, MII_BMCR, &reg))
1255                 val = reg << 16;
1256         if (!tg3_readphy(tp, MII_BMSR, &reg))
1257                 val |= (reg & 0xffff);
1258         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1259
1260         val = 0;
1261         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1262                 val = reg << 16;
1263         if (!tg3_readphy(tp, MII_LPA, &reg))
1264                 val |= (reg & 0xffff);
1265         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1266
1267         val = 0;
1268         if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1269                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1270                         val = reg << 16;
1271                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1272                         val |= (reg & 0xffff);
1273         }
1274         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1275
1276         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1277                 val = reg << 16;
1278         else
1279                 val = 0;
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1281
1282         tg3_generate_fw_event(tp);
1283 }
1284
1285 static void tg3_link_report(struct tg3 *tp)
1286 {
1287         if (!netif_carrier_ok(tp->dev)) {
1288                 netif_info(tp, link, tp->dev, "Link is down\n");
1289                 tg3_ump_link_report(tp);
1290         } else if (netif_msg_link(tp)) {
1291                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1292                             (tp->link_config.active_speed == SPEED_1000 ?
1293                              1000 :
1294                              (tp->link_config.active_speed == SPEED_100 ?
1295                               100 : 10)),
1296                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1297                              "full" : "half"));
1298
1299                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1300                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1301                             "on" : "off",
1302                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1303                             "on" : "off");
1304                 tg3_ump_link_report(tp);
1305         }
1306 }
1307
1308 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1309 {
1310         u16 miireg;
1311
1312         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1313                 miireg = ADVERTISE_PAUSE_CAP;
1314         else if (flow_ctrl & FLOW_CTRL_TX)
1315                 miireg = ADVERTISE_PAUSE_ASYM;
1316         else if (flow_ctrl & FLOW_CTRL_RX)
1317                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1318         else
1319                 miireg = 0;
1320
1321         return miireg;
1322 }
1323
1324 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1325 {
1326         u16 miireg;
1327
1328         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1329                 miireg = ADVERTISE_1000XPAUSE;
1330         else if (flow_ctrl & FLOW_CTRL_TX)
1331                 miireg = ADVERTISE_1000XPSE_ASYM;
1332         else if (flow_ctrl & FLOW_CTRL_RX)
1333                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1334         else
1335                 miireg = 0;
1336
1337         return miireg;
1338 }
1339
1340 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1341 {
1342         u8 cap = 0;
1343
1344         if (lcladv & ADVERTISE_1000XPAUSE) {
1345                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1346                         if (rmtadv & LPA_1000XPAUSE)
1347                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1348                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1349                                 cap = FLOW_CTRL_RX;
1350                 } else {
1351                         if (rmtadv & LPA_1000XPAUSE)
1352                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1353                 }
1354         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1355                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1356                         cap = FLOW_CTRL_TX;
1357         }
1358
1359         return cap;
1360 }
1361
1362 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1363 {
1364         u8 autoneg;
1365         u8 flowctrl = 0;
1366         u32 old_rx_mode = tp->rx_mode;
1367         u32 old_tx_mode = tp->tx_mode;
1368
1369         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1370                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1371         else
1372                 autoneg = tp->link_config.autoneg;
1373
1374         if (autoneg == AUTONEG_ENABLE &&
1375             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1376                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1377                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1378                 else
1379                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1380         } else
1381                 flowctrl = tp->link_config.flowctrl;
1382
1383         tp->link_config.active_flowctrl = flowctrl;
1384
1385         if (flowctrl & FLOW_CTRL_RX)
1386                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1387         else
1388                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1389
1390         if (old_rx_mode != tp->rx_mode)
1391                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1392
1393         if (flowctrl & FLOW_CTRL_TX)
1394                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1395         else
1396                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1397
1398         if (old_tx_mode != tp->tx_mode)
1399                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1400 }
1401
1402 static void tg3_adjust_link(struct net_device *dev)
1403 {
1404         u8 oldflowctrl, linkmesg = 0;
1405         u32 mac_mode, lcl_adv, rmt_adv;
1406         struct tg3 *tp = netdev_priv(dev);
1407         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1408
1409         spin_lock_bh(&tp->lock);
1410
1411         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1412                                     MAC_MODE_HALF_DUPLEX);
1413
1414         oldflowctrl = tp->link_config.active_flowctrl;
1415
1416         if (phydev->link) {
1417                 lcl_adv = 0;
1418                 rmt_adv = 0;
1419
1420                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1421                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1422                 else if (phydev->speed == SPEED_1000 ||
1423                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1424                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1425                 else
1426                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1427
1428                 if (phydev->duplex == DUPLEX_HALF)
1429                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1430                 else {
1431                         lcl_adv = tg3_advert_flowctrl_1000T(
1432                                   tp->link_config.flowctrl);
1433
1434                         if (phydev->pause)
1435                                 rmt_adv = LPA_PAUSE_CAP;
1436                         if (phydev->asym_pause)
1437                                 rmt_adv |= LPA_PAUSE_ASYM;
1438                 }
1439
1440                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1441         } else
1442                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1443
1444         if (mac_mode != tp->mac_mode) {
1445                 tp->mac_mode = mac_mode;
1446                 tw32_f(MAC_MODE, tp->mac_mode);
1447                 udelay(40);
1448         }
1449
1450         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1451                 if (phydev->speed == SPEED_10)
1452                         tw32(MAC_MI_STAT,
1453                              MAC_MI_STAT_10MBPS_MODE |
1454                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1455                 else
1456                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1457         }
1458
1459         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1460                 tw32(MAC_TX_LENGTHS,
1461                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1462                       (6 << TX_LENGTHS_IPG_SHIFT) |
1463                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1464         else
1465                 tw32(MAC_TX_LENGTHS,
1466                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1467                       (6 << TX_LENGTHS_IPG_SHIFT) |
1468                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1469
1470         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1471             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1472             phydev->speed != tp->link_config.active_speed ||
1473             phydev->duplex != tp->link_config.active_duplex ||
1474             oldflowctrl != tp->link_config.active_flowctrl)
1475                 linkmesg = 1;
1476
1477         tp->link_config.active_speed = phydev->speed;
1478         tp->link_config.active_duplex = phydev->duplex;
1479
1480         spin_unlock_bh(&tp->lock);
1481
1482         if (linkmesg)
1483                 tg3_link_report(tp);
1484 }
1485
1486 static int tg3_phy_init(struct tg3 *tp)
1487 {
1488         struct phy_device *phydev;
1489
1490         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1491                 return 0;
1492
1493         /* Bring the PHY back to a known state. */
1494         tg3_bmcr_reset(tp);
1495
1496         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1497
1498         /* Attach the MAC to the PHY. */
1499         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1500                              phydev->dev_flags, phydev->interface);
1501         if (IS_ERR(phydev)) {
1502                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1503                 return PTR_ERR(phydev);
1504         }
1505
1506         /* Mask with MAC supported features. */
1507         switch (phydev->interface) {
1508         case PHY_INTERFACE_MODE_GMII:
1509         case PHY_INTERFACE_MODE_RGMII:
1510                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1511                         phydev->supported &= (PHY_GBIT_FEATURES |
1512                                               SUPPORTED_Pause |
1513                                               SUPPORTED_Asym_Pause);
1514                         break;
1515                 }
1516                 /* fallthru */
1517         case PHY_INTERFACE_MODE_MII:
1518                 phydev->supported &= (PHY_BASIC_FEATURES |
1519                                       SUPPORTED_Pause |
1520                                       SUPPORTED_Asym_Pause);
1521                 break;
1522         default:
1523                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1524                 return -EINVAL;
1525         }
1526
1527         tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1528
1529         phydev->advertising = phydev->supported;
1530
1531         return 0;
1532 }
1533
1534 static void tg3_phy_start(struct tg3 *tp)
1535 {
1536         struct phy_device *phydev;
1537
1538         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1539                 return;
1540
1541         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1542
1543         if (tp->link_config.phy_is_low_power) {
1544                 tp->link_config.phy_is_low_power = 0;
1545                 phydev->speed = tp->link_config.orig_speed;
1546                 phydev->duplex = tp->link_config.orig_duplex;
1547                 phydev->autoneg = tp->link_config.orig_autoneg;
1548                 phydev->advertising = tp->link_config.orig_advertising;
1549         }
1550
1551         phy_start(phydev);
1552
1553         phy_start_aneg(phydev);
1554 }
1555
1556 static void tg3_phy_stop(struct tg3 *tp)
1557 {
1558         if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1559                 return;
1560
1561         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1562 }
1563
1564 static void tg3_phy_fini(struct tg3 *tp)
1565 {
1566         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1567                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1568                 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1569         }
1570 }
1571
1572 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1573 {
1574         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1575         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1576 }
1577
1578 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1579 {
1580         u32 phytest;
1581
1582         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1583                 u32 phy;
1584
1585                 tg3_writephy(tp, MII_TG3_FET_TEST,
1586                              phytest | MII_TG3_FET_SHADOW_EN);
1587                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1588                         if (enable)
1589                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1590                         else
1591                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1592                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1593                 }
1594                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1595         }
1596 }
1597
1598 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1599 {
1600         u32 reg;
1601
1602         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1603                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1604              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1605                 return;
1606
1607         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1608                 tg3_phy_fet_toggle_apd(tp, enable);
1609                 return;
1610         }
1611
1612         reg = MII_TG3_MISC_SHDW_WREN |
1613               MII_TG3_MISC_SHDW_SCR5_SEL |
1614               MII_TG3_MISC_SHDW_SCR5_LPED |
1615               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1616               MII_TG3_MISC_SHDW_SCR5_SDTL |
1617               MII_TG3_MISC_SHDW_SCR5_C125OE;
1618         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1619                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1620
1621         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1622
1623
1624         reg = MII_TG3_MISC_SHDW_WREN |
1625               MII_TG3_MISC_SHDW_APD_SEL |
1626               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1627         if (enable)
1628                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1629
1630         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1631 }
1632
1633 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1634 {
1635         u32 phy;
1636
1637         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1638             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1639                 return;
1640
1641         if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1642                 u32 ephy;
1643
1644                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1645                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1646
1647                         tg3_writephy(tp, MII_TG3_FET_TEST,
1648                                      ephy | MII_TG3_FET_SHADOW_EN);
1649                         if (!tg3_readphy(tp, reg, &phy)) {
1650                                 if (enable)
1651                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1652                                 else
1653                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1654                                 tg3_writephy(tp, reg, phy);
1655                         }
1656                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1657                 }
1658         } else {
1659                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1660                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1661                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1662                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1663                         if (enable)
1664                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1665                         else
1666                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1667                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1668                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1669                 }
1670         }
1671 }
1672
1673 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1674 {
1675         u32 val;
1676
1677         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1678                 return;
1679
1680         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1681             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1682                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1683                              (val | (1 << 15) | (1 << 4)));
1684 }
1685
1686 static void tg3_phy_apply_otp(struct tg3 *tp)
1687 {
1688         u32 otp, phy;
1689
1690         if (!tp->phy_otp)
1691                 return;
1692
1693         otp = tp->phy_otp;
1694
1695         /* Enable SM_DSP clock and tx 6dB coding. */
1696         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1698               MII_TG3_AUXCTL_ACTL_TX_6DB;
1699         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1700
1701         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1702         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1703         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1704
1705         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1706               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1707         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1708
1709         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1710         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1711         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1712
1713         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1714         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1715
1716         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1717         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1718
1719         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1720               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1721         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1722
1723         /* Turn off SM_DSP clock. */
1724         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1725               MII_TG3_AUXCTL_ACTL_TX_6DB;
1726         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1727 }
1728
1729 static int tg3_wait_macro_done(struct tg3 *tp)
1730 {
1731         int limit = 100;
1732
1733         while (limit--) {
1734                 u32 tmp32;
1735
1736                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1737                         if ((tmp32 & 0x1000) == 0)
1738                                 break;
1739                 }
1740         }
1741         if (limit < 0)
1742                 return -EBUSY;
1743
1744         return 0;
1745 }
1746
1747 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1748 {
1749         static const u32 test_pat[4][6] = {
1750         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1751         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1752         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1753         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1754         };
1755         int chan;
1756
1757         for (chan = 0; chan < 4; chan++) {
1758                 int i;
1759
1760                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1761                              (chan * 0x2000) | 0x0200);
1762                 tg3_writephy(tp, 0x16, 0x0002);
1763
1764                 for (i = 0; i < 6; i++)
1765                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1766                                      test_pat[chan][i]);
1767
1768                 tg3_writephy(tp, 0x16, 0x0202);
1769                 if (tg3_wait_macro_done(tp)) {
1770                         *resetp = 1;
1771                         return -EBUSY;
1772                 }
1773
1774                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1775                              (chan * 0x2000) | 0x0200);
1776                 tg3_writephy(tp, 0x16, 0x0082);
1777                 if (tg3_wait_macro_done(tp)) {
1778                         *resetp = 1;
1779                         return -EBUSY;
1780                 }
1781
1782                 tg3_writephy(tp, 0x16, 0x0802);
1783                 if (tg3_wait_macro_done(tp)) {
1784                         *resetp = 1;
1785                         return -EBUSY;
1786                 }
1787
1788                 for (i = 0; i < 6; i += 2) {
1789                         u32 low, high;
1790
1791                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1792                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1793                             tg3_wait_macro_done(tp)) {
1794                                 *resetp = 1;
1795                                 return -EBUSY;
1796                         }
1797                         low &= 0x7fff;
1798                         high &= 0x000f;
1799                         if (low != test_pat[chan][i] ||
1800                             high != test_pat[chan][i+1]) {
1801                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1802                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1803                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1804
1805                                 return -EBUSY;
1806                         }
1807                 }
1808         }
1809
1810         return 0;
1811 }
1812
1813 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1814 {
1815         int chan;
1816
1817         for (chan = 0; chan < 4; chan++) {
1818                 int i;
1819
1820                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1821                              (chan * 0x2000) | 0x0200);
1822                 tg3_writephy(tp, 0x16, 0x0002);
1823                 for (i = 0; i < 6; i++)
1824                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1825                 tg3_writephy(tp, 0x16, 0x0202);
1826                 if (tg3_wait_macro_done(tp))
1827                         return -EBUSY;
1828         }
1829
1830         return 0;
1831 }
1832
1833 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1834 {
1835         u32 reg32, phy9_orig;
1836         int retries, do_phy_reset, err;
1837
1838         retries = 10;
1839         do_phy_reset = 1;
1840         do {
1841                 if (do_phy_reset) {
1842                         err = tg3_bmcr_reset(tp);
1843                         if (err)
1844                                 return err;
1845                         do_phy_reset = 0;
1846                 }
1847
1848                 /* Disable transmitter and interrupt.  */
1849                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1850                         continue;
1851
1852                 reg32 |= 0x3000;
1853                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1854
1855                 /* Set full-duplex, 1000 mbps.  */
1856                 tg3_writephy(tp, MII_BMCR,
1857                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1858
1859                 /* Set to master mode.  */
1860                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1861                         continue;
1862
1863                 tg3_writephy(tp, MII_TG3_CTRL,
1864                              (MII_TG3_CTRL_AS_MASTER |
1865                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1866
1867                 /* Enable SM_DSP_CLOCK and 6dB.  */
1868                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1869
1870                 /* Block the PHY control access.  */
1871                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1872                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1873
1874                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1875                 if (!err)
1876                         break;
1877         } while (--retries);
1878
1879         err = tg3_phy_reset_chanpat(tp);
1880         if (err)
1881                 return err;
1882
1883         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1884         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1885
1886         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1887         tg3_writephy(tp, 0x16, 0x0000);
1888
1889         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1890             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1891                 /* Set Extended packet length bit for jumbo frames */
1892                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1893         } else {
1894                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1895         }
1896
1897         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1898
1899         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1900                 reg32 &= ~0x3000;
1901                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1902         } else if (!err)
1903                 err = -EBUSY;
1904
1905         return err;
1906 }
1907
1908 /* This will reset the tigon3 PHY if there is no valid
1909  * link unless the FORCE argument is non-zero.
1910  */
1911 static int tg3_phy_reset(struct tg3 *tp)
1912 {
1913         u32 cpmuctrl;
1914         u32 phy_status;
1915         int err;
1916
1917         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1918                 u32 val;
1919
1920                 val = tr32(GRC_MISC_CFG);
1921                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1922                 udelay(40);
1923         }
1924         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
1925         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1926         if (err != 0)
1927                 return -EBUSY;
1928
1929         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1930                 netif_carrier_off(tp->dev);
1931                 tg3_link_report(tp);
1932         }
1933
1934         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1935             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1937                 err = tg3_phy_reset_5703_4_5(tp);
1938                 if (err)
1939                         return err;
1940                 goto out;
1941         }
1942
1943         cpmuctrl = 0;
1944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1945             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1946                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1947                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1948                         tw32(TG3_CPMU_CTRL,
1949                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1950         }
1951
1952         err = tg3_bmcr_reset(tp);
1953         if (err)
1954                 return err;
1955
1956         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1957                 u32 phy;
1958
1959                 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1960                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1961
1962                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1963         }
1964
1965         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1966             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1967                 u32 val;
1968
1969                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1970                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1971                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1972                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1973                         udelay(40);
1974                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1975                 }
1976         }
1977
1978         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1979             (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1980                 return 0;
1981
1982         tg3_phy_apply_otp(tp);
1983
1984         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1985                 tg3_phy_toggle_apd(tp, true);
1986         else
1987                 tg3_phy_toggle_apd(tp, false);
1988
1989 out:
1990         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1991                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1992                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1993                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1994                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1995                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1996                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1997         }
1998         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1999                 tg3_writephy(tp, 0x1c, 0x8d68);
2000                 tg3_writephy(tp, 0x1c, 0x8d68);
2001         }
2002         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
2003                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
2006                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2007                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
2008                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
2009                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
2010                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2011         } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
2012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
2015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2016                         tg3_writephy(tp, MII_TG3_TEST1,
2017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2018                 } else
2019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2021         }
2022         /* Set Extended packet length bit (bit 14) on all chips that */
2023         /* support jumbo frames */
2024         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2025                 /* Cannot do read-modify-write on 5401 */
2026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2027         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2028                 u32 phy_reg;
2029
2030                 /* Set bit 14 with read-modify-write to preserve other bits */
2031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
2033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
2034         }
2035
2036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2037          * jumbo frames transmission.
2038          */
2039         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2040                 u32 phy_reg;
2041
2042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2043                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2044                                      phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2045         }
2046
2047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2048                 /* adjust output voltage */
2049                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2050         }
2051
2052         tg3_phy_toggle_automdix(tp, 1);
2053         tg3_phy_set_wirespeed(tp);
2054         return 0;
2055 }
2056
2057 static void tg3_frob_aux_power(struct tg3 *tp)
2058 {
2059         struct tg3 *tp_peer = tp;
2060
2061         /* The GPIOs do something completely different on 57765. */
2062         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2063             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2064                 return;
2065
2066         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2067             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2069                 struct net_device *dev_peer;
2070
2071                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2072                 /* remove_one() may have been run on the peer. */
2073                 if (!dev_peer)
2074                         tp_peer = tp;
2075                 else
2076                         tp_peer = netdev_priv(dev_peer);
2077         }
2078
2079         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2080             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2081             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2082             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2083                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2084                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2085                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2086                                     (GRC_LCLCTRL_GPIO_OE0 |
2087                                      GRC_LCLCTRL_GPIO_OE1 |
2088                                      GRC_LCLCTRL_GPIO_OE2 |
2089                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2090                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2091                                     100);
2092                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2093                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2094                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2095                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2096                                              GRC_LCLCTRL_GPIO_OE1 |
2097                                              GRC_LCLCTRL_GPIO_OE2 |
2098                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2099                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2100                                              tp->grc_local_ctrl;
2101                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2102
2103                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2104                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2105
2106                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2107                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2108                 } else {
2109                         u32 no_gpio2;
2110                         u32 grc_local_ctrl = 0;
2111
2112                         if (tp_peer != tp &&
2113                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2114                                 return;
2115
2116                         /* Workaround to prevent overdrawing Amps. */
2117                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2118                             ASIC_REV_5714) {
2119                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2120                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2121                                             grc_local_ctrl, 100);
2122                         }
2123
2124                         /* On 5753 and variants, GPIO2 cannot be used. */
2125                         no_gpio2 = tp->nic_sram_data_cfg &
2126                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2127
2128                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2129                                          GRC_LCLCTRL_GPIO_OE1 |
2130                                          GRC_LCLCTRL_GPIO_OE2 |
2131                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2132                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2133                         if (no_gpio2) {
2134                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2135                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2136                         }
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                                     grc_local_ctrl, 100);
2139
2140                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2141
2142                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2143                                                     grc_local_ctrl, 100);
2144
2145                         if (!no_gpio2) {
2146                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2147                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2148                                             grc_local_ctrl, 100);
2149                         }
2150                 }
2151         } else {
2152                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2153                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2154                         if (tp_peer != tp &&
2155                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2156                                 return;
2157
2158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2159                                     (GRC_LCLCTRL_GPIO_OE1 |
2160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2161
2162                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2163                                     GRC_LCLCTRL_GPIO_OE1, 100);
2164
2165                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2166                                     (GRC_LCLCTRL_GPIO_OE1 |
2167                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2168                 }
2169         }
2170 }
2171
2172 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2173 {
2174         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2175                 return 1;
2176         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2177                 if (speed != SPEED_10)
2178                         return 1;
2179         } else if (speed == SPEED_10)
2180                 return 1;
2181
2182         return 0;
2183 }
2184
2185 static int tg3_setup_phy(struct tg3 *, int);
2186
2187 #define RESET_KIND_SHUTDOWN     0
2188 #define RESET_KIND_INIT         1
2189 #define RESET_KIND_SUSPEND      2
2190
2191 static void tg3_write_sig_post_reset(struct tg3 *, int);
2192 static int tg3_halt_cpu(struct tg3 *, u32);
2193
2194 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2195 {
2196         u32 val;
2197
2198         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2199                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2200                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2201                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2202
2203                         sg_dig_ctrl |=
2204                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2205                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2206                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2207                 }
2208                 return;
2209         }
2210
2211         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2212                 tg3_bmcr_reset(tp);
2213                 val = tr32(GRC_MISC_CFG);
2214                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2215                 udelay(40);
2216                 return;
2217         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2218                 u32 phytest;
2219                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2220                         u32 phy;
2221
2222                         tg3_writephy(tp, MII_ADVERTISE, 0);
2223                         tg3_writephy(tp, MII_BMCR,
2224                                      BMCR_ANENABLE | BMCR_ANRESTART);
2225
2226                         tg3_writephy(tp, MII_TG3_FET_TEST,
2227                                      phytest | MII_TG3_FET_SHADOW_EN);
2228                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2229                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2230                                 tg3_writephy(tp,
2231                                              MII_TG3_FET_SHDW_AUXMODE4,
2232                                              phy);
2233                         }
2234                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2235                 }
2236                 return;
2237         } else if (do_low_power) {
2238                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2239                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2240
2241                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2242                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2243                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2244                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2245                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2246         }
2247
2248         /* The PHY should not be powered down on some chips because
2249          * of bugs.
2250          */
2251         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2252             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2253             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2254              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2255                 return;
2256
2257         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2258             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2259                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2260                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2261                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2262                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2263         }
2264
2265         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2266 }
2267
2268 /* tp->lock is held. */
2269 static int tg3_nvram_lock(struct tg3 *tp)
2270 {
2271         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2272                 int i;
2273
2274                 if (tp->nvram_lock_cnt == 0) {
2275                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2276                         for (i = 0; i < 8000; i++) {
2277                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2278                                         break;
2279                                 udelay(20);
2280                         }
2281                         if (i == 8000) {
2282                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2283                                 return -ENODEV;
2284                         }
2285                 }
2286                 tp->nvram_lock_cnt++;
2287         }
2288         return 0;
2289 }
2290
2291 /* tp->lock is held. */
2292 static void tg3_nvram_unlock(struct tg3 *tp)
2293 {
2294         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2295                 if (tp->nvram_lock_cnt > 0)
2296                         tp->nvram_lock_cnt--;
2297                 if (tp->nvram_lock_cnt == 0)
2298                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2299         }
2300 }
2301
2302 /* tp->lock is held. */
2303 static void tg3_enable_nvram_access(struct tg3 *tp)
2304 {
2305         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2306             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2307                 u32 nvaccess = tr32(NVRAM_ACCESS);
2308
2309                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2310         }
2311 }
2312
2313 /* tp->lock is held. */
2314 static void tg3_disable_nvram_access(struct tg3 *tp)
2315 {
2316         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2317             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2318                 u32 nvaccess = tr32(NVRAM_ACCESS);
2319
2320                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2321         }
2322 }
2323
2324 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2325                                         u32 offset, u32 *val)
2326 {
2327         u32 tmp;
2328         int i;
2329
2330         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2331                 return -EINVAL;
2332
2333         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2334                                         EEPROM_ADDR_DEVID_MASK |
2335                                         EEPROM_ADDR_READ);
2336         tw32(GRC_EEPROM_ADDR,
2337              tmp |
2338              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2339              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2340               EEPROM_ADDR_ADDR_MASK) |
2341              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2342
2343         for (i = 0; i < 1000; i++) {
2344                 tmp = tr32(GRC_EEPROM_ADDR);
2345
2346                 if (tmp & EEPROM_ADDR_COMPLETE)
2347                         break;
2348                 msleep(1);
2349         }
2350         if (!(tmp & EEPROM_ADDR_COMPLETE))
2351                 return -EBUSY;
2352
2353         tmp = tr32(GRC_EEPROM_DATA);
2354
2355         /*
2356          * The data will always be opposite the native endian
2357          * format.  Perform a blind byteswap to compensate.
2358          */
2359         *val = swab32(tmp);
2360
2361         return 0;
2362 }
2363
2364 #define NVRAM_CMD_TIMEOUT 10000
2365
2366 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2367 {
2368         int i;
2369
2370         tw32(NVRAM_CMD, nvram_cmd);
2371         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2372                 udelay(10);
2373                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2374                         udelay(10);
2375                         break;
2376                 }
2377         }
2378
2379         if (i == NVRAM_CMD_TIMEOUT)
2380                 return -EBUSY;
2381
2382         return 0;
2383 }
2384
2385 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2386 {
2387         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2388             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2389             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2390            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2391             (tp->nvram_jedecnum == JEDEC_ATMEL))
2392
2393                 addr = ((addr / tp->nvram_pagesize) <<
2394                         ATMEL_AT45DB0X1B_PAGE_POS) +
2395                        (addr % tp->nvram_pagesize);
2396
2397         return addr;
2398 }
2399
2400 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2401 {
2402         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2403             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2404             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2405            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2406             (tp->nvram_jedecnum == JEDEC_ATMEL))
2407
2408                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2409                         tp->nvram_pagesize) +
2410                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2411
2412         return addr;
2413 }
2414
2415 /* NOTE: Data read in from NVRAM is byteswapped according to
2416  * the byteswapping settings for all other register accesses.
2417  * tg3 devices are BE devices, so on a BE machine, the data
2418  * returned will be exactly as it is seen in NVRAM.  On a LE
2419  * machine, the 32-bit value will be byteswapped.
2420  */
2421 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2422 {
2423         int ret;
2424
2425         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2426                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2427
2428         offset = tg3_nvram_phys_addr(tp, offset);
2429
2430         if (offset > NVRAM_ADDR_MSK)
2431                 return -EINVAL;
2432
2433         ret = tg3_nvram_lock(tp);
2434         if (ret)
2435                 return ret;
2436
2437         tg3_enable_nvram_access(tp);
2438
2439         tw32(NVRAM_ADDR, offset);
2440         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2441                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2442
2443         if (ret == 0)
2444                 *val = tr32(NVRAM_RDDATA);
2445
2446         tg3_disable_nvram_access(tp);
2447
2448         tg3_nvram_unlock(tp);
2449
2450         return ret;
2451 }
2452
2453 /* Ensures NVRAM data is in bytestream format. */
2454 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2455 {
2456         u32 v;
2457         int res = tg3_nvram_read(tp, offset, &v);
2458         if (!res)
2459                 *val = cpu_to_be32(v);
2460         return res;
2461 }
2462
2463 /* tp->lock is held. */
2464 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2465 {
2466         u32 addr_high, addr_low;
2467         int i;
2468
2469         addr_high = ((tp->dev->dev_addr[0] << 8) |
2470                      tp->dev->dev_addr[1]);
2471         addr_low = ((tp->dev->dev_addr[2] << 24) |
2472                     (tp->dev->dev_addr[3] << 16) |
2473                     (tp->dev->dev_addr[4] <<  8) |
2474                     (tp->dev->dev_addr[5] <<  0));
2475         for (i = 0; i < 4; i++) {
2476                 if (i == 1 && skip_mac_1)
2477                         continue;
2478                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2479                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2480         }
2481
2482         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2483             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2484                 for (i = 0; i < 12; i++) {
2485                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2486                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2487                 }
2488         }
2489
2490         addr_high = (tp->dev->dev_addr[0] +
2491                      tp->dev->dev_addr[1] +
2492                      tp->dev->dev_addr[2] +
2493                      tp->dev->dev_addr[3] +
2494                      tp->dev->dev_addr[4] +
2495                      tp->dev->dev_addr[5]) &
2496                 TX_BACKOFF_SEED_MASK;
2497         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2498 }
2499
2500 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2501 {
2502         u32 misc_host_ctrl;
2503         bool device_should_wake, do_low_power;
2504
2505         /* Make sure register accesses (indirect or otherwise)
2506          * will function correctly.
2507          */
2508         pci_write_config_dword(tp->pdev,
2509                                TG3PCI_MISC_HOST_CTRL,
2510                                tp->misc_host_ctrl);
2511
2512         switch (state) {
2513         case PCI_D0:
2514                 pci_enable_wake(tp->pdev, state, false);
2515                 pci_set_power_state(tp->pdev, PCI_D0);
2516
2517                 /* Switch out of Vaux if it is a NIC */
2518                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2519                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2520
2521                 return 0;
2522
2523         case PCI_D1:
2524         case PCI_D2:
2525         case PCI_D3hot:
2526                 break;
2527
2528         default:
2529                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2530                            state);
2531                 return -EINVAL;
2532         }
2533
2534         /* Restore the CLKREQ setting. */
2535         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2536                 u16 lnkctl;
2537
2538                 pci_read_config_word(tp->pdev,
2539                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2540                                      &lnkctl);
2541                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2542                 pci_write_config_word(tp->pdev,
2543                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2544                                       lnkctl);
2545         }
2546
2547         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2548         tw32(TG3PCI_MISC_HOST_CTRL,
2549              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2550
2551         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2552                              device_may_wakeup(&tp->pdev->dev) &&
2553                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2554
2555         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2556                 do_low_power = false;
2557                 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2558                     !tp->link_config.phy_is_low_power) {
2559                         struct phy_device *phydev;
2560                         u32 phyid, advertising;
2561
2562                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2563
2564                         tp->link_config.phy_is_low_power = 1;
2565
2566                         tp->link_config.orig_speed = phydev->speed;
2567                         tp->link_config.orig_duplex = phydev->duplex;
2568                         tp->link_config.orig_autoneg = phydev->autoneg;
2569                         tp->link_config.orig_advertising = phydev->advertising;
2570
2571                         advertising = ADVERTISED_TP |
2572                                       ADVERTISED_Pause |
2573                                       ADVERTISED_Autoneg |
2574                                       ADVERTISED_10baseT_Half;
2575
2576                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2577                             device_should_wake) {
2578                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2579                                         advertising |=
2580                                                 ADVERTISED_100baseT_Half |
2581                                                 ADVERTISED_100baseT_Full |
2582                                                 ADVERTISED_10baseT_Full;
2583                                 else
2584                                         advertising |= ADVERTISED_10baseT_Full;
2585                         }
2586
2587                         phydev->advertising = advertising;
2588
2589                         phy_start_aneg(phydev);
2590
2591                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2592                         if (phyid != PHY_ID_BCMAC131) {
2593                                 phyid &= PHY_BCM_OUI_MASK;
2594                                 if (phyid == PHY_BCM_OUI_1 ||
2595                                     phyid == PHY_BCM_OUI_2 ||
2596                                     phyid == PHY_BCM_OUI_3)
2597                                         do_low_power = true;
2598                         }
2599                 }
2600         } else {
2601                 do_low_power = true;
2602
2603                 if (tp->link_config.phy_is_low_power == 0) {
2604                         tp->link_config.phy_is_low_power = 1;
2605                         tp->link_config.orig_speed = tp->link_config.speed;
2606                         tp->link_config.orig_duplex = tp->link_config.duplex;
2607                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2608                 }
2609
2610                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2611                         tp->link_config.speed = SPEED_10;
2612                         tp->link_config.duplex = DUPLEX_HALF;
2613                         tp->link_config.autoneg = AUTONEG_ENABLE;
2614                         tg3_setup_phy(tp, 0);
2615                 }
2616         }
2617
2618         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2619                 u32 val;
2620
2621                 val = tr32(GRC_VCPU_EXT_CTRL);
2622                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2623         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2624                 int i;
2625                 u32 val;
2626
2627                 for (i = 0; i < 200; i++) {
2628                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2629                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2630                                 break;
2631                         msleep(1);
2632                 }
2633         }
2634         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2635                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2636                                                      WOL_DRV_STATE_SHUTDOWN |
2637                                                      WOL_DRV_WOL |
2638                                                      WOL_SET_MAGIC_PKT);
2639
2640         if (device_should_wake) {
2641                 u32 mac_mode;
2642
2643                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2644                         if (do_low_power) {
2645                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2646                                 udelay(40);
2647                         }
2648
2649                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2650                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2651                         else
2652                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2653
2654                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2655                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2656                             ASIC_REV_5700) {
2657                                 u32 speed = (tp->tg3_flags &
2658                                              TG3_FLAG_WOL_SPEED_100MB) ?
2659                                              SPEED_100 : SPEED_10;
2660                                 if (tg3_5700_link_polarity(tp, speed))
2661                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2662                                 else
2663                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2664                         }
2665                 } else {
2666                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2667                 }
2668
2669                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2670                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2671
2672                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2673                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2674                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2675                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2676                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2677                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2678
2679                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2680                         mac_mode |= tp->mac_mode &
2681                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2682                         if (mac_mode & MAC_MODE_APE_TX_EN)
2683                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2684                 }
2685
2686                 tw32_f(MAC_MODE, mac_mode);
2687                 udelay(100);
2688
2689                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2690                 udelay(10);
2691         }
2692
2693         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2694             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2695              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2696                 u32 base_val;
2697
2698                 base_val = tp->pci_clock_ctrl;
2699                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2700                              CLOCK_CTRL_TXCLK_DISABLE);
2701
2702                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2703                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2704         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2705                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2706                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2707                 /* do nothing */
2708         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2709                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2710                 u32 newbits1, newbits2;
2711
2712                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2713                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2714                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2715                                     CLOCK_CTRL_TXCLK_DISABLE |
2716                                     CLOCK_CTRL_ALTCLK);
2717                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2718                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2719                         newbits1 = CLOCK_CTRL_625_CORE;
2720                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2721                 } else {
2722                         newbits1 = CLOCK_CTRL_ALTCLK;
2723                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2724                 }
2725
2726                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2727                             40);
2728
2729                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2730                             40);
2731
2732                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2733                         u32 newbits3;
2734
2735                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2736                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2737                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2738                                             CLOCK_CTRL_TXCLK_DISABLE |
2739                                             CLOCK_CTRL_44MHZ_CORE);
2740                         } else {
2741                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2742                         }
2743
2744                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2745                                     tp->pci_clock_ctrl | newbits3, 40);
2746                 }
2747         }
2748
2749         if (!(device_should_wake) &&
2750             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2751                 tg3_power_down_phy(tp, do_low_power);
2752
2753         tg3_frob_aux_power(tp);
2754
2755         /* Workaround for unstable PLL clock */
2756         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2757             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2758                 u32 val = tr32(0x7d00);
2759
2760                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2761                 tw32(0x7d00, val);
2762                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2763                         int err;
2764
2765                         err = tg3_nvram_lock(tp);
2766                         tg3_halt_cpu(tp, RX_CPU_BASE);
2767                         if (!err)
2768                                 tg3_nvram_unlock(tp);
2769                 }
2770         }
2771
2772         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2773
2774         if (device_should_wake)
2775                 pci_enable_wake(tp->pdev, state, true);
2776
2777         /* Finally, set the new power state. */
2778         pci_set_power_state(tp->pdev, state);
2779
2780         return 0;
2781 }
2782
2783 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2784 {
2785         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2786         case MII_TG3_AUX_STAT_10HALF:
2787                 *speed = SPEED_10;
2788                 *duplex = DUPLEX_HALF;
2789                 break;
2790
2791         case MII_TG3_AUX_STAT_10FULL:
2792                 *speed = SPEED_10;
2793                 *duplex = DUPLEX_FULL;
2794                 break;
2795
2796         case MII_TG3_AUX_STAT_100HALF:
2797                 *speed = SPEED_100;
2798                 *duplex = DUPLEX_HALF;
2799                 break;
2800
2801         case MII_TG3_AUX_STAT_100FULL:
2802                 *speed = SPEED_100;
2803                 *duplex = DUPLEX_FULL;
2804                 break;
2805
2806         case MII_TG3_AUX_STAT_1000HALF:
2807                 *speed = SPEED_1000;
2808                 *duplex = DUPLEX_HALF;
2809                 break;
2810
2811         case MII_TG3_AUX_STAT_1000FULL:
2812                 *speed = SPEED_1000;
2813                 *duplex = DUPLEX_FULL;
2814                 break;
2815
2816         default:
2817                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2818                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2819                                  SPEED_10;
2820                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2821                                   DUPLEX_HALF;
2822                         break;
2823                 }
2824                 *speed = SPEED_INVALID;
2825                 *duplex = DUPLEX_INVALID;
2826                 break;
2827         }
2828 }
2829
2830 static void tg3_phy_copper_begin(struct tg3 *tp)
2831 {
2832         u32 new_adv;
2833         int i;
2834
2835         if (tp->link_config.phy_is_low_power) {
2836                 /* Entering low power mode.  Disable gigabit and
2837                  * 100baseT advertisements.
2838                  */
2839                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2840
2841                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2842                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2843                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2844                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2845
2846                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2847         } else if (tp->link_config.speed == SPEED_INVALID) {
2848                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2849                         tp->link_config.advertising &=
2850                                 ~(ADVERTISED_1000baseT_Half |
2851                                   ADVERTISED_1000baseT_Full);
2852
2853                 new_adv = ADVERTISE_CSMA;
2854                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2855                         new_adv |= ADVERTISE_10HALF;
2856                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2857                         new_adv |= ADVERTISE_10FULL;
2858                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2859                         new_adv |= ADVERTISE_100HALF;
2860                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2861                         new_adv |= ADVERTISE_100FULL;
2862
2863                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2864
2865                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2866
2867                 if (tp->link_config.advertising &
2868                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2869                         new_adv = 0;
2870                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2871                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2872                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2873                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2874                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2875                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2876                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2877                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2878                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2879                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2880                 } else {
2881                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2882                 }
2883         } else {
2884                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2885                 new_adv |= ADVERTISE_CSMA;
2886
2887                 /* Asking for a specific link mode. */
2888                 if (tp->link_config.speed == SPEED_1000) {
2889                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2890
2891                         if (tp->link_config.duplex == DUPLEX_FULL)
2892                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2893                         else
2894                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2895                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2896                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2897                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2898                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2899                 } else {
2900                         if (tp->link_config.speed == SPEED_100) {
2901                                 if (tp->link_config.duplex == DUPLEX_FULL)
2902                                         new_adv |= ADVERTISE_100FULL;
2903                                 else
2904                                         new_adv |= ADVERTISE_100HALF;
2905                         } else {
2906                                 if (tp->link_config.duplex == DUPLEX_FULL)
2907                                         new_adv |= ADVERTISE_10FULL;
2908                                 else
2909                                         new_adv |= ADVERTISE_10HALF;
2910                         }
2911                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2912
2913                         new_adv = 0;
2914                 }
2915
2916                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2917         }
2918
2919         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2920             tp->link_config.speed != SPEED_INVALID) {
2921                 u32 bmcr, orig_bmcr;
2922
2923                 tp->link_config.active_speed = tp->link_config.speed;
2924                 tp->link_config.active_duplex = tp->link_config.duplex;
2925
2926                 bmcr = 0;
2927                 switch (tp->link_config.speed) {
2928                 default:
2929                 case SPEED_10:
2930                         break;
2931
2932                 case SPEED_100:
2933                         bmcr |= BMCR_SPEED100;
2934                         break;
2935
2936                 case SPEED_1000:
2937                         bmcr |= TG3_BMCR_SPEED1000;
2938                         break;
2939                 }
2940
2941                 if (tp->link_config.duplex == DUPLEX_FULL)
2942                         bmcr |= BMCR_FULLDPLX;
2943
2944                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2945                     (bmcr != orig_bmcr)) {
2946                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2947                         for (i = 0; i < 1500; i++) {
2948                                 u32 tmp;
2949
2950                                 udelay(10);
2951                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2952                                     tg3_readphy(tp, MII_BMSR, &tmp))
2953                                         continue;
2954                                 if (!(tmp & BMSR_LSTATUS)) {
2955                                         udelay(40);
2956                                         break;
2957                                 }
2958                         }
2959                         tg3_writephy(tp, MII_BMCR, bmcr);
2960                         udelay(40);
2961                 }
2962         } else {
2963                 tg3_writephy(tp, MII_BMCR,
2964                              BMCR_ANENABLE | BMCR_ANRESTART);
2965         }
2966 }
2967
2968 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2969 {
2970         int err;
2971
2972         /* Turn off tap power management. */
2973         /* Set Extended packet length bit */
2974         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2975
2976         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2977         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2978
2979         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2980         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2981
2982         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2983         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2984
2985         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2986         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2987
2988         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2989         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2990
2991         udelay(40);
2992
2993         return err;
2994 }
2995
2996 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2997 {
2998         u32 adv_reg, all_mask = 0;
2999
3000         if (mask & ADVERTISED_10baseT_Half)
3001                 all_mask |= ADVERTISE_10HALF;
3002         if (mask & ADVERTISED_10baseT_Full)
3003                 all_mask |= ADVERTISE_10FULL;
3004         if (mask & ADVERTISED_100baseT_Half)
3005                 all_mask |= ADVERTISE_100HALF;
3006         if (mask & ADVERTISED_100baseT_Full)
3007                 all_mask |= ADVERTISE_100FULL;
3008
3009         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3010                 return 0;
3011
3012         if ((adv_reg & all_mask) != all_mask)
3013                 return 0;
3014         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
3015                 u32 tg3_ctrl;
3016
3017                 all_mask = 0;
3018                 if (mask & ADVERTISED_1000baseT_Half)
3019                         all_mask |= ADVERTISE_1000HALF;
3020                 if (mask & ADVERTISED_1000baseT_Full)
3021                         all_mask |= ADVERTISE_1000FULL;
3022
3023                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3024                         return 0;
3025
3026                 if ((tg3_ctrl & all_mask) != all_mask)
3027                         return 0;
3028         }
3029         return 1;
3030 }
3031
3032 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3033 {
3034         u32 curadv, reqadv;
3035
3036         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3037                 return 1;
3038
3039         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3040         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3041
3042         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3043                 if (curadv != reqadv)
3044                         return 0;
3045
3046                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3047                         tg3_readphy(tp, MII_LPA, rmtadv);
3048         } else {
3049                 /* Reprogram the advertisement register, even if it
3050                  * does not affect the current link.  If the link
3051                  * gets renegotiated in the future, we can save an
3052                  * additional renegotiation cycle by advertising
3053                  * it correctly in the first place.
3054                  */
3055                 if (curadv != reqadv) {
3056                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3057                                      ADVERTISE_PAUSE_ASYM);
3058                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3059                 }
3060         }
3061
3062         return 1;
3063 }
3064
3065 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3066 {
3067         int current_link_up;
3068         u32 bmsr, dummy;
3069         u32 lcl_adv, rmt_adv;
3070         u16 current_speed;
3071         u8 current_duplex;
3072         int i, err;
3073
3074         tw32(MAC_EVENT, 0);
3075
3076         tw32_f(MAC_STATUS,
3077              (MAC_STATUS_SYNC_CHANGED |
3078               MAC_STATUS_CFG_CHANGED |
3079               MAC_STATUS_MI_COMPLETION |
3080               MAC_STATUS_LNKSTATE_CHANGED));
3081         udelay(40);
3082
3083         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3084                 tw32_f(MAC_MI_MODE,
3085                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3086                 udelay(80);
3087         }
3088
3089         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3090
3091         /* Some third-party PHYs need to be reset on link going
3092          * down.
3093          */
3094         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3095              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3096              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3097             netif_carrier_ok(tp->dev)) {
3098                 tg3_readphy(tp, MII_BMSR, &bmsr);
3099                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3100                     !(bmsr & BMSR_LSTATUS))
3101                         force_reset = 1;
3102         }
3103         if (force_reset)
3104                 tg3_phy_reset(tp);
3105
3106         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3107                 tg3_readphy(tp, MII_BMSR, &bmsr);
3108                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3109                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3110                         bmsr = 0;
3111
3112                 if (!(bmsr & BMSR_LSTATUS)) {
3113                         err = tg3_init_5401phy_dsp(tp);
3114                         if (err)
3115                                 return err;
3116
3117                         tg3_readphy(tp, MII_BMSR, &bmsr);
3118                         for (i = 0; i < 1000; i++) {
3119                                 udelay(10);
3120                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3121                                     (bmsr & BMSR_LSTATUS)) {
3122                                         udelay(40);
3123                                         break;
3124                                 }
3125                         }
3126
3127                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3128                             TG3_PHY_REV_BCM5401_B0 &&
3129                             !(bmsr & BMSR_LSTATUS) &&
3130                             tp->link_config.active_speed == SPEED_1000) {
3131                                 err = tg3_phy_reset(tp);
3132                                 if (!err)
3133                                         err = tg3_init_5401phy_dsp(tp);
3134                                 if (err)
3135                                         return err;
3136                         }
3137                 }
3138         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3139                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3140                 /* 5701 {A0,B0} CRC bug workaround */
3141                 tg3_writephy(tp, 0x15, 0x0a75);
3142                 tg3_writephy(tp, 0x1c, 0x8c68);
3143                 tg3_writephy(tp, 0x1c, 0x8d68);
3144                 tg3_writephy(tp, 0x1c, 0x8c68);
3145         }
3146
3147         /* Clear pending interrupts... */
3148         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3149         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3150
3151         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3152                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3153         else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3154                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3155
3156         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3157             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3158                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3159                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3160                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3161                 else
3162                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3163         }
3164
3165         current_link_up = 0;
3166         current_speed = SPEED_INVALID;
3167         current_duplex = DUPLEX_INVALID;
3168
3169         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3170                 u32 val;
3171
3172                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3173                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3174                 if (!(val & (1 << 10))) {
3175                         val |= (1 << 10);
3176                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3177                         goto relink;
3178                 }
3179         }
3180
3181         bmsr = 0;
3182         for (i = 0; i < 100; i++) {
3183                 tg3_readphy(tp, MII_BMSR, &bmsr);
3184                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3185                     (bmsr & BMSR_LSTATUS))
3186                         break;
3187                 udelay(40);
3188         }
3189
3190         if (bmsr & BMSR_LSTATUS) {
3191                 u32 aux_stat, bmcr;
3192
3193                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3194                 for (i = 0; i < 2000; i++) {
3195                         udelay(10);
3196                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3197                             aux_stat)
3198                                 break;
3199                 }
3200
3201                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3202                                              &current_speed,
3203                                              &current_duplex);
3204
3205                 bmcr = 0;
3206                 for (i = 0; i < 200; i++) {
3207                         tg3_readphy(tp, MII_BMCR, &bmcr);
3208                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3209                                 continue;
3210                         if (bmcr && bmcr != 0x7fff)
3211                                 break;
3212                         udelay(10);
3213                 }
3214
3215                 lcl_adv = 0;
3216                 rmt_adv = 0;
3217
3218                 tp->link_config.active_speed = current_speed;
3219                 tp->link_config.active_duplex = current_duplex;
3220
3221                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3222                         if ((bmcr & BMCR_ANENABLE) &&
3223                             tg3_copper_is_advertising_all(tp,
3224                                                 tp->link_config.advertising)) {
3225                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3226                                                                   &rmt_adv))
3227                                         current_link_up = 1;
3228                         }
3229                 } else {
3230                         if (!(bmcr & BMCR_ANENABLE) &&
3231                             tp->link_config.speed == current_speed &&
3232                             tp->link_config.duplex == current_duplex &&
3233                             tp->link_config.flowctrl ==
3234                             tp->link_config.active_flowctrl) {
3235                                 current_link_up = 1;
3236                         }
3237                 }
3238
3239                 if (current_link_up == 1 &&
3240                     tp->link_config.active_duplex == DUPLEX_FULL)
3241                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3242         }
3243
3244 relink:
3245         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3246                 u32 tmp;
3247
3248                 tg3_phy_copper_begin(tp);
3249
3250                 tg3_readphy(tp, MII_BMSR, &tmp);
3251                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3252                     (tmp & BMSR_LSTATUS))
3253                         current_link_up = 1;
3254         }
3255
3256         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3257         if (current_link_up == 1) {
3258                 if (tp->link_config.active_speed == SPEED_100 ||
3259                     tp->link_config.active_speed == SPEED_10)
3260                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3261                 else
3262                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3263         } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3264                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3265         else
3266                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3267
3268         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3269         if (tp->link_config.active_duplex == DUPLEX_HALF)
3270                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3271
3272         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3273                 if (current_link_up == 1 &&
3274                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3275                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3276                 else
3277                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3278         }
3279
3280         /* ??? Without this setting Netgear GA302T PHY does not
3281          * ??? send/receive packets...
3282          */
3283         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3284             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3285                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3286                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3287                 udelay(80);
3288         }
3289
3290         tw32_f(MAC_MODE, tp->mac_mode);
3291         udelay(40);
3292
3293         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3294                 /* Polled via timer. */
3295                 tw32_f(MAC_EVENT, 0);
3296         } else {
3297                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3298         }
3299         udelay(40);
3300
3301         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3302             current_link_up == 1 &&
3303             tp->link_config.active_speed == SPEED_1000 &&
3304             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3305              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3306                 udelay(120);
3307                 tw32_f(MAC_STATUS,
3308                      (MAC_STATUS_SYNC_CHANGED |
3309                       MAC_STATUS_CFG_CHANGED));
3310                 udelay(40);
3311                 tg3_write_mem(tp,
3312                               NIC_SRAM_FIRMWARE_MBOX,
3313                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3314         }
3315
3316         /* Prevent send BD corruption. */
3317         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3318                 u16 oldlnkctl, newlnkctl;
3319
3320                 pci_read_config_word(tp->pdev,
3321                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3322                                      &oldlnkctl);
3323                 if (tp->link_config.active_speed == SPEED_100 ||
3324                     tp->link_config.active_speed == SPEED_10)
3325                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3326                 else
3327                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3328                 if (newlnkctl != oldlnkctl)
3329                         pci_write_config_word(tp->pdev,
3330                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3331                                               newlnkctl);
3332         }
3333
3334         if (current_link_up != netif_carrier_ok(tp->dev)) {
3335                 if (current_link_up)
3336                         netif_carrier_on(tp->dev);
3337                 else
3338                         netif_carrier_off(tp->dev);
3339                 tg3_link_report(tp);
3340         }
3341
3342         return 0;
3343 }
3344
3345 struct tg3_fiber_aneginfo {
3346         int state;
3347 #define ANEG_STATE_UNKNOWN              0
3348 #define ANEG_STATE_AN_ENABLE            1
3349 #define ANEG_STATE_RESTART_INIT         2
3350 #define ANEG_STATE_RESTART              3
3351 #define ANEG_STATE_DISABLE_LINK_OK      4
3352 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3353 #define ANEG_STATE_ABILITY_DETECT       6
3354 #define ANEG_STATE_ACK_DETECT_INIT      7
3355 #define ANEG_STATE_ACK_DETECT           8
3356 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3357 #define ANEG_STATE_COMPLETE_ACK         10
3358 #define ANEG_STATE_IDLE_DETECT_INIT     11
3359 #define ANEG_STATE_IDLE_DETECT          12
3360 #define ANEG_STATE_LINK_OK              13
3361 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3362 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3363
3364         u32 flags;
3365 #define MR_AN_ENABLE            0x00000001
3366 #define MR_RESTART_AN           0x00000002
3367 #define MR_AN_COMPLETE          0x00000004
3368 #define MR_PAGE_RX              0x00000008
3369 #define MR_NP_LOADED            0x00000010
3370 #define MR_TOGGLE_TX            0x00000020
3371 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3372 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3373 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3374 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3375 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3376 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3377 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3378 #define MR_TOGGLE_RX            0x00002000
3379 #define MR_NP_RX                0x00004000
3380
3381 #define MR_LINK_OK              0x80000000
3382
3383         unsigned long link_time, cur_time;
3384
3385         u32 ability_match_cfg;
3386         int ability_match_count;
3387
3388         char ability_match, idle_match, ack_match;
3389
3390         u32 txconfig, rxconfig;
3391 #define ANEG_CFG_NP             0x00000080
3392 #define ANEG_CFG_ACK            0x00000040
3393 #define ANEG_CFG_RF2            0x00000020
3394 #define ANEG_CFG_RF1            0x00000010
3395 #define ANEG_CFG_PS2            0x00000001
3396 #define ANEG_CFG_PS1            0x00008000
3397 #define ANEG_CFG_HD             0x00004000
3398 #define ANEG_CFG_FD             0x00002000
3399 #define ANEG_CFG_INVAL          0x00001f06
3400
3401 };
3402 #define ANEG_OK         0
3403 #define ANEG_DONE       1
3404 #define ANEG_TIMER_ENAB 2
3405 #define ANEG_FAILED     -1
3406
3407 #define ANEG_STATE_SETTLE_TIME  10000
3408
3409 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3410                                    struct tg3_fiber_aneginfo *ap)
3411 {
3412         u16 flowctrl;
3413         unsigned long delta;
3414         u32 rx_cfg_reg;
3415         int ret;
3416
3417         if (ap->state == ANEG_STATE_UNKNOWN) {
3418                 ap->rxconfig = 0;
3419                 ap->link_time = 0;
3420                 ap->cur_time = 0;
3421                 ap->ability_match_cfg = 0;
3422                 ap->ability_match_count = 0;
3423                 ap->ability_match = 0;
3424                 ap->idle_match = 0;
3425                 ap->ack_match = 0;
3426         }
3427         ap->cur_time++;
3428
3429         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3430                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3431
3432                 if (rx_cfg_reg != ap->ability_match_cfg) {
3433                         ap->ability_match_cfg = rx_cfg_reg;
3434                         ap->ability_match = 0;
3435                         ap->ability_match_count = 0;
3436                 } else {
3437                         if (++ap->ability_match_count > 1) {
3438                                 ap->ability_match = 1;
3439                                 ap->ability_match_cfg = rx_cfg_reg;
3440                         }
3441                 }
3442                 if (rx_cfg_reg & ANEG_CFG_ACK)
3443                         ap->ack_match = 1;
3444                 else
3445                         ap->ack_match = 0;
3446
3447                 ap->idle_match = 0;
3448         } else {
3449                 ap->idle_match = 1;
3450                 ap->ability_match_cfg = 0;
3451                 ap->ability_match_count = 0;
3452                 ap->ability_match = 0;
3453                 ap->ack_match = 0;
3454
3455                 rx_cfg_reg = 0;
3456         }
3457
3458         ap->rxconfig = rx_cfg_reg;
3459         ret = ANEG_OK;
3460
3461         switch (ap->state) {
3462         case ANEG_STATE_UNKNOWN:
3463                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3464                         ap->state = ANEG_STATE_AN_ENABLE;
3465
3466                 /* fallthru */
3467         case ANEG_STATE_AN_ENABLE:
3468                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3469                 if (ap->flags & MR_AN_ENABLE) {
3470                         ap->link_time = 0;
3471                         ap->cur_time = 0;
3472                         ap->ability_match_cfg = 0;
3473                         ap->ability_match_count = 0;
3474                         ap->ability_match = 0;
3475                         ap->idle_match = 0;
3476                         ap->ack_match = 0;
3477
3478                         ap->state = ANEG_STATE_RESTART_INIT;
3479                 } else {
3480                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3481                 }
3482                 break;
3483
3484         case ANEG_STATE_RESTART_INIT:
3485                 ap->link_time = ap->cur_time;
3486                 ap->flags &= ~(MR_NP_LOADED);
3487                 ap->txconfig = 0;
3488                 tw32(MAC_TX_AUTO_NEG, 0);
3489                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3490                 tw32_f(MAC_MODE, tp->mac_mode);
3491                 udelay(40);
3492
3493                 ret = ANEG_TIMER_ENAB;
3494                 ap->state = ANEG_STATE_RESTART;
3495
3496                 /* fallthru */
3497         case ANEG_STATE_RESTART:
3498                 delta = ap->cur_time - ap->link_time;
3499                 if (delta > ANEG_STATE_SETTLE_TIME)
3500                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3501                 else
3502                         ret = ANEG_TIMER_ENAB;
3503                 break;
3504
3505         case ANEG_STATE_DISABLE_LINK_OK:
3506                 ret = ANEG_DONE;
3507                 break;
3508
3509         case ANEG_STATE_ABILITY_DETECT_INIT:
3510                 ap->flags &= ~(MR_TOGGLE_TX);
3511                 ap->txconfig = ANEG_CFG_FD;
3512                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3513                 if (flowctrl & ADVERTISE_1000XPAUSE)
3514                         ap->txconfig |= ANEG_CFG_PS1;
3515                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3516                         ap->txconfig |= ANEG_CFG_PS2;
3517                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3518                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3519                 tw32_f(MAC_MODE, tp->mac_mode);
3520                 udelay(40);
3521
3522                 ap->state = ANEG_STATE_ABILITY_DETECT;
3523                 break;
3524
3525         case ANEG_STATE_ABILITY_DETECT:
3526                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3527                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3528                 break;
3529
3530         case ANEG_STATE_ACK_DETECT_INIT:
3531                 ap->txconfig |= ANEG_CFG_ACK;
3532                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3533                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3534                 tw32_f(MAC_MODE, tp->mac_mode);
3535                 udelay(40);
3536
3537                 ap->state = ANEG_STATE_ACK_DETECT;
3538
3539                 /* fallthru */
3540         case ANEG_STATE_ACK_DETECT:
3541                 if (ap->ack_match != 0) {
3542                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3543                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3544                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3545                         } else {
3546                                 ap->state = ANEG_STATE_AN_ENABLE;
3547                         }
3548                 } else if (ap->ability_match != 0 &&
3549                            ap->rxconfig == 0) {
3550                         ap->state = ANEG_STATE_AN_ENABLE;
3551                 }
3552                 break;
3553
3554         case ANEG_STATE_COMPLETE_ACK_INIT:
3555                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3556                         ret = ANEG_FAILED;
3557                         break;
3558                 }
3559                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3560                                MR_LP_ADV_HALF_DUPLEX |
3561                                MR_LP_ADV_SYM_PAUSE |
3562                                MR_LP_ADV_ASYM_PAUSE |
3563                                MR_LP_ADV_REMOTE_FAULT1 |
3564                                MR_LP_ADV_REMOTE_FAULT2 |
3565                                MR_LP_ADV_NEXT_PAGE |
3566                                MR_TOGGLE_RX |
3567                                MR_NP_RX);
3568                 if (ap->rxconfig & ANEG_CFG_FD)
3569                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3570                 if (ap->rxconfig & ANEG_CFG_HD)
3571                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3572                 if (ap->rxconfig & ANEG_CFG_PS1)
3573                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3574                 if (ap->rxconfig & ANEG_CFG_PS2)
3575                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3576                 if (ap->rxconfig & ANEG_CFG_RF1)
3577                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3578                 if (ap->rxconfig & ANEG_CFG_RF2)
3579                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3580                 if (ap->rxconfig & ANEG_CFG_NP)
3581                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3582
3583                 ap->link_time = ap->cur_time;
3584
3585                 ap->flags ^= (MR_TOGGLE_TX);
3586                 if (ap->rxconfig & 0x0008)
3587                         ap->flags |= MR_TOGGLE_RX;
3588                 if (ap->rxconfig & ANEG_CFG_NP)
3589                         ap->flags |= MR_NP_RX;
3590                 ap->flags |= MR_PAGE_RX;
3591
3592                 ap->state = ANEG_STATE_COMPLETE_ACK;
3593                 ret = ANEG_TIMER_ENAB;
3594                 break;
3595
3596         case ANEG_STATE_COMPLETE_ACK:
3597                 if (ap->ability_match != 0 &&
3598                     ap->rxconfig == 0) {
3599                         ap->state = ANEG_STATE_AN_ENABLE;
3600                         break;
3601                 }
3602                 delta = ap->cur_time - ap->link_time;
3603                 if (delta > ANEG_STATE_SETTLE_TIME) {
3604                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3605                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3606                         } else {
3607                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3608                                     !(ap->flags & MR_NP_RX)) {
3609                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3610                                 } else {
3611                                         ret = ANEG_FAILED;
3612                                 }
3613                         }
3614                 }
3615                 break;
3616
3617         case ANEG_STATE_IDLE_DETECT_INIT:
3618                 ap->link_time = ap->cur_time;
3619                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3620                 tw32_f(MAC_MODE, tp->mac_mode);
3621                 udelay(40);
3622
3623                 ap->state = ANEG_STATE_IDLE_DETECT;
3624                 ret = ANEG_TIMER_ENAB;
3625                 break;
3626
3627         case ANEG_STATE_IDLE_DETECT:
3628                 if (ap->ability_match != 0 &&
3629                     ap->rxconfig == 0) {
3630                         ap->state = ANEG_STATE_AN_ENABLE;
3631                         break;
3632                 }
3633                 delta = ap->cur_time - ap->link_time;
3634                 if (delta > ANEG_STATE_SETTLE_TIME) {
3635                         /* XXX another gem from the Broadcom driver :( */
3636                         ap->state = ANEG_STATE_LINK_OK;
3637                 }
3638                 break;
3639
3640         case ANEG_STATE_LINK_OK:
3641                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3642                 ret = ANEG_DONE;
3643                 break;
3644
3645         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3646                 /* ??? unimplemented */
3647                 break;
3648
3649         case ANEG_STATE_NEXT_PAGE_WAIT:
3650                 /* ??? unimplemented */
3651                 break;
3652
3653         default:
3654                 ret = ANEG_FAILED;
3655                 break;
3656         }
3657
3658         return ret;
3659 }
3660
3661 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3662 {
3663         int res = 0;
3664         struct tg3_fiber_aneginfo aninfo;
3665         int status = ANEG_FAILED;
3666         unsigned int tick;
3667         u32 tmp;
3668
3669         tw32_f(MAC_TX_AUTO_NEG, 0);
3670
3671         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3672         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3673         udelay(40);
3674
3675         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3676         udelay(40);
3677
3678         memset(&aninfo, 0, sizeof(aninfo));
3679         aninfo.flags |= MR_AN_ENABLE;
3680         aninfo.state = ANEG_STATE_UNKNOWN;
3681         aninfo.cur_time = 0;
3682         tick = 0;
3683         while (++tick < 195000) {
3684                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3685                 if (status == ANEG_DONE || status == ANEG_FAILED)
3686                         break;
3687
3688                 udelay(1);
3689         }
3690
3691         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3692         tw32_f(MAC_MODE, tp->mac_mode);
3693         udelay(40);
3694
3695         *txflags = aninfo.txconfig;
3696         *rxflags = aninfo.flags;
3697
3698         if (status == ANEG_DONE &&
3699             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3700                              MR_LP_ADV_FULL_DUPLEX)))
3701                 res = 1;
3702
3703         return res;
3704 }
3705
3706 static void tg3_init_bcm8002(struct tg3 *tp)
3707 {
3708         u32 mac_status = tr32(MAC_STATUS);
3709         int i;
3710
3711         /* Reset when initting first time or we have a link. */
3712         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3713             !(mac_status & MAC_STATUS_PCS_SYNCED))
3714                 return;
3715
3716         /* Set PLL lock range. */
3717         tg3_writephy(tp, 0x16, 0x8007);
3718
3719         /* SW reset */
3720         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3721
3722         /* Wait for reset to complete. */
3723         /* XXX schedule_timeout() ... */
3724         for (i = 0; i < 500; i++)
3725                 udelay(10);
3726
3727         /* Config mode; select PMA/Ch 1 regs. */
3728         tg3_writephy(tp, 0x10, 0x8411);
3729
3730         /* Enable auto-lock and comdet, select txclk for tx. */
3731         tg3_writephy(tp, 0x11, 0x0a10);
3732
3733         tg3_writephy(tp, 0x18, 0x00a0);
3734         tg3_writephy(tp, 0x16, 0x41ff);
3735
3736         /* Assert and deassert POR. */
3737         tg3_writephy(tp, 0x13, 0x0400);
3738         udelay(40);
3739         tg3_writephy(tp, 0x13, 0x0000);
3740
3741         tg3_writephy(tp, 0x11, 0x0a50);
3742         udelay(40);
3743         tg3_writephy(tp, 0x11, 0x0a10);
3744
3745         /* Wait for signal to stabilize */
3746         /* XXX schedule_timeout() ... */
3747         for (i = 0; i < 15000; i++)
3748                 udelay(10);
3749
3750         /* Deselect the channel register so we can read the PHYID
3751          * later.
3752          */
3753         tg3_writephy(tp, 0x10, 0x8011);
3754 }
3755
3756 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3757 {
3758         u16 flowctrl;
3759         u32 sg_dig_ctrl, sg_dig_status;
3760         u32 serdes_cfg, expected_sg_dig_ctrl;
3761         int workaround, port_a;
3762         int current_link_up;
3763
3764         serdes_cfg = 0;
3765         expected_sg_dig_ctrl = 0;
3766         workaround = 0;
3767         port_a = 1;
3768         current_link_up = 0;
3769
3770         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3771             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3772                 workaround = 1;
3773                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3774                         port_a = 0;
3775
3776                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3777                 /* preserve bits 20-23 for voltage regulator */
3778                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3779         }
3780
3781         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3782
3783         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3784                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3785                         if (workaround) {
3786                                 u32 val = serdes_cfg;
3787
3788                                 if (port_a)
3789                                         val |= 0xc010000;
3790                                 else
3791                                         val |= 0x4010000;
3792                                 tw32_f(MAC_SERDES_CFG, val);
3793                         }
3794
3795                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3796                 }
3797                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3798                         tg3_setup_flow_control(tp, 0, 0);
3799                         current_link_up = 1;
3800                 }
3801                 goto out;
3802         }
3803
3804         /* Want auto-negotiation.  */
3805         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3806
3807         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3808         if (flowctrl & ADVERTISE_1000XPAUSE)
3809                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3810         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3811                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3812
3813         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3814                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3815                     tp->serdes_counter &&
3816                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3817                                     MAC_STATUS_RCVD_CFG)) ==
3818                      MAC_STATUS_PCS_SYNCED)) {
3819                         tp->serdes_counter--;
3820                         current_link_up = 1;
3821                         goto out;
3822                 }
3823 restart_autoneg:
3824                 if (workaround)
3825                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3826                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3827                 udelay(5);
3828                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3829
3830                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3831                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3832         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3833                                  MAC_STATUS_SIGNAL_DET)) {
3834                 sg_dig_status = tr32(SG_DIG_STATUS);
3835                 mac_status = tr32(MAC_STATUS);
3836
3837                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3838                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3839                         u32 local_adv = 0, remote_adv = 0;
3840
3841                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3842                                 local_adv |= ADVERTISE_1000XPAUSE;
3843                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3844                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3845
3846                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3847                                 remote_adv |= LPA_1000XPAUSE;
3848                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3849                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3850
3851                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3852                         current_link_up = 1;
3853                         tp->serdes_counter = 0;
3854                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3855                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3856                         if (tp->serdes_counter)
3857                                 tp->serdes_counter--;
3858                         else {
3859                                 if (workaround) {
3860                                         u32 val = serdes_cfg;
3861
3862                                         if (port_a)
3863                                                 val |= 0xc010000;
3864                                         else
3865                                                 val |= 0x4010000;
3866
3867                                         tw32_f(MAC_SERDES_CFG, val);
3868                                 }
3869
3870                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3871                                 udelay(40);
3872
3873                                 /* Link parallel detection - link is up */
3874                                 /* only if we have PCS_SYNC and not */
3875                                 /* receiving config code words */
3876                                 mac_status = tr32(MAC_STATUS);
3877                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3878                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3879                                         tg3_setup_flow_control(tp, 0, 0);
3880                                         current_link_up = 1;
3881                                         tp->tg3_flags2 |=
3882                                                 TG3_FLG2_PARALLEL_DETECT;
3883                                         tp->serdes_counter =
3884                                                 SERDES_PARALLEL_DET_TIMEOUT;
3885                                 } else
3886                                         goto restart_autoneg;
3887                         }
3888                 }
3889         } else {
3890                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3891                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3892         }
3893
3894 out:
3895         return current_link_up;
3896 }
3897
3898 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3899 {
3900         int current_link_up = 0;
3901
3902         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3903                 goto out;
3904
3905         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3906                 u32 txflags, rxflags;
3907                 int i;
3908
3909                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3910                         u32 local_adv = 0, remote_adv = 0;
3911
3912                         if (txflags & ANEG_CFG_PS1)
3913                                 local_adv |= ADVERTISE_1000XPAUSE;
3914                         if (txflags & ANEG_CFG_PS2)
3915                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3916
3917                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3918                                 remote_adv |= LPA_1000XPAUSE;
3919                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3920                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3921
3922                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3923
3924                         current_link_up = 1;
3925                 }
3926                 for (i = 0; i < 30; i++) {
3927                         udelay(20);
3928                         tw32_f(MAC_STATUS,
3929                                (MAC_STATUS_SYNC_CHANGED |
3930                                 MAC_STATUS_CFG_CHANGED));
3931                         udelay(40);
3932                         if ((tr32(MAC_STATUS) &
3933                              (MAC_STATUS_SYNC_CHANGED |
3934                               MAC_STATUS_CFG_CHANGED)) == 0)
3935                                 break;
3936                 }
3937
3938                 mac_status = tr32(MAC_STATUS);
3939                 if (current_link_up == 0 &&
3940                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3941                     !(mac_status & MAC_STATUS_RCVD_CFG))
3942                         current_link_up = 1;
3943         } else {
3944                 tg3_setup_flow_control(tp, 0, 0);
3945
3946                 /* Forcing 1000FD link up. */
3947                 current_link_up = 1;
3948
3949                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3950                 udelay(40);
3951
3952                 tw32_f(MAC_MODE, tp->mac_mode);
3953                 udelay(40);
3954         }
3955
3956 out:
3957         return current_link_up;
3958 }
3959
3960 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3961 {
3962         u32 orig_pause_cfg;
3963         u16 orig_active_speed;
3964         u8 orig_active_duplex;
3965         u32 mac_status;
3966         int current_link_up;
3967         int i;
3968
3969         orig_pause_cfg = tp->link_config.active_flowctrl;
3970         orig_active_speed = tp->link_config.active_speed;
3971         orig_active_duplex = tp->link_config.active_duplex;
3972
3973         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3974             netif_carrier_ok(tp->dev) &&
3975             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3976                 mac_status = tr32(MAC_STATUS);
3977                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3978                                MAC_STATUS_SIGNAL_DET |
3979                                MAC_STATUS_CFG_CHANGED |
3980                                MAC_STATUS_RCVD_CFG);
3981                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3982                                    MAC_STATUS_SIGNAL_DET)) {
3983                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3984                                             MAC_STATUS_CFG_CHANGED));
3985                         return 0;
3986                 }
3987         }
3988
3989         tw32_f(MAC_TX_AUTO_NEG, 0);
3990
3991         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3992         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3993         tw32_f(MAC_MODE, tp->mac_mode);
3994         udelay(40);
3995
3996         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3997                 tg3_init_bcm8002(tp);
3998
3999         /* Enable link change event even when serdes polling.  */
4000         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4001         udelay(40);
4002
4003         current_link_up = 0;
4004         mac_status = tr32(MAC_STATUS);
4005
4006         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4007                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4008         else
4009                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4010
4011         tp->napi[0].hw_status->status =
4012                 (SD_STATUS_UPDATED |
4013                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4014
4015         for (i = 0; i < 100; i++) {
4016                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4017                                     MAC_STATUS_CFG_CHANGED));
4018                 udelay(5);
4019                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4020                                          MAC_STATUS_CFG_CHANGED |
4021                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4022                         break;
4023         }
4024
4025         mac_status = tr32(MAC_STATUS);
4026         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4027                 current_link_up = 0;
4028                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4029                     tp->serdes_counter == 0) {
4030                         tw32_f(MAC_MODE, (tp->mac_mode |
4031                                           MAC_MODE_SEND_CONFIGS));
4032                         udelay(1);
4033                         tw32_f(MAC_MODE, tp->mac_mode);
4034                 }
4035         }
4036
4037         if (current_link_up == 1) {
4038                 tp->link_config.active_speed = SPEED_1000;
4039                 tp->link_config.active_duplex = DUPLEX_FULL;
4040                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4041                                     LED_CTRL_LNKLED_OVERRIDE |
4042                                     LED_CTRL_1000MBPS_ON));
4043         } else {
4044                 tp->link_config.active_speed = SPEED_INVALID;
4045                 tp->link_config.active_duplex = DUPLEX_INVALID;
4046                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4047                                     LED_CTRL_LNKLED_OVERRIDE |
4048                                     LED_CTRL_TRAFFIC_OVERRIDE));
4049         }
4050
4051         if (current_link_up != netif_carrier_ok(tp->dev)) {
4052                 if (current_link_up)
4053                         netif_carrier_on(tp->dev);
4054                 else
4055                         netif_carrier_off(tp->dev);
4056                 tg3_link_report(tp);
4057         } else {
4058                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4059                 if (orig_pause_cfg != now_pause_cfg ||
4060                     orig_active_speed != tp->link_config.active_speed ||
4061                     orig_active_duplex != tp->link_config.active_duplex)
4062                         tg3_link_report(tp);
4063         }
4064
4065         return 0;
4066 }
4067
4068 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4069 {
4070         int current_link_up, err = 0;
4071         u32 bmsr, bmcr;
4072         u16 current_speed;
4073         u8 current_duplex;
4074         u32 local_adv, remote_adv;
4075
4076         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4077         tw32_f(MAC_MODE, tp->mac_mode);
4078         udelay(40);
4079
4080         tw32(MAC_EVENT, 0);
4081
4082         tw32_f(MAC_STATUS,
4083              (MAC_STATUS_SYNC_CHANGED |
4084               MAC_STATUS_CFG_CHANGED |
4085               MAC_STATUS_MI_COMPLETION |
4086               MAC_STATUS_LNKSTATE_CHANGED));
4087         udelay(40);
4088
4089         if (force_reset)
4090                 tg3_phy_reset(tp);
4091
4092         current_link_up = 0;
4093         current_speed = SPEED_INVALID;
4094         current_duplex = DUPLEX_INVALID;
4095
4096         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4097         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4099                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4100                         bmsr |= BMSR_LSTATUS;
4101                 else
4102                         bmsr &= ~BMSR_LSTATUS;
4103         }
4104
4105         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4106
4107         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4108             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4109                 /* do nothing, just check for link up at the end */
4110         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4111                 u32 adv, new_adv;
4112
4113                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4114                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4115                                   ADVERTISE_1000XPAUSE |
4116                                   ADVERTISE_1000XPSE_ASYM |
4117                                   ADVERTISE_SLCT);
4118
4119                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4120
4121                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4122                         new_adv |= ADVERTISE_1000XHALF;
4123                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4124                         new_adv |= ADVERTISE_1000XFULL;
4125
4126                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4127                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4128                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4129                         tg3_writephy(tp, MII_BMCR, bmcr);
4130
4131                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4132                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4133                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4134
4135                         return err;
4136                 }
4137         } else {
4138                 u32 new_bmcr;
4139
4140                 bmcr &= ~BMCR_SPEED1000;
4141                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4142
4143                 if (tp->link_config.duplex == DUPLEX_FULL)
4144                         new_bmcr |= BMCR_FULLDPLX;
4145
4146                 if (new_bmcr != bmcr) {
4147                         /* BMCR_SPEED1000 is a reserved bit that needs
4148                          * to be set on write.
4149                          */
4150                         new_bmcr |= BMCR_SPEED1000;
4151
4152                         /* Force a linkdown */
4153                         if (netif_carrier_ok(tp->dev)) {
4154                                 u32 adv;
4155
4156                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4157                                 adv &= ~(ADVERTISE_1000XFULL |
4158                                          ADVERTISE_1000XHALF |
4159                                          ADVERTISE_SLCT);
4160                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4161                                 tg3_writephy(tp, MII_BMCR, bmcr |
4162                                                            BMCR_ANRESTART |
4163                                                            BMCR_ANENABLE);
4164                                 udelay(10);
4165                                 netif_carrier_off(tp->dev);
4166                         }
4167                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4168                         bmcr = new_bmcr;
4169                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4170                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4171                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4172                             ASIC_REV_5714) {
4173                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4174                                         bmsr |= BMSR_LSTATUS;
4175                                 else
4176                                         bmsr &= ~BMSR_LSTATUS;
4177                         }
4178                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4179                 }
4180         }
4181
4182         if (bmsr & BMSR_LSTATUS) {
4183                 current_speed = SPEED_1000;
4184                 current_link_up = 1;
4185                 if (bmcr & BMCR_FULLDPLX)
4186                         current_duplex = DUPLEX_FULL;
4187                 else
4188                         current_duplex = DUPLEX_HALF;
4189
4190                 local_adv = 0;
4191                 remote_adv = 0;
4192
4193                 if (bmcr & BMCR_ANENABLE) {
4194                         u32 common;
4195
4196                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4197                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4198                         common = local_adv & remote_adv;
4199                         if (common & (ADVERTISE_1000XHALF |
4200                                       ADVERTISE_1000XFULL)) {
4201                                 if (common & ADVERTISE_1000XFULL)
4202                                         current_duplex = DUPLEX_FULL;
4203                                 else
4204                                         current_duplex = DUPLEX_HALF;
4205                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4206                                 /* Link is up via parallel detect */
4207                         } else {
4208                                 current_link_up = 0;
4209                         }
4210                 }
4211         }
4212
4213         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4214                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4215
4216         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4217         if (tp->link_config.active_duplex == DUPLEX_HALF)
4218                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4219
4220         tw32_f(MAC_MODE, tp->mac_mode);
4221         udelay(40);
4222
4223         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4224
4225         tp->link_config.active_speed = current_speed;
4226         tp->link_config.active_duplex = current_duplex;
4227
4228         if (current_link_up != netif_carrier_ok(tp->dev)) {
4229                 if (current_link_up)
4230                         netif_carrier_on(tp->dev);
4231                 else {
4232                         netif_carrier_off(tp->dev);
4233                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4234                 }
4235                 tg3_link_report(tp);
4236         }
4237         return err;
4238 }
4239
4240 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4241 {
4242         if (tp->serdes_counter) {
4243                 /* Give autoneg time to complete. */
4244                 tp->serdes_counter--;
4245                 return;
4246         }
4247
4248         if (!netif_carrier_ok(tp->dev) &&
4249             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4250                 u32 bmcr;
4251
4252                 tg3_readphy(tp, MII_BMCR, &bmcr);
4253                 if (bmcr & BMCR_ANENABLE) {
4254                         u32 phy1, phy2;
4255
4256                         /* Select shadow register 0x1f */
4257                         tg3_writephy(tp, 0x1c, 0x7c00);
4258                         tg3_readphy(tp, 0x1c, &phy1);
4259
4260                         /* Select expansion interrupt status register */
4261                         tg3_writephy(tp, 0x17, 0x0f01);
4262                         tg3_readphy(tp, 0x15, &phy2);
4263                         tg3_readphy(tp, 0x15, &phy2);
4264
4265                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4266                                 /* We have signal detect and not receiving
4267                                  * config code words, link is up by parallel
4268                                  * detection.
4269                                  */
4270
4271                                 bmcr &= ~BMCR_ANENABLE;
4272                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4273                                 tg3_writephy(tp, MII_BMCR, bmcr);
4274                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4275                         }
4276                 }
4277         } else if (netif_carrier_ok(tp->dev) &&
4278                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4279                    (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4280                 u32 phy2;
4281
4282                 /* Select expansion interrupt status register */
4283                 tg3_writephy(tp, 0x17, 0x0f01);
4284                 tg3_readphy(tp, 0x15, &phy2);
4285                 if (phy2 & 0x20) {
4286                         u32 bmcr;
4287
4288                         /* Config code words received, turn on autoneg. */
4289                         tg3_readphy(tp, MII_BMCR, &bmcr);
4290                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4291
4292                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4293
4294                 }
4295         }
4296 }
4297
4298 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4299 {
4300         int err;
4301
4302         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
4303                 err = tg3_setup_fiber_phy(tp, force_reset);
4304         else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
4305                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4306         else
4307                 err = tg3_setup_copper_phy(tp, force_reset);
4308
4309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4310                 u32 val, scale;
4311
4312                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4313                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4314                         scale = 65;
4315                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4316                         scale = 6;
4317                 else
4318                         scale = 12;
4319
4320                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4321                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4322                 tw32(GRC_MISC_CFG, val);
4323         }
4324
4325         if (tp->link_config.active_speed == SPEED_1000 &&
4326             tp->link_config.active_duplex == DUPLEX_HALF)
4327                 tw32(MAC_TX_LENGTHS,
4328                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4329                       (6 << TX_LENGTHS_IPG_SHIFT) |
4330                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4331         else
4332                 tw32(MAC_TX_LENGTHS,
4333                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4334                       (6 << TX_LENGTHS_IPG_SHIFT) |
4335                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4336
4337         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4338                 if (netif_carrier_ok(tp->dev)) {
4339                         tw32(HOSTCC_STAT_COAL_TICKS,
4340                              tp->coal.stats_block_coalesce_usecs);
4341                 } else {
4342                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4343                 }
4344         }
4345
4346         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4347                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4348                 if (!netif_carrier_ok(tp->dev))
4349                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4350                               tp->pwrmgmt_thresh;
4351                 else
4352                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4353                 tw32(PCIE_PWR_MGMT_THRESH, val);
4354         }
4355
4356         return err;
4357 }
4358
4359 /* This is called whenever we suspect that the system chipset is re-
4360  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4361  * is bogus tx completions. We try to recover by setting the
4362  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4363  * in the workqueue.
4364  */
4365 static void tg3_tx_recover(struct tg3 *tp)
4366 {
4367         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4368                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4369
4370         netdev_warn(tp->dev,
4371                     "The system may be re-ordering memory-mapped I/O "
4372                     "cycles to the network device, attempting to recover. "
4373                     "Please report the problem to the driver maintainer "
4374                     "and include system chipset information.\n");
4375
4376         spin_lock(&tp->lock);
4377         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4378         spin_unlock(&tp->lock);
4379 }
4380
4381 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4382 {
4383         smp_mb();
4384         return tnapi->tx_pending -
4385                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4386 }
4387
4388 /* Tigon3 never reports partial packet sends.  So we do not
4389  * need special logic to handle SKBs that have not had all
4390  * of their frags sent yet, like SunGEM does.
4391  */
4392 static void tg3_tx(struct tg3_napi *tnapi)
4393 {
4394         struct tg3 *tp = tnapi->tp;
4395         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4396         u32 sw_idx = tnapi->tx_cons;
4397         struct netdev_queue *txq;
4398         int index = tnapi - tp->napi;
4399
4400         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4401                 index--;
4402
4403         txq = netdev_get_tx_queue(tp->dev, index);
4404
4405         while (sw_idx != hw_idx) {
4406                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4407                 struct sk_buff *skb = ri->skb;
4408                 int i, tx_bug = 0;
4409
4410                 if (unlikely(skb == NULL)) {
4411                         tg3_tx_recover(tp);
4412                         return;
4413                 }
4414
4415                 pci_unmap_single(tp->pdev,
4416                                  dma_unmap_addr(ri, mapping),
4417                                  skb_headlen(skb),
4418                                  PCI_DMA_TODEVICE);
4419
4420                 ri->skb = NULL;
4421
4422                 sw_idx = NEXT_TX(sw_idx);
4423
4424                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4425                         ri = &tnapi->tx_buffers[sw_idx];
4426                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4427                                 tx_bug = 1;
4428
4429                         pci_unmap_page(tp->pdev,
4430                                        dma_unmap_addr(ri, mapping),
4431                                        skb_shinfo(skb)->frags[i].size,
4432                                        PCI_DMA_TODEVICE);
4433                         sw_idx = NEXT_TX(sw_idx);
4434                 }
4435
4436                 dev_kfree_skb(skb);
4437
4438                 if (unlikely(tx_bug)) {
4439                         tg3_tx_recover(tp);
4440                         return;
4441                 }
4442         }
4443
4444         tnapi->tx_cons = sw_idx;
4445
4446         /* Need to make the tx_cons update visible to tg3_start_xmit()
4447          * before checking for netif_queue_stopped().  Without the
4448          * memory barrier, there is a small possibility that tg3_start_xmit()
4449          * will miss it and cause the queue to be stopped forever.
4450          */
4451         smp_mb();
4452
4453         if (unlikely(netif_tx_queue_stopped(txq) &&
4454                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4455                 __netif_tx_lock(txq, smp_processor_id());
4456                 if (netif_tx_queue_stopped(txq) &&
4457                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4458                         netif_tx_wake_queue(txq);
4459                 __netif_tx_unlock(txq);
4460         }
4461 }
4462
4463 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4464 {
4465         if (!ri->skb)
4466                 return;
4467
4468         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4469                          map_sz, PCI_DMA_FROMDEVICE);
4470         dev_kfree_skb_any(ri->skb);
4471         ri->skb = NULL;
4472 }
4473
4474 /* Returns size of skb allocated or < 0 on error.
4475  *
4476  * We only need to fill in the address because the other members
4477  * of the RX descriptor are invariant, see tg3_init_rings.
4478  *
4479  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4480  * posting buffers we only dirty the first cache line of the RX
4481  * descriptor (containing the address).  Whereas for the RX status
4482  * buffers the cpu only reads the last cacheline of the RX descriptor
4483  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4484  */
4485 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4486                             u32 opaque_key, u32 dest_idx_unmasked)
4487 {
4488         struct tg3_rx_buffer_desc *desc;
4489         struct ring_info *map, *src_map;
4490         struct sk_buff *skb;
4491         dma_addr_t mapping;
4492         int skb_size, dest_idx;
4493
4494         src_map = NULL;
4495         switch (opaque_key) {
4496         case RXD_OPAQUE_RING_STD:
4497                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4498                 desc = &tpr->rx_std[dest_idx];
4499                 map = &tpr->rx_std_buffers[dest_idx];
4500                 skb_size = tp->rx_pkt_map_sz;
4501                 break;
4502
4503         case RXD_OPAQUE_RING_JUMBO:
4504                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4505                 desc = &tpr->rx_jmb[dest_idx].std;
4506                 map = &tpr->rx_jmb_buffers[dest_idx];
4507                 skb_size = TG3_RX_JMB_MAP_SZ;
4508                 break;
4509
4510         default:
4511                 return -EINVAL;
4512         }
4513
4514         /* Do not overwrite any of the map or rp information
4515          * until we are sure we can commit to a new buffer.
4516          *
4517          * Callers depend upon this behavior and assume that
4518          * we leave everything unchanged if we fail.
4519          */
4520         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4521         if (skb == NULL)
4522                 return -ENOMEM;
4523
4524         skb_reserve(skb, tp->rx_offset);
4525
4526         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4527                                  PCI_DMA_FROMDEVICE);
4528         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4529                 dev_kfree_skb(skb);
4530                 return -EIO;
4531         }
4532
4533         map->skb = skb;
4534         dma_unmap_addr_set(map, mapping, mapping);
4535
4536         desc->addr_hi = ((u64)mapping >> 32);
4537         desc->addr_lo = ((u64)mapping & 0xffffffff);
4538
4539         return skb_size;
4540 }
4541
4542 /* We only need to move over in the address because the other
4543  * members of the RX descriptor are invariant.  See notes above
4544  * tg3_alloc_rx_skb for full details.
4545  */
4546 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4547                            struct tg3_rx_prodring_set *dpr,
4548                            u32 opaque_key, int src_idx,
4549                            u32 dest_idx_unmasked)
4550 {
4551         struct tg3 *tp = tnapi->tp;
4552         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4553         struct ring_info *src_map, *dest_map;
4554         struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4555         int dest_idx;
4556
4557         switch (opaque_key) {
4558         case RXD_OPAQUE_RING_STD:
4559                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4560                 dest_desc = &dpr->rx_std[dest_idx];
4561                 dest_map = &dpr->rx_std_buffers[dest_idx];
4562                 src_desc = &spr->rx_std[src_idx];
4563                 src_map = &spr->rx_std_buffers[src_idx];
4564                 break;
4565
4566         case RXD_OPAQUE_RING_JUMBO:
4567                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4568                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4569                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4570                 src_desc = &spr->rx_jmb[src_idx].std;
4571                 src_map = &spr->rx_jmb_buffers[src_idx];
4572                 break;
4573
4574         default:
4575                 return;
4576         }
4577
4578         dest_map->skb = src_map->skb;
4579         dma_unmap_addr_set(dest_map, mapping,
4580                            dma_unmap_addr(src_map, mapping));
4581         dest_desc->addr_hi = src_desc->addr_hi;
4582         dest_desc->addr_lo = src_desc->addr_lo;
4583
4584         /* Ensure that the update to the skb happens after the physical
4585          * addresses have been transferred to the new BD location.
4586          */
4587         smp_wmb();
4588
4589         src_map->skb = NULL;
4590 }
4591
4592 /* The RX ring scheme is composed of multiple rings which post fresh
4593  * buffers to the chip, and one special ring the chip uses to report
4594  * status back to the host.
4595  *
4596  * The special ring reports the status of received packets to the
4597  * host.  The chip does not write into the original descriptor the
4598  * RX buffer was obtained from.  The chip simply takes the original
4599  * descriptor as provided by the host, updates the status and length
4600  * field, then writes this into the next status ring entry.
4601  *
4602  * Each ring the host uses to post buffers to the chip is described
4603  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4604  * it is first placed into the on-chip ram.  When the packet's length
4605  * is known, it walks down the TG3_BDINFO entries to select the ring.
4606  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4607  * which is within the range of the new packet's length is chosen.
4608  *
4609  * The "separate ring for rx status" scheme may sound queer, but it makes
4610  * sense from a cache coherency perspective.  If only the host writes
4611  * to the buffer post rings, and only the chip writes to the rx status
4612  * rings, then cache lines never move beyond shared-modified state.
4613  * If both the host and chip were to write into the same ring, cache line
4614  * eviction could occur since both entities want it in an exclusive state.
4615  */
4616 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4617 {
4618         struct tg3 *tp = tnapi->tp;
4619         u32 work_mask, rx_std_posted = 0;
4620         u32 std_prod_idx, jmb_prod_idx;
4621         u32 sw_idx = tnapi->rx_rcb_ptr;
4622         u16 hw_idx;
4623         int received;
4624         struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4625
4626         hw_idx = *(tnapi->rx_rcb_prod_idx);
4627         /*
4628          * We need to order the read of hw_idx and the read of
4629          * the opaque cookie.
4630          */
4631         rmb();
4632         work_mask = 0;
4633         received = 0;
4634         std_prod_idx = tpr->rx_std_prod_idx;
4635         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4636         while (sw_idx != hw_idx && budget > 0) {
4637                 struct ring_info *ri;
4638                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4639                 unsigned int len;
4640                 struct sk_buff *skb;
4641                 dma_addr_t dma_addr;
4642                 u32 opaque_key, desc_idx, *post_ptr;
4643                 bool hw_vlan __maybe_unused = false;
4644                 u16 vtag __maybe_unused = 0;
4645
4646                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4647                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4648                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4649                         ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4650                         dma_addr = dma_unmap_addr(ri, mapping);
4651                         skb = ri->skb;
4652                         post_ptr = &std_prod_idx;
4653                         rx_std_posted++;
4654                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4655                         ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4656                         dma_addr = dma_unmap_addr(ri, mapping);
4657                         skb = ri->skb;
4658                         post_ptr = &jmb_prod_idx;
4659                 } else
4660                         goto next_pkt_nopost;
4661
4662                 work_mask |= opaque_key;
4663
4664                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4665                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4666                 drop_it:
4667                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4668                                        desc_idx, *post_ptr);
4669                 drop_it_no_recycle:
4670                         /* Other statistics kept track of by card. */
4671                         tp->net_stats.rx_dropped++;
4672                         goto next_pkt;
4673                 }
4674
4675                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4676                       ETH_FCS_LEN;
4677
4678                 if (len > TG3_RX_COPY_THRESH(tp)) {
4679                         int skb_size;
4680
4681                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4682                                                     *post_ptr);
4683                         if (skb_size < 0)
4684                                 goto drop_it;
4685
4686                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4687                                          PCI_DMA_FROMDEVICE);
4688
4689                         /* Ensure that the update to the skb happens
4690                          * after the usage of the old DMA mapping.
4691                          */
4692                         smp_wmb();
4693
4694                         ri->skb = NULL;
4695
4696                         skb_put(skb, len);
4697                 } else {
4698                         struct sk_buff *copy_skb;
4699
4700                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4701                                        desc_idx, *post_ptr);
4702
4703                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4704                                                     TG3_RAW_IP_ALIGN);
4705                         if (copy_skb == NULL)
4706                                 goto drop_it_no_recycle;
4707
4708                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4709                         skb_put(copy_skb, len);
4710                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4711                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4712                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4713
4714                         /* We'll reuse the original ring buffer. */
4715                         skb = copy_skb;
4716                 }
4717
4718                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4719                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4720                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4721                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4722                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4723                 else
4724                         skb->ip_summed = CHECKSUM_NONE;
4725
4726                 skb->protocol = eth_type_trans(skb, tp->dev);
4727
4728                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4729                     skb->protocol != htons(ETH_P_8021Q)) {
4730                         dev_kfree_skb(skb);
4731                         goto next_pkt;
4732                 }
4733
4734                 if (desc->type_flags & RXD_FLAG_VLAN &&
4735                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4736                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4737 #if TG3_VLAN_TAG_USED
4738                         if (tp->vlgrp)
4739                                 hw_vlan = true;
4740                         else
4741 #endif
4742                         {
4743                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4744                                                     __skb_push(skb, VLAN_HLEN);
4745
4746                                 memmove(ve, skb->data + VLAN_HLEN,
4747                                         ETH_ALEN * 2);
4748                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4749                                 ve->h_vlan_TCI = htons(vtag);
4750                         }
4751                 }
4752
4753 #if TG3_VLAN_TAG_USED
4754                 if (hw_vlan)
4755                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4756                 else
4757 #endif
4758                         napi_gro_receive(&tnapi->napi, skb);
4759
4760                 received++;
4761                 budget--;
4762
4763 next_pkt:
4764                 (*post_ptr)++;
4765
4766                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4767                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4768                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4769                                      tpr->rx_std_prod_idx);
4770                         work_mask &= ~RXD_OPAQUE_RING_STD;
4771                         rx_std_posted = 0;
4772                 }
4773 next_pkt_nopost:
4774                 sw_idx++;
4775                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4776
4777                 /* Refresh hw_idx to see if there is new work */
4778                 if (sw_idx == hw_idx) {
4779                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4780                         rmb();
4781                 }
4782         }
4783
4784         /* ACK the status ring. */
4785         tnapi->rx_rcb_ptr = sw_idx;
4786         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4787
4788         /* Refill RX ring(s). */
4789         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4790                 if (work_mask & RXD_OPAQUE_RING_STD) {
4791                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4792                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4793                                      tpr->rx_std_prod_idx);
4794                 }
4795                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4796                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4797                                                TG3_RX_JUMBO_RING_SIZE;
4798                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4799                                      tpr->rx_jmb_prod_idx);
4800                 }
4801                 mmiowb();
4802         } else if (work_mask) {
4803                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4804                  * updated before the producer indices can be updated.
4805                  */
4806                 smp_wmb();
4807
4808                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4809                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4810
4811                 if (tnapi != &tp->napi[1])
4812                         napi_schedule(&tp->napi[1].napi);
4813         }
4814
4815         return received;
4816 }
4817
4818 static void tg3_poll_link(struct tg3 *tp)
4819 {
4820         /* handle link change and other phy events */
4821         if (!(tp->tg3_flags &
4822               (TG3_FLAG_USE_LINKCHG_REG |
4823                TG3_FLAG_POLL_SERDES))) {
4824                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4825
4826                 if (sblk->status & SD_STATUS_LINK_CHG) {
4827                         sblk->status = SD_STATUS_UPDATED |
4828                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4829                         spin_lock(&tp->lock);
4830                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4831                                 tw32_f(MAC_STATUS,
4832                                      (MAC_STATUS_SYNC_CHANGED |
4833                                       MAC_STATUS_CFG_CHANGED |
4834                                       MAC_STATUS_MI_COMPLETION |
4835                                       MAC_STATUS_LNKSTATE_CHANGED));
4836                                 udelay(40);
4837                         } else
4838                                 tg3_setup_phy(tp, 0);
4839                         spin_unlock(&tp->lock);
4840                 }
4841         }
4842 }
4843
4844 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4845                                 struct tg3_rx_prodring_set *dpr,
4846                                 struct tg3_rx_prodring_set *spr)
4847 {
4848         u32 si, di, cpycnt, src_prod_idx;
4849         int i, err = 0;
4850
4851         while (1) {
4852                 src_prod_idx = spr->rx_std_prod_idx;
4853
4854                 /* Make sure updates to the rx_std_buffers[] entries and the
4855                  * standard producer index are seen in the correct order.
4856                  */
4857                 smp_rmb();
4858
4859                 if (spr->rx_std_cons_idx == src_prod_idx)
4860                         break;
4861
4862                 if (spr->rx_std_cons_idx < src_prod_idx)
4863                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4864                 else
4865                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4866
4867                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4868
4869                 si = spr->rx_std_cons_idx;
4870                 di = dpr->rx_std_prod_idx;
4871
4872                 for (i = di; i < di + cpycnt; i++) {
4873                         if (dpr->rx_std_buffers[i].skb) {
4874                                 cpycnt = i - di;
4875                                 err = -ENOSPC;
4876                                 break;
4877                         }
4878                 }
4879
4880                 if (!cpycnt)
4881                         break;
4882
4883                 /* Ensure that updates to the rx_std_buffers ring and the
4884                  * shadowed hardware producer ring from tg3_recycle_skb() are
4885                  * ordered correctly WRT the skb check above.
4886                  */
4887                 smp_rmb();
4888
4889                 memcpy(&dpr->rx_std_buffers[di],
4890                        &spr->rx_std_buffers[si],
4891                        cpycnt * sizeof(struct ring_info));
4892
4893                 for (i = 0; i < cpycnt; i++, di++, si++) {
4894                         struct tg3_rx_buffer_desc *sbd, *dbd;
4895                         sbd = &spr->rx_std[si];
4896                         dbd = &dpr->rx_std[di];
4897                         dbd->addr_hi = sbd->addr_hi;
4898                         dbd->addr_lo = sbd->addr_lo;
4899                 }
4900
4901                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4902                                        TG3_RX_RING_SIZE;
4903                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4904                                        TG3_RX_RING_SIZE;
4905         }
4906
4907         while (1) {
4908                 src_prod_idx = spr->rx_jmb_prod_idx;
4909
4910                 /* Make sure updates to the rx_jmb_buffers[] entries and
4911                  * the jumbo producer index are seen in the correct order.
4912                  */
4913                 smp_rmb();
4914
4915                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4916                         break;
4917
4918                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4919                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4920                 else
4921                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4922
4923                 cpycnt = min(cpycnt,
4924                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4925
4926                 si = spr->rx_jmb_cons_idx;
4927                 di = dpr->rx_jmb_prod_idx;
4928
4929                 for (i = di; i < di + cpycnt; i++) {
4930                         if (dpr->rx_jmb_buffers[i].skb) {
4931                                 cpycnt = i - di;
4932                                 err = -ENOSPC;
4933                                 break;
4934                         }
4935                 }
4936
4937                 if (!cpycnt)
4938                         break;
4939
4940                 /* Ensure that updates to the rx_jmb_buffers ring and the
4941                  * shadowed hardware producer ring from tg3_recycle_skb() are
4942                  * ordered correctly WRT the skb check above.
4943                  */
4944                 smp_rmb();
4945
4946                 memcpy(&dpr->rx_jmb_buffers[di],
4947                        &spr->rx_jmb_buffers[si],
4948                        cpycnt * sizeof(struct ring_info));
4949
4950                 for (i = 0; i < cpycnt; i++, di++, si++) {
4951                         struct tg3_rx_buffer_desc *sbd, *dbd;
4952                         sbd = &spr->rx_jmb[si].std;
4953                         dbd = &dpr->rx_jmb[di].std;
4954                         dbd->addr_hi = sbd->addr_hi;
4955                         dbd->addr_lo = sbd->addr_lo;
4956                 }
4957
4958                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4959                                        TG3_RX_JUMBO_RING_SIZE;
4960                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4961                                        TG3_RX_JUMBO_RING_SIZE;
4962         }
4963
4964         return err;
4965 }
4966
4967 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4968 {
4969         struct tg3 *tp = tnapi->tp;
4970
4971         /* run TX completion thread */
4972         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4973                 tg3_tx(tnapi);
4974                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4975                         return work_done;
4976         }
4977
4978         /* run RX thread, within the bounds set by NAPI.
4979          * All RX "locking" is done by ensuring outside
4980          * code synchronizes with tg3->napi.poll()
4981          */
4982         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4983                 work_done += tg3_rx(tnapi, budget - work_done);
4984
4985         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4986                 struct tg3_rx_prodring_set *dpr = &tp->prodring[0];
4987                 int i, err = 0;
4988                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4989                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4990
4991                 for (i = 1; i < tp->irq_cnt; i++)
4992                         err |= tg3_rx_prodring_xfer(tp, dpr,
4993                                                     tp->napi[i].prodring);
4994
4995                 wmb();
4996
4997                 if (std_prod_idx != dpr->rx_std_prod_idx)
4998                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4999                                      dpr->rx_std_prod_idx);
5000
5001                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5002                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5003                                      dpr->rx_jmb_prod_idx);
5004
5005                 mmiowb();
5006
5007                 if (err)
5008                         tw32_f(HOSTCC_MODE, tp->coal_now);
5009         }
5010
5011         return work_done;
5012 }
5013
5014 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5015 {
5016         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5017         struct tg3 *tp = tnapi->tp;
5018         int work_done = 0;
5019         struct tg3_hw_status *sblk = tnapi->hw_status;
5020
5021         while (1) {
5022                 work_done = tg3_poll_work(tnapi, work_done, budget);
5023
5024                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5025                         goto tx_recovery;
5026
5027                 if (unlikely(work_done >= budget))
5028                         break;
5029
5030                 /* tp->last_tag is used in tg3_int_reenable() below
5031                  * to tell the hw how much work has been processed,
5032                  * so we must read it before checking for more work.
5033                  */
5034                 tnapi->last_tag = sblk->status_tag;
5035                 tnapi->last_irq_tag = tnapi->last_tag;
5036                 rmb();
5037
5038                 /* check for RX/TX work to do */
5039                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5040                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5041                         napi_complete(napi);
5042                         /* Reenable interrupts. */
5043                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5044                         mmiowb();
5045                         break;
5046                 }
5047         }
5048
5049         return work_done;
5050
5051 tx_recovery:
5052         /* work_done is guaranteed to be less than budget. */
5053         napi_complete(napi);
5054         schedule_work(&tp->reset_task);
5055         return work_done;
5056 }
5057
5058 static int tg3_poll(struct napi_struct *napi, int budget)
5059 {
5060         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5061         struct tg3 *tp = tnapi->tp;
5062         int work_done = 0;
5063         struct tg3_hw_status *sblk = tnapi->hw_status;
5064
5065         while (1) {
5066                 tg3_poll_link(tp);
5067
5068                 work_done = tg3_poll_work(tnapi, work_done, budget);
5069
5070                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5071                         goto tx_recovery;
5072
5073                 if (unlikely(work_done >= budget))
5074                         break;
5075
5076                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5077                         /* tp->last_tag is used in tg3_int_reenable() below
5078                          * to tell the hw how much work has been processed,
5079                          * so we must read it before checking for more work.
5080                          */
5081                         tnapi->last_tag = sblk->status_tag;
5082                         tnapi->last_irq_tag = tnapi->last_tag;
5083                         rmb();
5084                 } else
5085                         sblk->status &= ~SD_STATUS_UPDATED;
5086
5087                 if (likely(!tg3_has_work(tnapi))) {
5088                         napi_complete(napi);
5089                         tg3_int_reenable(tnapi);
5090                         break;
5091                 }
5092         }
5093
5094         return work_done;
5095
5096 tx_recovery:
5097         /* work_done is guaranteed to be less than budget. */
5098         napi_complete(napi);
5099         schedule_work(&tp->reset_task);
5100         return work_done;
5101 }
5102
5103 static void tg3_irq_quiesce(struct tg3 *tp)
5104 {
5105         int i;
5106
5107         BUG_ON(tp->irq_sync);
5108
5109         tp->irq_sync = 1;
5110         smp_mb();
5111
5112         for (i = 0; i < tp->irq_cnt; i++)
5113                 synchronize_irq(tp->napi[i].irq_vec);
5114 }
5115
5116 static inline int tg3_irq_sync(struct tg3 *tp)
5117 {
5118         return tp->irq_sync;
5119 }
5120
5121 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5122  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5123  * with as well.  Most of the time, this is not necessary except when
5124  * shutting down the device.
5125  */
5126 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5127 {
5128         spin_lock_bh(&tp->lock);
5129         if (irq_sync)
5130                 tg3_irq_quiesce(tp);
5131 }
5132
5133 static inline void tg3_full_unlock(struct tg3 *tp)
5134 {
5135         spin_unlock_bh(&tp->lock);
5136 }
5137
5138 /* One-shot MSI handler - Chip automatically disables interrupt
5139  * after sending MSI so driver doesn't have to do it.
5140  */
5141 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5142 {
5143         struct tg3_napi *tnapi = dev_id;
5144         struct tg3 *tp = tnapi->tp;
5145
5146         prefetch(tnapi->hw_status);
5147         if (tnapi->rx_rcb)
5148                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5149
5150         if (likely(!tg3_irq_sync(tp)))
5151                 napi_schedule(&tnapi->napi);
5152
5153         return IRQ_HANDLED;
5154 }
5155
5156 /* MSI ISR - No need to check for interrupt sharing and no need to
5157  * flush status block and interrupt mailbox. PCI ordering rules
5158  * guarantee that MSI will arrive after the status block.
5159  */
5160 static irqreturn_t tg3_msi(int irq, void *dev_id)
5161 {
5162         struct tg3_napi *tnapi = dev_id;
5163         struct tg3 *tp = tnapi->tp;
5164
5165         prefetch(tnapi->hw_status);
5166         if (tnapi->rx_rcb)
5167                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5168         /*
5169          * Writing any value to intr-mbox-0 clears PCI INTA# and
5170          * chip-internal interrupt pending events.
5171          * Writing non-zero to intr-mbox-0 additional tells the
5172          * NIC to stop sending us irqs, engaging "in-intr-handler"
5173          * event coalescing.
5174          */
5175         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5176         if (likely(!tg3_irq_sync(tp)))
5177                 napi_schedule(&tnapi->napi);
5178
5179         return IRQ_RETVAL(1);
5180 }
5181
5182 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5183 {
5184         struct tg3_napi *tnapi = dev_id;
5185         struct tg3 *tp = tnapi->tp;
5186         struct tg3_hw_status *sblk = tnapi->hw_status;
5187         unsigned int handled = 1;
5188
5189         /* In INTx mode, it is possible for the interrupt to arrive at
5190          * the CPU before the status block posted prior to the interrupt.
5191          * Reading the PCI State register will confirm whether the
5192          * interrupt is ours and will flush the status block.
5193          */
5194         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5195                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5196                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5197                         handled = 0;
5198                         goto out;
5199                 }
5200         }
5201
5202         /*
5203          * Writing any value to intr-mbox-0 clears PCI INTA# and
5204          * chip-internal interrupt pending events.
5205          * Writing non-zero to intr-mbox-0 additional tells the
5206          * NIC to stop sending us irqs, engaging "in-intr-handler"
5207          * event coalescing.
5208          *
5209          * Flush the mailbox to de-assert the IRQ immediately to prevent
5210          * spurious interrupts.  The flush impacts performance but
5211          * excessive spurious interrupts can be worse in some cases.
5212          */
5213         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5214         if (tg3_irq_sync(tp))
5215                 goto out;
5216         sblk->status &= ~SD_STATUS_UPDATED;
5217         if (likely(tg3_has_work(tnapi))) {
5218                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5219                 napi_schedule(&tnapi->napi);
5220         } else {
5221                 /* No work, shared interrupt perhaps?  re-enable
5222                  * interrupts, and flush that PCI write
5223                  */
5224                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5225                                0x00000000);
5226         }
5227 out:
5228         return IRQ_RETVAL(handled);
5229 }
5230
5231 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5232 {
5233         struct tg3_napi *tnapi = dev_id;
5234         struct tg3 *tp = tnapi->tp;
5235         struct tg3_hw_status *sblk = tnapi->hw_status;
5236         unsigned int handled = 1;
5237
5238         /* In INTx mode, it is possible for the interrupt to arrive at
5239          * the CPU before the status block posted prior to the interrupt.
5240          * Reading the PCI State register will confirm whether the
5241          * interrupt is ours and will flush the status block.
5242          */
5243         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5244                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5245                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5246                         handled = 0;
5247                         goto out;
5248                 }
5249         }
5250
5251         /*
5252          * writing any value to intr-mbox-0 clears PCI INTA# and
5253          * chip-internal interrupt pending events.
5254          * writing non-zero to intr-mbox-0 additional tells the
5255          * NIC to stop sending us irqs, engaging "in-intr-handler"
5256          * event coalescing.
5257          *
5258          * Flush the mailbox to de-assert the IRQ immediately to prevent
5259          * spurious interrupts.  The flush impacts performance but
5260          * excessive spurious interrupts can be worse in some cases.
5261          */
5262         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5263
5264         /*
5265          * In a shared interrupt configuration, sometimes other devices'
5266          * interrupts will scream.  We record the current status tag here
5267          * so that the above check can report that the screaming interrupts
5268          * are unhandled.  Eventually they will be silenced.
5269          */
5270         tnapi->last_irq_tag = sblk->status_tag;
5271
5272         if (tg3_irq_sync(tp))
5273                 goto out;
5274
5275         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5276
5277         napi_schedule(&tnapi->napi);
5278
5279 out:
5280         return IRQ_RETVAL(handled);
5281 }
5282
5283 /* ISR for interrupt test */
5284 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5285 {
5286         struct tg3_napi *tnapi = dev_id;
5287         struct tg3 *tp = tnapi->tp;
5288         struct tg3_hw_status *sblk = tnapi->hw_status;
5289
5290         if ((sblk->status & SD_STATUS_UPDATED) ||
5291             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5292                 tg3_disable_ints(tp);
5293                 return IRQ_RETVAL(1);
5294         }
5295         return IRQ_RETVAL(0);
5296 }
5297
5298 static int tg3_init_hw(struct tg3 *, int);
5299 static int tg3_halt(struct tg3 *, int, int);
5300
5301 /* Restart hardware after configuration changes, self-test, etc.
5302  * Invoked with tp->lock held.
5303  */
5304 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5305         __releases(tp->lock)
5306         __acquires(tp->lock)
5307 {
5308         int err;
5309
5310         err = tg3_init_hw(tp, reset_phy);
5311         if (err) {
5312                 netdev_err(tp->dev,
5313                            "Failed to re-initialize device, aborting\n");
5314                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5315                 tg3_full_unlock(tp);
5316                 del_timer_sync(&tp->timer);
5317                 tp->irq_sync = 0;
5318                 tg3_napi_enable(tp);
5319                 dev_close(tp->dev);
5320                 tg3_full_lock(tp, 0);
5321         }
5322         return err;
5323 }
5324
5325 #ifdef CONFIG_NET_POLL_CONTROLLER
5326 static void tg3_poll_controller(struct net_device *dev)
5327 {
5328         int i;
5329         struct tg3 *tp = netdev_priv(dev);
5330
5331         for (i = 0; i < tp->irq_cnt; i++)
5332                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5333 }
5334 #endif
5335
5336 static void tg3_reset_task(struct work_struct *work)
5337 {
5338         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5339         int err;
5340         unsigned int restart_timer;
5341
5342         tg3_full_lock(tp, 0);
5343
5344         if (!netif_running(tp->dev)) {
5345                 tg3_full_unlock(tp);
5346                 return;
5347         }
5348
5349         tg3_full_unlock(tp);
5350
5351         tg3_phy_stop(tp);
5352
5353         tg3_netif_stop(tp);
5354
5355         tg3_full_lock(tp, 1);
5356
5357         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5358         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5359
5360         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5361                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5362                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5363                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5364                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5365         }
5366
5367         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5368         err = tg3_init_hw(tp, 1);
5369         if (err)
5370                 goto out;
5371
5372         tg3_netif_start(tp);
5373
5374         if (restart_timer)
5375                 mod_timer(&tp->timer, jiffies + 1);
5376
5377 out:
5378         tg3_full_unlock(tp);
5379
5380         if (!err)
5381                 tg3_phy_start(tp);
5382 }
5383
5384 static void tg3_dump_short_state(struct tg3 *tp)
5385 {
5386         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5387                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5388         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5389                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5390 }
5391
5392 static void tg3_tx_timeout(struct net_device *dev)
5393 {
5394         struct tg3 *tp = netdev_priv(dev);
5395
5396         if (netif_msg_tx_err(tp)) {
5397                 netdev_err(dev, "transmit timed out, resetting\n");
5398                 tg3_dump_short_state(tp);
5399         }
5400
5401         schedule_work(&tp->reset_task);
5402 }
5403
5404 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5405 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5406 {
5407         u32 base = (u32) mapping & 0xffffffff;
5408
5409         return ((base > 0xffffdcc0) &&
5410                 (base + len + 8 < base));
5411 }
5412
5413 /* Test for DMA addresses > 40-bit */
5414 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5415                                           int len)
5416 {
5417 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5418         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5419                 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5420         return 0;
5421 #else
5422         return 0;
5423 #endif
5424 }
5425
5426 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5427
5428 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5429 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5430                                        struct sk_buff *skb, u32 last_plus_one,
5431                                        u32 *start, u32 base_flags, u32 mss)
5432 {
5433         struct tg3 *tp = tnapi->tp;
5434         struct sk_buff *new_skb;
5435         dma_addr_t new_addr = 0;
5436         u32 entry = *start;
5437         int i, ret = 0;
5438
5439         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5440                 new_skb = skb_copy(skb, GFP_ATOMIC);
5441         else {
5442                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5443
5444                 new_skb = skb_copy_expand(skb,
5445                                           skb_headroom(skb) + more_headroom,
5446                                           skb_tailroom(skb), GFP_ATOMIC);
5447         }
5448
5449         if (!new_skb) {
5450                 ret = -1;
5451         } else {
5452                 /* New SKB is guaranteed to be linear. */
5453                 entry = *start;
5454                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5455                                           PCI_DMA_TODEVICE);
5456                 /* Make sure the mapping succeeded */
5457                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5458                         ret = -1;
5459                         dev_kfree_skb(new_skb);
5460                         new_skb = NULL;
5461
5462                 /* Make sure new skb does not cross any 4G boundaries.
5463                  * Drop the packet if it does.
5464                  */
5465                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5466                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5467                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5468                                          PCI_DMA_TODEVICE);
5469                         ret = -1;
5470                         dev_kfree_skb(new_skb);
5471                         new_skb = NULL;
5472                 } else {
5473                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5474                                     base_flags, 1 | (mss << 1));
5475                         *start = NEXT_TX(entry);
5476                 }
5477         }
5478
5479         /* Now clean up the sw ring entries. */
5480         i = 0;
5481         while (entry != last_plus_one) {
5482                 int len;
5483
5484                 if (i == 0)
5485                         len = skb_headlen(skb);
5486                 else
5487                         len = skb_shinfo(skb)->frags[i-1].size;
5488
5489                 pci_unmap_single(tp->pdev,
5490                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5491                                                 mapping),
5492                                  len, PCI_DMA_TODEVICE);
5493                 if (i == 0) {
5494                         tnapi->tx_buffers[entry].skb = new_skb;
5495                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5496                                            new_addr);
5497                 } else {
5498                         tnapi->tx_buffers[entry].skb = NULL;
5499                 }
5500                 entry = NEXT_TX(entry);
5501                 i++;
5502         }
5503
5504         dev_kfree_skb(skb);
5505
5506         return ret;
5507 }
5508
5509 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5510                         dma_addr_t mapping, int len, u32 flags,
5511                         u32 mss_and_is_end)
5512 {
5513         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5514         int is_end = (mss_and_is_end & 0x1);
5515         u32 mss = (mss_and_is_end >> 1);
5516         u32 vlan_tag = 0;
5517
5518         if (is_end)
5519                 flags |= TXD_FLAG_END;
5520         if (flags & TXD_FLAG_VLAN) {
5521                 vlan_tag = flags >> 16;
5522                 flags &= 0xffff;
5523         }
5524         vlan_tag |= (mss << TXD_MSS_SHIFT);
5525
5526         txd->addr_hi = ((u64) mapping >> 32);
5527         txd->addr_lo = ((u64) mapping & 0xffffffff);
5528         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5529         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5530 }
5531
5532 /* hard_start_xmit for devices that don't have any bugs and
5533  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5534  */
5535 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5536                                   struct net_device *dev)
5537 {
5538         struct tg3 *tp = netdev_priv(dev);
5539         u32 len, entry, base_flags, mss;
5540         dma_addr_t mapping;
5541         struct tg3_napi *tnapi;
5542         struct netdev_queue *txq;
5543         unsigned int i, last;
5544
5545         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5546         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5547         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5548                 tnapi++;
5549
5550         /* We are running in BH disabled context with netif_tx_lock
5551          * and TX reclaim runs via tp->napi.poll inside of a software
5552          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5553          * no IRQ context deadlocks to worry about either.  Rejoice!
5554          */
5555         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5556                 if (!netif_tx_queue_stopped(txq)) {
5557                         netif_tx_stop_queue(txq);
5558
5559                         /* This is a hard error, log it. */
5560                         netdev_err(dev,
5561                                    "BUG! Tx Ring full when queue awake!\n");
5562                 }
5563                 return NETDEV_TX_BUSY;
5564         }
5565
5566         entry = tnapi->tx_prod;
5567         base_flags = 0;
5568         mss = 0;
5569         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5570                 int tcp_opt_len, ip_tcp_len;
5571                 u32 hdrlen;
5572
5573                 if (skb_header_cloned(skb) &&
5574                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5575                         dev_kfree_skb(skb);
5576                         goto out_unlock;
5577                 }
5578
5579                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5580                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5581                 else {
5582                         struct iphdr *iph = ip_hdr(skb);
5583
5584                         tcp_opt_len = tcp_optlen(skb);
5585                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5586
5587                         iph->check = 0;
5588                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5589                         hdrlen = ip_tcp_len + tcp_opt_len;
5590                 }
5591
5592                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5593                         mss |= (hdrlen & 0xc) << 12;
5594                         if (hdrlen & 0x10)
5595                                 base_flags |= 0x00000010;
5596                         base_flags |= (hdrlen & 0x3e0) << 5;
5597                 } else
5598                         mss |= hdrlen << 9;
5599
5600                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5601                                TXD_FLAG_CPU_POST_DMA);
5602
5603                 tcp_hdr(skb)->check = 0;
5604
5605         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5606                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5607         }
5608
5609 #if TG3_VLAN_TAG_USED
5610         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5611                 base_flags |= (TXD_FLAG_VLAN |
5612                                (vlan_tx_tag_get(skb) << 16));
5613 #endif
5614
5615         len = skb_headlen(skb);
5616
5617         /* Queue skb data, a.k.a. the main skb fragment. */
5618         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5619         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5620                 dev_kfree_skb(skb);
5621                 goto out_unlock;
5622         }
5623
5624         tnapi->tx_buffers[entry].skb = skb;
5625         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5626
5627         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5628             !mss && skb->len > ETH_DATA_LEN)
5629                 base_flags |= TXD_FLAG_JMB_PKT;
5630
5631         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5632                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5633
5634         entry = NEXT_TX(entry);
5635
5636         /* Now loop through additional data fragments, and queue them. */
5637         if (skb_shinfo(skb)->nr_frags > 0) {
5638                 last = skb_shinfo(skb)->nr_frags - 1;
5639                 for (i = 0; i <= last; i++) {
5640                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5641
5642                         len = frag->size;
5643                         mapping = pci_map_page(tp->pdev,
5644                                                frag->page,
5645                                                frag->page_offset,
5646                                                len, PCI_DMA_TODEVICE);
5647                         if (pci_dma_mapping_error(tp->pdev, mapping))
5648                                 goto dma_error;
5649
5650                         tnapi->tx_buffers[entry].skb = NULL;
5651                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5652                                            mapping);
5653
5654                         tg3_set_txd(tnapi, entry, mapping, len,
5655                                     base_flags, (i == last) | (mss << 1));
5656
5657                         entry = NEXT_TX(entry);
5658                 }
5659         }
5660
5661         /* Packets are ready, update Tx producer idx local and on card. */
5662         tw32_tx_mbox(tnapi->prodmbox, entry);
5663
5664         tnapi->tx_prod = entry;
5665         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5666                 netif_tx_stop_queue(txq);
5667                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5668                         netif_tx_wake_queue(txq);
5669         }
5670
5671 out_unlock:
5672         mmiowb();
5673
5674         return NETDEV_TX_OK;
5675
5676 dma_error:
5677         last = i;
5678         entry = tnapi->tx_prod;
5679         tnapi->tx_buffers[entry].skb = NULL;
5680         pci_unmap_single(tp->pdev,
5681                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5682                          skb_headlen(skb),
5683                          PCI_DMA_TODEVICE);
5684         for (i = 0; i <= last; i++) {
5685                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5686                 entry = NEXT_TX(entry);
5687
5688                 pci_unmap_page(tp->pdev,
5689                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5690                                               mapping),
5691                                frag->size, PCI_DMA_TODEVICE);
5692         }
5693
5694         dev_kfree_skb(skb);
5695         return NETDEV_TX_OK;
5696 }
5697
5698 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5699                                           struct net_device *);
5700
5701 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5702  * TSO header is greater than 80 bytes.
5703  */
5704 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5705 {
5706         struct sk_buff *segs, *nskb;
5707         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5708
5709         /* Estimate the number of fragments in the worst case */
5710         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5711                 netif_stop_queue(tp->dev);
5712                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5713                         return NETDEV_TX_BUSY;
5714
5715                 netif_wake_queue(tp->dev);
5716         }
5717
5718         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5719         if (IS_ERR(segs))
5720                 goto tg3_tso_bug_end;
5721
5722         do {
5723                 nskb = segs;
5724                 segs = segs->next;
5725                 nskb->next = NULL;
5726                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5727         } while (segs);
5728
5729 tg3_tso_bug_end:
5730         dev_kfree_skb(skb);
5731
5732         return NETDEV_TX_OK;
5733 }
5734
5735 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5736  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5737  */
5738 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5739                                           struct net_device *dev)
5740 {
5741         struct tg3 *tp = netdev_priv(dev);
5742         u32 len, entry, base_flags, mss;
5743         int would_hit_hwbug;
5744         dma_addr_t mapping;
5745         struct tg3_napi *tnapi;
5746         struct netdev_queue *txq;
5747         unsigned int i, last;
5748
5749         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5750         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5751         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5752                 tnapi++;
5753
5754         /* We are running in BH disabled context with netif_tx_lock
5755          * and TX reclaim runs via tp->napi.poll inside of a software
5756          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5757          * no IRQ context deadlocks to worry about either.  Rejoice!
5758          */
5759         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5760                 if (!netif_tx_queue_stopped(txq)) {
5761                         netif_tx_stop_queue(txq);
5762
5763                         /* This is a hard error, log it. */
5764                         netdev_err(dev,
5765                                    "BUG! Tx Ring full when queue awake!\n");
5766                 }
5767                 return NETDEV_TX_BUSY;
5768         }
5769
5770         entry = tnapi->tx_prod;
5771         base_flags = 0;
5772         if (skb->ip_summed == CHECKSUM_PARTIAL)
5773                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5774
5775         if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5776                 struct iphdr *iph;
5777                 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5778
5779                 if (skb_header_cloned(skb) &&
5780                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5781                         dev_kfree_skb(skb);
5782                         goto out_unlock;
5783                 }
5784
5785                 tcp_opt_len = tcp_optlen(skb);
5786                 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5787
5788                 hdr_len = ip_tcp_len + tcp_opt_len;
5789                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5790                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5791                         return tg3_tso_bug(tp, skb);
5792
5793                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5794                                TXD_FLAG_CPU_POST_DMA);
5795
5796                 iph = ip_hdr(skb);
5797                 iph->check = 0;
5798                 iph->tot_len = htons(mss + hdr_len);
5799                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5800                         tcp_hdr(skb)->check = 0;
5801                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5802                 } else
5803                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5804                                                                  iph->daddr, 0,
5805                                                                  IPPROTO_TCP,
5806                                                                  0);
5807
5808                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5809                         mss |= (hdr_len & 0xc) << 12;
5810                         if (hdr_len & 0x10)
5811                                 base_flags |= 0x00000010;
5812                         base_flags |= (hdr_len & 0x3e0) << 5;
5813                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5814                         mss |= hdr_len << 9;
5815                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5816                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5817                         if (tcp_opt_len || iph->ihl > 5) {
5818                                 int tsflags;
5819
5820                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5821                                 mss |= (tsflags << 11);
5822                         }
5823                 } else {
5824                         if (tcp_opt_len || iph->ihl > 5) {
5825                                 int tsflags;
5826
5827                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5828                                 base_flags |= tsflags << 12;
5829                         }
5830                 }
5831         }
5832 #if TG3_VLAN_TAG_USED
5833         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5834                 base_flags |= (TXD_FLAG_VLAN |
5835                                (vlan_tx_tag_get(skb) << 16));
5836 #endif
5837
5838         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5839             !mss && skb->len > ETH_DATA_LEN)
5840                 base_flags |= TXD_FLAG_JMB_PKT;
5841
5842         len = skb_headlen(skb);
5843
5844         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5845         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5846                 dev_kfree_skb(skb);
5847                 goto out_unlock;
5848         }
5849
5850         tnapi->tx_buffers[entry].skb = skb;
5851         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5852
5853         would_hit_hwbug = 0;
5854
5855         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5856                 would_hit_hwbug = 1;
5857
5858         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5859             tg3_4g_overflow_test(mapping, len))
5860                 would_hit_hwbug = 1;
5861
5862         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5863             tg3_40bit_overflow_test(tp, mapping, len))
5864                 would_hit_hwbug = 1;
5865
5866         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5867                 would_hit_hwbug = 1;
5868
5869         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5870                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5871
5872         entry = NEXT_TX(entry);
5873
5874         /* Now loop through additional data fragments, and queue them. */
5875         if (skb_shinfo(skb)->nr_frags > 0) {
5876                 last = skb_shinfo(skb)->nr_frags - 1;
5877                 for (i = 0; i <= last; i++) {
5878                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5879
5880                         len = frag->size;
5881                         mapping = pci_map_page(tp->pdev,
5882                                                frag->page,
5883                                                frag->page_offset,
5884                                                len, PCI_DMA_TODEVICE);
5885
5886                         tnapi->tx_buffers[entry].skb = NULL;
5887                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5888                                            mapping);
5889                         if (pci_dma_mapping_error(tp->pdev, mapping))
5890                                 goto dma_error;
5891
5892                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5893                             len <= 8)
5894                                 would_hit_hwbug = 1;
5895
5896                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5897                             tg3_4g_overflow_test(mapping, len))
5898                                 would_hit_hwbug = 1;
5899
5900                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5901                             tg3_40bit_overflow_test(tp, mapping, len))
5902                                 would_hit_hwbug = 1;
5903
5904                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5905                                 tg3_set_txd(tnapi, entry, mapping, len,
5906                                             base_flags, (i == last)|(mss << 1));
5907                         else
5908                                 tg3_set_txd(tnapi, entry, mapping, len,
5909                                             base_flags, (i == last));
5910
5911                         entry = NEXT_TX(entry);
5912                 }
5913         }
5914
5915         if (would_hit_hwbug) {
5916                 u32 last_plus_one = entry;
5917                 u32 start;
5918
5919                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5920                 start &= (TG3_TX_RING_SIZE - 1);
5921
5922                 /* If the workaround fails due to memory/mapping
5923                  * failure, silently drop this packet.
5924                  */
5925                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5926                                                 &start, base_flags, mss))
5927                         goto out_unlock;
5928
5929                 entry = start;
5930         }
5931
5932         /* Packets are ready, update Tx producer idx local and on card. */
5933         tw32_tx_mbox(tnapi->prodmbox, entry);
5934
5935         tnapi->tx_prod = entry;
5936         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5937                 netif_tx_stop_queue(txq);
5938                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5939                         netif_tx_wake_queue(txq);
5940         }
5941
5942 out_unlock:
5943         mmiowb();
5944
5945         return NETDEV_TX_OK;
5946
5947 dma_error:
5948         last = i;
5949         entry = tnapi->tx_prod;
5950         tnapi->tx_buffers[entry].skb = NULL;
5951         pci_unmap_single(tp->pdev,
5952                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5953                          skb_headlen(skb),
5954                          PCI_DMA_TODEVICE);
5955         for (i = 0; i <= last; i++) {
5956                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5957                 entry = NEXT_TX(entry);
5958
5959                 pci_unmap_page(tp->pdev,
5960                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5961                                               mapping),
5962                                frag->size, PCI_DMA_TODEVICE);
5963         }
5964
5965         dev_kfree_skb(skb);
5966         return NETDEV_TX_OK;
5967 }
5968
5969 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5970                                int new_mtu)
5971 {
5972         dev->mtu = new_mtu;
5973
5974         if (new_mtu > ETH_DATA_LEN) {
5975                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5976                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5977                         ethtool_op_set_tso(dev, 0);
5978                 } else {
5979                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5980                 }
5981         } else {
5982                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5983                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5984                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5985         }
5986 }
5987
5988 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5989 {
5990         struct tg3 *tp = netdev_priv(dev);
5991         int err;
5992
5993         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5994                 return -EINVAL;
5995
5996         if (!netif_running(dev)) {
5997                 /* We'll just catch it later when the
5998                  * device is up'd.
5999                  */
6000                 tg3_set_mtu(dev, tp, new_mtu);
6001                 return 0;
6002         }
6003
6004         tg3_phy_stop(tp);
6005
6006         tg3_netif_stop(tp);
6007
6008         tg3_full_lock(tp, 1);
6009
6010         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6011
6012         tg3_set_mtu(dev, tp, new_mtu);
6013
6014         err = tg3_restart_hw(tp, 0);
6015
6016         if (!err)
6017                 tg3_netif_start(tp);
6018
6019         tg3_full_unlock(tp);
6020
6021         if (!err)
6022                 tg3_phy_start(tp);
6023
6024         return err;
6025 }
6026
6027 static void tg3_rx_prodring_free(struct tg3 *tp,
6028                                  struct tg3_rx_prodring_set *tpr)
6029 {
6030         int i;
6031
6032         if (tpr != &tp->prodring[0]) {
6033                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6034                      i = (i + 1) % TG3_RX_RING_SIZE)
6035                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6036                                         tp->rx_pkt_map_sz);
6037
6038                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6039                         for (i = tpr->rx_jmb_cons_idx;
6040                              i != tpr->rx_jmb_prod_idx;
6041                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6042                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6043                                                 TG3_RX_JMB_MAP_SZ);
6044                         }
6045                 }
6046
6047                 return;
6048         }
6049
6050         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6051                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6052                                 tp->rx_pkt_map_sz);
6053
6054         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6055                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6056                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6057                                         TG3_RX_JMB_MAP_SZ);
6058         }
6059 }
6060
6061 /* Initialize rx rings for packet processing.
6062  *
6063  * The chip has been shut down and the driver detached from
6064  * the networking, so no interrupts or new tx packets will
6065  * end up in the driver.  tp->{tx,}lock are held and thus
6066  * we may not sleep.
6067  */
6068 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6069                                  struct tg3_rx_prodring_set *tpr)
6070 {
6071         u32 i, rx_pkt_dma_sz;
6072
6073         tpr->rx_std_cons_idx = 0;
6074         tpr->rx_std_prod_idx = 0;
6075         tpr->rx_jmb_cons_idx = 0;
6076         tpr->rx_jmb_prod_idx = 0;
6077
6078         if (tpr != &tp->prodring[0]) {
6079                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6080                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6081                         memset(&tpr->rx_jmb_buffers[0], 0,
6082                                TG3_RX_JMB_BUFF_RING_SIZE);
6083                 goto done;
6084         }
6085
6086         /* Zero out all descriptors. */
6087         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6088
6089         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6090         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6091             tp->dev->mtu > ETH_DATA_LEN)
6092                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6093         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6094
6095         /* Initialize invariants of the rings, we only set this
6096          * stuff once.  This works because the card does not
6097          * write into the rx buffer posting rings.
6098          */
6099         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6100                 struct tg3_rx_buffer_desc *rxd;
6101
6102                 rxd = &tpr->rx_std[i];
6103                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6104                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6105                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6106                                (i << RXD_OPAQUE_INDEX_SHIFT));
6107         }
6108
6109         /* Now allocate fresh SKBs for each rx ring. */
6110         for (i = 0; i < tp->rx_pending; i++) {
6111                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6112                         netdev_warn(tp->dev,
6113                                     "Using a smaller RX standard ring. Only "
6114                                     "%d out of %d buffers were allocated "
6115                                     "successfully\n", i, tp->rx_pending);
6116                         if (i == 0)
6117                                 goto initfail;
6118                         tp->rx_pending = i;
6119                         break;
6120                 }
6121         }
6122
6123         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6124                 goto done;
6125
6126         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6127
6128         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6129                 goto done;
6130
6131         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6132                 struct tg3_rx_buffer_desc *rxd;
6133
6134                 rxd = &tpr->rx_jmb[i].std;
6135                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6136                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6137                                   RXD_FLAG_JUMBO;
6138                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6139                        (i << RXD_OPAQUE_INDEX_SHIFT));
6140         }
6141
6142         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6143                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6144                         netdev_warn(tp->dev,
6145                                     "Using a smaller RX jumbo ring. Only %d "
6146                                     "out of %d buffers were allocated "
6147                                     "successfully\n", i, tp->rx_jumbo_pending);
6148                         if (i == 0)
6149                                 goto initfail;
6150                         tp->rx_jumbo_pending = i;
6151                         break;
6152                 }
6153         }
6154
6155 done:
6156         return 0;
6157
6158 initfail:
6159         tg3_rx_prodring_free(tp, tpr);
6160         return -ENOMEM;
6161 }
6162
6163 static void tg3_rx_prodring_fini(struct tg3 *tp,
6164                                  struct tg3_rx_prodring_set *tpr)
6165 {
6166         kfree(tpr->rx_std_buffers);
6167         tpr->rx_std_buffers = NULL;
6168         kfree(tpr->rx_jmb_buffers);
6169         tpr->rx_jmb_buffers = NULL;
6170         if (tpr->rx_std) {
6171                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6172                                     tpr->rx_std, tpr->rx_std_mapping);
6173                 tpr->rx_std = NULL;
6174         }
6175         if (tpr->rx_jmb) {
6176                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6177                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6178                 tpr->rx_jmb = NULL;
6179         }
6180 }
6181
6182 static int tg3_rx_prodring_init(struct tg3 *tp,
6183                                 struct tg3_rx_prodring_set *tpr)
6184 {
6185         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6186         if (!tpr->rx_std_buffers)
6187                 return -ENOMEM;
6188
6189         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6190                                            &tpr->rx_std_mapping);
6191         if (!tpr->rx_std)
6192                 goto err_out;
6193
6194         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6195                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6196                                               GFP_KERNEL);
6197                 if (!tpr->rx_jmb_buffers)
6198                         goto err_out;
6199
6200                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6201                                                    TG3_RX_JUMBO_RING_BYTES,
6202                                                    &tpr->rx_jmb_mapping);
6203                 if (!tpr->rx_jmb)
6204                         goto err_out;
6205         }
6206
6207         return 0;
6208
6209 err_out:
6210         tg3_rx_prodring_fini(tp, tpr);
6211         return -ENOMEM;
6212 }
6213
6214 /* Free up pending packets in all rx/tx rings.
6215  *
6216  * The chip has been shut down and the driver detached from
6217  * the networking, so no interrupts or new tx packets will
6218  * end up in the driver.  tp->{tx,}lock is not held and we are not
6219  * in an interrupt context and thus may sleep.
6220  */
6221 static void tg3_free_rings(struct tg3 *tp)
6222 {
6223         int i, j;
6224
6225         for (j = 0; j < tp->irq_cnt; j++) {
6226                 struct tg3_napi *tnapi = &tp->napi[j];
6227
6228                 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6229
6230                 if (!tnapi->tx_buffers)
6231                         continue;
6232
6233                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6234                         struct ring_info *txp;
6235                         struct sk_buff *skb;
6236                         unsigned int k;
6237
6238                         txp = &tnapi->tx_buffers[i];
6239                         skb = txp->skb;
6240
6241                         if (skb == NULL) {
6242                                 i++;
6243                                 continue;
6244                         }
6245
6246                         pci_unmap_single(tp->pdev,
6247                                          dma_unmap_addr(txp, mapping),
6248                                          skb_headlen(skb),
6249                                          PCI_DMA_TODEVICE);
6250                         txp->skb = NULL;
6251
6252                         i++;
6253
6254                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6255                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6256                                 pci_unmap_page(tp->pdev,
6257                                                dma_unmap_addr(txp, mapping),
6258                                                skb_shinfo(skb)->frags[k].size,
6259                                                PCI_DMA_TODEVICE);
6260                                 i++;
6261                         }
6262
6263                         dev_kfree_skb_any(skb);
6264                 }
6265         }
6266 }
6267
6268 /* Initialize tx/rx rings for packet processing.
6269  *
6270  * The chip has been shut down and the driver detached from
6271  * the networking, so no interrupts or new tx packets will
6272  * end up in the driver.  tp->{tx,}lock are held and thus
6273  * we may not sleep.
6274  */
6275 static int tg3_init_rings(struct tg3 *tp)
6276 {
6277         int i;
6278
6279         /* Free up all the SKBs. */
6280         tg3_free_rings(tp);
6281
6282         for (i = 0; i < tp->irq_cnt; i++) {
6283                 struct tg3_napi *tnapi = &tp->napi[i];
6284
6285                 tnapi->last_tag = 0;
6286                 tnapi->last_irq_tag = 0;
6287                 tnapi->hw_status->status = 0;
6288                 tnapi->hw_status->status_tag = 0;
6289                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6290
6291                 tnapi->tx_prod = 0;
6292                 tnapi->tx_cons = 0;
6293                 if (tnapi->tx_ring)
6294                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6295
6296                 tnapi->rx_rcb_ptr = 0;
6297                 if (tnapi->rx_rcb)
6298                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6299
6300                 if (tg3_rx_prodring_alloc(tp, &tp->prodring[i])) {
6301                         tg3_free_rings(tp);
6302                         return -ENOMEM;
6303                 }
6304         }
6305
6306         return 0;
6307 }
6308
6309 /*
6310  * Must not be invoked with interrupt sources disabled and
6311  * the hardware shutdown down.
6312  */
6313 static void tg3_free_consistent(struct tg3 *tp)
6314 {
6315         int i;
6316
6317         for (i = 0; i < tp->irq_cnt; i++) {
6318                 struct tg3_napi *tnapi = &tp->napi[i];
6319
6320                 if (tnapi->tx_ring) {
6321                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6322                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6323                         tnapi->tx_ring = NULL;
6324                 }
6325
6326                 kfree(tnapi->tx_buffers);
6327                 tnapi->tx_buffers = NULL;
6328
6329                 if (tnapi->rx_rcb) {
6330                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6331                                             tnapi->rx_rcb,
6332                                             tnapi->rx_rcb_mapping);
6333                         tnapi->rx_rcb = NULL;
6334                 }
6335
6336                 if (tnapi->hw_status) {
6337                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6338                                             tnapi->hw_status,
6339                                             tnapi->status_mapping);
6340                         tnapi->hw_status = NULL;
6341                 }
6342         }
6343
6344         if (tp->hw_stats) {
6345                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6346                                     tp->hw_stats, tp->stats_mapping);
6347                 tp->hw_stats = NULL;
6348         }
6349
6350         for (i = 0; i < tp->irq_cnt; i++)
6351                 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6352 }
6353
6354 /*
6355  * Must not be invoked with interrupt sources disabled and
6356  * the hardware shutdown down.  Can sleep.
6357  */
6358 static int tg3_alloc_consistent(struct tg3 *tp)
6359 {
6360         int i;
6361
6362         for (i = 0; i < tp->irq_cnt; i++) {
6363                 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6364                         goto err_out;
6365         }
6366
6367         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6368                                             sizeof(struct tg3_hw_stats),
6369                                             &tp->stats_mapping);
6370         if (!tp->hw_stats)
6371                 goto err_out;
6372
6373         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6374
6375         for (i = 0; i < tp->irq_cnt; i++) {
6376                 struct tg3_napi *tnapi = &tp->napi[i];
6377                 struct tg3_hw_status *sblk;
6378
6379                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6380                                                         TG3_HW_STATUS_SIZE,
6381                                                         &tnapi->status_mapping);
6382                 if (!tnapi->hw_status)
6383                         goto err_out;
6384
6385                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6386                 sblk = tnapi->hw_status;
6387
6388                 /* If multivector TSS is enabled, vector 0 does not handle
6389                  * tx interrupts.  Don't allocate any resources for it.
6390                  */
6391                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6392                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6393                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6394                                                     TG3_TX_RING_SIZE,
6395                                                     GFP_KERNEL);
6396                         if (!tnapi->tx_buffers)
6397                                 goto err_out;
6398
6399                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6400                                                               TG3_TX_RING_BYTES,
6401                                                        &tnapi->tx_desc_mapping);
6402                         if (!tnapi->tx_ring)
6403                                 goto err_out;
6404                 }
6405
6406                 /*
6407                  * When RSS is enabled, the status block format changes
6408                  * slightly.  The "rx_jumbo_consumer", "reserved",
6409                  * and "rx_mini_consumer" members get mapped to the
6410                  * other three rx return ring producer indexes.
6411                  */
6412                 switch (i) {
6413                 default:
6414                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6415                         break;
6416                 case 2:
6417                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6418                         break;
6419                 case 3:
6420                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6421                         break;
6422                 case 4:
6423                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6424                         break;
6425                 }
6426
6427                 tnapi->prodring = &tp->prodring[i];
6428
6429                 /*
6430                  * If multivector RSS is enabled, vector 0 does not handle
6431                  * rx or tx interrupts.  Don't allocate any resources for it.
6432                  */
6433                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6434                         continue;
6435
6436                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6437                                                      TG3_RX_RCB_RING_BYTES(tp),
6438                                                      &tnapi->rx_rcb_mapping);
6439                 if (!tnapi->rx_rcb)
6440                         goto err_out;
6441
6442                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6443         }
6444
6445         return 0;
6446
6447 err_out:
6448         tg3_free_consistent(tp);
6449         return -ENOMEM;
6450 }
6451
6452 #define MAX_WAIT_CNT 1000
6453
6454 /* To stop a block, clear the enable bit and poll till it
6455  * clears.  tp->lock is held.
6456  */
6457 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6458 {
6459         unsigned int i;
6460         u32 val;
6461
6462         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6463                 switch (ofs) {
6464                 case RCVLSC_MODE:
6465                 case DMAC_MODE:
6466                 case MBFREE_MODE:
6467                 case BUFMGR_MODE:
6468                 case MEMARB_MODE:
6469                         /* We can't enable/disable these bits of the
6470                          * 5705/5750, just say success.
6471                          */
6472                         return 0;
6473
6474                 default:
6475                         break;
6476                 }
6477         }
6478
6479         val = tr32(ofs);
6480         val &= ~enable_bit;
6481         tw32_f(ofs, val);
6482
6483         for (i = 0; i < MAX_WAIT_CNT; i++) {
6484                 udelay(100);
6485                 val = tr32(ofs);
6486                 if ((val & enable_bit) == 0)
6487                         break;
6488         }
6489
6490         if (i == MAX_WAIT_CNT && !silent) {
6491                 dev_err(&tp->pdev->dev,
6492                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6493                         ofs, enable_bit);
6494                 return -ENODEV;
6495         }
6496
6497         return 0;
6498 }
6499
6500 /* tp->lock is held. */
6501 static int tg3_abort_hw(struct tg3 *tp, int silent)
6502 {
6503         int i, err;
6504
6505         tg3_disable_ints(tp);
6506
6507         tp->rx_mode &= ~RX_MODE_ENABLE;
6508         tw32_f(MAC_RX_MODE, tp->rx_mode);
6509         udelay(10);
6510
6511         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6512         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6513         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6514         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6515         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6516         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6517
6518         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6519         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6520         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6521         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6522         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6523         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6524         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6525
6526         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6527         tw32_f(MAC_MODE, tp->mac_mode);
6528         udelay(40);
6529
6530         tp->tx_mode &= ~TX_MODE_ENABLE;
6531         tw32_f(MAC_TX_MODE, tp->tx_mode);
6532
6533         for (i = 0; i < MAX_WAIT_CNT; i++) {
6534                 udelay(100);
6535                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6536                         break;
6537         }
6538         if (i >= MAX_WAIT_CNT) {
6539                 dev_err(&tp->pdev->dev,
6540                         "%s timed out, TX_MODE_ENABLE will not clear "
6541                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6542                 err |= -ENODEV;
6543         }
6544
6545         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6546         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6548
6549         tw32(FTQ_RESET, 0xffffffff);
6550         tw32(FTQ_RESET, 0x00000000);
6551
6552         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6553         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6554
6555         for (i = 0; i < tp->irq_cnt; i++) {
6556                 struct tg3_napi *tnapi = &tp->napi[i];
6557                 if (tnapi->hw_status)
6558                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6559         }
6560         if (tp->hw_stats)
6561                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6562
6563         return err;
6564 }
6565
6566 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6567 {
6568         int i;
6569         u32 apedata;
6570
6571         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6572         if (apedata != APE_SEG_SIG_MAGIC)
6573                 return;
6574
6575         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6576         if (!(apedata & APE_FW_STATUS_READY))
6577                 return;
6578
6579         /* Wait for up to 1 millisecond for APE to service previous event. */
6580         for (i = 0; i < 10; i++) {
6581                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6582                         return;
6583
6584                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6585
6586                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6587                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6588                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6589
6590                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6591
6592                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6593                         break;
6594
6595                 udelay(100);
6596         }
6597
6598         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6599                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6600 }
6601
6602 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6603 {
6604         u32 event;
6605         u32 apedata;
6606
6607         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6608                 return;
6609
6610         switch (kind) {
6611         case RESET_KIND_INIT:
6612                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6613                                 APE_HOST_SEG_SIG_MAGIC);
6614                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6615                                 APE_HOST_SEG_LEN_MAGIC);
6616                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6617                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6618                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6619                                 APE_HOST_DRIVER_ID_MAGIC);
6620                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6621                                 APE_HOST_BEHAV_NO_PHYLOCK);
6622
6623                 event = APE_EVENT_STATUS_STATE_START;
6624                 break;
6625         case RESET_KIND_SHUTDOWN:
6626                 /* With the interface we are currently using,
6627                  * APE does not track driver state.  Wiping
6628                  * out the HOST SEGMENT SIGNATURE forces
6629                  * the APE to assume OS absent status.
6630                  */
6631                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6632
6633                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6634                 break;
6635         case RESET_KIND_SUSPEND:
6636                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6637                 break;
6638         default:
6639                 return;
6640         }
6641
6642         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6643
6644         tg3_ape_send_event(tp, event);
6645 }
6646
6647 /* tp->lock is held. */
6648 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6649 {
6650         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6651                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6652
6653         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6654                 switch (kind) {
6655                 case RESET_KIND_INIT:
6656                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6657                                       DRV_STATE_START);
6658                         break;
6659
6660                 case RESET_KIND_SHUTDOWN:
6661                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6662                                       DRV_STATE_UNLOAD);
6663                         break;
6664
6665                 case RESET_KIND_SUSPEND:
6666                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6667                                       DRV_STATE_SUSPEND);
6668                         break;
6669
6670                 default:
6671                         break;
6672                 }
6673         }
6674
6675         if (kind == RESET_KIND_INIT ||
6676             kind == RESET_KIND_SUSPEND)
6677                 tg3_ape_driver_state_change(tp, kind);
6678 }
6679
6680 /* tp->lock is held. */
6681 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6682 {
6683         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6684                 switch (kind) {
6685                 case RESET_KIND_INIT:
6686                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6687                                       DRV_STATE_START_DONE);
6688                         break;
6689
6690                 case RESET_KIND_SHUTDOWN:
6691                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6692                                       DRV_STATE_UNLOAD_DONE);
6693                         break;
6694
6695                 default:
6696                         break;
6697                 }
6698         }
6699
6700         if (kind == RESET_KIND_SHUTDOWN)
6701                 tg3_ape_driver_state_change(tp, kind);
6702 }
6703
6704 /* tp->lock is held. */
6705 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6706 {
6707         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6708                 switch (kind) {
6709                 case RESET_KIND_INIT:
6710                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6711                                       DRV_STATE_START);
6712                         break;
6713
6714                 case RESET_KIND_SHUTDOWN:
6715                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6716                                       DRV_STATE_UNLOAD);
6717                         break;
6718
6719                 case RESET_KIND_SUSPEND:
6720                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6721                                       DRV_STATE_SUSPEND);
6722                         break;
6723
6724                 default:
6725                         break;
6726                 }
6727         }
6728 }
6729
6730 static int tg3_poll_fw(struct tg3 *tp)
6731 {
6732         int i;
6733         u32 val;
6734
6735         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6736                 /* Wait up to 20ms for init done. */
6737                 for (i = 0; i < 200; i++) {
6738                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6739                                 return 0;
6740                         udelay(100);
6741                 }
6742                 return -ENODEV;
6743         }
6744
6745         /* Wait for firmware initialization to complete. */
6746         for (i = 0; i < 100000; i++) {
6747                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6748                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6749                         break;
6750                 udelay(10);
6751         }
6752
6753         /* Chip might not be fitted with firmware.  Some Sun onboard
6754          * parts are configured like that.  So don't signal the timeout
6755          * of the above loop as an error, but do report the lack of
6756          * running firmware once.
6757          */
6758         if (i >= 100000 &&
6759             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6760                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6761
6762                 netdev_info(tp->dev, "No firmware running\n");
6763         }
6764
6765         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6766                 /* The 57765 A0 needs a little more
6767                  * time to do some important work.
6768                  */
6769                 mdelay(10);
6770         }
6771
6772         return 0;
6773 }
6774
6775 /* Save PCI command register before chip reset */
6776 static void tg3_save_pci_state(struct tg3 *tp)
6777 {
6778         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6779 }
6780
6781 /* Restore PCI state after chip reset */
6782 static void tg3_restore_pci_state(struct tg3 *tp)
6783 {
6784         u32 val;
6785
6786         /* Re-enable indirect register accesses. */
6787         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6788                                tp->misc_host_ctrl);
6789
6790         /* Set MAX PCI retry to zero. */
6791         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6792         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6793             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6794                 val |= PCISTATE_RETRY_SAME_DMA;
6795         /* Allow reads and writes to the APE register and memory space. */
6796         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6797                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6798                        PCISTATE_ALLOW_APE_SHMEM_WR |
6799                        PCISTATE_ALLOW_APE_PSPACE_WR;
6800         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6801
6802         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6803
6804         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6805                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6806                         pcie_set_readrq(tp->pdev, 4096);
6807                 else {
6808                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6809                                               tp->pci_cacheline_sz);
6810                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6811                                               tp->pci_lat_timer);
6812                 }
6813         }
6814
6815         /* Make sure PCI-X relaxed ordering bit is clear. */
6816         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6817                 u16 pcix_cmd;
6818
6819                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6820                                      &pcix_cmd);
6821                 pcix_cmd &= ~PCI_X_CMD_ERO;
6822                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6823                                       pcix_cmd);
6824         }
6825
6826         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6827
6828                 /* Chip reset on 5780 will reset MSI enable bit,
6829                  * so need to restore it.
6830                  */
6831                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6832                         u16 ctrl;
6833
6834                         pci_read_config_word(tp->pdev,
6835                                              tp->msi_cap + PCI_MSI_FLAGS,
6836                                              &ctrl);
6837                         pci_write_config_word(tp->pdev,
6838                                               tp->msi_cap + PCI_MSI_FLAGS,
6839                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6840                         val = tr32(MSGINT_MODE);
6841                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6842                 }
6843         }
6844 }
6845
6846 static void tg3_stop_fw(struct tg3 *);
6847
6848 /* tp->lock is held. */
6849 static int tg3_chip_reset(struct tg3 *tp)
6850 {
6851         u32 val;
6852         void (*write_op)(struct tg3 *, u32, u32);
6853         int i, err;
6854
6855         tg3_nvram_lock(tp);
6856
6857         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6858
6859         /* No matching tg3_nvram_unlock() after this because
6860          * chip reset below will undo the nvram lock.
6861          */
6862         tp->nvram_lock_cnt = 0;
6863
6864         /* GRC_MISC_CFG core clock reset will clear the memory
6865          * enable bit in PCI register 4 and the MSI enable bit
6866          * on some chips, so we save relevant registers here.
6867          */
6868         tg3_save_pci_state(tp);
6869
6870         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6871             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6872                 tw32(GRC_FASTBOOT_PC, 0);
6873
6874         /*
6875          * We must avoid the readl() that normally takes place.
6876          * It locks machines, causes machine checks, and other
6877          * fun things.  So, temporarily disable the 5701
6878          * hardware workaround, while we do the reset.
6879          */
6880         write_op = tp->write32;
6881         if (write_op == tg3_write_flush_reg32)
6882                 tp->write32 = tg3_write32;
6883
6884         /* Prevent the irq handler from reading or writing PCI registers
6885          * during chip reset when the memory enable bit in the PCI command
6886          * register may be cleared.  The chip does not generate interrupt
6887          * at this time, but the irq handler may still be called due to irq
6888          * sharing or irqpoll.
6889          */
6890         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6891         for (i = 0; i < tp->irq_cnt; i++) {
6892                 struct tg3_napi *tnapi = &tp->napi[i];
6893                 if (tnapi->hw_status) {
6894                         tnapi->hw_status->status = 0;
6895                         tnapi->hw_status->status_tag = 0;
6896                 }
6897                 tnapi->last_tag = 0;
6898                 tnapi->last_irq_tag = 0;
6899         }
6900         smp_mb();
6901
6902         for (i = 0; i < tp->irq_cnt; i++)
6903                 synchronize_irq(tp->napi[i].irq_vec);
6904
6905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6906                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6907                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6908         }
6909
6910         /* do the reset */
6911         val = GRC_MISC_CFG_CORECLK_RESET;
6912
6913         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6914                 if (tr32(0x7e2c) == 0x60) {
6915                         tw32(0x7e2c, 0x20);
6916                 }
6917                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6918                         tw32(GRC_MISC_CFG, (1 << 29));
6919                         val |= (1 << 29);
6920                 }
6921         }
6922
6923         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6924                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6925                 tw32(GRC_VCPU_EXT_CTRL,
6926                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6927         }
6928
6929         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6930                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6931         tw32(GRC_MISC_CFG, val);
6932
6933         /* restore 5701 hardware bug workaround write method */
6934         tp->write32 = write_op;
6935
6936         /* Unfortunately, we have to delay before the PCI read back.
6937          * Some 575X chips even will not respond to a PCI cfg access
6938          * when the reset command is given to the chip.
6939          *
6940          * How do these hardware designers expect things to work
6941          * properly if the PCI write is posted for a long period
6942          * of time?  It is always necessary to have some method by
6943          * which a register read back can occur to push the write
6944          * out which does the reset.
6945          *
6946          * For most tg3 variants the trick below was working.
6947          * Ho hum...
6948          */
6949         udelay(120);
6950
6951         /* Flush PCI posted writes.  The normal MMIO registers
6952          * are inaccessible at this time so this is the only
6953          * way to make this reliably (actually, this is no longer
6954          * the case, see above).  I tried to use indirect
6955          * register read/write but this upset some 5701 variants.
6956          */
6957         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6958
6959         udelay(120);
6960
6961         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6962                 u16 val16;
6963
6964                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6965                         int i;
6966                         u32 cfg_val;
6967
6968                         /* Wait for link training to complete.  */
6969                         for (i = 0; i < 5000; i++)
6970                                 udelay(100);
6971
6972                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6973                         pci_write_config_dword(tp->pdev, 0xc4,
6974                                                cfg_val | (1 << 15));
6975                 }
6976
6977                 /* Clear the "no snoop" and "relaxed ordering" bits. */
6978                 pci_read_config_word(tp->pdev,
6979                                      tp->pcie_cap + PCI_EXP_DEVCTL,
6980                                      &val16);
6981                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6982                            PCI_EXP_DEVCTL_NOSNOOP_EN);
6983                 /*
6984                  * Older PCIe devices only support the 128 byte
6985                  * MPS setting.  Enforce the restriction.
6986                  */
6987                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6988                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6989                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6990                 pci_write_config_word(tp->pdev,
6991                                       tp->pcie_cap + PCI_EXP_DEVCTL,
6992                                       val16);
6993
6994                 pcie_set_readrq(tp->pdev, 4096);
6995
6996                 /* Clear error status */
6997                 pci_write_config_word(tp->pdev,
6998                                       tp->pcie_cap + PCI_EXP_DEVSTA,
6999                                       PCI_EXP_DEVSTA_CED |
7000                                       PCI_EXP_DEVSTA_NFED |
7001                                       PCI_EXP_DEVSTA_FED |
7002                                       PCI_EXP_DEVSTA_URD);
7003         }
7004
7005         tg3_restore_pci_state(tp);
7006
7007         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7008
7009         val = 0;
7010         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7011                 val = tr32(MEMARB_MODE);
7012         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7013
7014         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7015                 tg3_stop_fw(tp);
7016                 tw32(0x5000, 0x400);
7017         }
7018
7019         tw32(GRC_MODE, tp->grc_mode);
7020
7021         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7022                 val = tr32(0xc4);
7023
7024                 tw32(0xc4, val | (1 << 15));
7025         }
7026
7027         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7029                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7030                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7031                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7032                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7033         }
7034
7035         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
7036                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7037                 tw32_f(MAC_MODE, tp->mac_mode);
7038         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7039                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7040                 tw32_f(MAC_MODE, tp->mac_mode);
7041         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7042                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7043                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7044                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7045                 tw32_f(MAC_MODE, tp->mac_mode);
7046         } else
7047                 tw32_f(MAC_MODE, 0);
7048         udelay(40);
7049
7050         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7051
7052         err = tg3_poll_fw(tp);
7053         if (err)
7054                 return err;
7055
7056         tg3_mdio_start(tp);
7057
7058         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7059                 u8 phy_addr;
7060
7061                 phy_addr = tp->phy_addr;
7062                 tp->phy_addr = TG3_PHY_PCIE_ADDR;
7063
7064                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7065                              TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
7066                 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
7067                       TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
7068                       TG3_PCIEPHY_TX0CTRL1_NB_EN;
7069                 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
7070                 udelay(10);
7071
7072                 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
7073                              TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
7074                 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
7075                       TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
7076                 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
7077                 udelay(10);
7078
7079                 tp->phy_addr = phy_addr;
7080         }
7081
7082         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7083             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7084             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7085             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7086             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
7087                 val = tr32(0x7c00);
7088
7089                 tw32(0x7c00, val | (1 << 25));
7090         }
7091
7092         /* Reprobe ASF enable state.  */
7093         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7094         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7095         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7096         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7097                 u32 nic_cfg;
7098
7099                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7100                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7101                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7102                         tp->last_event_jiffies = jiffies;
7103                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7104                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7105                 }
7106         }
7107
7108         return 0;
7109 }
7110
7111 /* tp->lock is held. */
7112 static void tg3_stop_fw(struct tg3 *tp)
7113 {
7114         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7115            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7116                 /* Wait for RX cpu to ACK the previous event. */
7117                 tg3_wait_for_event_ack(tp);
7118
7119                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7120
7121                 tg3_generate_fw_event(tp);
7122
7123                 /* Wait for RX cpu to ACK this event. */
7124                 tg3_wait_for_event_ack(tp);
7125         }
7126 }
7127
7128 /* tp->lock is held. */
7129 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7130 {
7131         int err;
7132
7133         tg3_stop_fw(tp);
7134
7135         tg3_write_sig_pre_reset(tp, kind);
7136
7137         tg3_abort_hw(tp, silent);
7138         err = tg3_chip_reset(tp);
7139
7140         __tg3_set_mac_addr(tp, 0);
7141
7142         tg3_write_sig_legacy(tp, kind);
7143         tg3_write_sig_post_reset(tp, kind);
7144
7145         if (err)
7146                 return err;
7147
7148         return 0;
7149 }
7150
7151 #define RX_CPU_SCRATCH_BASE     0x30000
7152 #define RX_CPU_SCRATCH_SIZE     0x04000
7153 #define TX_CPU_SCRATCH_BASE     0x34000
7154 #define TX_CPU_SCRATCH_SIZE     0x04000
7155
7156 /* tp->lock is held. */
7157 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7158 {
7159         int i;
7160
7161         BUG_ON(offset == TX_CPU_BASE &&
7162             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7163
7164         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7165                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7166
7167                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7168                 return 0;
7169         }
7170         if (offset == RX_CPU_BASE) {
7171                 for (i = 0; i < 10000; i++) {
7172                         tw32(offset + CPU_STATE, 0xffffffff);
7173                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7174                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7175                                 break;
7176                 }
7177
7178                 tw32(offset + CPU_STATE, 0xffffffff);
7179                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7180                 udelay(10);
7181         } else {
7182                 for (i = 0; i < 10000; i++) {
7183                         tw32(offset + CPU_STATE, 0xffffffff);
7184                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7185                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7186                                 break;
7187                 }
7188         }
7189
7190         if (i >= 10000) {
7191                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7192                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7193                 return -ENODEV;
7194         }
7195
7196         /* Clear firmware's nvram arbitration. */
7197         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7198                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7199         return 0;
7200 }
7201
7202 struct fw_info {
7203         unsigned int fw_base;
7204         unsigned int fw_len;
7205         const __be32 *fw_data;
7206 };
7207
7208 /* tp->lock is held. */
7209 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7210                                  int cpu_scratch_size, struct fw_info *info)
7211 {
7212         int err, lock_err, i;
7213         void (*write_op)(struct tg3 *, u32, u32);
7214
7215         if (cpu_base == TX_CPU_BASE &&
7216             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7217                 netdev_err(tp->dev,
7218                            "%s: Trying to load TX cpu firmware which is 5705\n",
7219                            __func__);
7220                 return -EINVAL;
7221         }
7222
7223         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7224                 write_op = tg3_write_mem;
7225         else
7226                 write_op = tg3_write_indirect_reg32;
7227
7228         /* It is possible that bootcode is still loading at this point.
7229          * Get the nvram lock first before halting the cpu.
7230          */
7231         lock_err = tg3_nvram_lock(tp);
7232         err = tg3_halt_cpu(tp, cpu_base);
7233         if (!lock_err)
7234                 tg3_nvram_unlock(tp);
7235         if (err)
7236                 goto out;
7237
7238         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7239                 write_op(tp, cpu_scratch_base + i, 0);
7240         tw32(cpu_base + CPU_STATE, 0xffffffff);
7241         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7242         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7243                 write_op(tp, (cpu_scratch_base +
7244                               (info->fw_base & 0xffff) +
7245                               (i * sizeof(u32))),
7246                               be32_to_cpu(info->fw_data[i]));
7247
7248         err = 0;
7249
7250 out:
7251         return err;
7252 }
7253
7254 /* tp->lock is held. */
7255 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7256 {
7257         struct fw_info info;
7258         const __be32 *fw_data;
7259         int err, i;
7260
7261         fw_data = (void *)tp->fw->data;
7262
7263         /* Firmware blob starts with version numbers, followed by
7264            start address and length. We are setting complete length.
7265            length = end_address_of_bss - start_address_of_text.
7266            Remainder is the blob to be loaded contiguously
7267            from start address. */
7268
7269         info.fw_base = be32_to_cpu(fw_data[1]);
7270         info.fw_len = tp->fw->size - 12;
7271         info.fw_data = &fw_data[3];
7272
7273         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7274                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7275                                     &info);
7276         if (err)
7277                 return err;
7278
7279         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7280                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7281                                     &info);
7282         if (err)
7283                 return err;
7284
7285         /* Now startup only the RX cpu. */
7286         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7287         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7288
7289         for (i = 0; i < 5; i++) {
7290                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7291                         break;
7292                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7293                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7294                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7295                 udelay(1000);
7296         }
7297         if (i >= 5) {
7298                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7299                            "should be %08x\n", __func__,
7300                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7301                 return -ENODEV;
7302         }
7303         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7304         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7305
7306         return 0;
7307 }
7308
7309 /* 5705 needs a special version of the TSO firmware.  */
7310
7311 /* tp->lock is held. */
7312 static int tg3_load_tso_firmware(struct tg3 *tp)
7313 {
7314         struct fw_info info;
7315         const __be32 *fw_data;
7316         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7317         int err, i;
7318
7319         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7320                 return 0;
7321
7322         fw_data = (void *)tp->fw->data;
7323
7324         /* Firmware blob starts with version numbers, followed by
7325            start address and length. We are setting complete length.
7326            length = end_address_of_bss - start_address_of_text.
7327            Remainder is the blob to be loaded contiguously
7328            from start address. */
7329
7330         info.fw_base = be32_to_cpu(fw_data[1]);
7331         cpu_scratch_size = tp->fw_len;
7332         info.fw_len = tp->fw->size - 12;
7333         info.fw_data = &fw_data[3];
7334
7335         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7336                 cpu_base = RX_CPU_BASE;
7337                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7338         } else {
7339                 cpu_base = TX_CPU_BASE;
7340                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7341                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7342         }
7343
7344         err = tg3_load_firmware_cpu(tp, cpu_base,
7345                                     cpu_scratch_base, cpu_scratch_size,
7346                                     &info);
7347         if (err)
7348                 return err;
7349
7350         /* Now startup the cpu. */
7351         tw32(cpu_base + CPU_STATE, 0xffffffff);
7352         tw32_f(cpu_base + CPU_PC, info.fw_base);
7353
7354         for (i = 0; i < 5; i++) {
7355                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7356                         break;
7357                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7358                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7359                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7360                 udelay(1000);
7361         }
7362         if (i >= 5) {
7363                 netdev_err(tp->dev,
7364                            "%s fails to set CPU PC, is %08x should be %08x\n",
7365                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7366                 return -ENODEV;
7367         }
7368         tw32(cpu_base + CPU_STATE, 0xffffffff);
7369         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7370         return 0;
7371 }
7372
7373
7374 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7375 {
7376         struct tg3 *tp = netdev_priv(dev);
7377         struct sockaddr *addr = p;
7378         int err = 0, skip_mac_1 = 0;
7379
7380         if (!is_valid_ether_addr(addr->sa_data))
7381                 return -EINVAL;
7382
7383         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7384
7385         if (!netif_running(dev))
7386                 return 0;
7387
7388         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7389                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7390
7391                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7392                 addr0_low = tr32(MAC_ADDR_0_LOW);
7393                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7394                 addr1_low = tr32(MAC_ADDR_1_LOW);
7395
7396                 /* Skip MAC addr 1 if ASF is using it. */
7397                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7398                     !(addr1_high == 0 && addr1_low == 0))
7399                         skip_mac_1 = 1;
7400         }
7401         spin_lock_bh(&tp->lock);
7402         __tg3_set_mac_addr(tp, skip_mac_1);
7403         spin_unlock_bh(&tp->lock);
7404
7405         return err;
7406 }
7407
7408 /* tp->lock is held. */
7409 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7410                            dma_addr_t mapping, u32 maxlen_flags,
7411                            u32 nic_addr)
7412 {
7413         tg3_write_mem(tp,
7414                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7415                       ((u64) mapping >> 32));
7416         tg3_write_mem(tp,
7417                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7418                       ((u64) mapping & 0xffffffff));
7419         tg3_write_mem(tp,
7420                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7421                        maxlen_flags);
7422
7423         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7424                 tg3_write_mem(tp,
7425                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7426                               nic_addr);
7427 }
7428
7429 static void __tg3_set_rx_mode(struct net_device *);
7430 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7431 {
7432         int i;
7433
7434         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7435                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7436                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7437                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7438         } else {
7439                 tw32(HOSTCC_TXCOL_TICKS, 0);
7440                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7441                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7442         }
7443
7444         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7445                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7446                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7447                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7448         } else {
7449                 tw32(HOSTCC_RXCOL_TICKS, 0);
7450                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7451                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7452         }
7453
7454         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7455                 u32 val = ec->stats_block_coalesce_usecs;
7456
7457                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7458                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7459
7460                 if (!netif_carrier_ok(tp->dev))
7461                         val = 0;
7462
7463                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7464         }
7465
7466         for (i = 0; i < tp->irq_cnt - 1; i++) {
7467                 u32 reg;
7468
7469                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7470                 tw32(reg, ec->rx_coalesce_usecs);
7471                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7472                 tw32(reg, ec->rx_max_coalesced_frames);
7473                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7474                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7475
7476                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7477                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7478                         tw32(reg, ec->tx_coalesce_usecs);
7479                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7480                         tw32(reg, ec->tx_max_coalesced_frames);
7481                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7482                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7483                 }
7484         }
7485
7486         for (; i < tp->irq_max - 1; i++) {
7487                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7488                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7489                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7490
7491                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7492                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7493                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7494                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7495                 }
7496         }
7497 }
7498
7499 /* tp->lock is held. */
7500 static void tg3_rings_reset(struct tg3 *tp)
7501 {
7502         int i;
7503         u32 stblk, txrcb, rxrcb, limit;
7504         struct tg3_napi *tnapi = &tp->napi[0];
7505
7506         /* Disable all transmit rings but the first. */
7507         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7508                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7509         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7510                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7511         else
7512                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7513
7514         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7515              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7516                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7517                               BDINFO_FLAGS_DISABLED);
7518
7519
7520         /* Disable all receive return rings but the first. */
7521         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7522                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7523         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7524                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7525         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7526                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7527                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7528         else
7529                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7530
7531         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7532              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7533                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7534                               BDINFO_FLAGS_DISABLED);
7535
7536         /* Disable interrupts */
7537         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7538
7539         /* Zero mailbox registers. */
7540         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7541                 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7542                         tp->napi[i].tx_prod = 0;
7543                         tp->napi[i].tx_cons = 0;
7544                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7545                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7546                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7547                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7548                 }
7549                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7550                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7551         } else {
7552                 tp->napi[0].tx_prod = 0;
7553                 tp->napi[0].tx_cons = 0;
7554                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7555                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7556         }
7557
7558         /* Make sure the NIC-based send BD rings are disabled. */
7559         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7560                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7561                 for (i = 0; i < 16; i++)
7562                         tw32_tx_mbox(mbox + i * 8, 0);
7563         }
7564
7565         txrcb = NIC_SRAM_SEND_RCB;
7566         rxrcb = NIC_SRAM_RCV_RET_RCB;
7567
7568         /* Clear status block in ram. */
7569         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7570
7571         /* Set status block DMA address */
7572         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7573              ((u64) tnapi->status_mapping >> 32));
7574         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7575              ((u64) tnapi->status_mapping & 0xffffffff));
7576
7577         if (tnapi->tx_ring) {
7578                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7579                                (TG3_TX_RING_SIZE <<
7580                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7581                                NIC_SRAM_TX_BUFFER_DESC);
7582                 txrcb += TG3_BDINFO_SIZE;
7583         }
7584
7585         if (tnapi->rx_rcb) {
7586                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7587                                (TG3_RX_RCB_RING_SIZE(tp) <<
7588                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7589                 rxrcb += TG3_BDINFO_SIZE;
7590         }
7591
7592         stblk = HOSTCC_STATBLCK_RING1;
7593
7594         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7595                 u64 mapping = (u64)tnapi->status_mapping;
7596                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7597                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7598
7599                 /* Clear status block in ram. */
7600                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7601
7602                 if (tnapi->tx_ring) {
7603                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7604                                        (TG3_TX_RING_SIZE <<
7605                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7606                                        NIC_SRAM_TX_BUFFER_DESC);
7607                         txrcb += TG3_BDINFO_SIZE;
7608                 }
7609
7610                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7611                                (TG3_RX_RCB_RING_SIZE(tp) <<
7612                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7613
7614                 stblk += 8;
7615                 rxrcb += TG3_BDINFO_SIZE;
7616         }
7617 }
7618
7619 /* tp->lock is held. */
7620 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7621 {
7622         u32 val, rdmac_mode;
7623         int i, err, limit;
7624         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7625
7626         tg3_disable_ints(tp);
7627
7628         tg3_stop_fw(tp);
7629
7630         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7631
7632         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7633                 tg3_abort_hw(tp, 1);
7634
7635         if (reset_phy)
7636                 tg3_phy_reset(tp);
7637
7638         err = tg3_chip_reset(tp);
7639         if (err)
7640                 return err;
7641
7642         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7643
7644         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7645                 val = tr32(TG3_CPMU_CTRL);
7646                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7647                 tw32(TG3_CPMU_CTRL, val);
7648
7649                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7650                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7651                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7652                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7653
7654                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7655                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7656                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7657                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7658
7659                 val = tr32(TG3_CPMU_HST_ACC);
7660                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7661                 val |= CPMU_HST_ACC_MACCLK_6_25;
7662                 tw32(TG3_CPMU_HST_ACC, val);
7663         }
7664
7665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7666                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7667                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7668                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7669                 tw32(PCIE_PWR_MGMT_THRESH, val);
7670
7671                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7672                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7673
7674                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7675
7676                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7677                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7678         }
7679
7680         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7681                 u32 grc_mode = tr32(GRC_MODE);
7682
7683                 /* Access the lower 1K of PL PCIE block registers. */
7684                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7685                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7686
7687                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7688                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7689                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7690
7691                 tw32(GRC_MODE, grc_mode);
7692         }
7693
7694         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7695                 u32 grc_mode = tr32(GRC_MODE);
7696
7697                 /* Access the lower 1K of PL PCIE block registers. */
7698                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7699                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7700
7701                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7702                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7703                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7704
7705                 tw32(GRC_MODE, grc_mode);
7706
7707                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7708                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7709                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7710                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7711         }
7712
7713         /* This works around an issue with Athlon chipsets on
7714          * B3 tigon3 silicon.  This bit has no effect on any
7715          * other revision.  But do not set this on PCI Express
7716          * chips and don't even touch the clocks if the CPMU is present.
7717          */
7718         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7719                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7720                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7721                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7722         }
7723
7724         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7725             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7726                 val = tr32(TG3PCI_PCISTATE);
7727                 val |= PCISTATE_RETRY_SAME_DMA;
7728                 tw32(TG3PCI_PCISTATE, val);
7729         }
7730
7731         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7732                 /* Allow reads and writes to the
7733                  * APE register and memory space.
7734                  */
7735                 val = tr32(TG3PCI_PCISTATE);
7736                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7737                        PCISTATE_ALLOW_APE_SHMEM_WR |
7738                        PCISTATE_ALLOW_APE_PSPACE_WR;
7739                 tw32(TG3PCI_PCISTATE, val);
7740         }
7741
7742         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7743                 /* Enable some hw fixes.  */
7744                 val = tr32(TG3PCI_MSI_DATA);
7745                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7746                 tw32(TG3PCI_MSI_DATA, val);
7747         }
7748
7749         /* Descriptor ring init may make accesses to the
7750          * NIC SRAM area to setup the TX descriptors, so we
7751          * can only do this after the hardware has been
7752          * successfully reset.
7753          */
7754         err = tg3_init_rings(tp);
7755         if (err)
7756                 return err;
7757
7758         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7759             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7760                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7761                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7762                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7763                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7764                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7765         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7766                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7767                 /* This value is determined during the probe time DMA
7768                  * engine test, tg3_test_dma.
7769                  */
7770                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7771         }
7772
7773         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7774                           GRC_MODE_4X_NIC_SEND_RINGS |
7775                           GRC_MODE_NO_TX_PHDR_CSUM |
7776                           GRC_MODE_NO_RX_PHDR_CSUM);
7777         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7778
7779         /* Pseudo-header checksum is done by hardware logic and not
7780          * the offload processers, so make the chip do the pseudo-
7781          * header checksums on receive.  For transmit it is more
7782          * convenient to do the pseudo-header checksum in software
7783          * as Linux does that on transmit for us in all cases.
7784          */
7785         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7786
7787         tw32(GRC_MODE,
7788              tp->grc_mode |
7789              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7790
7791         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7792         val = tr32(GRC_MISC_CFG);
7793         val &= ~0xff;
7794         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7795         tw32(GRC_MISC_CFG, val);
7796
7797         /* Initialize MBUF/DESC pool. */
7798         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7799                 /* Do nothing.  */
7800         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7801                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7802                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7803                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7804                 else
7805                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7806                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7807                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7808         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7809                 int fw_len;
7810
7811                 fw_len = tp->fw_len;
7812                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7813                 tw32(BUFMGR_MB_POOL_ADDR,
7814                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7815                 tw32(BUFMGR_MB_POOL_SIZE,
7816                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7817         }
7818
7819         if (tp->dev->mtu <= ETH_DATA_LEN) {
7820                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7821                      tp->bufmgr_config.mbuf_read_dma_low_water);
7822                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7823                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7824                 tw32(BUFMGR_MB_HIGH_WATER,
7825                      tp->bufmgr_config.mbuf_high_water);
7826         } else {
7827                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7828                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7829                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7830                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7831                 tw32(BUFMGR_MB_HIGH_WATER,
7832                      tp->bufmgr_config.mbuf_high_water_jumbo);
7833         }
7834         tw32(BUFMGR_DMA_LOW_WATER,
7835              tp->bufmgr_config.dma_low_water);
7836         tw32(BUFMGR_DMA_HIGH_WATER,
7837              tp->bufmgr_config.dma_high_water);
7838
7839         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7840         for (i = 0; i < 2000; i++) {
7841                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7842                         break;
7843                 udelay(10);
7844         }
7845         if (i >= 2000) {
7846                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7847                 return -ENODEV;
7848         }
7849
7850         /* Setup replenish threshold. */
7851         val = tp->rx_pending / 8;
7852         if (val == 0)
7853                 val = 1;
7854         else if (val > tp->rx_std_max_post)
7855                 val = tp->rx_std_max_post;
7856         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7857                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7858                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7859
7860                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7861                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7862         }
7863
7864         tw32(RCVBDI_STD_THRESH, val);
7865
7866         /* Initialize TG3_BDINFO's at:
7867          *  RCVDBDI_STD_BD:     standard eth size rx ring
7868          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7869          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7870          *
7871          * like so:
7872          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7873          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7874          *                              ring attribute flags
7875          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7876          *
7877          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7878          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7879          *
7880          * The size of each ring is fixed in the firmware, but the location is
7881          * configurable.
7882          */
7883         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7884              ((u64) tpr->rx_std_mapping >> 32));
7885         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7886              ((u64) tpr->rx_std_mapping & 0xffffffff));
7887         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7888                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7889                      NIC_SRAM_RX_BUFFER_DESC);
7890
7891         /* Disable the mini ring */
7892         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7893                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7894                      BDINFO_FLAGS_DISABLED);
7895
7896         /* Program the jumbo buffer descriptor ring control
7897          * blocks on those devices that have them.
7898          */
7899         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7900             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7901                 /* Setup replenish threshold. */
7902                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7903
7904                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7905                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7906                              ((u64) tpr->rx_jmb_mapping >> 32));
7907                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7908                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7909                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7910                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7911                              BDINFO_FLAGS_USE_EXT_RECV);
7912                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7913                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7914                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7915                 } else {
7916                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7917                              BDINFO_FLAGS_DISABLED);
7918                 }
7919
7920                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7921                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7922                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7923                               (TG3_RX_STD_DMA_SZ << 2);
7924                 else
7925                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7926         } else
7927                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7928
7929         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7930
7931         tpr->rx_std_prod_idx = tp->rx_pending;
7932         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7933
7934         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7935                           tp->rx_jumbo_pending : 0;
7936         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7937
7938         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7939             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7940                 tw32(STD_REPLENISH_LWM, 32);
7941                 tw32(JMB_REPLENISH_LWM, 16);
7942         }
7943
7944         tg3_rings_reset(tp);
7945
7946         /* Initialize MAC address and backoff seed. */
7947         __tg3_set_mac_addr(tp, 0);
7948
7949         /* MTU + ethernet header + FCS + optional VLAN tag */
7950         tw32(MAC_RX_MTU_SIZE,
7951              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7952
7953         /* The slot time is changed by tg3_setup_phy if we
7954          * run at gigabit with half duplex.
7955          */
7956         tw32(MAC_TX_LENGTHS,
7957              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7958              (6 << TX_LENGTHS_IPG_SHIFT) |
7959              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7960
7961         /* Receive rules. */
7962         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7963         tw32(RCVLPC_CONFIG, 0x0181);
7964
7965         /* Calculate RDMAC_MODE setting early, we need it to determine
7966          * the RCVLPC_STATE_ENABLE mask.
7967          */
7968         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7969                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7970                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7971                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7972                       RDMAC_MODE_LNGREAD_ENAB);
7973
7974         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7975                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
7976
7977         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7978             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7979             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7980                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7981                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7982                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7983
7984         /* If statement applies to 5705 and 5750 PCI devices only */
7985         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7986              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7987             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7988                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7989                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7990                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7991                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7992                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7993                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7994                 }
7995         }
7996
7997         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7998                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7999
8000         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8001                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8002
8003         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8004             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8005             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8006                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8007
8008         /* Receive/send statistics. */
8009         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8010                 val = tr32(RCVLPC_STATS_ENABLE);
8011                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8012                 tw32(RCVLPC_STATS_ENABLE, val);
8013         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8014                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8015                 val = tr32(RCVLPC_STATS_ENABLE);
8016                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8017                 tw32(RCVLPC_STATS_ENABLE, val);
8018         } else {
8019                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8020         }
8021         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8022         tw32(SNDDATAI_STATSENAB, 0xffffff);
8023         tw32(SNDDATAI_STATSCTRL,
8024              (SNDDATAI_SCTRL_ENABLE |
8025               SNDDATAI_SCTRL_FASTUPD));
8026
8027         /* Setup host coalescing engine. */
8028         tw32(HOSTCC_MODE, 0);
8029         for (i = 0; i < 2000; i++) {
8030                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8031                         break;
8032                 udelay(10);
8033         }
8034
8035         __tg3_set_coalesce(tp, &tp->coal);
8036
8037         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8038                 /* Status/statistics block address.  See tg3_timer,
8039                  * the tg3_periodic_fetch_stats call there, and
8040                  * tg3_get_stats to see how this works for 5705/5750 chips.
8041                  */
8042                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8043                      ((u64) tp->stats_mapping >> 32));
8044                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8045                      ((u64) tp->stats_mapping & 0xffffffff));
8046                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8047
8048                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8049
8050                 /* Clear statistics and status block memory areas */
8051                 for (i = NIC_SRAM_STATS_BLK;
8052                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8053                      i += sizeof(u32)) {
8054                         tg3_write_mem(tp, i, 0);
8055                         udelay(40);
8056                 }
8057         }
8058
8059         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8060
8061         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8062         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8063         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8064                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8065
8066         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8067                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
8068                 /* reset to prevent losing 1st rx packet intermittently */
8069                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8070                 udelay(10);
8071         }
8072
8073         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8074                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8075         else
8076                 tp->mac_mode = 0;
8077         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8078                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8079         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8080             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8081             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8082                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8083         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8084         udelay(40);
8085
8086         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8087          * If TG3_FLG2_IS_NIC is zero, we should read the
8088          * register to preserve the GPIO settings for LOMs. The GPIOs,
8089          * whether used as inputs or outputs, are set by boot code after
8090          * reset.
8091          */
8092         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8093                 u32 gpio_mask;
8094
8095                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8096                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8097                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8098
8099                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8100                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8101                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8102
8103                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8104                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8105
8106                 tp->grc_local_ctrl &= ~gpio_mask;
8107                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8108
8109                 /* GPIO1 must be driven high for eeprom write protect */
8110                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8111                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8112                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8113         }
8114         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8115         udelay(100);
8116
8117         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8118                 val = tr32(MSGINT_MODE);
8119                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8120                 tw32(MSGINT_MODE, val);
8121         }
8122
8123         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8124                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8125                 udelay(40);
8126         }
8127
8128         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8129                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8130                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8131                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8132                WDMAC_MODE_LNGREAD_ENAB);
8133
8134         /* If statement applies to 5705 and 5750 PCI devices only */
8135         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8136              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8137             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8138                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8139                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8140                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8141                         /* nothing */
8142                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8143                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8144                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8145                         val |= WDMAC_MODE_RX_ACCEL;
8146                 }
8147         }
8148
8149         /* Enable host coalescing bug fix */
8150         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8151                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8152
8153         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8154                 val |= WDMAC_MODE_BURST_ALL_DATA;
8155
8156         tw32_f(WDMAC_MODE, val);
8157         udelay(40);
8158
8159         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8160                 u16 pcix_cmd;
8161
8162                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8163                                      &pcix_cmd);
8164                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8165                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8166                         pcix_cmd |= PCI_X_CMD_READ_2K;
8167                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8168                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8169                         pcix_cmd |= PCI_X_CMD_READ_2K;
8170                 }
8171                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8172                                       pcix_cmd);
8173         }
8174
8175         tw32_f(RDMAC_MODE, rdmac_mode);
8176         udelay(40);
8177
8178         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8179         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8180                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8181
8182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8183                 tw32(SNDDATAC_MODE,
8184                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8185         else
8186                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8187
8188         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8189         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8190         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8191         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8192         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8193                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8194         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8195         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8196                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8197         tw32(SNDBDI_MODE, val);
8198         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8199
8200         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8201                 err = tg3_load_5701_a0_firmware_fix(tp);
8202                 if (err)
8203                         return err;
8204         }
8205
8206         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8207                 err = tg3_load_tso_firmware(tp);
8208                 if (err)
8209                         return err;
8210         }
8211
8212         tp->tx_mode = TX_MODE_ENABLE;
8213         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8214             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8215                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8216         tw32_f(MAC_TX_MODE, tp->tx_mode);
8217         udelay(100);
8218
8219         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8220                 u32 reg = MAC_RSS_INDIR_TBL_0;
8221                 u8 *ent = (u8 *)&val;
8222
8223                 /* Setup the indirection table */
8224                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8225                         int idx = i % sizeof(val);
8226
8227                         ent[idx] = (i % (tp->irq_cnt - 1)) + 1;
8228                         if (idx == sizeof(val) - 1) {
8229                                 tw32(reg, val);
8230                                 reg += 4;
8231                         }
8232                 }
8233
8234                 /* Setup the "secret" hash key. */
8235                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8236                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8237                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8238                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8239                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8240                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8241                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8242                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8243                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8244                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8245         }
8246
8247         tp->rx_mode = RX_MODE_ENABLE;
8248         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8249                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8250
8251         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8252                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8253                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8254                                RX_MODE_RSS_IPV6_HASH_EN |
8255                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8256                                RX_MODE_RSS_IPV4_HASH_EN |
8257                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8258
8259         tw32_f(MAC_RX_MODE, tp->rx_mode);
8260         udelay(10);
8261
8262         tw32(MAC_LED_CTRL, tp->led_ctrl);
8263
8264         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8265         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8266                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8267                 udelay(10);
8268         }
8269         tw32_f(MAC_RX_MODE, tp->rx_mode);
8270         udelay(10);
8271
8272         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8273                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8274                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8275                         /* Set drive transmission level to 1.2V  */
8276                         /* only if the signal pre-emphasis bit is not set  */
8277                         val = tr32(MAC_SERDES_CFG);
8278                         val &= 0xfffff000;
8279                         val |= 0x880;
8280                         tw32(MAC_SERDES_CFG, val);
8281                 }
8282                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8283                         tw32(MAC_SERDES_CFG, 0x616000);
8284         }
8285
8286         /* Prevent chip from dropping frames when flow control
8287          * is enabled.
8288          */
8289         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8290                 val = 1;
8291         else
8292                 val = 2;
8293         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8294
8295         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8296             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8297                 /* Use hardware link auto-negotiation */
8298                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8299         }
8300
8301         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8302             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8303                 u32 tmp;
8304
8305                 tmp = tr32(SERDES_RX_CTRL);
8306                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8307                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8308                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8309                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8310         }
8311
8312         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8313                 if (tp->link_config.phy_is_low_power) {
8314                         tp->link_config.phy_is_low_power = 0;
8315                         tp->link_config.speed = tp->link_config.orig_speed;
8316                         tp->link_config.duplex = tp->link_config.orig_duplex;
8317                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8318                 }
8319
8320                 err = tg3_setup_phy(tp, 0);
8321                 if (err)
8322                         return err;
8323
8324                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8325                     !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8326                         u32 tmp;
8327
8328                         /* Clear CRC stats. */
8329                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8330                                 tg3_writephy(tp, MII_TG3_TEST1,
8331                                              tmp | MII_TG3_TEST1_CRC_EN);
8332                                 tg3_readphy(tp, 0x14, &tmp);
8333                         }
8334                 }
8335         }
8336
8337         __tg3_set_rx_mode(tp->dev);
8338
8339         /* Initialize receive rules. */
8340         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8341         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8342         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8343         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8344
8345         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8346             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8347                 limit = 8;
8348         else
8349                 limit = 16;
8350         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8351                 limit -= 4;
8352         switch (limit) {
8353         case 16:
8354                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8355         case 15:
8356                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8357         case 14:
8358                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8359         case 13:
8360                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8361         case 12:
8362                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8363         case 11:
8364                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8365         case 10:
8366                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8367         case 9:
8368                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8369         case 8:
8370                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8371         case 7:
8372                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8373         case 6:
8374                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8375         case 5:
8376                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8377         case 4:
8378                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8379         case 3:
8380                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8381         case 2:
8382         case 1:
8383
8384         default:
8385                 break;
8386         }
8387
8388         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8389                 /* Write our heartbeat update interval to APE. */
8390                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8391                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8392
8393         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8394
8395         return 0;
8396 }
8397
8398 /* Called at device open time to get the chip ready for
8399  * packet processing.  Invoked with tp->lock held.
8400  */
8401 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8402 {
8403         tg3_switch_clocks(tp);
8404
8405         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8406
8407         return tg3_reset_hw(tp, reset_phy);
8408 }
8409
8410 #define TG3_STAT_ADD32(PSTAT, REG) \
8411 do {    u32 __val = tr32(REG); \
8412         (PSTAT)->low += __val; \
8413         if ((PSTAT)->low < __val) \
8414                 (PSTAT)->high += 1; \
8415 } while (0)
8416
8417 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8418 {
8419         struct tg3_hw_stats *sp = tp->hw_stats;
8420
8421         if (!netif_carrier_ok(tp->dev))
8422                 return;
8423
8424         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8425         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8426         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8427         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8428         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8429         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8430         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8431         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8432         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8433         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8434         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8435         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8436         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8437
8438         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8439         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8440         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8441         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8442         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8443         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8444         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8445         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8446         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8447         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8448         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8449         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8450         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8451         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8452
8453         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8454         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8455         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8456 }
8457
8458 static void tg3_timer(unsigned long __opaque)
8459 {
8460         struct tg3 *tp = (struct tg3 *) __opaque;
8461
8462         if (tp->irq_sync)
8463                 goto restart_timer;
8464
8465         spin_lock(&tp->lock);
8466
8467         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8468                 /* All of this garbage is because when using non-tagged
8469                  * IRQ status the mailbox/status_block protocol the chip
8470                  * uses with the cpu is race prone.
8471                  */
8472                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8473                         tw32(GRC_LOCAL_CTRL,
8474                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8475                 } else {
8476                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8477                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8478                 }
8479
8480                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8481                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8482                         spin_unlock(&tp->lock);
8483                         schedule_work(&tp->reset_task);
8484                         return;
8485                 }
8486         }
8487
8488         /* This part only runs once per second. */
8489         if (!--tp->timer_counter) {
8490                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8491                         tg3_periodic_fetch_stats(tp);
8492
8493                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8494                         u32 mac_stat;
8495                         int phy_event;
8496
8497                         mac_stat = tr32(MAC_STATUS);
8498
8499                         phy_event = 0;
8500                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8501                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8502                                         phy_event = 1;
8503                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8504                                 phy_event = 1;
8505
8506                         if (phy_event)
8507                                 tg3_setup_phy(tp, 0);
8508                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8509                         u32 mac_stat = tr32(MAC_STATUS);
8510                         int need_setup = 0;
8511
8512                         if (netif_carrier_ok(tp->dev) &&
8513                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8514                                 need_setup = 1;
8515                         }
8516                         if (! netif_carrier_ok(tp->dev) &&
8517                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8518                                          MAC_STATUS_SIGNAL_DET))) {
8519                                 need_setup = 1;
8520                         }
8521                         if (need_setup) {
8522                                 if (!tp->serdes_counter) {
8523                                         tw32_f(MAC_MODE,
8524                                              (tp->mac_mode &
8525                                               ~MAC_MODE_PORT_MODE_MASK));
8526                                         udelay(40);
8527                                         tw32_f(MAC_MODE, tp->mac_mode);
8528                                         udelay(40);
8529                                 }
8530                                 tg3_setup_phy(tp, 0);
8531                         }
8532                 } else if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8533                            !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8534                         tg3_serdes_parallel_detect(tp);
8535                 }
8536
8537                 tp->timer_counter = tp->timer_multiplier;
8538         }
8539
8540         /* Heartbeat is only sent once every 2 seconds.
8541          *
8542          * The heartbeat is to tell the ASF firmware that the host
8543          * driver is still alive.  In the event that the OS crashes,
8544          * ASF needs to reset the hardware to free up the FIFO space
8545          * that may be filled with rx packets destined for the host.
8546          * If the FIFO is full, ASF will no longer function properly.
8547          *
8548          * Unintended resets have been reported on real time kernels
8549          * where the timer doesn't run on time.  Netpoll will also have
8550          * same problem.
8551          *
8552          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8553          * to check the ring condition when the heartbeat is expiring
8554          * before doing the reset.  This will prevent most unintended
8555          * resets.
8556          */
8557         if (!--tp->asf_counter) {
8558                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8559                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8560                         tg3_wait_for_event_ack(tp);
8561
8562                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8563                                       FWCMD_NICDRV_ALIVE3);
8564                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8565                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8566                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8567
8568                         tg3_generate_fw_event(tp);
8569                 }
8570                 tp->asf_counter = tp->asf_multiplier;
8571         }
8572
8573         spin_unlock(&tp->lock);
8574
8575 restart_timer:
8576         tp->timer.expires = jiffies + tp->timer_offset;
8577         add_timer(&tp->timer);
8578 }
8579
8580 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8581 {
8582         irq_handler_t fn;
8583         unsigned long flags;
8584         char *name;
8585         struct tg3_napi *tnapi = &tp->napi[irq_num];
8586
8587         if (tp->irq_cnt == 1)
8588                 name = tp->dev->name;
8589         else {
8590                 name = &tnapi->irq_lbl[0];
8591                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8592                 name[IFNAMSIZ-1] = 0;
8593         }
8594
8595         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8596                 fn = tg3_msi;
8597                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8598                         fn = tg3_msi_1shot;
8599                 flags = IRQF_SAMPLE_RANDOM;
8600         } else {
8601                 fn = tg3_interrupt;
8602                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8603                         fn = tg3_interrupt_tagged;
8604                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8605         }
8606
8607         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8608 }
8609
8610 static int tg3_test_interrupt(struct tg3 *tp)
8611 {
8612         struct tg3_napi *tnapi = &tp->napi[0];
8613         struct net_device *dev = tp->dev;
8614         int err, i, intr_ok = 0;
8615         u32 val;
8616
8617         if (!netif_running(dev))
8618                 return -ENODEV;
8619
8620         tg3_disable_ints(tp);
8621
8622         free_irq(tnapi->irq_vec, tnapi);
8623
8624         /*
8625          * Turn off MSI one shot mode.  Otherwise this test has no
8626          * observable way to know whether the interrupt was delivered.
8627          */
8628         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8629              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8630             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8631                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8632                 tw32(MSGINT_MODE, val);
8633         }
8634
8635         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8636                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8637         if (err)
8638                 return err;
8639
8640         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8641         tg3_enable_ints(tp);
8642
8643         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8644                tnapi->coal_now);
8645
8646         for (i = 0; i < 5; i++) {
8647                 u32 int_mbox, misc_host_ctrl;
8648
8649                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8650                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8651
8652                 if ((int_mbox != 0) ||
8653                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8654                         intr_ok = 1;
8655                         break;
8656                 }
8657
8658                 msleep(10);
8659         }
8660
8661         tg3_disable_ints(tp);
8662
8663         free_irq(tnapi->irq_vec, tnapi);
8664
8665         err = tg3_request_irq(tp, 0);
8666
8667         if (err)
8668                 return err;
8669
8670         if (intr_ok) {
8671                 /* Reenable MSI one shot mode. */
8672                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8673                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8674                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8675                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8676                         tw32(MSGINT_MODE, val);
8677                 }
8678                 return 0;
8679         }
8680
8681         return -EIO;
8682 }
8683
8684 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8685  * successfully restored
8686  */
8687 static int tg3_test_msi(struct tg3 *tp)
8688 {
8689         int err;
8690         u16 pci_cmd;
8691
8692         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8693                 return 0;
8694
8695         /* Turn off SERR reporting in case MSI terminates with Master
8696          * Abort.
8697          */
8698         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8699         pci_write_config_word(tp->pdev, PCI_COMMAND,
8700                               pci_cmd & ~PCI_COMMAND_SERR);
8701
8702         err = tg3_test_interrupt(tp);
8703
8704         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8705
8706         if (!err)
8707                 return 0;
8708
8709         /* other failures */
8710         if (err != -EIO)
8711                 return err;
8712
8713         /* MSI test failed, go back to INTx mode */
8714         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8715                     "to INTx mode. Please report this failure to the PCI "
8716                     "maintainer and include system chipset information\n");
8717
8718         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8719
8720         pci_disable_msi(tp->pdev);
8721
8722         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8723         tp->napi[0].irq_vec = tp->pdev->irq;
8724
8725         err = tg3_request_irq(tp, 0);
8726         if (err)
8727                 return err;
8728
8729         /* Need to reset the chip because the MSI cycle may have terminated
8730          * with Master Abort.
8731          */
8732         tg3_full_lock(tp, 1);
8733
8734         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8735         err = tg3_init_hw(tp, 1);
8736
8737         tg3_full_unlock(tp);
8738
8739         if (err)
8740                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8741
8742         return err;
8743 }
8744
8745 static int tg3_request_firmware(struct tg3 *tp)
8746 {
8747         const __be32 *fw_data;
8748
8749         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8750                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8751                            tp->fw_needed);
8752                 return -ENOENT;
8753         }
8754
8755         fw_data = (void *)tp->fw->data;
8756
8757         /* Firmware blob starts with version numbers, followed by
8758          * start address and _full_ length including BSS sections
8759          * (which must be longer than the actual data, of course
8760          */
8761
8762         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8763         if (tp->fw_len < (tp->fw->size - 12)) {
8764                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8765                            tp->fw_len, tp->fw_needed);
8766                 release_firmware(tp->fw);
8767                 tp->fw = NULL;
8768                 return -EINVAL;
8769         }
8770
8771         /* We no longer need firmware; we have it. */
8772         tp->fw_needed = NULL;
8773         return 0;
8774 }
8775
8776 static bool tg3_enable_msix(struct tg3 *tp)
8777 {
8778         int i, rc, cpus = num_online_cpus();
8779         struct msix_entry msix_ent[tp->irq_max];
8780
8781         if (cpus == 1)
8782                 /* Just fallback to the simpler MSI mode. */
8783                 return false;
8784
8785         /*
8786          * We want as many rx rings enabled as there are cpus.
8787          * The first MSIX vector only deals with link interrupts, etc,
8788          * so we add one to the number of vectors we are requesting.
8789          */
8790         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8791
8792         for (i = 0; i < tp->irq_max; i++) {
8793                 msix_ent[i].entry  = i;
8794                 msix_ent[i].vector = 0;
8795         }
8796
8797         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8798         if (rc < 0) {
8799                 return false;
8800         } else if (rc != 0) {
8801                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8802                         return false;
8803                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8804                               tp->irq_cnt, rc);
8805                 tp->irq_cnt = rc;
8806         }
8807
8808         for (i = 0; i < tp->irq_max; i++)
8809                 tp->napi[i].irq_vec = msix_ent[i].vector;
8810
8811         tp->dev->real_num_tx_queues = 1;
8812         if (tp->irq_cnt > 1) {
8813                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8814
8815                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8816                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8817                         tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8818                 }
8819         }
8820
8821         return true;
8822 }
8823
8824 static void tg3_ints_init(struct tg3 *tp)
8825 {
8826         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8827             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8828                 /* All MSI supporting chips should support tagged
8829                  * status.  Assert that this is the case.
8830                  */
8831                 netdev_warn(tp->dev,
8832                             "MSI without TAGGED_STATUS? Not using MSI\n");
8833                 goto defcfg;
8834         }
8835
8836         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8837                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8838         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8839                  pci_enable_msi(tp->pdev) == 0)
8840                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8841
8842         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8843                 u32 msi_mode = tr32(MSGINT_MODE);
8844                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8845                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8846                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8847         }
8848 defcfg:
8849         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8850                 tp->irq_cnt = 1;
8851                 tp->napi[0].irq_vec = tp->pdev->irq;
8852                 tp->dev->real_num_tx_queues = 1;
8853         }
8854 }
8855
8856 static void tg3_ints_fini(struct tg3 *tp)
8857 {
8858         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8859                 pci_disable_msix(tp->pdev);
8860         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8861                 pci_disable_msi(tp->pdev);
8862         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8863         tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8864 }
8865
8866 static int tg3_open(struct net_device *dev)
8867 {
8868         struct tg3 *tp = netdev_priv(dev);
8869         int i, err;
8870
8871         if (tp->fw_needed) {
8872                 err = tg3_request_firmware(tp);
8873                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8874                         if (err)
8875                                 return err;
8876                 } else if (err) {
8877                         netdev_warn(tp->dev, "TSO capability disabled\n");
8878                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8879                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8880                         netdev_notice(tp->dev, "TSO capability restored\n");
8881                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8882                 }
8883         }
8884
8885         netif_carrier_off(tp->dev);
8886
8887         err = tg3_set_power_state(tp, PCI_D0);
8888         if (err)
8889                 return err;
8890
8891         tg3_full_lock(tp, 0);
8892
8893         tg3_disable_ints(tp);
8894         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8895
8896         tg3_full_unlock(tp);
8897
8898         /*
8899          * Setup interrupts first so we know how
8900          * many NAPI resources to allocate
8901          */
8902         tg3_ints_init(tp);
8903
8904         /* The placement of this call is tied
8905          * to the setup and use of Host TX descriptors.
8906          */
8907         err = tg3_alloc_consistent(tp);
8908         if (err)
8909                 goto err_out1;
8910
8911         tg3_napi_enable(tp);
8912
8913         for (i = 0; i < tp->irq_cnt; i++) {
8914                 struct tg3_napi *tnapi = &tp->napi[i];
8915                 err = tg3_request_irq(tp, i);
8916                 if (err) {
8917                         for (i--; i >= 0; i--)
8918                                 free_irq(tnapi->irq_vec, tnapi);
8919                         break;
8920                 }
8921         }
8922
8923         if (err)
8924                 goto err_out2;
8925
8926         tg3_full_lock(tp, 0);
8927
8928         err = tg3_init_hw(tp, 1);
8929         if (err) {
8930                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8931                 tg3_free_rings(tp);
8932         } else {
8933                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8934                         tp->timer_offset = HZ;
8935                 else
8936                         tp->timer_offset = HZ / 10;
8937
8938                 BUG_ON(tp->timer_offset > HZ);
8939                 tp->timer_counter = tp->timer_multiplier =
8940                         (HZ / tp->timer_offset);
8941                 tp->asf_counter = tp->asf_multiplier =
8942                         ((HZ / tp->timer_offset) * 2);
8943
8944                 init_timer(&tp->timer);
8945                 tp->timer.expires = jiffies + tp->timer_offset;
8946                 tp->timer.data = (unsigned long) tp;
8947                 tp->timer.function = tg3_timer;
8948         }
8949
8950         tg3_full_unlock(tp);
8951
8952         if (err)
8953                 goto err_out3;
8954
8955         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8956                 err = tg3_test_msi(tp);
8957
8958                 if (err) {
8959                         tg3_full_lock(tp, 0);
8960                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8961                         tg3_free_rings(tp);
8962                         tg3_full_unlock(tp);
8963
8964                         goto err_out2;
8965                 }
8966
8967                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8968                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8969                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8970                     (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8971                         u32 val = tr32(PCIE_TRANSACTION_CFG);
8972
8973                         tw32(PCIE_TRANSACTION_CFG,
8974                              val | PCIE_TRANS_CFG_1SHOT_MSI);
8975                 }
8976         }
8977
8978         tg3_phy_start(tp);
8979
8980         tg3_full_lock(tp, 0);
8981
8982         add_timer(&tp->timer);
8983         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8984         tg3_enable_ints(tp);
8985
8986         tg3_full_unlock(tp);
8987
8988         netif_tx_start_all_queues(dev);
8989
8990         return 0;
8991
8992 err_out3:
8993         for (i = tp->irq_cnt - 1; i >= 0; i--) {
8994                 struct tg3_napi *tnapi = &tp->napi[i];
8995                 free_irq(tnapi->irq_vec, tnapi);
8996         }
8997
8998 err_out2:
8999         tg3_napi_disable(tp);
9000         tg3_free_consistent(tp);
9001
9002 err_out1:
9003         tg3_ints_fini(tp);
9004         return err;
9005 }
9006
9007 static struct net_device_stats *tg3_get_stats(struct net_device *);
9008 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9009
9010 static int tg3_close(struct net_device *dev)
9011 {
9012         int i;
9013         struct tg3 *tp = netdev_priv(dev);
9014
9015         tg3_napi_disable(tp);
9016         cancel_work_sync(&tp->reset_task);
9017
9018         netif_tx_stop_all_queues(dev);
9019
9020         del_timer_sync(&tp->timer);
9021
9022         tg3_phy_stop(tp);
9023
9024         tg3_full_lock(tp, 1);
9025
9026         tg3_disable_ints(tp);
9027
9028         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9029         tg3_free_rings(tp);
9030         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9031
9032         tg3_full_unlock(tp);
9033
9034         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9035                 struct tg3_napi *tnapi = &tp->napi[i];
9036                 free_irq(tnapi->irq_vec, tnapi);
9037         }
9038
9039         tg3_ints_fini(tp);
9040
9041         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9042                sizeof(tp->net_stats_prev));
9043         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9044                sizeof(tp->estats_prev));
9045
9046         tg3_free_consistent(tp);
9047
9048         tg3_set_power_state(tp, PCI_D3hot);
9049
9050         netif_carrier_off(tp->dev);
9051
9052         return 0;
9053 }
9054
9055 static inline unsigned long get_stat64(tg3_stat64_t *val)
9056 {
9057         unsigned long ret;
9058
9059 #if (BITS_PER_LONG == 32)
9060         ret = val->low;
9061 #else
9062         ret = ((u64)val->high << 32) | ((u64)val->low);
9063 #endif
9064         return ret;
9065 }
9066
9067 static inline u64 get_estat64(tg3_stat64_t *val)
9068 {
9069        return ((u64)val->high << 32) | ((u64)val->low);
9070 }
9071
9072 static unsigned long calc_crc_errors(struct tg3 *tp)
9073 {
9074         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9075
9076         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9078              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9079                 u32 val;
9080
9081                 spin_lock_bh(&tp->lock);
9082                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9083                         tg3_writephy(tp, MII_TG3_TEST1,
9084                                      val | MII_TG3_TEST1_CRC_EN);
9085                         tg3_readphy(tp, 0x14, &val);
9086                 } else
9087                         val = 0;
9088                 spin_unlock_bh(&tp->lock);
9089
9090                 tp->phy_crc_errors += val;
9091
9092                 return tp->phy_crc_errors;
9093         }
9094
9095         return get_stat64(&hw_stats->rx_fcs_errors);
9096 }
9097
9098 #define ESTAT_ADD(member) \
9099         estats->member =        old_estats->member + \
9100                                 get_estat64(&hw_stats->member)
9101
9102 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9103 {
9104         struct tg3_ethtool_stats *estats = &tp->estats;
9105         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9106         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9107
9108         if (!hw_stats)
9109                 return old_estats;
9110
9111         ESTAT_ADD(rx_octets);
9112         ESTAT_ADD(rx_fragments);
9113         ESTAT_ADD(rx_ucast_packets);
9114         ESTAT_ADD(rx_mcast_packets);
9115         ESTAT_ADD(rx_bcast_packets);
9116         ESTAT_ADD(rx_fcs_errors);
9117         ESTAT_ADD(rx_align_errors);
9118         ESTAT_ADD(rx_xon_pause_rcvd);
9119         ESTAT_ADD(rx_xoff_pause_rcvd);
9120         ESTAT_ADD(rx_mac_ctrl_rcvd);
9121         ESTAT_ADD(rx_xoff_entered);
9122         ESTAT_ADD(rx_frame_too_long_errors);
9123         ESTAT_ADD(rx_jabbers);
9124         ESTAT_ADD(rx_undersize_packets);
9125         ESTAT_ADD(rx_in_length_errors);
9126         ESTAT_ADD(rx_out_length_errors);
9127         ESTAT_ADD(rx_64_or_less_octet_packets);
9128         ESTAT_ADD(rx_65_to_127_octet_packets);
9129         ESTAT_ADD(rx_128_to_255_octet_packets);
9130         ESTAT_ADD(rx_256_to_511_octet_packets);
9131         ESTAT_ADD(rx_512_to_1023_octet_packets);
9132         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9133         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9134         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9135         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9136         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9137
9138         ESTAT_ADD(tx_octets);
9139         ESTAT_ADD(tx_collisions);
9140         ESTAT_ADD(tx_xon_sent);
9141         ESTAT_ADD(tx_xoff_sent);
9142         ESTAT_ADD(tx_flow_control);
9143         ESTAT_ADD(tx_mac_errors);
9144         ESTAT_ADD(tx_single_collisions);
9145         ESTAT_ADD(tx_mult_collisions);
9146         ESTAT_ADD(tx_deferred);
9147         ESTAT_ADD(tx_excessive_collisions);
9148         ESTAT_ADD(tx_late_collisions);
9149         ESTAT_ADD(tx_collide_2times);
9150         ESTAT_ADD(tx_collide_3times);
9151         ESTAT_ADD(tx_collide_4times);
9152         ESTAT_ADD(tx_collide_5times);
9153         ESTAT_ADD(tx_collide_6times);
9154         ESTAT_ADD(tx_collide_7times);
9155         ESTAT_ADD(tx_collide_8times);
9156         ESTAT_ADD(tx_collide_9times);
9157         ESTAT_ADD(tx_collide_10times);
9158         ESTAT_ADD(tx_collide_11times);
9159         ESTAT_ADD(tx_collide_12times);
9160         ESTAT_ADD(tx_collide_13times);
9161         ESTAT_ADD(tx_collide_14times);
9162         ESTAT_ADD(tx_collide_15times);
9163         ESTAT_ADD(tx_ucast_packets);
9164         ESTAT_ADD(tx_mcast_packets);
9165         ESTAT_ADD(tx_bcast_packets);
9166         ESTAT_ADD(tx_carrier_sense_errors);
9167         ESTAT_ADD(tx_discards);
9168         ESTAT_ADD(tx_errors);
9169
9170         ESTAT_ADD(dma_writeq_full);
9171         ESTAT_ADD(dma_write_prioq_full);
9172         ESTAT_ADD(rxbds_empty);
9173         ESTAT_ADD(rx_discards);
9174         ESTAT_ADD(rx_errors);
9175         ESTAT_ADD(rx_threshold_hit);
9176
9177         ESTAT_ADD(dma_readq_full);
9178         ESTAT_ADD(dma_read_prioq_full);
9179         ESTAT_ADD(tx_comp_queue_full);
9180
9181         ESTAT_ADD(ring_set_send_prod_index);
9182         ESTAT_ADD(ring_status_update);
9183         ESTAT_ADD(nic_irqs);
9184         ESTAT_ADD(nic_avoided_irqs);
9185         ESTAT_ADD(nic_tx_threshold_hit);
9186
9187         return estats;
9188 }
9189
9190 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9191 {
9192         struct tg3 *tp = netdev_priv(dev);
9193         struct net_device_stats *stats = &tp->net_stats;
9194         struct net_device_stats *old_stats = &tp->net_stats_prev;
9195         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9196
9197         if (!hw_stats)
9198                 return old_stats;
9199
9200         stats->rx_packets = old_stats->rx_packets +
9201                 get_stat64(&hw_stats->rx_ucast_packets) +
9202                 get_stat64(&hw_stats->rx_mcast_packets) +
9203                 get_stat64(&hw_stats->rx_bcast_packets);
9204
9205         stats->tx_packets = old_stats->tx_packets +
9206                 get_stat64(&hw_stats->tx_ucast_packets) +
9207                 get_stat64(&hw_stats->tx_mcast_packets) +
9208                 get_stat64(&hw_stats->tx_bcast_packets);
9209
9210         stats->rx_bytes = old_stats->rx_bytes +
9211                 get_stat64(&hw_stats->rx_octets);
9212         stats->tx_bytes = old_stats->tx_bytes +
9213                 get_stat64(&hw_stats->tx_octets);
9214
9215         stats->rx_errors = old_stats->rx_errors +
9216                 get_stat64(&hw_stats->rx_errors);
9217         stats->tx_errors = old_stats->tx_errors +
9218                 get_stat64(&hw_stats->tx_errors) +
9219                 get_stat64(&hw_stats->tx_mac_errors) +
9220                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9221                 get_stat64(&hw_stats->tx_discards);
9222
9223         stats->multicast = old_stats->multicast +
9224                 get_stat64(&hw_stats->rx_mcast_packets);
9225         stats->collisions = old_stats->collisions +
9226                 get_stat64(&hw_stats->tx_collisions);
9227
9228         stats->rx_length_errors = old_stats->rx_length_errors +
9229                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9230                 get_stat64(&hw_stats->rx_undersize_packets);
9231
9232         stats->rx_over_errors = old_stats->rx_over_errors +
9233                 get_stat64(&hw_stats->rxbds_empty);
9234         stats->rx_frame_errors = old_stats->rx_frame_errors +
9235                 get_stat64(&hw_stats->rx_align_errors);
9236         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9237                 get_stat64(&hw_stats->tx_discards);
9238         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9239                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9240
9241         stats->rx_crc_errors = old_stats->rx_crc_errors +
9242                 calc_crc_errors(tp);
9243
9244         stats->rx_missed_errors = old_stats->rx_missed_errors +
9245                 get_stat64(&hw_stats->rx_discards);
9246
9247         return stats;
9248 }
9249
9250 static inline u32 calc_crc(unsigned char *buf, int len)
9251 {
9252         u32 reg;
9253         u32 tmp;
9254         int j, k;
9255
9256         reg = 0xffffffff;
9257
9258         for (j = 0; j < len; j++) {
9259                 reg ^= buf[j];
9260
9261                 for (k = 0; k < 8; k++) {
9262                         tmp = reg & 0x01;
9263
9264                         reg >>= 1;
9265
9266                         if (tmp)
9267                                 reg ^= 0xedb88320;
9268                 }
9269         }
9270
9271         return ~reg;
9272 }
9273
9274 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9275 {
9276         /* accept or reject all multicast frames */
9277         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9278         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9279         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9280         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9281 }
9282
9283 static void __tg3_set_rx_mode(struct net_device *dev)
9284 {
9285         struct tg3 *tp = netdev_priv(dev);
9286         u32 rx_mode;
9287
9288         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9289                                   RX_MODE_KEEP_VLAN_TAG);
9290
9291         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9292          * flag clear.
9293          */
9294 #if TG3_VLAN_TAG_USED
9295         if (!tp->vlgrp &&
9296             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9297                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9298 #else
9299         /* By definition, VLAN is disabled always in this
9300          * case.
9301          */
9302         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9303                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9304 #endif
9305
9306         if (dev->flags & IFF_PROMISC) {
9307                 /* Promiscuous mode. */
9308                 rx_mode |= RX_MODE_PROMISC;
9309         } else if (dev->flags & IFF_ALLMULTI) {
9310                 /* Accept all multicast. */
9311                 tg3_set_multi(tp, 1);
9312         } else if (netdev_mc_empty(dev)) {
9313                 /* Reject all multicast. */
9314                 tg3_set_multi(tp, 0);
9315         } else {
9316                 /* Accept one or more multicast(s). */
9317                 struct netdev_hw_addr *ha;
9318                 u32 mc_filter[4] = { 0, };
9319                 u32 regidx;
9320                 u32 bit;
9321                 u32 crc;
9322
9323                 netdev_for_each_mc_addr(ha, dev) {
9324                         crc = calc_crc(ha->addr, ETH_ALEN);
9325                         bit = ~crc & 0x7f;
9326                         regidx = (bit & 0x60) >> 5;
9327                         bit &= 0x1f;
9328                         mc_filter[regidx] |= (1 << bit);
9329                 }
9330
9331                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9332                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9333                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9334                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9335         }
9336
9337         if (rx_mode != tp->rx_mode) {
9338                 tp->rx_mode = rx_mode;
9339                 tw32_f(MAC_RX_MODE, rx_mode);
9340                 udelay(10);
9341         }
9342 }
9343
9344 static void tg3_set_rx_mode(struct net_device *dev)
9345 {
9346         struct tg3 *tp = netdev_priv(dev);
9347
9348         if (!netif_running(dev))
9349                 return;
9350
9351         tg3_full_lock(tp, 0);
9352         __tg3_set_rx_mode(dev);
9353         tg3_full_unlock(tp);
9354 }
9355
9356 #define TG3_REGDUMP_LEN         (32 * 1024)
9357
9358 static int tg3_get_regs_len(struct net_device *dev)
9359 {
9360         return TG3_REGDUMP_LEN;
9361 }
9362
9363 static void tg3_get_regs(struct net_device *dev,
9364                 struct ethtool_regs *regs, void *_p)
9365 {
9366         u32 *p = _p;
9367         struct tg3 *tp = netdev_priv(dev);
9368         u8 *orig_p = _p;
9369         int i;
9370
9371         regs->version = 0;
9372
9373         memset(p, 0, TG3_REGDUMP_LEN);
9374
9375         if (tp->link_config.phy_is_low_power)
9376                 return;
9377
9378         tg3_full_lock(tp, 0);
9379
9380 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9381 #define GET_REG32_LOOP(base,len)                \
9382 do {    p = (u32 *)(orig_p + (base));           \
9383         for (i = 0; i < len; i += 4)            \
9384                 __GET_REG32((base) + i);        \
9385 } while (0)
9386 #define GET_REG32_1(reg)                        \
9387 do {    p = (u32 *)(orig_p + (reg));            \
9388         __GET_REG32((reg));                     \
9389 } while (0)
9390
9391         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9392         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9393         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9394         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9395         GET_REG32_1(SNDDATAC_MODE);
9396         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9397         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9398         GET_REG32_1(SNDBDC_MODE);
9399         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9400         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9401         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9402         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9403         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9404         GET_REG32_1(RCVDCC_MODE);
9405         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9406         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9407         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9408         GET_REG32_1(MBFREE_MODE);
9409         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9410         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9411         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9412         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9413         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9414         GET_REG32_1(RX_CPU_MODE);
9415         GET_REG32_1(RX_CPU_STATE);
9416         GET_REG32_1(RX_CPU_PGMCTR);
9417         GET_REG32_1(RX_CPU_HWBKPT);
9418         GET_REG32_1(TX_CPU_MODE);
9419         GET_REG32_1(TX_CPU_STATE);
9420         GET_REG32_1(TX_CPU_PGMCTR);
9421         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9422         GET_REG32_LOOP(FTQ_RESET, 0x120);
9423         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9424         GET_REG32_1(DMAC_MODE);
9425         GET_REG32_LOOP(GRC_MODE, 0x4c);
9426         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9427                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9428
9429 #undef __GET_REG32
9430 #undef GET_REG32_LOOP
9431 #undef GET_REG32_1
9432
9433         tg3_full_unlock(tp);
9434 }
9435
9436 static int tg3_get_eeprom_len(struct net_device *dev)
9437 {
9438         struct tg3 *tp = netdev_priv(dev);
9439
9440         return tp->nvram_size;
9441 }
9442
9443 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9444 {
9445         struct tg3 *tp = netdev_priv(dev);
9446         int ret;
9447         u8  *pd;
9448         u32 i, offset, len, b_offset, b_count;
9449         __be32 val;
9450
9451         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9452                 return -EINVAL;
9453
9454         if (tp->link_config.phy_is_low_power)
9455                 return -EAGAIN;
9456
9457         offset = eeprom->offset;
9458         len = eeprom->len;
9459         eeprom->len = 0;
9460
9461         eeprom->magic = TG3_EEPROM_MAGIC;
9462
9463         if (offset & 3) {
9464                 /* adjustments to start on required 4 byte boundary */
9465                 b_offset = offset & 3;
9466                 b_count = 4 - b_offset;
9467                 if (b_count > len) {
9468                         /* i.e. offset=1 len=2 */
9469                         b_count = len;
9470                 }
9471                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9472                 if (ret)
9473                         return ret;
9474                 memcpy(data, ((char*)&val) + b_offset, b_count);
9475                 len -= b_count;
9476                 offset += b_count;
9477                 eeprom->len += b_count;
9478         }
9479
9480         /* read bytes upto the last 4 byte boundary */
9481         pd = &data[eeprom->len];
9482         for (i = 0; i < (len - (len & 3)); i += 4) {
9483                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9484                 if (ret) {
9485                         eeprom->len += i;
9486                         return ret;
9487                 }
9488                 memcpy(pd + i, &val, 4);
9489         }
9490         eeprom->len += i;
9491
9492         if (len & 3) {
9493                 /* read last bytes not ending on 4 byte boundary */
9494                 pd = &data[eeprom->len];
9495                 b_count = len & 3;
9496                 b_offset = offset + len - b_count;
9497                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9498                 if (ret)
9499                         return ret;
9500                 memcpy(pd, &val, b_count);
9501                 eeprom->len += b_count;
9502         }
9503         return 0;
9504 }
9505
9506 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9507
9508 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9509 {
9510         struct tg3 *tp = netdev_priv(dev);
9511         int ret;
9512         u32 offset, len, b_offset, odd_len;
9513         u8 *buf;
9514         __be32 start, end;
9515
9516         if (tp->link_config.phy_is_low_power)
9517                 return -EAGAIN;
9518
9519         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9520             eeprom->magic != TG3_EEPROM_MAGIC)
9521                 return -EINVAL;
9522
9523         offset = eeprom->offset;
9524         len = eeprom->len;
9525
9526         if ((b_offset = (offset & 3))) {
9527                 /* adjustments to start on required 4 byte boundary */
9528                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9529                 if (ret)
9530                         return ret;
9531                 len += b_offset;
9532                 offset &= ~3;
9533                 if (len < 4)
9534                         len = 4;
9535         }
9536
9537         odd_len = 0;
9538         if (len & 3) {
9539                 /* adjustments to end on required 4 byte boundary */
9540                 odd_len = 1;
9541                 len = (len + 3) & ~3;
9542                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9543                 if (ret)
9544                         return ret;
9545         }
9546
9547         buf = data;
9548         if (b_offset || odd_len) {
9549                 buf = kmalloc(len, GFP_KERNEL);
9550                 if (!buf)
9551                         return -ENOMEM;
9552                 if (b_offset)
9553                         memcpy(buf, &start, 4);
9554                 if (odd_len)
9555                         memcpy(buf+len-4, &end, 4);
9556                 memcpy(buf + b_offset, data, eeprom->len);
9557         }
9558
9559         ret = tg3_nvram_write_block(tp, offset, len, buf);
9560
9561         if (buf != data)
9562                 kfree(buf);
9563
9564         return ret;
9565 }
9566
9567 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9568 {
9569         struct tg3 *tp = netdev_priv(dev);
9570
9571         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9572                 struct phy_device *phydev;
9573                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9574                         return -EAGAIN;
9575                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9576                 return phy_ethtool_gset(phydev, cmd);
9577         }
9578
9579         cmd->supported = (SUPPORTED_Autoneg);
9580
9581         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9582                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9583                                    SUPPORTED_1000baseT_Full);
9584
9585         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9586                 cmd->supported |= (SUPPORTED_100baseT_Half |
9587                                   SUPPORTED_100baseT_Full |
9588                                   SUPPORTED_10baseT_Half |
9589                                   SUPPORTED_10baseT_Full |
9590                                   SUPPORTED_TP);
9591                 cmd->port = PORT_TP;
9592         } else {
9593                 cmd->supported |= SUPPORTED_FIBRE;
9594                 cmd->port = PORT_FIBRE;
9595         }
9596
9597         cmd->advertising = tp->link_config.advertising;
9598         if (netif_running(dev)) {
9599                 cmd->speed = tp->link_config.active_speed;
9600                 cmd->duplex = tp->link_config.active_duplex;
9601         }
9602         cmd->phy_address = tp->phy_addr;
9603         cmd->transceiver = XCVR_INTERNAL;
9604         cmd->autoneg = tp->link_config.autoneg;
9605         cmd->maxtxpkt = 0;
9606         cmd->maxrxpkt = 0;
9607         return 0;
9608 }
9609
9610 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9611 {
9612         struct tg3 *tp = netdev_priv(dev);
9613
9614         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9615                 struct phy_device *phydev;
9616                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9617                         return -EAGAIN;
9618                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9619                 return phy_ethtool_sset(phydev, cmd);
9620         }
9621
9622         if (cmd->autoneg != AUTONEG_ENABLE &&
9623             cmd->autoneg != AUTONEG_DISABLE)
9624                 return -EINVAL;
9625
9626         if (cmd->autoneg == AUTONEG_DISABLE &&
9627             cmd->duplex != DUPLEX_FULL &&
9628             cmd->duplex != DUPLEX_HALF)
9629                 return -EINVAL;
9630
9631         if (cmd->autoneg == AUTONEG_ENABLE) {
9632                 u32 mask = ADVERTISED_Autoneg |
9633                            ADVERTISED_Pause |
9634                            ADVERTISED_Asym_Pause;
9635
9636                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9637                         mask |= ADVERTISED_1000baseT_Half |
9638                                 ADVERTISED_1000baseT_Full;
9639
9640                 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9641                         mask |= ADVERTISED_100baseT_Half |
9642                                 ADVERTISED_100baseT_Full |
9643                                 ADVERTISED_10baseT_Half |
9644                                 ADVERTISED_10baseT_Full |
9645                                 ADVERTISED_TP;
9646                 else
9647                         mask |= ADVERTISED_FIBRE;
9648
9649                 if (cmd->advertising & ~mask)
9650                         return -EINVAL;
9651
9652                 mask &= (ADVERTISED_1000baseT_Half |
9653                          ADVERTISED_1000baseT_Full |
9654                          ADVERTISED_100baseT_Half |
9655                          ADVERTISED_100baseT_Full |
9656                          ADVERTISED_10baseT_Half |
9657                          ADVERTISED_10baseT_Full);
9658
9659                 cmd->advertising &= mask;
9660         } else {
9661                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9662                         if (cmd->speed != SPEED_1000)
9663                                 return -EINVAL;
9664
9665                         if (cmd->duplex != DUPLEX_FULL)
9666                                 return -EINVAL;
9667                 } else {
9668                         if (cmd->speed != SPEED_100 &&
9669                             cmd->speed != SPEED_10)
9670                                 return -EINVAL;
9671                 }
9672         }
9673
9674         tg3_full_lock(tp, 0);
9675
9676         tp->link_config.autoneg = cmd->autoneg;
9677         if (cmd->autoneg == AUTONEG_ENABLE) {
9678                 tp->link_config.advertising = (cmd->advertising |
9679                                               ADVERTISED_Autoneg);
9680                 tp->link_config.speed = SPEED_INVALID;
9681                 tp->link_config.duplex = DUPLEX_INVALID;
9682         } else {
9683                 tp->link_config.advertising = 0;
9684                 tp->link_config.speed = cmd->speed;
9685                 tp->link_config.duplex = cmd->duplex;
9686         }
9687
9688         tp->link_config.orig_speed = tp->link_config.speed;
9689         tp->link_config.orig_duplex = tp->link_config.duplex;
9690         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9691
9692         if (netif_running(dev))
9693                 tg3_setup_phy(tp, 1);
9694
9695         tg3_full_unlock(tp);
9696
9697         return 0;
9698 }
9699
9700 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9701 {
9702         struct tg3 *tp = netdev_priv(dev);
9703
9704         strcpy(info->driver, DRV_MODULE_NAME);
9705         strcpy(info->version, DRV_MODULE_VERSION);
9706         strcpy(info->fw_version, tp->fw_ver);
9707         strcpy(info->bus_info, pci_name(tp->pdev));
9708 }
9709
9710 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9711 {
9712         struct tg3 *tp = netdev_priv(dev);
9713
9714         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9715             device_can_wakeup(&tp->pdev->dev))
9716                 wol->supported = WAKE_MAGIC;
9717         else
9718                 wol->supported = 0;
9719         wol->wolopts = 0;
9720         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9721             device_can_wakeup(&tp->pdev->dev))
9722                 wol->wolopts = WAKE_MAGIC;
9723         memset(&wol->sopass, 0, sizeof(wol->sopass));
9724 }
9725
9726 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9727 {
9728         struct tg3 *tp = netdev_priv(dev);
9729         struct device *dp = &tp->pdev->dev;
9730
9731         if (wol->wolopts & ~WAKE_MAGIC)
9732                 return -EINVAL;
9733         if ((wol->wolopts & WAKE_MAGIC) &&
9734             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9735                 return -EINVAL;
9736
9737         spin_lock_bh(&tp->lock);
9738         if (wol->wolopts & WAKE_MAGIC) {
9739                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9740                 device_set_wakeup_enable(dp, true);
9741         } else {
9742                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9743                 device_set_wakeup_enable(dp, false);
9744         }
9745         spin_unlock_bh(&tp->lock);
9746
9747         return 0;
9748 }
9749
9750 static u32 tg3_get_msglevel(struct net_device *dev)
9751 {
9752         struct tg3 *tp = netdev_priv(dev);
9753         return tp->msg_enable;
9754 }
9755
9756 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9757 {
9758         struct tg3 *tp = netdev_priv(dev);
9759         tp->msg_enable = value;
9760 }
9761
9762 static int tg3_set_tso(struct net_device *dev, u32 value)
9763 {
9764         struct tg3 *tp = netdev_priv(dev);
9765
9766         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9767                 if (value)
9768                         return -EINVAL;
9769                 return 0;
9770         }
9771         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9772             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9773              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9774                 if (value) {
9775                         dev->features |= NETIF_F_TSO6;
9776                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9777                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9778                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9779                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9780                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9781                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9782                                 dev->features |= NETIF_F_TSO_ECN;
9783                 } else
9784                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9785         }
9786         return ethtool_op_set_tso(dev, value);
9787 }
9788
9789 static int tg3_nway_reset(struct net_device *dev)
9790 {
9791         struct tg3 *tp = netdev_priv(dev);
9792         int r;
9793
9794         if (!netif_running(dev))
9795                 return -EAGAIN;
9796
9797         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9798                 return -EINVAL;
9799
9800         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9801                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9802                         return -EAGAIN;
9803                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9804         } else {
9805                 u32 bmcr;
9806
9807                 spin_lock_bh(&tp->lock);
9808                 r = -EINVAL;
9809                 tg3_readphy(tp, MII_BMCR, &bmcr);
9810                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9811                     ((bmcr & BMCR_ANENABLE) ||
9812                      (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9813                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9814                                                    BMCR_ANENABLE);
9815                         r = 0;
9816                 }
9817                 spin_unlock_bh(&tp->lock);
9818         }
9819
9820         return r;
9821 }
9822
9823 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9824 {
9825         struct tg3 *tp = netdev_priv(dev);
9826
9827         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9828         ering->rx_mini_max_pending = 0;
9829         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9830                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9831         else
9832                 ering->rx_jumbo_max_pending = 0;
9833
9834         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9835
9836         ering->rx_pending = tp->rx_pending;
9837         ering->rx_mini_pending = 0;
9838         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9839                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9840         else
9841                 ering->rx_jumbo_pending = 0;
9842
9843         ering->tx_pending = tp->napi[0].tx_pending;
9844 }
9845
9846 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9847 {
9848         struct tg3 *tp = netdev_priv(dev);
9849         int i, irq_sync = 0, err = 0;
9850
9851         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9852             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9853             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9854             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9855             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9856              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9857                 return -EINVAL;
9858
9859         if (netif_running(dev)) {
9860                 tg3_phy_stop(tp);
9861                 tg3_netif_stop(tp);
9862                 irq_sync = 1;
9863         }
9864
9865         tg3_full_lock(tp, irq_sync);
9866
9867         tp->rx_pending = ering->rx_pending;
9868
9869         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9870             tp->rx_pending > 63)
9871                 tp->rx_pending = 63;
9872         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9873
9874         for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9875                 tp->napi[i].tx_pending = ering->tx_pending;
9876
9877         if (netif_running(dev)) {
9878                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9879                 err = tg3_restart_hw(tp, 1);
9880                 if (!err)
9881                         tg3_netif_start(tp);
9882         }
9883
9884         tg3_full_unlock(tp);
9885
9886         if (irq_sync && !err)
9887                 tg3_phy_start(tp);
9888
9889         return err;
9890 }
9891
9892 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9893 {
9894         struct tg3 *tp = netdev_priv(dev);
9895
9896         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9897
9898         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9899                 epause->rx_pause = 1;
9900         else
9901                 epause->rx_pause = 0;
9902
9903         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9904                 epause->tx_pause = 1;
9905         else
9906                 epause->tx_pause = 0;
9907 }
9908
9909 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9910 {
9911         struct tg3 *tp = netdev_priv(dev);
9912         int err = 0;
9913
9914         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9915                 u32 newadv;
9916                 struct phy_device *phydev;
9917
9918                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9919
9920                 if (!(phydev->supported & SUPPORTED_Pause) ||
9921                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9922                      ((epause->rx_pause && !epause->tx_pause) ||
9923                       (!epause->rx_pause && epause->tx_pause))))
9924                         return -EINVAL;
9925
9926                 tp->link_config.flowctrl = 0;
9927                 if (epause->rx_pause) {
9928                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9929
9930                         if (epause->tx_pause) {
9931                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9932                                 newadv = ADVERTISED_Pause;
9933                         } else
9934                                 newadv = ADVERTISED_Pause |
9935                                          ADVERTISED_Asym_Pause;
9936                 } else if (epause->tx_pause) {
9937                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9938                         newadv = ADVERTISED_Asym_Pause;
9939                 } else
9940                         newadv = 0;
9941
9942                 if (epause->autoneg)
9943                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9944                 else
9945                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9946
9947                 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
9948                         u32 oldadv = phydev->advertising &
9949                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9950                         if (oldadv != newadv) {
9951                                 phydev->advertising &=
9952                                         ~(ADVERTISED_Pause |
9953                                           ADVERTISED_Asym_Pause);
9954                                 phydev->advertising |= newadv;
9955                                 if (phydev->autoneg) {
9956                                         /*
9957                                          * Always renegotiate the link to
9958                                          * inform our link partner of our
9959                                          * flow control settings, even if the
9960                                          * flow control is forced.  Let
9961                                          * tg3_adjust_link() do the final
9962                                          * flow control setup.
9963                                          */
9964                                         return phy_start_aneg(phydev);
9965                                 }
9966                         }
9967
9968                         if (!epause->autoneg)
9969                                 tg3_setup_flow_control(tp, 0, 0);
9970                 } else {
9971                         tp->link_config.orig_advertising &=
9972                                         ~(ADVERTISED_Pause |
9973                                           ADVERTISED_Asym_Pause);
9974                         tp->link_config.orig_advertising |= newadv;
9975                 }
9976         } else {
9977                 int irq_sync = 0;
9978
9979                 if (netif_running(dev)) {
9980                         tg3_netif_stop(tp);
9981                         irq_sync = 1;
9982                 }
9983
9984                 tg3_full_lock(tp, irq_sync);
9985
9986                 if (epause->autoneg)
9987                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9988                 else
9989                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9990                 if (epause->rx_pause)
9991                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9992                 else
9993                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
9994                 if (epause->tx_pause)
9995                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9996                 else
9997                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
9998
9999                 if (netif_running(dev)) {
10000                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10001                         err = tg3_restart_hw(tp, 1);
10002                         if (!err)
10003                                 tg3_netif_start(tp);
10004                 }
10005
10006                 tg3_full_unlock(tp);
10007         }
10008
10009         return err;
10010 }
10011
10012 static u32 tg3_get_rx_csum(struct net_device *dev)
10013 {
10014         struct tg3 *tp = netdev_priv(dev);
10015         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10016 }
10017
10018 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10019 {
10020         struct tg3 *tp = netdev_priv(dev);
10021
10022         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10023                 if (data != 0)
10024                         return -EINVAL;
10025                 return 0;
10026         }
10027
10028         spin_lock_bh(&tp->lock);
10029         if (data)
10030                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10031         else
10032                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10033         spin_unlock_bh(&tp->lock);
10034
10035         return 0;
10036 }
10037
10038 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10039 {
10040         struct tg3 *tp = netdev_priv(dev);
10041
10042         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10043                 if (data != 0)
10044                         return -EINVAL;
10045                 return 0;
10046         }
10047
10048         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10049                 ethtool_op_set_tx_ipv6_csum(dev, data);
10050         else
10051                 ethtool_op_set_tx_csum(dev, data);
10052
10053         return 0;
10054 }
10055
10056 static int tg3_get_sset_count(struct net_device *dev, int sset)
10057 {
10058         switch (sset) {
10059         case ETH_SS_TEST:
10060                 return TG3_NUM_TEST;
10061         case ETH_SS_STATS:
10062                 return TG3_NUM_STATS;
10063         default:
10064                 return -EOPNOTSUPP;
10065         }
10066 }
10067
10068 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10069 {
10070         switch (stringset) {
10071         case ETH_SS_STATS:
10072                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10073                 break;
10074         case ETH_SS_TEST:
10075                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10076                 break;
10077         default:
10078                 WARN_ON(1);     /* we need a WARN() */
10079                 break;
10080         }
10081 }
10082
10083 static int tg3_phys_id(struct net_device *dev, u32 data)
10084 {
10085         struct tg3 *tp = netdev_priv(dev);
10086         int i;
10087
10088         if (!netif_running(tp->dev))
10089                 return -EAGAIN;
10090
10091         if (data == 0)
10092                 data = UINT_MAX / 2;
10093
10094         for (i = 0; i < (data * 2); i++) {
10095                 if ((i % 2) == 0)
10096                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10097                                            LED_CTRL_1000MBPS_ON |
10098                                            LED_CTRL_100MBPS_ON |
10099                                            LED_CTRL_10MBPS_ON |
10100                                            LED_CTRL_TRAFFIC_OVERRIDE |
10101                                            LED_CTRL_TRAFFIC_BLINK |
10102                                            LED_CTRL_TRAFFIC_LED);
10103
10104                 else
10105                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10106                                            LED_CTRL_TRAFFIC_OVERRIDE);
10107
10108                 if (msleep_interruptible(500))
10109                         break;
10110         }
10111         tw32(MAC_LED_CTRL, tp->led_ctrl);
10112         return 0;
10113 }
10114
10115 static void tg3_get_ethtool_stats(struct net_device *dev,
10116                                    struct ethtool_stats *estats, u64 *tmp_stats)
10117 {
10118         struct tg3 *tp = netdev_priv(dev);
10119         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10120 }
10121
10122 #define NVRAM_TEST_SIZE 0x100
10123 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10124 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10125 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10126 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10127 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10128
10129 static int tg3_test_nvram(struct tg3 *tp)
10130 {
10131         u32 csum, magic;
10132         __be32 *buf;
10133         int i, j, k, err = 0, size;
10134
10135         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10136                 return 0;
10137
10138         if (tg3_nvram_read(tp, 0, &magic) != 0)
10139                 return -EIO;
10140
10141         if (magic == TG3_EEPROM_MAGIC)
10142                 size = NVRAM_TEST_SIZE;
10143         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10144                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10145                     TG3_EEPROM_SB_FORMAT_1) {
10146                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10147                         case TG3_EEPROM_SB_REVISION_0:
10148                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10149                                 break;
10150                         case TG3_EEPROM_SB_REVISION_2:
10151                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10152                                 break;
10153                         case TG3_EEPROM_SB_REVISION_3:
10154                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10155                                 break;
10156                         default:
10157                                 return 0;
10158                         }
10159                 } else
10160                         return 0;
10161         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10162                 size = NVRAM_SELFBOOT_HW_SIZE;
10163         else
10164                 return -EIO;
10165
10166         buf = kmalloc(size, GFP_KERNEL);
10167         if (buf == NULL)
10168                 return -ENOMEM;
10169
10170         err = -EIO;
10171         for (i = 0, j = 0; i < size; i += 4, j++) {
10172                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10173                 if (err)
10174                         break;
10175         }
10176         if (i < size)
10177                 goto out;
10178
10179         /* Selfboot format */
10180         magic = be32_to_cpu(buf[0]);
10181         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10182             TG3_EEPROM_MAGIC_FW) {
10183                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10184
10185                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10186                     TG3_EEPROM_SB_REVISION_2) {
10187                         /* For rev 2, the csum doesn't include the MBA. */
10188                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10189                                 csum8 += buf8[i];
10190                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10191                                 csum8 += buf8[i];
10192                 } else {
10193                         for (i = 0; i < size; i++)
10194                                 csum8 += buf8[i];
10195                 }
10196
10197                 if (csum8 == 0) {
10198                         err = 0;
10199                         goto out;
10200                 }
10201
10202                 err = -EIO;
10203                 goto out;
10204         }
10205
10206         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10207             TG3_EEPROM_MAGIC_HW) {
10208                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10209                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10210                 u8 *buf8 = (u8 *) buf;
10211
10212                 /* Separate the parity bits and the data bytes.  */
10213                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10214                         if ((i == 0) || (i == 8)) {
10215                                 int l;
10216                                 u8 msk;
10217
10218                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10219                                         parity[k++] = buf8[i] & msk;
10220                                 i++;
10221                         } else if (i == 16) {
10222                                 int l;
10223                                 u8 msk;
10224
10225                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10226                                         parity[k++] = buf8[i] & msk;
10227                                 i++;
10228
10229                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10230                                         parity[k++] = buf8[i] & msk;
10231                                 i++;
10232                         }
10233                         data[j++] = buf8[i];
10234                 }
10235
10236                 err = -EIO;
10237                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10238                         u8 hw8 = hweight8(data[i]);
10239
10240                         if ((hw8 & 0x1) && parity[i])
10241                                 goto out;
10242                         else if (!(hw8 & 0x1) && !parity[i])
10243                                 goto out;
10244                 }
10245                 err = 0;
10246                 goto out;
10247         }
10248
10249         /* Bootstrap checksum at offset 0x10 */
10250         csum = calc_crc((unsigned char *) buf, 0x10);
10251         if (csum != be32_to_cpu(buf[0x10/4]))
10252                 goto out;
10253
10254         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10255         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10256         if (csum != be32_to_cpu(buf[0xfc/4]))
10257                 goto out;
10258
10259         err = 0;
10260
10261 out:
10262         kfree(buf);
10263         return err;
10264 }
10265
10266 #define TG3_SERDES_TIMEOUT_SEC  2
10267 #define TG3_COPPER_TIMEOUT_SEC  6
10268
10269 static int tg3_test_link(struct tg3 *tp)
10270 {
10271         int i, max;
10272
10273         if (!netif_running(tp->dev))
10274                 return -ENODEV;
10275
10276         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10277                 max = TG3_SERDES_TIMEOUT_SEC;
10278         else
10279                 max = TG3_COPPER_TIMEOUT_SEC;
10280
10281         for (i = 0; i < max; i++) {
10282                 if (netif_carrier_ok(tp->dev))
10283                         return 0;
10284
10285                 if (msleep_interruptible(1000))
10286                         break;
10287         }
10288
10289         return -EIO;
10290 }
10291
10292 /* Only test the commonly used registers */
10293 static int tg3_test_registers(struct tg3 *tp)
10294 {
10295         int i, is_5705, is_5750;
10296         u32 offset, read_mask, write_mask, val, save_val, read_val;
10297         static struct {
10298                 u16 offset;
10299                 u16 flags;
10300 #define TG3_FL_5705     0x1
10301 #define TG3_FL_NOT_5705 0x2
10302 #define TG3_FL_NOT_5788 0x4
10303 #define TG3_FL_NOT_5750 0x8
10304                 u32 read_mask;
10305                 u32 write_mask;
10306         } reg_tbl[] = {
10307                 /* MAC Control Registers */
10308                 { MAC_MODE, TG3_FL_NOT_5705,
10309                         0x00000000, 0x00ef6f8c },
10310                 { MAC_MODE, TG3_FL_5705,
10311                         0x00000000, 0x01ef6b8c },
10312                 { MAC_STATUS, TG3_FL_NOT_5705,
10313                         0x03800107, 0x00000000 },
10314                 { MAC_STATUS, TG3_FL_5705,
10315                         0x03800100, 0x00000000 },
10316                 { MAC_ADDR_0_HIGH, 0x0000,
10317                         0x00000000, 0x0000ffff },
10318                 { MAC_ADDR_0_LOW, 0x0000,
10319                         0x00000000, 0xffffffff },
10320                 { MAC_RX_MTU_SIZE, 0x0000,
10321                         0x00000000, 0x0000ffff },
10322                 { MAC_TX_MODE, 0x0000,
10323                         0x00000000, 0x00000070 },
10324                 { MAC_TX_LENGTHS, 0x0000,
10325                         0x00000000, 0x00003fff },
10326                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10327                         0x00000000, 0x000007fc },
10328                 { MAC_RX_MODE, TG3_FL_5705,
10329                         0x00000000, 0x000007dc },
10330                 { MAC_HASH_REG_0, 0x0000,
10331                         0x00000000, 0xffffffff },
10332                 { MAC_HASH_REG_1, 0x0000,
10333                         0x00000000, 0xffffffff },
10334                 { MAC_HASH_REG_2, 0x0000,
10335                         0x00000000, 0xffffffff },
10336                 { MAC_HASH_REG_3, 0x0000,
10337                         0x00000000, 0xffffffff },
10338
10339                 /* Receive Data and Receive BD Initiator Control Registers. */
10340                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10341                         0x00000000, 0xffffffff },
10342                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10343                         0x00000000, 0xffffffff },
10344                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10345                         0x00000000, 0x00000003 },
10346                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10347                         0x00000000, 0xffffffff },
10348                 { RCVDBDI_STD_BD+0, 0x0000,
10349                         0x00000000, 0xffffffff },
10350                 { RCVDBDI_STD_BD+4, 0x0000,
10351                         0x00000000, 0xffffffff },
10352                 { RCVDBDI_STD_BD+8, 0x0000,
10353                         0x00000000, 0xffff0002 },
10354                 { RCVDBDI_STD_BD+0xc, 0x0000,
10355                         0x00000000, 0xffffffff },
10356
10357                 /* Receive BD Initiator Control Registers. */
10358                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10359                         0x00000000, 0xffffffff },
10360                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10361                         0x00000000, 0x000003ff },
10362                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10363                         0x00000000, 0xffffffff },
10364
10365                 /* Host Coalescing Control Registers. */
10366                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10367                         0x00000000, 0x00000004 },
10368                 { HOSTCC_MODE, TG3_FL_5705,
10369                         0x00000000, 0x000000f6 },
10370                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10371                         0x00000000, 0xffffffff },
10372                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10373                         0x00000000, 0x000003ff },
10374                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10375                         0x00000000, 0xffffffff },
10376                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10377                         0x00000000, 0x000003ff },
10378                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10379                         0x00000000, 0xffffffff },
10380                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10381                         0x00000000, 0x000000ff },
10382                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10383                         0x00000000, 0xffffffff },
10384                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10385                         0x00000000, 0x000000ff },
10386                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10387                         0x00000000, 0xffffffff },
10388                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10391                         0x00000000, 0xffffffff },
10392                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10393                         0x00000000, 0x000000ff },
10394                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10395                         0x00000000, 0xffffffff },
10396                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10397                         0x00000000, 0x000000ff },
10398                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10399                         0x00000000, 0xffffffff },
10400                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10403                         0x00000000, 0xffffffff },
10404                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10407                         0x00000000, 0xffffffff },
10408                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10409                         0xffffffff, 0x00000000 },
10410                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10411                         0xffffffff, 0x00000000 },
10412
10413                 /* Buffer Manager Control Registers. */
10414                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10415                         0x00000000, 0x007fff80 },
10416                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10417                         0x00000000, 0x007fffff },
10418                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10419                         0x00000000, 0x0000003f },
10420                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10421                         0x00000000, 0x000001ff },
10422                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10423                         0x00000000, 0x000001ff },
10424                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10425                         0xffffffff, 0x00000000 },
10426                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10427                         0xffffffff, 0x00000000 },
10428
10429                 /* Mailbox Registers */
10430                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10431                         0x00000000, 0x000001ff },
10432                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10433                         0x00000000, 0x000001ff },
10434                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10435                         0x00000000, 0x000007ff },
10436                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10437                         0x00000000, 0x000001ff },
10438
10439                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10440         };
10441
10442         is_5705 = is_5750 = 0;
10443         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10444                 is_5705 = 1;
10445                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10446                         is_5750 = 1;
10447         }
10448
10449         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10450                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10451                         continue;
10452
10453                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10454                         continue;
10455
10456                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10457                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10458                         continue;
10459
10460                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10461                         continue;
10462
10463                 offset = (u32) reg_tbl[i].offset;
10464                 read_mask = reg_tbl[i].read_mask;
10465                 write_mask = reg_tbl[i].write_mask;
10466
10467                 /* Save the original register content */
10468                 save_val = tr32(offset);
10469
10470                 /* Determine the read-only value. */
10471                 read_val = save_val & read_mask;
10472
10473                 /* Write zero to the register, then make sure the read-only bits
10474                  * are not changed and the read/write bits are all zeros.
10475                  */
10476                 tw32(offset, 0);
10477
10478                 val = tr32(offset);
10479
10480                 /* Test the read-only and read/write bits. */
10481                 if (((val & read_mask) != read_val) || (val & write_mask))
10482                         goto out;
10483
10484                 /* Write ones to all the bits defined by RdMask and WrMask, then
10485                  * make sure the read-only bits are not changed and the
10486                  * read/write bits are all ones.
10487                  */
10488                 tw32(offset, read_mask | write_mask);
10489
10490                 val = tr32(offset);
10491
10492                 /* Test the read-only bits. */
10493                 if ((val & read_mask) != read_val)
10494                         goto out;
10495
10496                 /* Test the read/write bits. */
10497                 if ((val & write_mask) != write_mask)
10498                         goto out;
10499
10500                 tw32(offset, save_val);
10501         }
10502
10503         return 0;
10504
10505 out:
10506         if (netif_msg_hw(tp))
10507                 netdev_err(tp->dev,
10508                            "Register test failed at offset %x\n", offset);
10509         tw32(offset, save_val);
10510         return -EIO;
10511 }
10512
10513 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10514 {
10515         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10516         int i;
10517         u32 j;
10518
10519         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10520                 for (j = 0; j < len; j += 4) {
10521                         u32 val;
10522
10523                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10524                         tg3_read_mem(tp, offset + j, &val);
10525                         if (val != test_pattern[i])
10526                                 return -EIO;
10527                 }
10528         }
10529         return 0;
10530 }
10531
10532 static int tg3_test_memory(struct tg3 *tp)
10533 {
10534         static struct mem_entry {
10535                 u32 offset;
10536                 u32 len;
10537         } mem_tbl_570x[] = {
10538                 { 0x00000000, 0x00b50},
10539                 { 0x00002000, 0x1c000},
10540                 { 0xffffffff, 0x00000}
10541         }, mem_tbl_5705[] = {
10542                 { 0x00000100, 0x0000c},
10543                 { 0x00000200, 0x00008},
10544                 { 0x00004000, 0x00800},
10545                 { 0x00006000, 0x01000},
10546                 { 0x00008000, 0x02000},
10547                 { 0x00010000, 0x0e000},
10548                 { 0xffffffff, 0x00000}
10549         }, mem_tbl_5755[] = {
10550                 { 0x00000200, 0x00008},
10551                 { 0x00004000, 0x00800},
10552                 { 0x00006000, 0x00800},
10553                 { 0x00008000, 0x02000},
10554                 { 0x00010000, 0x0c000},
10555                 { 0xffffffff, 0x00000}
10556         }, mem_tbl_5906[] = {
10557                 { 0x00000200, 0x00008},
10558                 { 0x00004000, 0x00400},
10559                 { 0x00006000, 0x00400},
10560                 { 0x00008000, 0x01000},
10561                 { 0x00010000, 0x01000},
10562                 { 0xffffffff, 0x00000}
10563         }, mem_tbl_5717[] = {
10564                 { 0x00000200, 0x00008},
10565                 { 0x00010000, 0x0a000},
10566                 { 0x00020000, 0x13c00},
10567                 { 0xffffffff, 0x00000}
10568         }, mem_tbl_57765[] = {
10569                 { 0x00000200, 0x00008},
10570                 { 0x00004000, 0x00800},
10571                 { 0x00006000, 0x09800},
10572                 { 0x00010000, 0x0a000},
10573                 { 0xffffffff, 0x00000}
10574         };
10575         struct mem_entry *mem_tbl;
10576         int err = 0;
10577         int i;
10578
10579         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10580                 mem_tbl = mem_tbl_5717;
10581         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10582                 mem_tbl = mem_tbl_57765;
10583         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10584                 mem_tbl = mem_tbl_5755;
10585         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10586                 mem_tbl = mem_tbl_5906;
10587         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10588                 mem_tbl = mem_tbl_5705;
10589         else
10590                 mem_tbl = mem_tbl_570x;
10591
10592         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10593                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10594                     mem_tbl[i].len)) != 0)
10595                         break;
10596         }
10597
10598         return err;
10599 }
10600
10601 #define TG3_MAC_LOOPBACK        0
10602 #define TG3_PHY_LOOPBACK        1
10603
10604 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10605 {
10606         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10607         u32 desc_idx, coal_now;
10608         struct sk_buff *skb, *rx_skb;
10609         u8 *tx_data;
10610         dma_addr_t map;
10611         int num_pkts, tx_len, rx_len, i, err;
10612         struct tg3_rx_buffer_desc *desc;
10613         struct tg3_napi *tnapi, *rnapi;
10614         struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10615
10616         tnapi = &tp->napi[0];
10617         rnapi = &tp->napi[0];
10618         if (tp->irq_cnt > 1) {
10619                 rnapi = &tp->napi[1];
10620                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10621                         tnapi = &tp->napi[1];
10622         }
10623         coal_now = tnapi->coal_now | rnapi->coal_now;
10624
10625         if (loopback_mode == TG3_MAC_LOOPBACK) {
10626                 /* HW errata - mac loopback fails in some cases on 5780.
10627                  * Normal traffic and PHY loopback are not affected by
10628                  * errata.
10629                  */
10630                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10631                         return 0;
10632
10633                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10634                            MAC_MODE_PORT_INT_LPBACK;
10635                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10636                         mac_mode |= MAC_MODE_LINK_POLARITY;
10637                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10638                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10639                 else
10640                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10641                 tw32(MAC_MODE, mac_mode);
10642         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10643                 u32 val;
10644
10645                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10646                         tg3_phy_fet_toggle_apd(tp, false);
10647                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10648                 } else
10649                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10650
10651                 tg3_phy_toggle_automdix(tp, 0);
10652
10653                 tg3_writephy(tp, MII_BMCR, val);
10654                 udelay(40);
10655
10656                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10657                 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10658                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10659                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10660                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10661                         /* The write needs to be flushed for the AC131 */
10662                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10663                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10664                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10665                 } else
10666                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10667
10668                 /* reset to prevent losing 1st rx packet intermittently */
10669                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10670                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10671                         udelay(10);
10672                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10673                 }
10674                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10675                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10676                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10677                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10678                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10679                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10680                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10681                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10682                 }
10683                 tw32(MAC_MODE, mac_mode);
10684         } else {
10685                 return -EINVAL;
10686         }
10687
10688         err = -EIO;
10689
10690         tx_len = 1514;
10691         skb = netdev_alloc_skb(tp->dev, tx_len);
10692         if (!skb)
10693                 return -ENOMEM;
10694
10695         tx_data = skb_put(skb, tx_len);
10696         memcpy(tx_data, tp->dev->dev_addr, 6);
10697         memset(tx_data + 6, 0x0, 8);
10698
10699         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10700
10701         for (i = 14; i < tx_len; i++)
10702                 tx_data[i] = (u8) (i & 0xff);
10703
10704         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10705         if (pci_dma_mapping_error(tp->pdev, map)) {
10706                 dev_kfree_skb(skb);
10707                 return -EIO;
10708         }
10709
10710         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10711                rnapi->coal_now);
10712
10713         udelay(10);
10714
10715         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10716
10717         num_pkts = 0;
10718
10719         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10720
10721         tnapi->tx_prod++;
10722         num_pkts++;
10723
10724         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10725         tr32_mailbox(tnapi->prodmbox);
10726
10727         udelay(10);
10728
10729         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10730         for (i = 0; i < 35; i++) {
10731                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10732                        coal_now);
10733
10734                 udelay(10);
10735
10736                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10737                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10738                 if ((tx_idx == tnapi->tx_prod) &&
10739                     (rx_idx == (rx_start_idx + num_pkts)))
10740                         break;
10741         }
10742
10743         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10744         dev_kfree_skb(skb);
10745
10746         if (tx_idx != tnapi->tx_prod)
10747                 goto out;
10748
10749         if (rx_idx != rx_start_idx + num_pkts)
10750                 goto out;
10751
10752         desc = &rnapi->rx_rcb[rx_start_idx];
10753         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10754         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10755         if (opaque_key != RXD_OPAQUE_RING_STD)
10756                 goto out;
10757
10758         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10759             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10760                 goto out;
10761
10762         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10763         if (rx_len != tx_len)
10764                 goto out;
10765
10766         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10767
10768         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10769         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10770
10771         for (i = 14; i < tx_len; i++) {
10772                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10773                         goto out;
10774         }
10775         err = 0;
10776
10777         /* tg3_free_rings will unmap and free the rx_skb */
10778 out:
10779         return err;
10780 }
10781
10782 #define TG3_MAC_LOOPBACK_FAILED         1
10783 #define TG3_PHY_LOOPBACK_FAILED         2
10784 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10785                                          TG3_PHY_LOOPBACK_FAILED)
10786
10787 static int tg3_test_loopback(struct tg3 *tp)
10788 {
10789         int err = 0;
10790         u32 cpmuctrl = 0;
10791
10792         if (!netif_running(tp->dev))
10793                 return TG3_LOOPBACK_FAILED;
10794
10795         err = tg3_reset_hw(tp, 1);
10796         if (err)
10797                 return TG3_LOOPBACK_FAILED;
10798
10799         /* Turn off gphy autopowerdown. */
10800         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10801                 tg3_phy_toggle_apd(tp, false);
10802
10803         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10804                 int i;
10805                 u32 status;
10806
10807                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10808
10809                 /* Wait for up to 40 microseconds to acquire lock. */
10810                 for (i = 0; i < 4; i++) {
10811                         status = tr32(TG3_CPMU_MUTEX_GNT);
10812                         if (status == CPMU_MUTEX_GNT_DRIVER)
10813                                 break;
10814                         udelay(10);
10815                 }
10816
10817                 if (status != CPMU_MUTEX_GNT_DRIVER)
10818                         return TG3_LOOPBACK_FAILED;
10819
10820                 /* Turn off link-based power management. */
10821                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10822                 tw32(TG3_CPMU_CTRL,
10823                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10824                                   CPMU_CTRL_LINK_AWARE_MODE));
10825         }
10826
10827         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10828                 err |= TG3_MAC_LOOPBACK_FAILED;
10829
10830         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10831                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10832
10833                 /* Release the mutex */
10834                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10835         }
10836
10837         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10838             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10839                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10840                         err |= TG3_PHY_LOOPBACK_FAILED;
10841         }
10842
10843         /* Re-enable gphy autopowerdown. */
10844         if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10845                 tg3_phy_toggle_apd(tp, true);
10846
10847         return err;
10848 }
10849
10850 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10851                           u64 *data)
10852 {
10853         struct tg3 *tp = netdev_priv(dev);
10854
10855         if (tp->link_config.phy_is_low_power)
10856                 tg3_set_power_state(tp, PCI_D0);
10857
10858         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10859
10860         if (tg3_test_nvram(tp) != 0) {
10861                 etest->flags |= ETH_TEST_FL_FAILED;
10862                 data[0] = 1;
10863         }
10864         if (tg3_test_link(tp) != 0) {
10865                 etest->flags |= ETH_TEST_FL_FAILED;
10866                 data[1] = 1;
10867         }
10868         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10869                 int err, err2 = 0, irq_sync = 0;
10870
10871                 if (netif_running(dev)) {
10872                         tg3_phy_stop(tp);
10873                         tg3_netif_stop(tp);
10874                         irq_sync = 1;
10875                 }
10876
10877                 tg3_full_lock(tp, irq_sync);
10878
10879                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10880                 err = tg3_nvram_lock(tp);
10881                 tg3_halt_cpu(tp, RX_CPU_BASE);
10882                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10883                         tg3_halt_cpu(tp, TX_CPU_BASE);
10884                 if (!err)
10885                         tg3_nvram_unlock(tp);
10886
10887                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10888                         tg3_phy_reset(tp);
10889
10890                 if (tg3_test_registers(tp) != 0) {
10891                         etest->flags |= ETH_TEST_FL_FAILED;
10892                         data[2] = 1;
10893                 }
10894                 if (tg3_test_memory(tp) != 0) {
10895                         etest->flags |= ETH_TEST_FL_FAILED;
10896                         data[3] = 1;
10897                 }
10898                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10899                         etest->flags |= ETH_TEST_FL_FAILED;
10900
10901                 tg3_full_unlock(tp);
10902
10903                 if (tg3_test_interrupt(tp) != 0) {
10904                         etest->flags |= ETH_TEST_FL_FAILED;
10905                         data[5] = 1;
10906                 }
10907
10908                 tg3_full_lock(tp, 0);
10909
10910                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10911                 if (netif_running(dev)) {
10912                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10913                         err2 = tg3_restart_hw(tp, 1);
10914                         if (!err2)
10915                                 tg3_netif_start(tp);
10916                 }
10917
10918                 tg3_full_unlock(tp);
10919
10920                 if (irq_sync && !err2)
10921                         tg3_phy_start(tp);
10922         }
10923         if (tp->link_config.phy_is_low_power)
10924                 tg3_set_power_state(tp, PCI_D3hot);
10925
10926 }
10927
10928 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10929 {
10930         struct mii_ioctl_data *data = if_mii(ifr);
10931         struct tg3 *tp = netdev_priv(dev);
10932         int err;
10933
10934         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10935                 struct phy_device *phydev;
10936                 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10937                         return -EAGAIN;
10938                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10939                 return phy_mii_ioctl(phydev, data, cmd);
10940         }
10941
10942         switch (cmd) {
10943         case SIOCGMIIPHY:
10944                 data->phy_id = tp->phy_addr;
10945
10946                 /* fallthru */
10947         case SIOCGMIIREG: {
10948                 u32 mii_regval;
10949
10950                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10951                         break;                  /* We have no PHY */
10952
10953                 if (tp->link_config.phy_is_low_power)
10954                         return -EAGAIN;
10955
10956                 spin_lock_bh(&tp->lock);
10957                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10958                 spin_unlock_bh(&tp->lock);
10959
10960                 data->val_out = mii_regval;
10961
10962                 return err;
10963         }
10964
10965         case SIOCSMIIREG:
10966                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10967                         break;                  /* We have no PHY */
10968
10969                 if (tp->link_config.phy_is_low_power)
10970                         return -EAGAIN;
10971
10972                 spin_lock_bh(&tp->lock);
10973                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
10974                 spin_unlock_bh(&tp->lock);
10975
10976                 return err;
10977
10978         default:
10979                 /* do nothing */
10980                 break;
10981         }
10982         return -EOPNOTSUPP;
10983 }
10984
10985 #if TG3_VLAN_TAG_USED
10986 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
10987 {
10988         struct tg3 *tp = netdev_priv(dev);
10989
10990         if (!netif_running(dev)) {
10991                 tp->vlgrp = grp;
10992                 return;
10993         }
10994
10995         tg3_netif_stop(tp);
10996
10997         tg3_full_lock(tp, 0);
10998
10999         tp->vlgrp = grp;
11000
11001         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11002         __tg3_set_rx_mode(dev);
11003
11004         tg3_netif_start(tp);
11005
11006         tg3_full_unlock(tp);
11007 }
11008 #endif
11009
11010 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11011 {
11012         struct tg3 *tp = netdev_priv(dev);
11013
11014         memcpy(ec, &tp->coal, sizeof(*ec));
11015         return 0;
11016 }
11017
11018 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11019 {
11020         struct tg3 *tp = netdev_priv(dev);
11021         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11022         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11023
11024         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11025                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11026                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11027                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11028                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11029         }
11030
11031         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11032             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11033             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11034             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11035             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11036             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11037             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11038             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11039             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11040             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11041                 return -EINVAL;
11042
11043         /* No rx interrupts will be generated if both are zero */
11044         if ((ec->rx_coalesce_usecs == 0) &&
11045             (ec->rx_max_coalesced_frames == 0))
11046                 return -EINVAL;
11047
11048         /* No tx interrupts will be generated if both are zero */
11049         if ((ec->tx_coalesce_usecs == 0) &&
11050             (ec->tx_max_coalesced_frames == 0))
11051                 return -EINVAL;
11052
11053         /* Only copy relevant parameters, ignore all others. */
11054         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11055         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11056         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11057         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11058         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11059         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11060         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11061         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11062         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11063
11064         if (netif_running(dev)) {
11065                 tg3_full_lock(tp, 0);
11066                 __tg3_set_coalesce(tp, &tp->coal);
11067                 tg3_full_unlock(tp);
11068         }
11069         return 0;
11070 }
11071
11072 static const struct ethtool_ops tg3_ethtool_ops = {
11073         .get_settings           = tg3_get_settings,
11074         .set_settings           = tg3_set_settings,
11075         .get_drvinfo            = tg3_get_drvinfo,
11076         .get_regs_len           = tg3_get_regs_len,
11077         .get_regs               = tg3_get_regs,
11078         .get_wol                = tg3_get_wol,
11079         .set_wol                = tg3_set_wol,
11080         .get_msglevel           = tg3_get_msglevel,
11081         .set_msglevel           = tg3_set_msglevel,
11082         .nway_reset             = tg3_nway_reset,
11083         .get_link               = ethtool_op_get_link,
11084         .get_eeprom_len         = tg3_get_eeprom_len,
11085         .get_eeprom             = tg3_get_eeprom,
11086         .set_eeprom             = tg3_set_eeprom,
11087         .get_ringparam          = tg3_get_ringparam,
11088         .set_ringparam          = tg3_set_ringparam,
11089         .get_pauseparam         = tg3_get_pauseparam,
11090         .set_pauseparam         = tg3_set_pauseparam,
11091         .get_rx_csum            = tg3_get_rx_csum,
11092         .set_rx_csum            = tg3_set_rx_csum,
11093         .set_tx_csum            = tg3_set_tx_csum,
11094         .set_sg                 = ethtool_op_set_sg,
11095         .set_tso                = tg3_set_tso,
11096         .self_test              = tg3_self_test,
11097         .get_strings            = tg3_get_strings,
11098         .phys_id                = tg3_phys_id,
11099         .get_ethtool_stats      = tg3_get_ethtool_stats,
11100         .get_coalesce           = tg3_get_coalesce,
11101         .set_coalesce           = tg3_set_coalesce,
11102         .get_sset_count         = tg3_get_sset_count,
11103 };
11104
11105 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11106 {
11107         u32 cursize, val, magic;
11108
11109         tp->nvram_size = EEPROM_CHIP_SIZE;
11110
11111         if (tg3_nvram_read(tp, 0, &magic) != 0)
11112                 return;
11113
11114         if ((magic != TG3_EEPROM_MAGIC) &&
11115             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11116             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11117                 return;
11118
11119         /*
11120          * Size the chip by reading offsets at increasing powers of two.
11121          * When we encounter our validation signature, we know the addressing
11122          * has wrapped around, and thus have our chip size.
11123          */
11124         cursize = 0x10;
11125
11126         while (cursize < tp->nvram_size) {
11127                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11128                         return;
11129
11130                 if (val == magic)
11131                         break;
11132
11133                 cursize <<= 1;
11134         }
11135
11136         tp->nvram_size = cursize;
11137 }
11138
11139 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11140 {
11141         u32 val;
11142
11143         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11144             tg3_nvram_read(tp, 0, &val) != 0)
11145                 return;
11146
11147         /* Selfboot format */
11148         if (val != TG3_EEPROM_MAGIC) {
11149                 tg3_get_eeprom_size(tp);
11150                 return;
11151         }
11152
11153         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11154                 if (val != 0) {
11155                         /* This is confusing.  We want to operate on the
11156                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11157                          * call will read from NVRAM and byteswap the data
11158                          * according to the byteswapping settings for all
11159                          * other register accesses.  This ensures the data we
11160                          * want will always reside in the lower 16-bits.
11161                          * However, the data in NVRAM is in LE format, which
11162                          * means the data from the NVRAM read will always be
11163                          * opposite the endianness of the CPU.  The 16-bit
11164                          * byteswap then brings the data to CPU endianness.
11165                          */
11166                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11167                         return;
11168                 }
11169         }
11170         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11171 }
11172
11173 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11174 {
11175         u32 nvcfg1;
11176
11177         nvcfg1 = tr32(NVRAM_CFG1);
11178         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11179                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11180         } else {
11181                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11182                 tw32(NVRAM_CFG1, nvcfg1);
11183         }
11184
11185         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11186             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11187                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11188                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11189                         tp->nvram_jedecnum = JEDEC_ATMEL;
11190                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11191                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11192                         break;
11193                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11194                         tp->nvram_jedecnum = JEDEC_ATMEL;
11195                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11196                         break;
11197                 case FLASH_VENDOR_ATMEL_EEPROM:
11198                         tp->nvram_jedecnum = JEDEC_ATMEL;
11199                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11200                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11201                         break;
11202                 case FLASH_VENDOR_ST:
11203                         tp->nvram_jedecnum = JEDEC_ST;
11204                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11205                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11206                         break;
11207                 case FLASH_VENDOR_SAIFUN:
11208                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11209                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11210                         break;
11211                 case FLASH_VENDOR_SST_SMALL:
11212                 case FLASH_VENDOR_SST_LARGE:
11213                         tp->nvram_jedecnum = JEDEC_SST;
11214                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11215                         break;
11216                 }
11217         } else {
11218                 tp->nvram_jedecnum = JEDEC_ATMEL;
11219                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11220                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11221         }
11222 }
11223
11224 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11225 {
11226         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11227         case FLASH_5752PAGE_SIZE_256:
11228                 tp->nvram_pagesize = 256;
11229                 break;
11230         case FLASH_5752PAGE_SIZE_512:
11231                 tp->nvram_pagesize = 512;
11232                 break;
11233         case FLASH_5752PAGE_SIZE_1K:
11234                 tp->nvram_pagesize = 1024;
11235                 break;
11236         case FLASH_5752PAGE_SIZE_2K:
11237                 tp->nvram_pagesize = 2048;
11238                 break;
11239         case FLASH_5752PAGE_SIZE_4K:
11240                 tp->nvram_pagesize = 4096;
11241                 break;
11242         case FLASH_5752PAGE_SIZE_264:
11243                 tp->nvram_pagesize = 264;
11244                 break;
11245         case FLASH_5752PAGE_SIZE_528:
11246                 tp->nvram_pagesize = 528;
11247                 break;
11248         }
11249 }
11250
11251 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11252 {
11253         u32 nvcfg1;
11254
11255         nvcfg1 = tr32(NVRAM_CFG1);
11256
11257         /* NVRAM protection for TPM */
11258         if (nvcfg1 & (1 << 27))
11259                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11260
11261         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11262         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11263         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11264                 tp->nvram_jedecnum = JEDEC_ATMEL;
11265                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11266                 break;
11267         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11268                 tp->nvram_jedecnum = JEDEC_ATMEL;
11269                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11270                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11271                 break;
11272         case FLASH_5752VENDOR_ST_M45PE10:
11273         case FLASH_5752VENDOR_ST_M45PE20:
11274         case FLASH_5752VENDOR_ST_M45PE40:
11275                 tp->nvram_jedecnum = JEDEC_ST;
11276                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11277                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11278                 break;
11279         }
11280
11281         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11282                 tg3_nvram_get_pagesize(tp, nvcfg1);
11283         } else {
11284                 /* For eeprom, set pagesize to maximum eeprom size */
11285                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11286
11287                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11288                 tw32(NVRAM_CFG1, nvcfg1);
11289         }
11290 }
11291
11292 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11293 {
11294         u32 nvcfg1, protect = 0;
11295
11296         nvcfg1 = tr32(NVRAM_CFG1);
11297
11298         /* NVRAM protection for TPM */
11299         if (nvcfg1 & (1 << 27)) {
11300                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11301                 protect = 1;
11302         }
11303
11304         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11305         switch (nvcfg1) {
11306         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11307         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11308         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11309         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11310                 tp->nvram_jedecnum = JEDEC_ATMEL;
11311                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11312                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11313                 tp->nvram_pagesize = 264;
11314                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11315                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11316                         tp->nvram_size = (protect ? 0x3e200 :
11317                                           TG3_NVRAM_SIZE_512KB);
11318                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11319                         tp->nvram_size = (protect ? 0x1f200 :
11320                                           TG3_NVRAM_SIZE_256KB);
11321                 else
11322                         tp->nvram_size = (protect ? 0x1f200 :
11323                                           TG3_NVRAM_SIZE_128KB);
11324                 break;
11325         case FLASH_5752VENDOR_ST_M45PE10:
11326         case FLASH_5752VENDOR_ST_M45PE20:
11327         case FLASH_5752VENDOR_ST_M45PE40:
11328                 tp->nvram_jedecnum = JEDEC_ST;
11329                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11330                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11331                 tp->nvram_pagesize = 256;
11332                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11333                         tp->nvram_size = (protect ?
11334                                           TG3_NVRAM_SIZE_64KB :
11335                                           TG3_NVRAM_SIZE_128KB);
11336                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11337                         tp->nvram_size = (protect ?
11338                                           TG3_NVRAM_SIZE_64KB :
11339                                           TG3_NVRAM_SIZE_256KB);
11340                 else
11341                         tp->nvram_size = (protect ?
11342                                           TG3_NVRAM_SIZE_128KB :
11343                                           TG3_NVRAM_SIZE_512KB);
11344                 break;
11345         }
11346 }
11347
11348 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11349 {
11350         u32 nvcfg1;
11351
11352         nvcfg1 = tr32(NVRAM_CFG1);
11353
11354         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11355         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11356         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11357         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11358         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11359                 tp->nvram_jedecnum = JEDEC_ATMEL;
11360                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11361                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11362
11363                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11364                 tw32(NVRAM_CFG1, nvcfg1);
11365                 break;
11366         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11367         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11368         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11369         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11370                 tp->nvram_jedecnum = JEDEC_ATMEL;
11371                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11372                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11373                 tp->nvram_pagesize = 264;
11374                 break;
11375         case FLASH_5752VENDOR_ST_M45PE10:
11376         case FLASH_5752VENDOR_ST_M45PE20:
11377         case FLASH_5752VENDOR_ST_M45PE40:
11378                 tp->nvram_jedecnum = JEDEC_ST;
11379                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11380                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11381                 tp->nvram_pagesize = 256;
11382                 break;
11383         }
11384 }
11385
11386 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11387 {
11388         u32 nvcfg1, protect = 0;
11389
11390         nvcfg1 = tr32(NVRAM_CFG1);
11391
11392         /* NVRAM protection for TPM */
11393         if (nvcfg1 & (1 << 27)) {
11394                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11395                 protect = 1;
11396         }
11397
11398         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11399         switch (nvcfg1) {
11400         case FLASH_5761VENDOR_ATMEL_ADB021D:
11401         case FLASH_5761VENDOR_ATMEL_ADB041D:
11402         case FLASH_5761VENDOR_ATMEL_ADB081D:
11403         case FLASH_5761VENDOR_ATMEL_ADB161D:
11404         case FLASH_5761VENDOR_ATMEL_MDB021D:
11405         case FLASH_5761VENDOR_ATMEL_MDB041D:
11406         case FLASH_5761VENDOR_ATMEL_MDB081D:
11407         case FLASH_5761VENDOR_ATMEL_MDB161D:
11408                 tp->nvram_jedecnum = JEDEC_ATMEL;
11409                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11410                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11411                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11412                 tp->nvram_pagesize = 256;
11413                 break;
11414         case FLASH_5761VENDOR_ST_A_M45PE20:
11415         case FLASH_5761VENDOR_ST_A_M45PE40:
11416         case FLASH_5761VENDOR_ST_A_M45PE80:
11417         case FLASH_5761VENDOR_ST_A_M45PE16:
11418         case FLASH_5761VENDOR_ST_M_M45PE20:
11419         case FLASH_5761VENDOR_ST_M_M45PE40:
11420         case FLASH_5761VENDOR_ST_M_M45PE80:
11421         case FLASH_5761VENDOR_ST_M_M45PE16:
11422                 tp->nvram_jedecnum = JEDEC_ST;
11423                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11424                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11425                 tp->nvram_pagesize = 256;
11426                 break;
11427         }
11428
11429         if (protect) {
11430                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11431         } else {
11432                 switch (nvcfg1) {
11433                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11434                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11435                 case FLASH_5761VENDOR_ST_A_M45PE16:
11436                 case FLASH_5761VENDOR_ST_M_M45PE16:
11437                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11438                         break;
11439                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11440                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11441                 case FLASH_5761VENDOR_ST_A_M45PE80:
11442                 case FLASH_5761VENDOR_ST_M_M45PE80:
11443                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11444                         break;
11445                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11446                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11447                 case FLASH_5761VENDOR_ST_A_M45PE40:
11448                 case FLASH_5761VENDOR_ST_M_M45PE40:
11449                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11450                         break;
11451                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11452                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11453                 case FLASH_5761VENDOR_ST_A_M45PE20:
11454                 case FLASH_5761VENDOR_ST_M_M45PE20:
11455                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11456                         break;
11457                 }
11458         }
11459 }
11460
11461 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11462 {
11463         tp->nvram_jedecnum = JEDEC_ATMEL;
11464         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11465         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11466 }
11467
11468 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11469 {
11470         u32 nvcfg1;
11471
11472         nvcfg1 = tr32(NVRAM_CFG1);
11473
11474         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11475         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11476         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11477                 tp->nvram_jedecnum = JEDEC_ATMEL;
11478                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11479                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11480
11481                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11482                 tw32(NVRAM_CFG1, nvcfg1);
11483                 return;
11484         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11485         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11486         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11487         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11488         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11489         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11490         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11491                 tp->nvram_jedecnum = JEDEC_ATMEL;
11492                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11493                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11494
11495                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11496                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11497                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11498                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11499                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11500                         break;
11501                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11502                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11503                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11504                         break;
11505                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11506                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11507                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11508                         break;
11509                 }
11510                 break;
11511         case FLASH_5752VENDOR_ST_M45PE10:
11512         case FLASH_5752VENDOR_ST_M45PE20:
11513         case FLASH_5752VENDOR_ST_M45PE40:
11514                 tp->nvram_jedecnum = JEDEC_ST;
11515                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11516                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11517
11518                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11519                 case FLASH_5752VENDOR_ST_M45PE10:
11520                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11521                         break;
11522                 case FLASH_5752VENDOR_ST_M45PE20:
11523                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11524                         break;
11525                 case FLASH_5752VENDOR_ST_M45PE40:
11526                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11527                         break;
11528                 }
11529                 break;
11530         default:
11531                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11532                 return;
11533         }
11534
11535         tg3_nvram_get_pagesize(tp, nvcfg1);
11536         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11537                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11538 }
11539
11540
11541 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11542 {
11543         u32 nvcfg1;
11544
11545         nvcfg1 = tr32(NVRAM_CFG1);
11546
11547         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11548         case FLASH_5717VENDOR_ATMEL_EEPROM:
11549         case FLASH_5717VENDOR_MICRO_EEPROM:
11550                 tp->nvram_jedecnum = JEDEC_ATMEL;
11551                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11552                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11553
11554                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11555                 tw32(NVRAM_CFG1, nvcfg1);
11556                 return;
11557         case FLASH_5717VENDOR_ATMEL_MDB011D:
11558         case FLASH_5717VENDOR_ATMEL_ADB011B:
11559         case FLASH_5717VENDOR_ATMEL_ADB011D:
11560         case FLASH_5717VENDOR_ATMEL_MDB021D:
11561         case FLASH_5717VENDOR_ATMEL_ADB021B:
11562         case FLASH_5717VENDOR_ATMEL_ADB021D:
11563         case FLASH_5717VENDOR_ATMEL_45USPT:
11564                 tp->nvram_jedecnum = JEDEC_ATMEL;
11565                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11566                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11567
11568                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11569                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11570                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11571                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11572                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11573                         break;
11574                 default:
11575                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11576                         break;
11577                 }
11578                 break;
11579         case FLASH_5717VENDOR_ST_M_M25PE10:
11580         case FLASH_5717VENDOR_ST_A_M25PE10:
11581         case FLASH_5717VENDOR_ST_M_M45PE10:
11582         case FLASH_5717VENDOR_ST_A_M45PE10:
11583         case FLASH_5717VENDOR_ST_M_M25PE20:
11584         case FLASH_5717VENDOR_ST_A_M25PE20:
11585         case FLASH_5717VENDOR_ST_M_M45PE20:
11586         case FLASH_5717VENDOR_ST_A_M45PE20:
11587         case FLASH_5717VENDOR_ST_25USPT:
11588         case FLASH_5717VENDOR_ST_45USPT:
11589                 tp->nvram_jedecnum = JEDEC_ST;
11590                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11591                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11592
11593                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11594                 case FLASH_5717VENDOR_ST_M_M25PE20:
11595                 case FLASH_5717VENDOR_ST_A_M25PE20:
11596                 case FLASH_5717VENDOR_ST_M_M45PE20:
11597                 case FLASH_5717VENDOR_ST_A_M45PE20:
11598                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11599                         break;
11600                 default:
11601                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11602                         break;
11603                 }
11604                 break;
11605         default:
11606                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11607                 return;
11608         }
11609
11610         tg3_nvram_get_pagesize(tp, nvcfg1);
11611         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11612                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11613 }
11614
11615 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11616 static void __devinit tg3_nvram_init(struct tg3 *tp)
11617 {
11618         tw32_f(GRC_EEPROM_ADDR,
11619              (EEPROM_ADDR_FSM_RESET |
11620               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11621                EEPROM_ADDR_CLKPERD_SHIFT)));
11622
11623         msleep(1);
11624
11625         /* Enable seeprom accesses. */
11626         tw32_f(GRC_LOCAL_CTRL,
11627              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11628         udelay(100);
11629
11630         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11631             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11632                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11633
11634                 if (tg3_nvram_lock(tp)) {
11635                         netdev_warn(tp->dev,
11636                                     "Cannot get nvram lock, %s failed\n",
11637                                     __func__);
11638                         return;
11639                 }
11640                 tg3_enable_nvram_access(tp);
11641
11642                 tp->nvram_size = 0;
11643
11644                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11645                         tg3_get_5752_nvram_info(tp);
11646                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11647                         tg3_get_5755_nvram_info(tp);
11648                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11649                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11650                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11651                         tg3_get_5787_nvram_info(tp);
11652                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11653                         tg3_get_5761_nvram_info(tp);
11654                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11655                         tg3_get_5906_nvram_info(tp);
11656                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11657                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11658                         tg3_get_57780_nvram_info(tp);
11659                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11660                         tg3_get_5717_nvram_info(tp);
11661                 else
11662                         tg3_get_nvram_info(tp);
11663
11664                 if (tp->nvram_size == 0)
11665                         tg3_get_nvram_size(tp);
11666
11667                 tg3_disable_nvram_access(tp);
11668                 tg3_nvram_unlock(tp);
11669
11670         } else {
11671                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11672
11673                 tg3_get_eeprom_size(tp);
11674         }
11675 }
11676
11677 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11678                                     u32 offset, u32 len, u8 *buf)
11679 {
11680         int i, j, rc = 0;
11681         u32 val;
11682
11683         for (i = 0; i < len; i += 4) {
11684                 u32 addr;
11685                 __be32 data;
11686
11687                 addr = offset + i;
11688
11689                 memcpy(&data, buf + i, 4);
11690
11691                 /*
11692                  * The SEEPROM interface expects the data to always be opposite
11693                  * the native endian format.  We accomplish this by reversing
11694                  * all the operations that would have been performed on the
11695                  * data from a call to tg3_nvram_read_be32().
11696                  */
11697                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11698
11699                 val = tr32(GRC_EEPROM_ADDR);
11700                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11701
11702                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11703                         EEPROM_ADDR_READ);
11704                 tw32(GRC_EEPROM_ADDR, val |
11705                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11706                         (addr & EEPROM_ADDR_ADDR_MASK) |
11707                         EEPROM_ADDR_START |
11708                         EEPROM_ADDR_WRITE);
11709
11710                 for (j = 0; j < 1000; j++) {
11711                         val = tr32(GRC_EEPROM_ADDR);
11712
11713                         if (val & EEPROM_ADDR_COMPLETE)
11714                                 break;
11715                         msleep(1);
11716                 }
11717                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11718                         rc = -EBUSY;
11719                         break;
11720                 }
11721         }
11722
11723         return rc;
11724 }
11725
11726 /* offset and length are dword aligned */
11727 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11728                 u8 *buf)
11729 {
11730         int ret = 0;
11731         u32 pagesize = tp->nvram_pagesize;
11732         u32 pagemask = pagesize - 1;
11733         u32 nvram_cmd;
11734         u8 *tmp;
11735
11736         tmp = kmalloc(pagesize, GFP_KERNEL);
11737         if (tmp == NULL)
11738                 return -ENOMEM;
11739
11740         while (len) {
11741                 int j;
11742                 u32 phy_addr, page_off, size;
11743
11744                 phy_addr = offset & ~pagemask;
11745
11746                 for (j = 0; j < pagesize; j += 4) {
11747                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11748                                                   (__be32 *) (tmp + j));
11749                         if (ret)
11750                                 break;
11751                 }
11752                 if (ret)
11753                         break;
11754
11755                 page_off = offset & pagemask;
11756                 size = pagesize;
11757                 if (len < size)
11758                         size = len;
11759
11760                 len -= size;
11761
11762                 memcpy(tmp + page_off, buf, size);
11763
11764                 offset = offset + (pagesize - page_off);
11765
11766                 tg3_enable_nvram_access(tp);
11767
11768                 /*
11769                  * Before we can erase the flash page, we need
11770                  * to issue a special "write enable" command.
11771                  */
11772                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11773
11774                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11775                         break;
11776
11777                 /* Erase the target page */
11778                 tw32(NVRAM_ADDR, phy_addr);
11779
11780                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11781                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11782
11783                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11784                         break;
11785
11786                 /* Issue another write enable to start the write. */
11787                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11788
11789                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11790                         break;
11791
11792                 for (j = 0; j < pagesize; j += 4) {
11793                         __be32 data;
11794
11795                         data = *((__be32 *) (tmp + j));
11796
11797                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11798
11799                         tw32(NVRAM_ADDR, phy_addr + j);
11800
11801                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11802                                 NVRAM_CMD_WR;
11803
11804                         if (j == 0)
11805                                 nvram_cmd |= NVRAM_CMD_FIRST;
11806                         else if (j == (pagesize - 4))
11807                                 nvram_cmd |= NVRAM_CMD_LAST;
11808
11809                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11810                                 break;
11811                 }
11812                 if (ret)
11813                         break;
11814         }
11815
11816         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11817         tg3_nvram_exec_cmd(tp, nvram_cmd);
11818
11819         kfree(tmp);
11820
11821         return ret;
11822 }
11823
11824 /* offset and length are dword aligned */
11825 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11826                 u8 *buf)
11827 {
11828         int i, ret = 0;
11829
11830         for (i = 0; i < len; i += 4, offset += 4) {
11831                 u32 page_off, phy_addr, nvram_cmd;
11832                 __be32 data;
11833
11834                 memcpy(&data, buf + i, 4);
11835                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11836
11837                 page_off = offset % tp->nvram_pagesize;
11838
11839                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11840
11841                 tw32(NVRAM_ADDR, phy_addr);
11842
11843                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11844
11845                 if (page_off == 0 || i == 0)
11846                         nvram_cmd |= NVRAM_CMD_FIRST;
11847                 if (page_off == (tp->nvram_pagesize - 4))
11848                         nvram_cmd |= NVRAM_CMD_LAST;
11849
11850                 if (i == (len - 4))
11851                         nvram_cmd |= NVRAM_CMD_LAST;
11852
11853                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11854                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11855                     (tp->nvram_jedecnum == JEDEC_ST) &&
11856                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11857
11858                         if ((ret = tg3_nvram_exec_cmd(tp,
11859                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11860                                 NVRAM_CMD_DONE)))
11861
11862                                 break;
11863                 }
11864                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11865                         /* We always do complete word writes to eeprom. */
11866                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11867                 }
11868
11869                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11870                         break;
11871         }
11872         return ret;
11873 }
11874
11875 /* offset and length are dword aligned */
11876 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11877 {
11878         int ret;
11879
11880         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11881                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11882                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11883                 udelay(40);
11884         }
11885
11886         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11887                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11888         } else {
11889                 u32 grc_mode;
11890
11891                 ret = tg3_nvram_lock(tp);
11892                 if (ret)
11893                         return ret;
11894
11895                 tg3_enable_nvram_access(tp);
11896                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11897                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11898                         tw32(NVRAM_WRITE1, 0x406);
11899
11900                 grc_mode = tr32(GRC_MODE);
11901                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11902
11903                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11904                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11905
11906                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11907                                 buf);
11908                 } else {
11909                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11910                                 buf);
11911                 }
11912
11913                 grc_mode = tr32(GRC_MODE);
11914                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11915
11916                 tg3_disable_nvram_access(tp);
11917                 tg3_nvram_unlock(tp);
11918         }
11919
11920         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11921                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11922                 udelay(40);
11923         }
11924
11925         return ret;
11926 }
11927
11928 struct subsys_tbl_ent {
11929         u16 subsys_vendor, subsys_devid;
11930         u32 phy_id;
11931 };
11932
11933 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11934         /* Broadcom boards. */
11935         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11936           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11937         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11938           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11939         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11940           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11941         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11942           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11943         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11944           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11945         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11946           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11947         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11948           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11949         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11950           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11951         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11952           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11953         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11954           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11955         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11956           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11957
11958         /* 3com boards. */
11959         { TG3PCI_SUBVENDOR_ID_3COM,
11960           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11961         { TG3PCI_SUBVENDOR_ID_3COM,
11962           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11963         { TG3PCI_SUBVENDOR_ID_3COM,
11964           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11965         { TG3PCI_SUBVENDOR_ID_3COM,
11966           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11967         { TG3PCI_SUBVENDOR_ID_3COM,
11968           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
11969
11970         /* DELL boards. */
11971         { TG3PCI_SUBVENDOR_ID_DELL,
11972           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
11973         { TG3PCI_SUBVENDOR_ID_DELL,
11974           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
11975         { TG3PCI_SUBVENDOR_ID_DELL,
11976           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
11977         { TG3PCI_SUBVENDOR_ID_DELL,
11978           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
11979
11980         /* Compaq boards. */
11981         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11982           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
11983         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11984           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11986           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
11987         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11988           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
11989         { TG3PCI_SUBVENDOR_ID_COMPAQ,
11990           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
11991
11992         /* IBM boards. */
11993         { TG3PCI_SUBVENDOR_ID_IBM,
11994           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
11995 };
11996
11997 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
11998 {
11999         int i;
12000
12001         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12002                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12003                      tp->pdev->subsystem_vendor) &&
12004                     (subsys_id_to_phy_id[i].subsys_devid ==
12005                      tp->pdev->subsystem_device))
12006                         return &subsys_id_to_phy_id[i];
12007         }
12008         return NULL;
12009 }
12010
12011 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12012 {
12013         u32 val;
12014         u16 pmcsr;
12015
12016         /* On some early chips the SRAM cannot be accessed in D3hot state,
12017          * so need make sure we're in D0.
12018          */
12019         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12020         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12021         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12022         msleep(1);
12023
12024         /* Make sure register accesses (indirect or otherwise)
12025          * will function correctly.
12026          */
12027         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12028                                tp->misc_host_ctrl);
12029
12030         /* The memory arbiter has to be enabled in order for SRAM accesses
12031          * to succeed.  Normally on powerup the tg3 chip firmware will make
12032          * sure it is enabled, but other entities such as system netboot
12033          * code might disable it.
12034          */
12035         val = tr32(MEMARB_MODE);
12036         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12037
12038         tp->phy_id = TG3_PHY_ID_INVALID;
12039         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12040
12041         /* Assume an onboard device and WOL capable by default.  */
12042         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12043
12044         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12045                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12046                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12047                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12048                 }
12049                 val = tr32(VCPU_CFGSHDW);
12050                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12051                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12052                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12053                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12054                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12055                 goto done;
12056         }
12057
12058         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12059         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12060                 u32 nic_cfg, led_cfg;
12061                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12062                 int eeprom_phy_serdes = 0;
12063
12064                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12065                 tp->nic_sram_data_cfg = nic_cfg;
12066
12067                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12068                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12069                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12070                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12071                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12072                     (ver > 0) && (ver < 0x100))
12073                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12074
12075                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12076                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12077
12078                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12079                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12080                         eeprom_phy_serdes = 1;
12081
12082                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12083                 if (nic_phy_id != 0) {
12084                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12085                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12086
12087                         eeprom_phy_id  = (id1 >> 16) << 10;
12088                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12089                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12090                 } else
12091                         eeprom_phy_id = 0;
12092
12093                 tp->phy_id = eeprom_phy_id;
12094                 if (eeprom_phy_serdes) {
12095                         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12096                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12097                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12098                         else
12099                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12100                 }
12101
12102                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12103                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12104                                     SHASTA_EXT_LED_MODE_MASK);
12105                 else
12106                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12107
12108                 switch (led_cfg) {
12109                 default:
12110                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12111                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12112                         break;
12113
12114                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12115                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12116                         break;
12117
12118                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12119                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12120
12121                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12122                          * read on some older 5700/5701 bootcode.
12123                          */
12124                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12125                             ASIC_REV_5700 ||
12126                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12127                             ASIC_REV_5701)
12128                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12129
12130                         break;
12131
12132                 case SHASTA_EXT_LED_SHARED:
12133                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12134                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12135                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12136                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12137                                                  LED_CTRL_MODE_PHY_2);
12138                         break;
12139
12140                 case SHASTA_EXT_LED_MAC:
12141                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12142                         break;
12143
12144                 case SHASTA_EXT_LED_COMBO:
12145                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12146                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12147                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12148                                                  LED_CTRL_MODE_PHY_2);
12149                         break;
12150
12151                 }
12152
12153                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12154                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12155                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12156                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12157
12158                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12159                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12160
12161                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12162                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12163                         if ((tp->pdev->subsystem_vendor ==
12164                              PCI_VENDOR_ID_ARIMA) &&
12165                             (tp->pdev->subsystem_device == 0x205a ||
12166                              tp->pdev->subsystem_device == 0x2063))
12167                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12168                 } else {
12169                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12170                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12171                 }
12172
12173                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12174                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12175                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12176                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12177                 }
12178
12179                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12180                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12181                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12182
12183                 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12184                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12185                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12186
12187                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12188                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12189                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12190
12191                 if (cfg2 & (1 << 17))
12192                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12193
12194                 /* serdes signal pre-emphasis in register 0x590 set by */
12195                 /* bootcode if bit 18 is set */
12196                 if (cfg2 & (1 << 18))
12197                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12198
12199                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12200                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12201                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12202                         tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12203
12204                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12205                         u32 cfg3;
12206
12207                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12208                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12209                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12210                 }
12211
12212                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12213                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12214                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12215                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12216                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12217                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12218         }
12219 done:
12220         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12221         device_set_wakeup_enable(&tp->pdev->dev,
12222                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12223 }
12224
12225 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12226 {
12227         int i;
12228         u32 val;
12229
12230         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12231         tw32(OTP_CTRL, cmd);
12232
12233         /* Wait for up to 1 ms for command to execute. */
12234         for (i = 0; i < 100; i++) {
12235                 val = tr32(OTP_STATUS);
12236                 if (val & OTP_STATUS_CMD_DONE)
12237                         break;
12238                 udelay(10);
12239         }
12240
12241         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12242 }
12243
12244 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12245  * configuration is a 32-bit value that straddles the alignment boundary.
12246  * We do two 32-bit reads and then shift and merge the results.
12247  */
12248 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12249 {
12250         u32 bhalf_otp, thalf_otp;
12251
12252         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12253
12254         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12255                 return 0;
12256
12257         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12258
12259         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12260                 return 0;
12261
12262         thalf_otp = tr32(OTP_READ_DATA);
12263
12264         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12265
12266         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12267                 return 0;
12268
12269         bhalf_otp = tr32(OTP_READ_DATA);
12270
12271         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12272 }
12273
12274 static int __devinit tg3_phy_probe(struct tg3 *tp)
12275 {
12276         u32 hw_phy_id_1, hw_phy_id_2;
12277         u32 hw_phy_id, hw_phy_id_masked;
12278         int err;
12279
12280         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12281                 return tg3_phy_init(tp);
12282
12283         /* Reading the PHY ID register can conflict with ASF
12284          * firmware access to the PHY hardware.
12285          */
12286         err = 0;
12287         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12288             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12289                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12290         } else {
12291                 /* Now read the physical PHY_ID from the chip and verify
12292                  * that it is sane.  If it doesn't look good, we fall back
12293                  * to either the hard-coded table based PHY_ID and failing
12294                  * that the value found in the eeprom area.
12295                  */
12296                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12297                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12298
12299                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12300                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12301                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12302
12303                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12304         }
12305
12306         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12307                 tp->phy_id = hw_phy_id;
12308                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12309                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12310                 else
12311                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12312         } else {
12313                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12314                         /* Do nothing, phy ID already set up in
12315                          * tg3_get_eeprom_hw_cfg().
12316                          */
12317                 } else {
12318                         struct subsys_tbl_ent *p;
12319
12320                         /* No eeprom signature?  Try the hardcoded
12321                          * subsys device table.
12322                          */
12323                         p = tg3_lookup_by_subsys(tp);
12324                         if (!p)
12325                                 return -ENODEV;
12326
12327                         tp->phy_id = p->phy_id;
12328                         if (!tp->phy_id ||
12329                             tp->phy_id == TG3_PHY_ID_BCM8002)
12330                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12331                 }
12332         }
12333
12334         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12335             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12336             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12337                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12338
12339                 tg3_readphy(tp, MII_BMSR, &bmsr);
12340                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12341                     (bmsr & BMSR_LSTATUS))
12342                         goto skip_phy_reset;
12343
12344                 err = tg3_phy_reset(tp);
12345                 if (err)
12346                         return err;
12347
12348                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12349                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12350                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12351                 tg3_ctrl = 0;
12352                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12353                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12354                                     MII_TG3_CTRL_ADV_1000_FULL);
12355                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12356                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12357                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12358                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12359                 }
12360
12361                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12362                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12363                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12364                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12365                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12366
12367                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12368                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12369
12370                         tg3_writephy(tp, MII_BMCR,
12371                                      BMCR_ANENABLE | BMCR_ANRESTART);
12372                 }
12373                 tg3_phy_set_wirespeed(tp);
12374
12375                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12376                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12377                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12378         }
12379
12380 skip_phy_reset:
12381         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12382                 err = tg3_init_5401phy_dsp(tp);
12383                 if (err)
12384                         return err;
12385
12386                 err = tg3_init_5401phy_dsp(tp);
12387         }
12388
12389         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12390                 tp->link_config.advertising =
12391                         (ADVERTISED_1000baseT_Half |
12392                          ADVERTISED_1000baseT_Full |
12393                          ADVERTISED_Autoneg |
12394                          ADVERTISED_FIBRE);
12395         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12396                 tp->link_config.advertising &=
12397                         ~(ADVERTISED_1000baseT_Half |
12398                           ADVERTISED_1000baseT_Full);
12399
12400         return err;
12401 }
12402
12403 static void __devinit tg3_read_vpd(struct tg3 *tp)
12404 {
12405         u8 vpd_data[TG3_NVM_VPD_LEN];
12406         unsigned int block_end, rosize, len;
12407         int j, i = 0;
12408         u32 magic;
12409
12410         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12411             tg3_nvram_read(tp, 0x0, &magic))
12412                 goto out_not_found;
12413
12414         if (magic == TG3_EEPROM_MAGIC) {
12415                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12416                         u32 tmp;
12417
12418                         /* The data is in little-endian format in NVRAM.
12419                          * Use the big-endian read routines to preserve
12420                          * the byte order as it exists in NVRAM.
12421                          */
12422                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12423                                 goto out_not_found;
12424
12425                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12426                 }
12427         } else {
12428                 ssize_t cnt;
12429                 unsigned int pos = 0;
12430
12431                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12432                         cnt = pci_read_vpd(tp->pdev, pos,
12433                                            TG3_NVM_VPD_LEN - pos,
12434                                            &vpd_data[pos]);
12435                         if (cnt == -ETIMEDOUT || -EINTR)
12436                                 cnt = 0;
12437                         else if (cnt < 0)
12438                                 goto out_not_found;
12439                 }
12440                 if (pos != TG3_NVM_VPD_LEN)
12441                         goto out_not_found;
12442         }
12443
12444         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12445                              PCI_VPD_LRDT_RO_DATA);
12446         if (i < 0)
12447                 goto out_not_found;
12448
12449         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12450         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12451         i += PCI_VPD_LRDT_TAG_SIZE;
12452
12453         if (block_end > TG3_NVM_VPD_LEN)
12454                 goto out_not_found;
12455
12456         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12457                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12458         if (j > 0) {
12459                 len = pci_vpd_info_field_size(&vpd_data[j]);
12460
12461                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12462                 if (j + len > block_end || len != 4 ||
12463                     memcmp(&vpd_data[j], "1028", 4))
12464                         goto partno;
12465
12466                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12467                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12468                 if (j < 0)
12469                         goto partno;
12470
12471                 len = pci_vpd_info_field_size(&vpd_data[j]);
12472
12473                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12474                 if (j + len > block_end)
12475                         goto partno;
12476
12477                 memcpy(tp->fw_ver, &vpd_data[j], len);
12478                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12479         }
12480
12481 partno:
12482         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12483                                       PCI_VPD_RO_KEYWORD_PARTNO);
12484         if (i < 0)
12485                 goto out_not_found;
12486
12487         len = pci_vpd_info_field_size(&vpd_data[i]);
12488
12489         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12490         if (len > TG3_BPN_SIZE ||
12491             (len + i) > TG3_NVM_VPD_LEN)
12492                 goto out_not_found;
12493
12494         memcpy(tp->board_part_number, &vpd_data[i], len);
12495
12496         return;
12497
12498 out_not_found:
12499         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12500                 strcpy(tp->board_part_number, "BCM95906");
12501         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12502                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12503                 strcpy(tp->board_part_number, "BCM57780");
12504         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12505                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12506                 strcpy(tp->board_part_number, "BCM57760");
12507         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12508                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12509                 strcpy(tp->board_part_number, "BCM57790");
12510         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12511                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12512                 strcpy(tp->board_part_number, "BCM57788");
12513         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12514                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12515                 strcpy(tp->board_part_number, "BCM57761");
12516         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12517                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12518                 strcpy(tp->board_part_number, "BCM57765");
12519         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12520                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12521                 strcpy(tp->board_part_number, "BCM57781");
12522         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12523                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12524                 strcpy(tp->board_part_number, "BCM57785");
12525         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12526                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12527                 strcpy(tp->board_part_number, "BCM57791");
12528         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12529                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12530                 strcpy(tp->board_part_number, "BCM57795");
12531         else
12532                 strcpy(tp->board_part_number, "none");
12533 }
12534
12535 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12536 {
12537         u32 val;
12538
12539         if (tg3_nvram_read(tp, offset, &val) ||
12540             (val & 0xfc000000) != 0x0c000000 ||
12541             tg3_nvram_read(tp, offset + 4, &val) ||
12542             val != 0)
12543                 return 0;
12544
12545         return 1;
12546 }
12547
12548 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12549 {
12550         u32 val, offset, start, ver_offset;
12551         int i, dst_off;
12552         bool newver = false;
12553
12554         if (tg3_nvram_read(tp, 0xc, &offset) ||
12555             tg3_nvram_read(tp, 0x4, &start))
12556                 return;
12557
12558         offset = tg3_nvram_logical_addr(tp, offset);
12559
12560         if (tg3_nvram_read(tp, offset, &val))
12561                 return;
12562
12563         if ((val & 0xfc000000) == 0x0c000000) {
12564                 if (tg3_nvram_read(tp, offset + 4, &val))
12565                         return;
12566
12567                 if (val == 0)
12568                         newver = true;
12569         }
12570
12571         dst_off = strlen(tp->fw_ver);
12572
12573         if (newver) {
12574                 if (TG3_VER_SIZE - dst_off < 16 ||
12575                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12576                         return;
12577
12578                 offset = offset + ver_offset - start;
12579                 for (i = 0; i < 16; i += 4) {
12580                         __be32 v;
12581                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12582                                 return;
12583
12584                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12585                 }
12586         } else {
12587                 u32 major, minor;
12588
12589                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12590                         return;
12591
12592                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12593                         TG3_NVM_BCVER_MAJSFT;
12594                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12595                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12596                          "v%d.%02d", major, minor);
12597         }
12598 }
12599
12600 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12601 {
12602         u32 val, major, minor;
12603
12604         /* Use native endian representation */
12605         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12606                 return;
12607
12608         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12609                 TG3_NVM_HWSB_CFG1_MAJSFT;
12610         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12611                 TG3_NVM_HWSB_CFG1_MINSFT;
12612
12613         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12614 }
12615
12616 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12617 {
12618         u32 offset, major, minor, build;
12619
12620         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12621
12622         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12623                 return;
12624
12625         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12626         case TG3_EEPROM_SB_REVISION_0:
12627                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12628                 break;
12629         case TG3_EEPROM_SB_REVISION_2:
12630                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12631                 break;
12632         case TG3_EEPROM_SB_REVISION_3:
12633                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12634                 break;
12635         case TG3_EEPROM_SB_REVISION_4:
12636                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12637                 break;
12638         case TG3_EEPROM_SB_REVISION_5:
12639                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12640                 break;
12641         default:
12642                 return;
12643         }
12644
12645         if (tg3_nvram_read(tp, offset, &val))
12646                 return;
12647
12648         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12649                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12650         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12651                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12652         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12653
12654         if (minor > 99 || build > 26)
12655                 return;
12656
12657         offset = strlen(tp->fw_ver);
12658         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12659                  " v%d.%02d", major, minor);
12660
12661         if (build > 0) {
12662                 offset = strlen(tp->fw_ver);
12663                 if (offset < TG3_VER_SIZE - 1)
12664                         tp->fw_ver[offset] = 'a' + build - 1;
12665         }
12666 }
12667
12668 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12669 {
12670         u32 val, offset, start;
12671         int i, vlen;
12672
12673         for (offset = TG3_NVM_DIR_START;
12674              offset < TG3_NVM_DIR_END;
12675              offset += TG3_NVM_DIRENT_SIZE) {
12676                 if (tg3_nvram_read(tp, offset, &val))
12677                         return;
12678
12679                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12680                         break;
12681         }
12682
12683         if (offset == TG3_NVM_DIR_END)
12684                 return;
12685
12686         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12687                 start = 0x08000000;
12688         else if (tg3_nvram_read(tp, offset - 4, &start))
12689                 return;
12690
12691         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12692             !tg3_fw_img_is_valid(tp, offset) ||
12693             tg3_nvram_read(tp, offset + 8, &val))
12694                 return;
12695
12696         offset += val - start;
12697
12698         vlen = strlen(tp->fw_ver);
12699
12700         tp->fw_ver[vlen++] = ',';
12701         tp->fw_ver[vlen++] = ' ';
12702
12703         for (i = 0; i < 4; i++) {
12704                 __be32 v;
12705                 if (tg3_nvram_read_be32(tp, offset, &v))
12706                         return;
12707
12708                 offset += sizeof(v);
12709
12710                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12711                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12712                         break;
12713                 }
12714
12715                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12716                 vlen += sizeof(v);
12717         }
12718 }
12719
12720 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12721 {
12722         int vlen;
12723         u32 apedata;
12724
12725         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12726             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12727                 return;
12728
12729         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12730         if (apedata != APE_SEG_SIG_MAGIC)
12731                 return;
12732
12733         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12734         if (!(apedata & APE_FW_STATUS_READY))
12735                 return;
12736
12737         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12738
12739         vlen = strlen(tp->fw_ver);
12740
12741         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12742                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12743                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12744                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12745                  (apedata & APE_FW_VERSION_BLDMSK));
12746 }
12747
12748 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12749 {
12750         u32 val;
12751         bool vpd_vers = false;
12752
12753         if (tp->fw_ver[0] != 0)
12754                 vpd_vers = true;
12755
12756         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12757                 strcat(tp->fw_ver, "sb");
12758                 return;
12759         }
12760
12761         if (tg3_nvram_read(tp, 0, &val))
12762                 return;
12763
12764         if (val == TG3_EEPROM_MAGIC)
12765                 tg3_read_bc_ver(tp);
12766         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12767                 tg3_read_sb_ver(tp, val);
12768         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12769                 tg3_read_hwsb_ver(tp);
12770         else
12771                 return;
12772
12773         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12774              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12775                 goto done;
12776
12777         tg3_read_mgmtfw_ver(tp);
12778
12779 done:
12780         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12781 }
12782
12783 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12784
12785 static int __devinit tg3_get_invariants(struct tg3 *tp)
12786 {
12787         static struct pci_device_id write_reorder_chipsets[] = {
12788                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12789                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12790                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12791                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12792                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12793                              PCI_DEVICE_ID_VIA_8385_0) },
12794                 { },
12795         };
12796         u32 misc_ctrl_reg;
12797         u32 pci_state_reg, grc_misc_cfg;
12798         u32 val;
12799         u16 pci_cmd;
12800         int err;
12801
12802         /* Force memory write invalidate off.  If we leave it on,
12803          * then on 5700_BX chips we have to enable a workaround.
12804          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12805          * to match the cacheline size.  The Broadcom driver have this
12806          * workaround but turns MWI off all the times so never uses
12807          * it.  This seems to suggest that the workaround is insufficient.
12808          */
12809         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12810         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12811         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12812
12813         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12814          * has the register indirect write enable bit set before
12815          * we try to access any of the MMIO registers.  It is also
12816          * critical that the PCI-X hw workaround situation is decided
12817          * before that as well.
12818          */
12819         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12820                               &misc_ctrl_reg);
12821
12822         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12823                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12825                 u32 prod_id_asic_rev;
12826
12827                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12828                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12829                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12830                         pci_read_config_dword(tp->pdev,
12831                                               TG3PCI_GEN2_PRODID_ASICREV,
12832                                               &prod_id_asic_rev);
12833                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12834                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12835                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12836                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12837                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12838                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12839                         pci_read_config_dword(tp->pdev,
12840                                               TG3PCI_GEN15_PRODID_ASICREV,
12841                                               &prod_id_asic_rev);
12842                 else
12843                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12844                                               &prod_id_asic_rev);
12845
12846                 tp->pci_chip_rev_id = prod_id_asic_rev;
12847         }
12848
12849         /* Wrong chip ID in 5752 A0. This code can be removed later
12850          * as A0 is not in production.
12851          */
12852         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12853                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12854
12855         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12856          * we need to disable memory and use config. cycles
12857          * only to access all registers. The 5702/03 chips
12858          * can mistakenly decode the special cycles from the
12859          * ICH chipsets as memory write cycles, causing corruption
12860          * of register and memory space. Only certain ICH bridges
12861          * will drive special cycles with non-zero data during the
12862          * address phase which can fall within the 5703's address
12863          * range. This is not an ICH bug as the PCI spec allows
12864          * non-zero address during special cycles. However, only
12865          * these ICH bridges are known to drive non-zero addresses
12866          * during special cycles.
12867          *
12868          * Since special cycles do not cross PCI bridges, we only
12869          * enable this workaround if the 5703 is on the secondary
12870          * bus of these ICH bridges.
12871          */
12872         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12873             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12874                 static struct tg3_dev_id {
12875                         u32     vendor;
12876                         u32     device;
12877                         u32     rev;
12878                 } ich_chipsets[] = {
12879                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12880                           PCI_ANY_ID },
12881                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12882                           PCI_ANY_ID },
12883                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12884                           0xa },
12885                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12886                           PCI_ANY_ID },
12887                         { },
12888                 };
12889                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12890                 struct pci_dev *bridge = NULL;
12891
12892                 while (pci_id->vendor != 0) {
12893                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12894                                                 bridge);
12895                         if (!bridge) {
12896                                 pci_id++;
12897                                 continue;
12898                         }
12899                         if (pci_id->rev != PCI_ANY_ID) {
12900                                 if (bridge->revision > pci_id->rev)
12901                                         continue;
12902                         }
12903                         if (bridge->subordinate &&
12904                             (bridge->subordinate->number ==
12905                              tp->pdev->bus->number)) {
12906
12907                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12908                                 pci_dev_put(bridge);
12909                                 break;
12910                         }
12911                 }
12912         }
12913
12914         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12915                 static struct tg3_dev_id {
12916                         u32     vendor;
12917                         u32     device;
12918                 } bridge_chipsets[] = {
12919                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12920                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12921                         { },
12922                 };
12923                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12924                 struct pci_dev *bridge = NULL;
12925
12926                 while (pci_id->vendor != 0) {
12927                         bridge = pci_get_device(pci_id->vendor,
12928                                                 pci_id->device,
12929                                                 bridge);
12930                         if (!bridge) {
12931                                 pci_id++;
12932                                 continue;
12933                         }
12934                         if (bridge->subordinate &&
12935                             (bridge->subordinate->number <=
12936                              tp->pdev->bus->number) &&
12937                             (bridge->subordinate->subordinate >=
12938                              tp->pdev->bus->number)) {
12939                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12940                                 pci_dev_put(bridge);
12941                                 break;
12942                         }
12943                 }
12944         }
12945
12946         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12947          * DMA addresses > 40-bit. This bridge may have other additional
12948          * 57xx devices behind it in some 4-port NIC designs for example.
12949          * Any tg3 device found behind the bridge will also need the 40-bit
12950          * DMA workaround.
12951          */
12952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12954                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12955                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12956                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12957         } else {
12958                 struct pci_dev *bridge = NULL;
12959
12960                 do {
12961                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12962                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
12963                                                 bridge);
12964                         if (bridge && bridge->subordinate &&
12965                             (bridge->subordinate->number <=
12966                              tp->pdev->bus->number) &&
12967                             (bridge->subordinate->subordinate >=
12968                              tp->pdev->bus->number)) {
12969                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12970                                 pci_dev_put(bridge);
12971                                 break;
12972                         }
12973                 } while (bridge);
12974         }
12975
12976         /* Initialize misc host control in PCI block. */
12977         tp->misc_host_ctrl |= (misc_ctrl_reg &
12978                                MISC_HOST_CTRL_CHIPREV);
12979         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12980                                tp->misc_host_ctrl);
12981
12982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
12983             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
12984             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12985                 tp->pdev_peer = tg3_find_peer(tp);
12986
12987         /* Intentionally exclude ASIC_REV_5906 */
12988         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12989             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
12990             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
12991             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
12992             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
12993             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
12994             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12995             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12996                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
12997
12998         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
12999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13000             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13001             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13002             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13003                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13004
13005         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13006             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13007                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13008
13009         /* 5700 B0 chips do not support checksumming correctly due
13010          * to hardware bugs.
13011          */
13012         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13013                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13014         else {
13015                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13016                 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13017                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13018                         tp->dev->features |= NETIF_F_IPV6_CSUM;
13019                 tp->dev->features |= NETIF_F_GRO;
13020         }
13021
13022         /* Determine TSO capabilities */
13023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13025                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13026         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13027                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13028                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13029         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13030                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13031                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13032                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13033                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13034         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13035                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13036                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13037                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13038                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13039                         tp->fw_needed = FIRMWARE_TG3TSO5;
13040                 else
13041                         tp->fw_needed = FIRMWARE_TG3TSO;
13042         }
13043
13044         tp->irq_max = 1;
13045
13046         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13047                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13048                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13049                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13050                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13051                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13052                      tp->pdev_peer == tp->pdev))
13053                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13054
13055                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13056                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13057                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13058                 }
13059
13060                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13061                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13062                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13063                         tp->irq_max = TG3_IRQ_MAX_VECS;
13064                 }
13065         }
13066
13067         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13068             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13069                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13070         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13071                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13072                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13073         }
13074
13075         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13076             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13077                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13078
13079         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13080             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13081             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13082                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13083
13084         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13085                               &pci_state_reg);
13086
13087         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13088         if (tp->pcie_cap != 0) {
13089                 u16 lnkctl;
13090
13091                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13092
13093                 pcie_set_readrq(tp->pdev, 4096);
13094
13095                 pci_read_config_word(tp->pdev,
13096                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13097                                      &lnkctl);
13098                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13099                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13100                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13101                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13102                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13103                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13104                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13105                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13106                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13107                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13108                 }
13109         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13110                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13111         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13112                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13113                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13114                 if (!tp->pcix_cap) {
13115                         dev_err(&tp->pdev->dev,
13116                                 "Cannot find PCI-X capability, aborting\n");
13117                         return -EIO;
13118                 }
13119
13120                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13121                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13122         }
13123
13124         /* If we have an AMD 762 or VIA K8T800 chipset, write
13125          * reordering to the mailbox registers done by the host
13126          * controller can cause major troubles.  We read back from
13127          * every mailbox register write to force the writes to be
13128          * posted to the chip in order.
13129          */
13130         if (pci_dev_present(write_reorder_chipsets) &&
13131             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13132                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13133
13134         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13135                              &tp->pci_cacheline_sz);
13136         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13137                              &tp->pci_lat_timer);
13138         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13139             tp->pci_lat_timer < 64) {
13140                 tp->pci_lat_timer = 64;
13141                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13142                                       tp->pci_lat_timer);
13143         }
13144
13145         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13146                 /* 5700 BX chips need to have their TX producer index
13147                  * mailboxes written twice to workaround a bug.
13148                  */
13149                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13150
13151                 /* If we are in PCI-X mode, enable register write workaround.
13152                  *
13153                  * The workaround is to use indirect register accesses
13154                  * for all chip writes not to mailbox registers.
13155                  */
13156                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13157                         u32 pm_reg;
13158
13159                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13160
13161                         /* The chip can have it's power management PCI config
13162                          * space registers clobbered due to this bug.
13163                          * So explicitly force the chip into D0 here.
13164                          */
13165                         pci_read_config_dword(tp->pdev,
13166                                               tp->pm_cap + PCI_PM_CTRL,
13167                                               &pm_reg);
13168                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13169                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13170                         pci_write_config_dword(tp->pdev,
13171                                                tp->pm_cap + PCI_PM_CTRL,
13172                                                pm_reg);
13173
13174                         /* Also, force SERR#/PERR# in PCI command. */
13175                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13176                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13177                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13178                 }
13179         }
13180
13181         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13182                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13183         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13184                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13185
13186         /* Chip-specific fixup from Broadcom driver */
13187         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13188             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13189                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13190                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13191         }
13192
13193         /* Default fast path register access methods */
13194         tp->read32 = tg3_read32;
13195         tp->write32 = tg3_write32;
13196         tp->read32_mbox = tg3_read32;
13197         tp->write32_mbox = tg3_write32;
13198         tp->write32_tx_mbox = tg3_write32;
13199         tp->write32_rx_mbox = tg3_write32;
13200
13201         /* Various workaround register access methods */
13202         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13203                 tp->write32 = tg3_write_indirect_reg32;
13204         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13205                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13206                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13207                 /*
13208                  * Back to back register writes can cause problems on these
13209                  * chips, the workaround is to read back all reg writes
13210                  * except those to mailbox regs.
13211                  *
13212                  * See tg3_write_indirect_reg32().
13213                  */
13214                 tp->write32 = tg3_write_flush_reg32;
13215         }
13216
13217         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13218             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13219                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13220                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13221                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13222         }
13223
13224         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13225                 tp->read32 = tg3_read_indirect_reg32;
13226                 tp->write32 = tg3_write_indirect_reg32;
13227                 tp->read32_mbox = tg3_read_indirect_mbox;
13228                 tp->write32_mbox = tg3_write_indirect_mbox;
13229                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13230                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13231
13232                 iounmap(tp->regs);
13233                 tp->regs = NULL;
13234
13235                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13236                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13237                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13238         }
13239         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13240                 tp->read32_mbox = tg3_read32_mbox_5906;
13241                 tp->write32_mbox = tg3_write32_mbox_5906;
13242                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13243                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13244         }
13245
13246         if (tp->write32 == tg3_write_indirect_reg32 ||
13247             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13248              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13249               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13250                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13251
13252         /* Get eeprom hw config before calling tg3_set_power_state().
13253          * In particular, the TG3_FLG2_IS_NIC flag must be
13254          * determined before calling tg3_set_power_state() so that
13255          * we know whether or not to switch out of Vaux power.
13256          * When the flag is set, it means that GPIO1 is used for eeprom
13257          * write protect and also implies that it is a LOM where GPIOs
13258          * are not used to switch power.
13259          */
13260         tg3_get_eeprom_hw_cfg(tp);
13261
13262         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13263                 /* Allow reads and writes to the
13264                  * APE register and memory space.
13265                  */
13266                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13267                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13268                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13269                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13270                                        pci_state_reg);
13271         }
13272
13273         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13274             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13275             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13276             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13277             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13278             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13279                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13280
13281         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13282          * GPIO1 driven high will bring 5700's external PHY out of reset.
13283          * It is also used as eeprom write protect on LOMs.
13284          */
13285         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13286         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13287             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13288                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13289                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13290         /* Unused GPIO3 must be driven as output on 5752 because there
13291          * are no pull-up resistors on unused GPIO pins.
13292          */
13293         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13294                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13295
13296         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13297             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13298             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13299                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13300
13301         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13302             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13303                 /* Turn off the debug UART. */
13304                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13305                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13306                         /* Keep VMain power. */
13307                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13308                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13309         }
13310
13311         /* Force the chip into D0. */
13312         err = tg3_set_power_state(tp, PCI_D0);
13313         if (err) {
13314                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13315                 return err;
13316         }
13317
13318         /* Derive initial jumbo mode from MTU assigned in
13319          * ether_setup() via the alloc_etherdev() call
13320          */
13321         if (tp->dev->mtu > ETH_DATA_LEN &&
13322             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13323                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13324
13325         /* Determine WakeOnLan speed to use. */
13326         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13327             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13328             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13329             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13330                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13331         } else {
13332                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13333         }
13334
13335         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13336                 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13337
13338         /* A few boards don't want Ethernet@WireSpeed phy feature */
13339         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13340             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13341              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13342              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13343             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13344             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13345                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13346
13347         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13348             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13349                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13350         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13351                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13352
13353         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13354             !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13355             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13356             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13357             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13358             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13359                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13360                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13362                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13363                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13364                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13365                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13366                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13367                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13368                 } else
13369                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13370         }
13371
13372         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13373             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13374                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13375                 if (tp->phy_otp == 0)
13376                         tp->phy_otp = TG3_OTP_DEFAULT;
13377         }
13378
13379         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13380                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13381         else
13382                 tp->mi_mode = MAC_MI_MODE_BASE;
13383
13384         tp->coalesce_mode = 0;
13385         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13386             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13387                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13388
13389         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13390             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13391                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13392
13393         err = tg3_mdio_init(tp);
13394         if (err)
13395                 return err;
13396
13397         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13398             (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13399                  (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13400                 return -ENOTSUPP;
13401
13402         /* Initialize data/descriptor byte/word swapping. */
13403         val = tr32(GRC_MODE);
13404         val &= GRC_MODE_HOST_STACKUP;
13405         tw32(GRC_MODE, val | tp->grc_mode);
13406
13407         tg3_switch_clocks(tp);
13408
13409         /* Clear this out for sanity. */
13410         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13411
13412         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13413                               &pci_state_reg);
13414         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13415             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13416                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13417
13418                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13419                     chiprevid == CHIPREV_ID_5701_B0 ||
13420                     chiprevid == CHIPREV_ID_5701_B2 ||
13421                     chiprevid == CHIPREV_ID_5701_B5) {
13422                         void __iomem *sram_base;
13423
13424                         /* Write some dummy words into the SRAM status block
13425                          * area, see if it reads back correctly.  If the return
13426                          * value is bad, force enable the PCIX workaround.
13427                          */
13428                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13429
13430                         writel(0x00000000, sram_base);
13431                         writel(0x00000000, sram_base + 4);
13432                         writel(0xffffffff, sram_base + 4);
13433                         if (readl(sram_base) != 0x00000000)
13434                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13435                 }
13436         }
13437
13438         udelay(50);
13439         tg3_nvram_init(tp);
13440
13441         grc_misc_cfg = tr32(GRC_MISC_CFG);
13442         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13443
13444         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13445             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13446              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13447                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13448
13449         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13450             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13451                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13452         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13453                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13454                                       HOSTCC_MODE_CLRTICK_TXBD);
13455
13456                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13457                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13458                                        tp->misc_host_ctrl);
13459         }
13460
13461         /* Preserve the APE MAC_MODE bits */
13462         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13463                 tp->mac_mode = tr32(MAC_MODE) |
13464                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13465         else
13466                 tp->mac_mode = TG3_DEF_MAC_MODE;
13467
13468         /* these are limited to 10/100 only */
13469         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13470              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13471             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13472              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13473              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13474               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13475               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13476             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13477              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13478               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13479               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13480             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13481             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13482             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13483             (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13484                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13485
13486         err = tg3_phy_probe(tp);
13487         if (err) {
13488                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13489                 /* ... but do not return immediately ... */
13490                 tg3_mdio_fini(tp);
13491         }
13492
13493         tg3_read_vpd(tp);
13494         tg3_read_fw_ver(tp);
13495
13496         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13497                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13498         } else {
13499                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13500                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13501                 else
13502                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13503         }
13504
13505         /* 5700 {AX,BX} chips have a broken status block link
13506          * change bit implementation, so we must use the
13507          * status register in those cases.
13508          */
13509         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13510                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13511         else
13512                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13513
13514         /* The led_ctrl is set during tg3_phy_probe, here we might
13515          * have to force the link status polling mechanism based
13516          * upon subsystem IDs.
13517          */
13518         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13519             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13520             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13521                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13522                                   TG3_FLAG_USE_LINKCHG_REG);
13523         }
13524
13525         /* For all SERDES we poll the MAC status register. */
13526         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13527                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13528         else
13529                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13530
13531         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13532         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13533         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13534             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13535                 tp->rx_offset -= NET_IP_ALIGN;
13536 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13537                 tp->rx_copy_thresh = ~(u16)0;
13538 #endif
13539         }
13540
13541         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13542
13543         /* Increment the rx prod index on the rx std ring by at most
13544          * 8 for these chips to workaround hw errata.
13545          */
13546         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13547             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13548             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13549                 tp->rx_std_max_post = 8;
13550
13551         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13552                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13553                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13554
13555         return err;
13556 }
13557
13558 #ifdef CONFIG_SPARC
13559 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13560 {
13561         struct net_device *dev = tp->dev;
13562         struct pci_dev *pdev = tp->pdev;
13563         struct device_node *dp = pci_device_to_OF_node(pdev);
13564         const unsigned char *addr;
13565         int len;
13566
13567         addr = of_get_property(dp, "local-mac-address", &len);
13568         if (addr && len == 6) {
13569                 memcpy(dev->dev_addr, addr, 6);
13570                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13571                 return 0;
13572         }
13573         return -ENODEV;
13574 }
13575
13576 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13577 {
13578         struct net_device *dev = tp->dev;
13579
13580         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13581         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13582         return 0;
13583 }
13584 #endif
13585
13586 static int __devinit tg3_get_device_address(struct tg3 *tp)
13587 {
13588         struct net_device *dev = tp->dev;
13589         u32 hi, lo, mac_offset;
13590         int addr_ok = 0;
13591
13592 #ifdef CONFIG_SPARC
13593         if (!tg3_get_macaddr_sparc(tp))
13594                 return 0;
13595 #endif
13596
13597         mac_offset = 0x7c;
13598         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13599             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13600                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13601                         mac_offset = 0xcc;
13602                 if (tg3_nvram_lock(tp))
13603                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13604                 else
13605                         tg3_nvram_unlock(tp);
13606         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13607                 if (PCI_FUNC(tp->pdev->devfn))
13608                         mac_offset = 0xcc;
13609         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13610                 mac_offset = 0x10;
13611
13612         /* First try to get it from MAC address mailbox. */
13613         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13614         if ((hi >> 16) == 0x484b) {
13615                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13616                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13617
13618                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13619                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13620                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13621                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13622                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13623
13624                 /* Some old bootcode may report a 0 MAC address in SRAM */
13625                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13626         }
13627         if (!addr_ok) {
13628                 /* Next, try NVRAM. */
13629                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13630                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13631                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13632                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13633                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13634                 }
13635                 /* Finally just fetch it out of the MAC control regs. */
13636                 else {
13637                         hi = tr32(MAC_ADDR_0_HIGH);
13638                         lo = tr32(MAC_ADDR_0_LOW);
13639
13640                         dev->dev_addr[5] = lo & 0xff;
13641                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13642                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13643                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13644                         dev->dev_addr[1] = hi & 0xff;
13645                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13646                 }
13647         }
13648
13649         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13650 #ifdef CONFIG_SPARC
13651                 if (!tg3_get_default_macaddr_sparc(tp))
13652                         return 0;
13653 #endif
13654                 return -EINVAL;
13655         }
13656         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13657         return 0;
13658 }
13659
13660 #define BOUNDARY_SINGLE_CACHELINE       1
13661 #define BOUNDARY_MULTI_CACHELINE        2
13662
13663 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13664 {
13665         int cacheline_size;
13666         u8 byte;
13667         int goal;
13668
13669         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13670         if (byte == 0)
13671                 cacheline_size = 1024;
13672         else
13673                 cacheline_size = (int) byte * 4;
13674
13675         /* On 5703 and later chips, the boundary bits have no
13676          * effect.
13677          */
13678         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13679             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13680             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13681                 goto out;
13682
13683 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13684         goal = BOUNDARY_MULTI_CACHELINE;
13685 #else
13686 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13687         goal = BOUNDARY_SINGLE_CACHELINE;
13688 #else
13689         goal = 0;
13690 #endif
13691 #endif
13692
13693         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13694             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13695                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13696                 goto out;
13697         }
13698
13699         if (!goal)
13700                 goto out;
13701
13702         /* PCI controllers on most RISC systems tend to disconnect
13703          * when a device tries to burst across a cache-line boundary.
13704          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13705          *
13706          * Unfortunately, for PCI-E there are only limited
13707          * write-side controls for this, and thus for reads
13708          * we will still get the disconnects.  We'll also waste
13709          * these PCI cycles for both read and write for chips
13710          * other than 5700 and 5701 which do not implement the
13711          * boundary bits.
13712          */
13713         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13714             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13715                 switch (cacheline_size) {
13716                 case 16:
13717                 case 32:
13718                 case 64:
13719                 case 128:
13720                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13721                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13722                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13723                         } else {
13724                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13725                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13726                         }
13727                         break;
13728
13729                 case 256:
13730                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13731                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13732                         break;
13733
13734                 default:
13735                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13736                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13737                         break;
13738                 }
13739         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13740                 switch (cacheline_size) {
13741                 case 16:
13742                 case 32:
13743                 case 64:
13744                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13745                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13746                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13747                                 break;
13748                         }
13749                         /* fallthrough */
13750                 case 128:
13751                 default:
13752                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13753                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13754                         break;
13755                 }
13756         } else {
13757                 switch (cacheline_size) {
13758                 case 16:
13759                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13760                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13761                                         DMA_RWCTRL_WRITE_BNDRY_16);
13762                                 break;
13763                         }
13764                         /* fallthrough */
13765                 case 32:
13766                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13767                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13768                                         DMA_RWCTRL_WRITE_BNDRY_32);
13769                                 break;
13770                         }
13771                         /* fallthrough */
13772                 case 64:
13773                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13774                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13775                                         DMA_RWCTRL_WRITE_BNDRY_64);
13776                                 break;
13777                         }
13778                         /* fallthrough */
13779                 case 128:
13780                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13781                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13782                                         DMA_RWCTRL_WRITE_BNDRY_128);
13783                                 break;
13784                         }
13785                         /* fallthrough */
13786                 case 256:
13787                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13788                                 DMA_RWCTRL_WRITE_BNDRY_256);
13789                         break;
13790                 case 512:
13791                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13792                                 DMA_RWCTRL_WRITE_BNDRY_512);
13793                         break;
13794                 case 1024:
13795                 default:
13796                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13797                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13798                         break;
13799                 }
13800         }
13801
13802 out:
13803         return val;
13804 }
13805
13806 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13807 {
13808         struct tg3_internal_buffer_desc test_desc;
13809         u32 sram_dma_descs;
13810         int i, ret;
13811
13812         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13813
13814         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13815         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13816         tw32(RDMAC_STATUS, 0);
13817         tw32(WDMAC_STATUS, 0);
13818
13819         tw32(BUFMGR_MODE, 0);
13820         tw32(FTQ_RESET, 0);
13821
13822         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13823         test_desc.addr_lo = buf_dma & 0xffffffff;
13824         test_desc.nic_mbuf = 0x00002100;
13825         test_desc.len = size;
13826
13827         /*
13828          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13829          * the *second* time the tg3 driver was getting loaded after an
13830          * initial scan.
13831          *
13832          * Broadcom tells me:
13833          *   ...the DMA engine is connected to the GRC block and a DMA
13834          *   reset may affect the GRC block in some unpredictable way...
13835          *   The behavior of resets to individual blocks has not been tested.
13836          *
13837          * Broadcom noted the GRC reset will also reset all sub-components.
13838          */
13839         if (to_device) {
13840                 test_desc.cqid_sqid = (13 << 8) | 2;
13841
13842                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13843                 udelay(40);
13844         } else {
13845                 test_desc.cqid_sqid = (16 << 8) | 7;
13846
13847                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13848                 udelay(40);
13849         }
13850         test_desc.flags = 0x00000005;
13851
13852         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13853                 u32 val;
13854
13855                 val = *(((u32 *)&test_desc) + i);
13856                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13857                                        sram_dma_descs + (i * sizeof(u32)));
13858                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13859         }
13860         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13861
13862         if (to_device)
13863                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13864         else
13865                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13866
13867         ret = -ENODEV;
13868         for (i = 0; i < 40; i++) {
13869                 u32 val;
13870
13871                 if (to_device)
13872                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13873                 else
13874                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13875                 if ((val & 0xffff) == sram_dma_descs) {
13876                         ret = 0;
13877                         break;
13878                 }
13879
13880                 udelay(100);
13881         }
13882
13883         return ret;
13884 }
13885
13886 #define TEST_BUFFER_SIZE        0x2000
13887
13888 static int __devinit tg3_test_dma(struct tg3 *tp)
13889 {
13890         dma_addr_t buf_dma;
13891         u32 *buf, saved_dma_rwctrl;
13892         int ret = 0;
13893
13894         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13895         if (!buf) {
13896                 ret = -ENOMEM;
13897                 goto out_nofree;
13898         }
13899
13900         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13901                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13902
13903         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13904
13905         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13906             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13907                 goto out;
13908
13909         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13910                 /* DMA read watermark not used on PCIE */
13911                 tp->dma_rwctrl |= 0x00180000;
13912         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13913                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13914                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13915                         tp->dma_rwctrl |= 0x003f0000;
13916                 else
13917                         tp->dma_rwctrl |= 0x003f000f;
13918         } else {
13919                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13920                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13921                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13922                         u32 read_water = 0x7;
13923
13924                         /* If the 5704 is behind the EPB bridge, we can
13925                          * do the less restrictive ONE_DMA workaround for
13926                          * better performance.
13927                          */
13928                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13929                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13930                                 tp->dma_rwctrl |= 0x8000;
13931                         else if (ccval == 0x6 || ccval == 0x7)
13932                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13933
13934                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13935                                 read_water = 4;
13936                         /* Set bit 23 to enable PCIX hw bug fix */
13937                         tp->dma_rwctrl |=
13938                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13939                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13940                                 (1 << 23);
13941                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13942                         /* 5780 always in PCIX mode */
13943                         tp->dma_rwctrl |= 0x00144000;
13944                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13945                         /* 5714 always in PCIX mode */
13946                         tp->dma_rwctrl |= 0x00148000;
13947                 } else {
13948                         tp->dma_rwctrl |= 0x001b000f;
13949                 }
13950         }
13951
13952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13954                 tp->dma_rwctrl &= 0xfffffff0;
13955
13956         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13957             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13958                 /* Remove this if it causes problems for some boards. */
13959                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13960
13961                 /* On 5700/5701 chips, we need to set this bit.
13962                  * Otherwise the chip will issue cacheline transactions
13963                  * to streamable DMA memory with not all the byte
13964                  * enables turned on.  This is an error on several
13965                  * RISC PCI controllers, in particular sparc64.
13966                  *
13967                  * On 5703/5704 chips, this bit has been reassigned
13968                  * a different meaning.  In particular, it is used
13969                  * on those chips to enable a PCI-X workaround.
13970                  */
13971                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13972         }
13973
13974         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13975
13976 #if 0
13977         /* Unneeded, already done by tg3_get_invariants.  */
13978         tg3_switch_clocks(tp);
13979 #endif
13980
13981         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13982             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
13983                 goto out;
13984
13985         /* It is best to perform DMA test with maximum write burst size
13986          * to expose the 5700/5701 write DMA bug.
13987          */
13988         saved_dma_rwctrl = tp->dma_rwctrl;
13989         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
13990         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
13991
13992         while (1) {
13993                 u32 *p = buf, i;
13994
13995                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
13996                         p[i] = i;
13997
13998                 /* Send the buffer to the chip. */
13999                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14000                 if (ret) {
14001                         dev_err(&tp->pdev->dev,
14002                                 "%s: Buffer write failed. err = %d\n",
14003                                 __func__, ret);
14004                         break;
14005                 }
14006
14007 #if 0
14008                 /* validate data reached card RAM correctly. */
14009                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14010                         u32 val;
14011                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14012                         if (le32_to_cpu(val) != p[i]) {
14013                                 dev_err(&tp->pdev->dev,
14014                                         "%s: Buffer corrupted on device! "
14015                                         "(%d != %d)\n", __func__, val, i);
14016                                 /* ret = -ENODEV here? */
14017                         }
14018                         p[i] = 0;
14019                 }
14020 #endif
14021                 /* Now read it back. */
14022                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14023                 if (ret) {
14024                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14025                                 "err = %d\n", __func__, ret);
14026                         break;
14027                 }
14028
14029                 /* Verify it. */
14030                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14031                         if (p[i] == i)
14032                                 continue;
14033
14034                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14035                             DMA_RWCTRL_WRITE_BNDRY_16) {
14036                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14037                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14038                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14039                                 break;
14040                         } else {
14041                                 dev_err(&tp->pdev->dev,
14042                                         "%s: Buffer corrupted on read back! "
14043                                         "(%d != %d)\n", __func__, p[i], i);
14044                                 ret = -ENODEV;
14045                                 goto out;
14046                         }
14047                 }
14048
14049                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14050                         /* Success. */
14051                         ret = 0;
14052                         break;
14053                 }
14054         }
14055         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14056             DMA_RWCTRL_WRITE_BNDRY_16) {
14057                 static struct pci_device_id dma_wait_state_chipsets[] = {
14058                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14059                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14060                         { },
14061                 };
14062
14063                 /* DMA test passed without adjusting DMA boundary,
14064                  * now look for chipsets that are known to expose the
14065                  * DMA bug without failing the test.
14066                  */
14067                 if (pci_dev_present(dma_wait_state_chipsets)) {
14068                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14069                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14070                 } else {
14071                         /* Safe to use the calculated DMA boundary. */
14072                         tp->dma_rwctrl = saved_dma_rwctrl;
14073                 }
14074
14075                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14076         }
14077
14078 out:
14079         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14080 out_nofree:
14081         return ret;
14082 }
14083
14084 static void __devinit tg3_init_link_config(struct tg3 *tp)
14085 {
14086         tp->link_config.advertising =
14087                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14088                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14089                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14090                  ADVERTISED_Autoneg | ADVERTISED_MII);
14091         tp->link_config.speed = SPEED_INVALID;
14092         tp->link_config.duplex = DUPLEX_INVALID;
14093         tp->link_config.autoneg = AUTONEG_ENABLE;
14094         tp->link_config.active_speed = SPEED_INVALID;
14095         tp->link_config.active_duplex = DUPLEX_INVALID;
14096         tp->link_config.phy_is_low_power = 0;
14097         tp->link_config.orig_speed = SPEED_INVALID;
14098         tp->link_config.orig_duplex = DUPLEX_INVALID;
14099         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14100 }
14101
14102 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14103 {
14104         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14105             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14106                 tp->bufmgr_config.mbuf_read_dma_low_water =
14107                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14108                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14109                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14110                 tp->bufmgr_config.mbuf_high_water =
14111                         DEFAULT_MB_HIGH_WATER_57765;
14112
14113                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14114                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14115                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14116                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14117                 tp->bufmgr_config.mbuf_high_water_jumbo =
14118                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14119         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14120                 tp->bufmgr_config.mbuf_read_dma_low_water =
14121                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14122                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14123                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14124                 tp->bufmgr_config.mbuf_high_water =
14125                         DEFAULT_MB_HIGH_WATER_5705;
14126                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14127                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14128                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14129                         tp->bufmgr_config.mbuf_high_water =
14130                                 DEFAULT_MB_HIGH_WATER_5906;
14131                 }
14132
14133                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14134                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14135                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14136                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14137                 tp->bufmgr_config.mbuf_high_water_jumbo =
14138                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14139         } else {
14140                 tp->bufmgr_config.mbuf_read_dma_low_water =
14141                         DEFAULT_MB_RDMA_LOW_WATER;
14142                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14143                         DEFAULT_MB_MACRX_LOW_WATER;
14144                 tp->bufmgr_config.mbuf_high_water =
14145                         DEFAULT_MB_HIGH_WATER;
14146
14147                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14148                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14149                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14150                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14151                 tp->bufmgr_config.mbuf_high_water_jumbo =
14152                         DEFAULT_MB_HIGH_WATER_JUMBO;
14153         }
14154
14155         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14156         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14157 }
14158
14159 static char * __devinit tg3_phy_string(struct tg3 *tp)
14160 {
14161         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14162         case TG3_PHY_ID_BCM5400:        return "5400";
14163         case TG3_PHY_ID_BCM5401:        return "5401";
14164         case TG3_PHY_ID_BCM5411:        return "5411";
14165         case TG3_PHY_ID_BCM5701:        return "5701";
14166         case TG3_PHY_ID_BCM5703:        return "5703";
14167         case TG3_PHY_ID_BCM5704:        return "5704";
14168         case TG3_PHY_ID_BCM5705:        return "5705";
14169         case TG3_PHY_ID_BCM5750:        return "5750";
14170         case TG3_PHY_ID_BCM5752:        return "5752";
14171         case TG3_PHY_ID_BCM5714:        return "5714";
14172         case TG3_PHY_ID_BCM5780:        return "5780";
14173         case TG3_PHY_ID_BCM5755:        return "5755";
14174         case TG3_PHY_ID_BCM5787:        return "5787";
14175         case TG3_PHY_ID_BCM5784:        return "5784";
14176         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14177         case TG3_PHY_ID_BCM5906:        return "5906";
14178         case TG3_PHY_ID_BCM5761:        return "5761";
14179         case TG3_PHY_ID_BCM5718C:       return "5718C";
14180         case TG3_PHY_ID_BCM5718S:       return "5718S";
14181         case TG3_PHY_ID_BCM57765:       return "57765";
14182         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14183         case 0:                 return "serdes";
14184         default:                return "unknown";
14185         }
14186 }
14187
14188 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14189 {
14190         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14191                 strcpy(str, "PCI Express");
14192                 return str;
14193         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14194                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14195
14196                 strcpy(str, "PCIX:");
14197
14198                 if ((clock_ctrl == 7) ||
14199                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14200                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14201                         strcat(str, "133MHz");
14202                 else if (clock_ctrl == 0)
14203                         strcat(str, "33MHz");
14204                 else if (clock_ctrl == 2)
14205                         strcat(str, "50MHz");
14206                 else if (clock_ctrl == 4)
14207                         strcat(str, "66MHz");
14208                 else if (clock_ctrl == 6)
14209                         strcat(str, "100MHz");
14210         } else {
14211                 strcpy(str, "PCI:");
14212                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14213                         strcat(str, "66MHz");
14214                 else
14215                         strcat(str, "33MHz");
14216         }
14217         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14218                 strcat(str, ":32-bit");
14219         else
14220                 strcat(str, ":64-bit");
14221         return str;
14222 }
14223
14224 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14225 {
14226         struct pci_dev *peer;
14227         unsigned int func, devnr = tp->pdev->devfn & ~7;
14228
14229         for (func = 0; func < 8; func++) {
14230                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14231                 if (peer && peer != tp->pdev)
14232                         break;
14233                 pci_dev_put(peer);
14234         }
14235         /* 5704 can be configured in single-port mode, set peer to
14236          * tp->pdev in that case.
14237          */
14238         if (!peer) {
14239                 peer = tp->pdev;
14240                 return peer;
14241         }
14242
14243         /*
14244          * We don't need to keep the refcount elevated; there's no way
14245          * to remove one half of this device without removing the other
14246          */
14247         pci_dev_put(peer);
14248
14249         return peer;
14250 }
14251
14252 static void __devinit tg3_init_coal(struct tg3 *tp)
14253 {
14254         struct ethtool_coalesce *ec = &tp->coal;
14255
14256         memset(ec, 0, sizeof(*ec));
14257         ec->cmd = ETHTOOL_GCOALESCE;
14258         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14259         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14260         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14261         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14262         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14263         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14264         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14265         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14266         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14267
14268         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14269                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14270                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14271                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14272                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14273                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14274         }
14275
14276         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14277                 ec->rx_coalesce_usecs_irq = 0;
14278                 ec->tx_coalesce_usecs_irq = 0;
14279                 ec->stats_block_coalesce_usecs = 0;
14280         }
14281 }
14282
14283 static const struct net_device_ops tg3_netdev_ops = {
14284         .ndo_open               = tg3_open,
14285         .ndo_stop               = tg3_close,
14286         .ndo_start_xmit         = tg3_start_xmit,
14287         .ndo_get_stats          = tg3_get_stats,
14288         .ndo_validate_addr      = eth_validate_addr,
14289         .ndo_set_multicast_list = tg3_set_rx_mode,
14290         .ndo_set_mac_address    = tg3_set_mac_addr,
14291         .ndo_do_ioctl           = tg3_ioctl,
14292         .ndo_tx_timeout         = tg3_tx_timeout,
14293         .ndo_change_mtu         = tg3_change_mtu,
14294 #if TG3_VLAN_TAG_USED
14295         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14296 #endif
14297 #ifdef CONFIG_NET_POLL_CONTROLLER
14298         .ndo_poll_controller    = tg3_poll_controller,
14299 #endif
14300 };
14301
14302 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14303         .ndo_open               = tg3_open,
14304         .ndo_stop               = tg3_close,
14305         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14306         .ndo_get_stats          = tg3_get_stats,
14307         .ndo_validate_addr      = eth_validate_addr,
14308         .ndo_set_multicast_list = tg3_set_rx_mode,
14309         .ndo_set_mac_address    = tg3_set_mac_addr,
14310         .ndo_do_ioctl           = tg3_ioctl,
14311         .ndo_tx_timeout         = tg3_tx_timeout,
14312         .ndo_change_mtu         = tg3_change_mtu,
14313 #if TG3_VLAN_TAG_USED
14314         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14315 #endif
14316 #ifdef CONFIG_NET_POLL_CONTROLLER
14317         .ndo_poll_controller    = tg3_poll_controller,
14318 #endif
14319 };
14320
14321 static int __devinit tg3_init_one(struct pci_dev *pdev,
14322                                   const struct pci_device_id *ent)
14323 {
14324         struct net_device *dev;
14325         struct tg3 *tp;
14326         int i, err, pm_cap;
14327         u32 sndmbx, rcvmbx, intmbx;
14328         char str[40];
14329         u64 dma_mask, persist_dma_mask;
14330
14331         printk_once(KERN_INFO "%s\n", version);
14332
14333         err = pci_enable_device(pdev);
14334         if (err) {
14335                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14336                 return err;
14337         }
14338
14339         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14340         if (err) {
14341                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14342                 goto err_out_disable_pdev;
14343         }
14344
14345         pci_set_master(pdev);
14346
14347         /* Find power-management capability. */
14348         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14349         if (pm_cap == 0) {
14350                 dev_err(&pdev->dev,
14351                         "Cannot find Power Management capability, aborting\n");
14352                 err = -EIO;
14353                 goto err_out_free_res;
14354         }
14355
14356         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14357         if (!dev) {
14358                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14359                 err = -ENOMEM;
14360                 goto err_out_free_res;
14361         }
14362
14363         SET_NETDEV_DEV(dev, &pdev->dev);
14364
14365 #if TG3_VLAN_TAG_USED
14366         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14367 #endif
14368
14369         tp = netdev_priv(dev);
14370         tp->pdev = pdev;
14371         tp->dev = dev;
14372         tp->pm_cap = pm_cap;
14373         tp->rx_mode = TG3_DEF_RX_MODE;
14374         tp->tx_mode = TG3_DEF_TX_MODE;
14375
14376         if (tg3_debug > 0)
14377                 tp->msg_enable = tg3_debug;
14378         else
14379                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14380
14381         /* The word/byte swap controls here control register access byte
14382          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14383          * setting below.
14384          */
14385         tp->misc_host_ctrl =
14386                 MISC_HOST_CTRL_MASK_PCI_INT |
14387                 MISC_HOST_CTRL_WORD_SWAP |
14388                 MISC_HOST_CTRL_INDIR_ACCESS |
14389                 MISC_HOST_CTRL_PCISTATE_RW;
14390
14391         /* The NONFRM (non-frame) byte/word swap controls take effect
14392          * on descriptor entries, anything which isn't packet data.
14393          *
14394          * The StrongARM chips on the board (one for tx, one for rx)
14395          * are running in big-endian mode.
14396          */
14397         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14398                         GRC_MODE_WSWAP_NONFRM_DATA);
14399 #ifdef __BIG_ENDIAN
14400         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14401 #endif
14402         spin_lock_init(&tp->lock);
14403         spin_lock_init(&tp->indirect_lock);
14404         INIT_WORK(&tp->reset_task, tg3_reset_task);
14405
14406         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14407         if (!tp->regs) {
14408                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14409                 err = -ENOMEM;
14410                 goto err_out_free_dev;
14411         }
14412
14413         tg3_init_link_config(tp);
14414
14415         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14416         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14417
14418         dev->ethtool_ops = &tg3_ethtool_ops;
14419         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14420         dev->irq = pdev->irq;
14421
14422         err = tg3_get_invariants(tp);
14423         if (err) {
14424                 dev_err(&pdev->dev,
14425                         "Problem fetching invariants of chip, aborting\n");
14426                 goto err_out_iounmap;
14427         }
14428
14429         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14430             tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14431                 dev->netdev_ops = &tg3_netdev_ops;
14432         else
14433                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14434
14435
14436         /* The EPB bridge inside 5714, 5715, and 5780 and any
14437          * device behind the EPB cannot support DMA addresses > 40-bit.
14438          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14439          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14440          * do DMA address check in tg3_start_xmit().
14441          */
14442         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14443                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14444         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14445                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14446 #ifdef CONFIG_HIGHMEM
14447                 dma_mask = DMA_BIT_MASK(64);
14448 #endif
14449         } else
14450                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14451
14452         /* Configure DMA attributes. */
14453         if (dma_mask > DMA_BIT_MASK(32)) {
14454                 err = pci_set_dma_mask(pdev, dma_mask);
14455                 if (!err) {
14456                         dev->features |= NETIF_F_HIGHDMA;
14457                         err = pci_set_consistent_dma_mask(pdev,
14458                                                           persist_dma_mask);
14459                         if (err < 0) {
14460                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14461                                         "DMA for consistent allocations\n");
14462                                 goto err_out_iounmap;
14463                         }
14464                 }
14465         }
14466         if (err || dma_mask == DMA_BIT_MASK(32)) {
14467                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14468                 if (err) {
14469                         dev_err(&pdev->dev,
14470                                 "No usable DMA configuration, aborting\n");
14471                         goto err_out_iounmap;
14472                 }
14473         }
14474
14475         tg3_init_bufmgr_config(tp);
14476
14477         /* Selectively allow TSO based on operating conditions */
14478         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14479             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14480                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14481         else {
14482                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14483                 tp->fw_needed = NULL;
14484         }
14485
14486         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14487                 tp->fw_needed = FIRMWARE_TG3;
14488
14489         /* TSO is on by default on chips that support hardware TSO.
14490          * Firmware TSO on older chips gives lower performance, so it
14491          * is off by default, but can be enabled using ethtool.
14492          */
14493         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14494             (dev->features & NETIF_F_IP_CSUM))
14495                 dev->features |= NETIF_F_TSO;
14496
14497         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14498             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14499                 if (dev->features & NETIF_F_IPV6_CSUM)
14500                         dev->features |= NETIF_F_TSO6;
14501                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14502                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14503                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14504                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14505                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14506                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14507                         dev->features |= NETIF_F_TSO_ECN;
14508         }
14509
14510         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14511             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14512             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14513                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14514                 tp->rx_pending = 63;
14515         }
14516
14517         err = tg3_get_device_address(tp);
14518         if (err) {
14519                 dev_err(&pdev->dev,
14520                         "Could not obtain valid ethernet address, aborting\n");
14521                 goto err_out_iounmap;
14522         }
14523
14524         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14525                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14526                 if (!tp->aperegs) {
14527                         dev_err(&pdev->dev,
14528                                 "Cannot map APE registers, aborting\n");
14529                         err = -ENOMEM;
14530                         goto err_out_iounmap;
14531                 }
14532
14533                 tg3_ape_lock_init(tp);
14534
14535                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14536                         tg3_read_dash_ver(tp);
14537         }
14538
14539         /*
14540          * Reset chip in case UNDI or EFI driver did not shutdown
14541          * DMA self test will enable WDMAC and we'll see (spurious)
14542          * pending DMA on the PCI bus at that point.
14543          */
14544         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14545             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14546                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14547                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14548         }
14549
14550         err = tg3_test_dma(tp);
14551         if (err) {
14552                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14553                 goto err_out_apeunmap;
14554         }
14555
14556         /* flow control autonegotiation is default behavior */
14557         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14558         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14559
14560         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14561         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14562         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14563         for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14564                 struct tg3_napi *tnapi = &tp->napi[i];
14565
14566                 tnapi->tp = tp;
14567                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14568
14569                 tnapi->int_mbox = intmbx;
14570                 if (i < 4)
14571                         intmbx += 0x8;
14572                 else
14573                         intmbx += 0x4;
14574
14575                 tnapi->consmbox = rcvmbx;
14576                 tnapi->prodmbox = sndmbx;
14577
14578                 if (i) {
14579                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14580                         netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14581                 } else {
14582                         tnapi->coal_now = HOSTCC_MODE_NOW;
14583                         netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14584                 }
14585
14586                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14587                         break;
14588
14589                 /*
14590                  * If we support MSIX, we'll be using RSS.  If we're using
14591                  * RSS, the first vector only handles link interrupts and the
14592                  * remaining vectors handle rx and tx interrupts.  Reuse the
14593                  * mailbox values for the next iteration.  The values we setup
14594                  * above are still useful for the single vectored mode.
14595                  */
14596                 if (!i)
14597                         continue;
14598
14599                 rcvmbx += 0x8;
14600
14601                 if (sndmbx & 0x4)
14602                         sndmbx -= 0x4;
14603                 else
14604                         sndmbx += 0xc;
14605         }
14606
14607         tg3_init_coal(tp);
14608
14609         pci_set_drvdata(pdev, dev);
14610
14611         err = register_netdev(dev);
14612         if (err) {
14613                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14614                 goto err_out_apeunmap;
14615         }
14616
14617         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14618                     tp->board_part_number,
14619                     tp->pci_chip_rev_id,
14620                     tg3_bus_string(tp, str),
14621                     dev->dev_addr);
14622
14623         if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14624                 struct phy_device *phydev;
14625                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14626                 netdev_info(dev,
14627                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14628                             phydev->drv->name, dev_name(&phydev->dev));
14629         } else
14630                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14631                             "(WireSpeed[%d])\n", tg3_phy_string(tp),
14632                             ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14633                              ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14634                               "10/100/1000Base-T")),
14635                             (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14636
14637         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14638                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14639                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14640                     (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14641                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14642                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14643         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14644                     tp->dma_rwctrl,
14645                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14646                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14647
14648         return 0;
14649
14650 err_out_apeunmap:
14651         if (tp->aperegs) {
14652                 iounmap(tp->aperegs);
14653                 tp->aperegs = NULL;
14654         }
14655
14656 err_out_iounmap:
14657         if (tp->regs) {
14658                 iounmap(tp->regs);
14659                 tp->regs = NULL;
14660         }
14661
14662 err_out_free_dev:
14663         free_netdev(dev);
14664
14665 err_out_free_res:
14666         pci_release_regions(pdev);
14667
14668 err_out_disable_pdev:
14669         pci_disable_device(pdev);
14670         pci_set_drvdata(pdev, NULL);
14671         return err;
14672 }
14673
14674 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14675 {
14676         struct net_device *dev = pci_get_drvdata(pdev);
14677
14678         if (dev) {
14679                 struct tg3 *tp = netdev_priv(dev);
14680
14681                 if (tp->fw)
14682                         release_firmware(tp->fw);
14683
14684                 flush_scheduled_work();
14685
14686                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14687                         tg3_phy_fini(tp);
14688                         tg3_mdio_fini(tp);
14689                 }
14690
14691                 unregister_netdev(dev);
14692                 if (tp->aperegs) {
14693                         iounmap(tp->aperegs);
14694                         tp->aperegs = NULL;
14695                 }
14696                 if (tp->regs) {
14697                         iounmap(tp->regs);
14698                         tp->regs = NULL;
14699                 }
14700                 free_netdev(dev);
14701                 pci_release_regions(pdev);
14702                 pci_disable_device(pdev);
14703                 pci_set_drvdata(pdev, NULL);
14704         }
14705 }
14706
14707 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14708 {
14709         struct net_device *dev = pci_get_drvdata(pdev);
14710         struct tg3 *tp = netdev_priv(dev);
14711         pci_power_t target_state;
14712         int err;
14713
14714         /* PCI register 4 needs to be saved whether netif_running() or not.
14715          * MSI address and data need to be saved if using MSI and
14716          * netif_running().
14717          */
14718         pci_save_state(pdev);
14719
14720         if (!netif_running(dev))
14721                 return 0;
14722
14723         flush_scheduled_work();
14724         tg3_phy_stop(tp);
14725         tg3_netif_stop(tp);
14726
14727         del_timer_sync(&tp->timer);
14728
14729         tg3_full_lock(tp, 1);
14730         tg3_disable_ints(tp);
14731         tg3_full_unlock(tp);
14732
14733         netif_device_detach(dev);
14734
14735         tg3_full_lock(tp, 0);
14736         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14737         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14738         tg3_full_unlock(tp);
14739
14740         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14741
14742         err = tg3_set_power_state(tp, target_state);
14743         if (err) {
14744                 int err2;
14745
14746                 tg3_full_lock(tp, 0);
14747
14748                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14749                 err2 = tg3_restart_hw(tp, 1);
14750                 if (err2)
14751                         goto out;
14752
14753                 tp->timer.expires = jiffies + tp->timer_offset;
14754                 add_timer(&tp->timer);
14755
14756                 netif_device_attach(dev);
14757                 tg3_netif_start(tp);
14758
14759 out:
14760                 tg3_full_unlock(tp);
14761
14762                 if (!err2)
14763                         tg3_phy_start(tp);
14764         }
14765
14766         return err;
14767 }
14768
14769 static int tg3_resume(struct pci_dev *pdev)
14770 {
14771         struct net_device *dev = pci_get_drvdata(pdev);
14772         struct tg3 *tp = netdev_priv(dev);
14773         int err;
14774
14775         pci_restore_state(tp->pdev);
14776
14777         if (!netif_running(dev))
14778                 return 0;
14779
14780         err = tg3_set_power_state(tp, PCI_D0);
14781         if (err)
14782                 return err;
14783
14784         netif_device_attach(dev);
14785
14786         tg3_full_lock(tp, 0);
14787
14788         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14789         err = tg3_restart_hw(tp, 1);
14790         if (err)
14791                 goto out;
14792
14793         tp->timer.expires = jiffies + tp->timer_offset;
14794         add_timer(&tp->timer);
14795
14796         tg3_netif_start(tp);
14797
14798 out:
14799         tg3_full_unlock(tp);
14800
14801         if (!err)
14802                 tg3_phy_start(tp);
14803
14804         return err;
14805 }
14806
14807 static struct pci_driver tg3_driver = {
14808         .name           = DRV_MODULE_NAME,
14809         .id_table       = tg3_pci_tbl,
14810         .probe          = tg3_init_one,
14811         .remove         = __devexit_p(tg3_remove_one),
14812         .suspend        = tg3_suspend,
14813         .resume         = tg3_resume
14814 };
14815
14816 static int __init tg3_init(void)
14817 {
14818         return pci_register_driver(&tg3_driver);
14819 }
14820
14821 static void __exit tg3_cleanup(void)
14822 {
14823         pci_unregister_driver(&tg3_driver);
14824 }
14825
14826 module_init(tg3_init);
14827 module_exit(tg3_cleanup);