drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     114
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "September 30, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_STD_RING_SIZE(tp) \
 105         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 106           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 107          RX_STD_MAX_SIZE_5717 : 512)
 108 #define TG3_DEF_RX_RING_PENDING         200
 109 #define TG3_RX_JMB_RING_SIZE(tp) \
 110         ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || \
 111           GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) ? \
 112          1024 : 256)
 113 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 114 #define TG3_RSS_INDIR_TBL_SIZE          128
 115
 116 /* Do not place this n-ring entries value into the tp struct itself,
 117  * we really want to expose these constants to GCC so that modulo et
 118  * al.  operations are done with shifts and masks instead of with
 119  * hw multiply/modulo instructions.  Another solution would be to
 120  * replace things like '% foo' with '& (foo - 1)'.
 121  */
 122
 123 #define TG3_TX_RING_SIZE                512
 124 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 125
 126 #define TG3_RX_STD_RING_BYTES(tp) \
 127         (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
 128 #define TG3_RX_JMB_RING_BYTES(tp) \
 129         (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
 130 #define TG3_RX_RCB_RING_BYTES(tp) \
 131         (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
 132 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 133                                  TG3_TX_RING_SIZE)
 134 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 135
 136 #define TG3_RX_DMA_ALIGN                16
 137 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 138
 139 #define TG3_DMA_BYTE_ENAB               64
 140
 141 #define TG3_RX_STD_DMA_SZ               1536
 142 #define TG3_RX_JMB_DMA_SZ               9046
 143
 144 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 145
 146 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 147 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 148
 149 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
 150         (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
 151
 152 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
 153         (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
 154
 155 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 156  * that are at least dword aligned when used in PCIX mode.  The driver
 157  * works around this bug by double copying the packet.  This workaround
 158  * is built into the normal double copy length check for efficiency.
 159  *
 160  * However, the double copy is only necessary on those architectures
 161  * where unaligned memory accesses are inefficient.  For those architectures
 162  * where unaligned memory accesses incur little penalty, we can reintegrate
 163  * the 5701 in the normal rx path.  Doing so saves a device structure
 164  * dereference by hardcoding the double copy threshold in place.
 165  */
 166 #define TG3_RX_COPY_THRESHOLD           256
 167 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 168         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 169 #else
 170         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 171 #endif
 172
 173 /* minimum number of free TX descriptors required to wake up TX process */
 174 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 175
 176 #define TG3_RAW_IP_ALIGN 2
 177
 178 /* number of ETHTOOL_GSTATS u64's */
 179 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 180
 181 #define TG3_NUM_TEST            6
 182
 183 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 184
 185 #define FIRMWARE_TG3            "tigon/tg3.bin"
 186 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 187 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 188
 189 static char version[] __devinitdata =
 190         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 191
 192 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 193 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 194 MODULE_LICENSE("GPL");
 195 MODULE_VERSION(DRV_MODULE_VERSION);
 196 MODULE_FIRMWARE(FIRMWARE_TG3);
 197 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 198 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 199
 200 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 201 module_param(tg3_debug, int, 0);
 202 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 203
 204 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 281         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 282         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 283         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 284         {}
 285 };
 286
 287 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 288
 289 static const struct {
 290         const char string[ETH_GSTRING_LEN];
 291 } ethtool_stats_keys[TG3_NUM_STATS] = {
 292         { "rx_octets" },
 293         { "rx_fragments" },
 294         { "rx_ucast_packets" },
 295         { "rx_mcast_packets" },
 296         { "rx_bcast_packets" },
 297         { "rx_fcs_errors" },
 298         { "rx_align_errors" },
 299         { "rx_xon_pause_rcvd" },
 300         { "rx_xoff_pause_rcvd" },
 301         { "rx_mac_ctrl_rcvd" },
 302         { "rx_xoff_entered" },
 303         { "rx_frame_too_long_errors" },
 304         { "rx_jabbers" },
 305         { "rx_undersize_packets" },
 306         { "rx_in_length_errors" },
 307         { "rx_out_length_errors" },
 308         { "rx_64_or_less_octet_packets" },
 309         { "rx_65_to_127_octet_packets" },
 310         { "rx_128_to_255_octet_packets" },
 311         { "rx_256_to_511_octet_packets" },
 312         { "rx_512_to_1023_octet_packets" },
 313         { "rx_1024_to_1522_octet_packets" },
 314         { "rx_1523_to_2047_octet_packets" },
 315         { "rx_2048_to_4095_octet_packets" },
 316         { "rx_4096_to_8191_octet_packets" },
 317         { "rx_8192_to_9022_octet_packets" },
 318
 319         { "tx_octets" },
 320         { "tx_collisions" },
 321
 322         { "tx_xon_sent" },
 323         { "tx_xoff_sent" },
 324         { "tx_flow_control" },
 325         { "tx_mac_errors" },
 326         { "tx_single_collisions" },
 327         { "tx_mult_collisions" },
 328         { "tx_deferred" },
 329         { "tx_excessive_collisions" },
 330         { "tx_late_collisions" },
 331         { "tx_collide_2times" },
 332         { "tx_collide_3times" },
 333         { "tx_collide_4times" },
 334         { "tx_collide_5times" },
 335         { "tx_collide_6times" },
 336         { "tx_collide_7times" },
 337         { "tx_collide_8times" },
 338         { "tx_collide_9times" },
 339         { "tx_collide_10times" },
 340         { "tx_collide_11times" },
 341         { "tx_collide_12times" },
 342         { "tx_collide_13times" },
 343         { "tx_collide_14times" },
 344         { "tx_collide_15times" },
 345         { "tx_ucast_packets" },
 346         { "tx_mcast_packets" },
 347         { "tx_bcast_packets" },
 348         { "tx_carrier_sense_errors" },
 349         { "tx_discards" },
 350         { "tx_errors" },
 351
 352         { "dma_writeq_full" },
 353         { "dma_write_prioq_full" },
 354         { "rxbds_empty" },
 355         { "rx_discards" },
 356         { "rx_errors" },
 357         { "rx_threshold_hit" },
 358
 359         { "dma_readq_full" },
 360         { "dma_read_prioq_full" },
 361         { "tx_comp_queue_full" },
 362
 363         { "ring_set_send_prod_index" },
 364         { "ring_status_update" },
 365         { "nic_irqs" },
 366         { "nic_avoided_irqs" },
 367         { "nic_tx_threshold_hit" }
 368 };
 369
 370 static const struct {
 371         const char string[ETH_GSTRING_LEN];
 372 } ethtool_test_keys[TG3_NUM_TEST] = {
 373         { "nvram test     (online) " },
 374         { "link test      (online) " },
 375         { "register test  (offline)" },
 376         { "memory test    (offline)" },
 377         { "loopback test  (offline)" },
 378         { "interrupt test (offline)" },
 379 };
 380
 381 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 382 {
 383         writel(val, tp->regs + off);
 384 }
 385
 386 static u32 tg3_read32(struct tg3 *tp, u32 off)
 387 {
 388         return readl(tp->regs + off);
 389 }
 390
 391 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 392 {
 393         writel(val, tp->aperegs + off);
 394 }
 395
 396 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 397 {
 398         return readl(tp->aperegs + off);
 399 }
 400
 401 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 402 {
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&tp->indirect_lock, flags);
 406         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 407         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 408         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 409 }
 410
 411 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 412 {
 413         writel(val, tp->regs + off);
 414         readl(tp->regs + off);
 415 }
 416
 417 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 418 {
 419         unsigned long flags;
 420         u32 val;
 421
 422         spin_lock_irqsave(&tp->indirect_lock, flags);
 423         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 424         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 425         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 426         return val;
 427 }
 428
 429 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 430 {
 431         unsigned long flags;
 432
 433         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 434                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 435                                        TG3_64BIT_REG_LOW, val);
 436                 return;
 437         }
 438         if (off == TG3_RX_STD_PROD_IDX_REG) {
 439                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 440                                        TG3_64BIT_REG_LOW, val);
 441                 return;
 442         }
 443
 444         spin_lock_irqsave(&tp->indirect_lock, flags);
 445         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 446         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 447         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 448
 449         /* In indirect mode when disabling interrupts, we also need
 450          * to clear the interrupt bit in the GRC local ctrl register.
 451          */
 452         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 453             (val == 0x1)) {
 454                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 455                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 456         }
 457 }
 458
 459 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 460 {
 461         unsigned long flags;
 462         u32 val;
 463
 464         spin_lock_irqsave(&tp->indirect_lock, flags);
 465         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 466         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 467         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 468         return val;
 469 }
 470
 471 /* usec_wait specifies the wait time in usec when writing to certain registers
 472  * where it is unsafe to read back the register without some delay.
 473  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 474  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 475  */
 476 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 477 {
 478         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 479             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 480                 /* Non-posted methods */
 481                 tp->write32(tp, off, val);
 482         else {
 483                 /* Posted method */
 484                 tg3_write32(tp, off, val);
 485                 if (usec_wait)
 486                         udelay(usec_wait);
 487                 tp->read32(tp, off);
 488         }
 489         /* Wait again after the read for the posted method to guarantee that
 490          * the wait time is met.
 491          */
 492         if (usec_wait)
 493                 udelay(usec_wait);
 494 }
 495
 496 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 497 {
 498         tp->write32_mbox(tp, off, val);
 499         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 500             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 501                 tp->read32_mbox(tp, off);
 502 }
 503
 504 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 505 {
 506         void __iomem *mbox = tp->regs + off;
 507         writel(val, mbox);
 508         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 509                 writel(val, mbox);
 510         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 511                 readl(mbox);
 512 }
 513
 514 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 515 {
 516         return readl(tp->regs + off + GRCMBOX_BASE);
 517 }
 518
 519 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 520 {
 521         writel(val, tp->regs + off + GRCMBOX_BASE);
 522 }
 523
 524 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 525 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 526 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 527 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 528 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 529
 530 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 531 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 532 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 533 #define tr32(reg)                       tp->read32(tp, reg)
 534
 535 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 536 {
 537         unsigned long flags;
 538
 539         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 540             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 541                 return;
 542
 543         spin_lock_irqsave(&tp->indirect_lock, flags);
 544         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 545                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 547
 548                 /* Always leave this as zero. */
 549                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 550         } else {
 551                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 552                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 553
 554                 /* Always leave this as zero. */
 555                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 556         }
 557         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 558 }
 559
 560 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 561 {
 562         unsigned long flags;
 563
 564         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 565             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 566                 *val = 0;
 567                 return;
 568         }
 569
 570         spin_lock_irqsave(&tp->indirect_lock, flags);
 571         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 572                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 573                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 574
 575                 /* Always leave this as zero. */
 576                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 577         } else {
 578                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 579                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 580
 581                 /* Always leave this as zero. */
 582                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 583         }
 584         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 585 }
 586
 587 static void tg3_ape_lock_init(struct tg3 *tp)
 588 {
 589         int i;
 590         u32 regbase;
 591
 592         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 593                 regbase = TG3_APE_LOCK_GRANT;
 594         else
 595                 regbase = TG3_APE_PER_LOCK_GRANT;
 596
 597         /* Make sure the driver hasn't any stale locks. */
 598         for (i = 0; i < 8; i++)
 599                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 600 }
 601
 602 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 603 {
 604         int i, off;
 605         int ret = 0;
 606         u32 status, req, gnt;
 607
 608         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 609                 return 0;
 610
 611         switch (locknum) {
 612         case TG3_APE_LOCK_GRC:
 613         case TG3_APE_LOCK_MEM:
 614                 break;
 615         default:
 616                 return -EINVAL;
 617         }
 618
 619         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 620                 req = TG3_APE_LOCK_REQ;
 621                 gnt = TG3_APE_LOCK_GRANT;
 622         } else {
 623                 req = TG3_APE_PER_LOCK_REQ;
 624                 gnt = TG3_APE_PER_LOCK_GRANT;
 625         }
 626
 627         off = 4 * locknum;
 628
 629         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 630
 631         /* Wait for up to 1 millisecond to acquire lock. */
 632         for (i = 0; i < 100; i++) {
 633                 status = tg3_ape_read32(tp, gnt + off);
 634                 if (status == APE_LOCK_GRANT_DRIVER)
 635                         break;
 636                 udelay(10);
 637         }
 638
 639         if (status != APE_LOCK_GRANT_DRIVER) {
 640                 /* Revoke the lock request. */
 641                 tg3_ape_write32(tp, gnt + off,
 642                                 APE_LOCK_GRANT_DRIVER);
 643
 644                 ret = -EBUSY;
 645         }
 646
 647         return ret;
 648 }
 649
 650 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 651 {
 652         u32 gnt;
 653
 654         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 655                 return;
 656
 657         switch (locknum) {
 658         case TG3_APE_LOCK_GRC:
 659         case TG3_APE_LOCK_MEM:
 660                 break;
 661         default:
 662                 return;
 663         }
 664
 665         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 666                 gnt = TG3_APE_LOCK_GRANT;
 667         else
 668                 gnt = TG3_APE_PER_LOCK_GRANT;
 669
 670         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 671 }
 672
 673 static void tg3_disable_ints(struct tg3 *tp)
 674 {
 675         int i;
 676
 677         tw32(TG3PCI_MISC_HOST_CTRL,
 678              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 679         for (i = 0; i < tp->irq_max; i++)
 680                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 681 }
 682
 683 static void tg3_enable_ints(struct tg3 *tp)
 684 {
 685         int i;
 686
 687         tp->irq_sync = 0;
 688         wmb();
 689
 690         tw32(TG3PCI_MISC_HOST_CTRL,
 691              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 692
 693         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 694         for (i = 0; i < tp->irq_cnt; i++) {
 695                 struct tg3_napi *tnapi = &tp->napi[i];
 696
 697                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 698                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 699                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 700
 701                 tp->coal_now |= tnapi->coal_now;
 702         }
 703
 704         /* Force an initial interrupt */
 705         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 706             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 707                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 708         else
 709                 tw32(HOSTCC_MODE, tp->coal_now);
 710
 711         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 712 }
 713
 714 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 715 {
 716         struct tg3 *tp = tnapi->tp;
 717         struct tg3_hw_status *sblk = tnapi->hw_status;
 718         unsigned int work_exists = 0;
 719
 720         /* check for phy events */
 721         if (!(tp->tg3_flags &
 722               (TG3_FLAG_USE_LINKCHG_REG |
 723                TG3_FLAG_POLL_SERDES))) {
 724                 if (sblk->status & SD_STATUS_LINK_CHG)
 725                         work_exists = 1;
 726         }
 727         /* check for RX/TX work to do */
 728         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 729             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 730                 work_exists = 1;
 731
 732         return work_exists;
 733 }
 734
 735 /* tg3_int_reenable
 736  *  similar to tg3_enable_ints, but it accurately determines whether there
 737  *  is new work pending and can return without flushing the PIO write
 738  *  which reenables interrupts
 739  */
 740 static void tg3_int_reenable(struct tg3_napi *tnapi)
 741 {
 742         struct tg3 *tp = tnapi->tp;
 743
 744         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 745         mmiowb();
 746
 747         /* When doing tagged status, this work check is unnecessary.
 748          * The last_tag we write above tells the chip which piece of
 749          * work we've completed.
 750          */
 751         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 752             tg3_has_work(tnapi))
 753                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 754                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 755 }
 756
 757 static void tg3_switch_clocks(struct tg3 *tp)
 758 {
 759         u32 clock_ctrl;
 760         u32 orig_clock_ctrl;
 761
 762         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 763             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 764                 return;
 765
 766         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 767
 768         orig_clock_ctrl = clock_ctrl;
 769         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 770                        CLOCK_CTRL_CLKRUN_OENABLE |
 771                        0x1f);
 772         tp->pci_clock_ctrl = clock_ctrl;
 773
 774         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 775                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 776                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 777                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 778                 }
 779         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 780                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 781                             clock_ctrl |
 782                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 783                             40);
 784                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 785                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 786                             40);
 787         }
 788         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 789 }
 790
 791 #define PHY_BUSY_LOOPS  5000
 792
 793 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 794 {
 795         u32 frame_val;
 796         unsigned int loops;
 797         int ret;
 798
 799         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 800                 tw32_f(MAC_MI_MODE,
 801                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 802                 udelay(80);
 803         }
 804
 805         *val = 0x0;
 806
 807         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 808                       MI_COM_PHY_ADDR_MASK);
 809         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 810                       MI_COM_REG_ADDR_MASK);
 811         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 812
 813         tw32_f(MAC_MI_COM, frame_val);
 814
 815         loops = PHY_BUSY_LOOPS;
 816         while (loops != 0) {
 817                 udelay(10);
 818                 frame_val = tr32(MAC_MI_COM);
 819
 820                 if ((frame_val & MI_COM_BUSY) == 0) {
 821                         udelay(5);
 822                         frame_val = tr32(MAC_MI_COM);
 823                         break;
 824                 }
 825                 loops -= 1;
 826         }
 827
 828         ret = -EBUSY;
 829         if (loops != 0) {
 830                 *val = frame_val & MI_COM_DATA_MASK;
 831                 ret = 0;
 832         }
 833
 834         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 835                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 836                 udelay(80);
 837         }
 838
 839         return ret;
 840 }
 841
 842 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 843 {
 844         u32 frame_val;
 845         unsigned int loops;
 846         int ret;
 847
 848         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 849             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 850                 return 0;
 851
 852         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 853                 tw32_f(MAC_MI_MODE,
 854                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 855                 udelay(80);
 856         }
 857
 858         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 859                       MI_COM_PHY_ADDR_MASK);
 860         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 861                       MI_COM_REG_ADDR_MASK);
 862         frame_val |= (val & MI_COM_DATA_MASK);
 863         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 864
 865         tw32_f(MAC_MI_COM, frame_val);
 866
 867         loops = PHY_BUSY_LOOPS;
 868         while (loops != 0) {
 869                 udelay(10);
 870                 frame_val = tr32(MAC_MI_COM);
 871                 if ((frame_val & MI_COM_BUSY) == 0) {
 872                         udelay(5);
 873                         frame_val = tr32(MAC_MI_COM);
 874                         break;
 875                 }
 876                 loops -= 1;
 877         }
 878
 879         ret = -EBUSY;
 880         if (loops != 0)
 881                 ret = 0;
 882
 883         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 884                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 885                 udelay(80);
 886         }
 887
 888         return ret;
 889 }
 890
 891 static int tg3_bmcr_reset(struct tg3 *tp)
 892 {
 893         u32 phy_control;
 894         int limit, err;
 895
 896         /* OK, reset it, and poll the BMCR_RESET bit until it
 897          * clears or we time out.
 898          */
 899         phy_control = BMCR_RESET;
 900         err = tg3_writephy(tp, MII_BMCR, phy_control);
 901         if (err != 0)
 902                 return -EBUSY;
 903
 904         limit = 5000;
 905         while (limit--) {
 906                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 907                 if (err != 0)
 908                         return -EBUSY;
 909
 910                 if ((phy_control & BMCR_RESET) == 0) {
 911                         udelay(40);
 912                         break;
 913                 }
 914                 udelay(10);
 915         }
 916         if (limit < 0)
 917                 return -EBUSY;
 918
 919         return 0;
 920 }
 921
 922 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 923 {
 924         struct tg3 *tp = bp->priv;
 925         u32 val;
 926
 927         spin_lock_bh(&tp->lock);
 928
 929         if (tg3_readphy(tp, reg, &val))
 930                 val = -EIO;
 931
 932         spin_unlock_bh(&tp->lock);
 933
 934         return val;
 935 }
 936
 937 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 938 {
 939         struct tg3 *tp = bp->priv;
 940         u32 ret = 0;
 941
 942         spin_lock_bh(&tp->lock);
 943
 944         if (tg3_writephy(tp, reg, val))
 945                 ret = -EIO;
 946
 947         spin_unlock_bh(&tp->lock);
 948
 949         return ret;
 950 }
 951
 952 static int tg3_mdio_reset(struct mii_bus *bp)
 953 {
 954         return 0;
 955 }
 956
 957 static void tg3_mdio_config_5785(struct tg3 *tp)
 958 {
 959         u32 val;
 960         struct phy_device *phydev;
 961
 962         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 963         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 964         case PHY_ID_BCM50610:
 965         case PHY_ID_BCM50610M:
 966                 val = MAC_PHYCFG2_50610_LED_MODES;
 967                 break;
 968         case PHY_ID_BCMAC131:
 969                 val = MAC_PHYCFG2_AC131_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8211C:
 972                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 973                 break;
 974         case PHY_ID_RTL8201E:
 975                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 976                 break;
 977         default:
 978                 return;
 979         }
 980
 981         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 982                 tw32(MAC_PHYCFG2, val);
 983
 984                 val = tr32(MAC_PHYCFG1);
 985                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 986                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 987                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 988                 tw32(MAC_PHYCFG1, val);
 989
 990                 return;
 991         }
 992
 993         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 994                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 995                        MAC_PHYCFG2_FMODE_MASK_MASK |
 996                        MAC_PHYCFG2_GMODE_MASK_MASK |
 997                        MAC_PHYCFG2_ACT_MASK_MASK   |
 998                        MAC_PHYCFG2_QUAL_MASK_MASK |
 999                        MAC_PHYCFG2_INBAND_ENABLE;
1000
1001         tw32(MAC_PHYCFG2, val);
1002
1003         val = tr32(MAC_PHYCFG1);
1004         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1005                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1006         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1007                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1008                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1009                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1010                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1011         }
1012         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1013                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1014         tw32(MAC_PHYCFG1, val);
1015
1016         val = tr32(MAC_EXT_RGMII_MODE);
1017         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1018                  MAC_RGMII_MODE_RX_QUALITY |
1019                  MAC_RGMII_MODE_RX_ACTIVITY |
1020                  MAC_RGMII_MODE_RX_ENG_DET |
1021                  MAC_RGMII_MODE_TX_ENABLE |
1022                  MAC_RGMII_MODE_TX_LOWPWR |
1023                  MAC_RGMII_MODE_TX_RESET);
1024         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1025                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1026                         val |= MAC_RGMII_MODE_RX_INT_B |
1027                                MAC_RGMII_MODE_RX_QUALITY |
1028                                MAC_RGMII_MODE_RX_ACTIVITY |
1029                                MAC_RGMII_MODE_RX_ENG_DET;
1030                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1031                         val |= MAC_RGMII_MODE_TX_ENABLE |
1032                                MAC_RGMII_MODE_TX_LOWPWR |
1033                                MAC_RGMII_MODE_TX_RESET;
1034         }
1035         tw32(MAC_EXT_RGMII_MODE, val);
1036 }
1037
1038 static void tg3_mdio_start(struct tg3 *tp)
1039 {
1040         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1041         tw32_f(MAC_MI_MODE, tp->mi_mode);
1042         udelay(80);
1043
1044         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1046                 tg3_mdio_config_5785(tp);
1047 }
1048
1049 static int tg3_mdio_init(struct tg3 *tp)
1050 {
1051         int i;
1052         u32 reg;
1053         struct phy_device *phydev;
1054
1055         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1056             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1057                 u32 is_serdes;
1058
1059                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1060
1061                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1062                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1063                 else
1064                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1065                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1066                 if (is_serdes)
1067                         tp->phy_addr += 7;
1068         } else
1069                 tp->phy_addr = TG3_PHY_MII_ADDR;
1070
1071         tg3_mdio_start(tp);
1072
1073         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1074             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1075                 return 0;
1076
1077         tp->mdio_bus = mdiobus_alloc();
1078         if (tp->mdio_bus == NULL)
1079                 return -ENOMEM;
1080
1081         tp->mdio_bus->name     = "tg3 mdio bus";
1082         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1083                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1084         tp->mdio_bus->priv     = tp;
1085         tp->mdio_bus->parent   = &tp->pdev->dev;
1086         tp->mdio_bus->read     = &tg3_mdio_read;
1087         tp->mdio_bus->write    = &tg3_mdio_write;
1088         tp->mdio_bus->reset    = &tg3_mdio_reset;
1089         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1090         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1091
1092         for (i = 0; i < PHY_MAX_ADDR; i++)
1093                 tp->mdio_bus->irq[i] = PHY_POLL;
1094
1095         /* The bus registration will look for all the PHYs on the mdio bus.
1096          * Unfortunately, it does not ensure the PHY is powered up before
1097          * accessing the PHY ID registers.  A chip reset is the
1098          * quickest way to bring the device back to an operational state..
1099          */
1100         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1101                 tg3_bmcr_reset(tp);
1102
1103         i = mdiobus_register(tp->mdio_bus);
1104         if (i) {
1105                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1106                 mdiobus_free(tp->mdio_bus);
1107                 return i;
1108         }
1109
1110         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1111
1112         if (!phydev || !phydev->drv) {
1113                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1114                 mdiobus_unregister(tp->mdio_bus);
1115                 mdiobus_free(tp->mdio_bus);
1116                 return -ENODEV;
1117         }
1118
1119         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1120         case PHY_ID_BCM57780:
1121                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1122                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1123                 break;
1124         case PHY_ID_BCM50610:
1125         case PHY_ID_BCM50610M:
1126                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1127                                      PHY_BRCM_RX_REFCLK_UNUSED |
1128                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1129                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1130                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1131                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1132                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1133                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1134                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1135                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1136                 /* fallthru */
1137         case PHY_ID_RTL8211C:
1138                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1139                 break;
1140         case PHY_ID_RTL8201E:
1141         case PHY_ID_BCMAC131:
1142                 phydev->interface = PHY_INTERFACE_MODE_MII;
1143                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1144                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1145                 break;
1146         }
1147
1148         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1149
1150         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1151                 tg3_mdio_config_5785(tp);
1152
1153         return 0;
1154 }
1155
1156 static void tg3_mdio_fini(struct tg3 *tp)
1157 {
1158         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1159                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1160                 mdiobus_unregister(tp->mdio_bus);
1161                 mdiobus_free(tp->mdio_bus);
1162         }
1163 }
1164
1165 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1166 {
1167         int err;
1168
1169         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1170         if (err)
1171                 goto done;
1172
1173         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1174         if (err)
1175                 goto done;
1176
1177         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1178                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1179         if (err)
1180                 goto done;
1181
1182         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1183
1184 done:
1185         return err;
1186 }
1187
1188 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1189 {
1190         int err;
1191
1192         err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1193         if (err)
1194                 goto done;
1195
1196         err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1197         if (err)
1198                 goto done;
1199
1200         err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1201                            MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1202         if (err)
1203                 goto done;
1204
1205         err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1206
1207 done:
1208         return err;
1209 }
1210
1211 /* tp->lock is held. */
1212 static inline void tg3_generate_fw_event(struct tg3 *tp)
1213 {
1214         u32 val;
1215
1216         val = tr32(GRC_RX_CPU_EVENT);
1217         val |= GRC_RX_CPU_DRIVER_EVENT;
1218         tw32_f(GRC_RX_CPU_EVENT, val);
1219
1220         tp->last_event_jiffies = jiffies;
1221 }
1222
1223 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1224
1225 /* tp->lock is held. */
1226 static void tg3_wait_for_event_ack(struct tg3 *tp)
1227 {
1228         int i;
1229         unsigned int delay_cnt;
1230         long time_remain;
1231
1232         /* If enough time has passed, no wait is necessary. */
1233         time_remain = (long)(tp->last_event_jiffies + 1 +
1234                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1235                       (long)jiffies;
1236         if (time_remain < 0)
1237                 return;
1238
1239         /* Check if we can shorten the wait time. */
1240         delay_cnt = jiffies_to_usecs(time_remain);
1241         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1242                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1243         delay_cnt = (delay_cnt >> 3) + 1;
1244
1245         for (i = 0; i < delay_cnt; i++) {
1246                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1247                         break;
1248                 udelay(8);
1249         }
1250 }
1251
1252 /* tp->lock is held. */
1253 static void tg3_ump_link_report(struct tg3 *tp)
1254 {
1255         u32 reg;
1256         u32 val;
1257
1258         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1259             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1260                 return;
1261
1262         tg3_wait_for_event_ack(tp);
1263
1264         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1265
1266         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1267
1268         val = 0;
1269         if (!tg3_readphy(tp, MII_BMCR, &reg))
1270                 val = reg << 16;
1271         if (!tg3_readphy(tp, MII_BMSR, &reg))
1272                 val |= (reg & 0xffff);
1273         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1274
1275         val = 0;
1276         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1277                 val = reg << 16;
1278         if (!tg3_readphy(tp, MII_LPA, &reg))
1279                 val |= (reg & 0xffff);
1280         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1281
1282         val = 0;
1283         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1284                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1285                         val = reg << 16;
1286                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1287                         val |= (reg & 0xffff);
1288         }
1289         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1290
1291         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1292                 val = reg << 16;
1293         else
1294                 val = 0;
1295         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1296
1297         tg3_generate_fw_event(tp);
1298 }
1299
1300 static void tg3_link_report(struct tg3 *tp)
1301 {
1302         if (!netif_carrier_ok(tp->dev)) {
1303                 netif_info(tp, link, tp->dev, "Link is down\n");
1304                 tg3_ump_link_report(tp);
1305         } else if (netif_msg_link(tp)) {
1306                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1307                             (tp->link_config.active_speed == SPEED_1000 ?
1308                              1000 :
1309                              (tp->link_config.active_speed == SPEED_100 ?
1310                               100 : 10)),
1311                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1312                              "full" : "half"));
1313
1314                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1315                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1316                             "on" : "off",
1317                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1318                             "on" : "off");
1319                 tg3_ump_link_report(tp);
1320         }
1321 }
1322
1323 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1324 {
1325         u16 miireg;
1326
1327         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1328                 miireg = ADVERTISE_PAUSE_CAP;
1329         else if (flow_ctrl & FLOW_CTRL_TX)
1330                 miireg = ADVERTISE_PAUSE_ASYM;
1331         else if (flow_ctrl & FLOW_CTRL_RX)
1332                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1333         else
1334                 miireg = 0;
1335
1336         return miireg;
1337 }
1338
1339 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1340 {
1341         u16 miireg;
1342
1343         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1344                 miireg = ADVERTISE_1000XPAUSE;
1345         else if (flow_ctrl & FLOW_CTRL_TX)
1346                 miireg = ADVERTISE_1000XPSE_ASYM;
1347         else if (flow_ctrl & FLOW_CTRL_RX)
1348                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1349         else
1350                 miireg = 0;
1351
1352         return miireg;
1353 }
1354
1355 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1356 {
1357         u8 cap = 0;
1358
1359         if (lcladv & ADVERTISE_1000XPAUSE) {
1360                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1361                         if (rmtadv & LPA_1000XPAUSE)
1362                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1363                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1364                                 cap = FLOW_CTRL_RX;
1365                 } else {
1366                         if (rmtadv & LPA_1000XPAUSE)
1367                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1368                 }
1369         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1370                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1371                         cap = FLOW_CTRL_TX;
1372         }
1373
1374         return cap;
1375 }
1376
1377 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1378 {
1379         u8 autoneg;
1380         u8 flowctrl = 0;
1381         u32 old_rx_mode = tp->rx_mode;
1382         u32 old_tx_mode = tp->tx_mode;
1383
1384         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1385                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1386         else
1387                 autoneg = tp->link_config.autoneg;
1388
1389         if (autoneg == AUTONEG_ENABLE &&
1390             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1391                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1392                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1393                 else
1394                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1395         } else
1396                 flowctrl = tp->link_config.flowctrl;
1397
1398         tp->link_config.active_flowctrl = flowctrl;
1399
1400         if (flowctrl & FLOW_CTRL_RX)
1401                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1402         else
1403                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1404
1405         if (old_rx_mode != tp->rx_mode)
1406                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1407
1408         if (flowctrl & FLOW_CTRL_TX)
1409                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1410         else
1411                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1412
1413         if (old_tx_mode != tp->tx_mode)
1414                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1415 }
1416
1417 static void tg3_adjust_link(struct net_device *dev)
1418 {
1419         u8 oldflowctrl, linkmesg = 0;
1420         u32 mac_mode, lcl_adv, rmt_adv;
1421         struct tg3 *tp = netdev_priv(dev);
1422         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1423
1424         spin_lock_bh(&tp->lock);
1425
1426         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1427                                     MAC_MODE_HALF_DUPLEX);
1428
1429         oldflowctrl = tp->link_config.active_flowctrl;
1430
1431         if (phydev->link) {
1432                 lcl_adv = 0;
1433                 rmt_adv = 0;
1434
1435                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1436                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1437                 else if (phydev->speed == SPEED_1000 ||
1438                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1439                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1440                 else
1441                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1442
1443                 if (phydev->duplex == DUPLEX_HALF)
1444                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1445                 else {
1446                         lcl_adv = tg3_advert_flowctrl_1000T(
1447                                   tp->link_config.flowctrl);
1448
1449                         if (phydev->pause)
1450                                 rmt_adv = LPA_PAUSE_CAP;
1451                         if (phydev->asym_pause)
1452                                 rmt_adv |= LPA_PAUSE_ASYM;
1453                 }
1454
1455                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1456         } else
1457                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1458
1459         if (mac_mode != tp->mac_mode) {
1460                 tp->mac_mode = mac_mode;
1461                 tw32_f(MAC_MODE, tp->mac_mode);
1462                 udelay(40);
1463         }
1464
1465         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1466                 if (phydev->speed == SPEED_10)
1467                         tw32(MAC_MI_STAT,
1468                              MAC_MI_STAT_10MBPS_MODE |
1469                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1470                 else
1471                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1472         }
1473
1474         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1475                 tw32(MAC_TX_LENGTHS,
1476                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1477                       (6 << TX_LENGTHS_IPG_SHIFT) |
1478                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1479         else
1480                 tw32(MAC_TX_LENGTHS,
1481                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1482                       (6 << TX_LENGTHS_IPG_SHIFT) |
1483                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1484
1485         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1486             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1487             phydev->speed != tp->link_config.active_speed ||
1488             phydev->duplex != tp->link_config.active_duplex ||
1489             oldflowctrl != tp->link_config.active_flowctrl)
1490                 linkmesg = 1;
1491
1492         tp->link_config.active_speed = phydev->speed;
1493         tp->link_config.active_duplex = phydev->duplex;
1494
1495         spin_unlock_bh(&tp->lock);
1496
1497         if (linkmesg)
1498                 tg3_link_report(tp);
1499 }
1500
1501 static int tg3_phy_init(struct tg3 *tp)
1502 {
1503         struct phy_device *phydev;
1504
1505         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1506                 return 0;
1507
1508         /* Bring the PHY back to a known state. */
1509         tg3_bmcr_reset(tp);
1510
1511         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1512
1513         /* Attach the MAC to the PHY. */
1514         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1515                              phydev->dev_flags, phydev->interface);
1516         if (IS_ERR(phydev)) {
1517                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1518                 return PTR_ERR(phydev);
1519         }
1520
1521         /* Mask with MAC supported features. */
1522         switch (phydev->interface) {
1523         case PHY_INTERFACE_MODE_GMII:
1524         case PHY_INTERFACE_MODE_RGMII:
1525                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1526                         phydev->supported &= (PHY_GBIT_FEATURES |
1527                                               SUPPORTED_Pause |
1528                                               SUPPORTED_Asym_Pause);
1529                         break;
1530                 }
1531                 /* fallthru */
1532         case PHY_INTERFACE_MODE_MII:
1533                 phydev->supported &= (PHY_BASIC_FEATURES |
1534                                       SUPPORTED_Pause |
1535                                       SUPPORTED_Asym_Pause);
1536                 break;
1537         default:
1538                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1539                 return -EINVAL;
1540         }
1541
1542         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1543
1544         phydev->advertising = phydev->supported;
1545
1546         return 0;
1547 }
1548
1549 static void tg3_phy_start(struct tg3 *tp)
1550 {
1551         struct phy_device *phydev;
1552
1553         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1554                 return;
1555
1556         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1557
1558         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1559                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1560                 phydev->speed = tp->link_config.orig_speed;
1561                 phydev->duplex = tp->link_config.orig_duplex;
1562                 phydev->autoneg = tp->link_config.orig_autoneg;
1563                 phydev->advertising = tp->link_config.orig_advertising;
1564         }
1565
1566         phy_start(phydev);
1567
1568         phy_start_aneg(phydev);
1569 }
1570
1571 static void tg3_phy_stop(struct tg3 *tp)
1572 {
1573         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1574                 return;
1575
1576         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1577 }
1578
1579 static void tg3_phy_fini(struct tg3 *tp)
1580 {
1581         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1582                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1583                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1584         }
1585 }
1586
1587 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1588 {
1589         int err;
1590
1591         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1592         if (!err)
1593                 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1594
1595         return err;
1596 }
1597
1598 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1599 {
1600         int err;
1601
1602         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1603         if (!err)
1604                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1605
1606         return err;
1607 }
1608
1609 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1610 {
1611         u32 phytest;
1612
1613         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1614                 u32 phy;
1615
1616                 tg3_writephy(tp, MII_TG3_FET_TEST,
1617                              phytest | MII_TG3_FET_SHADOW_EN);
1618                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1619                         if (enable)
1620                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1621                         else
1622                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1623                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1624                 }
1625                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1626         }
1627 }
1628
1629 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1630 {
1631         u32 reg;
1632
1633         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1634             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1635               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1636              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1637                 return;
1638
1639         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1640                 tg3_phy_fet_toggle_apd(tp, enable);
1641                 return;
1642         }
1643
1644         reg = MII_TG3_MISC_SHDW_WREN |
1645               MII_TG3_MISC_SHDW_SCR5_SEL |
1646               MII_TG3_MISC_SHDW_SCR5_LPED |
1647               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1648               MII_TG3_MISC_SHDW_SCR5_SDTL |
1649               MII_TG3_MISC_SHDW_SCR5_C125OE;
1650         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1651                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1652
1653         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1654
1655
1656         reg = MII_TG3_MISC_SHDW_WREN |
1657               MII_TG3_MISC_SHDW_APD_SEL |
1658               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1659         if (enable)
1660                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1661
1662         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1663 }
1664
1665 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1666 {
1667         u32 phy;
1668
1669         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1670             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1671                 return;
1672
1673         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1674                 u32 ephy;
1675
1676                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1677                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1678
1679                         tg3_writephy(tp, MII_TG3_FET_TEST,
1680                                      ephy | MII_TG3_FET_SHADOW_EN);
1681                         if (!tg3_readphy(tp, reg, &phy)) {
1682                                 if (enable)
1683                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1684                                 else
1685                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1686                                 tg3_writephy(tp, reg, phy);
1687                         }
1688                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1689                 }
1690         } else {
1691                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1692                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1693                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1694                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1695                         if (enable)
1696                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1697                         else
1698                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1699                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1700                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1701                 }
1702         }
1703 }
1704
1705 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1706 {
1707         u32 val;
1708
1709         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1710                 return;
1711
1712         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1713             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1714                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1715                              (val | (1 << 15) | (1 << 4)));
1716 }
1717
1718 static void tg3_phy_apply_otp(struct tg3 *tp)
1719 {
1720         u32 otp, phy;
1721
1722         if (!tp->phy_otp)
1723                 return;
1724
1725         otp = tp->phy_otp;
1726
1727         /* Enable SM_DSP clock and tx 6dB coding. */
1728         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1729               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1730               MII_TG3_AUXCTL_ACTL_TX_6DB;
1731         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1732
1733         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1734         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1735         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1736
1737         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1738               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1739         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1740
1741         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1742         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1743         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1744
1745         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1746         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1747
1748         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1749         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1750
1751         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1752               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1753         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1754
1755         /* Turn off SM_DSP clock. */
1756         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1757               MII_TG3_AUXCTL_ACTL_TX_6DB;
1758         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1759 }
1760
1761 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
1762 {
1763         u32 val;
1764
1765         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
1766                 return;
1767
1768         tp->setlpicnt = 0;
1769
1770         if (tp->link_config.autoneg == AUTONEG_ENABLE &&
1771             current_link_up == 1 &&
1772             (tp->link_config.active_speed == SPEED_1000 ||
1773              (tp->link_config.active_speed == SPEED_100 &&
1774               tp->link_config.active_duplex == DUPLEX_FULL))) {
1775                 u32 eeectl;
1776
1777                 if (tp->link_config.active_speed == SPEED_1000)
1778                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
1779                 else
1780                         eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
1781
1782                 tw32(TG3_CPMU_EEE_CTRL, eeectl);
1783
1784                 tg3_phy_cl45_read(tp, 0x7, TG3_CL45_D7_EEERES_STAT, &val);
1785
1786                 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
1787                     val == TG3_CL45_D7_EEERES_STAT_LP_100TX)
1788                         tp->setlpicnt = 2;
1789         }
1790
1791         if (!tp->setlpicnt) {
1792                 val = tr32(TG3_CPMU_EEE_MODE);
1793                 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
1794         }
1795 }
1796
1797 static int tg3_wait_macro_done(struct tg3 *tp)
1798 {
1799         int limit = 100;
1800
1801         while (limit--) {
1802                 u32 tmp32;
1803
1804                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1805                         if ((tmp32 & 0x1000) == 0)
1806                                 break;
1807                 }
1808         }
1809         if (limit < 0)
1810                 return -EBUSY;
1811
1812         return 0;
1813 }
1814
1815 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1816 {
1817         static const u32 test_pat[4][6] = {
1818         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1819         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1820         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1821         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1822         };
1823         int chan;
1824
1825         for (chan = 0; chan < 4; chan++) {
1826                 int i;
1827
1828                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1829                              (chan * 0x2000) | 0x0200);
1830                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1831
1832                 for (i = 0; i < 6; i++)
1833                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1834                                      test_pat[chan][i]);
1835
1836                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1837                 if (tg3_wait_macro_done(tp)) {
1838                         *resetp = 1;
1839                         return -EBUSY;
1840                 }
1841
1842                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1843                              (chan * 0x2000) | 0x0200);
1844                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1845                 if (tg3_wait_macro_done(tp)) {
1846                         *resetp = 1;
1847                         return -EBUSY;
1848                 }
1849
1850                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1851                 if (tg3_wait_macro_done(tp)) {
1852                         *resetp = 1;
1853                         return -EBUSY;
1854                 }
1855
1856                 for (i = 0; i < 6; i += 2) {
1857                         u32 low, high;
1858
1859                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1860                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1861                             tg3_wait_macro_done(tp)) {
1862                                 *resetp = 1;
1863                                 return -EBUSY;
1864                         }
1865                         low &= 0x7fff;
1866                         high &= 0x000f;
1867                         if (low != test_pat[chan][i] ||
1868                             high != test_pat[chan][i+1]) {
1869                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1870                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1871                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1872
1873                                 return -EBUSY;
1874                         }
1875                 }
1876         }
1877
1878         return 0;
1879 }
1880
1881 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1882 {
1883         int chan;
1884
1885         for (chan = 0; chan < 4; chan++) {
1886                 int i;
1887
1888                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1889                              (chan * 0x2000) | 0x0200);
1890                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1891                 for (i = 0; i < 6; i++)
1892                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1893                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1894                 if (tg3_wait_macro_done(tp))
1895                         return -EBUSY;
1896         }
1897
1898         return 0;
1899 }
1900
1901 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1902 {
1903         u32 reg32, phy9_orig;
1904         int retries, do_phy_reset, err;
1905
1906         retries = 10;
1907         do_phy_reset = 1;
1908         do {
1909                 if (do_phy_reset) {
1910                         err = tg3_bmcr_reset(tp);
1911                         if (err)
1912                                 return err;
1913                         do_phy_reset = 0;
1914                 }
1915
1916                 /* Disable transmitter and interrupt.  */
1917                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1918                         continue;
1919
1920                 reg32 |= 0x3000;
1921                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1922
1923                 /* Set full-duplex, 1000 mbps.  */
1924                 tg3_writephy(tp, MII_BMCR,
1925                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1926
1927                 /* Set to master mode.  */
1928                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1929                         continue;
1930
1931                 tg3_writephy(tp, MII_TG3_CTRL,
1932                              (MII_TG3_CTRL_AS_MASTER |
1933                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1934
1935                 /* Enable SM_DSP_CLOCK and 6dB.  */
1936                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1937
1938                 /* Block the PHY control access.  */
1939                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1940
1941                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1942                 if (!err)
1943                         break;
1944         } while (--retries);
1945
1946         err = tg3_phy_reset_chanpat(tp);
1947         if (err)
1948                 return err;
1949
1950         tg3_phydsp_write(tp, 0x8005, 0x0000);
1951
1952         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1953         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1954
1955         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1956             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1957                 /* Set Extended packet length bit for jumbo frames */
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1959         } else {
1960                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1961         }
1962
1963         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1964
1965         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1966                 reg32 &= ~0x3000;
1967                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1968         } else if (!err)
1969                 err = -EBUSY;
1970
1971         return err;
1972 }
1973
1974 /* This will reset the tigon3 PHY if there is no valid
1975  * link unless the FORCE argument is non-zero.
1976  */
1977 static int tg3_phy_reset(struct tg3 *tp)
1978 {
1979         u32 val, cpmuctrl;
1980         int err;
1981
1982         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1983                 val = tr32(GRC_MISC_CFG);
1984                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1985                 udelay(40);
1986         }
1987         err  = tg3_readphy(tp, MII_BMSR, &val);
1988         err |= tg3_readphy(tp, MII_BMSR, &val);
1989         if (err != 0)
1990                 return -EBUSY;
1991
1992         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1993                 netif_carrier_off(tp->dev);
1994                 tg3_link_report(tp);
1995         }
1996
1997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1999             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2000                 err = tg3_phy_reset_5703_4_5(tp);
2001                 if (err)
2002                         return err;
2003                 goto out;
2004         }
2005
2006         cpmuctrl = 0;
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
2008             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
2009                 cpmuctrl = tr32(TG3_CPMU_CTRL);
2010                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2011                         tw32(TG3_CPMU_CTRL,
2012                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2013         }
2014
2015         err = tg3_bmcr_reset(tp);
2016         if (err)
2017                 return err;
2018
2019         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2020                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2021                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2022
2023                 tw32(TG3_CPMU_CTRL, cpmuctrl);
2024         }
2025
2026         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2027             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2028                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2029                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2030                     CPMU_LSPD_1000MB_MACCLK_12_5) {
2031                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2032                         udelay(40);
2033                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2034                 }
2035         }
2036
2037         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2038              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
2039             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2040                 return 0;
2041
2042         tg3_phy_apply_otp(tp);
2043
2044         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2045                 tg3_phy_toggle_apd(tp, true);
2046         else
2047                 tg3_phy_toggle_apd(tp, false);
2048
2049 out:
2050         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
2051                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2052                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2053                 tg3_phydsp_write(tp, 0x000a, 0x0323);
2054                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2055         }
2056         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2057                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2058                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2059         }
2060         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2061                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2062                 tg3_phydsp_write(tp, 0x000a, 0x310b);
2063                 tg3_phydsp_write(tp, 0x201f, 0x9506);
2064                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2065                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2066         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2067                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2068                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2069                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2070                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2071                         tg3_writephy(tp, MII_TG3_TEST1,
2072                                      MII_TG3_TEST1_TRIM_EN | 0x4);
2073                 } else
2074                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2075                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
2076         }
2077         /* Set Extended packet length bit (bit 14) on all chips that */
2078         /* support jumbo frames */
2079         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2080                 /* Cannot do read-modify-write on 5401 */
2081                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2082         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2083                 /* Set bit 14 with read-modify-write to preserve other bits */
2084                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
2085                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
2086                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
2087         }
2088
2089         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2090          * jumbo frames transmission.
2091          */
2092         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2093                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2094                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
2095                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2096         }
2097
2098         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2099                 /* adjust output voltage */
2100                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2101         }
2102
2103         tg3_phy_toggle_automdix(tp, 1);
2104         tg3_phy_set_wirespeed(tp);
2105         return 0;
2106 }
2107
2108 static void tg3_frob_aux_power(struct tg3 *tp)
2109 {
2110         struct tg3 *tp_peer = tp;
2111
2112         /* The GPIOs do something completely different on 57765. */
2113         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2114             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2115             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2116                 return;
2117
2118         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2119             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2120             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2121                 struct net_device *dev_peer;
2122
2123                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2124                 /* remove_one() may have been run on the peer. */
2125                 if (!dev_peer)
2126                         tp_peer = tp;
2127                 else
2128                         tp_peer = netdev_priv(dev_peer);
2129         }
2130
2131         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2132             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2133             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2134             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2135                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2136                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2137                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2138                                     (GRC_LCLCTRL_GPIO_OE0 |
2139                                      GRC_LCLCTRL_GPIO_OE1 |
2140                                      GRC_LCLCTRL_GPIO_OE2 |
2141                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2142                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2143                                     100);
2144                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2145                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2146                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2147                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2148                                              GRC_LCLCTRL_GPIO_OE1 |
2149                                              GRC_LCLCTRL_GPIO_OE2 |
2150                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2151                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2152                                              tp->grc_local_ctrl;
2153                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2154
2155                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2156                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2157
2158                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2159                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2160                 } else {
2161                         u32 no_gpio2;
2162                         u32 grc_local_ctrl = 0;
2163
2164                         if (tp_peer != tp &&
2165                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2166                                 return;
2167
2168                         /* Workaround to prevent overdrawing Amps. */
2169                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2170                             ASIC_REV_5714) {
2171                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2172                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2173                                             grc_local_ctrl, 100);
2174                         }
2175
2176                         /* On 5753 and variants, GPIO2 cannot be used. */
2177                         no_gpio2 = tp->nic_sram_data_cfg &
2178                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2179
2180                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2181                                          GRC_LCLCTRL_GPIO_OE1 |
2182                                          GRC_LCLCTRL_GPIO_OE2 |
2183                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2184                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2185                         if (no_gpio2) {
2186                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2187                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2188                         }
2189                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2190                                                     grc_local_ctrl, 100);
2191
2192                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2193
2194                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2195                                                     grc_local_ctrl, 100);
2196
2197                         if (!no_gpio2) {
2198                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2199                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2200                                             grc_local_ctrl, 100);
2201                         }
2202                 }
2203         } else {
2204                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2205                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2206                         if (tp_peer != tp &&
2207                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2208                                 return;
2209
2210                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2211                                     (GRC_LCLCTRL_GPIO_OE1 |
2212                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2213
2214                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2215                                     GRC_LCLCTRL_GPIO_OE1, 100);
2216
2217                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2218                                     (GRC_LCLCTRL_GPIO_OE1 |
2219                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2220                 }
2221         }
2222 }
2223
2224 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2225 {
2226         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2227                 return 1;
2228         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2229                 if (speed != SPEED_10)
2230                         return 1;
2231         } else if (speed == SPEED_10)
2232                 return 1;
2233
2234         return 0;
2235 }
2236
2237 static int tg3_setup_phy(struct tg3 *, int);
2238
2239 #define RESET_KIND_SHUTDOWN     0
2240 #define RESET_KIND_INIT         1
2241 #define RESET_KIND_SUSPEND      2
2242
2243 static void tg3_write_sig_post_reset(struct tg3 *, int);
2244 static int tg3_halt_cpu(struct tg3 *, u32);
2245
2246 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2247 {
2248         u32 val;
2249
2250         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2251                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2252                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2253                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2254
2255                         sg_dig_ctrl |=
2256                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2257                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2258                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2259                 }
2260                 return;
2261         }
2262
2263         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2264                 tg3_bmcr_reset(tp);
2265                 val = tr32(GRC_MISC_CFG);
2266                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2267                 udelay(40);
2268                 return;
2269         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2270                 u32 phytest;
2271                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2272                         u32 phy;
2273
2274                         tg3_writephy(tp, MII_ADVERTISE, 0);
2275                         tg3_writephy(tp, MII_BMCR,
2276                                      BMCR_ANENABLE | BMCR_ANRESTART);
2277
2278                         tg3_writephy(tp, MII_TG3_FET_TEST,
2279                                      phytest | MII_TG3_FET_SHADOW_EN);
2280                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2281                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2282                                 tg3_writephy(tp,
2283                                              MII_TG3_FET_SHDW_AUXMODE4,
2284                                              phy);
2285                         }
2286                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2287                 }
2288                 return;
2289         } else if (do_low_power) {
2290                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2291                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2292
2293                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2294                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2295                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2296                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2297                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2298         }
2299
2300         /* The PHY should not be powered down on some chips because
2301          * of bugs.
2302          */
2303         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2304             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2305             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2306              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2307                 return;
2308
2309         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2310             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2311                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2312                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2313                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2314                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2315         }
2316
2317         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2318 }
2319
2320 /* tp->lock is held. */
2321 static int tg3_nvram_lock(struct tg3 *tp)
2322 {
2323         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2324                 int i;
2325
2326                 if (tp->nvram_lock_cnt == 0) {
2327                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2328                         for (i = 0; i < 8000; i++) {
2329                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2330                                         break;
2331                                 udelay(20);
2332                         }
2333                         if (i == 8000) {
2334                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2335                                 return -ENODEV;
2336                         }
2337                 }
2338                 tp->nvram_lock_cnt++;
2339         }
2340         return 0;
2341 }
2342
2343 /* tp->lock is held. */
2344 static void tg3_nvram_unlock(struct tg3 *tp)
2345 {
2346         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2347                 if (tp->nvram_lock_cnt > 0)
2348                         tp->nvram_lock_cnt--;
2349                 if (tp->nvram_lock_cnt == 0)
2350                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2351         }
2352 }
2353
2354 /* tp->lock is held. */
2355 static void tg3_enable_nvram_access(struct tg3 *tp)
2356 {
2357         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2358             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2359                 u32 nvaccess = tr32(NVRAM_ACCESS);
2360
2361                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2362         }
2363 }
2364
2365 /* tp->lock is held. */
2366 static void tg3_disable_nvram_access(struct tg3 *tp)
2367 {
2368         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2369             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2370                 u32 nvaccess = tr32(NVRAM_ACCESS);
2371
2372                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2373         }
2374 }
2375
2376 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2377                                         u32 offset, u32 *val)
2378 {
2379         u32 tmp;
2380         int i;
2381
2382         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2383                 return -EINVAL;
2384
2385         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2386                                         EEPROM_ADDR_DEVID_MASK |
2387                                         EEPROM_ADDR_READ);
2388         tw32(GRC_EEPROM_ADDR,
2389              tmp |
2390              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2391              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2392               EEPROM_ADDR_ADDR_MASK) |
2393              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2394
2395         for (i = 0; i < 1000; i++) {
2396                 tmp = tr32(GRC_EEPROM_ADDR);
2397
2398                 if (tmp & EEPROM_ADDR_COMPLETE)
2399                         break;
2400                 msleep(1);
2401         }
2402         if (!(tmp & EEPROM_ADDR_COMPLETE))
2403                 return -EBUSY;
2404
2405         tmp = tr32(GRC_EEPROM_DATA);
2406
2407         /*
2408          * The data will always be opposite the native endian
2409          * format.  Perform a blind byteswap to compensate.
2410          */
2411         *val = swab32(tmp);
2412
2413         return 0;
2414 }
2415
2416 #define NVRAM_CMD_TIMEOUT 10000
2417
2418 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2419 {
2420         int i;
2421
2422         tw32(NVRAM_CMD, nvram_cmd);
2423         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2424                 udelay(10);
2425                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2426                         udelay(10);
2427                         break;
2428                 }
2429         }
2430
2431         if (i == NVRAM_CMD_TIMEOUT)
2432                 return -EBUSY;
2433
2434         return 0;
2435 }
2436
2437 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2438 {
2439         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2440             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2441             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2442            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2443             (tp->nvram_jedecnum == JEDEC_ATMEL))
2444
2445                 addr = ((addr / tp->nvram_pagesize) <<
2446                         ATMEL_AT45DB0X1B_PAGE_POS) +
2447                        (addr % tp->nvram_pagesize);
2448
2449         return addr;
2450 }
2451
2452 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2453 {
2454         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2455             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2456             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2457            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2458             (tp->nvram_jedecnum == JEDEC_ATMEL))
2459
2460                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2461                         tp->nvram_pagesize) +
2462                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2463
2464         return addr;
2465 }
2466
2467 /* NOTE: Data read in from NVRAM is byteswapped according to
2468  * the byteswapping settings for all other register accesses.
2469  * tg3 devices are BE devices, so on a BE machine, the data
2470  * returned will be exactly as it is seen in NVRAM.  On a LE
2471  * machine, the 32-bit value will be byteswapped.
2472  */
2473 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2474 {
2475         int ret;
2476
2477         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2478                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2479
2480         offset = tg3_nvram_phys_addr(tp, offset);
2481
2482         if (offset > NVRAM_ADDR_MSK)
2483                 return -EINVAL;
2484
2485         ret = tg3_nvram_lock(tp);
2486         if (ret)
2487                 return ret;
2488
2489         tg3_enable_nvram_access(tp);
2490
2491         tw32(NVRAM_ADDR, offset);
2492         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2493                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2494
2495         if (ret == 0)
2496                 *val = tr32(NVRAM_RDDATA);
2497
2498         tg3_disable_nvram_access(tp);
2499
2500         tg3_nvram_unlock(tp);
2501
2502         return ret;
2503 }
2504
2505 /* Ensures NVRAM data is in bytestream format. */
2506 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2507 {
2508         u32 v;
2509         int res = tg3_nvram_read(tp, offset, &v);
2510         if (!res)
2511                 *val = cpu_to_be32(v);
2512         return res;
2513 }
2514
2515 /* tp->lock is held. */
2516 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2517 {
2518         u32 addr_high, addr_low;
2519         int i;
2520
2521         addr_high = ((tp->dev->dev_addr[0] << 8) |
2522                      tp->dev->dev_addr[1]);
2523         addr_low = ((tp->dev->dev_addr[2] << 24) |
2524                     (tp->dev->dev_addr[3] << 16) |
2525                     (tp->dev->dev_addr[4] <<  8) |
2526                     (tp->dev->dev_addr[5] <<  0));
2527         for (i = 0; i < 4; i++) {
2528                 if (i == 1 && skip_mac_1)
2529                         continue;
2530                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2531                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2532         }
2533
2534         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2535             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2536                 for (i = 0; i < 12; i++) {
2537                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2538                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2539                 }
2540         }
2541
2542         addr_high = (tp->dev->dev_addr[0] +
2543                      tp->dev->dev_addr[1] +
2544                      tp->dev->dev_addr[2] +
2545                      tp->dev->dev_addr[3] +
2546                      tp->dev->dev_addr[4] +
2547                      tp->dev->dev_addr[5]) &
2548                 TX_BACKOFF_SEED_MASK;
2549         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2550 }
2551
2552 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2553 {
2554         u32 misc_host_ctrl;
2555         bool device_should_wake, do_low_power;
2556
2557         /* Make sure register accesses (indirect or otherwise)
2558          * will function correctly.
2559          */
2560         pci_write_config_dword(tp->pdev,
2561                                TG3PCI_MISC_HOST_CTRL,
2562                                tp->misc_host_ctrl);
2563
2564         switch (state) {
2565         case PCI_D0:
2566                 pci_enable_wake(tp->pdev, state, false);
2567                 pci_set_power_state(tp->pdev, PCI_D0);
2568
2569                 /* Switch out of Vaux if it is a NIC */
2570                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2571                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2572
2573                 return 0;
2574
2575         case PCI_D1:
2576         case PCI_D2:
2577         case PCI_D3hot:
2578                 break;
2579
2580         default:
2581                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2582                            state);
2583                 return -EINVAL;
2584         }
2585
2586         /* Restore the CLKREQ setting. */
2587         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2588                 u16 lnkctl;
2589
2590                 pci_read_config_word(tp->pdev,
2591                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2592                                      &lnkctl);
2593                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2594                 pci_write_config_word(tp->pdev,
2595                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2596                                       lnkctl);
2597         }
2598
2599         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2600         tw32(TG3PCI_MISC_HOST_CTRL,
2601              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2602
2603         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2604                              device_may_wakeup(&tp->pdev->dev) &&
2605                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2606
2607         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2608                 do_low_power = false;
2609                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2610                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2611                         struct phy_device *phydev;
2612                         u32 phyid, advertising;
2613
2614                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2615
2616                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2617
2618                         tp->link_config.orig_speed = phydev->speed;
2619                         tp->link_config.orig_duplex = phydev->duplex;
2620                         tp->link_config.orig_autoneg = phydev->autoneg;
2621                         tp->link_config.orig_advertising = phydev->advertising;
2622
2623                         advertising = ADVERTISED_TP |
2624                                       ADVERTISED_Pause |
2625                                       ADVERTISED_Autoneg |
2626                                       ADVERTISED_10baseT_Half;
2627
2628                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2629                             device_should_wake) {
2630                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2631                                         advertising |=
2632                                                 ADVERTISED_100baseT_Half |
2633                                                 ADVERTISED_100baseT_Full |
2634                                                 ADVERTISED_10baseT_Full;
2635                                 else
2636                                         advertising |= ADVERTISED_10baseT_Full;
2637                         }
2638
2639                         phydev->advertising = advertising;
2640
2641                         phy_start_aneg(phydev);
2642
2643                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2644                         if (phyid != PHY_ID_BCMAC131) {
2645                                 phyid &= PHY_BCM_OUI_MASK;
2646                                 if (phyid == PHY_BCM_OUI_1 ||
2647                                     phyid == PHY_BCM_OUI_2 ||
2648                                     phyid == PHY_BCM_OUI_3)
2649                                         do_low_power = true;
2650                         }
2651                 }
2652         } else {
2653                 do_low_power = true;
2654
2655                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2656                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2657                         tp->link_config.orig_speed = tp->link_config.speed;
2658                         tp->link_config.orig_duplex = tp->link_config.duplex;
2659                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2660                 }
2661
2662                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2663                         tp->link_config.speed = SPEED_10;
2664                         tp->link_config.duplex = DUPLEX_HALF;
2665                         tp->link_config.autoneg = AUTONEG_ENABLE;
2666                         tg3_setup_phy(tp, 0);
2667                 }
2668         }
2669
2670         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2671                 u32 val;
2672
2673                 val = tr32(GRC_VCPU_EXT_CTRL);
2674                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2675         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2676                 int i;
2677                 u32 val;
2678
2679                 for (i = 0; i < 200; i++) {
2680                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2681                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2682                                 break;
2683                         msleep(1);
2684                 }
2685         }
2686         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2687                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2688                                                      WOL_DRV_STATE_SHUTDOWN |
2689                                                      WOL_DRV_WOL |
2690                                                      WOL_SET_MAGIC_PKT);
2691
2692         if (device_should_wake) {
2693                 u32 mac_mode;
2694
2695                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2696                         if (do_low_power) {
2697                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2698                                 udelay(40);
2699                         }
2700
2701                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2702                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2703                         else
2704                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2705
2706                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2707                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2708                             ASIC_REV_5700) {
2709                                 u32 speed = (tp->tg3_flags &
2710                                              TG3_FLAG_WOL_SPEED_100MB) ?
2711                                              SPEED_100 : SPEED_10;
2712                                 if (tg3_5700_link_polarity(tp, speed))
2713                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2714                                 else
2715                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2716                         }
2717                 } else {
2718                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2719                 }
2720
2721                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2722                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2723
2724                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2725                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2726                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2727                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2728                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2729                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2730
2731                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2732                         mac_mode |= tp->mac_mode &
2733                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2734                         if (mac_mode & MAC_MODE_APE_TX_EN)
2735                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2736                 }
2737
2738                 tw32_f(MAC_MODE, mac_mode);
2739                 udelay(100);
2740
2741                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2742                 udelay(10);
2743         }
2744
2745         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2746             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2747              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2748                 u32 base_val;
2749
2750                 base_val = tp->pci_clock_ctrl;
2751                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2752                              CLOCK_CTRL_TXCLK_DISABLE);
2753
2754                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2755                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2756         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2757                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2758                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2759                 /* do nothing */
2760         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2761                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2762                 u32 newbits1, newbits2;
2763
2764                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2765                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2766                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2767                                     CLOCK_CTRL_TXCLK_DISABLE |
2768                                     CLOCK_CTRL_ALTCLK);
2769                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2770                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2771                         newbits1 = CLOCK_CTRL_625_CORE;
2772                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2773                 } else {
2774                         newbits1 = CLOCK_CTRL_ALTCLK;
2775                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2776                 }
2777
2778                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2779                             40);
2780
2781                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2782                             40);
2783
2784                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2785                         u32 newbits3;
2786
2787                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2788                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2789                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2790                                             CLOCK_CTRL_TXCLK_DISABLE |
2791                                             CLOCK_CTRL_44MHZ_CORE);
2792                         } else {
2793                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2794                         }
2795
2796                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2797                                     tp->pci_clock_ctrl | newbits3, 40);
2798                 }
2799         }
2800
2801         if (!(device_should_wake) &&
2802             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2803                 tg3_power_down_phy(tp, do_low_power);
2804
2805         tg3_frob_aux_power(tp);
2806
2807         /* Workaround for unstable PLL clock */
2808         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2809             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2810                 u32 val = tr32(0x7d00);
2811
2812                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2813                 tw32(0x7d00, val);
2814                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2815                         int err;
2816
2817                         err = tg3_nvram_lock(tp);
2818                         tg3_halt_cpu(tp, RX_CPU_BASE);
2819                         if (!err)
2820                                 tg3_nvram_unlock(tp);
2821                 }
2822         }
2823
2824         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2825
2826         if (device_should_wake)
2827                 pci_enable_wake(tp->pdev, state, true);
2828
2829         /* Finally, set the new power state. */
2830         pci_set_power_state(tp->pdev, state);
2831
2832         return 0;
2833 }
2834
2835 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2836 {
2837         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2838         case MII_TG3_AUX_STAT_10HALF:
2839                 *speed = SPEED_10;
2840                 *duplex = DUPLEX_HALF;
2841                 break;
2842
2843         case MII_TG3_AUX_STAT_10FULL:
2844                 *speed = SPEED_10;
2845                 *duplex = DUPLEX_FULL;
2846                 break;
2847
2848         case MII_TG3_AUX_STAT_100HALF:
2849                 *speed = SPEED_100;
2850                 *duplex = DUPLEX_HALF;
2851                 break;
2852
2853         case MII_TG3_AUX_STAT_100FULL:
2854                 *speed = SPEED_100;
2855                 *duplex = DUPLEX_FULL;
2856                 break;
2857
2858         case MII_TG3_AUX_STAT_1000HALF:
2859                 *speed = SPEED_1000;
2860                 *duplex = DUPLEX_HALF;
2861                 break;
2862
2863         case MII_TG3_AUX_STAT_1000FULL:
2864                 *speed = SPEED_1000;
2865                 *duplex = DUPLEX_FULL;
2866                 break;
2867
2868         default:
2869                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2870                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2871                                  SPEED_10;
2872                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2873                                   DUPLEX_HALF;
2874                         break;
2875                 }
2876                 *speed = SPEED_INVALID;
2877                 *duplex = DUPLEX_INVALID;
2878                 break;
2879         }
2880 }
2881
2882 static void tg3_phy_copper_begin(struct tg3 *tp)
2883 {
2884         u32 new_adv;
2885         int i;
2886
2887         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2888                 /* Entering low power mode.  Disable gigabit and
2889                  * 100baseT advertisements.
2890                  */
2891                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2892
2893                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2894                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2895                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2896                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2897
2898                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2899         } else if (tp->link_config.speed == SPEED_INVALID) {
2900                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2901                         tp->link_config.advertising &=
2902                                 ~(ADVERTISED_1000baseT_Half |
2903                                   ADVERTISED_1000baseT_Full);
2904
2905                 new_adv = ADVERTISE_CSMA;
2906                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2907                         new_adv |= ADVERTISE_10HALF;
2908                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2909                         new_adv |= ADVERTISE_10FULL;
2910                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2911                         new_adv |= ADVERTISE_100HALF;
2912                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2913                         new_adv |= ADVERTISE_100FULL;
2914
2915                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2916
2917                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2918
2919                 if (tp->link_config.advertising &
2920                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2921                         new_adv = 0;
2922                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2923                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2924                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2925                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2926                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2927                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2928                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2929                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2930                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2931                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2932                 } else {
2933                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2934                 }
2935         } else {
2936                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2937                 new_adv |= ADVERTISE_CSMA;
2938
2939                 /* Asking for a specific link mode. */
2940                 if (tp->link_config.speed == SPEED_1000) {
2941                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2942
2943                         if (tp->link_config.duplex == DUPLEX_FULL)
2944                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2945                         else
2946                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2947                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2948                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2949                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2950                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2951                 } else {
2952                         if (tp->link_config.speed == SPEED_100) {
2953                                 if (tp->link_config.duplex == DUPLEX_FULL)
2954                                         new_adv |= ADVERTISE_100FULL;
2955                                 else
2956                                         new_adv |= ADVERTISE_100HALF;
2957                         } else {
2958                                 if (tp->link_config.duplex == DUPLEX_FULL)
2959                                         new_adv |= ADVERTISE_10FULL;
2960                                 else
2961                                         new_adv |= ADVERTISE_10HALF;
2962                         }
2963                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2964
2965                         new_adv = 0;
2966                 }
2967
2968                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2969         }
2970
2971         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
2972                 u32 val = 0;
2973
2974                 tw32(TG3_CPMU_EEE_MODE,
2975                      tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2976
2977                 /* Enable SM_DSP clock and tx 6dB coding. */
2978                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
2979                       MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
2980                       MII_TG3_AUXCTL_ACTL_TX_6DB;
2981                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
2982
2983                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
2984                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
2985                     !tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
2986                         tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2,
2987                                          val | MII_TG3_DSP_CH34TP2_HIBW01);
2988
2989                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2990                         /* Advertise 100-BaseTX EEE ability */
2991                         if (tp->link_config.advertising &
2992                             (ADVERTISED_100baseT_Half |
2993                              ADVERTISED_100baseT_Full))
2994                                 val |= TG3_CL45_D7_EEEADV_CAP_100TX;
2995                         /* Advertise 1000-BaseT EEE ability */
2996                         if (tp->link_config.advertising &
2997                             (ADVERTISED_1000baseT_Half |
2998                              ADVERTISED_1000baseT_Full))
2999                                 val |= TG3_CL45_D7_EEEADV_CAP_1000T;
3000                 }
3001                 tg3_phy_cl45_write(tp, 0x7, TG3_CL45_D7_EEEADV_CAP, val);
3002
3003                 /* Turn off SM_DSP clock. */
3004                 val = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
3005                       MII_TG3_AUXCTL_ACTL_TX_6DB;
3006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3007         }
3008
3009         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
3010             tp->link_config.speed != SPEED_INVALID) {
3011                 u32 bmcr, orig_bmcr;
3012
3013                 tp->link_config.active_speed = tp->link_config.speed;
3014                 tp->link_config.active_duplex = tp->link_config.duplex;
3015
3016                 bmcr = 0;
3017                 switch (tp->link_config.speed) {
3018                 default:
3019                 case SPEED_10:
3020                         break;
3021
3022                 case SPEED_100:
3023                         bmcr |= BMCR_SPEED100;
3024                         break;
3025
3026                 case SPEED_1000:
3027                         bmcr |= TG3_BMCR_SPEED1000;
3028                         break;
3029                 }
3030
3031                 if (tp->link_config.duplex == DUPLEX_FULL)
3032                         bmcr |= BMCR_FULLDPLX;
3033
3034                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
3035                     (bmcr != orig_bmcr)) {
3036                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
3037                         for (i = 0; i < 1500; i++) {
3038                                 u32 tmp;
3039
3040                                 udelay(10);
3041                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
3042                                     tg3_readphy(tp, MII_BMSR, &tmp))
3043                                         continue;
3044                                 if (!(tmp & BMSR_LSTATUS)) {
3045                                         udelay(40);
3046                                         break;
3047                                 }
3048                         }
3049                         tg3_writephy(tp, MII_BMCR, bmcr);
3050                         udelay(40);
3051                 }
3052         } else {
3053                 tg3_writephy(tp, MII_BMCR,
3054                              BMCR_ANENABLE | BMCR_ANRESTART);
3055         }
3056 }
3057
3058 static int tg3_init_5401phy_dsp(struct tg3 *tp)
3059 {
3060         int err;
3061
3062         /* Turn off tap power management. */
3063         /* Set Extended packet length bit */
3064         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
3065
3066         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
3067         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
3068         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
3069         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
3070         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
3071
3072         udelay(40);
3073
3074         return err;
3075 }
3076
3077 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
3078 {
3079         u32 adv_reg, all_mask = 0;
3080
3081         if (mask & ADVERTISED_10baseT_Half)
3082                 all_mask |= ADVERTISE_10HALF;
3083         if (mask & ADVERTISED_10baseT_Full)
3084                 all_mask |= ADVERTISE_10FULL;
3085         if (mask & ADVERTISED_100baseT_Half)
3086                 all_mask |= ADVERTISE_100HALF;
3087         if (mask & ADVERTISED_100baseT_Full)
3088                 all_mask |= ADVERTISE_100FULL;
3089
3090         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
3091                 return 0;
3092
3093         if ((adv_reg & all_mask) != all_mask)
3094                 return 0;
3095         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3096                 u32 tg3_ctrl;
3097
3098                 all_mask = 0;
3099                 if (mask & ADVERTISED_1000baseT_Half)
3100                         all_mask |= ADVERTISE_1000HALF;
3101                 if (mask & ADVERTISED_1000baseT_Full)
3102                         all_mask |= ADVERTISE_1000FULL;
3103
3104                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
3105                         return 0;
3106
3107                 if ((tg3_ctrl & all_mask) != all_mask)
3108                         return 0;
3109         }
3110         return 1;
3111 }
3112
3113 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
3114 {
3115         u32 curadv, reqadv;
3116
3117         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3118                 return 1;
3119
3120         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3121         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3122
3123         if (tp->link_config.active_duplex == DUPLEX_FULL) {
3124                 if (curadv != reqadv)
3125                         return 0;
3126
3127                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3128                         tg3_readphy(tp, MII_LPA, rmtadv);
3129         } else {
3130                 /* Reprogram the advertisement register, even if it
3131                  * does not affect the current link.  If the link
3132                  * gets renegotiated in the future, we can save an
3133                  * additional renegotiation cycle by advertising
3134                  * it correctly in the first place.
3135                  */
3136                 if (curadv != reqadv) {
3137                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3138                                      ADVERTISE_PAUSE_ASYM);
3139                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3140                 }
3141         }
3142
3143         return 1;
3144 }
3145
3146 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3147 {
3148         int current_link_up;
3149         u32 bmsr, val;
3150         u32 lcl_adv, rmt_adv;
3151         u16 current_speed;
3152         u8 current_duplex;
3153         int i, err;
3154
3155         tw32(MAC_EVENT, 0);
3156
3157         tw32_f(MAC_STATUS,
3158              (MAC_STATUS_SYNC_CHANGED |
3159               MAC_STATUS_CFG_CHANGED |
3160               MAC_STATUS_MI_COMPLETION |
3161               MAC_STATUS_LNKSTATE_CHANGED));
3162         udelay(40);
3163
3164         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3165                 tw32_f(MAC_MI_MODE,
3166                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3167                 udelay(80);
3168         }
3169
3170         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3171
3172         /* Some third-party PHYs need to be reset on link going
3173          * down.
3174          */
3175         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3176              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3177              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3178             netif_carrier_ok(tp->dev)) {
3179                 tg3_readphy(tp, MII_BMSR, &bmsr);
3180                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3181                     !(bmsr & BMSR_LSTATUS))
3182                         force_reset = 1;
3183         }
3184         if (force_reset)
3185                 tg3_phy_reset(tp);
3186
3187         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3188                 tg3_readphy(tp, MII_BMSR, &bmsr);
3189                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3190                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3191                         bmsr = 0;
3192
3193                 if (!(bmsr & BMSR_LSTATUS)) {
3194                         err = tg3_init_5401phy_dsp(tp);
3195                         if (err)
3196                                 return err;
3197
3198                         tg3_readphy(tp, MII_BMSR, &bmsr);
3199                         for (i = 0; i < 1000; i++) {
3200                                 udelay(10);
3201                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3202                                     (bmsr & BMSR_LSTATUS)) {
3203                                         udelay(40);
3204                                         break;
3205                                 }
3206                         }
3207
3208                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3209                             TG3_PHY_REV_BCM5401_B0 &&
3210                             !(bmsr & BMSR_LSTATUS) &&
3211                             tp->link_config.active_speed == SPEED_1000) {
3212                                 err = tg3_phy_reset(tp);
3213                                 if (!err)
3214                                         err = tg3_init_5401phy_dsp(tp);
3215                                 if (err)
3216                                         return err;
3217                         }
3218                 }
3219         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3220                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3221                 /* 5701 {A0,B0} CRC bug workaround */
3222                 tg3_writephy(tp, 0x15, 0x0a75);
3223                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3224                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3225                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3226         }
3227
3228         /* Clear pending interrupts... */
3229         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3230         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3231
3232         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3233                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3234         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3235                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3236
3237         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3238             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3239                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3240                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3241                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3242                 else
3243                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3244         }
3245
3246         current_link_up = 0;
3247         current_speed = SPEED_INVALID;
3248         current_duplex = DUPLEX_INVALID;
3249
3250         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3251                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3252                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3253                 if (!(val & (1 << 10))) {
3254                         val |= (1 << 10);
3255                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3256                         goto relink;
3257                 }
3258         }
3259
3260         bmsr = 0;
3261         for (i = 0; i < 100; i++) {
3262                 tg3_readphy(tp, MII_BMSR, &bmsr);
3263                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3264                     (bmsr & BMSR_LSTATUS))
3265                         break;
3266                 udelay(40);
3267         }
3268
3269         if (bmsr & BMSR_LSTATUS) {
3270                 u32 aux_stat, bmcr;
3271
3272                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3273                 for (i = 0; i < 2000; i++) {
3274                         udelay(10);
3275                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3276                             aux_stat)
3277                                 break;
3278                 }
3279
3280                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3281                                              &current_speed,
3282                                              &current_duplex);
3283
3284                 bmcr = 0;
3285                 for (i = 0; i < 200; i++) {
3286                         tg3_readphy(tp, MII_BMCR, &bmcr);
3287                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3288                                 continue;
3289                         if (bmcr && bmcr != 0x7fff)
3290                                 break;
3291                         udelay(10);
3292                 }
3293
3294                 lcl_adv = 0;
3295                 rmt_adv = 0;
3296
3297                 tp->link_config.active_speed = current_speed;
3298                 tp->link_config.active_duplex = current_duplex;
3299
3300                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3301                         if ((bmcr & BMCR_ANENABLE) &&
3302                             tg3_copper_is_advertising_all(tp,
3303                                                 tp->link_config.advertising)) {
3304                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3305                                                                   &rmt_adv))
3306                                         current_link_up = 1;
3307                         }
3308                 } else {
3309                         if (!(bmcr & BMCR_ANENABLE) &&
3310                             tp->link_config.speed == current_speed &&
3311                             tp->link_config.duplex == current_duplex &&
3312                             tp->link_config.flowctrl ==
3313                             tp->link_config.active_flowctrl) {
3314                                 current_link_up = 1;
3315                         }
3316                 }
3317
3318                 if (current_link_up == 1 &&
3319                     tp->link_config.active_duplex == DUPLEX_FULL)
3320                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3321         }
3322
3323 relink:
3324         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3325                 tg3_phy_copper_begin(tp);
3326
3327                 tg3_readphy(tp, MII_BMSR, &bmsr);
3328                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3329                     (bmsr & BMSR_LSTATUS))
3330                         current_link_up = 1;
3331         }
3332
3333         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3334         if (current_link_up == 1) {
3335                 if (tp->link_config.active_speed == SPEED_100 ||
3336                     tp->link_config.active_speed == SPEED_10)
3337                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3338                 else
3339                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3340         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3341                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3342         else
3343                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3344
3345         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3346         if (tp->link_config.active_duplex == DUPLEX_HALF)
3347                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3348
3349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3350                 if (current_link_up == 1 &&
3351                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3352                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3353                 else
3354                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3355         }
3356
3357         /* ??? Without this setting Netgear GA302T PHY does not
3358          * ??? send/receive packets...
3359          */
3360         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3361             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3362                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3363                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3364                 udelay(80);
3365         }
3366
3367         tw32_f(MAC_MODE, tp->mac_mode);
3368         udelay(40);
3369
3370         tg3_phy_eee_adjust(tp, current_link_up);
3371
3372         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3373                 /* Polled via timer. */
3374                 tw32_f(MAC_EVENT, 0);
3375         } else {
3376                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3377         }
3378         udelay(40);
3379
3380         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3381             current_link_up == 1 &&
3382             tp->link_config.active_speed == SPEED_1000 &&
3383             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3384              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3385                 udelay(120);
3386                 tw32_f(MAC_STATUS,
3387                      (MAC_STATUS_SYNC_CHANGED |
3388                       MAC_STATUS_CFG_CHANGED));
3389                 udelay(40);
3390                 tg3_write_mem(tp,
3391                               NIC_SRAM_FIRMWARE_MBOX,
3392                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3393         }
3394
3395         /* Prevent send BD corruption. */
3396         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3397                 u16 oldlnkctl, newlnkctl;
3398
3399                 pci_read_config_word(tp->pdev,
3400                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3401                                      &oldlnkctl);
3402                 if (tp->link_config.active_speed == SPEED_100 ||
3403                     tp->link_config.active_speed == SPEED_10)
3404                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3405                 else
3406                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3407                 if (newlnkctl != oldlnkctl)
3408                         pci_write_config_word(tp->pdev,
3409                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3410                                               newlnkctl);
3411         }
3412
3413         if (current_link_up != netif_carrier_ok(tp->dev)) {
3414                 if (current_link_up)
3415                         netif_carrier_on(tp->dev);
3416                 else
3417                         netif_carrier_off(tp->dev);
3418                 tg3_link_report(tp);
3419         }
3420
3421         return 0;
3422 }
3423
3424 struct tg3_fiber_aneginfo {
3425         int state;
3426 #define ANEG_STATE_UNKNOWN              0
3427 #define ANEG_STATE_AN_ENABLE            1
3428 #define ANEG_STATE_RESTART_INIT         2
3429 #define ANEG_STATE_RESTART              3
3430 #define ANEG_STATE_DISABLE_LINK_OK      4
3431 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3432 #define ANEG_STATE_ABILITY_DETECT       6
3433 #define ANEG_STATE_ACK_DETECT_INIT      7
3434 #define ANEG_STATE_ACK_DETECT           8
3435 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3436 #define ANEG_STATE_COMPLETE_ACK         10
3437 #define ANEG_STATE_IDLE_DETECT_INIT     11
3438 #define ANEG_STATE_IDLE_DETECT          12
3439 #define ANEG_STATE_LINK_OK              13
3440 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3441 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3442
3443         u32 flags;
3444 #define MR_AN_ENABLE            0x00000001
3445 #define MR_RESTART_AN           0x00000002
3446 #define MR_AN_COMPLETE          0x00000004
3447 #define MR_PAGE_RX              0x00000008
3448 #define MR_NP_LOADED            0x00000010
3449 #define MR_TOGGLE_TX            0x00000020
3450 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3451 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3452 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3453 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3454 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3455 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3456 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3457 #define MR_TOGGLE_RX            0x00002000
3458 #define MR_NP_RX                0x00004000
3459
3460 #define MR_LINK_OK              0x80000000
3461
3462         unsigned long link_time, cur_time;
3463
3464         u32 ability_match_cfg;
3465         int ability_match_count;
3466
3467         char ability_match, idle_match, ack_match;
3468
3469         u32 txconfig, rxconfig;
3470 #define ANEG_CFG_NP             0x00000080
3471 #define ANEG_CFG_ACK            0x00000040
3472 #define ANEG_CFG_RF2            0x00000020
3473 #define ANEG_CFG_RF1            0x00000010
3474 #define ANEG_CFG_PS2            0x00000001
3475 #define ANEG_CFG_PS1            0x00008000
3476 #define ANEG_CFG_HD             0x00004000
3477 #define ANEG_CFG_FD             0x00002000
3478 #define ANEG_CFG_INVAL          0x00001f06
3479
3480 };
3481 #define ANEG_OK         0
3482 #define ANEG_DONE       1
3483 #define ANEG_TIMER_ENAB 2
3484 #define ANEG_FAILED     -1
3485
3486 #define ANEG_STATE_SETTLE_TIME  10000
3487
3488 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3489                                    struct tg3_fiber_aneginfo *ap)
3490 {
3491         u16 flowctrl;
3492         unsigned long delta;
3493         u32 rx_cfg_reg;
3494         int ret;
3495
3496         if (ap->state == ANEG_STATE_UNKNOWN) {
3497                 ap->rxconfig = 0;
3498                 ap->link_time = 0;
3499                 ap->cur_time = 0;
3500                 ap->ability_match_cfg = 0;
3501                 ap->ability_match_count = 0;
3502                 ap->ability_match = 0;
3503                 ap->idle_match = 0;
3504                 ap->ack_match = 0;
3505         }
3506         ap->cur_time++;
3507
3508         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3509                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3510
3511                 if (rx_cfg_reg != ap->ability_match_cfg) {
3512                         ap->ability_match_cfg = rx_cfg_reg;
3513                         ap->ability_match = 0;
3514                         ap->ability_match_count = 0;
3515                 } else {
3516                         if (++ap->ability_match_count > 1) {
3517                                 ap->ability_match = 1;
3518                                 ap->ability_match_cfg = rx_cfg_reg;
3519                         }
3520                 }
3521                 if (rx_cfg_reg & ANEG_CFG_ACK)
3522                         ap->ack_match = 1;
3523                 else
3524                         ap->ack_match = 0;
3525
3526                 ap->idle_match = 0;
3527         } else {
3528                 ap->idle_match = 1;
3529                 ap->ability_match_cfg = 0;
3530                 ap->ability_match_count = 0;
3531                 ap->ability_match = 0;
3532                 ap->ack_match = 0;
3533
3534                 rx_cfg_reg = 0;
3535         }
3536
3537         ap->rxconfig = rx_cfg_reg;
3538         ret = ANEG_OK;
3539
3540         switch (ap->state) {
3541         case ANEG_STATE_UNKNOWN:
3542                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3543                         ap->state = ANEG_STATE_AN_ENABLE;
3544
3545                 /* fallthru */
3546         case ANEG_STATE_AN_ENABLE:
3547                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3548                 if (ap->flags & MR_AN_ENABLE) {
3549                         ap->link_time = 0;
3550                         ap->cur_time = 0;
3551                         ap->ability_match_cfg = 0;
3552                         ap->ability_match_count = 0;
3553                         ap->ability_match = 0;
3554                         ap->idle_match = 0;
3555                         ap->ack_match = 0;
3556
3557                         ap->state = ANEG_STATE_RESTART_INIT;
3558                 } else {
3559                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3560                 }
3561                 break;
3562
3563         case ANEG_STATE_RESTART_INIT:
3564                 ap->link_time = ap->cur_time;
3565                 ap->flags &= ~(MR_NP_LOADED);
3566                 ap->txconfig = 0;
3567                 tw32(MAC_TX_AUTO_NEG, 0);
3568                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3569                 tw32_f(MAC_MODE, tp->mac_mode);
3570                 udelay(40);
3571
3572                 ret = ANEG_TIMER_ENAB;
3573                 ap->state = ANEG_STATE_RESTART;
3574
3575                 /* fallthru */
3576         case ANEG_STATE_RESTART:
3577                 delta = ap->cur_time - ap->link_time;
3578                 if (delta > ANEG_STATE_SETTLE_TIME)
3579                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3580                 else
3581                         ret = ANEG_TIMER_ENAB;
3582                 break;
3583
3584         case ANEG_STATE_DISABLE_LINK_OK:
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_ABILITY_DETECT_INIT:
3589                 ap->flags &= ~(MR_TOGGLE_TX);
3590                 ap->txconfig = ANEG_CFG_FD;
3591                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3592                 if (flowctrl & ADVERTISE_1000XPAUSE)
3593                         ap->txconfig |= ANEG_CFG_PS1;
3594                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3595                         ap->txconfig |= ANEG_CFG_PS2;
3596                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3597                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3598                 tw32_f(MAC_MODE, tp->mac_mode);
3599                 udelay(40);
3600
3601                 ap->state = ANEG_STATE_ABILITY_DETECT;
3602                 break;
3603
3604         case ANEG_STATE_ABILITY_DETECT:
3605                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3606                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3607                 break;
3608
3609         case ANEG_STATE_ACK_DETECT_INIT:
3610                 ap->txconfig |= ANEG_CFG_ACK;
3611                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3612                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3613                 tw32_f(MAC_MODE, tp->mac_mode);
3614                 udelay(40);
3615
3616                 ap->state = ANEG_STATE_ACK_DETECT;
3617
3618                 /* fallthru */
3619         case ANEG_STATE_ACK_DETECT:
3620                 if (ap->ack_match != 0) {
3621                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3622                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3623                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3624                         } else {
3625                                 ap->state = ANEG_STATE_AN_ENABLE;
3626                         }
3627                 } else if (ap->ability_match != 0 &&
3628                            ap->rxconfig == 0) {
3629                         ap->state = ANEG_STATE_AN_ENABLE;
3630                 }
3631                 break;
3632
3633         case ANEG_STATE_COMPLETE_ACK_INIT:
3634                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3635                         ret = ANEG_FAILED;
3636                         break;
3637                 }
3638                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3639                                MR_LP_ADV_HALF_DUPLEX |
3640                                MR_LP_ADV_SYM_PAUSE |
3641                                MR_LP_ADV_ASYM_PAUSE |
3642                                MR_LP_ADV_REMOTE_FAULT1 |
3643                                MR_LP_ADV_REMOTE_FAULT2 |
3644                                MR_LP_ADV_NEXT_PAGE |
3645                                MR_TOGGLE_RX |
3646                                MR_NP_RX);
3647                 if (ap->rxconfig & ANEG_CFG_FD)
3648                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3649                 if (ap->rxconfig & ANEG_CFG_HD)
3650                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3651                 if (ap->rxconfig & ANEG_CFG_PS1)
3652                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3653                 if (ap->rxconfig & ANEG_CFG_PS2)
3654                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3655                 if (ap->rxconfig & ANEG_CFG_RF1)
3656                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3657                 if (ap->rxconfig & ANEG_CFG_RF2)
3658                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3659                 if (ap->rxconfig & ANEG_CFG_NP)
3660                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3661
3662                 ap->link_time = ap->cur_time;
3663
3664                 ap->flags ^= (MR_TOGGLE_TX);
3665                 if (ap->rxconfig & 0x0008)
3666                         ap->flags |= MR_TOGGLE_RX;
3667                 if (ap->rxconfig & ANEG_CFG_NP)
3668                         ap->flags |= MR_NP_RX;
3669                 ap->flags |= MR_PAGE_RX;
3670
3671                 ap->state = ANEG_STATE_COMPLETE_ACK;
3672                 ret = ANEG_TIMER_ENAB;
3673                 break;
3674
3675         case ANEG_STATE_COMPLETE_ACK:
3676                 if (ap->ability_match != 0 &&
3677                     ap->rxconfig == 0) {
3678                         ap->state = ANEG_STATE_AN_ENABLE;
3679                         break;
3680                 }
3681                 delta = ap->cur_time - ap->link_time;
3682                 if (delta > ANEG_STATE_SETTLE_TIME) {
3683                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3684                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3685                         } else {
3686                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3687                                     !(ap->flags & MR_NP_RX)) {
3688                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3689                                 } else {
3690                                         ret = ANEG_FAILED;
3691                                 }
3692                         }
3693                 }
3694                 break;
3695
3696         case ANEG_STATE_IDLE_DETECT_INIT:
3697                 ap->link_time = ap->cur_time;
3698                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3699                 tw32_f(MAC_MODE, tp->mac_mode);
3700                 udelay(40);
3701
3702                 ap->state = ANEG_STATE_IDLE_DETECT;
3703                 ret = ANEG_TIMER_ENAB;
3704                 break;
3705
3706         case ANEG_STATE_IDLE_DETECT:
3707                 if (ap->ability_match != 0 &&
3708                     ap->rxconfig == 0) {
3709                         ap->state = ANEG_STATE_AN_ENABLE;
3710                         break;
3711                 }
3712                 delta = ap->cur_time - ap->link_time;
3713                 if (delta > ANEG_STATE_SETTLE_TIME) {
3714                         /* XXX another gem from the Broadcom driver :( */
3715                         ap->state = ANEG_STATE_LINK_OK;
3716                 }
3717                 break;
3718
3719         case ANEG_STATE_LINK_OK:
3720                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3721                 ret = ANEG_DONE;
3722                 break;
3723
3724         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3725                 /* ??? unimplemented */
3726                 break;
3727
3728         case ANEG_STATE_NEXT_PAGE_WAIT:
3729                 /* ??? unimplemented */
3730                 break;
3731
3732         default:
3733                 ret = ANEG_FAILED;
3734                 break;
3735         }
3736
3737         return ret;
3738 }
3739
3740 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3741 {
3742         int res = 0;
3743         struct tg3_fiber_aneginfo aninfo;
3744         int status = ANEG_FAILED;
3745         unsigned int tick;
3746         u32 tmp;
3747
3748         tw32_f(MAC_TX_AUTO_NEG, 0);
3749
3750         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3751         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3752         udelay(40);
3753
3754         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3755         udelay(40);
3756
3757         memset(&aninfo, 0, sizeof(aninfo));
3758         aninfo.flags |= MR_AN_ENABLE;
3759         aninfo.state = ANEG_STATE_UNKNOWN;
3760         aninfo.cur_time = 0;
3761         tick = 0;
3762         while (++tick < 195000) {
3763                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3764                 if (status == ANEG_DONE || status == ANEG_FAILED)
3765                         break;
3766
3767                 udelay(1);
3768         }
3769
3770         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3771         tw32_f(MAC_MODE, tp->mac_mode);
3772         udelay(40);
3773
3774         *txflags = aninfo.txconfig;
3775         *rxflags = aninfo.flags;
3776
3777         if (status == ANEG_DONE &&
3778             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3779                              MR_LP_ADV_FULL_DUPLEX)))
3780                 res = 1;
3781
3782         return res;
3783 }
3784
3785 static void tg3_init_bcm8002(struct tg3 *tp)
3786 {
3787         u32 mac_status = tr32(MAC_STATUS);
3788         int i;
3789
3790         /* Reset when initting first time or we have a link. */
3791         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3792             !(mac_status & MAC_STATUS_PCS_SYNCED))
3793                 return;
3794
3795         /* Set PLL lock range. */
3796         tg3_writephy(tp, 0x16, 0x8007);
3797
3798         /* SW reset */
3799         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3800
3801         /* Wait for reset to complete. */
3802         /* XXX schedule_timeout() ... */
3803         for (i = 0; i < 500; i++)
3804                 udelay(10);
3805
3806         /* Config mode; select PMA/Ch 1 regs. */
3807         tg3_writephy(tp, 0x10, 0x8411);
3808
3809         /* Enable auto-lock and comdet, select txclk for tx. */
3810         tg3_writephy(tp, 0x11, 0x0a10);
3811
3812         tg3_writephy(tp, 0x18, 0x00a0);
3813         tg3_writephy(tp, 0x16, 0x41ff);
3814
3815         /* Assert and deassert POR. */
3816         tg3_writephy(tp, 0x13, 0x0400);
3817         udelay(40);
3818         tg3_writephy(tp, 0x13, 0x0000);
3819
3820         tg3_writephy(tp, 0x11, 0x0a50);
3821         udelay(40);
3822         tg3_writephy(tp, 0x11, 0x0a10);
3823
3824         /* Wait for signal to stabilize */
3825         /* XXX schedule_timeout() ... */
3826         for (i = 0; i < 15000; i++)
3827                 udelay(10);
3828
3829         /* Deselect the channel register so we can read the PHYID
3830          * later.
3831          */
3832         tg3_writephy(tp, 0x10, 0x8011);
3833 }
3834
3835 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3836 {
3837         u16 flowctrl;
3838         u32 sg_dig_ctrl, sg_dig_status;
3839         u32 serdes_cfg, expected_sg_dig_ctrl;
3840         int workaround, port_a;
3841         int current_link_up;
3842
3843         serdes_cfg = 0;
3844         expected_sg_dig_ctrl = 0;
3845         workaround = 0;
3846         port_a = 1;
3847         current_link_up = 0;
3848
3849         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3850             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3851                 workaround = 1;
3852                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3853                         port_a = 0;
3854
3855                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3856                 /* preserve bits 20-23 for voltage regulator */
3857                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3858         }
3859
3860         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3861
3862         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3863                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3864                         if (workaround) {
3865                                 u32 val = serdes_cfg;
3866
3867                                 if (port_a)
3868                                         val |= 0xc010000;
3869                                 else
3870                                         val |= 0x4010000;
3871                                 tw32_f(MAC_SERDES_CFG, val);
3872                         }
3873
3874                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3875                 }
3876                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3877                         tg3_setup_flow_control(tp, 0, 0);
3878                         current_link_up = 1;
3879                 }
3880                 goto out;
3881         }
3882
3883         /* Want auto-negotiation.  */
3884         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3885
3886         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3887         if (flowctrl & ADVERTISE_1000XPAUSE)
3888                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3889         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3890                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3891
3892         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3893                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3894                     tp->serdes_counter &&
3895                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3896                                     MAC_STATUS_RCVD_CFG)) ==
3897                      MAC_STATUS_PCS_SYNCED)) {
3898                         tp->serdes_counter--;
3899                         current_link_up = 1;
3900                         goto out;
3901                 }
3902 restart_autoneg:
3903                 if (workaround)
3904                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3905                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3906                 udelay(5);
3907                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3908
3909                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3910                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3911         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3912                                  MAC_STATUS_SIGNAL_DET)) {
3913                 sg_dig_status = tr32(SG_DIG_STATUS);
3914                 mac_status = tr32(MAC_STATUS);
3915
3916                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3917                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3918                         u32 local_adv = 0, remote_adv = 0;
3919
3920                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3921                                 local_adv |= ADVERTISE_1000XPAUSE;
3922                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3923                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3924
3925                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3926                                 remote_adv |= LPA_1000XPAUSE;
3927                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3928                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3929
3930                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3931                         current_link_up = 1;
3932                         tp->serdes_counter = 0;
3933                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3934                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3935                         if (tp->serdes_counter)
3936                                 tp->serdes_counter--;
3937                         else {
3938                                 if (workaround) {
3939                                         u32 val = serdes_cfg;
3940
3941                                         if (port_a)
3942                                                 val |= 0xc010000;
3943                                         else
3944                                                 val |= 0x4010000;
3945
3946                                         tw32_f(MAC_SERDES_CFG, val);
3947                                 }
3948
3949                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3950                                 udelay(40);
3951
3952                                 /* Link parallel detection - link is up */
3953                                 /* only if we have PCS_SYNC and not */
3954                                 /* receiving config code words */
3955                                 mac_status = tr32(MAC_STATUS);
3956                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3957                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3958                                         tg3_setup_flow_control(tp, 0, 0);
3959                                         current_link_up = 1;
3960                                         tp->phy_flags |=
3961                                                 TG3_PHYFLG_PARALLEL_DETECT;
3962                                         tp->serdes_counter =
3963                                                 SERDES_PARALLEL_DET_TIMEOUT;
3964                                 } else
3965                                         goto restart_autoneg;
3966                         }
3967                 }
3968         } else {
3969                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3970                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3971         }
3972
3973 out:
3974         return current_link_up;
3975 }
3976
3977 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3978 {
3979         int current_link_up = 0;
3980
3981         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3982                 goto out;
3983
3984         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3985                 u32 txflags, rxflags;
3986                 int i;
3987
3988                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3989                         u32 local_adv = 0, remote_adv = 0;
3990
3991                         if (txflags & ANEG_CFG_PS1)
3992                                 local_adv |= ADVERTISE_1000XPAUSE;
3993                         if (txflags & ANEG_CFG_PS2)
3994                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3995
3996                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3997                                 remote_adv |= LPA_1000XPAUSE;
3998                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3999                                 remote_adv |= LPA_1000XPAUSE_ASYM;
4000
4001                         tg3_setup_flow_control(tp, local_adv, remote_adv);
4002
4003                         current_link_up = 1;
4004                 }
4005                 for (i = 0; i < 30; i++) {
4006                         udelay(20);
4007                         tw32_f(MAC_STATUS,
4008                                (MAC_STATUS_SYNC_CHANGED |
4009                                 MAC_STATUS_CFG_CHANGED));
4010                         udelay(40);
4011                         if ((tr32(MAC_STATUS) &
4012                              (MAC_STATUS_SYNC_CHANGED |
4013                               MAC_STATUS_CFG_CHANGED)) == 0)
4014                                 break;
4015                 }
4016
4017                 mac_status = tr32(MAC_STATUS);
4018                 if (current_link_up == 0 &&
4019                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
4020                     !(mac_status & MAC_STATUS_RCVD_CFG))
4021                         current_link_up = 1;
4022         } else {
4023                 tg3_setup_flow_control(tp, 0, 0);
4024
4025                 /* Forcing 1000FD link up. */
4026                 current_link_up = 1;
4027
4028                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
4029                 udelay(40);
4030
4031                 tw32_f(MAC_MODE, tp->mac_mode);
4032                 udelay(40);
4033         }
4034
4035 out:
4036         return current_link_up;
4037 }
4038
4039 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
4040 {
4041         u32 orig_pause_cfg;
4042         u16 orig_active_speed;
4043         u8 orig_active_duplex;
4044         u32 mac_status;
4045         int current_link_up;
4046         int i;
4047
4048         orig_pause_cfg = tp->link_config.active_flowctrl;
4049         orig_active_speed = tp->link_config.active_speed;
4050         orig_active_duplex = tp->link_config.active_duplex;
4051
4052         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
4053             netif_carrier_ok(tp->dev) &&
4054             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
4055                 mac_status = tr32(MAC_STATUS);
4056                 mac_status &= (MAC_STATUS_PCS_SYNCED |
4057                                MAC_STATUS_SIGNAL_DET |
4058                                MAC_STATUS_CFG_CHANGED |
4059                                MAC_STATUS_RCVD_CFG);
4060                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
4061                                    MAC_STATUS_SIGNAL_DET)) {
4062                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4063                                             MAC_STATUS_CFG_CHANGED));
4064                         return 0;
4065                 }
4066         }
4067
4068         tw32_f(MAC_TX_AUTO_NEG, 0);
4069
4070         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
4071         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
4072         tw32_f(MAC_MODE, tp->mac_mode);
4073         udelay(40);
4074
4075         if (tp->phy_id == TG3_PHY_ID_BCM8002)
4076                 tg3_init_bcm8002(tp);
4077
4078         /* Enable link change event even when serdes polling.  */
4079         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4080         udelay(40);
4081
4082         current_link_up = 0;
4083         mac_status = tr32(MAC_STATUS);
4084
4085         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
4086                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
4087         else
4088                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
4089
4090         tp->napi[0].hw_status->status =
4091                 (SD_STATUS_UPDATED |
4092                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
4093
4094         for (i = 0; i < 100; i++) {
4095                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
4096                                     MAC_STATUS_CFG_CHANGED));
4097                 udelay(5);
4098                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
4099                                          MAC_STATUS_CFG_CHANGED |
4100                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
4101                         break;
4102         }
4103
4104         mac_status = tr32(MAC_STATUS);
4105         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
4106                 current_link_up = 0;
4107                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
4108                     tp->serdes_counter == 0) {
4109                         tw32_f(MAC_MODE, (tp->mac_mode |
4110                                           MAC_MODE_SEND_CONFIGS));
4111                         udelay(1);
4112                         tw32_f(MAC_MODE, tp->mac_mode);
4113                 }
4114         }
4115
4116         if (current_link_up == 1) {
4117                 tp->link_config.active_speed = SPEED_1000;
4118                 tp->link_config.active_duplex = DUPLEX_FULL;
4119                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4120                                     LED_CTRL_LNKLED_OVERRIDE |
4121                                     LED_CTRL_1000MBPS_ON));
4122         } else {
4123                 tp->link_config.active_speed = SPEED_INVALID;
4124                 tp->link_config.active_duplex = DUPLEX_INVALID;
4125                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4126                                     LED_CTRL_LNKLED_OVERRIDE |
4127                                     LED_CTRL_TRAFFIC_OVERRIDE));
4128         }
4129
4130         if (current_link_up != netif_carrier_ok(tp->dev)) {
4131                 if (current_link_up)
4132                         netif_carrier_on(tp->dev);
4133                 else
4134                         netif_carrier_off(tp->dev);
4135                 tg3_link_report(tp);
4136         } else {
4137                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4138                 if (orig_pause_cfg != now_pause_cfg ||
4139                     orig_active_speed != tp->link_config.active_speed ||
4140                     orig_active_duplex != tp->link_config.active_duplex)
4141                         tg3_link_report(tp);
4142         }
4143
4144         return 0;
4145 }
4146
4147 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4148 {
4149         int current_link_up, err = 0;
4150         u32 bmsr, bmcr;
4151         u16 current_speed;
4152         u8 current_duplex;
4153         u32 local_adv, remote_adv;
4154
4155         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4156         tw32_f(MAC_MODE, tp->mac_mode);
4157         udelay(40);
4158
4159         tw32(MAC_EVENT, 0);
4160
4161         tw32_f(MAC_STATUS,
4162              (MAC_STATUS_SYNC_CHANGED |
4163               MAC_STATUS_CFG_CHANGED |
4164               MAC_STATUS_MI_COMPLETION |
4165               MAC_STATUS_LNKSTATE_CHANGED));
4166         udelay(40);
4167
4168         if (force_reset)
4169                 tg3_phy_reset(tp);
4170
4171         current_link_up = 0;
4172         current_speed = SPEED_INVALID;
4173         current_duplex = DUPLEX_INVALID;
4174
4175         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4176         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4177         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4178                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4179                         bmsr |= BMSR_LSTATUS;
4180                 else
4181                         bmsr &= ~BMSR_LSTATUS;
4182         }
4183
4184         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4185
4186         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4187             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4188                 /* do nothing, just check for link up at the end */
4189         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4190                 u32 adv, new_adv;
4191
4192                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4193                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4194                                   ADVERTISE_1000XPAUSE |
4195                                   ADVERTISE_1000XPSE_ASYM |
4196                                   ADVERTISE_SLCT);
4197
4198                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4199
4200                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4201                         new_adv |= ADVERTISE_1000XHALF;
4202                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4203                         new_adv |= ADVERTISE_1000XFULL;
4204
4205                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4206                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4207                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4208                         tg3_writephy(tp, MII_BMCR, bmcr);
4209
4210                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4211                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4212                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4213
4214                         return err;
4215                 }
4216         } else {
4217                 u32 new_bmcr;
4218
4219                 bmcr &= ~BMCR_SPEED1000;
4220                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4221
4222                 if (tp->link_config.duplex == DUPLEX_FULL)
4223                         new_bmcr |= BMCR_FULLDPLX;
4224
4225                 if (new_bmcr != bmcr) {
4226                         /* BMCR_SPEED1000 is a reserved bit that needs
4227                          * to be set on write.
4228                          */
4229                         new_bmcr |= BMCR_SPEED1000;
4230
4231                         /* Force a linkdown */
4232                         if (netif_carrier_ok(tp->dev)) {
4233                                 u32 adv;
4234
4235                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4236                                 adv &= ~(ADVERTISE_1000XFULL |
4237                                          ADVERTISE_1000XHALF |
4238                                          ADVERTISE_SLCT);
4239                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4240                                 tg3_writephy(tp, MII_BMCR, bmcr |
4241                                                            BMCR_ANRESTART |
4242                                                            BMCR_ANENABLE);
4243                                 udelay(10);
4244                                 netif_carrier_off(tp->dev);
4245                         }
4246                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4247                         bmcr = new_bmcr;
4248                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4249                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4250                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4251                             ASIC_REV_5714) {
4252                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4253                                         bmsr |= BMSR_LSTATUS;
4254                                 else
4255                                         bmsr &= ~BMSR_LSTATUS;
4256                         }
4257                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4258                 }
4259         }
4260
4261         if (bmsr & BMSR_LSTATUS) {
4262                 current_speed = SPEED_1000;
4263                 current_link_up = 1;
4264                 if (bmcr & BMCR_FULLDPLX)
4265                         current_duplex = DUPLEX_FULL;
4266                 else
4267                         current_duplex = DUPLEX_HALF;
4268
4269                 local_adv = 0;
4270                 remote_adv = 0;
4271
4272                 if (bmcr & BMCR_ANENABLE) {
4273                         u32 common;
4274
4275                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4276                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4277                         common = local_adv & remote_adv;
4278                         if (common & (ADVERTISE_1000XHALF |
4279                                       ADVERTISE_1000XFULL)) {
4280                                 if (common & ADVERTISE_1000XFULL)
4281                                         current_duplex = DUPLEX_FULL;
4282                                 else
4283                                         current_duplex = DUPLEX_HALF;
4284                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4285                                 /* Link is up via parallel detect */
4286                         } else {
4287                                 current_link_up = 0;
4288                         }
4289                 }
4290         }
4291
4292         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4293                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4294
4295         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4296         if (tp->link_config.active_duplex == DUPLEX_HALF)
4297                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4298
4299         tw32_f(MAC_MODE, tp->mac_mode);
4300         udelay(40);
4301
4302         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4303
4304         tp->link_config.active_speed = current_speed;
4305         tp->link_config.active_duplex = current_duplex;
4306
4307         if (current_link_up != netif_carrier_ok(tp->dev)) {
4308                 if (current_link_up)
4309                         netif_carrier_on(tp->dev);
4310                 else {
4311                         netif_carrier_off(tp->dev);
4312                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4313                 }
4314                 tg3_link_report(tp);
4315         }
4316         return err;
4317 }
4318
4319 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4320 {
4321         if (tp->serdes_counter) {
4322                 /* Give autoneg time to complete. */
4323                 tp->serdes_counter--;
4324                 return;
4325         }
4326
4327         if (!netif_carrier_ok(tp->dev) &&
4328             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4329                 u32 bmcr;
4330
4331                 tg3_readphy(tp, MII_BMCR, &bmcr);
4332                 if (bmcr & BMCR_ANENABLE) {
4333                         u32 phy1, phy2;
4334
4335                         /* Select shadow register 0x1f */
4336                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4337                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4338
4339                         /* Select expansion interrupt status register */
4340                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4341                                          MII_TG3_DSP_EXP1_INT_STAT);
4342                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4343                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4344
4345                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4346                                 /* We have signal detect and not receiving
4347                                  * config code words, link is up by parallel
4348                                  * detection.
4349                                  */
4350
4351                                 bmcr &= ~BMCR_ANENABLE;
4352                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4353                                 tg3_writephy(tp, MII_BMCR, bmcr);
4354                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4355                         }
4356                 }
4357         } else if (netif_carrier_ok(tp->dev) &&
4358                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4359                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4360                 u32 phy2;
4361
4362                 /* Select expansion interrupt status register */
4363                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4364                                  MII_TG3_DSP_EXP1_INT_STAT);
4365                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4366                 if (phy2 & 0x20) {
4367                         u32 bmcr;
4368
4369                         /* Config code words received, turn on autoneg. */
4370                         tg3_readphy(tp, MII_BMCR, &bmcr);
4371                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4372
4373                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4374
4375                 }
4376         }
4377 }
4378
4379 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4380 {
4381         int err;
4382
4383         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4384                 err = tg3_setup_fiber_phy(tp, force_reset);
4385         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4386                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4387         else
4388                 err = tg3_setup_copper_phy(tp, force_reset);
4389
4390         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4391                 u32 val, scale;
4392
4393                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4394                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4395                         scale = 65;
4396                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4397                         scale = 6;
4398                 else
4399                         scale = 12;
4400
4401                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4402                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4403                 tw32(GRC_MISC_CFG, val);
4404         }
4405
4406         if (tp->link_config.active_speed == SPEED_1000 &&
4407             tp->link_config.active_duplex == DUPLEX_HALF)
4408                 tw32(MAC_TX_LENGTHS,
4409                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4410                       (6 << TX_LENGTHS_IPG_SHIFT) |
4411                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4412         else
4413                 tw32(MAC_TX_LENGTHS,
4414                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4415                       (6 << TX_LENGTHS_IPG_SHIFT) |
4416                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4417
4418         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4419                 if (netif_carrier_ok(tp->dev)) {
4420                         tw32(HOSTCC_STAT_COAL_TICKS,
4421                              tp->coal.stats_block_coalesce_usecs);
4422                 } else {
4423                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4424                 }
4425         }
4426
4427         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4428                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4429                 if (!netif_carrier_ok(tp->dev))
4430                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4431                               tp->pwrmgmt_thresh;
4432                 else
4433                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4434                 tw32(PCIE_PWR_MGMT_THRESH, val);
4435         }
4436
4437         return err;
4438 }
4439
4440 static inline int tg3_irq_sync(struct tg3 *tp)
4441 {
4442         return tp->irq_sync;
4443 }
4444
4445 /* This is called whenever we suspect that the system chipset is re-
4446  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4447  * is bogus tx completions. We try to recover by setting the
4448  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4449  * in the workqueue.
4450  */
4451 static void tg3_tx_recover(struct tg3 *tp)
4452 {
4453         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4454                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4455
4456         netdev_warn(tp->dev,
4457                     "The system may be re-ordering memory-mapped I/O "
4458                     "cycles to the network device, attempting to recover. "
4459                     "Please report the problem to the driver maintainer "
4460                     "and include system chipset information.\n");
4461
4462         spin_lock(&tp->lock);
4463         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4464         spin_unlock(&tp->lock);
4465 }
4466
4467 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4468 {
4469         /* Tell compiler to fetch tx indices from memory. */
4470         barrier();
4471         return tnapi->tx_pending -
4472                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4473 }
4474
4475 /* Tigon3 never reports partial packet sends.  So we do not
4476  * need special logic to handle SKBs that have not had all
4477  * of their frags sent yet, like SunGEM does.
4478  */
4479 static void tg3_tx(struct tg3_napi *tnapi)
4480 {
4481         struct tg3 *tp = tnapi->tp;
4482         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4483         u32 sw_idx = tnapi->tx_cons;
4484         struct netdev_queue *txq;
4485         int index = tnapi - tp->napi;
4486
4487         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4488                 index--;
4489
4490         txq = netdev_get_tx_queue(tp->dev, index);
4491
4492         while (sw_idx != hw_idx) {
4493                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4494                 struct sk_buff *skb = ri->skb;
4495                 int i, tx_bug = 0;
4496
4497                 if (unlikely(skb == NULL)) {
4498                         tg3_tx_recover(tp);
4499                         return;
4500                 }
4501
4502                 pci_unmap_single(tp->pdev,
4503                                  dma_unmap_addr(ri, mapping),
4504                                  skb_headlen(skb),
4505                                  PCI_DMA_TODEVICE);
4506
4507                 ri->skb = NULL;
4508
4509                 sw_idx = NEXT_TX(sw_idx);
4510
4511                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4512                         ri = &tnapi->tx_buffers[sw_idx];
4513                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4514                                 tx_bug = 1;
4515
4516                         pci_unmap_page(tp->pdev,
4517                                        dma_unmap_addr(ri, mapping),
4518                                        skb_shinfo(skb)->frags[i].size,
4519                                        PCI_DMA_TODEVICE);
4520                         sw_idx = NEXT_TX(sw_idx);
4521                 }
4522
4523                 dev_kfree_skb(skb);
4524
4525                 if (unlikely(tx_bug)) {
4526                         tg3_tx_recover(tp);
4527                         return;
4528                 }
4529         }
4530
4531         tnapi->tx_cons = sw_idx;
4532
4533         /* Need to make the tx_cons update visible to tg3_start_xmit()
4534          * before checking for netif_queue_stopped().  Without the
4535          * memory barrier, there is a small possibility that tg3_start_xmit()
4536          * will miss it and cause the queue to be stopped forever.
4537          */
4538         smp_mb();
4539
4540         if (unlikely(netif_tx_queue_stopped(txq) &&
4541                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4542                 __netif_tx_lock(txq, smp_processor_id());
4543                 if (netif_tx_queue_stopped(txq) &&
4544                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4545                         netif_tx_wake_queue(txq);
4546                 __netif_tx_unlock(txq);
4547         }
4548 }
4549
4550 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4551 {
4552         if (!ri->skb)
4553                 return;
4554
4555         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4556                          map_sz, PCI_DMA_FROMDEVICE);
4557         dev_kfree_skb_any(ri->skb);
4558         ri->skb = NULL;
4559 }
4560
4561 /* Returns size of skb allocated or < 0 on error.
4562  *
4563  * We only need to fill in the address because the other members
4564  * of the RX descriptor are invariant, see tg3_init_rings.
4565  *
4566  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4567  * posting buffers we only dirty the first cache line of the RX
4568  * descriptor (containing the address).  Whereas for the RX status
4569  * buffers the cpu only reads the last cacheline of the RX descriptor
4570  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4571  */
4572 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4573                             u32 opaque_key, u32 dest_idx_unmasked)
4574 {
4575         struct tg3_rx_buffer_desc *desc;
4576         struct ring_info *map;
4577         struct sk_buff *skb;
4578         dma_addr_t mapping;
4579         int skb_size, dest_idx;
4580
4581         switch (opaque_key) {
4582         case RXD_OPAQUE_RING_STD:
4583                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4584                 desc = &tpr->rx_std[dest_idx];
4585                 map = &tpr->rx_std_buffers[dest_idx];
4586                 skb_size = tp->rx_pkt_map_sz;
4587                 break;
4588
4589         case RXD_OPAQUE_RING_JUMBO:
4590                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4591                 desc = &tpr->rx_jmb[dest_idx].std;
4592                 map = &tpr->rx_jmb_buffers[dest_idx];
4593                 skb_size = TG3_RX_JMB_MAP_SZ;
4594                 break;
4595
4596         default:
4597                 return -EINVAL;
4598         }
4599
4600         /* Do not overwrite any of the map or rp information
4601          * until we are sure we can commit to a new buffer.
4602          *
4603          * Callers depend upon this behavior and assume that
4604          * we leave everything unchanged if we fail.
4605          */
4606         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4607         if (skb == NULL)
4608                 return -ENOMEM;
4609
4610         skb_reserve(skb, tp->rx_offset);
4611
4612         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4613                                  PCI_DMA_FROMDEVICE);
4614         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4615                 dev_kfree_skb(skb);
4616                 return -EIO;
4617         }
4618
4619         map->skb = skb;
4620         dma_unmap_addr_set(map, mapping, mapping);
4621
4622         desc->addr_hi = ((u64)mapping >> 32);
4623         desc->addr_lo = ((u64)mapping & 0xffffffff);
4624
4625         return skb_size;
4626 }
4627
4628 /* We only need to move over in the address because the other
4629  * members of the RX descriptor are invariant.  See notes above
4630  * tg3_alloc_rx_skb for full details.
4631  */
4632 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4633                            struct tg3_rx_prodring_set *dpr,
4634                            u32 opaque_key, int src_idx,
4635                            u32 dest_idx_unmasked)
4636 {
4637         struct tg3 *tp = tnapi->tp;
4638         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4639         struct ring_info *src_map, *dest_map;
4640         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4641         int dest_idx;
4642
4643         switch (opaque_key) {
4644         case RXD_OPAQUE_RING_STD:
4645                 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
4646                 dest_desc = &dpr->rx_std[dest_idx];
4647                 dest_map = &dpr->rx_std_buffers[dest_idx];
4648                 src_desc = &spr->rx_std[src_idx];
4649                 src_map = &spr->rx_std_buffers[src_idx];
4650                 break;
4651
4652         case RXD_OPAQUE_RING_JUMBO:
4653                 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
4654                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4655                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4656                 src_desc = &spr->rx_jmb[src_idx].std;
4657                 src_map = &spr->rx_jmb_buffers[src_idx];
4658                 break;
4659
4660         default:
4661                 return;
4662         }
4663
4664         dest_map->skb = src_map->skb;
4665         dma_unmap_addr_set(dest_map, mapping,
4666                            dma_unmap_addr(src_map, mapping));
4667         dest_desc->addr_hi = src_desc->addr_hi;
4668         dest_desc->addr_lo = src_desc->addr_lo;
4669
4670         /* Ensure that the update to the skb happens after the physical
4671          * addresses have been transferred to the new BD location.
4672          */
4673         smp_wmb();
4674
4675         src_map->skb = NULL;
4676 }
4677
4678 /* The RX ring scheme is composed of multiple rings which post fresh
4679  * buffers to the chip, and one special ring the chip uses to report
4680  * status back to the host.
4681  *
4682  * The special ring reports the status of received packets to the
4683  * host.  The chip does not write into the original descriptor the
4684  * RX buffer was obtained from.  The chip simply takes the original
4685  * descriptor as provided by the host, updates the status and length
4686  * field, then writes this into the next status ring entry.
4687  *
4688  * Each ring the host uses to post buffers to the chip is described
4689  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4690  * it is first placed into the on-chip ram.  When the packet's length
4691  * is known, it walks down the TG3_BDINFO entries to select the ring.
4692  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4693  * which is within the range of the new packet's length is chosen.
4694  *
4695  * The "separate ring for rx status" scheme may sound queer, but it makes
4696  * sense from a cache coherency perspective.  If only the host writes
4697  * to the buffer post rings, and only the chip writes to the rx status
4698  * rings, then cache lines never move beyond shared-modified state.
4699  * If both the host and chip were to write into the same ring, cache line
4700  * eviction could occur since both entities want it in an exclusive state.
4701  */
4702 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4703 {
4704         struct tg3 *tp = tnapi->tp;
4705         u32 work_mask, rx_std_posted = 0;
4706         u32 std_prod_idx, jmb_prod_idx;
4707         u32 sw_idx = tnapi->rx_rcb_ptr;
4708         u16 hw_idx;
4709         int received;
4710         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4711
4712         hw_idx = *(tnapi->rx_rcb_prod_idx);
4713         /*
4714          * We need to order the read of hw_idx and the read of
4715          * the opaque cookie.
4716          */
4717         rmb();
4718         work_mask = 0;
4719         received = 0;
4720         std_prod_idx = tpr->rx_std_prod_idx;
4721         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4722         while (sw_idx != hw_idx && budget > 0) {
4723                 struct ring_info *ri;
4724                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4725                 unsigned int len;
4726                 struct sk_buff *skb;
4727                 dma_addr_t dma_addr;
4728                 u32 opaque_key, desc_idx, *post_ptr;
4729                 bool hw_vlan __maybe_unused = false;
4730                 u16 vtag __maybe_unused = 0;
4731
4732                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4733                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4734                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4735                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4736                         dma_addr = dma_unmap_addr(ri, mapping);
4737                         skb = ri->skb;
4738                         post_ptr = &std_prod_idx;
4739                         rx_std_posted++;
4740                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4741                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4742                         dma_addr = dma_unmap_addr(ri, mapping);
4743                         skb = ri->skb;
4744                         post_ptr = &jmb_prod_idx;
4745                 } else
4746                         goto next_pkt_nopost;
4747
4748                 work_mask |= opaque_key;
4749
4750                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4751                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4752                 drop_it:
4753                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4754                                        desc_idx, *post_ptr);
4755                 drop_it_no_recycle:
4756                         /* Other statistics kept track of by card. */
4757                         tp->net_stats.rx_dropped++;
4758                         goto next_pkt;
4759                 }
4760
4761                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4762                       ETH_FCS_LEN;
4763
4764                 if (len > TG3_RX_COPY_THRESH(tp)) {
4765                         int skb_size;
4766
4767                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4768                                                     *post_ptr);
4769                         if (skb_size < 0)
4770                                 goto drop_it;
4771
4772                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4773                                          PCI_DMA_FROMDEVICE);
4774
4775                         /* Ensure that the update to the skb happens
4776                          * after the usage of the old DMA mapping.
4777                          */
4778                         smp_wmb();
4779
4780                         ri->skb = NULL;
4781
4782                         skb_put(skb, len);
4783                 } else {
4784                         struct sk_buff *copy_skb;
4785
4786                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4787                                        desc_idx, *post_ptr);
4788
4789                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4790                                                     TG3_RAW_IP_ALIGN);
4791                         if (copy_skb == NULL)
4792                                 goto drop_it_no_recycle;
4793
4794                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4795                         skb_put(copy_skb, len);
4796                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4797                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4798                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4799
4800                         /* We'll reuse the original ring buffer. */
4801                         skb = copy_skb;
4802                 }
4803
4804                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4805                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4806                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4807                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4808                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4809                 else
4810                         skb_checksum_none_assert(skb);
4811
4812                 skb->protocol = eth_type_trans(skb, tp->dev);
4813
4814                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4815                     skb->protocol != htons(ETH_P_8021Q)) {
4816                         dev_kfree_skb(skb);
4817                         goto next_pkt;
4818                 }
4819
4820                 if (desc->type_flags & RXD_FLAG_VLAN &&
4821                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4822                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4823 #if TG3_VLAN_TAG_USED
4824                         if (tp->vlgrp)
4825                                 hw_vlan = true;
4826                         else
4827 #endif
4828                         {
4829                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4830                                                     __skb_push(skb, VLAN_HLEN);
4831
4832                                 memmove(ve, skb->data + VLAN_HLEN,
4833                                         ETH_ALEN * 2);
4834                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4835                                 ve->h_vlan_TCI = htons(vtag);
4836                         }
4837                 }
4838
4839 #if TG3_VLAN_TAG_USED
4840                 if (hw_vlan)
4841                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4842                 else
4843 #endif
4844                         napi_gro_receive(&tnapi->napi, skb);
4845
4846                 received++;
4847                 budget--;
4848
4849 next_pkt:
4850                 (*post_ptr)++;
4851
4852                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4853                         tpr->rx_std_prod_idx = std_prod_idx &
4854                                                tp->rx_std_ring_mask;
4855                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4856                                      tpr->rx_std_prod_idx);
4857                         work_mask &= ~RXD_OPAQUE_RING_STD;
4858                         rx_std_posted = 0;
4859                 }
4860 next_pkt_nopost:
4861                 sw_idx++;
4862                 sw_idx &= tp->rx_ret_ring_mask;
4863
4864                 /* Refresh hw_idx to see if there is new work */
4865                 if (sw_idx == hw_idx) {
4866                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4867                         rmb();
4868                 }
4869         }
4870
4871         /* ACK the status ring. */
4872         tnapi->rx_rcb_ptr = sw_idx;
4873         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4874
4875         /* Refill RX ring(s). */
4876         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4877                 if (work_mask & RXD_OPAQUE_RING_STD) {
4878                         tpr->rx_std_prod_idx = std_prod_idx &
4879                                                tp->rx_std_ring_mask;
4880                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4881                                      tpr->rx_std_prod_idx);
4882                 }
4883                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4884                         tpr->rx_jmb_prod_idx = jmb_prod_idx &
4885                                                tp->rx_jmb_ring_mask;
4886                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4887                                      tpr->rx_jmb_prod_idx);
4888                 }
4889                 mmiowb();
4890         } else if (work_mask) {
4891                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4892                  * updated before the producer indices can be updated.
4893                  */
4894                 smp_wmb();
4895
4896                 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
4897                 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
4898
4899                 if (tnapi != &tp->napi[1])
4900                         napi_schedule(&tp->napi[1].napi);
4901         }
4902
4903         return received;
4904 }
4905
4906 static void tg3_poll_link(struct tg3 *tp)
4907 {
4908         /* handle link change and other phy events */
4909         if (!(tp->tg3_flags &
4910               (TG3_FLAG_USE_LINKCHG_REG |
4911                TG3_FLAG_POLL_SERDES))) {
4912                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4913
4914                 if (sblk->status & SD_STATUS_LINK_CHG) {
4915                         sblk->status = SD_STATUS_UPDATED |
4916                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4917                         spin_lock(&tp->lock);
4918                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4919                                 tw32_f(MAC_STATUS,
4920                                      (MAC_STATUS_SYNC_CHANGED |
4921                                       MAC_STATUS_CFG_CHANGED |
4922                                       MAC_STATUS_MI_COMPLETION |
4923                                       MAC_STATUS_LNKSTATE_CHANGED));
4924                                 udelay(40);
4925                         } else
4926                                 tg3_setup_phy(tp, 0);
4927                         spin_unlock(&tp->lock);
4928                 }
4929         }
4930 }
4931
4932 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4933                                 struct tg3_rx_prodring_set *dpr,
4934                                 struct tg3_rx_prodring_set *spr)
4935 {
4936         u32 si, di, cpycnt, src_prod_idx;
4937         int i, err = 0;
4938
4939         while (1) {
4940                 src_prod_idx = spr->rx_std_prod_idx;
4941
4942                 /* Make sure updates to the rx_std_buffers[] entries and the
4943                  * standard producer index are seen in the correct order.
4944                  */
4945                 smp_rmb();
4946
4947                 if (spr->rx_std_cons_idx == src_prod_idx)
4948                         break;
4949
4950                 if (spr->rx_std_cons_idx < src_prod_idx)
4951                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4952                 else
4953                         cpycnt = tp->rx_std_ring_mask + 1 -
4954                                  spr->rx_std_cons_idx;
4955
4956                 cpycnt = min(cpycnt,
4957                              tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
4958
4959                 si = spr->rx_std_cons_idx;
4960                 di = dpr->rx_std_prod_idx;
4961
4962                 for (i = di; i < di + cpycnt; i++) {
4963                         if (dpr->rx_std_buffers[i].skb) {
4964                                 cpycnt = i - di;
4965                                 err = -ENOSPC;
4966                                 break;
4967                         }
4968                 }
4969
4970                 if (!cpycnt)
4971                         break;
4972
4973                 /* Ensure that updates to the rx_std_buffers ring and the
4974                  * shadowed hardware producer ring from tg3_recycle_skb() are
4975                  * ordered correctly WRT the skb check above.
4976                  */
4977                 smp_rmb();
4978
4979                 memcpy(&dpr->rx_std_buffers[di],
4980                        &spr->rx_std_buffers[si],
4981                        cpycnt * sizeof(struct ring_info));
4982
4983                 for (i = 0; i < cpycnt; i++, di++, si++) {
4984                         struct tg3_rx_buffer_desc *sbd, *dbd;
4985                         sbd = &spr->rx_std[si];
4986                         dbd = &dpr->rx_std[di];
4987                         dbd->addr_hi = sbd->addr_hi;
4988                         dbd->addr_lo = sbd->addr_lo;
4989                 }
4990
4991                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
4992                                        tp->rx_std_ring_mask;
4993                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
4994                                        tp->rx_std_ring_mask;
4995         }
4996
4997         while (1) {
4998                 src_prod_idx = spr->rx_jmb_prod_idx;
4999
5000                 /* Make sure updates to the rx_jmb_buffers[] entries and
5001                  * the jumbo producer index are seen in the correct order.
5002                  */
5003                 smp_rmb();
5004
5005                 if (spr->rx_jmb_cons_idx == src_prod_idx)
5006                         break;
5007
5008                 if (spr->rx_jmb_cons_idx < src_prod_idx)
5009                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
5010                 else
5011                         cpycnt = tp->rx_jmb_ring_mask + 1 -
5012                                  spr->rx_jmb_cons_idx;
5013
5014                 cpycnt = min(cpycnt,
5015                              tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
5016
5017                 si = spr->rx_jmb_cons_idx;
5018                 di = dpr->rx_jmb_prod_idx;
5019
5020                 for (i = di; i < di + cpycnt; i++) {
5021                         if (dpr->rx_jmb_buffers[i].skb) {
5022                                 cpycnt = i - di;
5023                                 err = -ENOSPC;
5024                                 break;
5025                         }
5026                 }
5027
5028                 if (!cpycnt)
5029                         break;
5030
5031                 /* Ensure that updates to the rx_jmb_buffers ring and the
5032                  * shadowed hardware producer ring from tg3_recycle_skb() are
5033                  * ordered correctly WRT the skb check above.
5034                  */
5035                 smp_rmb();
5036
5037                 memcpy(&dpr->rx_jmb_buffers[di],
5038                        &spr->rx_jmb_buffers[si],
5039                        cpycnt * sizeof(struct ring_info));
5040
5041                 for (i = 0; i < cpycnt; i++, di++, si++) {
5042                         struct tg3_rx_buffer_desc *sbd, *dbd;
5043                         sbd = &spr->rx_jmb[si].std;
5044                         dbd = &dpr->rx_jmb[di].std;
5045                         dbd->addr_hi = sbd->addr_hi;
5046                         dbd->addr_lo = sbd->addr_lo;
5047                 }
5048
5049                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
5050                                        tp->rx_jmb_ring_mask;
5051                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
5052                                        tp->rx_jmb_ring_mask;
5053         }
5054
5055         return err;
5056 }
5057
5058 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
5059 {
5060         struct tg3 *tp = tnapi->tp;
5061
5062         /* run TX completion thread */
5063         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
5064                 tg3_tx(tnapi);
5065                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5066                         return work_done;
5067         }
5068
5069         /* run RX thread, within the bounds set by NAPI.
5070          * All RX "locking" is done by ensuring outside
5071          * code synchronizes with tg3->napi.poll()
5072          */
5073         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
5074                 work_done += tg3_rx(tnapi, budget - work_done);
5075
5076         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
5077                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
5078                 int i, err = 0;
5079                 u32 std_prod_idx = dpr->rx_std_prod_idx;
5080                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
5081
5082                 for (i = 1; i < tp->irq_cnt; i++)
5083                         err |= tg3_rx_prodring_xfer(tp, dpr,
5084                                                     &tp->napi[i].prodring);
5085
5086                 wmb();
5087
5088                 if (std_prod_idx != dpr->rx_std_prod_idx)
5089                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
5090                                      dpr->rx_std_prod_idx);
5091
5092                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
5093                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
5094                                      dpr->rx_jmb_prod_idx);
5095
5096                 mmiowb();
5097
5098                 if (err)
5099                         tw32_f(HOSTCC_MODE, tp->coal_now);
5100         }
5101
5102         return work_done;
5103 }
5104
5105 static int tg3_poll_msix(struct napi_struct *napi, int budget)
5106 {
5107         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5108         struct tg3 *tp = tnapi->tp;
5109         int work_done = 0;
5110         struct tg3_hw_status *sblk = tnapi->hw_status;
5111
5112         while (1) {
5113                 work_done = tg3_poll_work(tnapi, work_done, budget);
5114
5115                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5116                         goto tx_recovery;
5117
5118                 if (unlikely(work_done >= budget))
5119                         break;
5120
5121                 /* tp->last_tag is used in tg3_int_reenable() below
5122                  * to tell the hw how much work has been processed,
5123                  * so we must read it before checking for more work.
5124                  */
5125                 tnapi->last_tag = sblk->status_tag;
5126                 tnapi->last_irq_tag = tnapi->last_tag;
5127                 rmb();
5128
5129                 /* check for RX/TX work to do */
5130                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
5131                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
5132                         napi_complete(napi);
5133                         /* Reenable interrupts. */
5134                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
5135                         mmiowb();
5136                         break;
5137                 }
5138         }
5139
5140         return work_done;
5141
5142 tx_recovery:
5143         /* work_done is guaranteed to be less than budget. */
5144         napi_complete(napi);
5145         schedule_work(&tp->reset_task);
5146         return work_done;
5147 }
5148
5149 static int tg3_poll(struct napi_struct *napi, int budget)
5150 {
5151         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5152         struct tg3 *tp = tnapi->tp;
5153         int work_done = 0;
5154         struct tg3_hw_status *sblk = tnapi->hw_status;
5155
5156         while (1) {
5157                 tg3_poll_link(tp);
5158
5159                 work_done = tg3_poll_work(tnapi, work_done, budget);
5160
5161                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5162                         goto tx_recovery;
5163
5164                 if (unlikely(work_done >= budget))
5165                         break;
5166
5167                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5168                         /* tp->last_tag is used in tg3_int_reenable() below
5169                          * to tell the hw how much work has been processed,
5170                          * so we must read it before checking for more work.
5171                          */
5172                         tnapi->last_tag = sblk->status_tag;
5173                         tnapi->last_irq_tag = tnapi->last_tag;
5174                         rmb();
5175                 } else
5176                         sblk->status &= ~SD_STATUS_UPDATED;
5177
5178                 if (likely(!tg3_has_work(tnapi))) {
5179                         napi_complete(napi);
5180                         tg3_int_reenable(tnapi);
5181                         break;
5182                 }
5183         }
5184
5185         return work_done;
5186
5187 tx_recovery:
5188         /* work_done is guaranteed to be less than budget. */
5189         napi_complete(napi);
5190         schedule_work(&tp->reset_task);
5191         return work_done;
5192 }
5193
5194 static void tg3_napi_disable(struct tg3 *tp)
5195 {
5196         int i;
5197
5198         for (i = tp->irq_cnt - 1; i >= 0; i--)
5199                 napi_disable(&tp->napi[i].napi);
5200 }
5201
5202 static void tg3_napi_enable(struct tg3 *tp)
5203 {
5204         int i;
5205
5206         for (i = 0; i < tp->irq_cnt; i++)
5207                 napi_enable(&tp->napi[i].napi);
5208 }
5209
5210 static void tg3_napi_init(struct tg3 *tp)
5211 {
5212         int i;
5213
5214         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5215         for (i = 1; i < tp->irq_cnt; i++)
5216                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5217 }
5218
5219 static void tg3_napi_fini(struct tg3 *tp)
5220 {
5221         int i;
5222
5223         for (i = 0; i < tp->irq_cnt; i++)
5224                 netif_napi_del(&tp->napi[i].napi);
5225 }
5226
5227 static inline void tg3_netif_stop(struct tg3 *tp)
5228 {
5229         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5230         tg3_napi_disable(tp);
5231         netif_tx_disable(tp->dev);
5232 }
5233
5234 static inline void tg3_netif_start(struct tg3 *tp)
5235 {
5236         /* NOTE: unconditional netif_tx_wake_all_queues is only
5237          * appropriate so long as all callers are assured to
5238          * have free tx slots (such as after tg3_init_hw)
5239          */
5240         netif_tx_wake_all_queues(tp->dev);
5241
5242         tg3_napi_enable(tp);
5243         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5244         tg3_enable_ints(tp);
5245 }
5246
5247 static void tg3_irq_quiesce(struct tg3 *tp)
5248 {
5249         int i;
5250
5251         BUG_ON(tp->irq_sync);
5252
5253         tp->irq_sync = 1;
5254         smp_mb();
5255
5256         for (i = 0; i < tp->irq_cnt; i++)
5257                 synchronize_irq(tp->napi[i].irq_vec);
5258 }
5259
5260 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5261  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5262  * with as well.  Most of the time, this is not necessary except when
5263  * shutting down the device.
5264  */
5265 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5266 {
5267         spin_lock_bh(&tp->lock);
5268         if (irq_sync)
5269                 tg3_irq_quiesce(tp);
5270 }
5271
5272 static inline void tg3_full_unlock(struct tg3 *tp)
5273 {
5274         spin_unlock_bh(&tp->lock);
5275 }
5276
5277 /* One-shot MSI handler - Chip automatically disables interrupt
5278  * after sending MSI so driver doesn't have to do it.
5279  */
5280 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5281 {
5282         struct tg3_napi *tnapi = dev_id;
5283         struct tg3 *tp = tnapi->tp;
5284
5285         prefetch(tnapi->hw_status);
5286         if (tnapi->rx_rcb)
5287                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5288
5289         if (likely(!tg3_irq_sync(tp)))
5290                 napi_schedule(&tnapi->napi);
5291
5292         return IRQ_HANDLED;
5293 }
5294
5295 /* MSI ISR - No need to check for interrupt sharing and no need to
5296  * flush status block and interrupt mailbox. PCI ordering rules
5297  * guarantee that MSI will arrive after the status block.
5298  */
5299 static irqreturn_t tg3_msi(int irq, void *dev_id)
5300 {
5301         struct tg3_napi *tnapi = dev_id;
5302         struct tg3 *tp = tnapi->tp;
5303
5304         prefetch(tnapi->hw_status);
5305         if (tnapi->rx_rcb)
5306                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5307         /*
5308          * Writing any value to intr-mbox-0 clears PCI INTA# and
5309          * chip-internal interrupt pending events.
5310          * Writing non-zero to intr-mbox-0 additional tells the
5311          * NIC to stop sending us irqs, engaging "in-intr-handler"
5312          * event coalescing.
5313          */
5314         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5315         if (likely(!tg3_irq_sync(tp)))
5316                 napi_schedule(&tnapi->napi);
5317
5318         return IRQ_RETVAL(1);
5319 }
5320
5321 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5322 {
5323         struct tg3_napi *tnapi = dev_id;
5324         struct tg3 *tp = tnapi->tp;
5325         struct tg3_hw_status *sblk = tnapi->hw_status;
5326         unsigned int handled = 1;
5327
5328         /* In INTx mode, it is possible for the interrupt to arrive at
5329          * the CPU before the status block posted prior to the interrupt.
5330          * Reading the PCI State register will confirm whether the
5331          * interrupt is ours and will flush the status block.
5332          */
5333         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5334                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5335                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5336                         handled = 0;
5337                         goto out;
5338                 }
5339         }
5340
5341         /*
5342          * Writing any value to intr-mbox-0 clears PCI INTA# and
5343          * chip-internal interrupt pending events.
5344          * Writing non-zero to intr-mbox-0 additional tells the
5345          * NIC to stop sending us irqs, engaging "in-intr-handler"
5346          * event coalescing.
5347          *
5348          * Flush the mailbox to de-assert the IRQ immediately to prevent
5349          * spurious interrupts.  The flush impacts performance but
5350          * excessive spurious interrupts can be worse in some cases.
5351          */
5352         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5353         if (tg3_irq_sync(tp))
5354                 goto out;
5355         sblk->status &= ~SD_STATUS_UPDATED;
5356         if (likely(tg3_has_work(tnapi))) {
5357                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5358                 napi_schedule(&tnapi->napi);
5359         } else {
5360                 /* No work, shared interrupt perhaps?  re-enable
5361                  * interrupts, and flush that PCI write
5362                  */
5363                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5364                                0x00000000);
5365         }
5366 out:
5367         return IRQ_RETVAL(handled);
5368 }
5369
5370 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5371 {
5372         struct tg3_napi *tnapi = dev_id;
5373         struct tg3 *tp = tnapi->tp;
5374         struct tg3_hw_status *sblk = tnapi->hw_status;
5375         unsigned int handled = 1;
5376
5377         /* In INTx mode, it is possible for the interrupt to arrive at
5378          * the CPU before the status block posted prior to the interrupt.
5379          * Reading the PCI State register will confirm whether the
5380          * interrupt is ours and will flush the status block.
5381          */
5382         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5383                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5384                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5385                         handled = 0;
5386                         goto out;
5387                 }
5388         }
5389
5390         /*
5391          * writing any value to intr-mbox-0 clears PCI INTA# and
5392          * chip-internal interrupt pending events.
5393          * writing non-zero to intr-mbox-0 additional tells the
5394          * NIC to stop sending us irqs, engaging "in-intr-handler"
5395          * event coalescing.
5396          *
5397          * Flush the mailbox to de-assert the IRQ immediately to prevent
5398          * spurious interrupts.  The flush impacts performance but
5399          * excessive spurious interrupts can be worse in some cases.
5400          */
5401         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5402
5403         /*
5404          * In a shared interrupt configuration, sometimes other devices'
5405          * interrupts will scream.  We record the current status tag here
5406          * so that the above check can report that the screaming interrupts
5407          * are unhandled.  Eventually they will be silenced.
5408          */
5409         tnapi->last_irq_tag = sblk->status_tag;
5410
5411         if (tg3_irq_sync(tp))
5412                 goto out;
5413
5414         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5415
5416         napi_schedule(&tnapi->napi);
5417
5418 out:
5419         return IRQ_RETVAL(handled);
5420 }
5421
5422 /* ISR for interrupt test */
5423 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5424 {
5425         struct tg3_napi *tnapi = dev_id;
5426         struct tg3 *tp = tnapi->tp;
5427         struct tg3_hw_status *sblk = tnapi->hw_status;
5428
5429         if ((sblk->status & SD_STATUS_UPDATED) ||
5430             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5431                 tg3_disable_ints(tp);
5432                 return IRQ_RETVAL(1);
5433         }
5434         return IRQ_RETVAL(0);
5435 }
5436
5437 static int tg3_init_hw(struct tg3 *, int);
5438 static int tg3_halt(struct tg3 *, int, int);
5439
5440 /* Restart hardware after configuration changes, self-test, etc.
5441  * Invoked with tp->lock held.
5442  */
5443 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5444         __releases(tp->lock)
5445         __acquires(tp->lock)
5446 {
5447         int err;
5448
5449         err = tg3_init_hw(tp, reset_phy);
5450         if (err) {
5451                 netdev_err(tp->dev,
5452                            "Failed to re-initialize device, aborting\n");
5453                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5454                 tg3_full_unlock(tp);
5455                 del_timer_sync(&tp->timer);
5456                 tp->irq_sync = 0;
5457                 tg3_napi_enable(tp);
5458                 dev_close(tp->dev);
5459                 tg3_full_lock(tp, 0);
5460         }
5461         return err;
5462 }
5463
5464 #ifdef CONFIG_NET_POLL_CONTROLLER
5465 static void tg3_poll_controller(struct net_device *dev)
5466 {
5467         int i;
5468         struct tg3 *tp = netdev_priv(dev);
5469
5470         for (i = 0; i < tp->irq_cnt; i++)
5471                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5472 }
5473 #endif
5474
5475 static void tg3_reset_task(struct work_struct *work)
5476 {
5477         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5478         int err;
5479         unsigned int restart_timer;
5480
5481         tg3_full_lock(tp, 0);
5482
5483         if (!netif_running(tp->dev)) {
5484                 tg3_full_unlock(tp);
5485                 return;
5486         }
5487
5488         tg3_full_unlock(tp);
5489
5490         tg3_phy_stop(tp);
5491
5492         tg3_netif_stop(tp);
5493
5494         tg3_full_lock(tp, 1);
5495
5496         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5497         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5498
5499         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5500                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5501                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5502                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5503                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5504         }
5505
5506         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5507         err = tg3_init_hw(tp, 1);
5508         if (err)
5509                 goto out;
5510
5511         tg3_netif_start(tp);
5512
5513         if (restart_timer)
5514                 mod_timer(&tp->timer, jiffies + 1);
5515
5516 out:
5517         tg3_full_unlock(tp);
5518
5519         if (!err)
5520                 tg3_phy_start(tp);
5521 }
5522
5523 static void tg3_dump_short_state(struct tg3 *tp)
5524 {
5525         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5526                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5527         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5528                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5529 }
5530
5531 static void tg3_tx_timeout(struct net_device *dev)
5532 {
5533         struct tg3 *tp = netdev_priv(dev);
5534
5535         if (netif_msg_tx_err(tp)) {
5536                 netdev_err(dev, "transmit timed out, resetting\n");
5537                 tg3_dump_short_state(tp);
5538         }
5539
5540         schedule_work(&tp->reset_task);
5541 }
5542
5543 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5544 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5545 {
5546         u32 base = (u32) mapping & 0xffffffff;
5547
5548         return (base > 0xffffdcc0) && (base + len + 8 < base);
5549 }
5550
5551 /* Test for DMA addresses > 40-bit */
5552 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5553                                           int len)
5554 {
5555 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5556         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5557                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5558         return 0;
5559 #else
5560         return 0;
5561 #endif
5562 }
5563
5564 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5565
5566 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5567 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5568                                        struct sk_buff *skb, u32 last_plus_one,
5569                                        u32 *start, u32 base_flags, u32 mss)
5570 {
5571         struct tg3 *tp = tnapi->tp;
5572         struct sk_buff *new_skb;
5573         dma_addr_t new_addr = 0;
5574         u32 entry = *start;
5575         int i, ret = 0;
5576
5577         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5578                 new_skb = skb_copy(skb, GFP_ATOMIC);
5579         else {
5580                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5581
5582                 new_skb = skb_copy_expand(skb,
5583                                           skb_headroom(skb) + more_headroom,
5584                                           skb_tailroom(skb), GFP_ATOMIC);
5585         }
5586
5587         if (!new_skb) {
5588                 ret = -1;
5589         } else {
5590                 /* New SKB is guaranteed to be linear. */
5591                 entry = *start;
5592                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5593                                           PCI_DMA_TODEVICE);
5594                 /* Make sure the mapping succeeded */
5595                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5596                         ret = -1;
5597                         dev_kfree_skb(new_skb);
5598                         new_skb = NULL;
5599
5600                 /* Make sure new skb does not cross any 4G boundaries.
5601                  * Drop the packet if it does.
5602                  */
5603                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5604                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5605                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5606                                          PCI_DMA_TODEVICE);
5607                         ret = -1;
5608                         dev_kfree_skb(new_skb);
5609                         new_skb = NULL;
5610                 } else {
5611                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5612                                     base_flags, 1 | (mss << 1));
5613                         *start = NEXT_TX(entry);
5614                 }
5615         }
5616
5617         /* Now clean up the sw ring entries. */
5618         i = 0;
5619         while (entry != last_plus_one) {
5620                 int len;
5621
5622                 if (i == 0)
5623                         len = skb_headlen(skb);
5624                 else
5625                         len = skb_shinfo(skb)->frags[i-1].size;
5626
5627                 pci_unmap_single(tp->pdev,
5628                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5629                                                 mapping),
5630                                  len, PCI_DMA_TODEVICE);
5631                 if (i == 0) {
5632                         tnapi->tx_buffers[entry].skb = new_skb;
5633                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5634                                            new_addr);
5635                 } else {
5636                         tnapi->tx_buffers[entry].skb = NULL;
5637                 }
5638                 entry = NEXT_TX(entry);
5639                 i++;
5640         }
5641
5642         dev_kfree_skb(skb);
5643
5644         return ret;
5645 }
5646
5647 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5648                         dma_addr_t mapping, int len, u32 flags,
5649                         u32 mss_and_is_end)
5650 {
5651         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5652         int is_end = (mss_and_is_end & 0x1);
5653         u32 mss = (mss_and_is_end >> 1);
5654         u32 vlan_tag = 0;
5655
5656         if (is_end)
5657                 flags |= TXD_FLAG_END;
5658         if (flags & TXD_FLAG_VLAN) {
5659                 vlan_tag = flags >> 16;
5660                 flags &= 0xffff;
5661         }
5662         vlan_tag |= (mss << TXD_MSS_SHIFT);
5663
5664         txd->addr_hi = ((u64) mapping >> 32);
5665         txd->addr_lo = ((u64) mapping & 0xffffffff);
5666         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5667         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5668 }
5669
5670 /* hard_start_xmit for devices that don't have any bugs and
5671  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5672  */
5673 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5674                                   struct net_device *dev)
5675 {
5676         struct tg3 *tp = netdev_priv(dev);
5677         u32 len, entry, base_flags, mss;
5678         dma_addr_t mapping;
5679         struct tg3_napi *tnapi;
5680         struct netdev_queue *txq;
5681         unsigned int i, last;
5682
5683         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5684         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5685         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5686                 tnapi++;
5687
5688         /* We are running in BH disabled context with netif_tx_lock
5689          * and TX reclaim runs via tp->napi.poll inside of a software
5690          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5691          * no IRQ context deadlocks to worry about either.  Rejoice!
5692          */
5693         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5694                 if (!netif_tx_queue_stopped(txq)) {
5695                         netif_tx_stop_queue(txq);
5696
5697                         /* This is a hard error, log it. */
5698                         netdev_err(dev,
5699                                    "BUG! Tx Ring full when queue awake!\n");
5700                 }
5701                 return NETDEV_TX_BUSY;
5702         }
5703
5704         entry = tnapi->tx_prod;
5705         base_flags = 0;
5706         mss = skb_shinfo(skb)->gso_size;
5707         if (mss) {
5708                 int tcp_opt_len, ip_tcp_len;
5709                 u32 hdrlen;
5710
5711                 if (skb_header_cloned(skb) &&
5712                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5713                         dev_kfree_skb(skb);
5714                         goto out_unlock;
5715                 }
5716
5717                 if (skb_is_gso_v6(skb)) {
5718                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5719                 } else {
5720                         struct iphdr *iph = ip_hdr(skb);
5721
5722                         tcp_opt_len = tcp_optlen(skb);
5723                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5724
5725                         iph->check = 0;
5726                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5727                         hdrlen = ip_tcp_len + tcp_opt_len;
5728                 }
5729
5730                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5731                         mss |= (hdrlen & 0xc) << 12;
5732                         if (hdrlen & 0x10)
5733                                 base_flags |= 0x00000010;
5734                         base_flags |= (hdrlen & 0x3e0) << 5;
5735                 } else
5736                         mss |= hdrlen << 9;
5737
5738                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5739                                TXD_FLAG_CPU_POST_DMA);
5740
5741                 tcp_hdr(skb)->check = 0;
5742
5743         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5744                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5745         }
5746
5747 #if TG3_VLAN_TAG_USED
5748         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5749                 base_flags |= (TXD_FLAG_VLAN |
5750                                (vlan_tx_tag_get(skb) << 16));
5751 #endif
5752
5753         len = skb_headlen(skb);
5754
5755         /* Queue skb data, a.k.a. the main skb fragment. */
5756         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5757         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5758                 dev_kfree_skb(skb);
5759                 goto out_unlock;
5760         }
5761
5762         tnapi->tx_buffers[entry].skb = skb;
5763         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5764
5765         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5766             !mss && skb->len > ETH_DATA_LEN)
5767                 base_flags |= TXD_FLAG_JMB_PKT;
5768
5769         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5770                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5771
5772         entry = NEXT_TX(entry);
5773
5774         /* Now loop through additional data fragments, and queue them. */
5775         if (skb_shinfo(skb)->nr_frags > 0) {
5776                 last = skb_shinfo(skb)->nr_frags - 1;
5777                 for (i = 0; i <= last; i++) {
5778                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5779
5780                         len = frag->size;
5781                         mapping = pci_map_page(tp->pdev,
5782                                                frag->page,
5783                                                frag->page_offset,
5784                                                len, PCI_DMA_TODEVICE);
5785                         if (pci_dma_mapping_error(tp->pdev, mapping))
5786                                 goto dma_error;
5787
5788                         tnapi->tx_buffers[entry].skb = NULL;
5789                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5790                                            mapping);
5791
5792                         tg3_set_txd(tnapi, entry, mapping, len,
5793                                     base_flags, (i == last) | (mss << 1));
5794
5795                         entry = NEXT_TX(entry);
5796                 }
5797         }
5798
5799         /* Packets are ready, update Tx producer idx local and on card. */
5800         tw32_tx_mbox(tnapi->prodmbox, entry);
5801
5802         tnapi->tx_prod = entry;
5803         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5804                 netif_tx_stop_queue(txq);
5805
5806                 /* netif_tx_stop_queue() must be done before checking
5807                  * checking tx index in tg3_tx_avail() below, because in
5808                  * tg3_tx(), we update tx index before checking for
5809                  * netif_tx_queue_stopped().
5810                  */
5811                 smp_mb();
5812                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5813                         netif_tx_wake_queue(txq);
5814         }
5815
5816 out_unlock:
5817         mmiowb();
5818
5819         return NETDEV_TX_OK;
5820
5821 dma_error:
5822         last = i;
5823         entry = tnapi->tx_prod;
5824         tnapi->tx_buffers[entry].skb = NULL;
5825         pci_unmap_single(tp->pdev,
5826                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5827                          skb_headlen(skb),
5828                          PCI_DMA_TODEVICE);
5829         for (i = 0; i <= last; i++) {
5830                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5831                 entry = NEXT_TX(entry);
5832
5833                 pci_unmap_page(tp->pdev,
5834                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5835                                               mapping),
5836                                frag->size, PCI_DMA_TODEVICE);
5837         }
5838
5839         dev_kfree_skb(skb);
5840         return NETDEV_TX_OK;
5841 }
5842
5843 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5844                                           struct net_device *);
5845
5846 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5847  * TSO header is greater than 80 bytes.
5848  */
5849 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5850 {
5851         struct sk_buff *segs, *nskb;
5852         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5853
5854         /* Estimate the number of fragments in the worst case */
5855         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5856                 netif_stop_queue(tp->dev);
5857
5858                 /* netif_tx_stop_queue() must be done before checking
5859                  * checking tx index in tg3_tx_avail() below, because in
5860                  * tg3_tx(), we update tx index before checking for
5861                  * netif_tx_queue_stopped().
5862                  */
5863                 smp_mb();
5864                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5865                         return NETDEV_TX_BUSY;
5866
5867                 netif_wake_queue(tp->dev);
5868         }
5869
5870         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5871         if (IS_ERR(segs))
5872                 goto tg3_tso_bug_end;
5873
5874         do {
5875                 nskb = segs;
5876                 segs = segs->next;
5877                 nskb->next = NULL;
5878                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5879         } while (segs);
5880
5881 tg3_tso_bug_end:
5882         dev_kfree_skb(skb);
5883
5884         return NETDEV_TX_OK;
5885 }
5886
5887 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5888  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5889  */
5890 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5891                                           struct net_device *dev)
5892 {
5893         struct tg3 *tp = netdev_priv(dev);
5894         u32 len, entry, base_flags, mss;
5895         int would_hit_hwbug;
5896         dma_addr_t mapping;
5897         struct tg3_napi *tnapi;
5898         struct netdev_queue *txq;
5899         unsigned int i, last;
5900
5901         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5902         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5903         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5904                 tnapi++;
5905
5906         /* We are running in BH disabled context with netif_tx_lock
5907          * and TX reclaim runs via tp->napi.poll inside of a software
5908          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5909          * no IRQ context deadlocks to worry about either.  Rejoice!
5910          */
5911         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5912                 if (!netif_tx_queue_stopped(txq)) {
5913                         netif_tx_stop_queue(txq);
5914
5915                         /* This is a hard error, log it. */
5916                         netdev_err(dev,
5917                                    "BUG! Tx Ring full when queue awake!\n");
5918                 }
5919                 return NETDEV_TX_BUSY;
5920         }
5921
5922         entry = tnapi->tx_prod;
5923         base_flags = 0;
5924         if (skb->ip_summed == CHECKSUM_PARTIAL)
5925                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5926
5927         mss = skb_shinfo(skb)->gso_size;
5928         if (mss) {
5929                 struct iphdr *iph;
5930                 u32 tcp_opt_len, hdr_len;
5931
5932                 if (skb_header_cloned(skb) &&
5933                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5934                         dev_kfree_skb(skb);
5935                         goto out_unlock;
5936                 }
5937
5938                 iph = ip_hdr(skb);
5939                 tcp_opt_len = tcp_optlen(skb);
5940
5941                 if (skb_is_gso_v6(skb)) {
5942                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5943                 } else {
5944                         u32 ip_tcp_len;
5945
5946                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5947                         hdr_len = ip_tcp_len + tcp_opt_len;
5948
5949                         iph->check = 0;
5950                         iph->tot_len = htons(mss + hdr_len);
5951                 }
5952
5953                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5954                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5955                         return tg3_tso_bug(tp, skb);
5956
5957                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5958                                TXD_FLAG_CPU_POST_DMA);
5959
5960                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5961                         tcp_hdr(skb)->check = 0;
5962                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5963                 } else
5964                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5965                                                                  iph->daddr, 0,
5966                                                                  IPPROTO_TCP,
5967                                                                  0);
5968
5969                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5970                         mss |= (hdr_len & 0xc) << 12;
5971                         if (hdr_len & 0x10)
5972                                 base_flags |= 0x00000010;
5973                         base_flags |= (hdr_len & 0x3e0) << 5;
5974                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5975                         mss |= hdr_len << 9;
5976                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5977                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5978                         if (tcp_opt_len || iph->ihl > 5) {
5979                                 int tsflags;
5980
5981                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5982                                 mss |= (tsflags << 11);
5983                         }
5984                 } else {
5985                         if (tcp_opt_len || iph->ihl > 5) {
5986                                 int tsflags;
5987
5988                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5989                                 base_flags |= tsflags << 12;
5990                         }
5991                 }
5992         }
5993 #if TG3_VLAN_TAG_USED
5994         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5995                 base_flags |= (TXD_FLAG_VLAN |
5996                                (vlan_tx_tag_get(skb) << 16));
5997 #endif
5998
5999         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
6000             !mss && skb->len > ETH_DATA_LEN)
6001                 base_flags |= TXD_FLAG_JMB_PKT;
6002
6003         len = skb_headlen(skb);
6004
6005         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
6006         if (pci_dma_mapping_error(tp->pdev, mapping)) {
6007                 dev_kfree_skb(skb);
6008                 goto out_unlock;
6009         }
6010
6011         tnapi->tx_buffers[entry].skb = skb;
6012         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
6013
6014         would_hit_hwbug = 0;
6015
6016         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
6017                 would_hit_hwbug = 1;
6018
6019         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6020             tg3_4g_overflow_test(mapping, len))
6021                 would_hit_hwbug = 1;
6022
6023         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6024             tg3_40bit_overflow_test(tp, mapping, len))
6025                 would_hit_hwbug = 1;
6026
6027         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
6028                 would_hit_hwbug = 1;
6029
6030         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
6031                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
6032
6033         entry = NEXT_TX(entry);
6034
6035         /* Now loop through additional data fragments, and queue them. */
6036         if (skb_shinfo(skb)->nr_frags > 0) {
6037                 last = skb_shinfo(skb)->nr_frags - 1;
6038                 for (i = 0; i <= last; i++) {
6039                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6040
6041                         len = frag->size;
6042                         mapping = pci_map_page(tp->pdev,
6043                                                frag->page,
6044                                                frag->page_offset,
6045                                                len, PCI_DMA_TODEVICE);
6046
6047                         tnapi->tx_buffers[entry].skb = NULL;
6048                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
6049                                            mapping);
6050                         if (pci_dma_mapping_error(tp->pdev, mapping))
6051                                 goto dma_error;
6052
6053                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
6054                             len <= 8)
6055                                 would_hit_hwbug = 1;
6056
6057                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
6058                             tg3_4g_overflow_test(mapping, len))
6059                                 would_hit_hwbug = 1;
6060
6061                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
6062                             tg3_40bit_overflow_test(tp, mapping, len))
6063                                 would_hit_hwbug = 1;
6064
6065                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6066                                 tg3_set_txd(tnapi, entry, mapping, len,
6067                                             base_flags, (i == last)|(mss << 1));
6068                         else
6069                                 tg3_set_txd(tnapi, entry, mapping, len,
6070                                             base_flags, (i == last));
6071
6072                         entry = NEXT_TX(entry);
6073                 }
6074         }
6075
6076         if (would_hit_hwbug) {
6077                 u32 last_plus_one = entry;
6078                 u32 start;
6079
6080                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
6081                 start &= (TG3_TX_RING_SIZE - 1);
6082
6083                 /* If the workaround fails due to memory/mapping
6084                  * failure, silently drop this packet.
6085                  */
6086                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
6087                                                 &start, base_flags, mss))
6088                         goto out_unlock;
6089
6090                 entry = start;
6091         }
6092
6093         /* Packets are ready, update Tx producer idx local and on card. */
6094         tw32_tx_mbox(tnapi->prodmbox, entry);
6095
6096         tnapi->tx_prod = entry;
6097         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
6098                 netif_tx_stop_queue(txq);
6099
6100                 /* netif_tx_stop_queue() must be done before checking
6101                  * checking tx index in tg3_tx_avail() below, because in
6102                  * tg3_tx(), we update tx index before checking for
6103                  * netif_tx_queue_stopped().
6104                  */
6105                 smp_mb();
6106                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
6107                         netif_tx_wake_queue(txq);
6108         }
6109
6110 out_unlock:
6111         mmiowb();
6112
6113         return NETDEV_TX_OK;
6114
6115 dma_error:
6116         last = i;
6117         entry = tnapi->tx_prod;
6118         tnapi->tx_buffers[entry].skb = NULL;
6119         pci_unmap_single(tp->pdev,
6120                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
6121                          skb_headlen(skb),
6122                          PCI_DMA_TODEVICE);
6123         for (i = 0; i <= last; i++) {
6124                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
6125                 entry = NEXT_TX(entry);
6126
6127                 pci_unmap_page(tp->pdev,
6128                                dma_unmap_addr(&tnapi->tx_buffers[entry],
6129                                               mapping),
6130                                frag->size, PCI_DMA_TODEVICE);
6131         }
6132
6133         dev_kfree_skb(skb);
6134         return NETDEV_TX_OK;
6135 }
6136
6137 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
6138                                int new_mtu)
6139 {
6140         dev->mtu = new_mtu;
6141
6142         if (new_mtu > ETH_DATA_LEN) {
6143                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6144                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6145                         ethtool_op_set_tso(dev, 0);
6146                 } else {
6147                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6148                 }
6149         } else {
6150                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6151                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6152                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6153         }
6154 }
6155
6156 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6157 {
6158         struct tg3 *tp = netdev_priv(dev);
6159         int err;
6160
6161         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6162                 return -EINVAL;
6163
6164         if (!netif_running(dev)) {
6165                 /* We'll just catch it later when the
6166                  * device is up'd.
6167                  */
6168                 tg3_set_mtu(dev, tp, new_mtu);
6169                 return 0;
6170         }
6171
6172         tg3_phy_stop(tp);
6173
6174         tg3_netif_stop(tp);
6175
6176         tg3_full_lock(tp, 1);
6177
6178         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6179
6180         tg3_set_mtu(dev, tp, new_mtu);
6181
6182         err = tg3_restart_hw(tp, 0);
6183
6184         if (!err)
6185                 tg3_netif_start(tp);
6186
6187         tg3_full_unlock(tp);
6188
6189         if (!err)
6190                 tg3_phy_start(tp);
6191
6192         return err;
6193 }
6194
6195 static void tg3_rx_prodring_free(struct tg3 *tp,
6196                                  struct tg3_rx_prodring_set *tpr)
6197 {
6198         int i;
6199
6200         if (tpr != &tp->napi[0].prodring) {
6201                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6202                      i = (i + 1) & tp->rx_std_ring_mask)
6203                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6204                                         tp->rx_pkt_map_sz);
6205
6206                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6207                         for (i = tpr->rx_jmb_cons_idx;
6208                              i != tpr->rx_jmb_prod_idx;
6209                              i = (i + 1) & tp->rx_jmb_ring_mask) {
6210                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6211                                                 TG3_RX_JMB_MAP_SZ);
6212                         }
6213                 }
6214
6215                 return;
6216         }
6217
6218         for (i = 0; i <= tp->rx_std_ring_mask; i++)
6219                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6220                                 tp->rx_pkt_map_sz);
6221
6222         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6223             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6224                 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
6225                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6226                                         TG3_RX_JMB_MAP_SZ);
6227         }
6228 }
6229
6230 /* Initialize rx rings for packet processing.
6231  *
6232  * The chip has been shut down and the driver detached from
6233  * the networking, so no interrupts or new tx packets will
6234  * end up in the driver.  tp->{tx,}lock are held and thus
6235  * we may not sleep.
6236  */
6237 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6238                                  struct tg3_rx_prodring_set *tpr)
6239 {
6240         u32 i, rx_pkt_dma_sz;
6241
6242         tpr->rx_std_cons_idx = 0;
6243         tpr->rx_std_prod_idx = 0;
6244         tpr->rx_jmb_cons_idx = 0;
6245         tpr->rx_jmb_prod_idx = 0;
6246
6247         if (tpr != &tp->napi[0].prodring) {
6248                 memset(&tpr->rx_std_buffers[0], 0,
6249                        TG3_RX_STD_BUFF_RING_SIZE(tp));
6250                 if (tpr->rx_jmb_buffers)
6251                         memset(&tpr->rx_jmb_buffers[0], 0,
6252                                TG3_RX_JMB_BUFF_RING_SIZE(tp));
6253                 goto done;
6254         }
6255
6256         /* Zero out all descriptors. */
6257         memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
6258
6259         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6260         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6261             tp->dev->mtu > ETH_DATA_LEN)
6262                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6263         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6264
6265         /* Initialize invariants of the rings, we only set this
6266          * stuff once.  This works because the card does not
6267          * write into the rx buffer posting rings.
6268          */
6269         for (i = 0; i <= tp->rx_std_ring_mask; i++) {
6270                 struct tg3_rx_buffer_desc *rxd;
6271
6272                 rxd = &tpr->rx_std[i];
6273                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6274                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6275                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6276                                (i << RXD_OPAQUE_INDEX_SHIFT));
6277         }
6278
6279         /* Now allocate fresh SKBs for each rx ring. */
6280         for (i = 0; i < tp->rx_pending; i++) {
6281                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6282                         netdev_warn(tp->dev,
6283                                     "Using a smaller RX standard ring. Only "
6284                                     "%d out of %d buffers were allocated "
6285                                     "successfully\n", i, tp->rx_pending);
6286                         if (i == 0)
6287                                 goto initfail;
6288                         tp->rx_pending = i;
6289                         break;
6290                 }
6291         }
6292
6293         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ||
6294             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6295                 goto done;
6296
6297         memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
6298
6299         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6300                 goto done;
6301
6302         for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
6303                 struct tg3_rx_buffer_desc *rxd;
6304
6305                 rxd = &tpr->rx_jmb[i].std;
6306                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6307                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6308                                   RXD_FLAG_JUMBO;
6309                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6310                        (i << RXD_OPAQUE_INDEX_SHIFT));
6311         }
6312
6313         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6314                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6315                         netdev_warn(tp->dev,
6316                                     "Using a smaller RX jumbo ring. Only %d "
6317                                     "out of %d buffers were allocated "
6318                                     "successfully\n", i, tp->rx_jumbo_pending);
6319                         if (i == 0)
6320                                 goto initfail;
6321                         tp->rx_jumbo_pending = i;
6322                         break;
6323                 }
6324         }
6325
6326 done:
6327         return 0;
6328
6329 initfail:
6330         tg3_rx_prodring_free(tp, tpr);
6331         return -ENOMEM;
6332 }
6333
6334 static void tg3_rx_prodring_fini(struct tg3 *tp,
6335                                  struct tg3_rx_prodring_set *tpr)
6336 {
6337         kfree(tpr->rx_std_buffers);
6338         tpr->rx_std_buffers = NULL;
6339         kfree(tpr->rx_jmb_buffers);
6340         tpr->rx_jmb_buffers = NULL;
6341         if (tpr->rx_std) {
6342                 pci_free_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6343                                     tpr->rx_std, tpr->rx_std_mapping);
6344                 tpr->rx_std = NULL;
6345         }
6346         if (tpr->rx_jmb) {
6347                 pci_free_consistent(tp->pdev, TG3_RX_JMB_RING_BYTES(tp),
6348                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6349                 tpr->rx_jmb = NULL;
6350         }
6351 }
6352
6353 static int tg3_rx_prodring_init(struct tg3 *tp,
6354                                 struct tg3_rx_prodring_set *tpr)
6355 {
6356         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
6357                                       GFP_KERNEL);
6358         if (!tpr->rx_std_buffers)
6359                 return -ENOMEM;
6360
6361         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_STD_RING_BYTES(tp),
6362                                            &tpr->rx_std_mapping);
6363         if (!tpr->rx_std)
6364                 goto err_out;
6365
6366         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
6367             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
6368                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
6369                                               GFP_KERNEL);
6370                 if (!tpr->rx_jmb_buffers)
6371                         goto err_out;
6372
6373                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6374                                                    TG3_RX_JMB_RING_BYTES(tp),
6375                                                    &tpr->rx_jmb_mapping);
6376                 if (!tpr->rx_jmb)
6377                         goto err_out;
6378         }
6379
6380         return 0;
6381
6382 err_out:
6383         tg3_rx_prodring_fini(tp, tpr);
6384         return -ENOMEM;
6385 }
6386
6387 /* Free up pending packets in all rx/tx rings.
6388  *
6389  * The chip has been shut down and the driver detached from
6390  * the networking, so no interrupts or new tx packets will
6391  * end up in the driver.  tp->{tx,}lock is not held and we are not
6392  * in an interrupt context and thus may sleep.
6393  */
6394 static void tg3_free_rings(struct tg3 *tp)
6395 {
6396         int i, j;
6397
6398         for (j = 0; j < tp->irq_cnt; j++) {
6399                 struct tg3_napi *tnapi = &tp->napi[j];
6400
6401                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6402
6403                 if (!tnapi->tx_buffers)
6404                         continue;
6405
6406                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6407                         struct ring_info *txp;
6408                         struct sk_buff *skb;
6409                         unsigned int k;
6410
6411                         txp = &tnapi->tx_buffers[i];
6412                         skb = txp->skb;
6413
6414                         if (skb == NULL) {
6415                                 i++;
6416                                 continue;
6417                         }
6418
6419                         pci_unmap_single(tp->pdev,
6420                                          dma_unmap_addr(txp, mapping),
6421                                          skb_headlen(skb),
6422                                          PCI_DMA_TODEVICE);
6423                         txp->skb = NULL;
6424
6425                         i++;
6426
6427                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6428                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6429                                 pci_unmap_page(tp->pdev,
6430                                                dma_unmap_addr(txp, mapping),
6431                                                skb_shinfo(skb)->frags[k].size,
6432                                                PCI_DMA_TODEVICE);
6433                                 i++;
6434                         }
6435
6436                         dev_kfree_skb_any(skb);
6437                 }
6438         }
6439 }
6440
6441 /* Initialize tx/rx rings for packet processing.
6442  *
6443  * The chip has been shut down and the driver detached from
6444  * the networking, so no interrupts or new tx packets will
6445  * end up in the driver.  tp->{tx,}lock are held and thus
6446  * we may not sleep.
6447  */
6448 static int tg3_init_rings(struct tg3 *tp)
6449 {
6450         int i;
6451
6452         /* Free up all the SKBs. */
6453         tg3_free_rings(tp);
6454
6455         for (i = 0; i < tp->irq_cnt; i++) {
6456                 struct tg3_napi *tnapi = &tp->napi[i];
6457
6458                 tnapi->last_tag = 0;
6459                 tnapi->last_irq_tag = 0;
6460                 tnapi->hw_status->status = 0;
6461                 tnapi->hw_status->status_tag = 0;
6462                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6463
6464                 tnapi->tx_prod = 0;
6465                 tnapi->tx_cons = 0;
6466                 if (tnapi->tx_ring)
6467                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6468
6469                 tnapi->rx_rcb_ptr = 0;
6470                 if (tnapi->rx_rcb)
6471                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6472
6473                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6474                         tg3_free_rings(tp);
6475                         return -ENOMEM;
6476                 }
6477         }
6478
6479         return 0;
6480 }
6481
6482 /*
6483  * Must not be invoked with interrupt sources disabled and
6484  * the hardware shutdown down.
6485  */
6486 static void tg3_free_consistent(struct tg3 *tp)
6487 {
6488         int i;
6489
6490         for (i = 0; i < tp->irq_cnt; i++) {
6491                 struct tg3_napi *tnapi = &tp->napi[i];
6492
6493                 if (tnapi->tx_ring) {
6494                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6495                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6496                         tnapi->tx_ring = NULL;
6497                 }
6498
6499                 kfree(tnapi->tx_buffers);
6500                 tnapi->tx_buffers = NULL;
6501
6502                 if (tnapi->rx_rcb) {
6503                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6504                                             tnapi->rx_rcb,
6505                                             tnapi->rx_rcb_mapping);
6506                         tnapi->rx_rcb = NULL;
6507                 }
6508
6509                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6510
6511                 if (tnapi->hw_status) {
6512                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6513                                             tnapi->hw_status,
6514                                             tnapi->status_mapping);
6515                         tnapi->hw_status = NULL;
6516                 }
6517         }
6518
6519         if (tp->hw_stats) {
6520                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6521                                     tp->hw_stats, tp->stats_mapping);
6522                 tp->hw_stats = NULL;
6523         }
6524 }
6525
6526 /*
6527  * Must not be invoked with interrupt sources disabled and
6528  * the hardware shutdown down.  Can sleep.
6529  */
6530 static int tg3_alloc_consistent(struct tg3 *tp)
6531 {
6532         int i;
6533
6534         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6535                                             sizeof(struct tg3_hw_stats),
6536                                             &tp->stats_mapping);
6537         if (!tp->hw_stats)
6538                 goto err_out;
6539
6540         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6541
6542         for (i = 0; i < tp->irq_cnt; i++) {
6543                 struct tg3_napi *tnapi = &tp->napi[i];
6544                 struct tg3_hw_status *sblk;
6545
6546                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6547                                                         TG3_HW_STATUS_SIZE,
6548                                                         &tnapi->status_mapping);
6549                 if (!tnapi->hw_status)
6550                         goto err_out;
6551
6552                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6553                 sblk = tnapi->hw_status;
6554
6555                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6556                         goto err_out;
6557
6558                 /* If multivector TSS is enabled, vector 0 does not handle
6559                  * tx interrupts.  Don't allocate any resources for it.
6560                  */
6561                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6562                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6563                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6564                                                     TG3_TX_RING_SIZE,
6565                                                     GFP_KERNEL);
6566                         if (!tnapi->tx_buffers)
6567                                 goto err_out;
6568
6569                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6570                                                               TG3_TX_RING_BYTES,
6571                                                        &tnapi->tx_desc_mapping);
6572                         if (!tnapi->tx_ring)
6573                                 goto err_out;
6574                 }
6575
6576                 /*
6577                  * When RSS is enabled, the status block format changes
6578                  * slightly.  The "rx_jumbo_consumer", "reserved",
6579                  * and "rx_mini_consumer" members get mapped to the
6580                  * other three rx return ring producer indexes.
6581                  */
6582                 switch (i) {
6583                 default:
6584                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6585                         break;
6586                 case 2:
6587                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6588                         break;
6589                 case 3:
6590                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6591                         break;
6592                 case 4:
6593                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6594                         break;
6595                 }
6596
6597                 /*
6598                  * If multivector RSS is enabled, vector 0 does not handle
6599                  * rx or tx interrupts.  Don't allocate any resources for it.
6600                  */
6601                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6602                         continue;
6603
6604                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6605                                                      TG3_RX_RCB_RING_BYTES(tp),
6606                                                      &tnapi->rx_rcb_mapping);
6607                 if (!tnapi->rx_rcb)
6608                         goto err_out;
6609
6610                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6611         }
6612
6613         return 0;
6614
6615 err_out:
6616         tg3_free_consistent(tp);
6617         return -ENOMEM;
6618 }
6619
6620 #define MAX_WAIT_CNT 1000
6621
6622 /* To stop a block, clear the enable bit and poll till it
6623  * clears.  tp->lock is held.
6624  */
6625 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6626 {
6627         unsigned int i;
6628         u32 val;
6629
6630         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6631                 switch (ofs) {
6632                 case RCVLSC_MODE:
6633                 case DMAC_MODE:
6634                 case MBFREE_MODE:
6635                 case BUFMGR_MODE:
6636                 case MEMARB_MODE:
6637                         /* We can't enable/disable these bits of the
6638                          * 5705/5750, just say success.
6639                          */
6640                         return 0;
6641
6642                 default:
6643                         break;
6644                 }
6645         }
6646
6647         val = tr32(ofs);
6648         val &= ~enable_bit;
6649         tw32_f(ofs, val);
6650
6651         for (i = 0; i < MAX_WAIT_CNT; i++) {
6652                 udelay(100);
6653                 val = tr32(ofs);
6654                 if ((val & enable_bit) == 0)
6655                         break;
6656         }
6657
6658         if (i == MAX_WAIT_CNT && !silent) {
6659                 dev_err(&tp->pdev->dev,
6660                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6661                         ofs, enable_bit);
6662                 return -ENODEV;
6663         }
6664
6665         return 0;
6666 }
6667
6668 /* tp->lock is held. */
6669 static int tg3_abort_hw(struct tg3 *tp, int silent)
6670 {
6671         int i, err;
6672
6673         tg3_disable_ints(tp);
6674
6675         tp->rx_mode &= ~RX_MODE_ENABLE;
6676         tw32_f(MAC_RX_MODE, tp->rx_mode);
6677         udelay(10);
6678
6679         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6680         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6681         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6682         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6683         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6684         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6685
6686         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6687         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6688         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6689         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6690         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6691         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6692         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6693
6694         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6695         tw32_f(MAC_MODE, tp->mac_mode);
6696         udelay(40);
6697
6698         tp->tx_mode &= ~TX_MODE_ENABLE;
6699         tw32_f(MAC_TX_MODE, tp->tx_mode);
6700
6701         for (i = 0; i < MAX_WAIT_CNT; i++) {
6702                 udelay(100);
6703                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6704                         break;
6705         }
6706         if (i >= MAX_WAIT_CNT) {
6707                 dev_err(&tp->pdev->dev,
6708                         "%s timed out, TX_MODE_ENABLE will not clear "
6709                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6710                 err |= -ENODEV;
6711         }
6712
6713         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6714         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6715         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6716
6717         tw32(FTQ_RESET, 0xffffffff);
6718         tw32(FTQ_RESET, 0x00000000);
6719
6720         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6721         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6722
6723         for (i = 0; i < tp->irq_cnt; i++) {
6724                 struct tg3_napi *tnapi = &tp->napi[i];
6725                 if (tnapi->hw_status)
6726                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6727         }
6728         if (tp->hw_stats)
6729                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6730
6731         return err;
6732 }
6733
6734 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6735 {
6736         int i;
6737         u32 apedata;
6738
6739         /* NCSI does not support APE events */
6740         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6741                 return;
6742
6743         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6744         if (apedata != APE_SEG_SIG_MAGIC)
6745                 return;
6746
6747         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6748         if (!(apedata & APE_FW_STATUS_READY))
6749                 return;
6750
6751         /* Wait for up to 1 millisecond for APE to service previous event. */
6752         for (i = 0; i < 10; i++) {
6753                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6754                         return;
6755
6756                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6757
6758                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6759                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6760                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6761
6762                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6763
6764                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6765                         break;
6766
6767                 udelay(100);
6768         }
6769
6770         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6771                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6772 }
6773
6774 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6775 {
6776         u32 event;
6777         u32 apedata;
6778
6779         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6780                 return;
6781
6782         switch (kind) {
6783         case RESET_KIND_INIT:
6784                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6785                                 APE_HOST_SEG_SIG_MAGIC);
6786                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6787                                 APE_HOST_SEG_LEN_MAGIC);
6788                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6789                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6790                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6791                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6792                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6793                                 APE_HOST_BEHAV_NO_PHYLOCK);
6794                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6795                                     TG3_APE_HOST_DRVR_STATE_START);
6796
6797                 event = APE_EVENT_STATUS_STATE_START;
6798                 break;
6799         case RESET_KIND_SHUTDOWN:
6800                 /* With the interface we are currently using,
6801                  * APE does not track driver state.  Wiping
6802                  * out the HOST SEGMENT SIGNATURE forces
6803                  * the APE to assume OS absent status.
6804                  */
6805                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6806
6807                 if (device_may_wakeup(&tp->pdev->dev) &&
6808                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6809                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6810                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6811                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6812                 } else
6813                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6814
6815                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6816
6817                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6818                 break;
6819         case RESET_KIND_SUSPEND:
6820                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6821                 break;
6822         default:
6823                 return;
6824         }
6825
6826         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6827
6828         tg3_ape_send_event(tp, event);
6829 }
6830
6831 /* tp->lock is held. */
6832 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6833 {
6834         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6835                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6836
6837         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6838                 switch (kind) {
6839                 case RESET_KIND_INIT:
6840                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6841                                       DRV_STATE_START);
6842                         break;
6843
6844                 case RESET_KIND_SHUTDOWN:
6845                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6846                                       DRV_STATE_UNLOAD);
6847                         break;
6848
6849                 case RESET_KIND_SUSPEND:
6850                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6851                                       DRV_STATE_SUSPEND);
6852                         break;
6853
6854                 default:
6855                         break;
6856                 }
6857         }
6858
6859         if (kind == RESET_KIND_INIT ||
6860             kind == RESET_KIND_SUSPEND)
6861                 tg3_ape_driver_state_change(tp, kind);
6862 }
6863
6864 /* tp->lock is held. */
6865 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6866 {
6867         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6868                 switch (kind) {
6869                 case RESET_KIND_INIT:
6870                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6871                                       DRV_STATE_START_DONE);
6872                         break;
6873
6874                 case RESET_KIND_SHUTDOWN:
6875                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6876                                       DRV_STATE_UNLOAD_DONE);
6877                         break;
6878
6879                 default:
6880                         break;
6881                 }
6882         }
6883
6884         if (kind == RESET_KIND_SHUTDOWN)
6885                 tg3_ape_driver_state_change(tp, kind);
6886 }
6887
6888 /* tp->lock is held. */
6889 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6890 {
6891         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6892                 switch (kind) {
6893                 case RESET_KIND_INIT:
6894                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6895                                       DRV_STATE_START);
6896                         break;
6897
6898                 case RESET_KIND_SHUTDOWN:
6899                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6900                                       DRV_STATE_UNLOAD);
6901                         break;
6902
6903                 case RESET_KIND_SUSPEND:
6904                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6905                                       DRV_STATE_SUSPEND);
6906                         break;
6907
6908                 default:
6909                         break;
6910                 }
6911         }
6912 }
6913
6914 static int tg3_poll_fw(struct tg3 *tp)
6915 {
6916         int i;
6917         u32 val;
6918
6919         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6920                 /* Wait up to 20ms for init done. */
6921                 for (i = 0; i < 200; i++) {
6922                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6923                                 return 0;
6924                         udelay(100);
6925                 }
6926                 return -ENODEV;
6927         }
6928
6929         /* Wait for firmware initialization to complete. */
6930         for (i = 0; i < 100000; i++) {
6931                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6932                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6933                         break;
6934                 udelay(10);
6935         }
6936
6937         /* Chip might not be fitted with firmware.  Some Sun onboard
6938          * parts are configured like that.  So don't signal the timeout
6939          * of the above loop as an error, but do report the lack of
6940          * running firmware once.
6941          */
6942         if (i >= 100000 &&
6943             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6944                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6945
6946                 netdev_info(tp->dev, "No firmware running\n");
6947         }
6948
6949         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6950                 /* The 57765 A0 needs a little more
6951                  * time to do some important work.
6952                  */
6953                 mdelay(10);
6954         }
6955
6956         return 0;
6957 }
6958
6959 /* Save PCI command register before chip reset */
6960 static void tg3_save_pci_state(struct tg3 *tp)
6961 {
6962         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6963 }
6964
6965 /* Restore PCI state after chip reset */
6966 static void tg3_restore_pci_state(struct tg3 *tp)
6967 {
6968         u32 val;
6969
6970         /* Re-enable indirect register accesses. */
6971         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6972                                tp->misc_host_ctrl);
6973
6974         /* Set MAX PCI retry to zero. */
6975         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6976         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6977             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6978                 val |= PCISTATE_RETRY_SAME_DMA;
6979         /* Allow reads and writes to the APE register and memory space. */
6980         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6981                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6982                        PCISTATE_ALLOW_APE_SHMEM_WR |
6983                        PCISTATE_ALLOW_APE_PSPACE_WR;
6984         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6985
6986         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6987
6988         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6989                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6990                         pcie_set_readrq(tp->pdev, 4096);
6991                 else {
6992                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6993                                               tp->pci_cacheline_sz);
6994                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6995                                               tp->pci_lat_timer);
6996                 }
6997         }
6998
6999         /* Make sure PCI-X relaxed ordering bit is clear. */
7000         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
7001                 u16 pcix_cmd;
7002
7003                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7004                                      &pcix_cmd);
7005                 pcix_cmd &= ~PCI_X_CMD_ERO;
7006                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
7007                                       pcix_cmd);
7008         }
7009
7010         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
7011
7012                 /* Chip reset on 5780 will reset MSI enable bit,
7013                  * so need to restore it.
7014                  */
7015                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7016                         u16 ctrl;
7017
7018                         pci_read_config_word(tp->pdev,
7019                                              tp->msi_cap + PCI_MSI_FLAGS,
7020                                              &ctrl);
7021                         pci_write_config_word(tp->pdev,
7022                                               tp->msi_cap + PCI_MSI_FLAGS,
7023                                               ctrl | PCI_MSI_FLAGS_ENABLE);
7024                         val = tr32(MSGINT_MODE);
7025                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
7026                 }
7027         }
7028 }
7029
7030 static void tg3_stop_fw(struct tg3 *);
7031
7032 /* tp->lock is held. */
7033 static int tg3_chip_reset(struct tg3 *tp)
7034 {
7035         u32 val;
7036         void (*write_op)(struct tg3 *, u32, u32);
7037         int i, err;
7038
7039         tg3_nvram_lock(tp);
7040
7041         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
7042
7043         /* No matching tg3_nvram_unlock() after this because
7044          * chip reset below will undo the nvram lock.
7045          */
7046         tp->nvram_lock_cnt = 0;
7047
7048         /* GRC_MISC_CFG core clock reset will clear the memory
7049          * enable bit in PCI register 4 and the MSI enable bit
7050          * on some chips, so we save relevant registers here.
7051          */
7052         tg3_save_pci_state(tp);
7053
7054         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
7055             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7056                 tw32(GRC_FASTBOOT_PC, 0);
7057
7058         /*
7059          * We must avoid the readl() that normally takes place.
7060          * It locks machines, causes machine checks, and other
7061          * fun things.  So, temporarily disable the 5701
7062          * hardware workaround, while we do the reset.
7063          */
7064         write_op = tp->write32;
7065         if (write_op == tg3_write_flush_reg32)
7066                 tp->write32 = tg3_write32;
7067
7068         /* Prevent the irq handler from reading or writing PCI registers
7069          * during chip reset when the memory enable bit in the PCI command
7070          * register may be cleared.  The chip does not generate interrupt
7071          * at this time, but the irq handler may still be called due to irq
7072          * sharing or irqpoll.
7073          */
7074         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
7075         for (i = 0; i < tp->irq_cnt; i++) {
7076                 struct tg3_napi *tnapi = &tp->napi[i];
7077                 if (tnapi->hw_status) {
7078                         tnapi->hw_status->status = 0;
7079                         tnapi->hw_status->status_tag = 0;
7080                 }
7081                 tnapi->last_tag = 0;
7082                 tnapi->last_irq_tag = 0;
7083         }
7084         smp_mb();
7085
7086         for (i = 0; i < tp->irq_cnt; i++)
7087                 synchronize_irq(tp->napi[i].irq_vec);
7088
7089         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7090                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7091                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7092         }
7093
7094         /* do the reset */
7095         val = GRC_MISC_CFG_CORECLK_RESET;
7096
7097         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
7098                 /* Force PCIe 1.0a mode */
7099                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7100                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
7101                     tr32(TG3_PCIE_PHY_TSTCTL) ==
7102                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
7103                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
7104
7105                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
7106                         tw32(GRC_MISC_CFG, (1 << 29));
7107                         val |= (1 << 29);
7108                 }
7109         }
7110
7111         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7112                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
7113                 tw32(GRC_VCPU_EXT_CTRL,
7114                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
7115         }
7116
7117         /* Manage gphy power for all CPMU absent PCIe devices. */
7118         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7119             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7120                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
7121
7122         tw32(GRC_MISC_CFG, val);
7123
7124         /* restore 5701 hardware bug workaround write method */
7125         tp->write32 = write_op;
7126
7127         /* Unfortunately, we have to delay before the PCI read back.
7128          * Some 575X chips even will not respond to a PCI cfg access
7129          * when the reset command is given to the chip.
7130          *
7131          * How do these hardware designers expect things to work
7132          * properly if the PCI write is posted for a long period
7133          * of time?  It is always necessary to have some method by
7134          * which a register read back can occur to push the write
7135          * out which does the reset.
7136          *
7137          * For most tg3 variants the trick below was working.
7138          * Ho hum...
7139          */
7140         udelay(120);
7141
7142         /* Flush PCI posted writes.  The normal MMIO registers
7143          * are inaccessible at this time so this is the only
7144          * way to make this reliably (actually, this is no longer
7145          * the case, see above).  I tried to use indirect
7146          * register read/write but this upset some 5701 variants.
7147          */
7148         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7149
7150         udelay(120);
7151
7152         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7153                 u16 val16;
7154
7155                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7156                         int i;
7157                         u32 cfg_val;
7158
7159                         /* Wait for link training to complete.  */
7160                         for (i = 0; i < 5000; i++)
7161                                 udelay(100);
7162
7163                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7164                         pci_write_config_dword(tp->pdev, 0xc4,
7165                                                cfg_val | (1 << 15));
7166                 }
7167
7168                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7169                 pci_read_config_word(tp->pdev,
7170                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7171                                      &val16);
7172                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7173                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7174                 /*
7175                  * Older PCIe devices only support the 128 byte
7176                  * MPS setting.  Enforce the restriction.
7177                  */
7178                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7179                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7180                 pci_write_config_word(tp->pdev,
7181                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7182                                       val16);
7183
7184                 pcie_set_readrq(tp->pdev, 4096);
7185
7186                 /* Clear error status */
7187                 pci_write_config_word(tp->pdev,
7188                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7189                                       PCI_EXP_DEVSTA_CED |
7190                                       PCI_EXP_DEVSTA_NFED |
7191                                       PCI_EXP_DEVSTA_FED |
7192                                       PCI_EXP_DEVSTA_URD);
7193         }
7194
7195         tg3_restore_pci_state(tp);
7196
7197         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7198
7199         val = 0;
7200         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7201                 val = tr32(MEMARB_MODE);
7202         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7203
7204         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7205                 tg3_stop_fw(tp);
7206                 tw32(0x5000, 0x400);
7207         }
7208
7209         tw32(GRC_MODE, tp->grc_mode);
7210
7211         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7212                 val = tr32(0xc4);
7213
7214                 tw32(0xc4, val | (1 << 15));
7215         }
7216
7217         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7218             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7219                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7220                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7221                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7222                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7223         }
7224
7225         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7226                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7227                 tw32_f(MAC_MODE, tp->mac_mode);
7228         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7229                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7230                 tw32_f(MAC_MODE, tp->mac_mode);
7231         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7232                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7233                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7234                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7235                 tw32_f(MAC_MODE, tp->mac_mode);
7236         } else
7237                 tw32_f(MAC_MODE, 0);
7238         udelay(40);
7239
7240         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7241
7242         err = tg3_poll_fw(tp);
7243         if (err)
7244                 return err;
7245
7246         tg3_mdio_start(tp);
7247
7248         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7249             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7250             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7251             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7252                 val = tr32(0x7c00);
7253
7254                 tw32(0x7c00, val | (1 << 25));
7255         }
7256
7257         /* Reprobe ASF enable state.  */
7258         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7259         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7260         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7261         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7262                 u32 nic_cfg;
7263
7264                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7265                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7266                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7267                         tp->last_event_jiffies = jiffies;
7268                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7269                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7270                 }
7271         }
7272
7273         return 0;
7274 }
7275
7276 /* tp->lock is held. */
7277 static void tg3_stop_fw(struct tg3 *tp)
7278 {
7279         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7280            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7281                 /* Wait for RX cpu to ACK the previous event. */
7282                 tg3_wait_for_event_ack(tp);
7283
7284                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7285
7286                 tg3_generate_fw_event(tp);
7287
7288                 /* Wait for RX cpu to ACK this event. */
7289                 tg3_wait_for_event_ack(tp);
7290         }
7291 }
7292
7293 /* tp->lock is held. */
7294 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7295 {
7296         int err;
7297
7298         tg3_stop_fw(tp);
7299
7300         tg3_write_sig_pre_reset(tp, kind);
7301
7302         tg3_abort_hw(tp, silent);
7303         err = tg3_chip_reset(tp);
7304
7305         __tg3_set_mac_addr(tp, 0);
7306
7307         tg3_write_sig_legacy(tp, kind);
7308         tg3_write_sig_post_reset(tp, kind);
7309
7310         if (err)
7311                 return err;
7312
7313         return 0;
7314 }
7315
7316 #define RX_CPU_SCRATCH_BASE     0x30000
7317 #define RX_CPU_SCRATCH_SIZE     0x04000
7318 #define TX_CPU_SCRATCH_BASE     0x34000
7319 #define TX_CPU_SCRATCH_SIZE     0x04000
7320
7321 /* tp->lock is held. */
7322 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7323 {
7324         int i;
7325
7326         BUG_ON(offset == TX_CPU_BASE &&
7327             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7328
7329         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7330                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7331
7332                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7333                 return 0;
7334         }
7335         if (offset == RX_CPU_BASE) {
7336                 for (i = 0; i < 10000; i++) {
7337                         tw32(offset + CPU_STATE, 0xffffffff);
7338                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7339                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7340                                 break;
7341                 }
7342
7343                 tw32(offset + CPU_STATE, 0xffffffff);
7344                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7345                 udelay(10);
7346         } else {
7347                 for (i = 0; i < 10000; i++) {
7348                         tw32(offset + CPU_STATE, 0xffffffff);
7349                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7350                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7351                                 break;
7352                 }
7353         }
7354
7355         if (i >= 10000) {
7356                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7357                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7358                 return -ENODEV;
7359         }
7360
7361         /* Clear firmware's nvram arbitration. */
7362         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7363                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7364         return 0;
7365 }
7366
7367 struct fw_info {
7368         unsigned int fw_base;
7369         unsigned int fw_len;
7370         const __be32 *fw_data;
7371 };
7372
7373 /* tp->lock is held. */
7374 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7375                                  int cpu_scratch_size, struct fw_info *info)
7376 {
7377         int err, lock_err, i;
7378         void (*write_op)(struct tg3 *, u32, u32);
7379
7380         if (cpu_base == TX_CPU_BASE &&
7381             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7382                 netdev_err(tp->dev,
7383                            "%s: Trying to load TX cpu firmware which is 5705\n",
7384                            __func__);
7385                 return -EINVAL;
7386         }
7387
7388         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7389                 write_op = tg3_write_mem;
7390         else
7391                 write_op = tg3_write_indirect_reg32;
7392
7393         /* It is possible that bootcode is still loading at this point.
7394          * Get the nvram lock first before halting the cpu.
7395          */
7396         lock_err = tg3_nvram_lock(tp);
7397         err = tg3_halt_cpu(tp, cpu_base);
7398         if (!lock_err)
7399                 tg3_nvram_unlock(tp);
7400         if (err)
7401                 goto out;
7402
7403         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7404                 write_op(tp, cpu_scratch_base + i, 0);
7405         tw32(cpu_base + CPU_STATE, 0xffffffff);
7406         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7407         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7408                 write_op(tp, (cpu_scratch_base +
7409                               (info->fw_base & 0xffff) +
7410                               (i * sizeof(u32))),
7411                               be32_to_cpu(info->fw_data[i]));
7412
7413         err = 0;
7414
7415 out:
7416         return err;
7417 }
7418
7419 /* tp->lock is held. */
7420 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7421 {
7422         struct fw_info info;
7423         const __be32 *fw_data;
7424         int err, i;
7425
7426         fw_data = (void *)tp->fw->data;
7427
7428         /* Firmware blob starts with version numbers, followed by
7429            start address and length. We are setting complete length.
7430            length = end_address_of_bss - start_address_of_text.
7431            Remainder is the blob to be loaded contiguously
7432            from start address. */
7433
7434         info.fw_base = be32_to_cpu(fw_data[1]);
7435         info.fw_len = tp->fw->size - 12;
7436         info.fw_data = &fw_data[3];
7437
7438         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7439                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7440                                     &info);
7441         if (err)
7442                 return err;
7443
7444         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7445                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7446                                     &info);
7447         if (err)
7448                 return err;
7449
7450         /* Now startup only the RX cpu. */
7451         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7452         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7453
7454         for (i = 0; i < 5; i++) {
7455                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7456                         break;
7457                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7458                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7459                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7460                 udelay(1000);
7461         }
7462         if (i >= 5) {
7463                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7464                            "should be %08x\n", __func__,
7465                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7466                 return -ENODEV;
7467         }
7468         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7469         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7470
7471         return 0;
7472 }
7473
7474 /* 5705 needs a special version of the TSO firmware.  */
7475
7476 /* tp->lock is held. */
7477 static int tg3_load_tso_firmware(struct tg3 *tp)
7478 {
7479         struct fw_info info;
7480         const __be32 *fw_data;
7481         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7482         int err, i;
7483
7484         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7485                 return 0;
7486
7487         fw_data = (void *)tp->fw->data;
7488
7489         /* Firmware blob starts with version numbers, followed by
7490            start address and length. We are setting complete length.
7491            length = end_address_of_bss - start_address_of_text.
7492            Remainder is the blob to be loaded contiguously
7493            from start address. */
7494
7495         info.fw_base = be32_to_cpu(fw_data[1]);
7496         cpu_scratch_size = tp->fw_len;
7497         info.fw_len = tp->fw->size - 12;
7498         info.fw_data = &fw_data[3];
7499
7500         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7501                 cpu_base = RX_CPU_BASE;
7502                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7503         } else {
7504                 cpu_base = TX_CPU_BASE;
7505                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7506                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7507         }
7508
7509         err = tg3_load_firmware_cpu(tp, cpu_base,
7510                                     cpu_scratch_base, cpu_scratch_size,
7511                                     &info);
7512         if (err)
7513                 return err;
7514
7515         /* Now startup the cpu. */
7516         tw32(cpu_base + CPU_STATE, 0xffffffff);
7517         tw32_f(cpu_base + CPU_PC, info.fw_base);
7518
7519         for (i = 0; i < 5; i++) {
7520                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7521                         break;
7522                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7523                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7524                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7525                 udelay(1000);
7526         }
7527         if (i >= 5) {
7528                 netdev_err(tp->dev,
7529                            "%s fails to set CPU PC, is %08x should be %08x\n",
7530                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7531                 return -ENODEV;
7532         }
7533         tw32(cpu_base + CPU_STATE, 0xffffffff);
7534         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7535         return 0;
7536 }
7537
7538
7539 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7540 {
7541         struct tg3 *tp = netdev_priv(dev);
7542         struct sockaddr *addr = p;
7543         int err = 0, skip_mac_1 = 0;
7544
7545         if (!is_valid_ether_addr(addr->sa_data))
7546                 return -EINVAL;
7547
7548         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7549
7550         if (!netif_running(dev))
7551                 return 0;
7552
7553         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7554                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7555
7556                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7557                 addr0_low = tr32(MAC_ADDR_0_LOW);
7558                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7559                 addr1_low = tr32(MAC_ADDR_1_LOW);
7560
7561                 /* Skip MAC addr 1 if ASF is using it. */
7562                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7563                     !(addr1_high == 0 && addr1_low == 0))
7564                         skip_mac_1 = 1;
7565         }
7566         spin_lock_bh(&tp->lock);
7567         __tg3_set_mac_addr(tp, skip_mac_1);
7568         spin_unlock_bh(&tp->lock);
7569
7570         return err;
7571 }
7572
7573 /* tp->lock is held. */
7574 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7575                            dma_addr_t mapping, u32 maxlen_flags,
7576                            u32 nic_addr)
7577 {
7578         tg3_write_mem(tp,
7579                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7580                       ((u64) mapping >> 32));
7581         tg3_write_mem(tp,
7582                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7583                       ((u64) mapping & 0xffffffff));
7584         tg3_write_mem(tp,
7585                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7586                        maxlen_flags);
7587
7588         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7589                 tg3_write_mem(tp,
7590                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7591                               nic_addr);
7592 }
7593
7594 static void __tg3_set_rx_mode(struct net_device *);
7595 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7596 {
7597         int i;
7598
7599         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7600                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7601                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7602                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7603         } else {
7604                 tw32(HOSTCC_TXCOL_TICKS, 0);
7605                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7606                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7607         }
7608
7609         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7610                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7611                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7612                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7613         } else {
7614                 tw32(HOSTCC_RXCOL_TICKS, 0);
7615                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7616                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7617         }
7618
7619         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7620                 u32 val = ec->stats_block_coalesce_usecs;
7621
7622                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7623                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7624
7625                 if (!netif_carrier_ok(tp->dev))
7626                         val = 0;
7627
7628                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7629         }
7630
7631         for (i = 0; i < tp->irq_cnt - 1; i++) {
7632                 u32 reg;
7633
7634                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7635                 tw32(reg, ec->rx_coalesce_usecs);
7636                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7637                 tw32(reg, ec->rx_max_coalesced_frames);
7638                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7639                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7640
7641                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7642                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7643                         tw32(reg, ec->tx_coalesce_usecs);
7644                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7645                         tw32(reg, ec->tx_max_coalesced_frames);
7646                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7647                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7648                 }
7649         }
7650
7651         for (; i < tp->irq_max - 1; i++) {
7652                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7653                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7654                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7655
7656                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7657                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7658                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7659                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7660                 }
7661         }
7662 }
7663
7664 /* tp->lock is held. */
7665 static void tg3_rings_reset(struct tg3 *tp)
7666 {
7667         int i;
7668         u32 stblk, txrcb, rxrcb, limit;
7669         struct tg3_napi *tnapi = &tp->napi[0];
7670
7671         /* Disable all transmit rings but the first. */
7672         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7673                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7674         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7675                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7676                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
7677         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7678                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7679         else
7680                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7681
7682         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7683              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7684                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7685                               BDINFO_FLAGS_DISABLED);
7686
7687
7688         /* Disable all receive return rings but the first. */
7689         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7690             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7691                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7692         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7693                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7694         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7695                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7696                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7697         else
7698                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7699
7700         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7701              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7702                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7703                               BDINFO_FLAGS_DISABLED);
7704
7705         /* Disable interrupts */
7706         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7707
7708         /* Zero mailbox registers. */
7709         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7710                 for (i = 1; i < tp->irq_max; i++) {
7711                         tp->napi[i].tx_prod = 0;
7712                         tp->napi[i].tx_cons = 0;
7713                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7714                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7715                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7716                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7717                 }
7718                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7719                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7720         } else {
7721                 tp->napi[0].tx_prod = 0;
7722                 tp->napi[0].tx_cons = 0;
7723                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7724                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7725         }
7726
7727         /* Make sure the NIC-based send BD rings are disabled. */
7728         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7729                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7730                 for (i = 0; i < 16; i++)
7731                         tw32_tx_mbox(mbox + i * 8, 0);
7732         }
7733
7734         txrcb = NIC_SRAM_SEND_RCB;
7735         rxrcb = NIC_SRAM_RCV_RET_RCB;
7736
7737         /* Clear status block in ram. */
7738         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7739
7740         /* Set status block DMA address */
7741         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7742              ((u64) tnapi->status_mapping >> 32));
7743         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7744              ((u64) tnapi->status_mapping & 0xffffffff));
7745
7746         if (tnapi->tx_ring) {
7747                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7748                                (TG3_TX_RING_SIZE <<
7749                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7750                                NIC_SRAM_TX_BUFFER_DESC);
7751                 txrcb += TG3_BDINFO_SIZE;
7752         }
7753
7754         if (tnapi->rx_rcb) {
7755                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7756                                (tp->rx_ret_ring_mask + 1) <<
7757                                 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
7758                 rxrcb += TG3_BDINFO_SIZE;
7759         }
7760
7761         stblk = HOSTCC_STATBLCK_RING1;
7762
7763         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7764                 u64 mapping = (u64)tnapi->status_mapping;
7765                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7766                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7767
7768                 /* Clear status block in ram. */
7769                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7770
7771                 if (tnapi->tx_ring) {
7772                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7773                                        (TG3_TX_RING_SIZE <<
7774                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7775                                        NIC_SRAM_TX_BUFFER_DESC);
7776                         txrcb += TG3_BDINFO_SIZE;
7777                 }
7778
7779                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7780                                ((tp->rx_ret_ring_mask + 1) <<
7781                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7782
7783                 stblk += 8;
7784                 rxrcb += TG3_BDINFO_SIZE;
7785         }
7786 }
7787
7788 /* tp->lock is held. */
7789 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7790 {
7791         u32 val, rdmac_mode;
7792         int i, err, limit;
7793         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7794
7795         tg3_disable_ints(tp);
7796
7797         tg3_stop_fw(tp);
7798
7799         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7800
7801         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7802                 tg3_abort_hw(tp, 1);
7803
7804         if (reset_phy)
7805                 tg3_phy_reset(tp);
7806
7807         err = tg3_chip_reset(tp);
7808         if (err)
7809                 return err;
7810
7811         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7812
7813         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7814                 val = tr32(TG3_CPMU_CTRL);
7815                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7816                 tw32(TG3_CPMU_CTRL, val);
7817
7818                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7819                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7820                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7821                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7822
7823                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7824                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7825                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7826                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7827
7828                 val = tr32(TG3_CPMU_HST_ACC);
7829                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7830                 val |= CPMU_HST_ACC_MACCLK_6_25;
7831                 tw32(TG3_CPMU_HST_ACC, val);
7832         }
7833
7834         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7835                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7836                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7837                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7838                 tw32(PCIE_PWR_MGMT_THRESH, val);
7839
7840                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7841                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7842
7843                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7844
7845                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7846                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7847         }
7848
7849         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7850                 u32 grc_mode = tr32(GRC_MODE);
7851
7852                 /* Access the lower 1K of PL PCIE block registers. */
7853                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7854                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7855
7856                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7857                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7858                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7859
7860                 tw32(GRC_MODE, grc_mode);
7861         }
7862
7863         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7864                 u32 grc_mode = tr32(GRC_MODE);
7865
7866                 /* Access the lower 1K of PL PCIE block registers. */
7867                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7868                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7869
7870                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7871                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7872                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7873
7874                 tw32(GRC_MODE, grc_mode);
7875
7876                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7877                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7878                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7879                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7880         }
7881
7882         /* Enable MAC control of LPI */
7883         if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) {
7884                 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL,
7885                        TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
7886                        TG3_CPMU_EEE_LNKIDL_UART_IDL);
7887
7888                 tw32_f(TG3_CPMU_EEE_CTRL,
7889                        TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
7890
7891                 tw32_f(TG3_CPMU_EEE_MODE,
7892                        TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
7893                        TG3_CPMU_EEEMD_LPI_IN_TX |
7894                        TG3_CPMU_EEEMD_LPI_IN_RX |
7895                        TG3_CPMU_EEEMD_EEE_ENABLE);
7896         }
7897
7898         /* This works around an issue with Athlon chipsets on
7899          * B3 tigon3 silicon.  This bit has no effect on any
7900          * other revision.  But do not set this on PCI Express
7901          * chips and don't even touch the clocks if the CPMU is present.
7902          */
7903         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7904                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7905                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7906                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7907         }
7908
7909         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7910             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7911                 val = tr32(TG3PCI_PCISTATE);
7912                 val |= PCISTATE_RETRY_SAME_DMA;
7913                 tw32(TG3PCI_PCISTATE, val);
7914         }
7915
7916         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7917                 /* Allow reads and writes to the
7918                  * APE register and memory space.
7919                  */
7920                 val = tr32(TG3PCI_PCISTATE);
7921                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7922                        PCISTATE_ALLOW_APE_SHMEM_WR |
7923                        PCISTATE_ALLOW_APE_PSPACE_WR;
7924                 tw32(TG3PCI_PCISTATE, val);
7925         }
7926
7927         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7928                 /* Enable some hw fixes.  */
7929                 val = tr32(TG3PCI_MSI_DATA);
7930                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7931                 tw32(TG3PCI_MSI_DATA, val);
7932         }
7933
7934         /* Descriptor ring init may make accesses to the
7935          * NIC SRAM area to setup the TX descriptors, so we
7936          * can only do this after the hardware has been
7937          * successfully reset.
7938          */
7939         err = tg3_init_rings(tp);
7940         if (err)
7941                 return err;
7942
7943         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7944                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7945                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7946                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7947                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7948                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7949         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7950                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7951                 /* This value is determined during the probe time DMA
7952                  * engine test, tg3_test_dma.
7953                  */
7954                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7955         }
7956
7957         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7958                           GRC_MODE_4X_NIC_SEND_RINGS |
7959                           GRC_MODE_NO_TX_PHDR_CSUM |
7960                           GRC_MODE_NO_RX_PHDR_CSUM);
7961         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7962
7963         /* Pseudo-header checksum is done by hardware logic and not
7964          * the offload processers, so make the chip do the pseudo-
7965          * header checksums on receive.  For transmit it is more
7966          * convenient to do the pseudo-header checksum in software
7967          * as Linux does that on transmit for us in all cases.
7968          */
7969         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7970
7971         tw32(GRC_MODE,
7972              tp->grc_mode |
7973              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7974
7975         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7976         val = tr32(GRC_MISC_CFG);
7977         val &= ~0xff;
7978         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7979         tw32(GRC_MISC_CFG, val);
7980
7981         /* Initialize MBUF/DESC pool. */
7982         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7983                 /* Do nothing.  */
7984         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7985                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7986                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7987                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7988                 else
7989                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7990                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7991                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7992         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7993                 int fw_len;
7994
7995                 fw_len = tp->fw_len;
7996                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7997                 tw32(BUFMGR_MB_POOL_ADDR,
7998                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7999                 tw32(BUFMGR_MB_POOL_SIZE,
8000                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
8001         }
8002
8003         if (tp->dev->mtu <= ETH_DATA_LEN) {
8004                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8005                      tp->bufmgr_config.mbuf_read_dma_low_water);
8006                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8007                      tp->bufmgr_config.mbuf_mac_rx_low_water);
8008                 tw32(BUFMGR_MB_HIGH_WATER,
8009                      tp->bufmgr_config.mbuf_high_water);
8010         } else {
8011                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
8012                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
8013                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
8014                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
8015                 tw32(BUFMGR_MB_HIGH_WATER,
8016                      tp->bufmgr_config.mbuf_high_water_jumbo);
8017         }
8018         tw32(BUFMGR_DMA_LOW_WATER,
8019              tp->bufmgr_config.dma_low_water);
8020         tw32(BUFMGR_DMA_HIGH_WATER,
8021              tp->bufmgr_config.dma_high_water);
8022
8023         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
8024         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8025                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
8026         tw32(BUFMGR_MODE, val);
8027         for (i = 0; i < 2000; i++) {
8028                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
8029                         break;
8030                 udelay(10);
8031         }
8032         if (i >= 2000) {
8033                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
8034                 return -ENODEV;
8035         }
8036
8037         /* Setup replenish threshold. */
8038         val = tp->rx_pending / 8;
8039         if (val == 0)
8040                 val = 1;
8041         else if (val > tp->rx_std_max_post)
8042                 val = tp->rx_std_max_post;
8043         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8044                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
8045                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
8046
8047                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
8048                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
8049         }
8050
8051         tw32(RCVBDI_STD_THRESH, val);
8052
8053         /* Initialize TG3_BDINFO's at:
8054          *  RCVDBDI_STD_BD:     standard eth size rx ring
8055          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
8056          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
8057          *
8058          * like so:
8059          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
8060          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
8061          *                              ring attribute flags
8062          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
8063          *
8064          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
8065          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
8066          *
8067          * The size of each ring is fixed in the firmware, but the location is
8068          * configurable.
8069          */
8070         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8071              ((u64) tpr->rx_std_mapping >> 32));
8072         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8073              ((u64) tpr->rx_std_mapping & 0xffffffff));
8074         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8075             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
8076                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
8077                      NIC_SRAM_RX_BUFFER_DESC);
8078
8079         /* Disable the mini ring */
8080         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8081                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
8082                      BDINFO_FLAGS_DISABLED);
8083
8084         /* Program the jumbo buffer descriptor ring control
8085          * blocks on those devices that have them.
8086          */
8087         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
8088             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8089                 /* Setup replenish threshold. */
8090                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
8091
8092                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
8093                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
8094                              ((u64) tpr->rx_jmb_mapping >> 32));
8095                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
8096                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
8097                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8098                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
8099                              BDINFO_FLAGS_USE_EXT_RECV);
8100                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
8101                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8102                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
8103                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
8104                 } else {
8105                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
8106                              BDINFO_FLAGS_DISABLED);
8107                 }
8108
8109                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8111                                 val = RX_STD_MAX_SIZE_5705;
8112                         else
8113                                 val = RX_STD_MAX_SIZE_5717;
8114                         val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
8115                         val |= (TG3_RX_STD_DMA_SZ << 2);
8116                 } else
8117                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
8118         } else
8119                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
8120
8121         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
8122
8123         tpr->rx_std_prod_idx = tp->rx_pending;
8124         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
8125
8126         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
8127                           tp->rx_jumbo_pending : 0;
8128         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
8129
8130         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
8131                 tw32(STD_REPLENISH_LWM, 32);
8132                 tw32(JMB_REPLENISH_LWM, 16);
8133         }
8134
8135         tg3_rings_reset(tp);
8136
8137         /* Initialize MAC address and backoff seed. */
8138         __tg3_set_mac_addr(tp, 0);
8139
8140         /* MTU + ethernet header + FCS + optional VLAN tag */
8141         tw32(MAC_RX_MTU_SIZE,
8142              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
8143
8144         /* The slot time is changed by tg3_setup_phy if we
8145          * run at gigabit with half duplex.
8146          */
8147         tw32(MAC_TX_LENGTHS,
8148              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
8149              (6 << TX_LENGTHS_IPG_SHIFT) |
8150              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
8151
8152         /* Receive rules. */
8153         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
8154         tw32(RCVLPC_CONFIG, 0x0181);
8155
8156         /* Calculate RDMAC_MODE setting early, we need it to determine
8157          * the RCVLPC_STATE_ENABLE mask.
8158          */
8159         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
8160                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
8161                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
8162                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
8163                       RDMAC_MODE_LNGREAD_ENAB);
8164
8165         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8166             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8167                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8168
8169         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8170             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8171             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8172                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8173                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8174                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8175
8176         /* If statement applies to 5705 and 5750 PCI devices only */
8177         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8178              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8179             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8180                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8181                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8182                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8183                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8184                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8185                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8186                 }
8187         }
8188
8189         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8190                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8191
8192         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8193                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8194
8195         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8196             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8197             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8198                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8199
8200         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8201             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8202             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8203             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8204             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8205                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8206                 tw32(TG3_RDMA_RSRVCTRL_REG,
8207                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8208         }
8209
8210         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8211                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8212                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8213                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8214                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8215         }
8216
8217         /* Receive/send statistics. */
8218         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8219                 val = tr32(RCVLPC_STATS_ENABLE);
8220                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8221                 tw32(RCVLPC_STATS_ENABLE, val);
8222         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8223                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8224                 val = tr32(RCVLPC_STATS_ENABLE);
8225                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8226                 tw32(RCVLPC_STATS_ENABLE, val);
8227         } else {
8228                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8229         }
8230         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8231         tw32(SNDDATAI_STATSENAB, 0xffffff);
8232         tw32(SNDDATAI_STATSCTRL,
8233              (SNDDATAI_SCTRL_ENABLE |
8234               SNDDATAI_SCTRL_FASTUPD));
8235
8236         /* Setup host coalescing engine. */
8237         tw32(HOSTCC_MODE, 0);
8238         for (i = 0; i < 2000; i++) {
8239                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8240                         break;
8241                 udelay(10);
8242         }
8243
8244         __tg3_set_coalesce(tp, &tp->coal);
8245
8246         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8247                 /* Status/statistics block address.  See tg3_timer,
8248                  * the tg3_periodic_fetch_stats call there, and
8249                  * tg3_get_stats to see how this works for 5705/5750 chips.
8250                  */
8251                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8252                      ((u64) tp->stats_mapping >> 32));
8253                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8254                      ((u64) tp->stats_mapping & 0xffffffff));
8255                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8256
8257                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8258
8259                 /* Clear statistics and status block memory areas */
8260                 for (i = NIC_SRAM_STATS_BLK;
8261                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8262                      i += sizeof(u32)) {
8263                         tg3_write_mem(tp, i, 0);
8264                         udelay(40);
8265                 }
8266         }
8267
8268         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8269
8270         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8271         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8272         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8273                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8274
8275         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8276                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8277                 /* reset to prevent losing 1st rx packet intermittently */
8278                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8279                 udelay(10);
8280         }
8281
8282         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8283                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8284         else
8285                 tp->mac_mode = 0;
8286         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8287                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8288         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8289             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8290             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8291                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8292         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8293         udelay(40);
8294
8295         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8296          * If TG3_FLG2_IS_NIC is zero, we should read the
8297          * register to preserve the GPIO settings for LOMs. The GPIOs,
8298          * whether used as inputs or outputs, are set by boot code after
8299          * reset.
8300          */
8301         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8302                 u32 gpio_mask;
8303
8304                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8305                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8306                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8307
8308                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8309                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8310                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8311
8312                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8313                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8314
8315                 tp->grc_local_ctrl &= ~gpio_mask;
8316                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8317
8318                 /* GPIO1 must be driven high for eeprom write protect */
8319                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8320                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8321                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8322         }
8323         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8324         udelay(100);
8325
8326         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8327                 val = tr32(MSGINT_MODE);
8328                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8329                 tw32(MSGINT_MODE, val);
8330         }
8331
8332         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8333                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8334                 udelay(40);
8335         }
8336
8337         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8338                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8339                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8340                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8341                WDMAC_MODE_LNGREAD_ENAB);
8342
8343         /* If statement applies to 5705 and 5750 PCI devices only */
8344         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8345              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8346             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8347                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8348                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8349                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8350                         /* nothing */
8351                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8352                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8353                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8354                         val |= WDMAC_MODE_RX_ACCEL;
8355                 }
8356         }
8357
8358         /* Enable host coalescing bug fix */
8359         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8360                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8361
8362         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8363                 val |= WDMAC_MODE_BURST_ALL_DATA;
8364
8365         tw32_f(WDMAC_MODE, val);
8366         udelay(40);
8367
8368         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8369                 u16 pcix_cmd;
8370
8371                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8372                                      &pcix_cmd);
8373                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8374                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8375                         pcix_cmd |= PCI_X_CMD_READ_2K;
8376                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8377                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8378                         pcix_cmd |= PCI_X_CMD_READ_2K;
8379                 }
8380                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8381                                       pcix_cmd);
8382         }
8383
8384         tw32_f(RDMAC_MODE, rdmac_mode);
8385         udelay(40);
8386
8387         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8388         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8389                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8390
8391         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8392                 tw32(SNDDATAC_MODE,
8393                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8394         else
8395                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8396
8397         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8398         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8399         val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
8400         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8401             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
8402                 val |= RCVDBDI_MODE_LRG_RING_SZ;
8403         tw32(RCVDBDI_MODE, val);
8404         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8405         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8406                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8407         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8408         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8409                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8410         tw32(SNDBDI_MODE, val);
8411         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8412
8413         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8414                 err = tg3_load_5701_a0_firmware_fix(tp);
8415                 if (err)
8416                         return err;
8417         }
8418
8419         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8420                 err = tg3_load_tso_firmware(tp);
8421                 if (err)
8422                         return err;
8423         }
8424
8425         tp->tx_mode = TX_MODE_ENABLE;
8426         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8427             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8428                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8429         tw32_f(MAC_TX_MODE, tp->tx_mode);
8430         udelay(100);
8431
8432         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8433                 u32 reg = MAC_RSS_INDIR_TBL_0;
8434                 u8 *ent = (u8 *)&val;
8435
8436                 /* Setup the indirection table */
8437                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8438                         int idx = i % sizeof(val);
8439
8440                         ent[idx] = i % (tp->irq_cnt - 1);
8441                         if (idx == sizeof(val) - 1) {
8442                                 tw32(reg, val);
8443                                 reg += 4;
8444                         }
8445                 }
8446
8447                 /* Setup the "secret" hash key. */
8448                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8449                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8450                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8451                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8452                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8453                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8454                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8455                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8456                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8457                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8458         }
8459
8460         tp->rx_mode = RX_MODE_ENABLE;
8461         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8462                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8463
8464         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8465                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8466                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8467                                RX_MODE_RSS_IPV6_HASH_EN |
8468                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8469                                RX_MODE_RSS_IPV4_HASH_EN |
8470                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8471
8472         tw32_f(MAC_RX_MODE, tp->rx_mode);
8473         udelay(10);
8474
8475         tw32(MAC_LED_CTRL, tp->led_ctrl);
8476
8477         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8478         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8479                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8480                 udelay(10);
8481         }
8482         tw32_f(MAC_RX_MODE, tp->rx_mode);
8483         udelay(10);
8484
8485         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8486                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8487                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8488                         /* Set drive transmission level to 1.2V  */
8489                         /* only if the signal pre-emphasis bit is not set  */
8490                         val = tr32(MAC_SERDES_CFG);
8491                         val &= 0xfffff000;
8492                         val |= 0x880;
8493                         tw32(MAC_SERDES_CFG, val);
8494                 }
8495                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8496                         tw32(MAC_SERDES_CFG, 0x616000);
8497         }
8498
8499         /* Prevent chip from dropping frames when flow control
8500          * is enabled.
8501          */
8502         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8503                 val = 1;
8504         else
8505                 val = 2;
8506         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8507
8508         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8509             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8510                 /* Use hardware link auto-negotiation */
8511                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8512         }
8513
8514         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8515             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8516                 u32 tmp;
8517
8518                 tmp = tr32(SERDES_RX_CTRL);
8519                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8520                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8521                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8522                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8523         }
8524
8525         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8526                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8527                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8528                         tp->link_config.speed = tp->link_config.orig_speed;
8529                         tp->link_config.duplex = tp->link_config.orig_duplex;
8530                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8531                 }
8532
8533                 err = tg3_setup_phy(tp, 0);
8534                 if (err)
8535                         return err;
8536
8537                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8538                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8539                         u32 tmp;
8540
8541                         /* Clear CRC stats. */
8542                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8543                                 tg3_writephy(tp, MII_TG3_TEST1,
8544                                              tmp | MII_TG3_TEST1_CRC_EN);
8545                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8546                         }
8547                 }
8548         }
8549
8550         __tg3_set_rx_mode(tp->dev);
8551
8552         /* Initialize receive rules. */
8553         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8554         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8555         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8556         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8557
8558         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8559             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8560                 limit = 8;
8561         else
8562                 limit = 16;
8563         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8564                 limit -= 4;
8565         switch (limit) {
8566         case 16:
8567                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8568         case 15:
8569                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8570         case 14:
8571                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8572         case 13:
8573                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8574         case 12:
8575                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8576         case 11:
8577                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8578         case 10:
8579                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8580         case 9:
8581                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8582         case 8:
8583                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8584         case 7:
8585                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8586         case 6:
8587                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8588         case 5:
8589                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8590         case 4:
8591                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8592         case 3:
8593                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8594         case 2:
8595         case 1:
8596
8597         default:
8598                 break;
8599         }
8600
8601         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8602                 /* Write our heartbeat update interval to APE. */
8603                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8604                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8605
8606         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8607
8608         return 0;
8609 }
8610
8611 /* Called at device open time to get the chip ready for
8612  * packet processing.  Invoked with tp->lock held.
8613  */
8614 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8615 {
8616         tg3_switch_clocks(tp);
8617
8618         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8619
8620         return tg3_reset_hw(tp, reset_phy);
8621 }
8622
8623 #define TG3_STAT_ADD32(PSTAT, REG) \
8624 do {    u32 __val = tr32(REG); \
8625         (PSTAT)->low += __val; \
8626         if ((PSTAT)->low < __val) \
8627                 (PSTAT)->high += 1; \
8628 } while (0)
8629
8630 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8631 {
8632         struct tg3_hw_stats *sp = tp->hw_stats;
8633
8634         if (!netif_carrier_ok(tp->dev))
8635                 return;
8636
8637         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8638         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8639         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8640         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8641         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8642         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8643         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8644         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8645         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8646         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8647         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8648         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8649         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8650
8651         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8652         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8653         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8654         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8655         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8656         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8657         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8658         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8659         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8660         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8661         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8662         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8663         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8664         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8665
8666         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8667         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8668         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8669 }
8670
8671 static void tg3_timer(unsigned long __opaque)
8672 {
8673         struct tg3 *tp = (struct tg3 *) __opaque;
8674
8675         if (tp->irq_sync)
8676                 goto restart_timer;
8677
8678         spin_lock(&tp->lock);
8679
8680         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8681                 /* All of this garbage is because when using non-tagged
8682                  * IRQ status the mailbox/status_block protocol the chip
8683                  * uses with the cpu is race prone.
8684                  */
8685                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8686                         tw32(GRC_LOCAL_CTRL,
8687                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8688                 } else {
8689                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8690                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8691                 }
8692
8693                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8694                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8695                         spin_unlock(&tp->lock);
8696                         schedule_work(&tp->reset_task);
8697                         return;
8698                 }
8699         }
8700
8701         /* This part only runs once per second. */
8702         if (!--tp->timer_counter) {
8703                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8704                         tg3_periodic_fetch_stats(tp);
8705
8706                 if (tp->setlpicnt && !--tp->setlpicnt) {
8707                         u32 val = tr32(TG3_CPMU_EEE_MODE);
8708                         tw32(TG3_CPMU_EEE_MODE,
8709                              val | TG3_CPMU_EEEMD_LPI_ENABLE);
8710                 }
8711
8712                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8713                         u32 mac_stat;
8714                         int phy_event;
8715
8716                         mac_stat = tr32(MAC_STATUS);
8717
8718                         phy_event = 0;
8719                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8720                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8721                                         phy_event = 1;
8722                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8723                                 phy_event = 1;
8724
8725                         if (phy_event)
8726                                 tg3_setup_phy(tp, 0);
8727                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8728                         u32 mac_stat = tr32(MAC_STATUS);
8729                         int need_setup = 0;
8730
8731                         if (netif_carrier_ok(tp->dev) &&
8732                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8733                                 need_setup = 1;
8734                         }
8735                         if (!netif_carrier_ok(tp->dev) &&
8736                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8737                                          MAC_STATUS_SIGNAL_DET))) {
8738                                 need_setup = 1;
8739                         }
8740                         if (need_setup) {
8741                                 if (!tp->serdes_counter) {
8742                                         tw32_f(MAC_MODE,
8743                                              (tp->mac_mode &
8744                                               ~MAC_MODE_PORT_MODE_MASK));
8745                                         udelay(40);
8746                                         tw32_f(MAC_MODE, tp->mac_mode);
8747                                         udelay(40);
8748                                 }
8749                                 tg3_setup_phy(tp, 0);
8750                         }
8751                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8752                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8753                         tg3_serdes_parallel_detect(tp);
8754                 }
8755
8756                 tp->timer_counter = tp->timer_multiplier;
8757         }
8758
8759         /* Heartbeat is only sent once every 2 seconds.
8760          *
8761          * The heartbeat is to tell the ASF firmware that the host
8762          * driver is still alive.  In the event that the OS crashes,
8763          * ASF needs to reset the hardware to free up the FIFO space
8764          * that may be filled with rx packets destined for the host.
8765          * If the FIFO is full, ASF will no longer function properly.
8766          *
8767          * Unintended resets have been reported on real time kernels
8768          * where the timer doesn't run on time.  Netpoll will also have
8769          * same problem.
8770          *
8771          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8772          * to check the ring condition when the heartbeat is expiring
8773          * before doing the reset.  This will prevent most unintended
8774          * resets.
8775          */
8776         if (!--tp->asf_counter) {
8777                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8778                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8779                         tg3_wait_for_event_ack(tp);
8780
8781                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8782                                       FWCMD_NICDRV_ALIVE3);
8783                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8784                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8785                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8786
8787                         tg3_generate_fw_event(tp);
8788                 }
8789                 tp->asf_counter = tp->asf_multiplier;
8790         }
8791
8792         spin_unlock(&tp->lock);
8793
8794 restart_timer:
8795         tp->timer.expires = jiffies + tp->timer_offset;
8796         add_timer(&tp->timer);
8797 }
8798
8799 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8800 {
8801         irq_handler_t fn;
8802         unsigned long flags;
8803         char *name;
8804         struct tg3_napi *tnapi = &tp->napi[irq_num];
8805
8806         if (tp->irq_cnt == 1)
8807                 name = tp->dev->name;
8808         else {
8809                 name = &tnapi->irq_lbl[0];
8810                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8811                 name[IFNAMSIZ-1] = 0;
8812         }
8813
8814         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8815                 fn = tg3_msi;
8816                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8817                         fn = tg3_msi_1shot;
8818                 flags = IRQF_SAMPLE_RANDOM;
8819         } else {
8820                 fn = tg3_interrupt;
8821                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8822                         fn = tg3_interrupt_tagged;
8823                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8824         }
8825
8826         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8827 }
8828
8829 static int tg3_test_interrupt(struct tg3 *tp)
8830 {
8831         struct tg3_napi *tnapi = &tp->napi[0];
8832         struct net_device *dev = tp->dev;
8833         int err, i, intr_ok = 0;
8834         u32 val;
8835
8836         if (!netif_running(dev))
8837                 return -ENODEV;
8838
8839         tg3_disable_ints(tp);
8840
8841         free_irq(tnapi->irq_vec, tnapi);
8842
8843         /*
8844          * Turn off MSI one shot mode.  Otherwise this test has no
8845          * observable way to know whether the interrupt was delivered.
8846          */
8847         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8848             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8849                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8850                 tw32(MSGINT_MODE, val);
8851         }
8852
8853         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8854                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8855         if (err)
8856                 return err;
8857
8858         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8859         tg3_enable_ints(tp);
8860
8861         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8862                tnapi->coal_now);
8863
8864         for (i = 0; i < 5; i++) {
8865                 u32 int_mbox, misc_host_ctrl;
8866
8867                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8868                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8869
8870                 if ((int_mbox != 0) ||
8871                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8872                         intr_ok = 1;
8873                         break;
8874                 }
8875
8876                 msleep(10);
8877         }
8878
8879         tg3_disable_ints(tp);
8880
8881         free_irq(tnapi->irq_vec, tnapi);
8882
8883         err = tg3_request_irq(tp, 0);
8884
8885         if (err)
8886                 return err;
8887
8888         if (intr_ok) {
8889                 /* Reenable MSI one shot mode. */
8890                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8891                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8892                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8893                         tw32(MSGINT_MODE, val);
8894                 }
8895                 return 0;
8896         }
8897
8898         return -EIO;
8899 }
8900
8901 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8902  * successfully restored
8903  */
8904 static int tg3_test_msi(struct tg3 *tp)
8905 {
8906         int err;
8907         u16 pci_cmd;
8908
8909         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8910                 return 0;
8911
8912         /* Turn off SERR reporting in case MSI terminates with Master
8913          * Abort.
8914          */
8915         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8916         pci_write_config_word(tp->pdev, PCI_COMMAND,
8917                               pci_cmd & ~PCI_COMMAND_SERR);
8918
8919         err = tg3_test_interrupt(tp);
8920
8921         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8922
8923         if (!err)
8924                 return 0;
8925
8926         /* other failures */
8927         if (err != -EIO)
8928                 return err;
8929
8930         /* MSI test failed, go back to INTx mode */
8931         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8932                     "to INTx mode. Please report this failure to the PCI "
8933                     "maintainer and include system chipset information\n");
8934
8935         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8936
8937         pci_disable_msi(tp->pdev);
8938
8939         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8940         tp->napi[0].irq_vec = tp->pdev->irq;
8941
8942         err = tg3_request_irq(tp, 0);
8943         if (err)
8944                 return err;
8945
8946         /* Need to reset the chip because the MSI cycle may have terminated
8947          * with Master Abort.
8948          */
8949         tg3_full_lock(tp, 1);
8950
8951         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8952         err = tg3_init_hw(tp, 1);
8953
8954         tg3_full_unlock(tp);
8955
8956         if (err)
8957                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8958
8959         return err;
8960 }
8961
8962 static int tg3_request_firmware(struct tg3 *tp)
8963 {
8964         const __be32 *fw_data;
8965
8966         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8967                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8968                            tp->fw_needed);
8969                 return -ENOENT;
8970         }
8971
8972         fw_data = (void *)tp->fw->data;
8973
8974         /* Firmware blob starts with version numbers, followed by
8975          * start address and _full_ length including BSS sections
8976          * (which must be longer than the actual data, of course
8977          */
8978
8979         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8980         if (tp->fw_len < (tp->fw->size - 12)) {
8981                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8982                            tp->fw_len, tp->fw_needed);
8983                 release_firmware(tp->fw);
8984                 tp->fw = NULL;
8985                 return -EINVAL;
8986         }
8987
8988         /* We no longer need firmware; we have it. */
8989         tp->fw_needed = NULL;
8990         return 0;
8991 }
8992
8993 static bool tg3_enable_msix(struct tg3 *tp)
8994 {
8995         int i, rc, cpus = num_online_cpus();
8996         struct msix_entry msix_ent[tp->irq_max];
8997
8998         if (cpus == 1)
8999                 /* Just fallback to the simpler MSI mode. */
9000                 return false;
9001
9002         /*
9003          * We want as many rx rings enabled as there are cpus.
9004          * The first MSIX vector only deals with link interrupts, etc,
9005          * so we add one to the number of vectors we are requesting.
9006          */
9007         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
9008
9009         for (i = 0; i < tp->irq_max; i++) {
9010                 msix_ent[i].entry  = i;
9011                 msix_ent[i].vector = 0;
9012         }
9013
9014         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
9015         if (rc < 0) {
9016                 return false;
9017         } else if (rc != 0) {
9018                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
9019                         return false;
9020                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
9021                               tp->irq_cnt, rc);
9022                 tp->irq_cnt = rc;
9023         }
9024
9025         for (i = 0; i < tp->irq_max; i++)
9026                 tp->napi[i].irq_vec = msix_ent[i].vector;
9027
9028         netif_set_real_num_tx_queues(tp->dev, 1);
9029         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
9030         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
9031                 pci_disable_msix(tp->pdev);
9032                 return false;
9033         }
9034         if (tp->irq_cnt > 1)
9035                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
9036
9037         return true;
9038 }
9039
9040 static void tg3_ints_init(struct tg3 *tp)
9041 {
9042         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
9043             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
9044                 /* All MSI supporting chips should support tagged
9045                  * status.  Assert that this is the case.
9046                  */
9047                 netdev_warn(tp->dev,
9048                             "MSI without TAGGED_STATUS? Not using MSI\n");
9049                 goto defcfg;
9050         }
9051
9052         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
9053                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
9054         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
9055                  pci_enable_msi(tp->pdev) == 0)
9056                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
9057
9058         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
9059                 u32 msi_mode = tr32(MSGINT_MODE);
9060                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9061                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
9062                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
9063         }
9064 defcfg:
9065         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
9066                 tp->irq_cnt = 1;
9067                 tp->napi[0].irq_vec = tp->pdev->irq;
9068                 netif_set_real_num_tx_queues(tp->dev, 1);
9069                 netif_set_real_num_rx_queues(tp->dev, 1);
9070         }
9071 }
9072
9073 static void tg3_ints_fini(struct tg3 *tp)
9074 {
9075         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
9076                 pci_disable_msix(tp->pdev);
9077         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
9078                 pci_disable_msi(tp->pdev);
9079         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
9080         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
9081 }
9082
9083 static int tg3_open(struct net_device *dev)
9084 {
9085         struct tg3 *tp = netdev_priv(dev);
9086         int i, err;
9087
9088         if (tp->fw_needed) {
9089                 err = tg3_request_firmware(tp);
9090                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
9091                         if (err)
9092                                 return err;
9093                 } else if (err) {
9094                         netdev_warn(tp->dev, "TSO capability disabled\n");
9095                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
9096                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9097                         netdev_notice(tp->dev, "TSO capability restored\n");
9098                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
9099                 }
9100         }
9101
9102         netif_carrier_off(tp->dev);
9103
9104         err = tg3_set_power_state(tp, PCI_D0);
9105         if (err)
9106                 return err;
9107
9108         tg3_full_lock(tp, 0);
9109
9110         tg3_disable_ints(tp);
9111         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9112
9113         tg3_full_unlock(tp);
9114
9115         /*
9116          * Setup interrupts first so we know how
9117          * many NAPI resources to allocate
9118          */
9119         tg3_ints_init(tp);
9120
9121         /* The placement of this call is tied
9122          * to the setup and use of Host TX descriptors.
9123          */
9124         err = tg3_alloc_consistent(tp);
9125         if (err)
9126                 goto err_out1;
9127
9128         tg3_napi_init(tp);
9129
9130         tg3_napi_enable(tp);
9131
9132         for (i = 0; i < tp->irq_cnt; i++) {
9133                 struct tg3_napi *tnapi = &tp->napi[i];
9134                 err = tg3_request_irq(tp, i);
9135                 if (err) {
9136                         for (i--; i >= 0; i--)
9137                                 free_irq(tnapi->irq_vec, tnapi);
9138                         break;
9139                 }
9140         }
9141
9142         if (err)
9143                 goto err_out2;
9144
9145         tg3_full_lock(tp, 0);
9146
9147         err = tg3_init_hw(tp, 1);
9148         if (err) {
9149                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9150                 tg3_free_rings(tp);
9151         } else {
9152                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
9153                         tp->timer_offset = HZ;
9154                 else
9155                         tp->timer_offset = HZ / 10;
9156
9157                 BUG_ON(tp->timer_offset > HZ);
9158                 tp->timer_counter = tp->timer_multiplier =
9159                         (HZ / tp->timer_offset);
9160                 tp->asf_counter = tp->asf_multiplier =
9161                         ((HZ / tp->timer_offset) * 2);
9162
9163                 init_timer(&tp->timer);
9164                 tp->timer.expires = jiffies + tp->timer_offset;
9165                 tp->timer.data = (unsigned long) tp;
9166                 tp->timer.function = tg3_timer;
9167         }
9168
9169         tg3_full_unlock(tp);
9170
9171         if (err)
9172                 goto err_out3;
9173
9174         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
9175                 err = tg3_test_msi(tp);
9176
9177                 if (err) {
9178                         tg3_full_lock(tp, 0);
9179                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9180                         tg3_free_rings(tp);
9181                         tg3_full_unlock(tp);
9182
9183                         goto err_out2;
9184                 }
9185
9186                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9187                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9188                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9189
9190                         tw32(PCIE_TRANSACTION_CFG,
9191                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9192                 }
9193         }
9194
9195         tg3_phy_start(tp);
9196
9197         tg3_full_lock(tp, 0);
9198
9199         add_timer(&tp->timer);
9200         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9201         tg3_enable_ints(tp);
9202
9203         tg3_full_unlock(tp);
9204
9205         netif_tx_start_all_queues(dev);
9206
9207         return 0;
9208
9209 err_out3:
9210         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9211                 struct tg3_napi *tnapi = &tp->napi[i];
9212                 free_irq(tnapi->irq_vec, tnapi);
9213         }
9214
9215 err_out2:
9216         tg3_napi_disable(tp);
9217         tg3_napi_fini(tp);
9218         tg3_free_consistent(tp);
9219
9220 err_out1:
9221         tg3_ints_fini(tp);
9222         return err;
9223 }
9224
9225 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9226                                                  struct rtnl_link_stats64 *);
9227 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9228
9229 static int tg3_close(struct net_device *dev)
9230 {
9231         int i;
9232         struct tg3 *tp = netdev_priv(dev);
9233
9234         tg3_napi_disable(tp);
9235         cancel_work_sync(&tp->reset_task);
9236
9237         netif_tx_stop_all_queues(dev);
9238
9239         del_timer_sync(&tp->timer);
9240
9241         tg3_phy_stop(tp);
9242
9243         tg3_full_lock(tp, 1);
9244
9245         tg3_disable_ints(tp);
9246
9247         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9248         tg3_free_rings(tp);
9249         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9250
9251         tg3_full_unlock(tp);
9252
9253         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9254                 struct tg3_napi *tnapi = &tp->napi[i];
9255                 free_irq(tnapi->irq_vec, tnapi);
9256         }
9257
9258         tg3_ints_fini(tp);
9259
9260         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9261
9262         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9263                sizeof(tp->estats_prev));
9264
9265         tg3_napi_fini(tp);
9266
9267         tg3_free_consistent(tp);
9268
9269         tg3_set_power_state(tp, PCI_D3hot);
9270
9271         netif_carrier_off(tp->dev);
9272
9273         return 0;
9274 }
9275
9276 static inline u64 get_stat64(tg3_stat64_t *val)
9277 {
9278        return ((u64)val->high << 32) | ((u64)val->low);
9279 }
9280
9281 static u64 calc_crc_errors(struct tg3 *tp)
9282 {
9283         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9284
9285         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9286             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9287              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9288                 u32 val;
9289
9290                 spin_lock_bh(&tp->lock);
9291                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9292                         tg3_writephy(tp, MII_TG3_TEST1,
9293                                      val | MII_TG3_TEST1_CRC_EN);
9294                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9295                 } else
9296                         val = 0;
9297                 spin_unlock_bh(&tp->lock);
9298
9299                 tp->phy_crc_errors += val;
9300
9301                 return tp->phy_crc_errors;
9302         }
9303
9304         return get_stat64(&hw_stats->rx_fcs_errors);
9305 }
9306
9307 #define ESTAT_ADD(member) \
9308         estats->member =        old_estats->member + \
9309                                 get_stat64(&hw_stats->member)
9310
9311 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9312 {
9313         struct tg3_ethtool_stats *estats = &tp->estats;
9314         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9315         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9316
9317         if (!hw_stats)
9318                 return old_estats;
9319
9320         ESTAT_ADD(rx_octets);
9321         ESTAT_ADD(rx_fragments);
9322         ESTAT_ADD(rx_ucast_packets);
9323         ESTAT_ADD(rx_mcast_packets);
9324         ESTAT_ADD(rx_bcast_packets);
9325         ESTAT_ADD(rx_fcs_errors);
9326         ESTAT_ADD(rx_align_errors);
9327         ESTAT_ADD(rx_xon_pause_rcvd);
9328         ESTAT_ADD(rx_xoff_pause_rcvd);
9329         ESTAT_ADD(rx_mac_ctrl_rcvd);
9330         ESTAT_ADD(rx_xoff_entered);
9331         ESTAT_ADD(rx_frame_too_long_errors);
9332         ESTAT_ADD(rx_jabbers);
9333         ESTAT_ADD(rx_undersize_packets);
9334         ESTAT_ADD(rx_in_length_errors);
9335         ESTAT_ADD(rx_out_length_errors);
9336         ESTAT_ADD(rx_64_or_less_octet_packets);
9337         ESTAT_ADD(rx_65_to_127_octet_packets);
9338         ESTAT_ADD(rx_128_to_255_octet_packets);
9339         ESTAT_ADD(rx_256_to_511_octet_packets);
9340         ESTAT_ADD(rx_512_to_1023_octet_packets);
9341         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9342         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9343         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9344         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9345         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9346
9347         ESTAT_ADD(tx_octets);
9348         ESTAT_ADD(tx_collisions);
9349         ESTAT_ADD(tx_xon_sent);
9350         ESTAT_ADD(tx_xoff_sent);
9351         ESTAT_ADD(tx_flow_control);
9352         ESTAT_ADD(tx_mac_errors);
9353         ESTAT_ADD(tx_single_collisions);
9354         ESTAT_ADD(tx_mult_collisions);
9355         ESTAT_ADD(tx_deferred);
9356         ESTAT_ADD(tx_excessive_collisions);
9357         ESTAT_ADD(tx_late_collisions);
9358         ESTAT_ADD(tx_collide_2times);
9359         ESTAT_ADD(tx_collide_3times);
9360         ESTAT_ADD(tx_collide_4times);
9361         ESTAT_ADD(tx_collide_5times);
9362         ESTAT_ADD(tx_collide_6times);
9363         ESTAT_ADD(tx_collide_7times);
9364         ESTAT_ADD(tx_collide_8times);
9365         ESTAT_ADD(tx_collide_9times);
9366         ESTAT_ADD(tx_collide_10times);
9367         ESTAT_ADD(tx_collide_11times);
9368         ESTAT_ADD(tx_collide_12times);
9369         ESTAT_ADD(tx_collide_13times);
9370         ESTAT_ADD(tx_collide_14times);
9371         ESTAT_ADD(tx_collide_15times);
9372         ESTAT_ADD(tx_ucast_packets);
9373         ESTAT_ADD(tx_mcast_packets);
9374         ESTAT_ADD(tx_bcast_packets);
9375         ESTAT_ADD(tx_carrier_sense_errors);
9376         ESTAT_ADD(tx_discards);
9377         ESTAT_ADD(tx_errors);
9378
9379         ESTAT_ADD(dma_writeq_full);
9380         ESTAT_ADD(dma_write_prioq_full);
9381         ESTAT_ADD(rxbds_empty);
9382         ESTAT_ADD(rx_discards);
9383         ESTAT_ADD(rx_errors);
9384         ESTAT_ADD(rx_threshold_hit);
9385
9386         ESTAT_ADD(dma_readq_full);
9387         ESTAT_ADD(dma_read_prioq_full);
9388         ESTAT_ADD(tx_comp_queue_full);
9389
9390         ESTAT_ADD(ring_set_send_prod_index);
9391         ESTAT_ADD(ring_status_update);
9392         ESTAT_ADD(nic_irqs);
9393         ESTAT_ADD(nic_avoided_irqs);
9394         ESTAT_ADD(nic_tx_threshold_hit);
9395
9396         return estats;
9397 }
9398
9399 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9400                                                  struct rtnl_link_stats64 *stats)
9401 {
9402         struct tg3 *tp = netdev_priv(dev);
9403         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9404         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9405
9406         if (!hw_stats)
9407                 return old_stats;
9408
9409         stats->rx_packets = old_stats->rx_packets +
9410                 get_stat64(&hw_stats->rx_ucast_packets) +
9411                 get_stat64(&hw_stats->rx_mcast_packets) +
9412                 get_stat64(&hw_stats->rx_bcast_packets);
9413
9414         stats->tx_packets = old_stats->tx_packets +
9415                 get_stat64(&hw_stats->tx_ucast_packets) +
9416                 get_stat64(&hw_stats->tx_mcast_packets) +
9417                 get_stat64(&hw_stats->tx_bcast_packets);
9418
9419         stats->rx_bytes = old_stats->rx_bytes +
9420                 get_stat64(&hw_stats->rx_octets);
9421         stats->tx_bytes = old_stats->tx_bytes +
9422                 get_stat64(&hw_stats->tx_octets);
9423
9424         stats->rx_errors = old_stats->rx_errors +
9425                 get_stat64(&hw_stats->rx_errors);
9426         stats->tx_errors = old_stats->tx_errors +
9427                 get_stat64(&hw_stats->tx_errors) +
9428                 get_stat64(&hw_stats->tx_mac_errors) +
9429                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9430                 get_stat64(&hw_stats->tx_discards);
9431
9432         stats->multicast = old_stats->multicast +
9433                 get_stat64(&hw_stats->rx_mcast_packets);
9434         stats->collisions = old_stats->collisions +
9435                 get_stat64(&hw_stats->tx_collisions);
9436
9437         stats->rx_length_errors = old_stats->rx_length_errors +
9438                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9439                 get_stat64(&hw_stats->rx_undersize_packets);
9440
9441         stats->rx_over_errors = old_stats->rx_over_errors +
9442                 get_stat64(&hw_stats->rxbds_empty);
9443         stats->rx_frame_errors = old_stats->rx_frame_errors +
9444                 get_stat64(&hw_stats->rx_align_errors);
9445         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9446                 get_stat64(&hw_stats->tx_discards);
9447         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9448                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9449
9450         stats->rx_crc_errors = old_stats->rx_crc_errors +
9451                 calc_crc_errors(tp);
9452
9453         stats->rx_missed_errors = old_stats->rx_missed_errors +
9454                 get_stat64(&hw_stats->rx_discards);
9455
9456         return stats;
9457 }
9458
9459 static inline u32 calc_crc(unsigned char *buf, int len)
9460 {
9461         u32 reg;
9462         u32 tmp;
9463         int j, k;
9464
9465         reg = 0xffffffff;
9466
9467         for (j = 0; j < len; j++) {
9468                 reg ^= buf[j];
9469
9470                 for (k = 0; k < 8; k++) {
9471                         tmp = reg & 0x01;
9472
9473                         reg >>= 1;
9474
9475                         if (tmp)
9476                                 reg ^= 0xedb88320;
9477                 }
9478         }
9479
9480         return ~reg;
9481 }
9482
9483 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9484 {
9485         /* accept or reject all multicast frames */
9486         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9487         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9488         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9489         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9490 }
9491
9492 static void __tg3_set_rx_mode(struct net_device *dev)
9493 {
9494         struct tg3 *tp = netdev_priv(dev);
9495         u32 rx_mode;
9496
9497         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9498                                   RX_MODE_KEEP_VLAN_TAG);
9499
9500         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9501          * flag clear.
9502          */
9503 #if TG3_VLAN_TAG_USED
9504         if (!tp->vlgrp &&
9505             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9506                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9507 #else
9508         /* By definition, VLAN is disabled always in this
9509          * case.
9510          */
9511         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9512                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9513 #endif
9514
9515         if (dev->flags & IFF_PROMISC) {
9516                 /* Promiscuous mode. */
9517                 rx_mode |= RX_MODE_PROMISC;
9518         } else if (dev->flags & IFF_ALLMULTI) {
9519                 /* Accept all multicast. */
9520                 tg3_set_multi(tp, 1);
9521         } else if (netdev_mc_empty(dev)) {
9522                 /* Reject all multicast. */
9523                 tg3_set_multi(tp, 0);
9524         } else {
9525                 /* Accept one or more multicast(s). */
9526                 struct netdev_hw_addr *ha;
9527                 u32 mc_filter[4] = { 0, };
9528                 u32 regidx;
9529                 u32 bit;
9530                 u32 crc;
9531
9532                 netdev_for_each_mc_addr(ha, dev) {
9533                         crc = calc_crc(ha->addr, ETH_ALEN);
9534                         bit = ~crc & 0x7f;
9535                         regidx = (bit & 0x60) >> 5;
9536                         bit &= 0x1f;
9537                         mc_filter[regidx] |= (1 << bit);
9538                 }
9539
9540                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9541                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9542                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9543                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9544         }
9545
9546         if (rx_mode != tp->rx_mode) {
9547                 tp->rx_mode = rx_mode;
9548                 tw32_f(MAC_RX_MODE, rx_mode);
9549                 udelay(10);
9550         }
9551 }
9552
9553 static void tg3_set_rx_mode(struct net_device *dev)
9554 {
9555         struct tg3 *tp = netdev_priv(dev);
9556
9557         if (!netif_running(dev))
9558                 return;
9559
9560         tg3_full_lock(tp, 0);
9561         __tg3_set_rx_mode(dev);
9562         tg3_full_unlock(tp);
9563 }
9564
9565 #define TG3_REGDUMP_LEN         (32 * 1024)
9566
9567 static int tg3_get_regs_len(struct net_device *dev)
9568 {
9569         return TG3_REGDUMP_LEN;
9570 }
9571
9572 static void tg3_get_regs(struct net_device *dev,
9573                 struct ethtool_regs *regs, void *_p)
9574 {
9575         u32 *p = _p;
9576         struct tg3 *tp = netdev_priv(dev);
9577         u8 *orig_p = _p;
9578         int i;
9579
9580         regs->version = 0;
9581
9582         memset(p, 0, TG3_REGDUMP_LEN);
9583
9584         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9585                 return;
9586
9587         tg3_full_lock(tp, 0);
9588
9589 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9590 #define GET_REG32_LOOP(base, len)               \
9591 do {    p = (u32 *)(orig_p + (base));           \
9592         for (i = 0; i < len; i += 4)            \
9593                 __GET_REG32((base) + i);        \
9594 } while (0)
9595 #define GET_REG32_1(reg)                        \
9596 do {    p = (u32 *)(orig_p + (reg));            \
9597         __GET_REG32((reg));                     \
9598 } while (0)
9599
9600         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9601         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9602         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9603         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9604         GET_REG32_1(SNDDATAC_MODE);
9605         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9606         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9607         GET_REG32_1(SNDBDC_MODE);
9608         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9609         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9610         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9611         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9612         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9613         GET_REG32_1(RCVDCC_MODE);
9614         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9615         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9616         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9617         GET_REG32_1(MBFREE_MODE);
9618         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9619         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9620         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9621         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9622         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9623         GET_REG32_1(RX_CPU_MODE);
9624         GET_REG32_1(RX_CPU_STATE);
9625         GET_REG32_1(RX_CPU_PGMCTR);
9626         GET_REG32_1(RX_CPU_HWBKPT);
9627         GET_REG32_1(TX_CPU_MODE);
9628         GET_REG32_1(TX_CPU_STATE);
9629         GET_REG32_1(TX_CPU_PGMCTR);
9630         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9631         GET_REG32_LOOP(FTQ_RESET, 0x120);
9632         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9633         GET_REG32_1(DMAC_MODE);
9634         GET_REG32_LOOP(GRC_MODE, 0x4c);
9635         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9636                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9637
9638 #undef __GET_REG32
9639 #undef GET_REG32_LOOP
9640 #undef GET_REG32_1
9641
9642         tg3_full_unlock(tp);
9643 }
9644
9645 static int tg3_get_eeprom_len(struct net_device *dev)
9646 {
9647         struct tg3 *tp = netdev_priv(dev);
9648
9649         return tp->nvram_size;
9650 }
9651
9652 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9653 {
9654         struct tg3 *tp = netdev_priv(dev);
9655         int ret;
9656         u8  *pd;
9657         u32 i, offset, len, b_offset, b_count;
9658         __be32 val;
9659
9660         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9661                 return -EINVAL;
9662
9663         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9664                 return -EAGAIN;
9665
9666         offset = eeprom->offset;
9667         len = eeprom->len;
9668         eeprom->len = 0;
9669
9670         eeprom->magic = TG3_EEPROM_MAGIC;
9671
9672         if (offset & 3) {
9673                 /* adjustments to start on required 4 byte boundary */
9674                 b_offset = offset & 3;
9675                 b_count = 4 - b_offset;
9676                 if (b_count > len) {
9677                         /* i.e. offset=1 len=2 */
9678                         b_count = len;
9679                 }
9680                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9681                 if (ret)
9682                         return ret;
9683                 memcpy(data, ((char *)&val) + b_offset, b_count);
9684                 len -= b_count;
9685                 offset += b_count;
9686                 eeprom->len += b_count;
9687         }
9688
9689         /* read bytes upto the last 4 byte boundary */
9690         pd = &data[eeprom->len];
9691         for (i = 0; i < (len - (len & 3)); i += 4) {
9692                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9693                 if (ret) {
9694                         eeprom->len += i;
9695                         return ret;
9696                 }
9697                 memcpy(pd + i, &val, 4);
9698         }
9699         eeprom->len += i;
9700
9701         if (len & 3) {
9702                 /* read last bytes not ending on 4 byte boundary */
9703                 pd = &data[eeprom->len];
9704                 b_count = len & 3;
9705                 b_offset = offset + len - b_count;
9706                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9707                 if (ret)
9708                         return ret;
9709                 memcpy(pd, &val, b_count);
9710                 eeprom->len += b_count;
9711         }
9712         return 0;
9713 }
9714
9715 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9716
9717 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9718 {
9719         struct tg3 *tp = netdev_priv(dev);
9720         int ret;
9721         u32 offset, len, b_offset, odd_len;
9722         u8 *buf;
9723         __be32 start, end;
9724
9725         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9726                 return -EAGAIN;
9727
9728         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9729             eeprom->magic != TG3_EEPROM_MAGIC)
9730                 return -EINVAL;
9731
9732         offset = eeprom->offset;
9733         len = eeprom->len;
9734
9735         if ((b_offset = (offset & 3))) {
9736                 /* adjustments to start on required 4 byte boundary */
9737                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9738                 if (ret)
9739                         return ret;
9740                 len += b_offset;
9741                 offset &= ~3;
9742                 if (len < 4)
9743                         len = 4;
9744         }
9745
9746         odd_len = 0;
9747         if (len & 3) {
9748                 /* adjustments to end on required 4 byte boundary */
9749                 odd_len = 1;
9750                 len = (len + 3) & ~3;
9751                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9752                 if (ret)
9753                         return ret;
9754         }
9755
9756         buf = data;
9757         if (b_offset || odd_len) {
9758                 buf = kmalloc(len, GFP_KERNEL);
9759                 if (!buf)
9760                         return -ENOMEM;
9761                 if (b_offset)
9762                         memcpy(buf, &start, 4);
9763                 if (odd_len)
9764                         memcpy(buf+len-4, &end, 4);
9765                 memcpy(buf + b_offset, data, eeprom->len);
9766         }
9767
9768         ret = tg3_nvram_write_block(tp, offset, len, buf);
9769
9770         if (buf != data)
9771                 kfree(buf);
9772
9773         return ret;
9774 }
9775
9776 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9777 {
9778         struct tg3 *tp = netdev_priv(dev);
9779
9780         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9781                 struct phy_device *phydev;
9782                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9783                         return -EAGAIN;
9784                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9785                 return phy_ethtool_gset(phydev, cmd);
9786         }
9787
9788         cmd->supported = (SUPPORTED_Autoneg);
9789
9790         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9791                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9792                                    SUPPORTED_1000baseT_Full);
9793
9794         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9795                 cmd->supported |= (SUPPORTED_100baseT_Half |
9796                                   SUPPORTED_100baseT_Full |
9797                                   SUPPORTED_10baseT_Half |
9798                                   SUPPORTED_10baseT_Full |
9799                                   SUPPORTED_TP);
9800                 cmd->port = PORT_TP;
9801         } else {
9802                 cmd->supported |= SUPPORTED_FIBRE;
9803                 cmd->port = PORT_FIBRE;
9804         }
9805
9806         cmd->advertising = tp->link_config.advertising;
9807         if (netif_running(dev)) {
9808                 cmd->speed = tp->link_config.active_speed;
9809                 cmd->duplex = tp->link_config.active_duplex;
9810         }
9811         cmd->phy_address = tp->phy_addr;
9812         cmd->transceiver = XCVR_INTERNAL;
9813         cmd->autoneg = tp->link_config.autoneg;
9814         cmd->maxtxpkt = 0;
9815         cmd->maxrxpkt = 0;
9816         return 0;
9817 }
9818
9819 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9820 {
9821         struct tg3 *tp = netdev_priv(dev);
9822
9823         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9824                 struct phy_device *phydev;
9825                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9826                         return -EAGAIN;
9827                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9828                 return phy_ethtool_sset(phydev, cmd);
9829         }
9830
9831         if (cmd->autoneg != AUTONEG_ENABLE &&
9832             cmd->autoneg != AUTONEG_DISABLE)
9833                 return -EINVAL;
9834
9835         if (cmd->autoneg == AUTONEG_DISABLE &&
9836             cmd->duplex != DUPLEX_FULL &&
9837             cmd->duplex != DUPLEX_HALF)
9838                 return -EINVAL;
9839
9840         if (cmd->autoneg == AUTONEG_ENABLE) {
9841                 u32 mask = ADVERTISED_Autoneg |
9842                            ADVERTISED_Pause |
9843                            ADVERTISED_Asym_Pause;
9844
9845                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9846                         mask |= ADVERTISED_1000baseT_Half |
9847                                 ADVERTISED_1000baseT_Full;
9848
9849                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9850                         mask |= ADVERTISED_100baseT_Half |
9851                                 ADVERTISED_100baseT_Full |
9852                                 ADVERTISED_10baseT_Half |
9853                                 ADVERTISED_10baseT_Full |
9854                                 ADVERTISED_TP;
9855                 else
9856                         mask |= ADVERTISED_FIBRE;
9857
9858                 if (cmd->advertising & ~mask)
9859                         return -EINVAL;
9860
9861                 mask &= (ADVERTISED_1000baseT_Half |
9862                          ADVERTISED_1000baseT_Full |
9863                          ADVERTISED_100baseT_Half |
9864                          ADVERTISED_100baseT_Full |
9865                          ADVERTISED_10baseT_Half |
9866                          ADVERTISED_10baseT_Full);
9867
9868                 cmd->advertising &= mask;
9869         } else {
9870                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9871                         if (cmd->speed != SPEED_1000)
9872                                 return -EINVAL;
9873
9874                         if (cmd->duplex != DUPLEX_FULL)
9875                                 return -EINVAL;
9876                 } else {
9877                         if (cmd->speed != SPEED_100 &&
9878                             cmd->speed != SPEED_10)
9879                                 return -EINVAL;
9880                 }
9881         }
9882
9883         tg3_full_lock(tp, 0);
9884
9885         tp->link_config.autoneg = cmd->autoneg;
9886         if (cmd->autoneg == AUTONEG_ENABLE) {
9887                 tp->link_config.advertising = (cmd->advertising |
9888                                               ADVERTISED_Autoneg);
9889                 tp->link_config.speed = SPEED_INVALID;
9890                 tp->link_config.duplex = DUPLEX_INVALID;
9891         } else {
9892                 tp->link_config.advertising = 0;
9893                 tp->link_config.speed = cmd->speed;
9894                 tp->link_config.duplex = cmd->duplex;
9895         }
9896
9897         tp->link_config.orig_speed = tp->link_config.speed;
9898         tp->link_config.orig_duplex = tp->link_config.duplex;
9899         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9900
9901         if (netif_running(dev))
9902                 tg3_setup_phy(tp, 1);
9903
9904         tg3_full_unlock(tp);
9905
9906         return 0;
9907 }
9908
9909 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9910 {
9911         struct tg3 *tp = netdev_priv(dev);
9912
9913         strcpy(info->driver, DRV_MODULE_NAME);
9914         strcpy(info->version, DRV_MODULE_VERSION);
9915         strcpy(info->fw_version, tp->fw_ver);
9916         strcpy(info->bus_info, pci_name(tp->pdev));
9917 }
9918
9919 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9920 {
9921         struct tg3 *tp = netdev_priv(dev);
9922
9923         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9924             device_can_wakeup(&tp->pdev->dev))
9925                 wol->supported = WAKE_MAGIC;
9926         else
9927                 wol->supported = 0;
9928         wol->wolopts = 0;
9929         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9930             device_can_wakeup(&tp->pdev->dev))
9931                 wol->wolopts = WAKE_MAGIC;
9932         memset(&wol->sopass, 0, sizeof(wol->sopass));
9933 }
9934
9935 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9936 {
9937         struct tg3 *tp = netdev_priv(dev);
9938         struct device *dp = &tp->pdev->dev;
9939
9940         if (wol->wolopts & ~WAKE_MAGIC)
9941                 return -EINVAL;
9942         if ((wol->wolopts & WAKE_MAGIC) &&
9943             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9944                 return -EINVAL;
9945
9946         spin_lock_bh(&tp->lock);
9947         if (wol->wolopts & WAKE_MAGIC) {
9948                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9949                 device_set_wakeup_enable(dp, true);
9950         } else {
9951                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9952                 device_set_wakeup_enable(dp, false);
9953         }
9954         spin_unlock_bh(&tp->lock);
9955
9956         return 0;
9957 }
9958
9959 static u32 tg3_get_msglevel(struct net_device *dev)
9960 {
9961         struct tg3 *tp = netdev_priv(dev);
9962         return tp->msg_enable;
9963 }
9964
9965 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9966 {
9967         struct tg3 *tp = netdev_priv(dev);
9968         tp->msg_enable = value;
9969 }
9970
9971 static int tg3_set_tso(struct net_device *dev, u32 value)
9972 {
9973         struct tg3 *tp = netdev_priv(dev);
9974
9975         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9976                 if (value)
9977                         return -EINVAL;
9978                 return 0;
9979         }
9980         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9981             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9982              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9983                 if (value) {
9984                         dev->features |= NETIF_F_TSO6;
9985                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9986                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9987                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9988                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9989                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9990                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9991                                 dev->features |= NETIF_F_TSO_ECN;
9992                 } else
9993                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9994         }
9995         return ethtool_op_set_tso(dev, value);
9996 }
9997
9998 static int tg3_nway_reset(struct net_device *dev)
9999 {
10000         struct tg3 *tp = netdev_priv(dev);
10001         int r;
10002
10003         if (!netif_running(dev))
10004                 return -EAGAIN;
10005
10006         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10007                 return -EINVAL;
10008
10009         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10010                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10011                         return -EAGAIN;
10012                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
10013         } else {
10014                 u32 bmcr;
10015
10016                 spin_lock_bh(&tp->lock);
10017                 r = -EINVAL;
10018                 tg3_readphy(tp, MII_BMCR, &bmcr);
10019                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
10020                     ((bmcr & BMCR_ANENABLE) ||
10021                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
10022                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
10023                                                    BMCR_ANENABLE);
10024                         r = 0;
10025                 }
10026                 spin_unlock_bh(&tp->lock);
10027         }
10028
10029         return r;
10030 }
10031
10032 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10033 {
10034         struct tg3 *tp = netdev_priv(dev);
10035
10036         ering->rx_max_pending = tp->rx_std_ring_mask;
10037         ering->rx_mini_max_pending = 0;
10038         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10039                 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
10040         else
10041                 ering->rx_jumbo_max_pending = 0;
10042
10043         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
10044
10045         ering->rx_pending = tp->rx_pending;
10046         ering->rx_mini_pending = 0;
10047         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
10048                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
10049         else
10050                 ering->rx_jumbo_pending = 0;
10051
10052         ering->tx_pending = tp->napi[0].tx_pending;
10053 }
10054
10055 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
10056 {
10057         struct tg3 *tp = netdev_priv(dev);
10058         int i, irq_sync = 0, err = 0;
10059
10060         if ((ering->rx_pending > tp->rx_std_ring_mask) ||
10061             (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
10062             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
10063             (ering->tx_pending <= MAX_SKB_FRAGS) ||
10064             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
10065              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
10066                 return -EINVAL;
10067
10068         if (netif_running(dev)) {
10069                 tg3_phy_stop(tp);
10070                 tg3_netif_stop(tp);
10071                 irq_sync = 1;
10072         }
10073
10074         tg3_full_lock(tp, irq_sync);
10075
10076         tp->rx_pending = ering->rx_pending;
10077
10078         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
10079             tp->rx_pending > 63)
10080                 tp->rx_pending = 63;
10081         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
10082
10083         for (i = 0; i < tp->irq_max; i++)
10084                 tp->napi[i].tx_pending = ering->tx_pending;
10085
10086         if (netif_running(dev)) {
10087                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10088                 err = tg3_restart_hw(tp, 1);
10089                 if (!err)
10090                         tg3_netif_start(tp);
10091         }
10092
10093         tg3_full_unlock(tp);
10094
10095         if (irq_sync && !err)
10096                 tg3_phy_start(tp);
10097
10098         return err;
10099 }
10100
10101 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10102 {
10103         struct tg3 *tp = netdev_priv(dev);
10104
10105         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10106
10107         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10108                 epause->rx_pause = 1;
10109         else
10110                 epause->rx_pause = 0;
10111
10112         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10113                 epause->tx_pause = 1;
10114         else
10115                 epause->tx_pause = 0;
10116 }
10117
10118 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10119 {
10120         struct tg3 *tp = netdev_priv(dev);
10121         int err = 0;
10122
10123         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10124                 u32 newadv;
10125                 struct phy_device *phydev;
10126
10127                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10128
10129                 if (!(phydev->supported & SUPPORTED_Pause) ||
10130                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
10131                      (epause->rx_pause != epause->tx_pause)))
10132                         return -EINVAL;
10133
10134                 tp->link_config.flowctrl = 0;
10135                 if (epause->rx_pause) {
10136                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10137
10138                         if (epause->tx_pause) {
10139                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10140                                 newadv = ADVERTISED_Pause;
10141                         } else
10142                                 newadv = ADVERTISED_Pause |
10143                                          ADVERTISED_Asym_Pause;
10144                 } else if (epause->tx_pause) {
10145                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10146                         newadv = ADVERTISED_Asym_Pause;
10147                 } else
10148                         newadv = 0;
10149
10150                 if (epause->autoneg)
10151                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10152                 else
10153                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10154
10155                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
10156                         u32 oldadv = phydev->advertising &
10157                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
10158                         if (oldadv != newadv) {
10159                                 phydev->advertising &=
10160                                         ~(ADVERTISED_Pause |
10161                                           ADVERTISED_Asym_Pause);
10162                                 phydev->advertising |= newadv;
10163                                 if (phydev->autoneg) {
10164                                         /*
10165                                          * Always renegotiate the link to
10166                                          * inform our link partner of our
10167                                          * flow control settings, even if the
10168                                          * flow control is forced.  Let
10169                                          * tg3_adjust_link() do the final
10170                                          * flow control setup.
10171                                          */
10172                                         return phy_start_aneg(phydev);
10173                                 }
10174                         }
10175
10176                         if (!epause->autoneg)
10177                                 tg3_setup_flow_control(tp, 0, 0);
10178                 } else {
10179                         tp->link_config.orig_advertising &=
10180                                         ~(ADVERTISED_Pause |
10181                                           ADVERTISED_Asym_Pause);
10182                         tp->link_config.orig_advertising |= newadv;
10183                 }
10184         } else {
10185                 int irq_sync = 0;
10186
10187                 if (netif_running(dev)) {
10188                         tg3_netif_stop(tp);
10189                         irq_sync = 1;
10190                 }
10191
10192                 tg3_full_lock(tp, irq_sync);
10193
10194                 if (epause->autoneg)
10195                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10196                 else
10197                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10198                 if (epause->rx_pause)
10199                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10200                 else
10201                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10202                 if (epause->tx_pause)
10203                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10204                 else
10205                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10206
10207                 if (netif_running(dev)) {
10208                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10209                         err = tg3_restart_hw(tp, 1);
10210                         if (!err)
10211                                 tg3_netif_start(tp);
10212                 }
10213
10214                 tg3_full_unlock(tp);
10215         }
10216
10217         return err;
10218 }
10219
10220 static u32 tg3_get_rx_csum(struct net_device *dev)
10221 {
10222         struct tg3 *tp = netdev_priv(dev);
10223         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10224 }
10225
10226 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10227 {
10228         struct tg3 *tp = netdev_priv(dev);
10229
10230         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10231                 if (data != 0)
10232                         return -EINVAL;
10233                 return 0;
10234         }
10235
10236         spin_lock_bh(&tp->lock);
10237         if (data)
10238                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10239         else
10240                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10241         spin_unlock_bh(&tp->lock);
10242
10243         return 0;
10244 }
10245
10246 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10247 {
10248         struct tg3 *tp = netdev_priv(dev);
10249
10250         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10251                 if (data != 0)
10252                         return -EINVAL;
10253                 return 0;
10254         }
10255
10256         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10257                 ethtool_op_set_tx_ipv6_csum(dev, data);
10258         else
10259                 ethtool_op_set_tx_csum(dev, data);
10260
10261         return 0;
10262 }
10263
10264 static int tg3_get_sset_count(struct net_device *dev, int sset)
10265 {
10266         switch (sset) {
10267         case ETH_SS_TEST:
10268                 return TG3_NUM_TEST;
10269         case ETH_SS_STATS:
10270                 return TG3_NUM_STATS;
10271         default:
10272                 return -EOPNOTSUPP;
10273         }
10274 }
10275
10276 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10277 {
10278         switch (stringset) {
10279         case ETH_SS_STATS:
10280                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10281                 break;
10282         case ETH_SS_TEST:
10283                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10284                 break;
10285         default:
10286                 WARN_ON(1);     /* we need a WARN() */
10287                 break;
10288         }
10289 }
10290
10291 static int tg3_phys_id(struct net_device *dev, u32 data)
10292 {
10293         struct tg3 *tp = netdev_priv(dev);
10294         int i;
10295
10296         if (!netif_running(tp->dev))
10297                 return -EAGAIN;
10298
10299         if (data == 0)
10300                 data = UINT_MAX / 2;
10301
10302         for (i = 0; i < (data * 2); i++) {
10303                 if ((i % 2) == 0)
10304                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10305                                            LED_CTRL_1000MBPS_ON |
10306                                            LED_CTRL_100MBPS_ON |
10307                                            LED_CTRL_10MBPS_ON |
10308                                            LED_CTRL_TRAFFIC_OVERRIDE |
10309                                            LED_CTRL_TRAFFIC_BLINK |
10310                                            LED_CTRL_TRAFFIC_LED);
10311
10312                 else
10313                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10314                                            LED_CTRL_TRAFFIC_OVERRIDE);
10315
10316                 if (msleep_interruptible(500))
10317                         break;
10318         }
10319         tw32(MAC_LED_CTRL, tp->led_ctrl);
10320         return 0;
10321 }
10322
10323 static void tg3_get_ethtool_stats(struct net_device *dev,
10324                                    struct ethtool_stats *estats, u64 *tmp_stats)
10325 {
10326         struct tg3 *tp = netdev_priv(dev);
10327         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10328 }
10329
10330 #define NVRAM_TEST_SIZE 0x100
10331 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10332 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10333 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10334 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10335 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10336
10337 static int tg3_test_nvram(struct tg3 *tp)
10338 {
10339         u32 csum, magic;
10340         __be32 *buf;
10341         int i, j, k, err = 0, size;
10342
10343         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10344                 return 0;
10345
10346         if (tg3_nvram_read(tp, 0, &magic) != 0)
10347                 return -EIO;
10348
10349         if (magic == TG3_EEPROM_MAGIC)
10350                 size = NVRAM_TEST_SIZE;
10351         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10352                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10353                     TG3_EEPROM_SB_FORMAT_1) {
10354                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10355                         case TG3_EEPROM_SB_REVISION_0:
10356                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10357                                 break;
10358                         case TG3_EEPROM_SB_REVISION_2:
10359                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10360                                 break;
10361                         case TG3_EEPROM_SB_REVISION_3:
10362                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10363                                 break;
10364                         default:
10365                                 return 0;
10366                         }
10367                 } else
10368                         return 0;
10369         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10370                 size = NVRAM_SELFBOOT_HW_SIZE;
10371         else
10372                 return -EIO;
10373
10374         buf = kmalloc(size, GFP_KERNEL);
10375         if (buf == NULL)
10376                 return -ENOMEM;
10377
10378         err = -EIO;
10379         for (i = 0, j = 0; i < size; i += 4, j++) {
10380                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10381                 if (err)
10382                         break;
10383         }
10384         if (i < size)
10385                 goto out;
10386
10387         /* Selfboot format */
10388         magic = be32_to_cpu(buf[0]);
10389         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10390             TG3_EEPROM_MAGIC_FW) {
10391                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10392
10393                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10394                     TG3_EEPROM_SB_REVISION_2) {
10395                         /* For rev 2, the csum doesn't include the MBA. */
10396                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10397                                 csum8 += buf8[i];
10398                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10399                                 csum8 += buf8[i];
10400                 } else {
10401                         for (i = 0; i < size; i++)
10402                                 csum8 += buf8[i];
10403                 }
10404
10405                 if (csum8 == 0) {
10406                         err = 0;
10407                         goto out;
10408                 }
10409
10410                 err = -EIO;
10411                 goto out;
10412         }
10413
10414         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10415             TG3_EEPROM_MAGIC_HW) {
10416                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10417                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10418                 u8 *buf8 = (u8 *) buf;
10419
10420                 /* Separate the parity bits and the data bytes.  */
10421                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10422                         if ((i == 0) || (i == 8)) {
10423                                 int l;
10424                                 u8 msk;
10425
10426                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10427                                         parity[k++] = buf8[i] & msk;
10428                                 i++;
10429                         } else if (i == 16) {
10430                                 int l;
10431                                 u8 msk;
10432
10433                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10434                                         parity[k++] = buf8[i] & msk;
10435                                 i++;
10436
10437                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10438                                         parity[k++] = buf8[i] & msk;
10439                                 i++;
10440                         }
10441                         data[j++] = buf8[i];
10442                 }
10443
10444                 err = -EIO;
10445                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10446                         u8 hw8 = hweight8(data[i]);
10447
10448                         if ((hw8 & 0x1) && parity[i])
10449                                 goto out;
10450                         else if (!(hw8 & 0x1) && !parity[i])
10451                                 goto out;
10452                 }
10453                 err = 0;
10454                 goto out;
10455         }
10456
10457         /* Bootstrap checksum at offset 0x10 */
10458         csum = calc_crc((unsigned char *) buf, 0x10);
10459         if (csum != be32_to_cpu(buf[0x10/4]))
10460                 goto out;
10461
10462         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10463         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10464         if (csum != be32_to_cpu(buf[0xfc/4]))
10465                 goto out;
10466
10467         err = 0;
10468
10469 out:
10470         kfree(buf);
10471         return err;
10472 }
10473
10474 #define TG3_SERDES_TIMEOUT_SEC  2
10475 #define TG3_COPPER_TIMEOUT_SEC  6
10476
10477 static int tg3_test_link(struct tg3 *tp)
10478 {
10479         int i, max;
10480
10481         if (!netif_running(tp->dev))
10482                 return -ENODEV;
10483
10484         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10485                 max = TG3_SERDES_TIMEOUT_SEC;
10486         else
10487                 max = TG3_COPPER_TIMEOUT_SEC;
10488
10489         for (i = 0; i < max; i++) {
10490                 if (netif_carrier_ok(tp->dev))
10491                         return 0;
10492
10493                 if (msleep_interruptible(1000))
10494                         break;
10495         }
10496
10497         return -EIO;
10498 }
10499
10500 /* Only test the commonly used registers */
10501 static int tg3_test_registers(struct tg3 *tp)
10502 {
10503         int i, is_5705, is_5750;
10504         u32 offset, read_mask, write_mask, val, save_val, read_val;
10505         static struct {
10506                 u16 offset;
10507                 u16 flags;
10508 #define TG3_FL_5705     0x1
10509 #define TG3_FL_NOT_5705 0x2
10510 #define TG3_FL_NOT_5788 0x4
10511 #define TG3_FL_NOT_5750 0x8
10512                 u32 read_mask;
10513                 u32 write_mask;
10514         } reg_tbl[] = {
10515                 /* MAC Control Registers */
10516                 { MAC_MODE, TG3_FL_NOT_5705,
10517                         0x00000000, 0x00ef6f8c },
10518                 { MAC_MODE, TG3_FL_5705,
10519                         0x00000000, 0x01ef6b8c },
10520                 { MAC_STATUS, TG3_FL_NOT_5705,
10521                         0x03800107, 0x00000000 },
10522                 { MAC_STATUS, TG3_FL_5705,
10523                         0x03800100, 0x00000000 },
10524                 { MAC_ADDR_0_HIGH, 0x0000,
10525                         0x00000000, 0x0000ffff },
10526                 { MAC_ADDR_0_LOW, 0x0000,
10527                         0x00000000, 0xffffffff },
10528                 { MAC_RX_MTU_SIZE, 0x0000,
10529                         0x00000000, 0x0000ffff },
10530                 { MAC_TX_MODE, 0x0000,
10531                         0x00000000, 0x00000070 },
10532                 { MAC_TX_LENGTHS, 0x0000,
10533                         0x00000000, 0x00003fff },
10534                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10535                         0x00000000, 0x000007fc },
10536                 { MAC_RX_MODE, TG3_FL_5705,
10537                         0x00000000, 0x000007dc },
10538                 { MAC_HASH_REG_0, 0x0000,
10539                         0x00000000, 0xffffffff },
10540                 { MAC_HASH_REG_1, 0x0000,
10541                         0x00000000, 0xffffffff },
10542                 { MAC_HASH_REG_2, 0x0000,
10543                         0x00000000, 0xffffffff },
10544                 { MAC_HASH_REG_3, 0x0000,
10545                         0x00000000, 0xffffffff },
10546
10547                 /* Receive Data and Receive BD Initiator Control Registers. */
10548                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10549                         0x00000000, 0xffffffff },
10550                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10551                         0x00000000, 0xffffffff },
10552                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10553                         0x00000000, 0x00000003 },
10554                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10555                         0x00000000, 0xffffffff },
10556                 { RCVDBDI_STD_BD+0, 0x0000,
10557                         0x00000000, 0xffffffff },
10558                 { RCVDBDI_STD_BD+4, 0x0000,
10559                         0x00000000, 0xffffffff },
10560                 { RCVDBDI_STD_BD+8, 0x0000,
10561                         0x00000000, 0xffff0002 },
10562                 { RCVDBDI_STD_BD+0xc, 0x0000,
10563                         0x00000000, 0xffffffff },
10564
10565                 /* Receive BD Initiator Control Registers. */
10566                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10567                         0x00000000, 0xffffffff },
10568                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10569                         0x00000000, 0x000003ff },
10570                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10571                         0x00000000, 0xffffffff },
10572
10573                 /* Host Coalescing Control Registers. */
10574                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10575                         0x00000000, 0x00000004 },
10576                 { HOSTCC_MODE, TG3_FL_5705,
10577                         0x00000000, 0x000000f6 },
10578                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10579                         0x00000000, 0xffffffff },
10580                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10581                         0x00000000, 0x000003ff },
10582                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10583                         0x00000000, 0xffffffff },
10584                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10585                         0x00000000, 0x000003ff },
10586                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10587                         0x00000000, 0xffffffff },
10588                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10589                         0x00000000, 0x000000ff },
10590                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10591                         0x00000000, 0xffffffff },
10592                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10593                         0x00000000, 0x000000ff },
10594                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10595                         0x00000000, 0xffffffff },
10596                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10597                         0x00000000, 0xffffffff },
10598                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10599                         0x00000000, 0xffffffff },
10600                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10601                         0x00000000, 0x000000ff },
10602                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10603                         0x00000000, 0xffffffff },
10604                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10605                         0x00000000, 0x000000ff },
10606                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10607                         0x00000000, 0xffffffff },
10608                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10609                         0x00000000, 0xffffffff },
10610                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10611                         0x00000000, 0xffffffff },
10612                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10613                         0x00000000, 0xffffffff },
10614                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10615                         0x00000000, 0xffffffff },
10616                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10617                         0xffffffff, 0x00000000 },
10618                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10619                         0xffffffff, 0x00000000 },
10620
10621                 /* Buffer Manager Control Registers. */
10622                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10623                         0x00000000, 0x007fff80 },
10624                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10625                         0x00000000, 0x007fffff },
10626                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10627                         0x00000000, 0x0000003f },
10628                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10629                         0x00000000, 0x000001ff },
10630                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10631                         0x00000000, 0x000001ff },
10632                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10633                         0xffffffff, 0x00000000 },
10634                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10635                         0xffffffff, 0x00000000 },
10636
10637                 /* Mailbox Registers */
10638                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10639                         0x00000000, 0x000001ff },
10640                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10641                         0x00000000, 0x000001ff },
10642                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10643                         0x00000000, 0x000007ff },
10644                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10645                         0x00000000, 0x000001ff },
10646
10647                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10648         };
10649
10650         is_5705 = is_5750 = 0;
10651         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10652                 is_5705 = 1;
10653                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10654                         is_5750 = 1;
10655         }
10656
10657         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10658                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10659                         continue;
10660
10661                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10662                         continue;
10663
10664                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10665                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10666                         continue;
10667
10668                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10669                         continue;
10670
10671                 offset = (u32) reg_tbl[i].offset;
10672                 read_mask = reg_tbl[i].read_mask;
10673                 write_mask = reg_tbl[i].write_mask;
10674
10675                 /* Save the original register content */
10676                 save_val = tr32(offset);
10677
10678                 /* Determine the read-only value. */
10679                 read_val = save_val & read_mask;
10680
10681                 /* Write zero to the register, then make sure the read-only bits
10682                  * are not changed and the read/write bits are all zeros.
10683                  */
10684                 tw32(offset, 0);
10685
10686                 val = tr32(offset);
10687
10688                 /* Test the read-only and read/write bits. */
10689                 if (((val & read_mask) != read_val) || (val & write_mask))
10690                         goto out;
10691
10692                 /* Write ones to all the bits defined by RdMask and WrMask, then
10693                  * make sure the read-only bits are not changed and the
10694                  * read/write bits are all ones.
10695                  */
10696                 tw32(offset, read_mask | write_mask);
10697
10698                 val = tr32(offset);
10699
10700                 /* Test the read-only bits. */
10701                 if ((val & read_mask) != read_val)
10702                         goto out;
10703
10704                 /* Test the read/write bits. */
10705                 if ((val & write_mask) != write_mask)
10706                         goto out;
10707
10708                 tw32(offset, save_val);
10709         }
10710
10711         return 0;
10712
10713 out:
10714         if (netif_msg_hw(tp))
10715                 netdev_err(tp->dev,
10716                            "Register test failed at offset %x\n", offset);
10717         tw32(offset, save_val);
10718         return -EIO;
10719 }
10720
10721 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10722 {
10723         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10724         int i;
10725         u32 j;
10726
10727         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10728                 for (j = 0; j < len; j += 4) {
10729                         u32 val;
10730
10731                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10732                         tg3_read_mem(tp, offset + j, &val);
10733                         if (val != test_pattern[i])
10734                                 return -EIO;
10735                 }
10736         }
10737         return 0;
10738 }
10739
10740 static int tg3_test_memory(struct tg3 *tp)
10741 {
10742         static struct mem_entry {
10743                 u32 offset;
10744                 u32 len;
10745         } mem_tbl_570x[] = {
10746                 { 0x00000000, 0x00b50},
10747                 { 0x00002000, 0x1c000},
10748                 { 0xffffffff, 0x00000}
10749         }, mem_tbl_5705[] = {
10750                 { 0x00000100, 0x0000c},
10751                 { 0x00000200, 0x00008},
10752                 { 0x00004000, 0x00800},
10753                 { 0x00006000, 0x01000},
10754                 { 0x00008000, 0x02000},
10755                 { 0x00010000, 0x0e000},
10756                 { 0xffffffff, 0x00000}
10757         }, mem_tbl_5755[] = {
10758                 { 0x00000200, 0x00008},
10759                 { 0x00004000, 0x00800},
10760                 { 0x00006000, 0x00800},
10761                 { 0x00008000, 0x02000},
10762                 { 0x00010000, 0x0c000},
10763                 { 0xffffffff, 0x00000}
10764         }, mem_tbl_5906[] = {
10765                 { 0x00000200, 0x00008},
10766                 { 0x00004000, 0x00400},
10767                 { 0x00006000, 0x00400},
10768                 { 0x00008000, 0x01000},
10769                 { 0x00010000, 0x01000},
10770                 { 0xffffffff, 0x00000}
10771         }, mem_tbl_5717[] = {
10772                 { 0x00000200, 0x00008},
10773                 { 0x00010000, 0x0a000},
10774                 { 0x00020000, 0x13c00},
10775                 { 0xffffffff, 0x00000}
10776         }, mem_tbl_57765[] = {
10777                 { 0x00000200, 0x00008},
10778                 { 0x00004000, 0x00800},
10779                 { 0x00006000, 0x09800},
10780                 { 0x00010000, 0x0a000},
10781                 { 0xffffffff, 0x00000}
10782         };
10783         struct mem_entry *mem_tbl;
10784         int err = 0;
10785         int i;
10786
10787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10788             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10789                 mem_tbl = mem_tbl_5717;
10790         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10791                 mem_tbl = mem_tbl_57765;
10792         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10793                 mem_tbl = mem_tbl_5755;
10794         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10795                 mem_tbl = mem_tbl_5906;
10796         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10797                 mem_tbl = mem_tbl_5705;
10798         else
10799                 mem_tbl = mem_tbl_570x;
10800
10801         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10802                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10803                 if (err)
10804                         break;
10805         }
10806
10807         return err;
10808 }
10809
10810 #define TG3_MAC_LOOPBACK        0
10811 #define TG3_PHY_LOOPBACK        1
10812
10813 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10814 {
10815         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10816         u32 desc_idx, coal_now;
10817         struct sk_buff *skb, *rx_skb;
10818         u8 *tx_data;
10819         dma_addr_t map;
10820         int num_pkts, tx_len, rx_len, i, err;
10821         struct tg3_rx_buffer_desc *desc;
10822         struct tg3_napi *tnapi, *rnapi;
10823         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10824
10825         tnapi = &tp->napi[0];
10826         rnapi = &tp->napi[0];
10827         if (tp->irq_cnt > 1) {
10828                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
10829                         rnapi = &tp->napi[1];
10830                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10831                         tnapi = &tp->napi[1];
10832         }
10833         coal_now = tnapi->coal_now | rnapi->coal_now;
10834
10835         if (loopback_mode == TG3_MAC_LOOPBACK) {
10836                 /* HW errata - mac loopback fails in some cases on 5780.
10837                  * Normal traffic and PHY loopback are not affected by
10838                  * errata.
10839                  */
10840                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10841                         return 0;
10842
10843                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10844                            MAC_MODE_PORT_INT_LPBACK;
10845                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10846                         mac_mode |= MAC_MODE_LINK_POLARITY;
10847                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10848                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10849                 else
10850                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10851                 tw32(MAC_MODE, mac_mode);
10852         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10853                 u32 val;
10854
10855                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10856                         tg3_phy_fet_toggle_apd(tp, false);
10857                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10858                 } else
10859                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10860
10861                 tg3_phy_toggle_automdix(tp, 0);
10862
10863                 tg3_writephy(tp, MII_BMCR, val);
10864                 udelay(40);
10865
10866                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10867                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10868                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10869                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10870                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10871                         /* The write needs to be flushed for the AC131 */
10872                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10873                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10874                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10875                 } else
10876                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10877
10878                 /* reset to prevent losing 1st rx packet intermittently */
10879                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10880                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10881                         udelay(10);
10882                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10883                 }
10884                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10885                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10886                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10887                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10888                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10889                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10890                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10891                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10892                 }
10893                 tw32(MAC_MODE, mac_mode);
10894         } else {
10895                 return -EINVAL;
10896         }
10897
10898         err = -EIO;
10899
10900         tx_len = 1514;
10901         skb = netdev_alloc_skb(tp->dev, tx_len);
10902         if (!skb)
10903                 return -ENOMEM;
10904
10905         tx_data = skb_put(skb, tx_len);
10906         memcpy(tx_data, tp->dev->dev_addr, 6);
10907         memset(tx_data + 6, 0x0, 8);
10908
10909         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10910
10911         for (i = 14; i < tx_len; i++)
10912                 tx_data[i] = (u8) (i & 0xff);
10913
10914         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10915         if (pci_dma_mapping_error(tp->pdev, map)) {
10916                 dev_kfree_skb(skb);
10917                 return -EIO;
10918         }
10919
10920         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10921                rnapi->coal_now);
10922
10923         udelay(10);
10924
10925         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10926
10927         num_pkts = 0;
10928
10929         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10930
10931         tnapi->tx_prod++;
10932         num_pkts++;
10933
10934         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10935         tr32_mailbox(tnapi->prodmbox);
10936
10937         udelay(10);
10938
10939         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10940         for (i = 0; i < 35; i++) {
10941                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10942                        coal_now);
10943
10944                 udelay(10);
10945
10946                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10947                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10948                 if ((tx_idx == tnapi->tx_prod) &&
10949                     (rx_idx == (rx_start_idx + num_pkts)))
10950                         break;
10951         }
10952
10953         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10954         dev_kfree_skb(skb);
10955
10956         if (tx_idx != tnapi->tx_prod)
10957                 goto out;
10958
10959         if (rx_idx != rx_start_idx + num_pkts)
10960                 goto out;
10961
10962         desc = &rnapi->rx_rcb[rx_start_idx];
10963         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10964         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10965         if (opaque_key != RXD_OPAQUE_RING_STD)
10966                 goto out;
10967
10968         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10969             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10970                 goto out;
10971
10972         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10973         if (rx_len != tx_len)
10974                 goto out;
10975
10976         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10977
10978         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10979         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10980
10981         for (i = 14; i < tx_len; i++) {
10982                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10983                         goto out;
10984         }
10985         err = 0;
10986
10987         /* tg3_free_rings will unmap and free the rx_skb */
10988 out:
10989         return err;
10990 }
10991
10992 #define TG3_MAC_LOOPBACK_FAILED         1
10993 #define TG3_PHY_LOOPBACK_FAILED         2
10994 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10995                                          TG3_PHY_LOOPBACK_FAILED)
10996
10997 static int tg3_test_loopback(struct tg3 *tp)
10998 {
10999         int err = 0;
11000         u32 cpmuctrl = 0;
11001
11002         if (!netif_running(tp->dev))
11003                 return TG3_LOOPBACK_FAILED;
11004
11005         err = tg3_reset_hw(tp, 1);
11006         if (err)
11007                 return TG3_LOOPBACK_FAILED;
11008
11009         /* Turn off gphy autopowerdown. */
11010         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11011                 tg3_phy_toggle_apd(tp, false);
11012
11013         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11014                 int i;
11015                 u32 status;
11016
11017                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
11018
11019                 /* Wait for up to 40 microseconds to acquire lock. */
11020                 for (i = 0; i < 4; i++) {
11021                         status = tr32(TG3_CPMU_MUTEX_GNT);
11022                         if (status == CPMU_MUTEX_GNT_DRIVER)
11023                                 break;
11024                         udelay(10);
11025                 }
11026
11027                 if (status != CPMU_MUTEX_GNT_DRIVER)
11028                         return TG3_LOOPBACK_FAILED;
11029
11030                 /* Turn off link-based power management. */
11031                 cpmuctrl = tr32(TG3_CPMU_CTRL);
11032                 tw32(TG3_CPMU_CTRL,
11033                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
11034                                   CPMU_CTRL_LINK_AWARE_MODE));
11035         }
11036
11037         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
11038                 err |= TG3_MAC_LOOPBACK_FAILED;
11039
11040         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
11041                 tw32(TG3_CPMU_CTRL, cpmuctrl);
11042
11043                 /* Release the mutex */
11044                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
11045         }
11046
11047         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11048             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
11049                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
11050                         err |= TG3_PHY_LOOPBACK_FAILED;
11051         }
11052
11053         /* Re-enable gphy autopowerdown. */
11054         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
11055                 tg3_phy_toggle_apd(tp, true);
11056
11057         return err;
11058 }
11059
11060 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
11061                           u64 *data)
11062 {
11063         struct tg3 *tp = netdev_priv(dev);
11064
11065         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11066                 tg3_set_power_state(tp, PCI_D0);
11067
11068         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
11069
11070         if (tg3_test_nvram(tp) != 0) {
11071                 etest->flags |= ETH_TEST_FL_FAILED;
11072                 data[0] = 1;
11073         }
11074         if (tg3_test_link(tp) != 0) {
11075                 etest->flags |= ETH_TEST_FL_FAILED;
11076                 data[1] = 1;
11077         }
11078         if (etest->flags & ETH_TEST_FL_OFFLINE) {
11079                 int err, err2 = 0, irq_sync = 0;
11080
11081                 if (netif_running(dev)) {
11082                         tg3_phy_stop(tp);
11083                         tg3_netif_stop(tp);
11084                         irq_sync = 1;
11085                 }
11086
11087                 tg3_full_lock(tp, irq_sync);
11088
11089                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
11090                 err = tg3_nvram_lock(tp);
11091                 tg3_halt_cpu(tp, RX_CPU_BASE);
11092                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
11093                         tg3_halt_cpu(tp, TX_CPU_BASE);
11094                 if (!err)
11095                         tg3_nvram_unlock(tp);
11096
11097                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
11098                         tg3_phy_reset(tp);
11099
11100                 if (tg3_test_registers(tp) != 0) {
11101                         etest->flags |= ETH_TEST_FL_FAILED;
11102                         data[2] = 1;
11103                 }
11104                 if (tg3_test_memory(tp) != 0) {
11105                         etest->flags |= ETH_TEST_FL_FAILED;
11106                         data[3] = 1;
11107                 }
11108                 if ((data[4] = tg3_test_loopback(tp)) != 0)
11109                         etest->flags |= ETH_TEST_FL_FAILED;
11110
11111                 tg3_full_unlock(tp);
11112
11113                 if (tg3_test_interrupt(tp) != 0) {
11114                         etest->flags |= ETH_TEST_FL_FAILED;
11115                         data[5] = 1;
11116                 }
11117
11118                 tg3_full_lock(tp, 0);
11119
11120                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11121                 if (netif_running(dev)) {
11122                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11123                         err2 = tg3_restart_hw(tp, 1);
11124                         if (!err2)
11125                                 tg3_netif_start(tp);
11126                 }
11127
11128                 tg3_full_unlock(tp);
11129
11130                 if (irq_sync && !err2)
11131                         tg3_phy_start(tp);
11132         }
11133         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11134                 tg3_set_power_state(tp, PCI_D3hot);
11135
11136 }
11137
11138 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11139 {
11140         struct mii_ioctl_data *data = if_mii(ifr);
11141         struct tg3 *tp = netdev_priv(dev);
11142         int err;
11143
11144         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11145                 struct phy_device *phydev;
11146                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
11147                         return -EAGAIN;
11148                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11149                 return phy_mii_ioctl(phydev, ifr, cmd);
11150         }
11151
11152         switch (cmd) {
11153         case SIOCGMIIPHY:
11154                 data->phy_id = tp->phy_addr;
11155
11156                 /* fallthru */
11157         case SIOCGMIIREG: {
11158                 u32 mii_regval;
11159
11160                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11161                         break;                  /* We have no PHY */
11162
11163                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11164                         return -EAGAIN;
11165
11166                 spin_lock_bh(&tp->lock);
11167                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11168                 spin_unlock_bh(&tp->lock);
11169
11170                 data->val_out = mii_regval;
11171
11172                 return err;
11173         }
11174
11175         case SIOCSMIIREG:
11176                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
11177                         break;                  /* We have no PHY */
11178
11179                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11180                         return -EAGAIN;
11181
11182                 spin_lock_bh(&tp->lock);
11183                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11184                 spin_unlock_bh(&tp->lock);
11185
11186                 return err;
11187
11188         default:
11189                 /* do nothing */
11190                 break;
11191         }
11192         return -EOPNOTSUPP;
11193 }
11194
11195 #if TG3_VLAN_TAG_USED
11196 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11197 {
11198         struct tg3 *tp = netdev_priv(dev);
11199
11200         if (!netif_running(dev)) {
11201                 tp->vlgrp = grp;
11202                 return;
11203         }
11204
11205         tg3_netif_stop(tp);
11206
11207         tg3_full_lock(tp, 0);
11208
11209         tp->vlgrp = grp;
11210
11211         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11212         __tg3_set_rx_mode(dev);
11213
11214         tg3_netif_start(tp);
11215
11216         tg3_full_unlock(tp);
11217 }
11218 #endif
11219
11220 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11221 {
11222         struct tg3 *tp = netdev_priv(dev);
11223
11224         memcpy(ec, &tp->coal, sizeof(*ec));
11225         return 0;
11226 }
11227
11228 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11229 {
11230         struct tg3 *tp = netdev_priv(dev);
11231         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11232         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11233
11234         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11235                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11236                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11237                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11238                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11239         }
11240
11241         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11242             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11243             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11244             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11245             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11246             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11247             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11248             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11249             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11250             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11251                 return -EINVAL;
11252
11253         /* No rx interrupts will be generated if both are zero */
11254         if ((ec->rx_coalesce_usecs == 0) &&
11255             (ec->rx_max_coalesced_frames == 0))
11256                 return -EINVAL;
11257
11258         /* No tx interrupts will be generated if both are zero */
11259         if ((ec->tx_coalesce_usecs == 0) &&
11260             (ec->tx_max_coalesced_frames == 0))
11261                 return -EINVAL;
11262
11263         /* Only copy relevant parameters, ignore all others. */
11264         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11265         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11266         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11267         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11268         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11269         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11270         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11271         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11272         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11273
11274         if (netif_running(dev)) {
11275                 tg3_full_lock(tp, 0);
11276                 __tg3_set_coalesce(tp, &tp->coal);
11277                 tg3_full_unlock(tp);
11278         }
11279         return 0;
11280 }
11281
11282 static const struct ethtool_ops tg3_ethtool_ops = {
11283         .get_settings           = tg3_get_settings,
11284         .set_settings           = tg3_set_settings,
11285         .get_drvinfo            = tg3_get_drvinfo,
11286         .get_regs_len           = tg3_get_regs_len,
11287         .get_regs               = tg3_get_regs,
11288         .get_wol                = tg3_get_wol,
11289         .set_wol                = tg3_set_wol,
11290         .get_msglevel           = tg3_get_msglevel,
11291         .set_msglevel           = tg3_set_msglevel,
11292         .nway_reset             = tg3_nway_reset,
11293         .get_link               = ethtool_op_get_link,
11294         .get_eeprom_len         = tg3_get_eeprom_len,
11295         .get_eeprom             = tg3_get_eeprom,
11296         .set_eeprom             = tg3_set_eeprom,
11297         .get_ringparam          = tg3_get_ringparam,
11298         .set_ringparam          = tg3_set_ringparam,
11299         .get_pauseparam         = tg3_get_pauseparam,
11300         .set_pauseparam         = tg3_set_pauseparam,
11301         .get_rx_csum            = tg3_get_rx_csum,
11302         .set_rx_csum            = tg3_set_rx_csum,
11303         .set_tx_csum            = tg3_set_tx_csum,
11304         .set_sg                 = ethtool_op_set_sg,
11305         .set_tso                = tg3_set_tso,
11306         .self_test              = tg3_self_test,
11307         .get_strings            = tg3_get_strings,
11308         .phys_id                = tg3_phys_id,
11309         .get_ethtool_stats      = tg3_get_ethtool_stats,
11310         .get_coalesce           = tg3_get_coalesce,
11311         .set_coalesce           = tg3_set_coalesce,
11312         .get_sset_count         = tg3_get_sset_count,
11313 };
11314
11315 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11316 {
11317         u32 cursize, val, magic;
11318
11319         tp->nvram_size = EEPROM_CHIP_SIZE;
11320
11321         if (tg3_nvram_read(tp, 0, &magic) != 0)
11322                 return;
11323
11324         if ((magic != TG3_EEPROM_MAGIC) &&
11325             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11326             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11327                 return;
11328
11329         /*
11330          * Size the chip by reading offsets at increasing powers of two.
11331          * When we encounter our validation signature, we know the addressing
11332          * has wrapped around, and thus have our chip size.
11333          */
11334         cursize = 0x10;
11335
11336         while (cursize < tp->nvram_size) {
11337                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11338                         return;
11339
11340                 if (val == magic)
11341                         break;
11342
11343                 cursize <<= 1;
11344         }
11345
11346         tp->nvram_size = cursize;
11347 }
11348
11349 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11350 {
11351         u32 val;
11352
11353         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11354             tg3_nvram_read(tp, 0, &val) != 0)
11355                 return;
11356
11357         /* Selfboot format */
11358         if (val != TG3_EEPROM_MAGIC) {
11359                 tg3_get_eeprom_size(tp);
11360                 return;
11361         }
11362
11363         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11364                 if (val != 0) {
11365                         /* This is confusing.  We want to operate on the
11366                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11367                          * call will read from NVRAM and byteswap the data
11368                          * according to the byteswapping settings for all
11369                          * other register accesses.  This ensures the data we
11370                          * want will always reside in the lower 16-bits.
11371                          * However, the data in NVRAM is in LE format, which
11372                          * means the data from the NVRAM read will always be
11373                          * opposite the endianness of the CPU.  The 16-bit
11374                          * byteswap then brings the data to CPU endianness.
11375                          */
11376                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11377                         return;
11378                 }
11379         }
11380         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11381 }
11382
11383 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11384 {
11385         u32 nvcfg1;
11386
11387         nvcfg1 = tr32(NVRAM_CFG1);
11388         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11389                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11390         } else {
11391                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11392                 tw32(NVRAM_CFG1, nvcfg1);
11393         }
11394
11395         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11396             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11397                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11398                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11399                         tp->nvram_jedecnum = JEDEC_ATMEL;
11400                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11401                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11402                         break;
11403                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11404                         tp->nvram_jedecnum = JEDEC_ATMEL;
11405                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11406                         break;
11407                 case FLASH_VENDOR_ATMEL_EEPROM:
11408                         tp->nvram_jedecnum = JEDEC_ATMEL;
11409                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11410                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11411                         break;
11412                 case FLASH_VENDOR_ST:
11413                         tp->nvram_jedecnum = JEDEC_ST;
11414                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11415                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11416                         break;
11417                 case FLASH_VENDOR_SAIFUN:
11418                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11419                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11420                         break;
11421                 case FLASH_VENDOR_SST_SMALL:
11422                 case FLASH_VENDOR_SST_LARGE:
11423                         tp->nvram_jedecnum = JEDEC_SST;
11424                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11425                         break;
11426                 }
11427         } else {
11428                 tp->nvram_jedecnum = JEDEC_ATMEL;
11429                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11430                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11431         }
11432 }
11433
11434 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11435 {
11436         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11437         case FLASH_5752PAGE_SIZE_256:
11438                 tp->nvram_pagesize = 256;
11439                 break;
11440         case FLASH_5752PAGE_SIZE_512:
11441                 tp->nvram_pagesize = 512;
11442                 break;
11443         case FLASH_5752PAGE_SIZE_1K:
11444                 tp->nvram_pagesize = 1024;
11445                 break;
11446         case FLASH_5752PAGE_SIZE_2K:
11447                 tp->nvram_pagesize = 2048;
11448                 break;
11449         case FLASH_5752PAGE_SIZE_4K:
11450                 tp->nvram_pagesize = 4096;
11451                 break;
11452         case FLASH_5752PAGE_SIZE_264:
11453                 tp->nvram_pagesize = 264;
11454                 break;
11455         case FLASH_5752PAGE_SIZE_528:
11456                 tp->nvram_pagesize = 528;
11457                 break;
11458         }
11459 }
11460
11461 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11462 {
11463         u32 nvcfg1;
11464
11465         nvcfg1 = tr32(NVRAM_CFG1);
11466
11467         /* NVRAM protection for TPM */
11468         if (nvcfg1 & (1 << 27))
11469                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11470
11471         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11472         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11473         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11474                 tp->nvram_jedecnum = JEDEC_ATMEL;
11475                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11476                 break;
11477         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11478                 tp->nvram_jedecnum = JEDEC_ATMEL;
11479                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11480                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11481                 break;
11482         case FLASH_5752VENDOR_ST_M45PE10:
11483         case FLASH_5752VENDOR_ST_M45PE20:
11484         case FLASH_5752VENDOR_ST_M45PE40:
11485                 tp->nvram_jedecnum = JEDEC_ST;
11486                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11487                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11488                 break;
11489         }
11490
11491         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11492                 tg3_nvram_get_pagesize(tp, nvcfg1);
11493         } else {
11494                 /* For eeprom, set pagesize to maximum eeprom size */
11495                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11496
11497                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11498                 tw32(NVRAM_CFG1, nvcfg1);
11499         }
11500 }
11501
11502 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11503 {
11504         u32 nvcfg1, protect = 0;
11505
11506         nvcfg1 = tr32(NVRAM_CFG1);
11507
11508         /* NVRAM protection for TPM */
11509         if (nvcfg1 & (1 << 27)) {
11510                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11511                 protect = 1;
11512         }
11513
11514         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11515         switch (nvcfg1) {
11516         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11517         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11518         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11519         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11520                 tp->nvram_jedecnum = JEDEC_ATMEL;
11521                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11522                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11523                 tp->nvram_pagesize = 264;
11524                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11525                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11526                         tp->nvram_size = (protect ? 0x3e200 :
11527                                           TG3_NVRAM_SIZE_512KB);
11528                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11529                         tp->nvram_size = (protect ? 0x1f200 :
11530                                           TG3_NVRAM_SIZE_256KB);
11531                 else
11532                         tp->nvram_size = (protect ? 0x1f200 :
11533                                           TG3_NVRAM_SIZE_128KB);
11534                 break;
11535         case FLASH_5752VENDOR_ST_M45PE10:
11536         case FLASH_5752VENDOR_ST_M45PE20:
11537         case FLASH_5752VENDOR_ST_M45PE40:
11538                 tp->nvram_jedecnum = JEDEC_ST;
11539                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11540                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11541                 tp->nvram_pagesize = 256;
11542                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11543                         tp->nvram_size = (protect ?
11544                                           TG3_NVRAM_SIZE_64KB :
11545                                           TG3_NVRAM_SIZE_128KB);
11546                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11547                         tp->nvram_size = (protect ?
11548                                           TG3_NVRAM_SIZE_64KB :
11549                                           TG3_NVRAM_SIZE_256KB);
11550                 else
11551                         tp->nvram_size = (protect ?
11552                                           TG3_NVRAM_SIZE_128KB :
11553                                           TG3_NVRAM_SIZE_512KB);
11554                 break;
11555         }
11556 }
11557
11558 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11559 {
11560         u32 nvcfg1;
11561
11562         nvcfg1 = tr32(NVRAM_CFG1);
11563
11564         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11565         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11566         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11567         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11568         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11569                 tp->nvram_jedecnum = JEDEC_ATMEL;
11570                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11571                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11572
11573                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11574                 tw32(NVRAM_CFG1, nvcfg1);
11575                 break;
11576         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11577         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11578         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11579         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11580                 tp->nvram_jedecnum = JEDEC_ATMEL;
11581                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11582                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11583                 tp->nvram_pagesize = 264;
11584                 break;
11585         case FLASH_5752VENDOR_ST_M45PE10:
11586         case FLASH_5752VENDOR_ST_M45PE20:
11587         case FLASH_5752VENDOR_ST_M45PE40:
11588                 tp->nvram_jedecnum = JEDEC_ST;
11589                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11591                 tp->nvram_pagesize = 256;
11592                 break;
11593         }
11594 }
11595
11596 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11597 {
11598         u32 nvcfg1, protect = 0;
11599
11600         nvcfg1 = tr32(NVRAM_CFG1);
11601
11602         /* NVRAM protection for TPM */
11603         if (nvcfg1 & (1 << 27)) {
11604                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11605                 protect = 1;
11606         }
11607
11608         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11609         switch (nvcfg1) {
11610         case FLASH_5761VENDOR_ATMEL_ADB021D:
11611         case FLASH_5761VENDOR_ATMEL_ADB041D:
11612         case FLASH_5761VENDOR_ATMEL_ADB081D:
11613         case FLASH_5761VENDOR_ATMEL_ADB161D:
11614         case FLASH_5761VENDOR_ATMEL_MDB021D:
11615         case FLASH_5761VENDOR_ATMEL_MDB041D:
11616         case FLASH_5761VENDOR_ATMEL_MDB081D:
11617         case FLASH_5761VENDOR_ATMEL_MDB161D:
11618                 tp->nvram_jedecnum = JEDEC_ATMEL;
11619                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11620                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11621                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11622                 tp->nvram_pagesize = 256;
11623                 break;
11624         case FLASH_5761VENDOR_ST_A_M45PE20:
11625         case FLASH_5761VENDOR_ST_A_M45PE40:
11626         case FLASH_5761VENDOR_ST_A_M45PE80:
11627         case FLASH_5761VENDOR_ST_A_M45PE16:
11628         case FLASH_5761VENDOR_ST_M_M45PE20:
11629         case FLASH_5761VENDOR_ST_M_M45PE40:
11630         case FLASH_5761VENDOR_ST_M_M45PE80:
11631         case FLASH_5761VENDOR_ST_M_M45PE16:
11632                 tp->nvram_jedecnum = JEDEC_ST;
11633                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11634                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11635                 tp->nvram_pagesize = 256;
11636                 break;
11637         }
11638
11639         if (protect) {
11640                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11641         } else {
11642                 switch (nvcfg1) {
11643                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11644                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11645                 case FLASH_5761VENDOR_ST_A_M45PE16:
11646                 case FLASH_5761VENDOR_ST_M_M45PE16:
11647                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11648                         break;
11649                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11650                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11651                 case FLASH_5761VENDOR_ST_A_M45PE80:
11652                 case FLASH_5761VENDOR_ST_M_M45PE80:
11653                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11654                         break;
11655                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11656                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11657                 case FLASH_5761VENDOR_ST_A_M45PE40:
11658                 case FLASH_5761VENDOR_ST_M_M45PE40:
11659                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11660                         break;
11661                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11662                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11663                 case FLASH_5761VENDOR_ST_A_M45PE20:
11664                 case FLASH_5761VENDOR_ST_M_M45PE20:
11665                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11666                         break;
11667                 }
11668         }
11669 }
11670
11671 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11672 {
11673         tp->nvram_jedecnum = JEDEC_ATMEL;
11674         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11675         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11676 }
11677
11678 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11679 {
11680         u32 nvcfg1;
11681
11682         nvcfg1 = tr32(NVRAM_CFG1);
11683
11684         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11685         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11686         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11687                 tp->nvram_jedecnum = JEDEC_ATMEL;
11688                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11689                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11690
11691                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11692                 tw32(NVRAM_CFG1, nvcfg1);
11693                 return;
11694         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11695         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11696         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11697         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11698         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11699         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11700         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11701                 tp->nvram_jedecnum = JEDEC_ATMEL;
11702                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11703                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11704
11705                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11706                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11707                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11708                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11709                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11710                         break;
11711                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11712                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11713                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11714                         break;
11715                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11716                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11717                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11718                         break;
11719                 }
11720                 break;
11721         case FLASH_5752VENDOR_ST_M45PE10:
11722         case FLASH_5752VENDOR_ST_M45PE20:
11723         case FLASH_5752VENDOR_ST_M45PE40:
11724                 tp->nvram_jedecnum = JEDEC_ST;
11725                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11726                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11727
11728                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11729                 case FLASH_5752VENDOR_ST_M45PE10:
11730                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11731                         break;
11732                 case FLASH_5752VENDOR_ST_M45PE20:
11733                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11734                         break;
11735                 case FLASH_5752VENDOR_ST_M45PE40:
11736                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11737                         break;
11738                 }
11739                 break;
11740         default:
11741                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11742                 return;
11743         }
11744
11745         tg3_nvram_get_pagesize(tp, nvcfg1);
11746         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11747                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11748 }
11749
11750
11751 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11752 {
11753         u32 nvcfg1;
11754
11755         nvcfg1 = tr32(NVRAM_CFG1);
11756
11757         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11758         case FLASH_5717VENDOR_ATMEL_EEPROM:
11759         case FLASH_5717VENDOR_MICRO_EEPROM:
11760                 tp->nvram_jedecnum = JEDEC_ATMEL;
11761                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11762                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11763
11764                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11765                 tw32(NVRAM_CFG1, nvcfg1);
11766                 return;
11767         case FLASH_5717VENDOR_ATMEL_MDB011D:
11768         case FLASH_5717VENDOR_ATMEL_ADB011B:
11769         case FLASH_5717VENDOR_ATMEL_ADB011D:
11770         case FLASH_5717VENDOR_ATMEL_MDB021D:
11771         case FLASH_5717VENDOR_ATMEL_ADB021B:
11772         case FLASH_5717VENDOR_ATMEL_ADB021D:
11773         case FLASH_5717VENDOR_ATMEL_45USPT:
11774                 tp->nvram_jedecnum = JEDEC_ATMEL;
11775                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11776                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11777
11778                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11779                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11780                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11781                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11782                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11783                         break;
11784                 default:
11785                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11786                         break;
11787                 }
11788                 break;
11789         case FLASH_5717VENDOR_ST_M_M25PE10:
11790         case FLASH_5717VENDOR_ST_A_M25PE10:
11791         case FLASH_5717VENDOR_ST_M_M45PE10:
11792         case FLASH_5717VENDOR_ST_A_M45PE10:
11793         case FLASH_5717VENDOR_ST_M_M25PE20:
11794         case FLASH_5717VENDOR_ST_A_M25PE20:
11795         case FLASH_5717VENDOR_ST_M_M45PE20:
11796         case FLASH_5717VENDOR_ST_A_M45PE20:
11797         case FLASH_5717VENDOR_ST_25USPT:
11798         case FLASH_5717VENDOR_ST_45USPT:
11799                 tp->nvram_jedecnum = JEDEC_ST;
11800                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11801                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11802
11803                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11804                 case FLASH_5717VENDOR_ST_M_M25PE20:
11805                 case FLASH_5717VENDOR_ST_A_M25PE20:
11806                 case FLASH_5717VENDOR_ST_M_M45PE20:
11807                 case FLASH_5717VENDOR_ST_A_M45PE20:
11808                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11809                         break;
11810                 default:
11811                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11812                         break;
11813                 }
11814                 break;
11815         default:
11816                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11817                 return;
11818         }
11819
11820         tg3_nvram_get_pagesize(tp, nvcfg1);
11821         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11822                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11823 }
11824
11825 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11826 static void __devinit tg3_nvram_init(struct tg3 *tp)
11827 {
11828         tw32_f(GRC_EEPROM_ADDR,
11829              (EEPROM_ADDR_FSM_RESET |
11830               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11831                EEPROM_ADDR_CLKPERD_SHIFT)));
11832
11833         msleep(1);
11834
11835         /* Enable seeprom accesses. */
11836         tw32_f(GRC_LOCAL_CTRL,
11837              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11838         udelay(100);
11839
11840         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11841             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11842                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11843
11844                 if (tg3_nvram_lock(tp)) {
11845                         netdev_warn(tp->dev,
11846                                     "Cannot get nvram lock, %s failed\n",
11847                                     __func__);
11848                         return;
11849                 }
11850                 tg3_enable_nvram_access(tp);
11851
11852                 tp->nvram_size = 0;
11853
11854                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11855                         tg3_get_5752_nvram_info(tp);
11856                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11857                         tg3_get_5755_nvram_info(tp);
11858                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11859                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11860                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11861                         tg3_get_5787_nvram_info(tp);
11862                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11863                         tg3_get_5761_nvram_info(tp);
11864                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11865                         tg3_get_5906_nvram_info(tp);
11866                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11867                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11868                         tg3_get_57780_nvram_info(tp);
11869                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11870                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11871                         tg3_get_5717_nvram_info(tp);
11872                 else
11873                         tg3_get_nvram_info(tp);
11874
11875                 if (tp->nvram_size == 0)
11876                         tg3_get_nvram_size(tp);
11877
11878                 tg3_disable_nvram_access(tp);
11879                 tg3_nvram_unlock(tp);
11880
11881         } else {
11882                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11883
11884                 tg3_get_eeprom_size(tp);
11885         }
11886 }
11887
11888 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11889                                     u32 offset, u32 len, u8 *buf)
11890 {
11891         int i, j, rc = 0;
11892         u32 val;
11893
11894         for (i = 0; i < len; i += 4) {
11895                 u32 addr;
11896                 __be32 data;
11897
11898                 addr = offset + i;
11899
11900                 memcpy(&data, buf + i, 4);
11901
11902                 /*
11903                  * The SEEPROM interface expects the data to always be opposite
11904                  * the native endian format.  We accomplish this by reversing
11905                  * all the operations that would have been performed on the
11906                  * data from a call to tg3_nvram_read_be32().
11907                  */
11908                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11909
11910                 val = tr32(GRC_EEPROM_ADDR);
11911                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11912
11913                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11914                         EEPROM_ADDR_READ);
11915                 tw32(GRC_EEPROM_ADDR, val |
11916                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11917                         (addr & EEPROM_ADDR_ADDR_MASK) |
11918                         EEPROM_ADDR_START |
11919                         EEPROM_ADDR_WRITE);
11920
11921                 for (j = 0; j < 1000; j++) {
11922                         val = tr32(GRC_EEPROM_ADDR);
11923
11924                         if (val & EEPROM_ADDR_COMPLETE)
11925                                 break;
11926                         msleep(1);
11927                 }
11928                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11929                         rc = -EBUSY;
11930                         break;
11931                 }
11932         }
11933
11934         return rc;
11935 }
11936
11937 /* offset and length are dword aligned */
11938 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11939                 u8 *buf)
11940 {
11941         int ret = 0;
11942         u32 pagesize = tp->nvram_pagesize;
11943         u32 pagemask = pagesize - 1;
11944         u32 nvram_cmd;
11945         u8 *tmp;
11946
11947         tmp = kmalloc(pagesize, GFP_KERNEL);
11948         if (tmp == NULL)
11949                 return -ENOMEM;
11950
11951         while (len) {
11952                 int j;
11953                 u32 phy_addr, page_off, size;
11954
11955                 phy_addr = offset & ~pagemask;
11956
11957                 for (j = 0; j < pagesize; j += 4) {
11958                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11959                                                   (__be32 *) (tmp + j));
11960                         if (ret)
11961                                 break;
11962                 }
11963                 if (ret)
11964                         break;
11965
11966                 page_off = offset & pagemask;
11967                 size = pagesize;
11968                 if (len < size)
11969                         size = len;
11970
11971                 len -= size;
11972
11973                 memcpy(tmp + page_off, buf, size);
11974
11975                 offset = offset + (pagesize - page_off);
11976
11977                 tg3_enable_nvram_access(tp);
11978
11979                 /*
11980                  * Before we can erase the flash page, we need
11981                  * to issue a special "write enable" command.
11982                  */
11983                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11984
11985                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11986                         break;
11987
11988                 /* Erase the target page */
11989                 tw32(NVRAM_ADDR, phy_addr);
11990
11991                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11992                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11993
11994                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11995                         break;
11996
11997                 /* Issue another write enable to start the write. */
11998                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11999
12000                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
12001                         break;
12002
12003                 for (j = 0; j < pagesize; j += 4) {
12004                         __be32 data;
12005
12006                         data = *((__be32 *) (tmp + j));
12007
12008                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
12009
12010                         tw32(NVRAM_ADDR, phy_addr + j);
12011
12012                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
12013                                 NVRAM_CMD_WR;
12014
12015                         if (j == 0)
12016                                 nvram_cmd |= NVRAM_CMD_FIRST;
12017                         else if (j == (pagesize - 4))
12018                                 nvram_cmd |= NVRAM_CMD_LAST;
12019
12020                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12021                                 break;
12022                 }
12023                 if (ret)
12024                         break;
12025         }
12026
12027         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
12028         tg3_nvram_exec_cmd(tp, nvram_cmd);
12029
12030         kfree(tmp);
12031
12032         return ret;
12033 }
12034
12035 /* offset and length are dword aligned */
12036 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
12037                 u8 *buf)
12038 {
12039         int i, ret = 0;
12040
12041         for (i = 0; i < len; i += 4, offset += 4) {
12042                 u32 page_off, phy_addr, nvram_cmd;
12043                 __be32 data;
12044
12045                 memcpy(&data, buf + i, 4);
12046                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
12047
12048                 page_off = offset % tp->nvram_pagesize;
12049
12050                 phy_addr = tg3_nvram_phys_addr(tp, offset);
12051
12052                 tw32(NVRAM_ADDR, phy_addr);
12053
12054                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
12055
12056                 if (page_off == 0 || i == 0)
12057                         nvram_cmd |= NVRAM_CMD_FIRST;
12058                 if (page_off == (tp->nvram_pagesize - 4))
12059                         nvram_cmd |= NVRAM_CMD_LAST;
12060
12061                 if (i == (len - 4))
12062                         nvram_cmd |= NVRAM_CMD_LAST;
12063
12064                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
12065                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
12066                     (tp->nvram_jedecnum == JEDEC_ST) &&
12067                     (nvram_cmd & NVRAM_CMD_FIRST)) {
12068
12069                         if ((ret = tg3_nvram_exec_cmd(tp,
12070                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
12071                                 NVRAM_CMD_DONE)))
12072
12073                                 break;
12074                 }
12075                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12076                         /* We always do complete word writes to eeprom. */
12077                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
12078                 }
12079
12080                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
12081                         break;
12082         }
12083         return ret;
12084 }
12085
12086 /* offset and length are dword aligned */
12087 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
12088 {
12089         int ret;
12090
12091         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12092                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
12093                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
12094                 udelay(40);
12095         }
12096
12097         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
12098                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
12099         } else {
12100                 u32 grc_mode;
12101
12102                 ret = tg3_nvram_lock(tp);
12103                 if (ret)
12104                         return ret;
12105
12106                 tg3_enable_nvram_access(tp);
12107                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
12108                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
12109                         tw32(NVRAM_WRITE1, 0x406);
12110
12111                 grc_mode = tr32(GRC_MODE);
12112                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12113
12114                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12115                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12116
12117                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
12118                                 buf);
12119                 } else {
12120                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12121                                 buf);
12122                 }
12123
12124                 grc_mode = tr32(GRC_MODE);
12125                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12126
12127                 tg3_disable_nvram_access(tp);
12128                 tg3_nvram_unlock(tp);
12129         }
12130
12131         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12132                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12133                 udelay(40);
12134         }
12135
12136         return ret;
12137 }
12138
12139 struct subsys_tbl_ent {
12140         u16 subsys_vendor, subsys_devid;
12141         u32 phy_id;
12142 };
12143
12144 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
12145         /* Broadcom boards. */
12146         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12147           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
12148         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12149           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
12150         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12151           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
12152         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12153           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
12154         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12155           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
12156         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12157           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
12158         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12159           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
12160         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12161           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
12162         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12163           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
12164         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12165           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
12166         { TG3PCI_SUBVENDOR_ID_BROADCOM,
12167           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
12168
12169         /* 3com boards. */
12170         { TG3PCI_SUBVENDOR_ID_3COM,
12171           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
12172         { TG3PCI_SUBVENDOR_ID_3COM,
12173           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
12174         { TG3PCI_SUBVENDOR_ID_3COM,
12175           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
12176         { TG3PCI_SUBVENDOR_ID_3COM,
12177           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
12178         { TG3PCI_SUBVENDOR_ID_3COM,
12179           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12180
12181         /* DELL boards. */
12182         { TG3PCI_SUBVENDOR_ID_DELL,
12183           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12184         { TG3PCI_SUBVENDOR_ID_DELL,
12185           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12186         { TG3PCI_SUBVENDOR_ID_DELL,
12187           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12188         { TG3PCI_SUBVENDOR_ID_DELL,
12189           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12190
12191         /* Compaq boards. */
12192         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12193           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12194         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12195           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12196         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12197           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12198         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12199           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12200         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12201           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12202
12203         /* IBM boards. */
12204         { TG3PCI_SUBVENDOR_ID_IBM,
12205           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12206 };
12207
12208 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12209 {
12210         int i;
12211
12212         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12213                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12214                      tp->pdev->subsystem_vendor) &&
12215                     (subsys_id_to_phy_id[i].subsys_devid ==
12216                      tp->pdev->subsystem_device))
12217                         return &subsys_id_to_phy_id[i];
12218         }
12219         return NULL;
12220 }
12221
12222 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12223 {
12224         u32 val;
12225         u16 pmcsr;
12226
12227         /* On some early chips the SRAM cannot be accessed in D3hot state,
12228          * so need make sure we're in D0.
12229          */
12230         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12231         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12232         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12233         msleep(1);
12234
12235         /* Make sure register accesses (indirect or otherwise)
12236          * will function correctly.
12237          */
12238         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12239                                tp->misc_host_ctrl);
12240
12241         /* The memory arbiter has to be enabled in order for SRAM accesses
12242          * to succeed.  Normally on powerup the tg3 chip firmware will make
12243          * sure it is enabled, but other entities such as system netboot
12244          * code might disable it.
12245          */
12246         val = tr32(MEMARB_MODE);
12247         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12248
12249         tp->phy_id = TG3_PHY_ID_INVALID;
12250         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12251
12252         /* Assume an onboard device and WOL capable by default.  */
12253         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12254
12255         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12256                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12257                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12258                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12259                 }
12260                 val = tr32(VCPU_CFGSHDW);
12261                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12262                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12263                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12264                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12265                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12266                 goto done;
12267         }
12268
12269         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12270         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12271                 u32 nic_cfg, led_cfg;
12272                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12273                 int eeprom_phy_serdes = 0;
12274
12275                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12276                 tp->nic_sram_data_cfg = nic_cfg;
12277
12278                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12279                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12280                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12281                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12282                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12283                     (ver > 0) && (ver < 0x100))
12284                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12285
12286                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12287                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12288
12289                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12290                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12291                         eeprom_phy_serdes = 1;
12292
12293                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12294                 if (nic_phy_id != 0) {
12295                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12296                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12297
12298                         eeprom_phy_id  = (id1 >> 16) << 10;
12299                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12300                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12301                 } else
12302                         eeprom_phy_id = 0;
12303
12304                 tp->phy_id = eeprom_phy_id;
12305                 if (eeprom_phy_serdes) {
12306                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12307                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12308                         else
12309                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12310                 }
12311
12312                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12313                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12314                                     SHASTA_EXT_LED_MODE_MASK);
12315                 else
12316                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12317
12318                 switch (led_cfg) {
12319                 default:
12320                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12321                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12322                         break;
12323
12324                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12325                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12326                         break;
12327
12328                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12329                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12330
12331                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12332                          * read on some older 5700/5701 bootcode.
12333                          */
12334                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12335                             ASIC_REV_5700 ||
12336                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12337                             ASIC_REV_5701)
12338                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12339
12340                         break;
12341
12342                 case SHASTA_EXT_LED_SHARED:
12343                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12344                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12345                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12346                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12347                                                  LED_CTRL_MODE_PHY_2);
12348                         break;
12349
12350                 case SHASTA_EXT_LED_MAC:
12351                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12352                         break;
12353
12354                 case SHASTA_EXT_LED_COMBO:
12355                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12356                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12357                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12358                                                  LED_CTRL_MODE_PHY_2);
12359                         break;
12360
12361                 }
12362
12363                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12364                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12365                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12366                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12367
12368                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12369                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12370
12371                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12372                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12373                         if ((tp->pdev->subsystem_vendor ==
12374                              PCI_VENDOR_ID_ARIMA) &&
12375                             (tp->pdev->subsystem_device == 0x205a ||
12376                              tp->pdev->subsystem_device == 0x2063))
12377                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12378                 } else {
12379                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12380                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12381                 }
12382
12383                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12384                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12385                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12386                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12387                 }
12388
12389                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12390                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12391                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12392
12393                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12394                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12395                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12396
12397                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12398                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12399                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12400
12401                 if (cfg2 & (1 << 17))
12402                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12403
12404                 /* serdes signal pre-emphasis in register 0x590 set by */
12405                 /* bootcode if bit 18 is set */
12406                 if (cfg2 & (1 << 18))
12407                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12408
12409                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12410                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12411                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12412                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12413
12414                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12415                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12416                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12417                         u32 cfg3;
12418
12419                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12420                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12421                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12422                 }
12423
12424                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12425                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12426                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12427                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12428                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12429                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12430         }
12431 done:
12432         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12433         device_set_wakeup_enable(&tp->pdev->dev,
12434                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12435 }
12436
12437 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12438 {
12439         int i;
12440         u32 val;
12441
12442         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12443         tw32(OTP_CTRL, cmd);
12444
12445         /* Wait for up to 1 ms for command to execute. */
12446         for (i = 0; i < 100; i++) {
12447                 val = tr32(OTP_STATUS);
12448                 if (val & OTP_STATUS_CMD_DONE)
12449                         break;
12450                 udelay(10);
12451         }
12452
12453         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12454 }
12455
12456 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12457  * configuration is a 32-bit value that straddles the alignment boundary.
12458  * We do two 32-bit reads and then shift and merge the results.
12459  */
12460 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12461 {
12462         u32 bhalf_otp, thalf_otp;
12463
12464         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12465
12466         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12467                 return 0;
12468
12469         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12470
12471         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12472                 return 0;
12473
12474         thalf_otp = tr32(OTP_READ_DATA);
12475
12476         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12477
12478         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12479                 return 0;
12480
12481         bhalf_otp = tr32(OTP_READ_DATA);
12482
12483         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12484 }
12485
12486 static int __devinit tg3_phy_probe(struct tg3 *tp)
12487 {
12488         u32 hw_phy_id_1, hw_phy_id_2;
12489         u32 hw_phy_id, hw_phy_id_masked;
12490         int err;
12491
12492         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12493                 return tg3_phy_init(tp);
12494
12495         /* Reading the PHY ID register can conflict with ASF
12496          * firmware access to the PHY hardware.
12497          */
12498         err = 0;
12499         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12500             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12501                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12502         } else {
12503                 /* Now read the physical PHY_ID from the chip and verify
12504                  * that it is sane.  If it doesn't look good, we fall back
12505                  * to either the hard-coded table based PHY_ID and failing
12506                  * that the value found in the eeprom area.
12507                  */
12508                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12509                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12510
12511                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12512                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12513                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12514
12515                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12516         }
12517
12518         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12519                 tp->phy_id = hw_phy_id;
12520                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12521                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12522                 else
12523                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12524         } else {
12525                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12526                         /* Do nothing, phy ID already set up in
12527                          * tg3_get_eeprom_hw_cfg().
12528                          */
12529                 } else {
12530                         struct subsys_tbl_ent *p;
12531
12532                         /* No eeprom signature?  Try the hardcoded
12533                          * subsys device table.
12534                          */
12535                         p = tg3_lookup_by_subsys(tp);
12536                         if (!p)
12537                                 return -ENODEV;
12538
12539                         tp->phy_id = p->phy_id;
12540                         if (!tp->phy_id ||
12541                             tp->phy_id == TG3_PHY_ID_BCM8002)
12542                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12543                 }
12544         }
12545
12546         if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12547             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12548              tp->pci_chip_rev_id != CHIPREV_ID_57765_A0))
12549                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
12550
12551         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12552             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12553             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12554                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12555
12556                 tg3_readphy(tp, MII_BMSR, &bmsr);
12557                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12558                     (bmsr & BMSR_LSTATUS))
12559                         goto skip_phy_reset;
12560
12561                 err = tg3_phy_reset(tp);
12562                 if (err)
12563                         return err;
12564
12565                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12566                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12567                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12568                 tg3_ctrl = 0;
12569                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12570                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12571                                     MII_TG3_CTRL_ADV_1000_FULL);
12572                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12573                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12574                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12575                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12576                 }
12577
12578                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12579                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12580                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12581                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12582                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12583
12584                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12585                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12586
12587                         tg3_writephy(tp, MII_BMCR,
12588                                      BMCR_ANENABLE | BMCR_ANRESTART);
12589                 }
12590                 tg3_phy_set_wirespeed(tp);
12591
12592                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12593                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12594                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12595         }
12596
12597 skip_phy_reset:
12598         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12599                 err = tg3_init_5401phy_dsp(tp);
12600                 if (err)
12601                         return err;
12602
12603                 err = tg3_init_5401phy_dsp(tp);
12604         }
12605
12606         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12607                 tp->link_config.advertising =
12608                         (ADVERTISED_1000baseT_Half |
12609                          ADVERTISED_1000baseT_Full |
12610                          ADVERTISED_Autoneg |
12611                          ADVERTISED_FIBRE);
12612         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12613                 tp->link_config.advertising &=
12614                         ~(ADVERTISED_1000baseT_Half |
12615                           ADVERTISED_1000baseT_Full);
12616
12617         return err;
12618 }
12619
12620 static void __devinit tg3_read_vpd(struct tg3 *tp)
12621 {
12622         u8 *vpd_data;
12623         unsigned int block_end, rosize, len;
12624         int j, i = 0;
12625         u32 magic;
12626
12627         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12628             tg3_nvram_read(tp, 0x0, &magic))
12629                 goto out_no_vpd;
12630
12631         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12632         if (!vpd_data)
12633                 goto out_no_vpd;
12634
12635         if (magic == TG3_EEPROM_MAGIC) {
12636                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12637                         u32 tmp;
12638
12639                         /* The data is in little-endian format in NVRAM.
12640                          * Use the big-endian read routines to preserve
12641                          * the byte order as it exists in NVRAM.
12642                          */
12643                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12644                                 goto out_not_found;
12645
12646                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12647                 }
12648         } else {
12649                 ssize_t cnt;
12650                 unsigned int pos = 0;
12651
12652                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12653                         cnt = pci_read_vpd(tp->pdev, pos,
12654                                            TG3_NVM_VPD_LEN - pos,
12655                                            &vpd_data[pos]);
12656                         if (cnt == -ETIMEDOUT || -EINTR)
12657                                 cnt = 0;
12658                         else if (cnt < 0)
12659                                 goto out_not_found;
12660                 }
12661                 if (pos != TG3_NVM_VPD_LEN)
12662                         goto out_not_found;
12663         }
12664
12665         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12666                              PCI_VPD_LRDT_RO_DATA);
12667         if (i < 0)
12668                 goto out_not_found;
12669
12670         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12671         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12672         i += PCI_VPD_LRDT_TAG_SIZE;
12673
12674         if (block_end > TG3_NVM_VPD_LEN)
12675                 goto out_not_found;
12676
12677         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12678                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12679         if (j > 0) {
12680                 len = pci_vpd_info_field_size(&vpd_data[j]);
12681
12682                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12683                 if (j + len > block_end || len != 4 ||
12684                     memcmp(&vpd_data[j], "1028", 4))
12685                         goto partno;
12686
12687                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12688                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12689                 if (j < 0)
12690                         goto partno;
12691
12692                 len = pci_vpd_info_field_size(&vpd_data[j]);
12693
12694                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12695                 if (j + len > block_end)
12696                         goto partno;
12697
12698                 memcpy(tp->fw_ver, &vpd_data[j], len);
12699                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12700         }
12701
12702 partno:
12703         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12704                                       PCI_VPD_RO_KEYWORD_PARTNO);
12705         if (i < 0)
12706                 goto out_not_found;
12707
12708         len = pci_vpd_info_field_size(&vpd_data[i]);
12709
12710         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12711         if (len > TG3_BPN_SIZE ||
12712             (len + i) > TG3_NVM_VPD_LEN)
12713                 goto out_not_found;
12714
12715         memcpy(tp->board_part_number, &vpd_data[i], len);
12716
12717 out_not_found:
12718         kfree(vpd_data);
12719         if (tp->board_part_number[0])
12720                 return;
12721
12722 out_no_vpd:
12723         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
12724                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717)
12725                         strcpy(tp->board_part_number, "BCM5717");
12726                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
12727                         strcpy(tp->board_part_number, "BCM5718");
12728                 else
12729                         goto nomatch;
12730         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
12731                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12732                         strcpy(tp->board_part_number, "BCM57780");
12733                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12734                         strcpy(tp->board_part_number, "BCM57760");
12735                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12736                         strcpy(tp->board_part_number, "BCM57790");
12737                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12738                         strcpy(tp->board_part_number, "BCM57788");
12739                 else
12740                         goto nomatch;
12741         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
12742                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12743                         strcpy(tp->board_part_number, "BCM57761");
12744                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12745                         strcpy(tp->board_part_number, "BCM57765");
12746                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12747                         strcpy(tp->board_part_number, "BCM57781");
12748                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12749                         strcpy(tp->board_part_number, "BCM57785");
12750                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12751                         strcpy(tp->board_part_number, "BCM57791");
12752                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12753                         strcpy(tp->board_part_number, "BCM57795");
12754                 else
12755                         goto nomatch;
12756         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12757                 strcpy(tp->board_part_number, "BCM95906");
12758         } else {
12759 nomatch:
12760                 strcpy(tp->board_part_number, "none");
12761         }
12762 }
12763
12764 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12765 {
12766         u32 val;
12767
12768         if (tg3_nvram_read(tp, offset, &val) ||
12769             (val & 0xfc000000) != 0x0c000000 ||
12770             tg3_nvram_read(tp, offset + 4, &val) ||
12771             val != 0)
12772                 return 0;
12773
12774         return 1;
12775 }
12776
12777 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12778 {
12779         u32 val, offset, start, ver_offset;
12780         int i, dst_off;
12781         bool newver = false;
12782
12783         if (tg3_nvram_read(tp, 0xc, &offset) ||
12784             tg3_nvram_read(tp, 0x4, &start))
12785                 return;
12786
12787         offset = tg3_nvram_logical_addr(tp, offset);
12788
12789         if (tg3_nvram_read(tp, offset, &val))
12790                 return;
12791
12792         if ((val & 0xfc000000) == 0x0c000000) {
12793                 if (tg3_nvram_read(tp, offset + 4, &val))
12794                         return;
12795
12796                 if (val == 0)
12797                         newver = true;
12798         }
12799
12800         dst_off = strlen(tp->fw_ver);
12801
12802         if (newver) {
12803                 if (TG3_VER_SIZE - dst_off < 16 ||
12804                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12805                         return;
12806
12807                 offset = offset + ver_offset - start;
12808                 for (i = 0; i < 16; i += 4) {
12809                         __be32 v;
12810                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12811                                 return;
12812
12813                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12814                 }
12815         } else {
12816                 u32 major, minor;
12817
12818                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12819                         return;
12820
12821                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12822                         TG3_NVM_BCVER_MAJSFT;
12823                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12824                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12825                          "v%d.%02d", major, minor);
12826         }
12827 }
12828
12829 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12830 {
12831         u32 val, major, minor;
12832
12833         /* Use native endian representation */
12834         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12835                 return;
12836
12837         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12838                 TG3_NVM_HWSB_CFG1_MAJSFT;
12839         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12840                 TG3_NVM_HWSB_CFG1_MINSFT;
12841
12842         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12843 }
12844
12845 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12846 {
12847         u32 offset, major, minor, build;
12848
12849         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12850
12851         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12852                 return;
12853
12854         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12855         case TG3_EEPROM_SB_REVISION_0:
12856                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12857                 break;
12858         case TG3_EEPROM_SB_REVISION_2:
12859                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12860                 break;
12861         case TG3_EEPROM_SB_REVISION_3:
12862                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12863                 break;
12864         case TG3_EEPROM_SB_REVISION_4:
12865                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12866                 break;
12867         case TG3_EEPROM_SB_REVISION_5:
12868                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12869                 break;
12870         case TG3_EEPROM_SB_REVISION_6:
12871                 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
12872                 break;
12873         default:
12874                 return;
12875         }
12876
12877         if (tg3_nvram_read(tp, offset, &val))
12878                 return;
12879
12880         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12881                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12882         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12883                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12884         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12885
12886         if (minor > 99 || build > 26)
12887                 return;
12888
12889         offset = strlen(tp->fw_ver);
12890         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12891                  " v%d.%02d", major, minor);
12892
12893         if (build > 0) {
12894                 offset = strlen(tp->fw_ver);
12895                 if (offset < TG3_VER_SIZE - 1)
12896                         tp->fw_ver[offset] = 'a' + build - 1;
12897         }
12898 }
12899
12900 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12901 {
12902         u32 val, offset, start;
12903         int i, vlen;
12904
12905         for (offset = TG3_NVM_DIR_START;
12906              offset < TG3_NVM_DIR_END;
12907              offset += TG3_NVM_DIRENT_SIZE) {
12908                 if (tg3_nvram_read(tp, offset, &val))
12909                         return;
12910
12911                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12912                         break;
12913         }
12914
12915         if (offset == TG3_NVM_DIR_END)
12916                 return;
12917
12918         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12919                 start = 0x08000000;
12920         else if (tg3_nvram_read(tp, offset - 4, &start))
12921                 return;
12922
12923         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12924             !tg3_fw_img_is_valid(tp, offset) ||
12925             tg3_nvram_read(tp, offset + 8, &val))
12926                 return;
12927
12928         offset += val - start;
12929
12930         vlen = strlen(tp->fw_ver);
12931
12932         tp->fw_ver[vlen++] = ',';
12933         tp->fw_ver[vlen++] = ' ';
12934
12935         for (i = 0; i < 4; i++) {
12936                 __be32 v;
12937                 if (tg3_nvram_read_be32(tp, offset, &v))
12938                         return;
12939
12940                 offset += sizeof(v);
12941
12942                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12943                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12944                         break;
12945                 }
12946
12947                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12948                 vlen += sizeof(v);
12949         }
12950 }
12951
12952 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12953 {
12954         int vlen;
12955         u32 apedata;
12956         char *fwtype;
12957
12958         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12959             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12960                 return;
12961
12962         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12963         if (apedata != APE_SEG_SIG_MAGIC)
12964                 return;
12965
12966         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12967         if (!(apedata & APE_FW_STATUS_READY))
12968                 return;
12969
12970         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12971
12972         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12973                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12974                 fwtype = "NCSI";
12975         } else {
12976                 fwtype = "DASH";
12977         }
12978
12979         vlen = strlen(tp->fw_ver);
12980
12981         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12982                  fwtype,
12983                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12984                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12985                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12986                  (apedata & APE_FW_VERSION_BLDMSK));
12987 }
12988
12989 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12990 {
12991         u32 val;
12992         bool vpd_vers = false;
12993
12994         if (tp->fw_ver[0] != 0)
12995                 vpd_vers = true;
12996
12997         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12998                 strcat(tp->fw_ver, "sb");
12999                 return;
13000         }
13001
13002         if (tg3_nvram_read(tp, 0, &val))
13003                 return;
13004
13005         if (val == TG3_EEPROM_MAGIC)
13006                 tg3_read_bc_ver(tp);
13007         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
13008                 tg3_read_sb_ver(tp, val);
13009         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
13010                 tg3_read_hwsb_ver(tp);
13011         else
13012                 return;
13013
13014         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
13015              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
13016                 goto done;
13017
13018         tg3_read_mgmtfw_ver(tp);
13019
13020 done:
13021         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
13022 }
13023
13024 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
13025
13026 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
13027 {
13028 #if TG3_VLAN_TAG_USED
13029         dev->vlan_features |= flags;
13030 #endif
13031 }
13032
13033 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
13034 {
13035         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13036             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
13037                 return 4096;
13038         else if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
13039                  !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13040                 return 1024;
13041         else
13042                 return 512;
13043 }
13044
13045 static int __devinit tg3_get_invariants(struct tg3 *tp)
13046 {
13047         static struct pci_device_id write_reorder_chipsets[] = {
13048                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13049                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
13050                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
13051                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
13052                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
13053                              PCI_DEVICE_ID_VIA_8385_0) },
13054                 { },
13055         };
13056         u32 misc_ctrl_reg;
13057         u32 pci_state_reg, grc_misc_cfg;
13058         u32 val;
13059         u16 pci_cmd;
13060         int err;
13061
13062         /* Force memory write invalidate off.  If we leave it on,
13063          * then on 5700_BX chips we have to enable a workaround.
13064          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
13065          * to match the cacheline size.  The Broadcom driver have this
13066          * workaround but turns MWI off all the times so never uses
13067          * it.  This seems to suggest that the workaround is insufficient.
13068          */
13069         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13070         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
13071         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13072
13073         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
13074          * has the register indirect write enable bit set before
13075          * we try to access any of the MMIO registers.  It is also
13076          * critical that the PCI-X hw workaround situation is decided
13077          * before that as well.
13078          */
13079         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13080                               &misc_ctrl_reg);
13081
13082         tp->pci_chip_rev_id = (misc_ctrl_reg >>
13083                                MISC_HOST_CTRL_CHIPREV_SHIFT);
13084         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
13085                 u32 prod_id_asic_rev;
13086
13087                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
13088                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
13089                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
13090                         pci_read_config_dword(tp->pdev,
13091                                               TG3PCI_GEN2_PRODID_ASICREV,
13092                                               &prod_id_asic_rev);
13093                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
13094                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
13095                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
13096                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
13097                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13098                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
13099                         pci_read_config_dword(tp->pdev,
13100                                               TG3PCI_GEN15_PRODID_ASICREV,
13101                                               &prod_id_asic_rev);
13102                 else
13103                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
13104                                               &prod_id_asic_rev);
13105
13106                 tp->pci_chip_rev_id = prod_id_asic_rev;
13107         }
13108
13109         /* Wrong chip ID in 5752 A0. This code can be removed later
13110          * as A0 is not in production.
13111          */
13112         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
13113                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
13114
13115         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
13116          * we need to disable memory and use config. cycles
13117          * only to access all registers. The 5702/03 chips
13118          * can mistakenly decode the special cycles from the
13119          * ICH chipsets as memory write cycles, causing corruption
13120          * of register and memory space. Only certain ICH bridges
13121          * will drive special cycles with non-zero data during the
13122          * address phase which can fall within the 5703's address
13123          * range. This is not an ICH bug as the PCI spec allows
13124          * non-zero address during special cycles. However, only
13125          * these ICH bridges are known to drive non-zero addresses
13126          * during special cycles.
13127          *
13128          * Since special cycles do not cross PCI bridges, we only
13129          * enable this workaround if the 5703 is on the secondary
13130          * bus of these ICH bridges.
13131          */
13132         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
13133             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
13134                 static struct tg3_dev_id {
13135                         u32     vendor;
13136                         u32     device;
13137                         u32     rev;
13138                 } ich_chipsets[] = {
13139                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
13140                           PCI_ANY_ID },
13141                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
13142                           PCI_ANY_ID },
13143                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
13144                           0xa },
13145                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
13146                           PCI_ANY_ID },
13147                         { },
13148                 };
13149                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
13150                 struct pci_dev *bridge = NULL;
13151
13152                 while (pci_id->vendor != 0) {
13153                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
13154                                                 bridge);
13155                         if (!bridge) {
13156                                 pci_id++;
13157                                 continue;
13158                         }
13159                         if (pci_id->rev != PCI_ANY_ID) {
13160                                 if (bridge->revision > pci_id->rev)
13161                                         continue;
13162                         }
13163                         if (bridge->subordinate &&
13164                             (bridge->subordinate->number ==
13165                              tp->pdev->bus->number)) {
13166
13167                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
13168                                 pci_dev_put(bridge);
13169                                 break;
13170                         }
13171                 }
13172         }
13173
13174         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
13175                 static struct tg3_dev_id {
13176                         u32     vendor;
13177                         u32     device;
13178                 } bridge_chipsets[] = {
13179                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
13180                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
13181                         { },
13182                 };
13183                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
13184                 struct pci_dev *bridge = NULL;
13185
13186                 while (pci_id->vendor != 0) {
13187                         bridge = pci_get_device(pci_id->vendor,
13188                                                 pci_id->device,
13189                                                 bridge);
13190                         if (!bridge) {
13191                                 pci_id++;
13192                                 continue;
13193                         }
13194                         if (bridge->subordinate &&
13195                             (bridge->subordinate->number <=
13196                              tp->pdev->bus->number) &&
13197                             (bridge->subordinate->subordinate >=
13198                              tp->pdev->bus->number)) {
13199                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
13200                                 pci_dev_put(bridge);
13201                                 break;
13202                         }
13203                 }
13204         }
13205
13206         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13207          * DMA addresses > 40-bit. This bridge may have other additional
13208          * 57xx devices behind it in some 4-port NIC designs for example.
13209          * Any tg3 device found behind the bridge will also need the 40-bit
13210          * DMA workaround.
13211          */
13212         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13213             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13214                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13215                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13216                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13217         } else {
13218                 struct pci_dev *bridge = NULL;
13219
13220                 do {
13221                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13222                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13223                                                 bridge);
13224                         if (bridge && bridge->subordinate &&
13225                             (bridge->subordinate->number <=
13226                              tp->pdev->bus->number) &&
13227                             (bridge->subordinate->subordinate >=
13228                              tp->pdev->bus->number)) {
13229                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13230                                 pci_dev_put(bridge);
13231                                 break;
13232                         }
13233                 } while (bridge);
13234         }
13235
13236         /* Initialize misc host control in PCI block. */
13237         tp->misc_host_ctrl |= (misc_ctrl_reg &
13238                                MISC_HOST_CTRL_CHIPREV);
13239         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13240                                tp->misc_host_ctrl);
13241
13242         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13243             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13244             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13245                 tp->pdev_peer = tg3_find_peer(tp);
13246
13247         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13248             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13249             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13250                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13251
13252         /* Intentionally exclude ASIC_REV_5906 */
13253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13254             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13255             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13256             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13257             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13258             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13259             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13260                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13261
13262         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13263             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13264             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13265             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13266             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13267                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13268
13269         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13270             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13271                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13272
13273         /* 5700 B0 chips do not support checksumming correctly due
13274          * to hardware bugs.
13275          */
13276         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13277                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13278         else {
13279                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13280
13281                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13282                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13283                         features |= NETIF_F_IPV6_CSUM;
13284                 tp->dev->features |= features;
13285                 vlan_features_add(tp->dev, features);
13286         }
13287
13288         /* Determine TSO capabilities */
13289         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13290                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13291         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13292                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13293                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13294         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13295                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13296                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13297                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13298                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13299         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13300                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13301                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13302                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13303                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13304                         tp->fw_needed = FIRMWARE_TG3TSO5;
13305                 else
13306                         tp->fw_needed = FIRMWARE_TG3TSO;
13307         }
13308
13309         tp->irq_max = 1;
13310
13311         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13312                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13313                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13314                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13315                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13316                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13317                      tp->pdev_peer == tp->pdev))
13318                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13319
13320                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13321                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13322                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13323                 }
13324
13325                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13326                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13327                         tp->irq_max = TG3_IRQ_MAX_VECS;
13328                 }
13329         }
13330
13331         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13332             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13333             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13334                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13335         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13336                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13337                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13338         }
13339
13340         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13341                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13342
13343         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13344             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13345             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13346                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13347
13348         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13349                               &pci_state_reg);
13350
13351         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13352         if (tp->pcie_cap != 0) {
13353                 u16 lnkctl;
13354
13355                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13356
13357                 pcie_set_readrq(tp->pdev, 4096);
13358
13359                 pci_read_config_word(tp->pdev,
13360                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13361                                      &lnkctl);
13362                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13363                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13364                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13365                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13366                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13367                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13368                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13369                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13370                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13371                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13372                 }
13373         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13374                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13375         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13376                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13377                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13378                 if (!tp->pcix_cap) {
13379                         dev_err(&tp->pdev->dev,
13380                                 "Cannot find PCI-X capability, aborting\n");
13381                         return -EIO;
13382                 }
13383
13384                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13385                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13386         }
13387
13388         /* If we have an AMD 762 or VIA K8T800 chipset, write
13389          * reordering to the mailbox registers done by the host
13390          * controller can cause major troubles.  We read back from
13391          * every mailbox register write to force the writes to be
13392          * posted to the chip in order.
13393          */
13394         if (pci_dev_present(write_reorder_chipsets) &&
13395             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13396                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13397
13398         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13399                              &tp->pci_cacheline_sz);
13400         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13401                              &tp->pci_lat_timer);
13402         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13403             tp->pci_lat_timer < 64) {
13404                 tp->pci_lat_timer = 64;
13405                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13406                                       tp->pci_lat_timer);
13407         }
13408
13409         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13410                 /* 5700 BX chips need to have their TX producer index
13411                  * mailboxes written twice to workaround a bug.
13412                  */
13413                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13414
13415                 /* If we are in PCI-X mode, enable register write workaround.
13416                  *
13417                  * The workaround is to use indirect register accesses
13418                  * for all chip writes not to mailbox registers.
13419                  */
13420                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13421                         u32 pm_reg;
13422
13423                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13424
13425                         /* The chip can have it's power management PCI config
13426                          * space registers clobbered due to this bug.
13427                          * So explicitly force the chip into D0 here.
13428                          */
13429                         pci_read_config_dword(tp->pdev,
13430                                               tp->pm_cap + PCI_PM_CTRL,
13431                                               &pm_reg);
13432                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13433                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13434                         pci_write_config_dword(tp->pdev,
13435                                                tp->pm_cap + PCI_PM_CTRL,
13436                                                pm_reg);
13437
13438                         /* Also, force SERR#/PERR# in PCI command. */
13439                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13440                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13441                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13442                 }
13443         }
13444
13445         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13446                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13447         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13448                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13449
13450         /* Chip-specific fixup from Broadcom driver */
13451         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13452             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13453                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13454                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13455         }
13456
13457         /* Default fast path register access methods */
13458         tp->read32 = tg3_read32;
13459         tp->write32 = tg3_write32;
13460         tp->read32_mbox = tg3_read32;
13461         tp->write32_mbox = tg3_write32;
13462         tp->write32_tx_mbox = tg3_write32;
13463         tp->write32_rx_mbox = tg3_write32;
13464
13465         /* Various workaround register access methods */
13466         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13467                 tp->write32 = tg3_write_indirect_reg32;
13468         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13469                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13470                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13471                 /*
13472                  * Back to back register writes can cause problems on these
13473                  * chips, the workaround is to read back all reg writes
13474                  * except those to mailbox regs.
13475                  *
13476                  * See tg3_write_indirect_reg32().
13477                  */
13478                 tp->write32 = tg3_write_flush_reg32;
13479         }
13480
13481         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13482             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13483                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13484                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13485                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13486         }
13487
13488         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13489                 tp->read32 = tg3_read_indirect_reg32;
13490                 tp->write32 = tg3_write_indirect_reg32;
13491                 tp->read32_mbox = tg3_read_indirect_mbox;
13492                 tp->write32_mbox = tg3_write_indirect_mbox;
13493                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13494                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13495
13496                 iounmap(tp->regs);
13497                 tp->regs = NULL;
13498
13499                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13500                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13501                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13502         }
13503         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13504                 tp->read32_mbox = tg3_read32_mbox_5906;
13505                 tp->write32_mbox = tg3_write32_mbox_5906;
13506                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13507                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13508         }
13509
13510         if (tp->write32 == tg3_write_indirect_reg32 ||
13511             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13512              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13513               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13514                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13515
13516         /* Get eeprom hw config before calling tg3_set_power_state().
13517          * In particular, the TG3_FLG2_IS_NIC flag must be
13518          * determined before calling tg3_set_power_state() so that
13519          * we know whether or not to switch out of Vaux power.
13520          * When the flag is set, it means that GPIO1 is used for eeprom
13521          * write protect and also implies that it is a LOM where GPIOs
13522          * are not used to switch power.
13523          */
13524         tg3_get_eeprom_hw_cfg(tp);
13525
13526         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13527                 /* Allow reads and writes to the
13528                  * APE register and memory space.
13529                  */
13530                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13531                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13532                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13533                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13534                                        pci_state_reg);
13535         }
13536
13537         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13538             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13539             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13540             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13541             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13542                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13543
13544         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13545          * GPIO1 driven high will bring 5700's external PHY out of reset.
13546          * It is also used as eeprom write protect on LOMs.
13547          */
13548         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13549         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13550             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13551                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13552                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13553         /* Unused GPIO3 must be driven as output on 5752 because there
13554          * are no pull-up resistors on unused GPIO pins.
13555          */
13556         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13557                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13558
13559         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13560             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13561             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13562                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13563
13564         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13565             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13566                 /* Turn off the debug UART. */
13567                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13568                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13569                         /* Keep VMain power. */
13570                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13571                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13572         }
13573
13574         /* Force the chip into D0. */
13575         err = tg3_set_power_state(tp, PCI_D0);
13576         if (err) {
13577                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13578                 return err;
13579         }
13580
13581         /* Derive initial jumbo mode from MTU assigned in
13582          * ether_setup() via the alloc_etherdev() call
13583          */
13584         if (tp->dev->mtu > ETH_DATA_LEN &&
13585             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13586                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13587
13588         /* Determine WakeOnLan speed to use. */
13589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13590             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13591             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13592             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13593                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13594         } else {
13595                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13596         }
13597
13598         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13599                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13600
13601         /* A few boards don't want Ethernet@WireSpeed phy feature */
13602         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13603             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13604              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13605              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13606             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13607             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13608                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13609
13610         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13611             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13612                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13613         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13614                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13615
13616         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13617             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13618             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13619             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13620             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13621                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13622                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13623                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13624                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13625                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13626                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13627                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13628                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13629                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13630                 } else
13631                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13632         }
13633
13634         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13635             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13636                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13637                 if (tp->phy_otp == 0)
13638                         tp->phy_otp = TG3_OTP_DEFAULT;
13639         }
13640
13641         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13642                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13643         else
13644                 tp->mi_mode = MAC_MI_MODE_BASE;
13645
13646         tp->coalesce_mode = 0;
13647         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13648             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13649                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13650
13651         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13652             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13653                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13654
13655         err = tg3_mdio_init(tp);
13656         if (err)
13657                 return err;
13658
13659         /* Initialize data/descriptor byte/word swapping. */
13660         val = tr32(GRC_MODE);
13661         val &= GRC_MODE_HOST_STACKUP;
13662         tw32(GRC_MODE, val | tp->grc_mode);
13663
13664         tg3_switch_clocks(tp);
13665
13666         /* Clear this out for sanity. */
13667         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13668
13669         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13670                               &pci_state_reg);
13671         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13672             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13673                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13674
13675                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13676                     chiprevid == CHIPREV_ID_5701_B0 ||
13677                     chiprevid == CHIPREV_ID_5701_B2 ||
13678                     chiprevid == CHIPREV_ID_5701_B5) {
13679                         void __iomem *sram_base;
13680
13681                         /* Write some dummy words into the SRAM status block
13682                          * area, see if it reads back correctly.  If the return
13683                          * value is bad, force enable the PCIX workaround.
13684                          */
13685                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13686
13687                         writel(0x00000000, sram_base);
13688                         writel(0x00000000, sram_base + 4);
13689                         writel(0xffffffff, sram_base + 4);
13690                         if (readl(sram_base) != 0x00000000)
13691                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13692                 }
13693         }
13694
13695         udelay(50);
13696         tg3_nvram_init(tp);
13697
13698         grc_misc_cfg = tr32(GRC_MISC_CFG);
13699         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13700
13701         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13702             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13703              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13704                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13705
13706         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13707             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13708                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13709         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13710                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13711                                       HOSTCC_MODE_CLRTICK_TXBD);
13712
13713                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13714                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13715                                        tp->misc_host_ctrl);
13716         }
13717
13718         /* Preserve the APE MAC_MODE bits */
13719         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13720                 tp->mac_mode = tr32(MAC_MODE) |
13721                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13722         else
13723                 tp->mac_mode = TG3_DEF_MAC_MODE;
13724
13725         /* these are limited to 10/100 only */
13726         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13727              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13728             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13729              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13730              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13731               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13732               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13733             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13734              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13735               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13736               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13737             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13738             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13739             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13740             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13741                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13742
13743         err = tg3_phy_probe(tp);
13744         if (err) {
13745                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13746                 /* ... but do not return immediately ... */
13747                 tg3_mdio_fini(tp);
13748         }
13749
13750         tg3_read_vpd(tp);
13751         tg3_read_fw_ver(tp);
13752
13753         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13754                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13755         } else {
13756                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13757                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13758                 else
13759                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13760         }
13761
13762         /* 5700 {AX,BX} chips have a broken status block link
13763          * change bit implementation, so we must use the
13764          * status register in those cases.
13765          */
13766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13767                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13768         else
13769                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13770
13771         /* The led_ctrl is set during tg3_phy_probe, here we might
13772          * have to force the link status polling mechanism based
13773          * upon subsystem IDs.
13774          */
13775         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13776             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13777             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13778                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13779                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13780         }
13781
13782         /* For all SERDES we poll the MAC status register. */
13783         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13784                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13785         else
13786                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13787
13788         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13789         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13790         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13791             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13792                 tp->rx_offset -= NET_IP_ALIGN;
13793 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13794                 tp->rx_copy_thresh = ~(u16)0;
13795 #endif
13796         }
13797
13798         tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
13799         tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
13800         tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
13801
13802         tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
13803
13804         /* Increment the rx prod index on the rx std ring by at most
13805          * 8 for these chips to workaround hw errata.
13806          */
13807         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13808             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13809             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13810                 tp->rx_std_max_post = 8;
13811
13812         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13813                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13814                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13815
13816         return err;
13817 }
13818
13819 #ifdef CONFIG_SPARC
13820 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13821 {
13822         struct net_device *dev = tp->dev;
13823         struct pci_dev *pdev = tp->pdev;
13824         struct device_node *dp = pci_device_to_OF_node(pdev);
13825         const unsigned char *addr;
13826         int len;
13827
13828         addr = of_get_property(dp, "local-mac-address", &len);
13829         if (addr && len == 6) {
13830                 memcpy(dev->dev_addr, addr, 6);
13831                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13832                 return 0;
13833         }
13834         return -ENODEV;
13835 }
13836
13837 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13838 {
13839         struct net_device *dev = tp->dev;
13840
13841         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13842         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13843         return 0;
13844 }
13845 #endif
13846
13847 static int __devinit tg3_get_device_address(struct tg3 *tp)
13848 {
13849         struct net_device *dev = tp->dev;
13850         u32 hi, lo, mac_offset;
13851         int addr_ok = 0;
13852
13853 #ifdef CONFIG_SPARC
13854         if (!tg3_get_macaddr_sparc(tp))
13855                 return 0;
13856 #endif
13857
13858         mac_offset = 0x7c;
13859         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13860             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13861                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13862                         mac_offset = 0xcc;
13863                 if (tg3_nvram_lock(tp))
13864                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13865                 else
13866                         tg3_nvram_unlock(tp);
13867         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13868                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13869                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13870                         mac_offset = 0xcc;
13871                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13872                         mac_offset += 0x18c;
13873         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13874                 mac_offset = 0x10;
13875
13876         /* First try to get it from MAC address mailbox. */
13877         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13878         if ((hi >> 16) == 0x484b) {
13879                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13880                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13881
13882                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13883                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13884                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13885                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13886                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13887
13888                 /* Some old bootcode may report a 0 MAC address in SRAM */
13889                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13890         }
13891         if (!addr_ok) {
13892                 /* Next, try NVRAM. */
13893                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13894                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13895                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13896                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13897                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13898                 }
13899                 /* Finally just fetch it out of the MAC control regs. */
13900                 else {
13901                         hi = tr32(MAC_ADDR_0_HIGH);
13902                         lo = tr32(MAC_ADDR_0_LOW);
13903
13904                         dev->dev_addr[5] = lo & 0xff;
13905                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13906                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13907                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13908                         dev->dev_addr[1] = hi & 0xff;
13909                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13910                 }
13911         }
13912
13913         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13914 #ifdef CONFIG_SPARC
13915                 if (!tg3_get_default_macaddr_sparc(tp))
13916                         return 0;
13917 #endif
13918                 return -EINVAL;
13919         }
13920         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13921         return 0;
13922 }
13923
13924 #define BOUNDARY_SINGLE_CACHELINE       1
13925 #define BOUNDARY_MULTI_CACHELINE        2
13926
13927 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13928 {
13929         int cacheline_size;
13930         u8 byte;
13931         int goal;
13932
13933         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13934         if (byte == 0)
13935                 cacheline_size = 1024;
13936         else
13937                 cacheline_size = (int) byte * 4;
13938
13939         /* On 5703 and later chips, the boundary bits have no
13940          * effect.
13941          */
13942         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13943             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13944             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13945                 goto out;
13946
13947 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13948         goal = BOUNDARY_MULTI_CACHELINE;
13949 #else
13950 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13951         goal = BOUNDARY_SINGLE_CACHELINE;
13952 #else
13953         goal = 0;
13954 #endif
13955 #endif
13956
13957         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13958                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13959                 goto out;
13960         }
13961
13962         if (!goal)
13963                 goto out;
13964
13965         /* PCI controllers on most RISC systems tend to disconnect
13966          * when a device tries to burst across a cache-line boundary.
13967          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13968          *
13969          * Unfortunately, for PCI-E there are only limited
13970          * write-side controls for this, and thus for reads
13971          * we will still get the disconnects.  We'll also waste
13972          * these PCI cycles for both read and write for chips
13973          * other than 5700 and 5701 which do not implement the
13974          * boundary bits.
13975          */
13976         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13977             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13978                 switch (cacheline_size) {
13979                 case 16:
13980                 case 32:
13981                 case 64:
13982                 case 128:
13983                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13984                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13985                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13986                         } else {
13987                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13988                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13989                         }
13990                         break;
13991
13992                 case 256:
13993                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13994                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13995                         break;
13996
13997                 default:
13998                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13999                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
14000                         break;
14001                 }
14002         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14003                 switch (cacheline_size) {
14004                 case 16:
14005                 case 32:
14006                 case 64:
14007                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14008                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14009                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
14010                                 break;
14011                         }
14012                         /* fallthrough */
14013                 case 128:
14014                 default:
14015                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
14016                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
14017                         break;
14018                 }
14019         } else {
14020                 switch (cacheline_size) {
14021                 case 16:
14022                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14023                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
14024                                         DMA_RWCTRL_WRITE_BNDRY_16);
14025                                 break;
14026                         }
14027                         /* fallthrough */
14028                 case 32:
14029                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14030                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
14031                                         DMA_RWCTRL_WRITE_BNDRY_32);
14032                                 break;
14033                         }
14034                         /* fallthrough */
14035                 case 64:
14036                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14037                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
14038                                         DMA_RWCTRL_WRITE_BNDRY_64);
14039                                 break;
14040                         }
14041                         /* fallthrough */
14042                 case 128:
14043                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
14044                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
14045                                         DMA_RWCTRL_WRITE_BNDRY_128);
14046                                 break;
14047                         }
14048                         /* fallthrough */
14049                 case 256:
14050                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
14051                                 DMA_RWCTRL_WRITE_BNDRY_256);
14052                         break;
14053                 case 512:
14054                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
14055                                 DMA_RWCTRL_WRITE_BNDRY_512);
14056                         break;
14057                 case 1024:
14058                 default:
14059                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
14060                                 DMA_RWCTRL_WRITE_BNDRY_1024);
14061                         break;
14062                 }
14063         }
14064
14065 out:
14066         return val;
14067 }
14068
14069 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
14070 {
14071         struct tg3_internal_buffer_desc test_desc;
14072         u32 sram_dma_descs;
14073         int i, ret;
14074
14075         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
14076
14077         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
14078         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
14079         tw32(RDMAC_STATUS, 0);
14080         tw32(WDMAC_STATUS, 0);
14081
14082         tw32(BUFMGR_MODE, 0);
14083         tw32(FTQ_RESET, 0);
14084
14085         test_desc.addr_hi = ((u64) buf_dma) >> 32;
14086         test_desc.addr_lo = buf_dma & 0xffffffff;
14087         test_desc.nic_mbuf = 0x00002100;
14088         test_desc.len = size;
14089
14090         /*
14091          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
14092          * the *second* time the tg3 driver was getting loaded after an
14093          * initial scan.
14094          *
14095          * Broadcom tells me:
14096          *   ...the DMA engine is connected to the GRC block and a DMA
14097          *   reset may affect the GRC block in some unpredictable way...
14098          *   The behavior of resets to individual blocks has not been tested.
14099          *
14100          * Broadcom noted the GRC reset will also reset all sub-components.
14101          */
14102         if (to_device) {
14103                 test_desc.cqid_sqid = (13 << 8) | 2;
14104
14105                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
14106                 udelay(40);
14107         } else {
14108                 test_desc.cqid_sqid = (16 << 8) | 7;
14109
14110                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
14111                 udelay(40);
14112         }
14113         test_desc.flags = 0x00000005;
14114
14115         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
14116                 u32 val;
14117
14118                 val = *(((u32 *)&test_desc) + i);
14119                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
14120                                        sram_dma_descs + (i * sizeof(u32)));
14121                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
14122         }
14123         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
14124
14125         if (to_device)
14126                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
14127         else
14128                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
14129
14130         ret = -ENODEV;
14131         for (i = 0; i < 40; i++) {
14132                 u32 val;
14133
14134                 if (to_device)
14135                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
14136                 else
14137                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
14138                 if ((val & 0xffff) == sram_dma_descs) {
14139                         ret = 0;
14140                         break;
14141                 }
14142
14143                 udelay(100);
14144         }
14145
14146         return ret;
14147 }
14148
14149 #define TEST_BUFFER_SIZE        0x2000
14150
14151 static int __devinit tg3_test_dma(struct tg3 *tp)
14152 {
14153         dma_addr_t buf_dma;
14154         u32 *buf, saved_dma_rwctrl;
14155         int ret = 0;
14156
14157         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
14158         if (!buf) {
14159                 ret = -ENOMEM;
14160                 goto out_nofree;
14161         }
14162
14163         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
14164                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
14165
14166         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
14167
14168         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
14169                 goto out;
14170
14171         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14172                 /* DMA read watermark not used on PCIE */
14173                 tp->dma_rwctrl |= 0x00180000;
14174         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
14175                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
14176                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
14177                         tp->dma_rwctrl |= 0x003f0000;
14178                 else
14179                         tp->dma_rwctrl |= 0x003f000f;
14180         } else {
14181                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14182                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
14183                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
14184                         u32 read_water = 0x7;
14185
14186                         /* If the 5704 is behind the EPB bridge, we can
14187                          * do the less restrictive ONE_DMA workaround for
14188                          * better performance.
14189                          */
14190                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
14191                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14192                                 tp->dma_rwctrl |= 0x8000;
14193                         else if (ccval == 0x6 || ccval == 0x7)
14194                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
14195
14196                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
14197                                 read_water = 4;
14198                         /* Set bit 23 to enable PCIX hw bug fix */
14199                         tp->dma_rwctrl |=
14200                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
14201                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
14202                                 (1 << 23);
14203                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
14204                         /* 5780 always in PCIX mode */
14205                         tp->dma_rwctrl |= 0x00144000;
14206                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
14207                         /* 5714 always in PCIX mode */
14208                         tp->dma_rwctrl |= 0x00148000;
14209                 } else {
14210                         tp->dma_rwctrl |= 0x001b000f;
14211                 }
14212         }
14213
14214         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14215             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14216                 tp->dma_rwctrl &= 0xfffffff0;
14217
14218         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14219             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14220                 /* Remove this if it causes problems for some boards. */
14221                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14222
14223                 /* On 5700/5701 chips, we need to set this bit.
14224                  * Otherwise the chip will issue cacheline transactions
14225                  * to streamable DMA memory with not all the byte
14226                  * enables turned on.  This is an error on several
14227                  * RISC PCI controllers, in particular sparc64.
14228                  *
14229                  * On 5703/5704 chips, this bit has been reassigned
14230                  * a different meaning.  In particular, it is used
14231                  * on those chips to enable a PCI-X workaround.
14232                  */
14233                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14234         }
14235
14236         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14237
14238 #if 0
14239         /* Unneeded, already done by tg3_get_invariants.  */
14240         tg3_switch_clocks(tp);
14241 #endif
14242
14243         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14244             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14245                 goto out;
14246
14247         /* It is best to perform DMA test with maximum write burst size
14248          * to expose the 5700/5701 write DMA bug.
14249          */
14250         saved_dma_rwctrl = tp->dma_rwctrl;
14251         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14252         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14253
14254         while (1) {
14255                 u32 *p = buf, i;
14256
14257                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14258                         p[i] = i;
14259
14260                 /* Send the buffer to the chip. */
14261                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14262                 if (ret) {
14263                         dev_err(&tp->pdev->dev,
14264                                 "%s: Buffer write failed. err = %d\n",
14265                                 __func__, ret);
14266                         break;
14267                 }
14268
14269 #if 0
14270                 /* validate data reached card RAM correctly. */
14271                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14272                         u32 val;
14273                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14274                         if (le32_to_cpu(val) != p[i]) {
14275                                 dev_err(&tp->pdev->dev,
14276                                         "%s: Buffer corrupted on device! "
14277                                         "(%d != %d)\n", __func__, val, i);
14278                                 /* ret = -ENODEV here? */
14279                         }
14280                         p[i] = 0;
14281                 }
14282 #endif
14283                 /* Now read it back. */
14284                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14285                 if (ret) {
14286                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14287                                 "err = %d\n", __func__, ret);
14288                         break;
14289                 }
14290
14291                 /* Verify it. */
14292                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14293                         if (p[i] == i)
14294                                 continue;
14295
14296                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14297                             DMA_RWCTRL_WRITE_BNDRY_16) {
14298                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14299                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14300                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14301                                 break;
14302                         } else {
14303                                 dev_err(&tp->pdev->dev,
14304                                         "%s: Buffer corrupted on read back! "
14305                                         "(%d != %d)\n", __func__, p[i], i);
14306                                 ret = -ENODEV;
14307                                 goto out;
14308                         }
14309                 }
14310
14311                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14312                         /* Success. */
14313                         ret = 0;
14314                         break;
14315                 }
14316         }
14317         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14318             DMA_RWCTRL_WRITE_BNDRY_16) {
14319                 static struct pci_device_id dma_wait_state_chipsets[] = {
14320                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14321                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14322                         { },
14323                 };
14324
14325                 /* DMA test passed without adjusting DMA boundary,
14326                  * now look for chipsets that are known to expose the
14327                  * DMA bug without failing the test.
14328                  */
14329                 if (pci_dev_present(dma_wait_state_chipsets)) {
14330                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14331                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14332                 } else {
14333                         /* Safe to use the calculated DMA boundary. */
14334                         tp->dma_rwctrl = saved_dma_rwctrl;
14335                 }
14336
14337                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14338         }
14339
14340 out:
14341         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14342 out_nofree:
14343         return ret;
14344 }
14345
14346 static void __devinit tg3_init_link_config(struct tg3 *tp)
14347 {
14348         tp->link_config.advertising =
14349                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14350                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14351                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14352                  ADVERTISED_Autoneg | ADVERTISED_MII);
14353         tp->link_config.speed = SPEED_INVALID;
14354         tp->link_config.duplex = DUPLEX_INVALID;
14355         tp->link_config.autoneg = AUTONEG_ENABLE;
14356         tp->link_config.active_speed = SPEED_INVALID;
14357         tp->link_config.active_duplex = DUPLEX_INVALID;
14358         tp->link_config.orig_speed = SPEED_INVALID;
14359         tp->link_config.orig_duplex = DUPLEX_INVALID;
14360         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14361 }
14362
14363 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14364 {
14365         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14366                 tp->bufmgr_config.mbuf_read_dma_low_water =
14367                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14368                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14369                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14370                 tp->bufmgr_config.mbuf_high_water =
14371                         DEFAULT_MB_HIGH_WATER_57765;
14372
14373                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14374                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14375                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14376                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14377                 tp->bufmgr_config.mbuf_high_water_jumbo =
14378                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14379         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14380                 tp->bufmgr_config.mbuf_read_dma_low_water =
14381                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14382                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14383                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14384                 tp->bufmgr_config.mbuf_high_water =
14385                         DEFAULT_MB_HIGH_WATER_5705;
14386                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14387                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14388                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14389                         tp->bufmgr_config.mbuf_high_water =
14390                                 DEFAULT_MB_HIGH_WATER_5906;
14391                 }
14392
14393                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14394                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14395                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14396                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14397                 tp->bufmgr_config.mbuf_high_water_jumbo =
14398                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14399         } else {
14400                 tp->bufmgr_config.mbuf_read_dma_low_water =
14401                         DEFAULT_MB_RDMA_LOW_WATER;
14402                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14403                         DEFAULT_MB_MACRX_LOW_WATER;
14404                 tp->bufmgr_config.mbuf_high_water =
14405                         DEFAULT_MB_HIGH_WATER;
14406
14407                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14408                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14409                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14410                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14411                 tp->bufmgr_config.mbuf_high_water_jumbo =
14412                         DEFAULT_MB_HIGH_WATER_JUMBO;
14413         }
14414
14415         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14416         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14417 }
14418
14419 static char * __devinit tg3_phy_string(struct tg3 *tp)
14420 {
14421         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14422         case TG3_PHY_ID_BCM5400:        return "5400";
14423         case TG3_PHY_ID_BCM5401:        return "5401";
14424         case TG3_PHY_ID_BCM5411:        return "5411";
14425         case TG3_PHY_ID_BCM5701:        return "5701";
14426         case TG3_PHY_ID_BCM5703:        return "5703";
14427         case TG3_PHY_ID_BCM5704:        return "5704";
14428         case TG3_PHY_ID_BCM5705:        return "5705";
14429         case TG3_PHY_ID_BCM5750:        return "5750";
14430         case TG3_PHY_ID_BCM5752:        return "5752";
14431         case TG3_PHY_ID_BCM5714:        return "5714";
14432         case TG3_PHY_ID_BCM5780:        return "5780";
14433         case TG3_PHY_ID_BCM5755:        return "5755";
14434         case TG3_PHY_ID_BCM5787:        return "5787";
14435         case TG3_PHY_ID_BCM5784:        return "5784";
14436         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14437         case TG3_PHY_ID_BCM5906:        return "5906";
14438         case TG3_PHY_ID_BCM5761:        return "5761";
14439         case TG3_PHY_ID_BCM5718C:       return "5718C";
14440         case TG3_PHY_ID_BCM5718S:       return "5718S";
14441         case TG3_PHY_ID_BCM57765:       return "57765";
14442         case TG3_PHY_ID_BCM5719C:       return "5719C";
14443         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14444         case 0:                 return "serdes";
14445         default:                return "unknown";
14446         }
14447 }
14448
14449 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14450 {
14451         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14452                 strcpy(str, "PCI Express");
14453                 return str;
14454         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14455                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14456
14457                 strcpy(str, "PCIX:");
14458
14459                 if ((clock_ctrl == 7) ||
14460                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14461                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14462                         strcat(str, "133MHz");
14463                 else if (clock_ctrl == 0)
14464                         strcat(str, "33MHz");
14465                 else if (clock_ctrl == 2)
14466                         strcat(str, "50MHz");
14467                 else if (clock_ctrl == 4)
14468                         strcat(str, "66MHz");
14469                 else if (clock_ctrl == 6)
14470                         strcat(str, "100MHz");
14471         } else {
14472                 strcpy(str, "PCI:");
14473                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14474                         strcat(str, "66MHz");
14475                 else
14476                         strcat(str, "33MHz");
14477         }
14478         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14479                 strcat(str, ":32-bit");
14480         else
14481                 strcat(str, ":64-bit");
14482         return str;
14483 }
14484
14485 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14486 {
14487         struct pci_dev *peer;
14488         unsigned int func, devnr = tp->pdev->devfn & ~7;
14489
14490         for (func = 0; func < 8; func++) {
14491                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14492                 if (peer && peer != tp->pdev)
14493                         break;
14494                 pci_dev_put(peer);
14495         }
14496         /* 5704 can be configured in single-port mode, set peer to
14497          * tp->pdev in that case.
14498          */
14499         if (!peer) {
14500                 peer = tp->pdev;
14501                 return peer;
14502         }
14503
14504         /*
14505          * We don't need to keep the refcount elevated; there's no way
14506          * to remove one half of this device without removing the other
14507          */
14508         pci_dev_put(peer);
14509
14510         return peer;
14511 }
14512
14513 static void __devinit tg3_init_coal(struct tg3 *tp)
14514 {
14515         struct ethtool_coalesce *ec = &tp->coal;
14516
14517         memset(ec, 0, sizeof(*ec));
14518         ec->cmd = ETHTOOL_GCOALESCE;
14519         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14520         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14521         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14522         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14523         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14524         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14525         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14526         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14527         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14528
14529         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14530                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14531                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14532                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14533                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14534                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14535         }
14536
14537         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14538                 ec->rx_coalesce_usecs_irq = 0;
14539                 ec->tx_coalesce_usecs_irq = 0;
14540                 ec->stats_block_coalesce_usecs = 0;
14541         }
14542 }
14543
14544 static const struct net_device_ops tg3_netdev_ops = {
14545         .ndo_open               = tg3_open,
14546         .ndo_stop               = tg3_close,
14547         .ndo_start_xmit         = tg3_start_xmit,
14548         .ndo_get_stats64        = tg3_get_stats64,
14549         .ndo_validate_addr      = eth_validate_addr,
14550         .ndo_set_multicast_list = tg3_set_rx_mode,
14551         .ndo_set_mac_address    = tg3_set_mac_addr,
14552         .ndo_do_ioctl           = tg3_ioctl,
14553         .ndo_tx_timeout         = tg3_tx_timeout,
14554         .ndo_change_mtu         = tg3_change_mtu,
14555 #if TG3_VLAN_TAG_USED
14556         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14557 #endif
14558 #ifdef CONFIG_NET_POLL_CONTROLLER
14559         .ndo_poll_controller    = tg3_poll_controller,
14560 #endif
14561 };
14562
14563 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14564         .ndo_open               = tg3_open,
14565         .ndo_stop               = tg3_close,
14566         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14567         .ndo_get_stats64        = tg3_get_stats64,
14568         .ndo_validate_addr      = eth_validate_addr,
14569         .ndo_set_multicast_list = tg3_set_rx_mode,
14570         .ndo_set_mac_address    = tg3_set_mac_addr,
14571         .ndo_do_ioctl           = tg3_ioctl,
14572         .ndo_tx_timeout         = tg3_tx_timeout,
14573         .ndo_change_mtu         = tg3_change_mtu,
14574 #if TG3_VLAN_TAG_USED
14575         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14576 #endif
14577 #ifdef CONFIG_NET_POLL_CONTROLLER
14578         .ndo_poll_controller    = tg3_poll_controller,
14579 #endif
14580 };
14581
14582 static int __devinit tg3_init_one(struct pci_dev *pdev,
14583                                   const struct pci_device_id *ent)
14584 {
14585         struct net_device *dev;
14586         struct tg3 *tp;
14587         int i, err, pm_cap;
14588         u32 sndmbx, rcvmbx, intmbx;
14589         char str[40];
14590         u64 dma_mask, persist_dma_mask;
14591
14592         printk_once(KERN_INFO "%s\n", version);
14593
14594         err = pci_enable_device(pdev);
14595         if (err) {
14596                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14597                 return err;
14598         }
14599
14600         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14601         if (err) {
14602                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14603                 goto err_out_disable_pdev;
14604         }
14605
14606         pci_set_master(pdev);
14607
14608         /* Find power-management capability. */
14609         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14610         if (pm_cap == 0) {
14611                 dev_err(&pdev->dev,
14612                         "Cannot find Power Management capability, aborting\n");
14613                 err = -EIO;
14614                 goto err_out_free_res;
14615         }
14616
14617         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14618         if (!dev) {
14619                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14620                 err = -ENOMEM;
14621                 goto err_out_free_res;
14622         }
14623
14624         SET_NETDEV_DEV(dev, &pdev->dev);
14625
14626 #if TG3_VLAN_TAG_USED
14627         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14628 #endif
14629
14630         tp = netdev_priv(dev);
14631         tp->pdev = pdev;
14632         tp->dev = dev;
14633         tp->pm_cap = pm_cap;
14634         tp->rx_mode = TG3_DEF_RX_MODE;
14635         tp->tx_mode = TG3_DEF_TX_MODE;
14636
14637         if (tg3_debug > 0)
14638                 tp->msg_enable = tg3_debug;
14639         else
14640                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14641
14642         /* The word/byte swap controls here control register access byte
14643          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14644          * setting below.
14645          */
14646         tp->misc_host_ctrl =
14647                 MISC_HOST_CTRL_MASK_PCI_INT |
14648                 MISC_HOST_CTRL_WORD_SWAP |
14649                 MISC_HOST_CTRL_INDIR_ACCESS |
14650                 MISC_HOST_CTRL_PCISTATE_RW;
14651
14652         /* The NONFRM (non-frame) byte/word swap controls take effect
14653          * on descriptor entries, anything which isn't packet data.
14654          *
14655          * The StrongARM chips on the board (one for tx, one for rx)
14656          * are running in big-endian mode.
14657          */
14658         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14659                         GRC_MODE_WSWAP_NONFRM_DATA);
14660 #ifdef __BIG_ENDIAN
14661         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14662 #endif
14663         spin_lock_init(&tp->lock);
14664         spin_lock_init(&tp->indirect_lock);
14665         INIT_WORK(&tp->reset_task, tg3_reset_task);
14666
14667         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14668         if (!tp->regs) {
14669                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14670                 err = -ENOMEM;
14671                 goto err_out_free_dev;
14672         }
14673
14674         tg3_init_link_config(tp);
14675
14676         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14677         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14678
14679         dev->ethtool_ops = &tg3_ethtool_ops;
14680         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14681         dev->irq = pdev->irq;
14682
14683         err = tg3_get_invariants(tp);
14684         if (err) {
14685                 dev_err(&pdev->dev,
14686                         "Problem fetching invariants of chip, aborting\n");
14687                 goto err_out_iounmap;
14688         }
14689
14690         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14691             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14692             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14693                 dev->netdev_ops = &tg3_netdev_ops;
14694         else
14695                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14696
14697
14698         /* The EPB bridge inside 5714, 5715, and 5780 and any
14699          * device behind the EPB cannot support DMA addresses > 40-bit.
14700          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14701          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14702          * do DMA address check in tg3_start_xmit().
14703          */
14704         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14705                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14706         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14707                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14708 #ifdef CONFIG_HIGHMEM
14709                 dma_mask = DMA_BIT_MASK(64);
14710 #endif
14711         } else
14712                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14713
14714         /* Configure DMA attributes. */
14715         if (dma_mask > DMA_BIT_MASK(32)) {
14716                 err = pci_set_dma_mask(pdev, dma_mask);
14717                 if (!err) {
14718                         dev->features |= NETIF_F_HIGHDMA;
14719                         err = pci_set_consistent_dma_mask(pdev,
14720                                                           persist_dma_mask);
14721                         if (err < 0) {
14722                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14723                                         "DMA for consistent allocations\n");
14724                                 goto err_out_iounmap;
14725                         }
14726                 }
14727         }
14728         if (err || dma_mask == DMA_BIT_MASK(32)) {
14729                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14730                 if (err) {
14731                         dev_err(&pdev->dev,
14732                                 "No usable DMA configuration, aborting\n");
14733                         goto err_out_iounmap;
14734                 }
14735         }
14736
14737         tg3_init_bufmgr_config(tp);
14738
14739         /* Selectively allow TSO based on operating conditions */
14740         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14741             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14742                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14743         else {
14744                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14745                 tp->fw_needed = NULL;
14746         }
14747
14748         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14749                 tp->fw_needed = FIRMWARE_TG3;
14750
14751         /* TSO is on by default on chips that support hardware TSO.
14752          * Firmware TSO on older chips gives lower performance, so it
14753          * is off by default, but can be enabled using ethtool.
14754          */
14755         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14756             (dev->features & NETIF_F_IP_CSUM)) {
14757                 dev->features |= NETIF_F_TSO;
14758                 vlan_features_add(dev, NETIF_F_TSO);
14759         }
14760         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14761             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14762                 if (dev->features & NETIF_F_IPV6_CSUM) {
14763                         dev->features |= NETIF_F_TSO6;
14764                         vlan_features_add(dev, NETIF_F_TSO6);
14765                 }
14766                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14767                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14768                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14769                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14770                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14771                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14772                         dev->features |= NETIF_F_TSO_ECN;
14773                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14774                 }
14775         }
14776
14777         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14778             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14779             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14780                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14781                 tp->rx_pending = 63;
14782         }
14783
14784         err = tg3_get_device_address(tp);
14785         if (err) {
14786                 dev_err(&pdev->dev,
14787                         "Could not obtain valid ethernet address, aborting\n");
14788                 goto err_out_iounmap;
14789         }
14790
14791         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14792                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14793                 if (!tp->aperegs) {
14794                         dev_err(&pdev->dev,
14795                                 "Cannot map APE registers, aborting\n");
14796                         err = -ENOMEM;
14797                         goto err_out_iounmap;
14798                 }
14799
14800                 tg3_ape_lock_init(tp);
14801
14802                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14803                         tg3_read_dash_ver(tp);
14804         }
14805
14806         /*
14807          * Reset chip in case UNDI or EFI driver did not shutdown
14808          * DMA self test will enable WDMAC and we'll see (spurious)
14809          * pending DMA on the PCI bus at that point.
14810          */
14811         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14812             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14813                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14814                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14815         }
14816
14817         err = tg3_test_dma(tp);
14818         if (err) {
14819                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14820                 goto err_out_apeunmap;
14821         }
14822
14823         /* flow control autonegotiation is default behavior */
14824         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14825         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14826
14827         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14828         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14829         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14830         for (i = 0; i < tp->irq_max; i++) {
14831                 struct tg3_napi *tnapi = &tp->napi[i];
14832
14833                 tnapi->tp = tp;
14834                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14835
14836                 tnapi->int_mbox = intmbx;
14837                 if (i < 4)
14838                         intmbx += 0x8;
14839                 else
14840                         intmbx += 0x4;
14841
14842                 tnapi->consmbox = rcvmbx;
14843                 tnapi->prodmbox = sndmbx;
14844
14845                 if (i)
14846                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14847                 else
14848                         tnapi->coal_now = HOSTCC_MODE_NOW;
14849
14850                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14851                         break;
14852
14853                 /*
14854                  * If we support MSIX, we'll be using RSS.  If we're using
14855                  * RSS, the first vector only handles link interrupts and the
14856                  * remaining vectors handle rx and tx interrupts.  Reuse the
14857                  * mailbox values for the next iteration.  The values we setup
14858                  * above are still useful for the single vectored mode.
14859                  */
14860                 if (!i)
14861                         continue;
14862
14863                 rcvmbx += 0x8;
14864
14865                 if (sndmbx & 0x4)
14866                         sndmbx -= 0x4;
14867                 else
14868                         sndmbx += 0xc;
14869         }
14870
14871         tg3_init_coal(tp);
14872
14873         pci_set_drvdata(pdev, dev);
14874
14875         err = register_netdev(dev);
14876         if (err) {
14877                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14878                 goto err_out_apeunmap;
14879         }
14880
14881         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14882                     tp->board_part_number,
14883                     tp->pci_chip_rev_id,
14884                     tg3_bus_string(tp, str),
14885                     dev->dev_addr);
14886
14887         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14888                 struct phy_device *phydev;
14889                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14890                 netdev_info(dev,
14891                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14892                             phydev->drv->name, dev_name(&phydev->dev));
14893         } else {
14894                 char *ethtype;
14895
14896                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14897                         ethtype = "10/100Base-TX";
14898                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14899                         ethtype = "1000Base-SX";
14900                 else
14901                         ethtype = "10/100/1000Base-T";
14902
14903                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14904                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14905                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14906         }
14907
14908         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14909                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14910                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14911                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14912                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14913                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14914         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14915                     tp->dma_rwctrl,
14916                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14917                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14918
14919         return 0;
14920
14921 err_out_apeunmap:
14922         if (tp->aperegs) {
14923                 iounmap(tp->aperegs);
14924                 tp->aperegs = NULL;
14925         }
14926
14927 err_out_iounmap:
14928         if (tp->regs) {
14929                 iounmap(tp->regs);
14930                 tp->regs = NULL;
14931         }
14932
14933 err_out_free_dev:
14934         free_netdev(dev);
14935
14936 err_out_free_res:
14937         pci_release_regions(pdev);
14938
14939 err_out_disable_pdev:
14940         pci_disable_device(pdev);
14941         pci_set_drvdata(pdev, NULL);
14942         return err;
14943 }
14944
14945 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14946 {
14947         struct net_device *dev = pci_get_drvdata(pdev);
14948
14949         if (dev) {
14950                 struct tg3 *tp = netdev_priv(dev);
14951
14952                 if (tp->fw)
14953                         release_firmware(tp->fw);
14954
14955                 flush_scheduled_work();
14956
14957                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14958                         tg3_phy_fini(tp);
14959                         tg3_mdio_fini(tp);
14960                 }
14961
14962                 unregister_netdev(dev);
14963                 if (tp->aperegs) {
14964                         iounmap(tp->aperegs);
14965                         tp->aperegs = NULL;
14966                 }
14967                 if (tp->regs) {
14968                         iounmap(tp->regs);
14969                         tp->regs = NULL;
14970                 }
14971                 free_netdev(dev);
14972                 pci_release_regions(pdev);
14973                 pci_disable_device(pdev);
14974                 pci_set_drvdata(pdev, NULL);
14975         }
14976 }
14977
14978 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14979 {
14980         struct net_device *dev = pci_get_drvdata(pdev);
14981         struct tg3 *tp = netdev_priv(dev);
14982         pci_power_t target_state;
14983         int err;
14984
14985         /* PCI register 4 needs to be saved whether netif_running() or not.
14986          * MSI address and data need to be saved if using MSI and
14987          * netif_running().
14988          */
14989         pci_save_state(pdev);
14990
14991         if (!netif_running(dev))
14992                 return 0;
14993
14994         flush_scheduled_work();
14995         tg3_phy_stop(tp);
14996         tg3_netif_stop(tp);
14997
14998         del_timer_sync(&tp->timer);
14999
15000         tg3_full_lock(tp, 1);
15001         tg3_disable_ints(tp);
15002         tg3_full_unlock(tp);
15003
15004         netif_device_detach(dev);
15005
15006         tg3_full_lock(tp, 0);
15007         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
15008         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
15009         tg3_full_unlock(tp);
15010
15011         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
15012
15013         err = tg3_set_power_state(tp, target_state);
15014         if (err) {
15015                 int err2;
15016
15017                 tg3_full_lock(tp, 0);
15018
15019                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15020                 err2 = tg3_restart_hw(tp, 1);
15021                 if (err2)
15022                         goto out;
15023
15024                 tp->timer.expires = jiffies + tp->timer_offset;
15025                 add_timer(&tp->timer);
15026
15027                 netif_device_attach(dev);
15028                 tg3_netif_start(tp);
15029
15030 out:
15031                 tg3_full_unlock(tp);
15032
15033                 if (!err2)
15034                         tg3_phy_start(tp);
15035         }
15036
15037         return err;
15038 }
15039
15040 static int tg3_resume(struct pci_dev *pdev)
15041 {
15042         struct net_device *dev = pci_get_drvdata(pdev);
15043         struct tg3 *tp = netdev_priv(dev);
15044         int err;
15045
15046         pci_restore_state(tp->pdev);
15047
15048         if (!netif_running(dev))
15049                 return 0;
15050
15051         err = tg3_set_power_state(tp, PCI_D0);
15052         if (err)
15053                 return err;
15054
15055         netif_device_attach(dev);
15056
15057         tg3_full_lock(tp, 0);
15058
15059         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
15060         err = tg3_restart_hw(tp, 1);
15061         if (err)
15062                 goto out;
15063
15064         tp->timer.expires = jiffies + tp->timer_offset;
15065         add_timer(&tp->timer);
15066
15067         tg3_netif_start(tp);
15068
15069 out:
15070         tg3_full_unlock(tp);
15071
15072         if (!err)
15073                 tg3_phy_start(tp);
15074
15075         return err;
15076 }
15077
15078 static struct pci_driver tg3_driver = {
15079         .name           = DRV_MODULE_NAME,
15080         .id_table       = tg3_pci_tbl,
15081         .probe          = tg3_init_one,
15082         .remove         = __devexit_p(tg3_remove_one),
15083         .suspend        = tg3_suspend,
15084         .resume         = tg3_resume
15085 };
15086
15087 static int __init tg3_init(void)
15088 {
15089         return pci_register_driver(&tg3_driver);
15090 }
15091
15092 static void __exit tg3_cleanup(void)
15093 {
15094         pci_unregister_driver(&tg3_driver);
15095 }
15096
15097 module_init(tg3_init);
15098 module_exit(tg3_cleanup);