drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005-2010 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/stringify.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/in.h>
  28 #include <linux/init.h>
  29 #include <linux/ioport.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/etherdevice.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/mii.h>
  36 #include <linux/phy.h>
  37 #include <linux/brcmphy.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/ip.h>
  40 #include <linux/tcp.h>
  41 #include <linux/workqueue.h>
  42 #include <linux/prefetch.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/firmware.h>
  45
  46 #include <net/checksum.h>
  47 #include <net/ip.h>
  48
  49 #include <asm/system.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52 #include <asm/uaccess.h>
  53
  54 #ifdef CONFIG_SPARC
  55 #include <asm/idprom.h>
  56 #include <asm/prom.h>
  57 #endif
  58
  59 #define BAR_0   0
  60 #define BAR_2   2
  61
  62 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  63 #define TG3_VLAN_TAG_USED 1
  64 #else
  65 #define TG3_VLAN_TAG_USED 0
  66 #endif
  67
  68 #include "tg3.h"
  69
  70 #define DRV_MODULE_NAME         "tg3"
  71 #define TG3_MAJ_NUM                     3
  72 #define TG3_MIN_NUM                     113
  73 #define DRV_MODULE_VERSION      \
  74         __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
  75 #define DRV_MODULE_RELDATE      "August 2, 2010"
  76
  77 #define TG3_DEF_MAC_MODE        0
  78 #define TG3_DEF_RX_MODE         0
  79 #define TG3_DEF_TX_MODE         0
  80 #define TG3_DEF_MSG_ENABLE        \
  81         (NETIF_MSG_DRV          | \
  82          NETIF_MSG_PROBE        | \
  83          NETIF_MSG_LINK         | \
  84          NETIF_MSG_TIMER        | \
  85          NETIF_MSG_IFDOWN       | \
  86          NETIF_MSG_IFUP         | \
  87          NETIF_MSG_RX_ERR       | \
  88          NETIF_MSG_TX_ERR)
  89
  90 /* length of time before we decide the hardware is borked,
  91  * and dev->tx_timeout() should be called to fix the problem
  92  */
  93 #define TG3_TX_TIMEOUT                  (5 * HZ)
  94
  95 /* hardware minimum and maximum for a single frame's data payload */
  96 #define TG3_MIN_MTU                     60
  97 #define TG3_MAX_MTU(tp) \
  98         ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
  99
 100 /* These numbers seem to be hard coded in the NIC firmware somehow.
 101  * You can't change the ring sizes, but you can change where you place
 102  * them in the NIC onboard memory.
 103  */
 104 #define TG3_RX_RING_SIZE                512
 105 #define TG3_DEF_RX_RING_PENDING         200
 106 #define TG3_RX_JUMBO_RING_SIZE          256
 107 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 108 #define TG3_RSS_INDIR_TBL_SIZE          128
 109
 110 /* Do not place this n-ring entries value into the tp struct itself,
 111  * we really want to expose these constants to GCC so that modulo et
 112  * al.  operations are done with shifts and masks instead of with
 113  * hw multiply/modulo instructions.  Another solution would be to
 114  * replace things like '% foo' with '& (foo - 1)'.
 115  */
 116 #define TG3_RX_RCB_RING_SIZE(tp)        \
 117         (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
 118           !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
 119
 120 #define TG3_TX_RING_SIZE                512
 121 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 122
 123 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 124                                  TG3_RX_RING_SIZE)
 125 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
 126                                  TG3_RX_JUMBO_RING_SIZE)
 127 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 128                                  TG3_RX_RCB_RING_SIZE(tp))
 129 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 130                                  TG3_TX_RING_SIZE)
 131 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 132
 133 #define TG3_RX_DMA_ALIGN                16
 134 #define TG3_RX_HEADROOM                 ALIGN(VLAN_HLEN, TG3_RX_DMA_ALIGN)
 135
 136 #define TG3_DMA_BYTE_ENAB               64
 137
 138 #define TG3_RX_STD_DMA_SZ               1536
 139 #define TG3_RX_JMB_DMA_SZ               9046
 140
 141 #define TG3_RX_DMA_TO_MAP_SZ(x)         ((x) + TG3_DMA_BYTE_ENAB)
 142
 143 #define TG3_RX_STD_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
 144 #define TG3_RX_JMB_MAP_SZ               TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
 145
 146 #define TG3_RX_STD_BUFF_RING_SIZE \
 147         (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
 148
 149 #define TG3_RX_JMB_BUFF_RING_SIZE \
 150         (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
 151
 152 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
 153  * that are at least dword aligned when used in PCIX mode.  The driver
 154  * works around this bug by double copying the packet.  This workaround
 155  * is built into the normal double copy length check for efficiency.
 156  *
 157  * However, the double copy is only necessary on those architectures
 158  * where unaligned memory accesses are inefficient.  For those architectures
 159  * where unaligned memory accesses incur little penalty, we can reintegrate
 160  * the 5701 in the normal rx path.  Doing so saves a device structure
 161  * dereference by hardcoding the double copy threshold in place.
 162  */
 163 #define TG3_RX_COPY_THRESHOLD           256
 164 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
 165         #define TG3_RX_COPY_THRESH(tp)  TG3_RX_COPY_THRESHOLD
 166 #else
 167         #define TG3_RX_COPY_THRESH(tp)  ((tp)->rx_copy_thresh)
 168 #endif
 169
 170 /* minimum number of free TX descriptors required to wake up TX process */
 171 #define TG3_TX_WAKEUP_THRESH(tnapi)             ((tnapi)->tx_pending / 4)
 172
 173 #define TG3_RAW_IP_ALIGN 2
 174
 175 /* number of ETHTOOL_GSTATS u64's */
 176 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 177
 178 #define TG3_NUM_TEST            6
 179
 180 #define TG3_FW_UPDATE_TIMEOUT_SEC       5
 181
 182 #define FIRMWARE_TG3            "tigon/tg3.bin"
 183 #define FIRMWARE_TG3TSO         "tigon/tg3_tso.bin"
 184 #define FIRMWARE_TG3TSO5        "tigon/tg3_tso5.bin"
 185
 186 static char version[] __devinitdata =
 187         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
 188
 189 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 190 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 191 MODULE_LICENSE("GPL");
 192 MODULE_VERSION(DRV_MODULE_VERSION);
 193 MODULE_FIRMWARE(FIRMWARE_TG3);
 194 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
 195 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
 196
 197 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 198 module_param(tg3_debug, int, 0);
 199 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 200
 201 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 212         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 213         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 214         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 215         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 216         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 217         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 218         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 219         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 220         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 221         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 222         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 223         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 224         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 225         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 226         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 227         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 228         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 229         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 230         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 231         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 232         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 233         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 234         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 235         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 236         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 237         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 238         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 239         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 240         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 241         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 242         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 243         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 244         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 245         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 246         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 247         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 248         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 249         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 250         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 251         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 252         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
 253         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
 254         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
 255         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
 256         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
 257         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
 258         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
 259         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
 260         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
 261         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
 262         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
 263         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
 264         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
 265         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
 266         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
 267         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
 268         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
 269         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
 270         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
 271         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791)},
 272         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795)},
 273         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
 274         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 275         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 276         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 277         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 278         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 279         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 280         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 281         {}
 282 };
 283
 284 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 285
 286 static const struct {
 287         const char string[ETH_GSTRING_LEN];
 288 } ethtool_stats_keys[TG3_NUM_STATS] = {
 289         { "rx_octets" },
 290         { "rx_fragments" },
 291         { "rx_ucast_packets" },
 292         { "rx_mcast_packets" },
 293         { "rx_bcast_packets" },
 294         { "rx_fcs_errors" },
 295         { "rx_align_errors" },
 296         { "rx_xon_pause_rcvd" },
 297         { "rx_xoff_pause_rcvd" },
 298         { "rx_mac_ctrl_rcvd" },
 299         { "rx_xoff_entered" },
 300         { "rx_frame_too_long_errors" },
 301         { "rx_jabbers" },
 302         { "rx_undersize_packets" },
 303         { "rx_in_length_errors" },
 304         { "rx_out_length_errors" },
 305         { "rx_64_or_less_octet_packets" },
 306         { "rx_65_to_127_octet_packets" },
 307         { "rx_128_to_255_octet_packets" },
 308         { "rx_256_to_511_octet_packets" },
 309         { "rx_512_to_1023_octet_packets" },
 310         { "rx_1024_to_1522_octet_packets" },
 311         { "rx_1523_to_2047_octet_packets" },
 312         { "rx_2048_to_4095_octet_packets" },
 313         { "rx_4096_to_8191_octet_packets" },
 314         { "rx_8192_to_9022_octet_packets" },
 315
 316         { "tx_octets" },
 317         { "tx_collisions" },
 318
 319         { "tx_xon_sent" },
 320         { "tx_xoff_sent" },
 321         { "tx_flow_control" },
 322         { "tx_mac_errors" },
 323         { "tx_single_collisions" },
 324         { "tx_mult_collisions" },
 325         { "tx_deferred" },
 326         { "tx_excessive_collisions" },
 327         { "tx_late_collisions" },
 328         { "tx_collide_2times" },
 329         { "tx_collide_3times" },
 330         { "tx_collide_4times" },
 331         { "tx_collide_5times" },
 332         { "tx_collide_6times" },
 333         { "tx_collide_7times" },
 334         { "tx_collide_8times" },
 335         { "tx_collide_9times" },
 336         { "tx_collide_10times" },
 337         { "tx_collide_11times" },
 338         { "tx_collide_12times" },
 339         { "tx_collide_13times" },
 340         { "tx_collide_14times" },
 341         { "tx_collide_15times" },
 342         { "tx_ucast_packets" },
 343         { "tx_mcast_packets" },
 344         { "tx_bcast_packets" },
 345         { "tx_carrier_sense_errors" },
 346         { "tx_discards" },
 347         { "tx_errors" },
 348
 349         { "dma_writeq_full" },
 350         { "dma_write_prioq_full" },
 351         { "rxbds_empty" },
 352         { "rx_discards" },
 353         { "rx_errors" },
 354         { "rx_threshold_hit" },
 355
 356         { "dma_readq_full" },
 357         { "dma_read_prioq_full" },
 358         { "tx_comp_queue_full" },
 359
 360         { "ring_set_send_prod_index" },
 361         { "ring_status_update" },
 362         { "nic_irqs" },
 363         { "nic_avoided_irqs" },
 364         { "nic_tx_threshold_hit" }
 365 };
 366
 367 static const struct {
 368         const char string[ETH_GSTRING_LEN];
 369 } ethtool_test_keys[TG3_NUM_TEST] = {
 370         { "nvram test     (online) " },
 371         { "link test      (online) " },
 372         { "register test  (offline)" },
 373         { "memory test    (offline)" },
 374         { "loopback test  (offline)" },
 375         { "interrupt test (offline)" },
 376 };
 377
 378 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 379 {
 380         writel(val, tp->regs + off);
 381 }
 382
 383 static u32 tg3_read32(struct tg3 *tp, u32 off)
 384 {
 385         return readl(tp->regs + off);
 386 }
 387
 388 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
 389 {
 390         writel(val, tp->aperegs + off);
 391 }
 392
 393 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
 394 {
 395         return readl(tp->aperegs + off);
 396 }
 397
 398 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 399 {
 400         unsigned long flags;
 401
 402         spin_lock_irqsave(&tp->indirect_lock, flags);
 403         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 404         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 405         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 406 }
 407
 408 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 409 {
 410         writel(val, tp->regs + off);
 411         readl(tp->regs + off);
 412 }
 413
 414 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 415 {
 416         unsigned long flags;
 417         u32 val;
 418
 419         spin_lock_irqsave(&tp->indirect_lock, flags);
 420         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 421         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 422         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 423         return val;
 424 }
 425
 426 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 427 {
 428         unsigned long flags;
 429
 430         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 431                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 432                                        TG3_64BIT_REG_LOW, val);
 433                 return;
 434         }
 435         if (off == TG3_RX_STD_PROD_IDX_REG) {
 436                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 437                                        TG3_64BIT_REG_LOW, val);
 438                 return;
 439         }
 440
 441         spin_lock_irqsave(&tp->indirect_lock, flags);
 442         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 443         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 444         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 445
 446         /* In indirect mode when disabling interrupts, we also need
 447          * to clear the interrupt bit in the GRC local ctrl register.
 448          */
 449         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 450             (val == 0x1)) {
 451                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 452                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 453         }
 454 }
 455
 456 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 457 {
 458         unsigned long flags;
 459         u32 val;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 463         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 464         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 465         return val;
 466 }
 467
 468 /* usec_wait specifies the wait time in usec when writing to certain registers
 469  * where it is unsafe to read back the register without some delay.
 470  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 471  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 472  */
 473 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 474 {
 475         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 476             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 477                 /* Non-posted methods */
 478                 tp->write32(tp, off, val);
 479         else {
 480                 /* Posted method */
 481                 tg3_write32(tp, off, val);
 482                 if (usec_wait)
 483                         udelay(usec_wait);
 484                 tp->read32(tp, off);
 485         }
 486         /* Wait again after the read for the posted method to guarantee that
 487          * the wait time is met.
 488          */
 489         if (usec_wait)
 490                 udelay(usec_wait);
 491 }
 492
 493 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 494 {
 495         tp->write32_mbox(tp, off, val);
 496         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 497             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 498                 tp->read32_mbox(tp, off);
 499 }
 500
 501 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 502 {
 503         void __iomem *mbox = tp->regs + off;
 504         writel(val, mbox);
 505         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 506                 writel(val, mbox);
 507         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 508                 readl(mbox);
 509 }
 510
 511 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 512 {
 513         return readl(tp->regs + off + GRCMBOX_BASE);
 514 }
 515
 516 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 517 {
 518         writel(val, tp->regs + off + GRCMBOX_BASE);
 519 }
 520
 521 #define tw32_mailbox(reg, val)          tp->write32_mbox(tp, reg, val)
 522 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 523 #define tw32_rx_mbox(reg, val)          tp->write32_rx_mbox(tp, reg, val)
 524 #define tw32_tx_mbox(reg, val)          tp->write32_tx_mbox(tp, reg, val)
 525 #define tr32_mailbox(reg)               tp->read32_mbox(tp, reg)
 526
 527 #define tw32(reg, val)                  tp->write32(tp, reg, val)
 528 #define tw32_f(reg, val)                _tw32_flush(tp, (reg), (val), 0)
 529 #define tw32_wait_f(reg, val, us)       _tw32_flush(tp, (reg), (val), (us))
 530 #define tr32(reg)                       tp->read32(tp, reg)
 531
 532 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 533 {
 534         unsigned long flags;
 535
 536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 537             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 538                 return;
 539
 540         spin_lock_irqsave(&tp->indirect_lock, flags);
 541         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 542                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 543                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 544
 545                 /* Always leave this as zero. */
 546                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 547         } else {
 548                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 549                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 550
 551                 /* Always leave this as zero. */
 552                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 553         }
 554         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 555 }
 556
 557 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 558 {
 559         unsigned long flags;
 560
 561         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 562             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 563                 *val = 0;
 564                 return;
 565         }
 566
 567         spin_lock_irqsave(&tp->indirect_lock, flags);
 568         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 569                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 570                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 571
 572                 /* Always leave this as zero. */
 573                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 574         } else {
 575                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 576                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 577
 578                 /* Always leave this as zero. */
 579                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 580         }
 581         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 582 }
 583
 584 static void tg3_ape_lock_init(struct tg3 *tp)
 585 {
 586         int i;
 587         u32 regbase;
 588
 589         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 590                 regbase = TG3_APE_LOCK_GRANT;
 591         else
 592                 regbase = TG3_APE_PER_LOCK_GRANT;
 593
 594         /* Make sure the driver hasn't any stale locks. */
 595         for (i = 0; i < 8; i++)
 596                 tg3_ape_write32(tp, regbase + 4 * i, APE_LOCK_GRANT_DRIVER);
 597 }
 598
 599 static int tg3_ape_lock(struct tg3 *tp, int locknum)
 600 {
 601         int i, off;
 602         int ret = 0;
 603         u32 status, req, gnt;
 604
 605         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 606                 return 0;
 607
 608         switch (locknum) {
 609         case TG3_APE_LOCK_GRC:
 610         case TG3_APE_LOCK_MEM:
 611                 break;
 612         default:
 613                 return -EINVAL;
 614         }
 615
 616         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
 617                 req = TG3_APE_LOCK_REQ;
 618                 gnt = TG3_APE_LOCK_GRANT;
 619         } else {
 620                 req = TG3_APE_PER_LOCK_REQ;
 621                 gnt = TG3_APE_PER_LOCK_GRANT;
 622         }
 623
 624         off = 4 * locknum;
 625
 626         tg3_ape_write32(tp, req + off, APE_LOCK_REQ_DRIVER);
 627
 628         /* Wait for up to 1 millisecond to acquire lock. */
 629         for (i = 0; i < 100; i++) {
 630                 status = tg3_ape_read32(tp, gnt + off);
 631                 if (status == APE_LOCK_GRANT_DRIVER)
 632                         break;
 633                 udelay(10);
 634         }
 635
 636         if (status != APE_LOCK_GRANT_DRIVER) {
 637                 /* Revoke the lock request. */
 638                 tg3_ape_write32(tp, gnt + off,
 639                                 APE_LOCK_GRANT_DRIVER);
 640
 641                 ret = -EBUSY;
 642         }
 643
 644         return ret;
 645 }
 646
 647 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
 648 {
 649         u32 gnt;
 650
 651         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
 652                 return;
 653
 654         switch (locknum) {
 655         case TG3_APE_LOCK_GRC:
 656         case TG3_APE_LOCK_MEM:
 657                 break;
 658         default:
 659                 return;
 660         }
 661
 662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
 663                 gnt = TG3_APE_LOCK_GRANT;
 664         else
 665                 gnt = TG3_APE_PER_LOCK_GRANT;
 666
 667         tg3_ape_write32(tp, gnt + 4 * locknum, APE_LOCK_GRANT_DRIVER);
 668 }
 669
 670 static void tg3_disable_ints(struct tg3 *tp)
 671 {
 672         int i;
 673
 674         tw32(TG3PCI_MISC_HOST_CTRL,
 675              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 676         for (i = 0; i < tp->irq_max; i++)
 677                 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
 678 }
 679
 680 static void tg3_enable_ints(struct tg3 *tp)
 681 {
 682         int i;
 683
 684         tp->irq_sync = 0;
 685         wmb();
 686
 687         tw32(TG3PCI_MISC_HOST_CTRL,
 688              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 689
 690         tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
 691         for (i = 0; i < tp->irq_cnt; i++) {
 692                 struct tg3_napi *tnapi = &tp->napi[i];
 693
 694                 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 695                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 696                         tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
 697
 698                 tp->coal_now |= tnapi->coal_now;
 699         }
 700
 701         /* Force an initial interrupt */
 702         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 703             (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
 704                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 705         else
 706                 tw32(HOSTCC_MODE, tp->coal_now);
 707
 708         tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
 709 }
 710
 711 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
 712 {
 713         struct tg3 *tp = tnapi->tp;
 714         struct tg3_hw_status *sblk = tnapi->hw_status;
 715         unsigned int work_exists = 0;
 716
 717         /* check for phy events */
 718         if (!(tp->tg3_flags &
 719               (TG3_FLAG_USE_LINKCHG_REG |
 720                TG3_FLAG_POLL_SERDES))) {
 721                 if (sblk->status & SD_STATUS_LINK_CHG)
 722                         work_exists = 1;
 723         }
 724         /* check for RX/TX work to do */
 725         if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
 726             *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
 727                 work_exists = 1;
 728
 729         return work_exists;
 730 }
 731
 732 /* tg3_int_reenable
 733  *  similar to tg3_enable_ints, but it accurately determines whether there
 734  *  is new work pending and can return without flushing the PIO write
 735  *  which reenables interrupts
 736  */
 737 static void tg3_int_reenable(struct tg3_napi *tnapi)
 738 {
 739         struct tg3 *tp = tnapi->tp;
 740
 741         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
 742         mmiowb();
 743
 744         /* When doing tagged status, this work check is unnecessary.
 745          * The last_tag we write above tells the chip which piece of
 746          * work we've completed.
 747          */
 748         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 749             tg3_has_work(tnapi))
 750                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 751                      HOSTCC_MODE_ENABLE | tnapi->coal_now);
 752 }
 753
 754 static void tg3_switch_clocks(struct tg3 *tp)
 755 {
 756         u32 clock_ctrl;
 757         u32 orig_clock_ctrl;
 758
 759         if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
 760             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
 761                 return;
 762
 763         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 764
 765         orig_clock_ctrl = clock_ctrl;
 766         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 767                        CLOCK_CTRL_CLKRUN_OENABLE |
 768                        0x1f);
 769         tp->pci_clock_ctrl = clock_ctrl;
 770
 771         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 772                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 773                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 774                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 775                 }
 776         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 777                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 778                             clock_ctrl |
 779                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 780                             40);
 781                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 782                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 783                             40);
 784         }
 785         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 786 }
 787
 788 #define PHY_BUSY_LOOPS  5000
 789
 790 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 791 {
 792         u32 frame_val;
 793         unsigned int loops;
 794         int ret;
 795
 796         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 797                 tw32_f(MAC_MI_MODE,
 798                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 799                 udelay(80);
 800         }
 801
 802         *val = 0x0;
 803
 804         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 805                       MI_COM_PHY_ADDR_MASK);
 806         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 807                       MI_COM_REG_ADDR_MASK);
 808         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 809
 810         tw32_f(MAC_MI_COM, frame_val);
 811
 812         loops = PHY_BUSY_LOOPS;
 813         while (loops != 0) {
 814                 udelay(10);
 815                 frame_val = tr32(MAC_MI_COM);
 816
 817                 if ((frame_val & MI_COM_BUSY) == 0) {
 818                         udelay(5);
 819                         frame_val = tr32(MAC_MI_COM);
 820                         break;
 821                 }
 822                 loops -= 1;
 823         }
 824
 825         ret = -EBUSY;
 826         if (loops != 0) {
 827                 *val = frame_val & MI_COM_DATA_MASK;
 828                 ret = 0;
 829         }
 830
 831         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 832                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 833                 udelay(80);
 834         }
 835
 836         return ret;
 837 }
 838
 839 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 840 {
 841         u32 frame_val;
 842         unsigned int loops;
 843         int ret;
 844
 845         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 846             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 847                 return 0;
 848
 849         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 850                 tw32_f(MAC_MI_MODE,
 851                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 852                 udelay(80);
 853         }
 854
 855         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 856                       MI_COM_PHY_ADDR_MASK);
 857         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 858                       MI_COM_REG_ADDR_MASK);
 859         frame_val |= (val & MI_COM_DATA_MASK);
 860         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 861
 862         tw32_f(MAC_MI_COM, frame_val);
 863
 864         loops = PHY_BUSY_LOOPS;
 865         while (loops != 0) {
 866                 udelay(10);
 867                 frame_val = tr32(MAC_MI_COM);
 868                 if ((frame_val & MI_COM_BUSY) == 0) {
 869                         udelay(5);
 870                         frame_val = tr32(MAC_MI_COM);
 871                         break;
 872                 }
 873                 loops -= 1;
 874         }
 875
 876         ret = -EBUSY;
 877         if (loops != 0)
 878                 ret = 0;
 879
 880         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 881                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 882                 udelay(80);
 883         }
 884
 885         return ret;
 886 }
 887
 888 static int tg3_bmcr_reset(struct tg3 *tp)
 889 {
 890         u32 phy_control;
 891         int limit, err;
 892
 893         /* OK, reset it, and poll the BMCR_RESET bit until it
 894          * clears or we time out.
 895          */
 896         phy_control = BMCR_RESET;
 897         err = tg3_writephy(tp, MII_BMCR, phy_control);
 898         if (err != 0)
 899                 return -EBUSY;
 900
 901         limit = 5000;
 902         while (limit--) {
 903                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 904                 if (err != 0)
 905                         return -EBUSY;
 906
 907                 if ((phy_control & BMCR_RESET) == 0) {
 908                         udelay(40);
 909                         break;
 910                 }
 911                 udelay(10);
 912         }
 913         if (limit < 0)
 914                 return -EBUSY;
 915
 916         return 0;
 917 }
 918
 919 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
 920 {
 921         struct tg3 *tp = bp->priv;
 922         u32 val;
 923
 924         spin_lock_bh(&tp->lock);
 925
 926         if (tg3_readphy(tp, reg, &val))
 927                 val = -EIO;
 928
 929         spin_unlock_bh(&tp->lock);
 930
 931         return val;
 932 }
 933
 934 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
 935 {
 936         struct tg3 *tp = bp->priv;
 937         u32 ret = 0;
 938
 939         spin_lock_bh(&tp->lock);
 940
 941         if (tg3_writephy(tp, reg, val))
 942                 ret = -EIO;
 943
 944         spin_unlock_bh(&tp->lock);
 945
 946         return ret;
 947 }
 948
 949 static int tg3_mdio_reset(struct mii_bus *bp)
 950 {
 951         return 0;
 952 }
 953
 954 static void tg3_mdio_config_5785(struct tg3 *tp)
 955 {
 956         u32 val;
 957         struct phy_device *phydev;
 958
 959         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
 960         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
 961         case PHY_ID_BCM50610:
 962         case PHY_ID_BCM50610M:
 963                 val = MAC_PHYCFG2_50610_LED_MODES;
 964                 break;
 965         case PHY_ID_BCMAC131:
 966                 val = MAC_PHYCFG2_AC131_LED_MODES;
 967                 break;
 968         case PHY_ID_RTL8211C:
 969                 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
 970                 break;
 971         case PHY_ID_RTL8201E:
 972                 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
 973                 break;
 974         default:
 975                 return;
 976         }
 977
 978         if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
 979                 tw32(MAC_PHYCFG2, val);
 980
 981                 val = tr32(MAC_PHYCFG1);
 982                 val &= ~(MAC_PHYCFG1_RGMII_INT |
 983                          MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
 984                 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
 985                 tw32(MAC_PHYCFG1, val);
 986
 987                 return;
 988         }
 989
 990         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE))
 991                 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
 992                        MAC_PHYCFG2_FMODE_MASK_MASK |
 993                        MAC_PHYCFG2_GMODE_MASK_MASK |
 994                        MAC_PHYCFG2_ACT_MASK_MASK   |
 995                        MAC_PHYCFG2_QUAL_MASK_MASK |
 996                        MAC_PHYCFG2_INBAND_ENABLE;
 997
 998         tw32(MAC_PHYCFG2, val);
 999
1000         val = tr32(MAC_PHYCFG1);
1001         val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1002                  MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1003         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1004                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1005                         val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1006                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1007                         val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1008         }
1009         val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1010                MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1011         tw32(MAC_PHYCFG1, val);
1012
1013         val = tr32(MAC_EXT_RGMII_MODE);
1014         val &= ~(MAC_RGMII_MODE_RX_INT_B |
1015                  MAC_RGMII_MODE_RX_QUALITY |
1016                  MAC_RGMII_MODE_RX_ACTIVITY |
1017                  MAC_RGMII_MODE_RX_ENG_DET |
1018                  MAC_RGMII_MODE_TX_ENABLE |
1019                  MAC_RGMII_MODE_TX_LOWPWR |
1020                  MAC_RGMII_MODE_TX_RESET);
1021         if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)) {
1022                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1023                         val |= MAC_RGMII_MODE_RX_INT_B |
1024                                MAC_RGMII_MODE_RX_QUALITY |
1025                                MAC_RGMII_MODE_RX_ACTIVITY |
1026                                MAC_RGMII_MODE_RX_ENG_DET;
1027                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1028                         val |= MAC_RGMII_MODE_TX_ENABLE |
1029                                MAC_RGMII_MODE_TX_LOWPWR |
1030                                MAC_RGMII_MODE_TX_RESET;
1031         }
1032         tw32(MAC_EXT_RGMII_MODE, val);
1033 }
1034
1035 static void tg3_mdio_start(struct tg3 *tp)
1036 {
1037         tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1038         tw32_f(MAC_MI_MODE, tp->mi_mode);
1039         udelay(80);
1040
1041         if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1042             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1043                 tg3_mdio_config_5785(tp);
1044 }
1045
1046 static int tg3_mdio_init(struct tg3 *tp)
1047 {
1048         int i;
1049         u32 reg;
1050         struct phy_device *phydev;
1051
1052         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
1054                 u32 is_serdes;
1055
1056                 tp->phy_addr = PCI_FUNC(tp->pdev->devfn) + 1;
1057
1058                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1059                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1060                 else
1061                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1062                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
1063                 if (is_serdes)
1064                         tp->phy_addr += 7;
1065         } else
1066                 tp->phy_addr = TG3_PHY_MII_ADDR;
1067
1068         tg3_mdio_start(tp);
1069
1070         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1071             (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1072                 return 0;
1073
1074         tp->mdio_bus = mdiobus_alloc();
1075         if (tp->mdio_bus == NULL)
1076                 return -ENOMEM;
1077
1078         tp->mdio_bus->name     = "tg3 mdio bus";
1079         snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1080                  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1081         tp->mdio_bus->priv     = tp;
1082         tp->mdio_bus->parent   = &tp->pdev->dev;
1083         tp->mdio_bus->read     = &tg3_mdio_read;
1084         tp->mdio_bus->write    = &tg3_mdio_write;
1085         tp->mdio_bus->reset    = &tg3_mdio_reset;
1086         tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1087         tp->mdio_bus->irq      = &tp->mdio_irq[0];
1088
1089         for (i = 0; i < PHY_MAX_ADDR; i++)
1090                 tp->mdio_bus->irq[i] = PHY_POLL;
1091
1092         /* The bus registration will look for all the PHYs on the mdio bus.
1093          * Unfortunately, it does not ensure the PHY is powered up before
1094          * accessing the PHY ID registers.  A chip reset is the
1095          * quickest way to bring the device back to an operational state..
1096          */
1097         if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1098                 tg3_bmcr_reset(tp);
1099
1100         i = mdiobus_register(tp->mdio_bus);
1101         if (i) {
1102                 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1103                 mdiobus_free(tp->mdio_bus);
1104                 return i;
1105         }
1106
1107         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1108
1109         if (!phydev || !phydev->drv) {
1110                 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1111                 mdiobus_unregister(tp->mdio_bus);
1112                 mdiobus_free(tp->mdio_bus);
1113                 return -ENODEV;
1114         }
1115
1116         switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1117         case PHY_ID_BCM57780:
1118                 phydev->interface = PHY_INTERFACE_MODE_GMII;
1119                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1120                 break;
1121         case PHY_ID_BCM50610:
1122         case PHY_ID_BCM50610M:
1123                 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1124                                      PHY_BRCM_RX_REFCLK_UNUSED |
1125                                      PHY_BRCM_DIS_TXCRXC_NOENRGY |
1126                                      PHY_BRCM_AUTO_PWRDWN_ENABLE;
1127                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_INBAND_DISABLE)
1128                         phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1129                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1130                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1131                 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1132                         phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1133                 /* fallthru */
1134         case PHY_ID_RTL8211C:
1135                 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1136                 break;
1137         case PHY_ID_RTL8201E:
1138         case PHY_ID_BCMAC131:
1139                 phydev->interface = PHY_INTERFACE_MODE_MII;
1140                 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1141                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1142                 break;
1143         }
1144
1145         tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1146
1147         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1148                 tg3_mdio_config_5785(tp);
1149
1150         return 0;
1151 }
1152
1153 static void tg3_mdio_fini(struct tg3 *tp)
1154 {
1155         if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1156                 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1157                 mdiobus_unregister(tp->mdio_bus);
1158                 mdiobus_free(tp->mdio_bus);
1159         }
1160 }
1161
1162 /* tp->lock is held. */
1163 static inline void tg3_generate_fw_event(struct tg3 *tp)
1164 {
1165         u32 val;
1166
1167         val = tr32(GRC_RX_CPU_EVENT);
1168         val |= GRC_RX_CPU_DRIVER_EVENT;
1169         tw32_f(GRC_RX_CPU_EVENT, val);
1170
1171         tp->last_event_jiffies = jiffies;
1172 }
1173
1174 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1175
1176 /* tp->lock is held. */
1177 static void tg3_wait_for_event_ack(struct tg3 *tp)
1178 {
1179         int i;
1180         unsigned int delay_cnt;
1181         long time_remain;
1182
1183         /* If enough time has passed, no wait is necessary. */
1184         time_remain = (long)(tp->last_event_jiffies + 1 +
1185                       usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1186                       (long)jiffies;
1187         if (time_remain < 0)
1188                 return;
1189
1190         /* Check if we can shorten the wait time. */
1191         delay_cnt = jiffies_to_usecs(time_remain);
1192         if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1193                 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1194         delay_cnt = (delay_cnt >> 3) + 1;
1195
1196         for (i = 0; i < delay_cnt; i++) {
1197                 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1198                         break;
1199                 udelay(8);
1200         }
1201 }
1202
1203 /* tp->lock is held. */
1204 static void tg3_ump_link_report(struct tg3 *tp)
1205 {
1206         u32 reg;
1207         u32 val;
1208
1209         if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1210             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
1211                 return;
1212
1213         tg3_wait_for_event_ack(tp);
1214
1215         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1216
1217         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1218
1219         val = 0;
1220         if (!tg3_readphy(tp, MII_BMCR, &reg))
1221                 val = reg << 16;
1222         if (!tg3_readphy(tp, MII_BMSR, &reg))
1223                 val |= (reg & 0xffff);
1224         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1225
1226         val = 0;
1227         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1228                 val = reg << 16;
1229         if (!tg3_readphy(tp, MII_LPA, &reg))
1230                 val |= (reg & 0xffff);
1231         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1232
1233         val = 0;
1234         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1235                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1236                         val = reg << 16;
1237                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1238                         val |= (reg & 0xffff);
1239         }
1240         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1241
1242         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1243                 val = reg << 16;
1244         else
1245                 val = 0;
1246         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1247
1248         tg3_generate_fw_event(tp);
1249 }
1250
1251 static void tg3_link_report(struct tg3 *tp)
1252 {
1253         if (!netif_carrier_ok(tp->dev)) {
1254                 netif_info(tp, link, tp->dev, "Link is down\n");
1255                 tg3_ump_link_report(tp);
1256         } else if (netif_msg_link(tp)) {
1257                 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1258                             (tp->link_config.active_speed == SPEED_1000 ?
1259                              1000 :
1260                              (tp->link_config.active_speed == SPEED_100 ?
1261                               100 : 10)),
1262                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1263                              "full" : "half"));
1264
1265                 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1266                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1267                             "on" : "off",
1268                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1269                             "on" : "off");
1270                 tg3_ump_link_report(tp);
1271         }
1272 }
1273
1274 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1275 {
1276         u16 miireg;
1277
1278         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1279                 miireg = ADVERTISE_PAUSE_CAP;
1280         else if (flow_ctrl & FLOW_CTRL_TX)
1281                 miireg = ADVERTISE_PAUSE_ASYM;
1282         else if (flow_ctrl & FLOW_CTRL_RX)
1283                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1284         else
1285                 miireg = 0;
1286
1287         return miireg;
1288 }
1289
1290 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1291 {
1292         u16 miireg;
1293
1294         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1295                 miireg = ADVERTISE_1000XPAUSE;
1296         else if (flow_ctrl & FLOW_CTRL_TX)
1297                 miireg = ADVERTISE_1000XPSE_ASYM;
1298         else if (flow_ctrl & FLOW_CTRL_RX)
1299                 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1300         else
1301                 miireg = 0;
1302
1303         return miireg;
1304 }
1305
1306 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1307 {
1308         u8 cap = 0;
1309
1310         if (lcladv & ADVERTISE_1000XPAUSE) {
1311                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1312                         if (rmtadv & LPA_1000XPAUSE)
1313                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1314                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1315                                 cap = FLOW_CTRL_RX;
1316                 } else {
1317                         if (rmtadv & LPA_1000XPAUSE)
1318                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1319                 }
1320         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1321                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1322                         cap = FLOW_CTRL_TX;
1323         }
1324
1325         return cap;
1326 }
1327
1328 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1329 {
1330         u8 autoneg;
1331         u8 flowctrl = 0;
1332         u32 old_rx_mode = tp->rx_mode;
1333         u32 old_tx_mode = tp->tx_mode;
1334
1335         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1336                 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1337         else
1338                 autoneg = tp->link_config.autoneg;
1339
1340         if (autoneg == AUTONEG_ENABLE &&
1341             (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1342                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1343                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1344                 else
1345                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1346         } else
1347                 flowctrl = tp->link_config.flowctrl;
1348
1349         tp->link_config.active_flowctrl = flowctrl;
1350
1351         if (flowctrl & FLOW_CTRL_RX)
1352                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1353         else
1354                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1355
1356         if (old_rx_mode != tp->rx_mode)
1357                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1358
1359         if (flowctrl & FLOW_CTRL_TX)
1360                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1361         else
1362                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1363
1364         if (old_tx_mode != tp->tx_mode)
1365                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1366 }
1367
1368 static void tg3_adjust_link(struct net_device *dev)
1369 {
1370         u8 oldflowctrl, linkmesg = 0;
1371         u32 mac_mode, lcl_adv, rmt_adv;
1372         struct tg3 *tp = netdev_priv(dev);
1373         struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1374
1375         spin_lock_bh(&tp->lock);
1376
1377         mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1378                                     MAC_MODE_HALF_DUPLEX);
1379
1380         oldflowctrl = tp->link_config.active_flowctrl;
1381
1382         if (phydev->link) {
1383                 lcl_adv = 0;
1384                 rmt_adv = 0;
1385
1386                 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1387                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1388                 else if (phydev->speed == SPEED_1000 ||
1389                          GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1390                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
1391                 else
1392                         mac_mode |= MAC_MODE_PORT_MODE_MII;
1393
1394                 if (phydev->duplex == DUPLEX_HALF)
1395                         mac_mode |= MAC_MODE_HALF_DUPLEX;
1396                 else {
1397                         lcl_adv = tg3_advert_flowctrl_1000T(
1398                                   tp->link_config.flowctrl);
1399
1400                         if (phydev->pause)
1401                                 rmt_adv = LPA_PAUSE_CAP;
1402                         if (phydev->asym_pause)
1403                                 rmt_adv |= LPA_PAUSE_ASYM;
1404                 }
1405
1406                 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1407         } else
1408                 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1409
1410         if (mac_mode != tp->mac_mode) {
1411                 tp->mac_mode = mac_mode;
1412                 tw32_f(MAC_MODE, tp->mac_mode);
1413                 udelay(40);
1414         }
1415
1416         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1417                 if (phydev->speed == SPEED_10)
1418                         tw32(MAC_MI_STAT,
1419                              MAC_MI_STAT_10MBPS_MODE |
1420                              MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1421                 else
1422                         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1423         }
1424
1425         if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1426                 tw32(MAC_TX_LENGTHS,
1427                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428                       (6 << TX_LENGTHS_IPG_SHIFT) |
1429                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1430         else
1431                 tw32(MAC_TX_LENGTHS,
1432                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1433                       (6 << TX_LENGTHS_IPG_SHIFT) |
1434                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1435
1436         if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1437             (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1438             phydev->speed != tp->link_config.active_speed ||
1439             phydev->duplex != tp->link_config.active_duplex ||
1440             oldflowctrl != tp->link_config.active_flowctrl)
1441                 linkmesg = 1;
1442
1443         tp->link_config.active_speed = phydev->speed;
1444         tp->link_config.active_duplex = phydev->duplex;
1445
1446         spin_unlock_bh(&tp->lock);
1447
1448         if (linkmesg)
1449                 tg3_link_report(tp);
1450 }
1451
1452 static int tg3_phy_init(struct tg3 *tp)
1453 {
1454         struct phy_device *phydev;
1455
1456         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
1457                 return 0;
1458
1459         /* Bring the PHY back to a known state. */
1460         tg3_bmcr_reset(tp);
1461
1462         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1463
1464         /* Attach the MAC to the PHY. */
1465         phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1466                              phydev->dev_flags, phydev->interface);
1467         if (IS_ERR(phydev)) {
1468                 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1469                 return PTR_ERR(phydev);
1470         }
1471
1472         /* Mask with MAC supported features. */
1473         switch (phydev->interface) {
1474         case PHY_INTERFACE_MODE_GMII:
1475         case PHY_INTERFACE_MODE_RGMII:
1476                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1477                         phydev->supported &= (PHY_GBIT_FEATURES |
1478                                               SUPPORTED_Pause |
1479                                               SUPPORTED_Asym_Pause);
1480                         break;
1481                 }
1482                 /* fallthru */
1483         case PHY_INTERFACE_MODE_MII:
1484                 phydev->supported &= (PHY_BASIC_FEATURES |
1485                                       SUPPORTED_Pause |
1486                                       SUPPORTED_Asym_Pause);
1487                 break;
1488         default:
1489                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1490                 return -EINVAL;
1491         }
1492
1493         tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
1494
1495         phydev->advertising = phydev->supported;
1496
1497         return 0;
1498 }
1499
1500 static void tg3_phy_start(struct tg3 *tp)
1501 {
1502         struct phy_device *phydev;
1503
1504         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1505                 return;
1506
1507         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1508
1509         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
1510                 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
1511                 phydev->speed = tp->link_config.orig_speed;
1512                 phydev->duplex = tp->link_config.orig_duplex;
1513                 phydev->autoneg = tp->link_config.orig_autoneg;
1514                 phydev->advertising = tp->link_config.orig_advertising;
1515         }
1516
1517         phy_start(phydev);
1518
1519         phy_start_aneg(phydev);
1520 }
1521
1522 static void tg3_phy_stop(struct tg3 *tp)
1523 {
1524         if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
1525                 return;
1526
1527         phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1528 }
1529
1530 static void tg3_phy_fini(struct tg3 *tp)
1531 {
1532         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
1533                 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1534                 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
1535         }
1536 }
1537
1538 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1539 {
1540         int err;
1541
1542         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1543         if (!err)
1544                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1545
1546         return err;
1547 }
1548
1549 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1550 {
1551         u32 phytest;
1552
1553         if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1554                 u32 phy;
1555
1556                 tg3_writephy(tp, MII_TG3_FET_TEST,
1557                              phytest | MII_TG3_FET_SHADOW_EN);
1558                 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1559                         if (enable)
1560                                 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1561                         else
1562                                 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1563                         tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1564                 }
1565                 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1566         }
1567 }
1568
1569 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1570 {
1571         u32 reg;
1572
1573         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1574             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1575               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1576              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
1577                 return;
1578
1579         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1580                 tg3_phy_fet_toggle_apd(tp, enable);
1581                 return;
1582         }
1583
1584         reg = MII_TG3_MISC_SHDW_WREN |
1585               MII_TG3_MISC_SHDW_SCR5_SEL |
1586               MII_TG3_MISC_SHDW_SCR5_LPED |
1587               MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1588               MII_TG3_MISC_SHDW_SCR5_SDTL |
1589               MII_TG3_MISC_SHDW_SCR5_C125OE;
1590         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1591                 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1592
1593         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594
1595
1596         reg = MII_TG3_MISC_SHDW_WREN |
1597               MII_TG3_MISC_SHDW_APD_SEL |
1598               MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1599         if (enable)
1600                 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1601
1602         tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1603 }
1604
1605 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1606 {
1607         u32 phy;
1608
1609         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1610             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
1611                 return;
1612
1613         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1614                 u32 ephy;
1615
1616                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1617                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1618
1619                         tg3_writephy(tp, MII_TG3_FET_TEST,
1620                                      ephy | MII_TG3_FET_SHADOW_EN);
1621                         if (!tg3_readphy(tp, reg, &phy)) {
1622                                 if (enable)
1623                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1624                                 else
1625                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1626                                 tg3_writephy(tp, reg, phy);
1627                         }
1628                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1629                 }
1630         } else {
1631                 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1632                       MII_TG3_AUXCTL_SHDWSEL_MISC;
1633                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1634                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1635                         if (enable)
1636                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1637                         else
1638                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1639                         phy |= MII_TG3_AUXCTL_MISC_WREN;
1640                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1641                 }
1642         }
1643 }
1644
1645 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1646 {
1647         u32 val;
1648
1649         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
1650                 return;
1651
1652         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1653             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1654                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1655                              (val | (1 << 15) | (1 << 4)));
1656 }
1657
1658 static void tg3_phy_apply_otp(struct tg3 *tp)
1659 {
1660         u32 otp, phy;
1661
1662         if (!tp->phy_otp)
1663                 return;
1664
1665         otp = tp->phy_otp;
1666
1667         /* Enable SM_DSP clock and tx 6dB coding. */
1668         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1669               MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1670               MII_TG3_AUXCTL_ACTL_TX_6DB;
1671         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1672
1673         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1674         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1675         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1676
1677         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1678               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1679         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1680
1681         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1682         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1683         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1684
1685         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1686         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1687
1688         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1689         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1690
1691         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1692               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1693         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1694
1695         /* Turn off SM_DSP clock. */
1696         phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1697               MII_TG3_AUXCTL_ACTL_TX_6DB;
1698         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1699 }
1700
1701 static int tg3_wait_macro_done(struct tg3 *tp)
1702 {
1703         int limit = 100;
1704
1705         while (limit--) {
1706                 u32 tmp32;
1707
1708                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
1709                         if ((tmp32 & 0x1000) == 0)
1710                                 break;
1711                 }
1712         }
1713         if (limit < 0)
1714                 return -EBUSY;
1715
1716         return 0;
1717 }
1718
1719 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1720 {
1721         static const u32 test_pat[4][6] = {
1722         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1723         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1724         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1725         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1726         };
1727         int chan;
1728
1729         for (chan = 0; chan < 4; chan++) {
1730                 int i;
1731
1732                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1733                              (chan * 0x2000) | 0x0200);
1734                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1735
1736                 for (i = 0; i < 6; i++)
1737                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1738                                      test_pat[chan][i]);
1739
1740                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1741                 if (tg3_wait_macro_done(tp)) {
1742                         *resetp = 1;
1743                         return -EBUSY;
1744                 }
1745
1746                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1747                              (chan * 0x2000) | 0x0200);
1748                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
1749                 if (tg3_wait_macro_done(tp)) {
1750                         *resetp = 1;
1751                         return -EBUSY;
1752                 }
1753
1754                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
1755                 if (tg3_wait_macro_done(tp)) {
1756                         *resetp = 1;
1757                         return -EBUSY;
1758                 }
1759
1760                 for (i = 0; i < 6; i += 2) {
1761                         u32 low, high;
1762
1763                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1764                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1765                             tg3_wait_macro_done(tp)) {
1766                                 *resetp = 1;
1767                                 return -EBUSY;
1768                         }
1769                         low &= 0x7fff;
1770                         high &= 0x000f;
1771                         if (low != test_pat[chan][i] ||
1772                             high != test_pat[chan][i+1]) {
1773                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1774                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1775                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1776
1777                                 return -EBUSY;
1778                         }
1779                 }
1780         }
1781
1782         return 0;
1783 }
1784
1785 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1786 {
1787         int chan;
1788
1789         for (chan = 0; chan < 4; chan++) {
1790                 int i;
1791
1792                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1793                              (chan * 0x2000) | 0x0200);
1794                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
1795                 for (i = 0; i < 6; i++)
1796                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1797                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
1798                 if (tg3_wait_macro_done(tp))
1799                         return -EBUSY;
1800         }
1801
1802         return 0;
1803 }
1804
1805 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1806 {
1807         u32 reg32, phy9_orig;
1808         int retries, do_phy_reset, err;
1809
1810         retries = 10;
1811         do_phy_reset = 1;
1812         do {
1813                 if (do_phy_reset) {
1814                         err = tg3_bmcr_reset(tp);
1815                         if (err)
1816                                 return err;
1817                         do_phy_reset = 0;
1818                 }
1819
1820                 /* Disable transmitter and interrupt.  */
1821                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
1822                         continue;
1823
1824                 reg32 |= 0x3000;
1825                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1826
1827                 /* Set full-duplex, 1000 mbps.  */
1828                 tg3_writephy(tp, MII_BMCR,
1829                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1830
1831                 /* Set to master mode.  */
1832                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1833                         continue;
1834
1835                 tg3_writephy(tp, MII_TG3_CTRL,
1836                              (MII_TG3_CTRL_AS_MASTER |
1837                               MII_TG3_CTRL_ENABLE_AS_MASTER));
1838
1839                 /* Enable SM_DSP_CLOCK and 6dB.  */
1840                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1841
1842                 /* Block the PHY control access.  */
1843                 tg3_phydsp_write(tp, 0x8005, 0x0800);
1844
1845                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1846                 if (!err)
1847                         break;
1848         } while (--retries);
1849
1850         err = tg3_phy_reset_chanpat(tp);
1851         if (err)
1852                 return err;
1853
1854         tg3_phydsp_write(tp, 0x8005, 0x0000);
1855
1856         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1857         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
1858
1859         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1860             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1861                 /* Set Extended packet length bit for jumbo frames */
1862                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1863         } else {
1864                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1865         }
1866
1867         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1868
1869         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
1870                 reg32 &= ~0x3000;
1871                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1872         } else if (!err)
1873                 err = -EBUSY;
1874
1875         return err;
1876 }
1877
1878 /* This will reset the tigon3 PHY if there is no valid
1879  * link unless the FORCE argument is non-zero.
1880  */
1881 static int tg3_phy_reset(struct tg3 *tp)
1882 {
1883         u32 val, cpmuctrl;
1884         int err;
1885
1886         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1887                 val = tr32(GRC_MISC_CFG);
1888                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1889                 udelay(40);
1890         }
1891         err  = tg3_readphy(tp, MII_BMSR, &val);
1892         err |= tg3_readphy(tp, MII_BMSR, &val);
1893         if (err != 0)
1894                 return -EBUSY;
1895
1896         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1897                 netif_carrier_off(tp->dev);
1898                 tg3_link_report(tp);
1899         }
1900
1901         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1903             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1904                 err = tg3_phy_reset_5703_4_5(tp);
1905                 if (err)
1906                         return err;
1907                 goto out;
1908         }
1909
1910         cpmuctrl = 0;
1911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1912             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1913                 cpmuctrl = tr32(TG3_CPMU_CTRL);
1914                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1915                         tw32(TG3_CPMU_CTRL,
1916                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1917         }
1918
1919         err = tg3_bmcr_reset(tp);
1920         if (err)
1921                 return err;
1922
1923         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1924                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1925                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
1926
1927                 tw32(TG3_CPMU_CTRL, cpmuctrl);
1928         }
1929
1930         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1931             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1932                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1933                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1934                     CPMU_LSPD_1000MB_MACCLK_12_5) {
1935                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1936                         udelay(40);
1937                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1938                 }
1939         }
1940
1941         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
1942              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) &&
1943             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
1944                 return 0;
1945
1946         tg3_phy_apply_otp(tp);
1947
1948         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
1949                 tg3_phy_toggle_apd(tp, true);
1950         else
1951                 tg3_phy_toggle_apd(tp, false);
1952
1953 out:
1954         if (tp->phy_flags & TG3_PHYFLG_ADC_BUG) {
1955                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1956                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
1957                 tg3_phydsp_write(tp, 0x000a, 0x0323);
1958                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1959         }
1960         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
1961                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1962                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1963         }
1964         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
1965                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966                 tg3_phydsp_write(tp, 0x000a, 0x310b);
1967                 tg3_phydsp_write(tp, 0x201f, 0x9506);
1968                 tg3_phydsp_write(tp, 0x401f, 0x14e2);
1969                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1970         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
1971                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1972                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1973                 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
1974                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1975                         tg3_writephy(tp, MII_TG3_TEST1,
1976                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1977                 } else
1978                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1979                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1980         }
1981         /* Set Extended packet length bit (bit 14) on all chips that */
1982         /* support jumbo frames */
1983         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1984                 /* Cannot do read-modify-write on 5401 */
1985                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1986         } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1987                 /* Set bit 14 with read-modify-write to preserve other bits */
1988                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1989                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1990                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val | 0x4000);
1991         }
1992
1993         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1994          * jumbo frames transmission.
1995          */
1996         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1997                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
1998                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1999                                      val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2000         }
2001
2002         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2003                 /* adjust output voltage */
2004                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2005         }
2006
2007         tg3_phy_toggle_automdix(tp, 1);
2008         tg3_phy_set_wirespeed(tp);
2009         return 0;
2010 }
2011
2012 static void tg3_frob_aux_power(struct tg3 *tp)
2013 {
2014         struct tg3 *tp_peer = tp;
2015
2016         /* The GPIOs do something completely different on 57765. */
2017         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0 ||
2018             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
2019             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
2020                 return;
2021
2022         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2023             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2024             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2025                 struct net_device *dev_peer;
2026
2027                 dev_peer = pci_get_drvdata(tp->pdev_peer);
2028                 /* remove_one() may have been run on the peer. */
2029                 if (!dev_peer)
2030                         tp_peer = tp;
2031                 else
2032                         tp_peer = netdev_priv(dev_peer);
2033         }
2034
2035         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2036             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2037             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2038             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2039                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2040                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2041                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2042                                     (GRC_LCLCTRL_GPIO_OE0 |
2043                                      GRC_LCLCTRL_GPIO_OE1 |
2044                                      GRC_LCLCTRL_GPIO_OE2 |
2045                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
2046                                      GRC_LCLCTRL_GPIO_OUTPUT1),
2047                                     100);
2048                 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2049                            tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2050                         /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2051                         u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2052                                              GRC_LCLCTRL_GPIO_OE1 |
2053                                              GRC_LCLCTRL_GPIO_OE2 |
2054                                              GRC_LCLCTRL_GPIO_OUTPUT0 |
2055                                              GRC_LCLCTRL_GPIO_OUTPUT1 |
2056                                              tp->grc_local_ctrl;
2057                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2058
2059                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2060                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2061
2062                         grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2063                         tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064                 } else {
2065                         u32 no_gpio2;
2066                         u32 grc_local_ctrl = 0;
2067
2068                         if (tp_peer != tp &&
2069                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2070                                 return;
2071
2072                         /* Workaround to prevent overdrawing Amps. */
2073                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2074                             ASIC_REV_5714) {
2075                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2076                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2077                                             grc_local_ctrl, 100);
2078                         }
2079
2080                         /* On 5753 and variants, GPIO2 cannot be used. */
2081                         no_gpio2 = tp->nic_sram_data_cfg &
2082                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
2083
2084                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2085                                          GRC_LCLCTRL_GPIO_OE1 |
2086                                          GRC_LCLCTRL_GPIO_OE2 |
2087                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
2088                                          GRC_LCLCTRL_GPIO_OUTPUT2;
2089                         if (no_gpio2) {
2090                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2091                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
2092                         }
2093                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2094                                                     grc_local_ctrl, 100);
2095
2096                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2097
2098                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099                                                     grc_local_ctrl, 100);
2100
2101                         if (!no_gpio2) {
2102                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2103                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104                                             grc_local_ctrl, 100);
2105                         }
2106                 }
2107         } else {
2108                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2109                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2110                         if (tp_peer != tp &&
2111                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2112                                 return;
2113
2114                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2115                                     (GRC_LCLCTRL_GPIO_OE1 |
2116                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2117
2118                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2119                                     GRC_LCLCTRL_GPIO_OE1, 100);
2120
2121                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2122                                     (GRC_LCLCTRL_GPIO_OE1 |
2123                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2124                 }
2125         }
2126 }
2127
2128 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2129 {
2130         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2131                 return 1;
2132         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2133                 if (speed != SPEED_10)
2134                         return 1;
2135         } else if (speed == SPEED_10)
2136                 return 1;
2137
2138         return 0;
2139 }
2140
2141 static int tg3_setup_phy(struct tg3 *, int);
2142
2143 #define RESET_KIND_SHUTDOWN     0
2144 #define RESET_KIND_INIT         1
2145 #define RESET_KIND_SUSPEND      2
2146
2147 static void tg3_write_sig_post_reset(struct tg3 *, int);
2148 static int tg3_halt_cpu(struct tg3 *, u32);
2149
2150 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2151 {
2152         u32 val;
2153
2154         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2155                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2156                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2157                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2158
2159                         sg_dig_ctrl |=
2160                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2161                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
2162                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2163                 }
2164                 return;
2165         }
2166
2167         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2168                 tg3_bmcr_reset(tp);
2169                 val = tr32(GRC_MISC_CFG);
2170                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2171                 udelay(40);
2172                 return;
2173         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2174                 u32 phytest;
2175                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2176                         u32 phy;
2177
2178                         tg3_writephy(tp, MII_ADVERTISE, 0);
2179                         tg3_writephy(tp, MII_BMCR,
2180                                      BMCR_ANENABLE | BMCR_ANRESTART);
2181
2182                         tg3_writephy(tp, MII_TG3_FET_TEST,
2183                                      phytest | MII_TG3_FET_SHADOW_EN);
2184                         if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2185                                 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2186                                 tg3_writephy(tp,
2187                                              MII_TG3_FET_SHDW_AUXMODE4,
2188                                              phy);
2189                         }
2190                         tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2191                 }
2192                 return;
2193         } else if (do_low_power) {
2194                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2195                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2196
2197                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2198                              MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2199                              MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2200                              MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2201                              MII_TG3_AUXCTL_PCTL_VREG_11V);
2202         }
2203
2204         /* The PHY should not be powered down on some chips because
2205          * of bugs.
2206          */
2207         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2208             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2209             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2210              (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2211                 return;
2212
2213         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2214             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2215                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2216                 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2217                 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2218                 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2219         }
2220
2221         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2222 }
2223
2224 /* tp->lock is held. */
2225 static int tg3_nvram_lock(struct tg3 *tp)
2226 {
2227         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2228                 int i;
2229
2230                 if (tp->nvram_lock_cnt == 0) {
2231                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2232                         for (i = 0; i < 8000; i++) {
2233                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2234                                         break;
2235                                 udelay(20);
2236                         }
2237                         if (i == 8000) {
2238                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2239                                 return -ENODEV;
2240                         }
2241                 }
2242                 tp->nvram_lock_cnt++;
2243         }
2244         return 0;
2245 }
2246
2247 /* tp->lock is held. */
2248 static void tg3_nvram_unlock(struct tg3 *tp)
2249 {
2250         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2251                 if (tp->nvram_lock_cnt > 0)
2252                         tp->nvram_lock_cnt--;
2253                 if (tp->nvram_lock_cnt == 0)
2254                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2255         }
2256 }
2257
2258 /* tp->lock is held. */
2259 static void tg3_enable_nvram_access(struct tg3 *tp)
2260 {
2261         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2262             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2263                 u32 nvaccess = tr32(NVRAM_ACCESS);
2264
2265                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2266         }
2267 }
2268
2269 /* tp->lock is held. */
2270 static void tg3_disable_nvram_access(struct tg3 *tp)
2271 {
2272         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2273             !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2274                 u32 nvaccess = tr32(NVRAM_ACCESS);
2275
2276                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2277         }
2278 }
2279
2280 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2281                                         u32 offset, u32 *val)
2282 {
2283         u32 tmp;
2284         int i;
2285
2286         if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2287                 return -EINVAL;
2288
2289         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2290                                         EEPROM_ADDR_DEVID_MASK |
2291                                         EEPROM_ADDR_READ);
2292         tw32(GRC_EEPROM_ADDR,
2293              tmp |
2294              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2295              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2296               EEPROM_ADDR_ADDR_MASK) |
2297              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2298
2299         for (i = 0; i < 1000; i++) {
2300                 tmp = tr32(GRC_EEPROM_ADDR);
2301
2302                 if (tmp & EEPROM_ADDR_COMPLETE)
2303                         break;
2304                 msleep(1);
2305         }
2306         if (!(tmp & EEPROM_ADDR_COMPLETE))
2307                 return -EBUSY;
2308
2309         tmp = tr32(GRC_EEPROM_DATA);
2310
2311         /*
2312          * The data will always be opposite the native endian
2313          * format.  Perform a blind byteswap to compensate.
2314          */
2315         *val = swab32(tmp);
2316
2317         return 0;
2318 }
2319
2320 #define NVRAM_CMD_TIMEOUT 10000
2321
2322 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2323 {
2324         int i;
2325
2326         tw32(NVRAM_CMD, nvram_cmd);
2327         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2328                 udelay(10);
2329                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2330                         udelay(10);
2331                         break;
2332                 }
2333         }
2334
2335         if (i == NVRAM_CMD_TIMEOUT)
2336                 return -EBUSY;
2337
2338         return 0;
2339 }
2340
2341 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2342 {
2343         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2344             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2345             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2346            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2347             (tp->nvram_jedecnum == JEDEC_ATMEL))
2348
2349                 addr = ((addr / tp->nvram_pagesize) <<
2350                         ATMEL_AT45DB0X1B_PAGE_POS) +
2351                        (addr % tp->nvram_pagesize);
2352
2353         return addr;
2354 }
2355
2356 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2357 {
2358         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2359             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2360             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2361            !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2362             (tp->nvram_jedecnum == JEDEC_ATMEL))
2363
2364                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2365                         tp->nvram_pagesize) +
2366                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2367
2368         return addr;
2369 }
2370
2371 /* NOTE: Data read in from NVRAM is byteswapped according to
2372  * the byteswapping settings for all other register accesses.
2373  * tg3 devices are BE devices, so on a BE machine, the data
2374  * returned will be exactly as it is seen in NVRAM.  On a LE
2375  * machine, the 32-bit value will be byteswapped.
2376  */
2377 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2378 {
2379         int ret;
2380
2381         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2382                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2383
2384         offset = tg3_nvram_phys_addr(tp, offset);
2385
2386         if (offset > NVRAM_ADDR_MSK)
2387                 return -EINVAL;
2388
2389         ret = tg3_nvram_lock(tp);
2390         if (ret)
2391                 return ret;
2392
2393         tg3_enable_nvram_access(tp);
2394
2395         tw32(NVRAM_ADDR, offset);
2396         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2397                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2398
2399         if (ret == 0)
2400                 *val = tr32(NVRAM_RDDATA);
2401
2402         tg3_disable_nvram_access(tp);
2403
2404         tg3_nvram_unlock(tp);
2405
2406         return ret;
2407 }
2408
2409 /* Ensures NVRAM data is in bytestream format. */
2410 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2411 {
2412         u32 v;
2413         int res = tg3_nvram_read(tp, offset, &v);
2414         if (!res)
2415                 *val = cpu_to_be32(v);
2416         return res;
2417 }
2418
2419 /* tp->lock is held. */
2420 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2421 {
2422         u32 addr_high, addr_low;
2423         int i;
2424
2425         addr_high = ((tp->dev->dev_addr[0] << 8) |
2426                      tp->dev->dev_addr[1]);
2427         addr_low = ((tp->dev->dev_addr[2] << 24) |
2428                     (tp->dev->dev_addr[3] << 16) |
2429                     (tp->dev->dev_addr[4] <<  8) |
2430                     (tp->dev->dev_addr[5] <<  0));
2431         for (i = 0; i < 4; i++) {
2432                 if (i == 1 && skip_mac_1)
2433                         continue;
2434                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2435                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2436         }
2437
2438         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2439             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2440                 for (i = 0; i < 12; i++) {
2441                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2442                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2443                 }
2444         }
2445
2446         addr_high = (tp->dev->dev_addr[0] +
2447                      tp->dev->dev_addr[1] +
2448                      tp->dev->dev_addr[2] +
2449                      tp->dev->dev_addr[3] +
2450                      tp->dev->dev_addr[4] +
2451                      tp->dev->dev_addr[5]) &
2452                 TX_BACKOFF_SEED_MASK;
2453         tw32(MAC_TX_BACKOFF_SEED, addr_high);
2454 }
2455
2456 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2457 {
2458         u32 misc_host_ctrl;
2459         bool device_should_wake, do_low_power;
2460
2461         /* Make sure register accesses (indirect or otherwise)
2462          * will function correctly.
2463          */
2464         pci_write_config_dword(tp->pdev,
2465                                TG3PCI_MISC_HOST_CTRL,
2466                                tp->misc_host_ctrl);
2467
2468         switch (state) {
2469         case PCI_D0:
2470                 pci_enable_wake(tp->pdev, state, false);
2471                 pci_set_power_state(tp->pdev, PCI_D0);
2472
2473                 /* Switch out of Vaux if it is a NIC */
2474                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2475                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2476
2477                 return 0;
2478
2479         case PCI_D1:
2480         case PCI_D2:
2481         case PCI_D3hot:
2482                 break;
2483
2484         default:
2485                 netdev_err(tp->dev, "Invalid power state (D%d) requested\n",
2486                            state);
2487                 return -EINVAL;
2488         }
2489
2490         /* Restore the CLKREQ setting. */
2491         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2492                 u16 lnkctl;
2493
2494                 pci_read_config_word(tp->pdev,
2495                                      tp->pcie_cap + PCI_EXP_LNKCTL,
2496                                      &lnkctl);
2497                 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2498                 pci_write_config_word(tp->pdev,
2499                                       tp->pcie_cap + PCI_EXP_LNKCTL,
2500                                       lnkctl);
2501         }
2502
2503         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2504         tw32(TG3PCI_MISC_HOST_CTRL,
2505              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2506
2507         device_should_wake = pci_pme_capable(tp->pdev, state) &&
2508                              device_may_wakeup(&tp->pdev->dev) &&
2509                              (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2510
2511         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2512                 do_low_power = false;
2513                 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
2514                     !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2515                         struct phy_device *phydev;
2516                         u32 phyid, advertising;
2517
2518                         phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2519
2520                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2521
2522                         tp->link_config.orig_speed = phydev->speed;
2523                         tp->link_config.orig_duplex = phydev->duplex;
2524                         tp->link_config.orig_autoneg = phydev->autoneg;
2525                         tp->link_config.orig_advertising = phydev->advertising;
2526
2527                         advertising = ADVERTISED_TP |
2528                                       ADVERTISED_Pause |
2529                                       ADVERTISED_Autoneg |
2530                                       ADVERTISED_10baseT_Half;
2531
2532                         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2533                             device_should_wake) {
2534                                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2535                                         advertising |=
2536                                                 ADVERTISED_100baseT_Half |
2537                                                 ADVERTISED_100baseT_Full |
2538                                                 ADVERTISED_10baseT_Full;
2539                                 else
2540                                         advertising |= ADVERTISED_10baseT_Full;
2541                         }
2542
2543                         phydev->advertising = advertising;
2544
2545                         phy_start_aneg(phydev);
2546
2547                         phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2548                         if (phyid != PHY_ID_BCMAC131) {
2549                                 phyid &= PHY_BCM_OUI_MASK;
2550                                 if (phyid == PHY_BCM_OUI_1 ||
2551                                     phyid == PHY_BCM_OUI_2 ||
2552                                     phyid == PHY_BCM_OUI_3)
2553                                         do_low_power = true;
2554                         }
2555                 }
2556         } else {
2557                 do_low_power = true;
2558
2559                 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
2560                         tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
2561                         tp->link_config.orig_speed = tp->link_config.speed;
2562                         tp->link_config.orig_duplex = tp->link_config.duplex;
2563                         tp->link_config.orig_autoneg = tp->link_config.autoneg;
2564                 }
2565
2566                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
2567                         tp->link_config.speed = SPEED_10;
2568                         tp->link_config.duplex = DUPLEX_HALF;
2569                         tp->link_config.autoneg = AUTONEG_ENABLE;
2570                         tg3_setup_phy(tp, 0);
2571                 }
2572         }
2573
2574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2575                 u32 val;
2576
2577                 val = tr32(GRC_VCPU_EXT_CTRL);
2578                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2579         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2580                 int i;
2581                 u32 val;
2582
2583                 for (i = 0; i < 200; i++) {
2584                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2585                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2586                                 break;
2587                         msleep(1);
2588                 }
2589         }
2590         if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2591                 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2592                                                      WOL_DRV_STATE_SHUTDOWN |
2593                                                      WOL_DRV_WOL |
2594                                                      WOL_SET_MAGIC_PKT);
2595
2596         if (device_should_wake) {
2597                 u32 mac_mode;
2598
2599                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
2600                         if (do_low_power) {
2601                                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2602                                 udelay(40);
2603                         }
2604
2605                         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
2606                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
2607                         else
2608                                 mac_mode = MAC_MODE_PORT_MODE_MII;
2609
2610                         mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2611                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2612                             ASIC_REV_5700) {
2613                                 u32 speed = (tp->tg3_flags &
2614                                              TG3_FLAG_WOL_SPEED_100MB) ?
2615                                              SPEED_100 : SPEED_10;
2616                                 if (tg3_5700_link_polarity(tp, speed))
2617                                         mac_mode |= MAC_MODE_LINK_POLARITY;
2618                                 else
2619                                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
2620                         }
2621                 } else {
2622                         mac_mode = MAC_MODE_PORT_MODE_TBI;
2623                 }
2624
2625                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2626                         tw32(MAC_LED_CTRL, tp->led_ctrl);
2627
2628                 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2629                 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2630                     !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2631                     ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2632                      (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2633                         mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2634
2635                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2636                         mac_mode |= tp->mac_mode &
2637                                     (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2638                         if (mac_mode & MAC_MODE_APE_TX_EN)
2639                                 mac_mode |= MAC_MODE_TDE_ENABLE;
2640                 }
2641
2642                 tw32_f(MAC_MODE, mac_mode);
2643                 udelay(100);
2644
2645                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2646                 udelay(10);
2647         }
2648
2649         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2650             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2651              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2652                 u32 base_val;
2653
2654                 base_val = tp->pci_clock_ctrl;
2655                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2656                              CLOCK_CTRL_TXCLK_DISABLE);
2657
2658                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2659                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
2660         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2661                    (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2662                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2663                 /* do nothing */
2664         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2665                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2666                 u32 newbits1, newbits2;
2667
2668                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2669                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2670                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2671                                     CLOCK_CTRL_TXCLK_DISABLE |
2672                                     CLOCK_CTRL_ALTCLK);
2673                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2674                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2675                         newbits1 = CLOCK_CTRL_625_CORE;
2676                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2677                 } else {
2678                         newbits1 = CLOCK_CTRL_ALTCLK;
2679                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2680                 }
2681
2682                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2683                             40);
2684
2685                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2686                             40);
2687
2688                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2689                         u32 newbits3;
2690
2691                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2692                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2693                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2694                                             CLOCK_CTRL_TXCLK_DISABLE |
2695                                             CLOCK_CTRL_44MHZ_CORE);
2696                         } else {
2697                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2698                         }
2699
2700                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
2701                                     tp->pci_clock_ctrl | newbits3, 40);
2702                 }
2703         }
2704
2705         if (!(device_should_wake) &&
2706             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2707                 tg3_power_down_phy(tp, do_low_power);
2708
2709         tg3_frob_aux_power(tp);
2710
2711         /* Workaround for unstable PLL clock */
2712         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2713             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2714                 u32 val = tr32(0x7d00);
2715
2716                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2717                 tw32(0x7d00, val);
2718                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2719                         int err;
2720
2721                         err = tg3_nvram_lock(tp);
2722                         tg3_halt_cpu(tp, RX_CPU_BASE);
2723                         if (!err)
2724                                 tg3_nvram_unlock(tp);
2725                 }
2726         }
2727
2728         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2729
2730         if (device_should_wake)
2731                 pci_enable_wake(tp->pdev, state, true);
2732
2733         /* Finally, set the new power state. */
2734         pci_set_power_state(tp->pdev, state);
2735
2736         return 0;
2737 }
2738
2739 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2740 {
2741         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2742         case MII_TG3_AUX_STAT_10HALF:
2743                 *speed = SPEED_10;
2744                 *duplex = DUPLEX_HALF;
2745                 break;
2746
2747         case MII_TG3_AUX_STAT_10FULL:
2748                 *speed = SPEED_10;
2749                 *duplex = DUPLEX_FULL;
2750                 break;
2751
2752         case MII_TG3_AUX_STAT_100HALF:
2753                 *speed = SPEED_100;
2754                 *duplex = DUPLEX_HALF;
2755                 break;
2756
2757         case MII_TG3_AUX_STAT_100FULL:
2758                 *speed = SPEED_100;
2759                 *duplex = DUPLEX_FULL;
2760                 break;
2761
2762         case MII_TG3_AUX_STAT_1000HALF:
2763                 *speed = SPEED_1000;
2764                 *duplex = DUPLEX_HALF;
2765                 break;
2766
2767         case MII_TG3_AUX_STAT_1000FULL:
2768                 *speed = SPEED_1000;
2769                 *duplex = DUPLEX_FULL;
2770                 break;
2771
2772         default:
2773                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2774                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2775                                  SPEED_10;
2776                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2777                                   DUPLEX_HALF;
2778                         break;
2779                 }
2780                 *speed = SPEED_INVALID;
2781                 *duplex = DUPLEX_INVALID;
2782                 break;
2783         }
2784 }
2785
2786 static void tg3_phy_copper_begin(struct tg3 *tp)
2787 {
2788         u32 new_adv;
2789         int i;
2790
2791         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2792                 /* Entering low power mode.  Disable gigabit and
2793                  * 100baseT advertisements.
2794                  */
2795                 tg3_writephy(tp, MII_TG3_CTRL, 0);
2796
2797                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2798                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2799                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2800                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2801
2802                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2803         } else if (tp->link_config.speed == SPEED_INVALID) {
2804                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
2805                         tp->link_config.advertising &=
2806                                 ~(ADVERTISED_1000baseT_Half |
2807                                   ADVERTISED_1000baseT_Full);
2808
2809                 new_adv = ADVERTISE_CSMA;
2810                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2811                         new_adv |= ADVERTISE_10HALF;
2812                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2813                         new_adv |= ADVERTISE_10FULL;
2814                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2815                         new_adv |= ADVERTISE_100HALF;
2816                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2817                         new_adv |= ADVERTISE_100FULL;
2818
2819                 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2820
2821                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2822
2823                 if (tp->link_config.advertising &
2824                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2825                         new_adv = 0;
2826                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2827                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2828                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2829                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2830                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY) &&
2831                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2832                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2833                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2834                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2835                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2836                 } else {
2837                         tg3_writephy(tp, MII_TG3_CTRL, 0);
2838                 }
2839         } else {
2840                 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2841                 new_adv |= ADVERTISE_CSMA;
2842
2843                 /* Asking for a specific link mode. */
2844                 if (tp->link_config.speed == SPEED_1000) {
2845                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2846
2847                         if (tp->link_config.duplex == DUPLEX_FULL)
2848                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2849                         else
2850                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2851                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2852                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2853                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2854                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
2855                 } else {
2856                         if (tp->link_config.speed == SPEED_100) {
2857                                 if (tp->link_config.duplex == DUPLEX_FULL)
2858                                         new_adv |= ADVERTISE_100FULL;
2859                                 else
2860                                         new_adv |= ADVERTISE_100HALF;
2861                         } else {
2862                                 if (tp->link_config.duplex == DUPLEX_FULL)
2863                                         new_adv |= ADVERTISE_10FULL;
2864                                 else
2865                                         new_adv |= ADVERTISE_10HALF;
2866                         }
2867                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2868
2869                         new_adv = 0;
2870                 }
2871
2872                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2873         }
2874
2875         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2876             tp->link_config.speed != SPEED_INVALID) {
2877                 u32 bmcr, orig_bmcr;
2878
2879                 tp->link_config.active_speed = tp->link_config.speed;
2880                 tp->link_config.active_duplex = tp->link_config.duplex;
2881
2882                 bmcr = 0;
2883                 switch (tp->link_config.speed) {
2884                 default:
2885                 case SPEED_10:
2886                         break;
2887
2888                 case SPEED_100:
2889                         bmcr |= BMCR_SPEED100;
2890                         break;
2891
2892                 case SPEED_1000:
2893                         bmcr |= TG3_BMCR_SPEED1000;
2894                         break;
2895                 }
2896
2897                 if (tp->link_config.duplex == DUPLEX_FULL)
2898                         bmcr |= BMCR_FULLDPLX;
2899
2900                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2901                     (bmcr != orig_bmcr)) {
2902                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2903                         for (i = 0; i < 1500; i++) {
2904                                 u32 tmp;
2905
2906                                 udelay(10);
2907                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2908                                     tg3_readphy(tp, MII_BMSR, &tmp))
2909                                         continue;
2910                                 if (!(tmp & BMSR_LSTATUS)) {
2911                                         udelay(40);
2912                                         break;
2913                                 }
2914                         }
2915                         tg3_writephy(tp, MII_BMCR, bmcr);
2916                         udelay(40);
2917                 }
2918         } else {
2919                 tg3_writephy(tp, MII_BMCR,
2920                              BMCR_ANENABLE | BMCR_ANRESTART);
2921         }
2922 }
2923
2924 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2925 {
2926         int err;
2927
2928         /* Turn off tap power management. */
2929         /* Set Extended packet length bit */
2930         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2931
2932         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
2933         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
2934         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
2935         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
2936         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
2937
2938         udelay(40);
2939
2940         return err;
2941 }
2942
2943 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2944 {
2945         u32 adv_reg, all_mask = 0;
2946
2947         if (mask & ADVERTISED_10baseT_Half)
2948                 all_mask |= ADVERTISE_10HALF;
2949         if (mask & ADVERTISED_10baseT_Full)
2950                 all_mask |= ADVERTISE_10FULL;
2951         if (mask & ADVERTISED_100baseT_Half)
2952                 all_mask |= ADVERTISE_100HALF;
2953         if (mask & ADVERTISED_100baseT_Full)
2954                 all_mask |= ADVERTISE_100FULL;
2955
2956         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2957                 return 0;
2958
2959         if ((adv_reg & all_mask) != all_mask)
2960                 return 0;
2961         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2962                 u32 tg3_ctrl;
2963
2964                 all_mask = 0;
2965                 if (mask & ADVERTISED_1000baseT_Half)
2966                         all_mask |= ADVERTISE_1000HALF;
2967                 if (mask & ADVERTISED_1000baseT_Full)
2968                         all_mask |= ADVERTISE_1000FULL;
2969
2970                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2971                         return 0;
2972
2973                 if ((tg3_ctrl & all_mask) != all_mask)
2974                         return 0;
2975         }
2976         return 1;
2977 }
2978
2979 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2980 {
2981         u32 curadv, reqadv;
2982
2983         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
2984                 return 1;
2985
2986         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2987         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2988
2989         if (tp->link_config.active_duplex == DUPLEX_FULL) {
2990                 if (curadv != reqadv)
2991                         return 0;
2992
2993                 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
2994                         tg3_readphy(tp, MII_LPA, rmtadv);
2995         } else {
2996                 /* Reprogram the advertisement register, even if it
2997                  * does not affect the current link.  If the link
2998                  * gets renegotiated in the future, we can save an
2999                  * additional renegotiation cycle by advertising
3000                  * it correctly in the first place.
3001                  */
3002                 if (curadv != reqadv) {
3003                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3004                                      ADVERTISE_PAUSE_ASYM);
3005                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3006                 }
3007         }
3008
3009         return 1;
3010 }
3011
3012 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3013 {
3014         int current_link_up;
3015         u32 bmsr, val;
3016         u32 lcl_adv, rmt_adv;
3017         u16 current_speed;
3018         u8 current_duplex;
3019         int i, err;
3020
3021         tw32(MAC_EVENT, 0);
3022
3023         tw32_f(MAC_STATUS,
3024              (MAC_STATUS_SYNC_CHANGED |
3025               MAC_STATUS_CFG_CHANGED |
3026               MAC_STATUS_MI_COMPLETION |
3027               MAC_STATUS_LNKSTATE_CHANGED));
3028         udelay(40);
3029
3030         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3031                 tw32_f(MAC_MI_MODE,
3032                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3033                 udelay(80);
3034         }
3035
3036         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3037
3038         /* Some third-party PHYs need to be reset on link going
3039          * down.
3040          */
3041         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3042              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3043              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3044             netif_carrier_ok(tp->dev)) {
3045                 tg3_readphy(tp, MII_BMSR, &bmsr);
3046                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3047                     !(bmsr & BMSR_LSTATUS))
3048                         force_reset = 1;
3049         }
3050         if (force_reset)
3051                 tg3_phy_reset(tp);
3052
3053         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
3054                 tg3_readphy(tp, MII_BMSR, &bmsr);
3055                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3056                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3057                         bmsr = 0;
3058
3059                 if (!(bmsr & BMSR_LSTATUS)) {
3060                         err = tg3_init_5401phy_dsp(tp);
3061                         if (err)
3062                                 return err;
3063
3064                         tg3_readphy(tp, MII_BMSR, &bmsr);
3065                         for (i = 0; i < 1000; i++) {
3066                                 udelay(10);
3067                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3068                                     (bmsr & BMSR_LSTATUS)) {
3069                                         udelay(40);
3070                                         break;
3071                                 }
3072                         }
3073
3074                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
3075                             TG3_PHY_REV_BCM5401_B0 &&
3076                             !(bmsr & BMSR_LSTATUS) &&
3077                             tp->link_config.active_speed == SPEED_1000) {
3078                                 err = tg3_phy_reset(tp);
3079                                 if (!err)
3080                                         err = tg3_init_5401phy_dsp(tp);
3081                                 if (err)
3082                                         return err;
3083                         }
3084                 }
3085         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3086                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3087                 /* 5701 {A0,B0} CRC bug workaround */
3088                 tg3_writephy(tp, 0x15, 0x0a75);
3089                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3090                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
3091                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
3092         }
3093
3094         /* Clear pending interrupts... */
3095         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3096         tg3_readphy(tp, MII_TG3_ISTAT, &val);
3097
3098         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
3099                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3100         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
3101                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3102
3103         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3104             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3105                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3106                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
3107                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3108                 else
3109                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3110         }
3111
3112         current_link_up = 0;
3113         current_speed = SPEED_INVALID;
3114         current_duplex = DUPLEX_INVALID;
3115
3116         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
3117                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3118                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3119                 if (!(val & (1 << 10))) {
3120                         val |= (1 << 10);
3121                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3122                         goto relink;
3123                 }
3124         }
3125
3126         bmsr = 0;
3127         for (i = 0; i < 100; i++) {
3128                 tg3_readphy(tp, MII_BMSR, &bmsr);
3129                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3130                     (bmsr & BMSR_LSTATUS))
3131                         break;
3132                 udelay(40);
3133         }
3134
3135         if (bmsr & BMSR_LSTATUS) {
3136                 u32 aux_stat, bmcr;
3137
3138                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3139                 for (i = 0; i < 2000; i++) {
3140                         udelay(10);
3141                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3142                             aux_stat)
3143                                 break;
3144                 }
3145
3146                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3147                                              &current_speed,
3148                                              &current_duplex);
3149
3150                 bmcr = 0;
3151                 for (i = 0; i < 200; i++) {
3152                         tg3_readphy(tp, MII_BMCR, &bmcr);
3153                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
3154                                 continue;
3155                         if (bmcr && bmcr != 0x7fff)
3156                                 break;
3157                         udelay(10);
3158                 }
3159
3160                 lcl_adv = 0;
3161                 rmt_adv = 0;
3162
3163                 tp->link_config.active_speed = current_speed;
3164                 tp->link_config.active_duplex = current_duplex;
3165
3166                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3167                         if ((bmcr & BMCR_ANENABLE) &&
3168                             tg3_copper_is_advertising_all(tp,
3169                                                 tp->link_config.advertising)) {
3170                                 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3171                                                                   &rmt_adv))
3172                                         current_link_up = 1;
3173                         }
3174                 } else {
3175                         if (!(bmcr & BMCR_ANENABLE) &&
3176                             tp->link_config.speed == current_speed &&
3177                             tp->link_config.duplex == current_duplex &&
3178                             tp->link_config.flowctrl ==
3179                             tp->link_config.active_flowctrl) {
3180                                 current_link_up = 1;
3181                         }
3182                 }
3183
3184                 if (current_link_up == 1 &&
3185                     tp->link_config.active_duplex == DUPLEX_FULL)
3186                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3187         }
3188
3189 relink:
3190         if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
3191                 tg3_phy_copper_begin(tp);
3192
3193                 tg3_readphy(tp, MII_BMSR, &bmsr);
3194                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3195                     (bmsr & BMSR_LSTATUS))
3196                         current_link_up = 1;
3197         }
3198
3199         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3200         if (current_link_up == 1) {
3201                 if (tp->link_config.active_speed == SPEED_100 ||
3202                     tp->link_config.active_speed == SPEED_10)
3203                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3204                 else
3205                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3206         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
3207                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3208         else
3209                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3210
3211         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3212         if (tp->link_config.active_duplex == DUPLEX_HALF)
3213                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3214
3215         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3216                 if (current_link_up == 1 &&
3217                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3218                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3219                 else
3220                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3221         }
3222
3223         /* ??? Without this setting Netgear GA302T PHY does not
3224          * ??? send/receive packets...
3225          */
3226         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
3227             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3228                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3229                 tw32_f(MAC_MI_MODE, tp->mi_mode);
3230                 udelay(80);
3231         }
3232
3233         tw32_f(MAC_MODE, tp->mac_mode);
3234         udelay(40);
3235
3236         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3237                 /* Polled via timer. */
3238                 tw32_f(MAC_EVENT, 0);
3239         } else {
3240                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3241         }
3242         udelay(40);
3243
3244         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3245             current_link_up == 1 &&
3246             tp->link_config.active_speed == SPEED_1000 &&
3247             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3248              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3249                 udelay(120);
3250                 tw32_f(MAC_STATUS,
3251                      (MAC_STATUS_SYNC_CHANGED |
3252                       MAC_STATUS_CFG_CHANGED));
3253                 udelay(40);
3254                 tg3_write_mem(tp,
3255                               NIC_SRAM_FIRMWARE_MBOX,
3256                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3257         }
3258
3259         /* Prevent send BD corruption. */
3260         if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3261                 u16 oldlnkctl, newlnkctl;
3262
3263                 pci_read_config_word(tp->pdev,
3264                                      tp->pcie_cap + PCI_EXP_LNKCTL,
3265                                      &oldlnkctl);
3266                 if (tp->link_config.active_speed == SPEED_100 ||
3267                     tp->link_config.active_speed == SPEED_10)
3268                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3269                 else
3270                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3271                 if (newlnkctl != oldlnkctl)
3272                         pci_write_config_word(tp->pdev,
3273                                               tp->pcie_cap + PCI_EXP_LNKCTL,
3274                                               newlnkctl);
3275         }
3276
3277         if (current_link_up != netif_carrier_ok(tp->dev)) {
3278                 if (current_link_up)
3279                         netif_carrier_on(tp->dev);
3280                 else
3281                         netif_carrier_off(tp->dev);
3282                 tg3_link_report(tp);
3283         }
3284
3285         return 0;
3286 }
3287
3288 struct tg3_fiber_aneginfo {
3289         int state;
3290 #define ANEG_STATE_UNKNOWN              0
3291 #define ANEG_STATE_AN_ENABLE            1
3292 #define ANEG_STATE_RESTART_INIT         2
3293 #define ANEG_STATE_RESTART              3
3294 #define ANEG_STATE_DISABLE_LINK_OK      4
3295 #define ANEG_STATE_ABILITY_DETECT_INIT  5
3296 #define ANEG_STATE_ABILITY_DETECT       6
3297 #define ANEG_STATE_ACK_DETECT_INIT      7
3298 #define ANEG_STATE_ACK_DETECT           8
3299 #define ANEG_STATE_COMPLETE_ACK_INIT    9
3300 #define ANEG_STATE_COMPLETE_ACK         10
3301 #define ANEG_STATE_IDLE_DETECT_INIT     11
3302 #define ANEG_STATE_IDLE_DETECT          12
3303 #define ANEG_STATE_LINK_OK              13
3304 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
3305 #define ANEG_STATE_NEXT_PAGE_WAIT       15
3306
3307         u32 flags;
3308 #define MR_AN_ENABLE            0x00000001
3309 #define MR_RESTART_AN           0x00000002
3310 #define MR_AN_COMPLETE          0x00000004
3311 #define MR_PAGE_RX              0x00000008
3312 #define MR_NP_LOADED            0x00000010
3313 #define MR_TOGGLE_TX            0x00000020
3314 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
3315 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
3316 #define MR_LP_ADV_SYM_PAUSE     0x00000100
3317 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
3318 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3319 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3320 #define MR_LP_ADV_NEXT_PAGE     0x00001000
3321 #define MR_TOGGLE_RX            0x00002000
3322 #define MR_NP_RX                0x00004000
3323
3324 #define MR_LINK_OK              0x80000000
3325
3326         unsigned long link_time, cur_time;
3327
3328         u32 ability_match_cfg;
3329         int ability_match_count;
3330
3331         char ability_match, idle_match, ack_match;
3332
3333         u32 txconfig, rxconfig;
3334 #define ANEG_CFG_NP             0x00000080
3335 #define ANEG_CFG_ACK            0x00000040
3336 #define ANEG_CFG_RF2            0x00000020
3337 #define ANEG_CFG_RF1            0x00000010
3338 #define ANEG_CFG_PS2            0x00000001
3339 #define ANEG_CFG_PS1            0x00008000
3340 #define ANEG_CFG_HD             0x00004000
3341 #define ANEG_CFG_FD             0x00002000
3342 #define ANEG_CFG_INVAL          0x00001f06
3343
3344 };
3345 #define ANEG_OK         0
3346 #define ANEG_DONE       1
3347 #define ANEG_TIMER_ENAB 2
3348 #define ANEG_FAILED     -1
3349
3350 #define ANEG_STATE_SETTLE_TIME  10000
3351
3352 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3353                                    struct tg3_fiber_aneginfo *ap)
3354 {
3355         u16 flowctrl;
3356         unsigned long delta;
3357         u32 rx_cfg_reg;
3358         int ret;
3359
3360         if (ap->state == ANEG_STATE_UNKNOWN) {
3361                 ap->rxconfig = 0;
3362                 ap->link_time = 0;
3363                 ap->cur_time = 0;
3364                 ap->ability_match_cfg = 0;
3365                 ap->ability_match_count = 0;
3366                 ap->ability_match = 0;
3367                 ap->idle_match = 0;
3368                 ap->ack_match = 0;
3369         }
3370         ap->cur_time++;
3371
3372         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3373                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3374
3375                 if (rx_cfg_reg != ap->ability_match_cfg) {
3376                         ap->ability_match_cfg = rx_cfg_reg;
3377                         ap->ability_match = 0;
3378                         ap->ability_match_count = 0;
3379                 } else {
3380                         if (++ap->ability_match_count > 1) {
3381                                 ap->ability_match = 1;
3382                                 ap->ability_match_cfg = rx_cfg_reg;
3383                         }
3384                 }
3385                 if (rx_cfg_reg & ANEG_CFG_ACK)
3386                         ap->ack_match = 1;
3387                 else
3388                         ap->ack_match = 0;
3389
3390                 ap->idle_match = 0;
3391         } else {
3392                 ap->idle_match = 1;
3393                 ap->ability_match_cfg = 0;
3394                 ap->ability_match_count = 0;
3395                 ap->ability_match = 0;
3396                 ap->ack_match = 0;
3397
3398                 rx_cfg_reg = 0;
3399         }
3400
3401         ap->rxconfig = rx_cfg_reg;
3402         ret = ANEG_OK;
3403
3404         switch (ap->state) {
3405         case ANEG_STATE_UNKNOWN:
3406                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3407                         ap->state = ANEG_STATE_AN_ENABLE;
3408
3409                 /* fallthru */
3410         case ANEG_STATE_AN_ENABLE:
3411                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3412                 if (ap->flags & MR_AN_ENABLE) {
3413                         ap->link_time = 0;
3414                         ap->cur_time = 0;
3415                         ap->ability_match_cfg = 0;
3416                         ap->ability_match_count = 0;
3417                         ap->ability_match = 0;
3418                         ap->idle_match = 0;
3419                         ap->ack_match = 0;
3420
3421                         ap->state = ANEG_STATE_RESTART_INIT;
3422                 } else {
3423                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
3424                 }
3425                 break;
3426
3427         case ANEG_STATE_RESTART_INIT:
3428                 ap->link_time = ap->cur_time;
3429                 ap->flags &= ~(MR_NP_LOADED);
3430                 ap->txconfig = 0;
3431                 tw32(MAC_TX_AUTO_NEG, 0);
3432                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3433                 tw32_f(MAC_MODE, tp->mac_mode);
3434                 udelay(40);
3435
3436                 ret = ANEG_TIMER_ENAB;
3437                 ap->state = ANEG_STATE_RESTART;
3438
3439                 /* fallthru */
3440         case ANEG_STATE_RESTART:
3441                 delta = ap->cur_time - ap->link_time;
3442                 if (delta > ANEG_STATE_SETTLE_TIME)
3443                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3444                 else
3445                         ret = ANEG_TIMER_ENAB;
3446                 break;
3447
3448         case ANEG_STATE_DISABLE_LINK_OK:
3449                 ret = ANEG_DONE;
3450                 break;
3451
3452         case ANEG_STATE_ABILITY_DETECT_INIT:
3453                 ap->flags &= ~(MR_TOGGLE_TX);
3454                 ap->txconfig = ANEG_CFG_FD;
3455                 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3456                 if (flowctrl & ADVERTISE_1000XPAUSE)
3457                         ap->txconfig |= ANEG_CFG_PS1;
3458                 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3459                         ap->txconfig |= ANEG_CFG_PS2;
3460                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3461                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3462                 tw32_f(MAC_MODE, tp->mac_mode);
3463                 udelay(40);
3464
3465                 ap->state = ANEG_STATE_ABILITY_DETECT;
3466                 break;
3467
3468         case ANEG_STATE_ABILITY_DETECT:
3469                 if (ap->ability_match != 0 && ap->rxconfig != 0)
3470                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
3471                 break;
3472
3473         case ANEG_STATE_ACK_DETECT_INIT:
3474                 ap->txconfig |= ANEG_CFG_ACK;
3475                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3476                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3477                 tw32_f(MAC_MODE, tp->mac_mode);
3478                 udelay(40);
3479
3480                 ap->state = ANEG_STATE_ACK_DETECT;
3481
3482                 /* fallthru */
3483         case ANEG_STATE_ACK_DETECT:
3484                 if (ap->ack_match != 0) {
3485                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3486                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3487                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3488                         } else {
3489                                 ap->state = ANEG_STATE_AN_ENABLE;
3490                         }
3491                 } else if (ap->ability_match != 0 &&
3492                            ap->rxconfig == 0) {
3493                         ap->state = ANEG_STATE_AN_ENABLE;
3494                 }
3495                 break;
3496
3497         case ANEG_STATE_COMPLETE_ACK_INIT:
3498                 if (ap->rxconfig & ANEG_CFG_INVAL) {
3499                         ret = ANEG_FAILED;
3500                         break;
3501                 }
3502                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3503                                MR_LP_ADV_HALF_DUPLEX |
3504                                MR_LP_ADV_SYM_PAUSE |
3505                                MR_LP_ADV_ASYM_PAUSE |
3506                                MR_LP_ADV_REMOTE_FAULT1 |
3507                                MR_LP_ADV_REMOTE_FAULT2 |
3508                                MR_LP_ADV_NEXT_PAGE |
3509                                MR_TOGGLE_RX |
3510                                MR_NP_RX);
3511                 if (ap->rxconfig & ANEG_CFG_FD)
3512                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3513                 if (ap->rxconfig & ANEG_CFG_HD)
3514                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3515                 if (ap->rxconfig & ANEG_CFG_PS1)
3516                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
3517                 if (ap->rxconfig & ANEG_CFG_PS2)
3518                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3519                 if (ap->rxconfig & ANEG_CFG_RF1)
3520                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3521                 if (ap->rxconfig & ANEG_CFG_RF2)
3522                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3523                 if (ap->rxconfig & ANEG_CFG_NP)
3524                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
3525
3526                 ap->link_time = ap->cur_time;
3527
3528                 ap->flags ^= (MR_TOGGLE_TX);
3529                 if (ap->rxconfig & 0x0008)
3530                         ap->flags |= MR_TOGGLE_RX;
3531                 if (ap->rxconfig & ANEG_CFG_NP)
3532                         ap->flags |= MR_NP_RX;
3533                 ap->flags |= MR_PAGE_RX;
3534
3535                 ap->state = ANEG_STATE_COMPLETE_ACK;
3536                 ret = ANEG_TIMER_ENAB;
3537                 break;
3538
3539         case ANEG_STATE_COMPLETE_ACK:
3540                 if (ap->ability_match != 0 &&
3541                     ap->rxconfig == 0) {
3542                         ap->state = ANEG_STATE_AN_ENABLE;
3543                         break;
3544                 }
3545                 delta = ap->cur_time - ap->link_time;
3546                 if (delta > ANEG_STATE_SETTLE_TIME) {
3547                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3548                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3549                         } else {
3550                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3551                                     !(ap->flags & MR_NP_RX)) {
3552                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3553                                 } else {
3554                                         ret = ANEG_FAILED;
3555                                 }
3556                         }
3557                 }
3558                 break;
3559
3560         case ANEG_STATE_IDLE_DETECT_INIT:
3561                 ap->link_time = ap->cur_time;
3562                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3563                 tw32_f(MAC_MODE, tp->mac_mode);
3564                 udelay(40);
3565
3566                 ap->state = ANEG_STATE_IDLE_DETECT;
3567                 ret = ANEG_TIMER_ENAB;
3568                 break;
3569
3570         case ANEG_STATE_IDLE_DETECT:
3571                 if (ap->ability_match != 0 &&
3572                     ap->rxconfig == 0) {
3573                         ap->state = ANEG_STATE_AN_ENABLE;
3574                         break;
3575                 }
3576                 delta = ap->cur_time - ap->link_time;
3577                 if (delta > ANEG_STATE_SETTLE_TIME) {
3578                         /* XXX another gem from the Broadcom driver :( */
3579                         ap->state = ANEG_STATE_LINK_OK;
3580                 }
3581                 break;
3582
3583         case ANEG_STATE_LINK_OK:
3584                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3585                 ret = ANEG_DONE;
3586                 break;
3587
3588         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3589                 /* ??? unimplemented */
3590                 break;
3591
3592         case ANEG_STATE_NEXT_PAGE_WAIT:
3593                 /* ??? unimplemented */
3594                 break;
3595
3596         default:
3597                 ret = ANEG_FAILED;
3598                 break;
3599         }
3600
3601         return ret;
3602 }
3603
3604 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3605 {
3606         int res = 0;
3607         struct tg3_fiber_aneginfo aninfo;
3608         int status = ANEG_FAILED;
3609         unsigned int tick;
3610         u32 tmp;
3611
3612         tw32_f(MAC_TX_AUTO_NEG, 0);
3613
3614         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3615         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3616         udelay(40);
3617
3618         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3619         udelay(40);
3620
3621         memset(&aninfo, 0, sizeof(aninfo));
3622         aninfo.flags |= MR_AN_ENABLE;
3623         aninfo.state = ANEG_STATE_UNKNOWN;
3624         aninfo.cur_time = 0;
3625         tick = 0;
3626         while (++tick < 195000) {
3627                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3628                 if (status == ANEG_DONE || status == ANEG_FAILED)
3629                         break;
3630
3631                 udelay(1);
3632         }
3633
3634         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3635         tw32_f(MAC_MODE, tp->mac_mode);
3636         udelay(40);
3637
3638         *txflags = aninfo.txconfig;
3639         *rxflags = aninfo.flags;
3640
3641         if (status == ANEG_DONE &&
3642             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3643                              MR_LP_ADV_FULL_DUPLEX)))
3644                 res = 1;
3645
3646         return res;
3647 }
3648
3649 static void tg3_init_bcm8002(struct tg3 *tp)
3650 {
3651         u32 mac_status = tr32(MAC_STATUS);
3652         int i;
3653
3654         /* Reset when initting first time or we have a link. */
3655         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3656             !(mac_status & MAC_STATUS_PCS_SYNCED))
3657                 return;
3658
3659         /* Set PLL lock range. */
3660         tg3_writephy(tp, 0x16, 0x8007);
3661
3662         /* SW reset */
3663         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3664
3665         /* Wait for reset to complete. */
3666         /* XXX schedule_timeout() ... */
3667         for (i = 0; i < 500; i++)
3668                 udelay(10);
3669
3670         /* Config mode; select PMA/Ch 1 regs. */
3671         tg3_writephy(tp, 0x10, 0x8411);
3672
3673         /* Enable auto-lock and comdet, select txclk for tx. */
3674         tg3_writephy(tp, 0x11, 0x0a10);
3675
3676         tg3_writephy(tp, 0x18, 0x00a0);
3677         tg3_writephy(tp, 0x16, 0x41ff);
3678
3679         /* Assert and deassert POR. */
3680         tg3_writephy(tp, 0x13, 0x0400);
3681         udelay(40);
3682         tg3_writephy(tp, 0x13, 0x0000);
3683
3684         tg3_writephy(tp, 0x11, 0x0a50);
3685         udelay(40);
3686         tg3_writephy(tp, 0x11, 0x0a10);
3687
3688         /* Wait for signal to stabilize */
3689         /* XXX schedule_timeout() ... */
3690         for (i = 0; i < 15000; i++)
3691                 udelay(10);
3692
3693         /* Deselect the channel register so we can read the PHYID
3694          * later.
3695          */
3696         tg3_writephy(tp, 0x10, 0x8011);
3697 }
3698
3699 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3700 {
3701         u16 flowctrl;
3702         u32 sg_dig_ctrl, sg_dig_status;
3703         u32 serdes_cfg, expected_sg_dig_ctrl;
3704         int workaround, port_a;
3705         int current_link_up;
3706
3707         serdes_cfg = 0;
3708         expected_sg_dig_ctrl = 0;
3709         workaround = 0;
3710         port_a = 1;
3711         current_link_up = 0;
3712
3713         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3714             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3715                 workaround = 1;
3716                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3717                         port_a = 0;
3718
3719                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3720                 /* preserve bits 20-23 for voltage regulator */
3721                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3722         }
3723
3724         sg_dig_ctrl = tr32(SG_DIG_CTRL);
3725
3726         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3727                 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3728                         if (workaround) {
3729                                 u32 val = serdes_cfg;
3730
3731                                 if (port_a)
3732                                         val |= 0xc010000;
3733                                 else
3734                                         val |= 0x4010000;
3735                                 tw32_f(MAC_SERDES_CFG, val);
3736                         }
3737
3738                         tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3739                 }
3740                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3741                         tg3_setup_flow_control(tp, 0, 0);
3742                         current_link_up = 1;
3743                 }
3744                 goto out;
3745         }
3746
3747         /* Want auto-negotiation.  */
3748         expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3749
3750         flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3751         if (flowctrl & ADVERTISE_1000XPAUSE)
3752                 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3753         if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3754                 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3755
3756         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3757                 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
3758                     tp->serdes_counter &&
3759                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
3760                                     MAC_STATUS_RCVD_CFG)) ==
3761                      MAC_STATUS_PCS_SYNCED)) {
3762                         tp->serdes_counter--;
3763                         current_link_up = 1;
3764                         goto out;
3765                 }
3766 restart_autoneg:
3767                 if (workaround)
3768                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3769                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3770                 udelay(5);
3771                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3772
3773                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3774                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3775         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3776                                  MAC_STATUS_SIGNAL_DET)) {
3777                 sg_dig_status = tr32(SG_DIG_STATUS);
3778                 mac_status = tr32(MAC_STATUS);
3779
3780                 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3781                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
3782                         u32 local_adv = 0, remote_adv = 0;
3783
3784                         if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3785                                 local_adv |= ADVERTISE_1000XPAUSE;
3786                         if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3787                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3788
3789                         if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3790                                 remote_adv |= LPA_1000XPAUSE;
3791                         if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3792                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3793
3794                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3795                         current_link_up = 1;
3796                         tp->serdes_counter = 0;
3797                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3798                 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3799                         if (tp->serdes_counter)
3800                                 tp->serdes_counter--;
3801                         else {
3802                                 if (workaround) {
3803                                         u32 val = serdes_cfg;
3804
3805                                         if (port_a)
3806                                                 val |= 0xc010000;
3807                                         else
3808                                                 val |= 0x4010000;
3809
3810                                         tw32_f(MAC_SERDES_CFG, val);
3811                                 }
3812
3813                                 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3814                                 udelay(40);
3815
3816                                 /* Link parallel detection - link is up */
3817                                 /* only if we have PCS_SYNC and not */
3818                                 /* receiving config code words */
3819                                 mac_status = tr32(MAC_STATUS);
3820                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3821                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
3822                                         tg3_setup_flow_control(tp, 0, 0);
3823                                         current_link_up = 1;
3824                                         tp->phy_flags |=
3825                                                 TG3_PHYFLG_PARALLEL_DETECT;
3826                                         tp->serdes_counter =
3827                                                 SERDES_PARALLEL_DET_TIMEOUT;
3828                                 } else
3829                                         goto restart_autoneg;
3830                         }
3831                 }
3832         } else {
3833                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3834                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
3835         }
3836
3837 out:
3838         return current_link_up;
3839 }
3840
3841 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3842 {
3843         int current_link_up = 0;
3844
3845         if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3846                 goto out;
3847
3848         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3849                 u32 txflags, rxflags;
3850                 int i;
3851
3852                 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3853                         u32 local_adv = 0, remote_adv = 0;
3854
3855                         if (txflags & ANEG_CFG_PS1)
3856                                 local_adv |= ADVERTISE_1000XPAUSE;
3857                         if (txflags & ANEG_CFG_PS2)
3858                                 local_adv |= ADVERTISE_1000XPSE_ASYM;
3859
3860                         if (rxflags & MR_LP_ADV_SYM_PAUSE)
3861                                 remote_adv |= LPA_1000XPAUSE;
3862                         if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3863                                 remote_adv |= LPA_1000XPAUSE_ASYM;
3864
3865                         tg3_setup_flow_control(tp, local_adv, remote_adv);
3866
3867                         current_link_up = 1;
3868                 }
3869                 for (i = 0; i < 30; i++) {
3870                         udelay(20);
3871                         tw32_f(MAC_STATUS,
3872                                (MAC_STATUS_SYNC_CHANGED |
3873                                 MAC_STATUS_CFG_CHANGED));
3874                         udelay(40);
3875                         if ((tr32(MAC_STATUS) &
3876                              (MAC_STATUS_SYNC_CHANGED |
3877                               MAC_STATUS_CFG_CHANGED)) == 0)
3878                                 break;
3879                 }
3880
3881                 mac_status = tr32(MAC_STATUS);
3882                 if (current_link_up == 0 &&
3883                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
3884                     !(mac_status & MAC_STATUS_RCVD_CFG))
3885                         current_link_up = 1;
3886         } else {
3887                 tg3_setup_flow_control(tp, 0, 0);
3888
3889                 /* Forcing 1000FD link up. */
3890                 current_link_up = 1;
3891
3892                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3893                 udelay(40);
3894
3895                 tw32_f(MAC_MODE, tp->mac_mode);
3896                 udelay(40);
3897         }
3898
3899 out:
3900         return current_link_up;
3901 }
3902
3903 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3904 {
3905         u32 orig_pause_cfg;
3906         u16 orig_active_speed;
3907         u8 orig_active_duplex;
3908         u32 mac_status;
3909         int current_link_up;
3910         int i;
3911
3912         orig_pause_cfg = tp->link_config.active_flowctrl;
3913         orig_active_speed = tp->link_config.active_speed;
3914         orig_active_duplex = tp->link_config.active_duplex;
3915
3916         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3917             netif_carrier_ok(tp->dev) &&
3918             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3919                 mac_status = tr32(MAC_STATUS);
3920                 mac_status &= (MAC_STATUS_PCS_SYNCED |
3921                                MAC_STATUS_SIGNAL_DET |
3922                                MAC_STATUS_CFG_CHANGED |
3923                                MAC_STATUS_RCVD_CFG);
3924                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3925                                    MAC_STATUS_SIGNAL_DET)) {
3926                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3927                                             MAC_STATUS_CFG_CHANGED));
3928                         return 0;
3929                 }
3930         }
3931
3932         tw32_f(MAC_TX_AUTO_NEG, 0);
3933
3934         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3935         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3936         tw32_f(MAC_MODE, tp->mac_mode);
3937         udelay(40);
3938
3939         if (tp->phy_id == TG3_PHY_ID_BCM8002)
3940                 tg3_init_bcm8002(tp);
3941
3942         /* Enable link change event even when serdes polling.  */
3943         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3944         udelay(40);
3945
3946         current_link_up = 0;
3947         mac_status = tr32(MAC_STATUS);
3948
3949         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3950                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3951         else
3952                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3953
3954         tp->napi[0].hw_status->status =
3955                 (SD_STATUS_UPDATED |
3956                  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3957
3958         for (i = 0; i < 100; i++) {
3959                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3960                                     MAC_STATUS_CFG_CHANGED));
3961                 udelay(5);
3962                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3963                                          MAC_STATUS_CFG_CHANGED |
3964                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3965                         break;
3966         }
3967
3968         mac_status = tr32(MAC_STATUS);
3969         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3970                 current_link_up = 0;
3971                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3972                     tp->serdes_counter == 0) {
3973                         tw32_f(MAC_MODE, (tp->mac_mode |
3974                                           MAC_MODE_SEND_CONFIGS));
3975                         udelay(1);
3976                         tw32_f(MAC_MODE, tp->mac_mode);
3977                 }
3978         }
3979
3980         if (current_link_up == 1) {
3981                 tp->link_config.active_speed = SPEED_1000;
3982                 tp->link_config.active_duplex = DUPLEX_FULL;
3983                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3984                                     LED_CTRL_LNKLED_OVERRIDE |
3985                                     LED_CTRL_1000MBPS_ON));
3986         } else {
3987                 tp->link_config.active_speed = SPEED_INVALID;
3988                 tp->link_config.active_duplex = DUPLEX_INVALID;
3989                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
3990                                     LED_CTRL_LNKLED_OVERRIDE |
3991                                     LED_CTRL_TRAFFIC_OVERRIDE));
3992         }
3993
3994         if (current_link_up != netif_carrier_ok(tp->dev)) {
3995                 if (current_link_up)
3996                         netif_carrier_on(tp->dev);
3997                 else
3998                         netif_carrier_off(tp->dev);
3999                 tg3_link_report(tp);
4000         } else {
4001                 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4002                 if (orig_pause_cfg != now_pause_cfg ||
4003                     orig_active_speed != tp->link_config.active_speed ||
4004                     orig_active_duplex != tp->link_config.active_duplex)
4005                         tg3_link_report(tp);
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4012 {
4013         int current_link_up, err = 0;
4014         u32 bmsr, bmcr;
4015         u16 current_speed;
4016         u8 current_duplex;
4017         u32 local_adv, remote_adv;
4018
4019         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4020         tw32_f(MAC_MODE, tp->mac_mode);
4021         udelay(40);
4022
4023         tw32(MAC_EVENT, 0);
4024
4025         tw32_f(MAC_STATUS,
4026              (MAC_STATUS_SYNC_CHANGED |
4027               MAC_STATUS_CFG_CHANGED |
4028               MAC_STATUS_MI_COMPLETION |
4029               MAC_STATUS_LNKSTATE_CHANGED));
4030         udelay(40);
4031
4032         if (force_reset)
4033                 tg3_phy_reset(tp);
4034
4035         current_link_up = 0;
4036         current_speed = SPEED_INVALID;
4037         current_duplex = DUPLEX_INVALID;
4038
4039         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4040         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4041         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4042                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4043                         bmsr |= BMSR_LSTATUS;
4044                 else
4045                         bmsr &= ~BMSR_LSTATUS;
4046         }
4047
4048         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4049
4050         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4051             (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4052                 /* do nothing, just check for link up at the end */
4053         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4054                 u32 adv, new_adv;
4055
4056                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4057                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4058                                   ADVERTISE_1000XPAUSE |
4059                                   ADVERTISE_1000XPSE_ASYM |
4060                                   ADVERTISE_SLCT);
4061
4062                 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4063
4064                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4065                         new_adv |= ADVERTISE_1000XHALF;
4066                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4067                         new_adv |= ADVERTISE_1000XFULL;
4068
4069                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4070                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
4071                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4072                         tg3_writephy(tp, MII_BMCR, bmcr);
4073
4074                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4075                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4076                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4077
4078                         return err;
4079                 }
4080         } else {
4081                 u32 new_bmcr;
4082
4083                 bmcr &= ~BMCR_SPEED1000;
4084                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4085
4086                 if (tp->link_config.duplex == DUPLEX_FULL)
4087                         new_bmcr |= BMCR_FULLDPLX;
4088
4089                 if (new_bmcr != bmcr) {
4090                         /* BMCR_SPEED1000 is a reserved bit that needs
4091                          * to be set on write.
4092                          */
4093                         new_bmcr |= BMCR_SPEED1000;
4094
4095                         /* Force a linkdown */
4096                         if (netif_carrier_ok(tp->dev)) {
4097                                 u32 adv;
4098
4099                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4100                                 adv &= ~(ADVERTISE_1000XFULL |
4101                                          ADVERTISE_1000XHALF |
4102                                          ADVERTISE_SLCT);
4103                                 tg3_writephy(tp, MII_ADVERTISE, adv);
4104                                 tg3_writephy(tp, MII_BMCR, bmcr |
4105                                                            BMCR_ANRESTART |
4106                                                            BMCR_ANENABLE);
4107                                 udelay(10);
4108                                 netif_carrier_off(tp->dev);
4109                         }
4110                         tg3_writephy(tp, MII_BMCR, new_bmcr);
4111                         bmcr = new_bmcr;
4112                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4113                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4114                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4115                             ASIC_REV_5714) {
4116                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4117                                         bmsr |= BMSR_LSTATUS;
4118                                 else
4119                                         bmsr &= ~BMSR_LSTATUS;
4120                         }
4121                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4122                 }
4123         }
4124
4125         if (bmsr & BMSR_LSTATUS) {
4126                 current_speed = SPEED_1000;
4127                 current_link_up = 1;
4128                 if (bmcr & BMCR_FULLDPLX)
4129                         current_duplex = DUPLEX_FULL;
4130                 else
4131                         current_duplex = DUPLEX_HALF;
4132
4133                 local_adv = 0;
4134                 remote_adv = 0;
4135
4136                 if (bmcr & BMCR_ANENABLE) {
4137                         u32 common;
4138
4139                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4140                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4141                         common = local_adv & remote_adv;
4142                         if (common & (ADVERTISE_1000XHALF |
4143                                       ADVERTISE_1000XFULL)) {
4144                                 if (common & ADVERTISE_1000XFULL)
4145                                         current_duplex = DUPLEX_FULL;
4146                                 else
4147                                         current_duplex = DUPLEX_HALF;
4148                         } else if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
4149                                 /* Link is up via parallel detect */
4150                         } else {
4151                                 current_link_up = 0;
4152                         }
4153                 }
4154         }
4155
4156         if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4157                 tg3_setup_flow_control(tp, local_adv, remote_adv);
4158
4159         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4160         if (tp->link_config.active_duplex == DUPLEX_HALF)
4161                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4162
4163         tw32_f(MAC_MODE, tp->mac_mode);
4164         udelay(40);
4165
4166         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4167
4168         tp->link_config.active_speed = current_speed;
4169         tp->link_config.active_duplex = current_duplex;
4170
4171         if (current_link_up != netif_carrier_ok(tp->dev)) {
4172                 if (current_link_up)
4173                         netif_carrier_on(tp->dev);
4174                 else {
4175                         netif_carrier_off(tp->dev);
4176                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4177                 }
4178                 tg3_link_report(tp);
4179         }
4180         return err;
4181 }
4182
4183 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4184 {
4185         if (tp->serdes_counter) {
4186                 /* Give autoneg time to complete. */
4187                 tp->serdes_counter--;
4188                 return;
4189         }
4190
4191         if (!netif_carrier_ok(tp->dev) &&
4192             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4193                 u32 bmcr;
4194
4195                 tg3_readphy(tp, MII_BMCR, &bmcr);
4196                 if (bmcr & BMCR_ANENABLE) {
4197                         u32 phy1, phy2;
4198
4199                         /* Select shadow register 0x1f */
4200                         tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
4201                         tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
4202
4203                         /* Select expansion interrupt status register */
4204                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4205                                          MII_TG3_DSP_EXP1_INT_STAT);
4206                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4207                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4208
4209                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4210                                 /* We have signal detect and not receiving
4211                                  * config code words, link is up by parallel
4212                                  * detection.
4213                                  */
4214
4215                                 bmcr &= ~BMCR_ANENABLE;
4216                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4217                                 tg3_writephy(tp, MII_BMCR, bmcr);
4218                                 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
4219                         }
4220                 }
4221         } else if (netif_carrier_ok(tp->dev) &&
4222                    (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4223                    (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
4224                 u32 phy2;
4225
4226                 /* Select expansion interrupt status register */
4227                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
4228                                  MII_TG3_DSP_EXP1_INT_STAT);
4229                 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
4230                 if (phy2 & 0x20) {
4231                         u32 bmcr;
4232
4233                         /* Config code words received, turn on autoneg. */
4234                         tg3_readphy(tp, MII_BMCR, &bmcr);
4235                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4236
4237                         tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4238
4239                 }
4240         }
4241 }
4242
4243 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4244 {
4245         int err;
4246
4247         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
4248                 err = tg3_setup_fiber_phy(tp, force_reset);
4249         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4250                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4251         else
4252                 err = tg3_setup_copper_phy(tp, force_reset);
4253
4254         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4255                 u32 val, scale;
4256
4257                 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4258                 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4259                         scale = 65;
4260                 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4261                         scale = 6;
4262                 else
4263                         scale = 12;
4264
4265                 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4266                 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4267                 tw32(GRC_MISC_CFG, val);
4268         }
4269
4270         if (tp->link_config.active_speed == SPEED_1000 &&
4271             tp->link_config.active_duplex == DUPLEX_HALF)
4272                 tw32(MAC_TX_LENGTHS,
4273                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4274                       (6 << TX_LENGTHS_IPG_SHIFT) |
4275                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4276         else
4277                 tw32(MAC_TX_LENGTHS,
4278                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4279                       (6 << TX_LENGTHS_IPG_SHIFT) |
4280                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4281
4282         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4283                 if (netif_carrier_ok(tp->dev)) {
4284                         tw32(HOSTCC_STAT_COAL_TICKS,
4285                              tp->coal.stats_block_coalesce_usecs);
4286                 } else {
4287                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
4288                 }
4289         }
4290
4291         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4292                 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4293                 if (!netif_carrier_ok(tp->dev))
4294                         val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4295                               tp->pwrmgmt_thresh;
4296                 else
4297                         val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4298                 tw32(PCIE_PWR_MGMT_THRESH, val);
4299         }
4300
4301         return err;
4302 }
4303
4304 static inline int tg3_irq_sync(struct tg3 *tp)
4305 {
4306         return tp->irq_sync;
4307 }
4308
4309 /* This is called whenever we suspect that the system chipset is re-
4310  * ordering the sequence of MMIO to the tx send mailbox. The symptom
4311  * is bogus tx completions. We try to recover by setting the
4312  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4313  * in the workqueue.
4314  */
4315 static void tg3_tx_recover(struct tg3 *tp)
4316 {
4317         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4318                tp->write32_tx_mbox == tg3_write_indirect_mbox);
4319
4320         netdev_warn(tp->dev,
4321                     "The system may be re-ordering memory-mapped I/O "
4322                     "cycles to the network device, attempting to recover. "
4323                     "Please report the problem to the driver maintainer "
4324                     "and include system chipset information.\n");
4325
4326         spin_lock(&tp->lock);
4327         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4328         spin_unlock(&tp->lock);
4329 }
4330
4331 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4332 {
4333         /* Tell compiler to fetch tx indices from memory. */
4334         barrier();
4335         return tnapi->tx_pending -
4336                ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4337 }
4338
4339 /* Tigon3 never reports partial packet sends.  So we do not
4340  * need special logic to handle SKBs that have not had all
4341  * of their frags sent yet, like SunGEM does.
4342  */
4343 static void tg3_tx(struct tg3_napi *tnapi)
4344 {
4345         struct tg3 *tp = tnapi->tp;
4346         u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4347         u32 sw_idx = tnapi->tx_cons;
4348         struct netdev_queue *txq;
4349         int index = tnapi - tp->napi;
4350
4351         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4352                 index--;
4353
4354         txq = netdev_get_tx_queue(tp->dev, index);
4355
4356         while (sw_idx != hw_idx) {
4357                 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4358                 struct sk_buff *skb = ri->skb;
4359                 int i, tx_bug = 0;
4360
4361                 if (unlikely(skb == NULL)) {
4362                         tg3_tx_recover(tp);
4363                         return;
4364                 }
4365
4366                 pci_unmap_single(tp->pdev,
4367                                  dma_unmap_addr(ri, mapping),
4368                                  skb_headlen(skb),
4369                                  PCI_DMA_TODEVICE);
4370
4371                 ri->skb = NULL;
4372
4373                 sw_idx = NEXT_TX(sw_idx);
4374
4375                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4376                         ri = &tnapi->tx_buffers[sw_idx];
4377                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4378                                 tx_bug = 1;
4379
4380                         pci_unmap_page(tp->pdev,
4381                                        dma_unmap_addr(ri, mapping),
4382                                        skb_shinfo(skb)->frags[i].size,
4383                                        PCI_DMA_TODEVICE);
4384                         sw_idx = NEXT_TX(sw_idx);
4385                 }
4386
4387                 dev_kfree_skb(skb);
4388
4389                 if (unlikely(tx_bug)) {
4390                         tg3_tx_recover(tp);
4391                         return;
4392                 }
4393         }
4394
4395         tnapi->tx_cons = sw_idx;
4396
4397         /* Need to make the tx_cons update visible to tg3_start_xmit()
4398          * before checking for netif_queue_stopped().  Without the
4399          * memory barrier, there is a small possibility that tg3_start_xmit()
4400          * will miss it and cause the queue to be stopped forever.
4401          */
4402         smp_mb();
4403
4404         if (unlikely(netif_tx_queue_stopped(txq) &&
4405                      (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4406                 __netif_tx_lock(txq, smp_processor_id());
4407                 if (netif_tx_queue_stopped(txq) &&
4408                     (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4409                         netif_tx_wake_queue(txq);
4410                 __netif_tx_unlock(txq);
4411         }
4412 }
4413
4414 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4415 {
4416         if (!ri->skb)
4417                 return;
4418
4419         pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
4420                          map_sz, PCI_DMA_FROMDEVICE);
4421         dev_kfree_skb_any(ri->skb);
4422         ri->skb = NULL;
4423 }
4424
4425 /* Returns size of skb allocated or < 0 on error.
4426  *
4427  * We only need to fill in the address because the other members
4428  * of the RX descriptor are invariant, see tg3_init_rings.
4429  *
4430  * Note the purposeful assymetry of cpu vs. chip accesses.  For
4431  * posting buffers we only dirty the first cache line of the RX
4432  * descriptor (containing the address).  Whereas for the RX status
4433  * buffers the cpu only reads the last cacheline of the RX descriptor
4434  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4435  */
4436 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4437                             u32 opaque_key, u32 dest_idx_unmasked)
4438 {
4439         struct tg3_rx_buffer_desc *desc;
4440         struct ring_info *map, *src_map;
4441         struct sk_buff *skb;
4442         dma_addr_t mapping;
4443         int skb_size, dest_idx;
4444
4445         src_map = NULL;
4446         switch (opaque_key) {
4447         case RXD_OPAQUE_RING_STD:
4448                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4449                 desc = &tpr->rx_std[dest_idx];
4450                 map = &tpr->rx_std_buffers[dest_idx];
4451                 skb_size = tp->rx_pkt_map_sz;
4452                 break;
4453
4454         case RXD_OPAQUE_RING_JUMBO:
4455                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4456                 desc = &tpr->rx_jmb[dest_idx].std;
4457                 map = &tpr->rx_jmb_buffers[dest_idx];
4458                 skb_size = TG3_RX_JMB_MAP_SZ;
4459                 break;
4460
4461         default:
4462                 return -EINVAL;
4463         }
4464
4465         /* Do not overwrite any of the map or rp information
4466          * until we are sure we can commit to a new buffer.
4467          *
4468          * Callers depend upon this behavior and assume that
4469          * we leave everything unchanged if we fail.
4470          */
4471         skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4472         if (skb == NULL)
4473                 return -ENOMEM;
4474
4475         skb_reserve(skb, tp->rx_offset);
4476
4477         mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4478                                  PCI_DMA_FROMDEVICE);
4479         if (pci_dma_mapping_error(tp->pdev, mapping)) {
4480                 dev_kfree_skb(skb);
4481                 return -EIO;
4482         }
4483
4484         map->skb = skb;
4485         dma_unmap_addr_set(map, mapping, mapping);
4486
4487         desc->addr_hi = ((u64)mapping >> 32);
4488         desc->addr_lo = ((u64)mapping & 0xffffffff);
4489
4490         return skb_size;
4491 }
4492
4493 /* We only need to move over in the address because the other
4494  * members of the RX descriptor are invariant.  See notes above
4495  * tg3_alloc_rx_skb for full details.
4496  */
4497 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4498                            struct tg3_rx_prodring_set *dpr,
4499                            u32 opaque_key, int src_idx,
4500                            u32 dest_idx_unmasked)
4501 {
4502         struct tg3 *tp = tnapi->tp;
4503         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4504         struct ring_info *src_map, *dest_map;
4505         struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
4506         int dest_idx;
4507
4508         switch (opaque_key) {
4509         case RXD_OPAQUE_RING_STD:
4510                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4511                 dest_desc = &dpr->rx_std[dest_idx];
4512                 dest_map = &dpr->rx_std_buffers[dest_idx];
4513                 src_desc = &spr->rx_std[src_idx];
4514                 src_map = &spr->rx_std_buffers[src_idx];
4515                 break;
4516
4517         case RXD_OPAQUE_RING_JUMBO:
4518                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4519                 dest_desc = &dpr->rx_jmb[dest_idx].std;
4520                 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4521                 src_desc = &spr->rx_jmb[src_idx].std;
4522                 src_map = &spr->rx_jmb_buffers[src_idx];
4523                 break;
4524
4525         default:
4526                 return;
4527         }
4528
4529         dest_map->skb = src_map->skb;
4530         dma_unmap_addr_set(dest_map, mapping,
4531                            dma_unmap_addr(src_map, mapping));
4532         dest_desc->addr_hi = src_desc->addr_hi;
4533         dest_desc->addr_lo = src_desc->addr_lo;
4534
4535         /* Ensure that the update to the skb happens after the physical
4536          * addresses have been transferred to the new BD location.
4537          */
4538         smp_wmb();
4539
4540         src_map->skb = NULL;
4541 }
4542
4543 /* The RX ring scheme is composed of multiple rings which post fresh
4544  * buffers to the chip, and one special ring the chip uses to report
4545  * status back to the host.
4546  *
4547  * The special ring reports the status of received packets to the
4548  * host.  The chip does not write into the original descriptor the
4549  * RX buffer was obtained from.  The chip simply takes the original
4550  * descriptor as provided by the host, updates the status and length
4551  * field, then writes this into the next status ring entry.
4552  *
4553  * Each ring the host uses to post buffers to the chip is described
4554  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
4555  * it is first placed into the on-chip ram.  When the packet's length
4556  * is known, it walks down the TG3_BDINFO entries to select the ring.
4557  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4558  * which is within the range of the new packet's length is chosen.
4559  *
4560  * The "separate ring for rx status" scheme may sound queer, but it makes
4561  * sense from a cache coherency perspective.  If only the host writes
4562  * to the buffer post rings, and only the chip writes to the rx status
4563  * rings, then cache lines never move beyond shared-modified state.
4564  * If both the host and chip were to write into the same ring, cache line
4565  * eviction could occur since both entities want it in an exclusive state.
4566  */
4567 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4568 {
4569         struct tg3 *tp = tnapi->tp;
4570         u32 work_mask, rx_std_posted = 0;
4571         u32 std_prod_idx, jmb_prod_idx;
4572         u32 sw_idx = tnapi->rx_rcb_ptr;
4573         u16 hw_idx;
4574         int received;
4575         struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
4576
4577         hw_idx = *(tnapi->rx_rcb_prod_idx);
4578         /*
4579          * We need to order the read of hw_idx and the read of
4580          * the opaque cookie.
4581          */
4582         rmb();
4583         work_mask = 0;
4584         received = 0;
4585         std_prod_idx = tpr->rx_std_prod_idx;
4586         jmb_prod_idx = tpr->rx_jmb_prod_idx;
4587         while (sw_idx != hw_idx && budget > 0) {
4588                 struct ring_info *ri;
4589                 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4590                 unsigned int len;
4591                 struct sk_buff *skb;
4592                 dma_addr_t dma_addr;
4593                 u32 opaque_key, desc_idx, *post_ptr;
4594                 bool hw_vlan __maybe_unused = false;
4595                 u16 vtag __maybe_unused = 0;
4596
4597                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4598                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4599                 if (opaque_key == RXD_OPAQUE_RING_STD) {
4600                         ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
4601                         dma_addr = dma_unmap_addr(ri, mapping);
4602                         skb = ri->skb;
4603                         post_ptr = &std_prod_idx;
4604                         rx_std_posted++;
4605                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4606                         ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
4607                         dma_addr = dma_unmap_addr(ri, mapping);
4608                         skb = ri->skb;
4609                         post_ptr = &jmb_prod_idx;
4610                 } else
4611                         goto next_pkt_nopost;
4612
4613                 work_mask |= opaque_key;
4614
4615                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4616                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4617                 drop_it:
4618                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4619                                        desc_idx, *post_ptr);
4620                 drop_it_no_recycle:
4621                         /* Other statistics kept track of by card. */
4622                         tp->net_stats.rx_dropped++;
4623                         goto next_pkt;
4624                 }
4625
4626                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4627                       ETH_FCS_LEN;
4628
4629                 if (len > TG3_RX_COPY_THRESH(tp)) {
4630                         int skb_size;
4631
4632                         skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4633                                                     *post_ptr);
4634                         if (skb_size < 0)
4635                                 goto drop_it;
4636
4637                         pci_unmap_single(tp->pdev, dma_addr, skb_size,
4638                                          PCI_DMA_FROMDEVICE);
4639
4640                         /* Ensure that the update to the skb happens
4641                          * after the usage of the old DMA mapping.
4642                          */
4643                         smp_wmb();
4644
4645                         ri->skb = NULL;
4646
4647                         skb_put(skb, len);
4648                 } else {
4649                         struct sk_buff *copy_skb;
4650
4651                         tg3_recycle_rx(tnapi, tpr, opaque_key,
4652                                        desc_idx, *post_ptr);
4653
4654                         copy_skb = netdev_alloc_skb(tp->dev, len + VLAN_HLEN +
4655                                                     TG3_RAW_IP_ALIGN);
4656                         if (copy_skb == NULL)
4657                                 goto drop_it_no_recycle;
4658
4659                         skb_reserve(copy_skb, TG3_RAW_IP_ALIGN + VLAN_HLEN);
4660                         skb_put(copy_skb, len);
4661                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4662                         skb_copy_from_linear_data(skb, copy_skb->data, len);
4663                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4664
4665                         /* We'll reuse the original ring buffer. */
4666                         skb = copy_skb;
4667                 }
4668
4669                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4670                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4671                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4672                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
4673                         skb->ip_summed = CHECKSUM_UNNECESSARY;
4674                 else
4675                         skb_checksum_none_assert(skb);
4676
4677                 skb->protocol = eth_type_trans(skb, tp->dev);
4678
4679                 if (len > (tp->dev->mtu + ETH_HLEN) &&
4680                     skb->protocol != htons(ETH_P_8021Q)) {
4681                         dev_kfree_skb(skb);
4682                         goto next_pkt;
4683                 }
4684
4685                 if (desc->type_flags & RXD_FLAG_VLAN &&
4686                     !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) {
4687                         vtag = desc->err_vlan & RXD_VLAN_MASK;
4688 #if TG3_VLAN_TAG_USED
4689                         if (tp->vlgrp)
4690                                 hw_vlan = true;
4691                         else
4692 #endif
4693                         {
4694                                 struct vlan_ethhdr *ve = (struct vlan_ethhdr *)
4695                                                     __skb_push(skb, VLAN_HLEN);
4696
4697                                 memmove(ve, skb->data + VLAN_HLEN,
4698                                         ETH_ALEN * 2);
4699                                 ve->h_vlan_proto = htons(ETH_P_8021Q);
4700                                 ve->h_vlan_TCI = htons(vtag);
4701                         }
4702                 }
4703
4704 #if TG3_VLAN_TAG_USED
4705                 if (hw_vlan)
4706                         vlan_gro_receive(&tnapi->napi, tp->vlgrp, vtag, skb);
4707                 else
4708 #endif
4709                         napi_gro_receive(&tnapi->napi, skb);
4710
4711                 received++;
4712                 budget--;
4713
4714 next_pkt:
4715                 (*post_ptr)++;
4716
4717                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4718                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4719                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4720                                      tpr->rx_std_prod_idx);
4721                         work_mask &= ~RXD_OPAQUE_RING_STD;
4722                         rx_std_posted = 0;
4723                 }
4724 next_pkt_nopost:
4725                 sw_idx++;
4726                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4727
4728                 /* Refresh hw_idx to see if there is new work */
4729                 if (sw_idx == hw_idx) {
4730                         hw_idx = *(tnapi->rx_rcb_prod_idx);
4731                         rmb();
4732                 }
4733         }
4734
4735         /* ACK the status ring. */
4736         tnapi->rx_rcb_ptr = sw_idx;
4737         tw32_rx_mbox(tnapi->consmbox, sw_idx);
4738
4739         /* Refill RX ring(s). */
4740         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
4741                 if (work_mask & RXD_OPAQUE_RING_STD) {
4742                         tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4744                                      tpr->rx_std_prod_idx);
4745                 }
4746                 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4747                         tpr->rx_jmb_prod_idx = jmb_prod_idx %
4748                                                TG3_RX_JUMBO_RING_SIZE;
4749                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4750                                      tpr->rx_jmb_prod_idx);
4751                 }
4752                 mmiowb();
4753         } else if (work_mask) {
4754                 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4755                  * updated before the producer indices can be updated.
4756                  */
4757                 smp_wmb();
4758
4759                 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4760                 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4761
4762                 if (tnapi != &tp->napi[1])
4763                         napi_schedule(&tp->napi[1].napi);
4764         }
4765
4766         return received;
4767 }
4768
4769 static void tg3_poll_link(struct tg3 *tp)
4770 {
4771         /* handle link change and other phy events */
4772         if (!(tp->tg3_flags &
4773               (TG3_FLAG_USE_LINKCHG_REG |
4774                TG3_FLAG_POLL_SERDES))) {
4775                 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4776
4777                 if (sblk->status & SD_STATUS_LINK_CHG) {
4778                         sblk->status = SD_STATUS_UPDATED |
4779                                        (sblk->status & ~SD_STATUS_LINK_CHG);
4780                         spin_lock(&tp->lock);
4781                         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4782                                 tw32_f(MAC_STATUS,
4783                                      (MAC_STATUS_SYNC_CHANGED |
4784                                       MAC_STATUS_CFG_CHANGED |
4785                                       MAC_STATUS_MI_COMPLETION |
4786                                       MAC_STATUS_LNKSTATE_CHANGED));
4787                                 udelay(40);
4788                         } else
4789                                 tg3_setup_phy(tp, 0);
4790                         spin_unlock(&tp->lock);
4791                 }
4792         }
4793 }
4794
4795 static int tg3_rx_prodring_xfer(struct tg3 *tp,
4796                                 struct tg3_rx_prodring_set *dpr,
4797                                 struct tg3_rx_prodring_set *spr)
4798 {
4799         u32 si, di, cpycnt, src_prod_idx;
4800         int i, err = 0;
4801
4802         while (1) {
4803                 src_prod_idx = spr->rx_std_prod_idx;
4804
4805                 /* Make sure updates to the rx_std_buffers[] entries and the
4806                  * standard producer index are seen in the correct order.
4807                  */
4808                 smp_rmb();
4809
4810                 if (spr->rx_std_cons_idx == src_prod_idx)
4811                         break;
4812
4813                 if (spr->rx_std_cons_idx < src_prod_idx)
4814                         cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4815                 else
4816                         cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4817
4818                 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4819
4820                 si = spr->rx_std_cons_idx;
4821                 di = dpr->rx_std_prod_idx;
4822
4823                 for (i = di; i < di + cpycnt; i++) {
4824                         if (dpr->rx_std_buffers[i].skb) {
4825                                 cpycnt = i - di;
4826                                 err = -ENOSPC;
4827                                 break;
4828                         }
4829                 }
4830
4831                 if (!cpycnt)
4832                         break;
4833
4834                 /* Ensure that updates to the rx_std_buffers ring and the
4835                  * shadowed hardware producer ring from tg3_recycle_skb() are
4836                  * ordered correctly WRT the skb check above.
4837                  */
4838                 smp_rmb();
4839
4840                 memcpy(&dpr->rx_std_buffers[di],
4841                        &spr->rx_std_buffers[si],
4842                        cpycnt * sizeof(struct ring_info));
4843
4844                 for (i = 0; i < cpycnt; i++, di++, si++) {
4845                         struct tg3_rx_buffer_desc *sbd, *dbd;
4846                         sbd = &spr->rx_std[si];
4847                         dbd = &dpr->rx_std[di];
4848                         dbd->addr_hi = sbd->addr_hi;
4849                         dbd->addr_lo = sbd->addr_lo;
4850                 }
4851
4852                 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4853                                        TG3_RX_RING_SIZE;
4854                 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4855                                        TG3_RX_RING_SIZE;
4856         }
4857
4858         while (1) {
4859                 src_prod_idx = spr->rx_jmb_prod_idx;
4860
4861                 /* Make sure updates to the rx_jmb_buffers[] entries and
4862                  * the jumbo producer index are seen in the correct order.
4863                  */
4864                 smp_rmb();
4865
4866                 if (spr->rx_jmb_cons_idx == src_prod_idx)
4867                         break;
4868
4869                 if (spr->rx_jmb_cons_idx < src_prod_idx)
4870                         cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4871                 else
4872                         cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4873
4874                 cpycnt = min(cpycnt,
4875                              TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4876
4877                 si = spr->rx_jmb_cons_idx;
4878                 di = dpr->rx_jmb_prod_idx;
4879
4880                 for (i = di; i < di + cpycnt; i++) {
4881                         if (dpr->rx_jmb_buffers[i].skb) {
4882                                 cpycnt = i - di;
4883                                 err = -ENOSPC;
4884                                 break;
4885                         }
4886                 }
4887
4888                 if (!cpycnt)
4889                         break;
4890
4891                 /* Ensure that updates to the rx_jmb_buffers ring and the
4892                  * shadowed hardware producer ring from tg3_recycle_skb() are
4893                  * ordered correctly WRT the skb check above.
4894                  */
4895                 smp_rmb();
4896
4897                 memcpy(&dpr->rx_jmb_buffers[di],
4898                        &spr->rx_jmb_buffers[si],
4899                        cpycnt * sizeof(struct ring_info));
4900
4901                 for (i = 0; i < cpycnt; i++, di++, si++) {
4902                         struct tg3_rx_buffer_desc *sbd, *dbd;
4903                         sbd = &spr->rx_jmb[si].std;
4904                         dbd = &dpr->rx_jmb[di].std;
4905                         dbd->addr_hi = sbd->addr_hi;
4906                         dbd->addr_lo = sbd->addr_lo;
4907                 }
4908
4909                 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4910                                        TG3_RX_JUMBO_RING_SIZE;
4911                 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4912                                        TG3_RX_JUMBO_RING_SIZE;
4913         }
4914
4915         return err;
4916 }
4917
4918 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4919 {
4920         struct tg3 *tp = tnapi->tp;
4921
4922         /* run TX completion thread */
4923         if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4924                 tg3_tx(tnapi);
4925                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4926                         return work_done;
4927         }
4928
4929         /* run RX thread, within the bounds set by NAPI.
4930          * All RX "locking" is done by ensuring outside
4931          * code synchronizes with tg3->napi.poll()
4932          */
4933         if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4934                 work_done += tg3_rx(tnapi, budget - work_done);
4935
4936         if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4937                 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
4938                 int i, err = 0;
4939                 u32 std_prod_idx = dpr->rx_std_prod_idx;
4940                 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
4941
4942                 for (i = 1; i < tp->irq_cnt; i++)
4943                         err |= tg3_rx_prodring_xfer(tp, dpr,
4944                                                     &tp->napi[i].prodring);
4945
4946                 wmb();
4947
4948                 if (std_prod_idx != dpr->rx_std_prod_idx)
4949                         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4950                                      dpr->rx_std_prod_idx);
4951
4952                 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
4953                         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4954                                      dpr->rx_jmb_prod_idx);
4955
4956                 mmiowb();
4957
4958                 if (err)
4959                         tw32_f(HOSTCC_MODE, tp->coal_now);
4960         }
4961
4962         return work_done;
4963 }
4964
4965 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4966 {
4967         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4968         struct tg3 *tp = tnapi->tp;
4969         int work_done = 0;
4970         struct tg3_hw_status *sblk = tnapi->hw_status;
4971
4972         while (1) {
4973                 work_done = tg3_poll_work(tnapi, work_done, budget);
4974
4975                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4976                         goto tx_recovery;
4977
4978                 if (unlikely(work_done >= budget))
4979                         break;
4980
4981                 /* tp->last_tag is used in tg3_int_reenable() below
4982                  * to tell the hw how much work has been processed,
4983                  * so we must read it before checking for more work.
4984                  */
4985                 tnapi->last_tag = sblk->status_tag;
4986                 tnapi->last_irq_tag = tnapi->last_tag;
4987                 rmb();
4988
4989                 /* check for RX/TX work to do */
4990                 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4991                            *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
4992                         napi_complete(napi);
4993                         /* Reenable interrupts. */
4994                         tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4995                         mmiowb();
4996                         break;
4997                 }
4998         }
4999
5000         return work_done;
5001
5002 tx_recovery:
5003         /* work_done is guaranteed to be less than budget. */
5004         napi_complete(napi);
5005         schedule_work(&tp->reset_task);
5006         return work_done;
5007 }
5008
5009 static int tg3_poll(struct napi_struct *napi, int budget)
5010 {
5011         struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
5012         struct tg3 *tp = tnapi->tp;
5013         int work_done = 0;
5014         struct tg3_hw_status *sblk = tnapi->hw_status;
5015
5016         while (1) {
5017                 tg3_poll_link(tp);
5018
5019                 work_done = tg3_poll_work(tnapi, work_done, budget);
5020
5021                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
5022                         goto tx_recovery;
5023
5024                 if (unlikely(work_done >= budget))
5025                         break;
5026
5027                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
5028                         /* tp->last_tag is used in tg3_int_reenable() below
5029                          * to tell the hw how much work has been processed,
5030                          * so we must read it before checking for more work.
5031                          */
5032                         tnapi->last_tag = sblk->status_tag;
5033                         tnapi->last_irq_tag = tnapi->last_tag;
5034                         rmb();
5035                 } else
5036                         sblk->status &= ~SD_STATUS_UPDATED;
5037
5038                 if (likely(!tg3_has_work(tnapi))) {
5039                         napi_complete(napi);
5040                         tg3_int_reenable(tnapi);
5041                         break;
5042                 }
5043         }
5044
5045         return work_done;
5046
5047 tx_recovery:
5048         /* work_done is guaranteed to be less than budget. */
5049         napi_complete(napi);
5050         schedule_work(&tp->reset_task);
5051         return work_done;
5052 }
5053
5054 static void tg3_napi_disable(struct tg3 *tp)
5055 {
5056         int i;
5057
5058         for (i = tp->irq_cnt - 1; i >= 0; i--)
5059                 napi_disable(&tp->napi[i].napi);
5060 }
5061
5062 static void tg3_napi_enable(struct tg3 *tp)
5063 {
5064         int i;
5065
5066         for (i = 0; i < tp->irq_cnt; i++)
5067                 napi_enable(&tp->napi[i].napi);
5068 }
5069
5070 static void tg3_napi_init(struct tg3 *tp)
5071 {
5072         int i;
5073
5074         netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
5075         for (i = 1; i < tp->irq_cnt; i++)
5076                 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
5077 }
5078
5079 static void tg3_napi_fini(struct tg3 *tp)
5080 {
5081         int i;
5082
5083         for (i = 0; i < tp->irq_cnt; i++)
5084                 netif_napi_del(&tp->napi[i].napi);
5085 }
5086
5087 static inline void tg3_netif_stop(struct tg3 *tp)
5088 {
5089         tp->dev->trans_start = jiffies; /* prevent tx timeout */
5090         tg3_napi_disable(tp);
5091         netif_tx_disable(tp->dev);
5092 }
5093
5094 static inline void tg3_netif_start(struct tg3 *tp)
5095 {
5096         /* NOTE: unconditional netif_tx_wake_all_queues is only
5097          * appropriate so long as all callers are assured to
5098          * have free tx slots (such as after tg3_init_hw)
5099          */
5100         netif_tx_wake_all_queues(tp->dev);
5101
5102         tg3_napi_enable(tp);
5103         tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
5104         tg3_enable_ints(tp);
5105 }
5106
5107 static void tg3_irq_quiesce(struct tg3 *tp)
5108 {
5109         int i;
5110
5111         BUG_ON(tp->irq_sync);
5112
5113         tp->irq_sync = 1;
5114         smp_mb();
5115
5116         for (i = 0; i < tp->irq_cnt; i++)
5117                 synchronize_irq(tp->napi[i].irq_vec);
5118 }
5119
5120 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5121  * If irq_sync is non-zero, then the IRQ handler must be synchronized
5122  * with as well.  Most of the time, this is not necessary except when
5123  * shutting down the device.
5124  */
5125 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5126 {
5127         spin_lock_bh(&tp->lock);
5128         if (irq_sync)
5129                 tg3_irq_quiesce(tp);
5130 }
5131
5132 static inline void tg3_full_unlock(struct tg3 *tp)
5133 {
5134         spin_unlock_bh(&tp->lock);
5135 }
5136
5137 /* One-shot MSI handler - Chip automatically disables interrupt
5138  * after sending MSI so driver doesn't have to do it.
5139  */
5140 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5141 {
5142         struct tg3_napi *tnapi = dev_id;
5143         struct tg3 *tp = tnapi->tp;
5144
5145         prefetch(tnapi->hw_status);
5146         if (tnapi->rx_rcb)
5147                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5148
5149         if (likely(!tg3_irq_sync(tp)))
5150                 napi_schedule(&tnapi->napi);
5151
5152         return IRQ_HANDLED;
5153 }
5154
5155 /* MSI ISR - No need to check for interrupt sharing and no need to
5156  * flush status block and interrupt mailbox. PCI ordering rules
5157  * guarantee that MSI will arrive after the status block.
5158  */
5159 static irqreturn_t tg3_msi(int irq, void *dev_id)
5160 {
5161         struct tg3_napi *tnapi = dev_id;
5162         struct tg3 *tp = tnapi->tp;
5163
5164         prefetch(tnapi->hw_status);
5165         if (tnapi->rx_rcb)
5166                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5167         /*
5168          * Writing any value to intr-mbox-0 clears PCI INTA# and
5169          * chip-internal interrupt pending events.
5170          * Writing non-zero to intr-mbox-0 additional tells the
5171          * NIC to stop sending us irqs, engaging "in-intr-handler"
5172          * event coalescing.
5173          */
5174         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5175         if (likely(!tg3_irq_sync(tp)))
5176                 napi_schedule(&tnapi->napi);
5177
5178         return IRQ_RETVAL(1);
5179 }
5180
5181 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5182 {
5183         struct tg3_napi *tnapi = dev_id;
5184         struct tg3 *tp = tnapi->tp;
5185         struct tg3_hw_status *sblk = tnapi->hw_status;
5186         unsigned int handled = 1;
5187
5188         /* In INTx mode, it is possible for the interrupt to arrive at
5189          * the CPU before the status block posted prior to the interrupt.
5190          * Reading the PCI State register will confirm whether the
5191          * interrupt is ours and will flush the status block.
5192          */
5193         if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5194                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5195                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5196                         handled = 0;
5197                         goto out;
5198                 }
5199         }
5200
5201         /*
5202          * Writing any value to intr-mbox-0 clears PCI INTA# and
5203          * chip-internal interrupt pending events.
5204          * Writing non-zero to intr-mbox-0 additional tells the
5205          * NIC to stop sending us irqs, engaging "in-intr-handler"
5206          * event coalescing.
5207          *
5208          * Flush the mailbox to de-assert the IRQ immediately to prevent
5209          * spurious interrupts.  The flush impacts performance but
5210          * excessive spurious interrupts can be worse in some cases.
5211          */
5212         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5213         if (tg3_irq_sync(tp))
5214                 goto out;
5215         sblk->status &= ~SD_STATUS_UPDATED;
5216         if (likely(tg3_has_work(tnapi))) {
5217                 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5218                 napi_schedule(&tnapi->napi);
5219         } else {
5220                 /* No work, shared interrupt perhaps?  re-enable
5221                  * interrupts, and flush that PCI write
5222                  */
5223                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5224                                0x00000000);
5225         }
5226 out:
5227         return IRQ_RETVAL(handled);
5228 }
5229
5230 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5231 {
5232         struct tg3_napi *tnapi = dev_id;
5233         struct tg3 *tp = tnapi->tp;
5234         struct tg3_hw_status *sblk = tnapi->hw_status;
5235         unsigned int handled = 1;
5236
5237         /* In INTx mode, it is possible for the interrupt to arrive at
5238          * the CPU before the status block posted prior to the interrupt.
5239          * Reading the PCI State register will confirm whether the
5240          * interrupt is ours and will flush the status block.
5241          */
5242         if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5243                 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5244                     (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5245                         handled = 0;
5246                         goto out;
5247                 }
5248         }
5249
5250         /*
5251          * writing any value to intr-mbox-0 clears PCI INTA# and
5252          * chip-internal interrupt pending events.
5253          * writing non-zero to intr-mbox-0 additional tells the
5254          * NIC to stop sending us irqs, engaging "in-intr-handler"
5255          * event coalescing.
5256          *
5257          * Flush the mailbox to de-assert the IRQ immediately to prevent
5258          * spurious interrupts.  The flush impacts performance but
5259          * excessive spurious interrupts can be worse in some cases.
5260          */
5261         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5262
5263         /*
5264          * In a shared interrupt configuration, sometimes other devices'
5265          * interrupts will scream.  We record the current status tag here
5266          * so that the above check can report that the screaming interrupts
5267          * are unhandled.  Eventually they will be silenced.
5268          */
5269         tnapi->last_irq_tag = sblk->status_tag;
5270
5271         if (tg3_irq_sync(tp))
5272                 goto out;
5273
5274         prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5275
5276         napi_schedule(&tnapi->napi);
5277
5278 out:
5279         return IRQ_RETVAL(handled);
5280 }
5281
5282 /* ISR for interrupt test */
5283 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5284 {
5285         struct tg3_napi *tnapi = dev_id;
5286         struct tg3 *tp = tnapi->tp;
5287         struct tg3_hw_status *sblk = tnapi->hw_status;
5288
5289         if ((sblk->status & SD_STATUS_UPDATED) ||
5290             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5291                 tg3_disable_ints(tp);
5292                 return IRQ_RETVAL(1);
5293         }
5294         return IRQ_RETVAL(0);
5295 }
5296
5297 static int tg3_init_hw(struct tg3 *, int);
5298 static int tg3_halt(struct tg3 *, int, int);
5299
5300 /* Restart hardware after configuration changes, self-test, etc.
5301  * Invoked with tp->lock held.
5302  */
5303 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5304         __releases(tp->lock)
5305         __acquires(tp->lock)
5306 {
5307         int err;
5308
5309         err = tg3_init_hw(tp, reset_phy);
5310         if (err) {
5311                 netdev_err(tp->dev,
5312                            "Failed to re-initialize device, aborting\n");
5313                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5314                 tg3_full_unlock(tp);
5315                 del_timer_sync(&tp->timer);
5316                 tp->irq_sync = 0;
5317                 tg3_napi_enable(tp);
5318                 dev_close(tp->dev);
5319                 tg3_full_lock(tp, 0);
5320         }
5321         return err;
5322 }
5323
5324 #ifdef CONFIG_NET_POLL_CONTROLLER
5325 static void tg3_poll_controller(struct net_device *dev)
5326 {
5327         int i;
5328         struct tg3 *tp = netdev_priv(dev);
5329
5330         for (i = 0; i < tp->irq_cnt; i++)
5331                 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
5332 }
5333 #endif
5334
5335 static void tg3_reset_task(struct work_struct *work)
5336 {
5337         struct tg3 *tp = container_of(work, struct tg3, reset_task);
5338         int err;
5339         unsigned int restart_timer;
5340
5341         tg3_full_lock(tp, 0);
5342
5343         if (!netif_running(tp->dev)) {
5344                 tg3_full_unlock(tp);
5345                 return;
5346         }
5347
5348         tg3_full_unlock(tp);
5349
5350         tg3_phy_stop(tp);
5351
5352         tg3_netif_stop(tp);
5353
5354         tg3_full_lock(tp, 1);
5355
5356         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5357         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5358
5359         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5360                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5361                 tp->write32_rx_mbox = tg3_write_flush_reg32;
5362                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5363                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5364         }
5365
5366         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5367         err = tg3_init_hw(tp, 1);
5368         if (err)
5369                 goto out;
5370
5371         tg3_netif_start(tp);
5372
5373         if (restart_timer)
5374                 mod_timer(&tp->timer, jiffies + 1);
5375
5376 out:
5377         tg3_full_unlock(tp);
5378
5379         if (!err)
5380                 tg3_phy_start(tp);
5381 }
5382
5383 static void tg3_dump_short_state(struct tg3 *tp)
5384 {
5385         netdev_err(tp->dev, "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5386                    tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5387         netdev_err(tp->dev, "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5388                    tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5389 }
5390
5391 static void tg3_tx_timeout(struct net_device *dev)
5392 {
5393         struct tg3 *tp = netdev_priv(dev);
5394
5395         if (netif_msg_tx_err(tp)) {
5396                 netdev_err(dev, "transmit timed out, resetting\n");
5397                 tg3_dump_short_state(tp);
5398         }
5399
5400         schedule_work(&tp->reset_task);
5401 }
5402
5403 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5404 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5405 {
5406         u32 base = (u32) mapping & 0xffffffff;
5407
5408         return (base > 0xffffdcc0) && (base + len + 8 < base);
5409 }
5410
5411 /* Test for DMA addresses > 40-bit */
5412 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5413                                           int len)
5414 {
5415 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5416         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5417                 return ((u64) mapping + len) > DMA_BIT_MASK(40);
5418         return 0;
5419 #else
5420         return 0;
5421 #endif
5422 }
5423
5424 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5425
5426 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5427 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5428                                        struct sk_buff *skb, u32 last_plus_one,
5429                                        u32 *start, u32 base_flags, u32 mss)
5430 {
5431         struct tg3 *tp = tnapi->tp;
5432         struct sk_buff *new_skb;
5433         dma_addr_t new_addr = 0;
5434         u32 entry = *start;
5435         int i, ret = 0;
5436
5437         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5438                 new_skb = skb_copy(skb, GFP_ATOMIC);
5439         else {
5440                 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5441
5442                 new_skb = skb_copy_expand(skb,
5443                                           skb_headroom(skb) + more_headroom,
5444                                           skb_tailroom(skb), GFP_ATOMIC);
5445         }
5446
5447         if (!new_skb) {
5448                 ret = -1;
5449         } else {
5450                 /* New SKB is guaranteed to be linear. */
5451                 entry = *start;
5452                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5453                                           PCI_DMA_TODEVICE);
5454                 /* Make sure the mapping succeeded */
5455                 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5456                         ret = -1;
5457                         dev_kfree_skb(new_skb);
5458                         new_skb = NULL;
5459
5460                 /* Make sure new skb does not cross any 4G boundaries.
5461                  * Drop the packet if it does.
5462                  */
5463                 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5464                             tg3_4g_overflow_test(new_addr, new_skb->len)) {
5465                         pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5466                                          PCI_DMA_TODEVICE);
5467                         ret = -1;
5468                         dev_kfree_skb(new_skb);
5469                         new_skb = NULL;
5470                 } else {
5471                         tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5472                                     base_flags, 1 | (mss << 1));
5473                         *start = NEXT_TX(entry);
5474                 }
5475         }
5476
5477         /* Now clean up the sw ring entries. */
5478         i = 0;
5479         while (entry != last_plus_one) {
5480                 int len;
5481
5482                 if (i == 0)
5483                         len = skb_headlen(skb);
5484                 else
5485                         len = skb_shinfo(skb)->frags[i-1].size;
5486
5487                 pci_unmap_single(tp->pdev,
5488                                  dma_unmap_addr(&tnapi->tx_buffers[entry],
5489                                                 mapping),
5490                                  len, PCI_DMA_TODEVICE);
5491                 if (i == 0) {
5492                         tnapi->tx_buffers[entry].skb = new_skb;
5493                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5494                                            new_addr);
5495                 } else {
5496                         tnapi->tx_buffers[entry].skb = NULL;
5497                 }
5498                 entry = NEXT_TX(entry);
5499                 i++;
5500         }
5501
5502         dev_kfree_skb(skb);
5503
5504         return ret;
5505 }
5506
5507 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5508                         dma_addr_t mapping, int len, u32 flags,
5509                         u32 mss_and_is_end)
5510 {
5511         struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5512         int is_end = (mss_and_is_end & 0x1);
5513         u32 mss = (mss_and_is_end >> 1);
5514         u32 vlan_tag = 0;
5515
5516         if (is_end)
5517                 flags |= TXD_FLAG_END;
5518         if (flags & TXD_FLAG_VLAN) {
5519                 vlan_tag = flags >> 16;
5520                 flags &= 0xffff;
5521         }
5522         vlan_tag |= (mss << TXD_MSS_SHIFT);
5523
5524         txd->addr_hi = ((u64) mapping >> 32);
5525         txd->addr_lo = ((u64) mapping & 0xffffffff);
5526         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5527         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5528 }
5529
5530 /* hard_start_xmit for devices that don't have any bugs and
5531  * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5532  */
5533 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5534                                   struct net_device *dev)
5535 {
5536         struct tg3 *tp = netdev_priv(dev);
5537         u32 len, entry, base_flags, mss;
5538         dma_addr_t mapping;
5539         struct tg3_napi *tnapi;
5540         struct netdev_queue *txq;
5541         unsigned int i, last;
5542
5543         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5544         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5545         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5546                 tnapi++;
5547
5548         /* We are running in BH disabled context with netif_tx_lock
5549          * and TX reclaim runs via tp->napi.poll inside of a software
5550          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5551          * no IRQ context deadlocks to worry about either.  Rejoice!
5552          */
5553         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5554                 if (!netif_tx_queue_stopped(txq)) {
5555                         netif_tx_stop_queue(txq);
5556
5557                         /* This is a hard error, log it. */
5558                         netdev_err(dev,
5559                                    "BUG! Tx Ring full when queue awake!\n");
5560                 }
5561                 return NETDEV_TX_BUSY;
5562         }
5563
5564         entry = tnapi->tx_prod;
5565         base_flags = 0;
5566         mss = skb_shinfo(skb)->gso_size;
5567         if (mss) {
5568                 int tcp_opt_len, ip_tcp_len;
5569                 u32 hdrlen;
5570
5571                 if (skb_header_cloned(skb) &&
5572                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5573                         dev_kfree_skb(skb);
5574                         goto out_unlock;
5575                 }
5576
5577                 if (skb_is_gso_v6(skb)) {
5578                         hdrlen = skb_headlen(skb) - ETH_HLEN;
5579                 } else {
5580                         struct iphdr *iph = ip_hdr(skb);
5581
5582                         tcp_opt_len = tcp_optlen(skb);
5583                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5584
5585                         iph->check = 0;
5586                         iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5587                         hdrlen = ip_tcp_len + tcp_opt_len;
5588                 }
5589
5590                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5591                         mss |= (hdrlen & 0xc) << 12;
5592                         if (hdrlen & 0x10)
5593                                 base_flags |= 0x00000010;
5594                         base_flags |= (hdrlen & 0x3e0) << 5;
5595                 } else
5596                         mss |= hdrlen << 9;
5597
5598                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5599                                TXD_FLAG_CPU_POST_DMA);
5600
5601                 tcp_hdr(skb)->check = 0;
5602
5603         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
5604                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5605         }
5606
5607 #if TG3_VLAN_TAG_USED
5608         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5609                 base_flags |= (TXD_FLAG_VLAN |
5610                                (vlan_tx_tag_get(skb) << 16));
5611 #endif
5612
5613         len = skb_headlen(skb);
5614
5615         /* Queue skb data, a.k.a. the main skb fragment. */
5616         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5617         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5618                 dev_kfree_skb(skb);
5619                 goto out_unlock;
5620         }
5621
5622         tnapi->tx_buffers[entry].skb = skb;
5623         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5624
5625         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5626             !mss && skb->len > ETH_DATA_LEN)
5627                 base_flags |= TXD_FLAG_JMB_PKT;
5628
5629         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5630                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5631
5632         entry = NEXT_TX(entry);
5633
5634         /* Now loop through additional data fragments, and queue them. */
5635         if (skb_shinfo(skb)->nr_frags > 0) {
5636                 last = skb_shinfo(skb)->nr_frags - 1;
5637                 for (i = 0; i <= last; i++) {
5638                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5639
5640                         len = frag->size;
5641                         mapping = pci_map_page(tp->pdev,
5642                                                frag->page,
5643                                                frag->page_offset,
5644                                                len, PCI_DMA_TODEVICE);
5645                         if (pci_dma_mapping_error(tp->pdev, mapping))
5646                                 goto dma_error;
5647
5648                         tnapi->tx_buffers[entry].skb = NULL;
5649                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5650                                            mapping);
5651
5652                         tg3_set_txd(tnapi, entry, mapping, len,
5653                                     base_flags, (i == last) | (mss << 1));
5654
5655                         entry = NEXT_TX(entry);
5656                 }
5657         }
5658
5659         /* Packets are ready, update Tx producer idx local and on card. */
5660         tw32_tx_mbox(tnapi->prodmbox, entry);
5661
5662         tnapi->tx_prod = entry;
5663         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5664                 netif_tx_stop_queue(txq);
5665
5666                 /* netif_tx_stop_queue() must be done before checking
5667                  * checking tx index in tg3_tx_avail() below, because in
5668                  * tg3_tx(), we update tx index before checking for
5669                  * netif_tx_queue_stopped().
5670                  */
5671                 smp_mb();
5672                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5673                         netif_tx_wake_queue(txq);
5674         }
5675
5676 out_unlock:
5677         mmiowb();
5678
5679         return NETDEV_TX_OK;
5680
5681 dma_error:
5682         last = i;
5683         entry = tnapi->tx_prod;
5684         tnapi->tx_buffers[entry].skb = NULL;
5685         pci_unmap_single(tp->pdev,
5686                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5687                          skb_headlen(skb),
5688                          PCI_DMA_TODEVICE);
5689         for (i = 0; i <= last; i++) {
5690                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5691                 entry = NEXT_TX(entry);
5692
5693                 pci_unmap_page(tp->pdev,
5694                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5695                                               mapping),
5696                                frag->size, PCI_DMA_TODEVICE);
5697         }
5698
5699         dev_kfree_skb(skb);
5700         return NETDEV_TX_OK;
5701 }
5702
5703 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5704                                           struct net_device *);
5705
5706 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5707  * TSO header is greater than 80 bytes.
5708  */
5709 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5710 {
5711         struct sk_buff *segs, *nskb;
5712         u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5713
5714         /* Estimate the number of fragments in the worst case */
5715         if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5716                 netif_stop_queue(tp->dev);
5717
5718                 /* netif_tx_stop_queue() must be done before checking
5719                  * checking tx index in tg3_tx_avail() below, because in
5720                  * tg3_tx(), we update tx index before checking for
5721                  * netif_tx_queue_stopped().
5722                  */
5723                 smp_mb();
5724                 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5725                         return NETDEV_TX_BUSY;
5726
5727                 netif_wake_queue(tp->dev);
5728         }
5729
5730         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5731         if (IS_ERR(segs))
5732                 goto tg3_tso_bug_end;
5733
5734         do {
5735                 nskb = segs;
5736                 segs = segs->next;
5737                 nskb->next = NULL;
5738                 tg3_start_xmit_dma_bug(nskb, tp->dev);
5739         } while (segs);
5740
5741 tg3_tso_bug_end:
5742         dev_kfree_skb(skb);
5743
5744         return NETDEV_TX_OK;
5745 }
5746
5747 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5748  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5749  */
5750 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5751                                           struct net_device *dev)
5752 {
5753         struct tg3 *tp = netdev_priv(dev);
5754         u32 len, entry, base_flags, mss;
5755         int would_hit_hwbug;
5756         dma_addr_t mapping;
5757         struct tg3_napi *tnapi;
5758         struct netdev_queue *txq;
5759         unsigned int i, last;
5760
5761         txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5762         tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5763         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5764                 tnapi++;
5765
5766         /* We are running in BH disabled context with netif_tx_lock
5767          * and TX reclaim runs via tp->napi.poll inside of a software
5768          * interrupt.  Furthermore, IRQ processing runs lockless so we have
5769          * no IRQ context deadlocks to worry about either.  Rejoice!
5770          */
5771         if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5772                 if (!netif_tx_queue_stopped(txq)) {
5773                         netif_tx_stop_queue(txq);
5774
5775                         /* This is a hard error, log it. */
5776                         netdev_err(dev,
5777                                    "BUG! Tx Ring full when queue awake!\n");
5778                 }
5779                 return NETDEV_TX_BUSY;
5780         }
5781
5782         entry = tnapi->tx_prod;
5783         base_flags = 0;
5784         if (skb->ip_summed == CHECKSUM_PARTIAL)
5785                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5786
5787         mss = skb_shinfo(skb)->gso_size;
5788         if (mss) {
5789                 struct iphdr *iph;
5790                 u32 tcp_opt_len, hdr_len;
5791
5792                 if (skb_header_cloned(skb) &&
5793                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5794                         dev_kfree_skb(skb);
5795                         goto out_unlock;
5796                 }
5797
5798                 iph = ip_hdr(skb);
5799                 tcp_opt_len = tcp_optlen(skb);
5800
5801                 if (skb_is_gso_v6(skb)) {
5802                         hdr_len = skb_headlen(skb) - ETH_HLEN;
5803                 } else {
5804                         u32 ip_tcp_len;
5805
5806                         ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5807                         hdr_len = ip_tcp_len + tcp_opt_len;
5808
5809                         iph->check = 0;
5810                         iph->tot_len = htons(mss + hdr_len);
5811                 }
5812
5813                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5814                              (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5815                         return tg3_tso_bug(tp, skb);
5816
5817                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5818                                TXD_FLAG_CPU_POST_DMA);
5819
5820                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5821                         tcp_hdr(skb)->check = 0;
5822                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5823                 } else
5824                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5825                                                                  iph->daddr, 0,
5826                                                                  IPPROTO_TCP,
5827                                                                  0);
5828
5829                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5830                         mss |= (hdr_len & 0xc) << 12;
5831                         if (hdr_len & 0x10)
5832                                 base_flags |= 0x00000010;
5833                         base_flags |= (hdr_len & 0x3e0) << 5;
5834                 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5835                         mss |= hdr_len << 9;
5836                 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5837                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5838                         if (tcp_opt_len || iph->ihl > 5) {
5839                                 int tsflags;
5840
5841                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5842                                 mss |= (tsflags << 11);
5843                         }
5844                 } else {
5845                         if (tcp_opt_len || iph->ihl > 5) {
5846                                 int tsflags;
5847
5848                                 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5849                                 base_flags |= tsflags << 12;
5850                         }
5851                 }
5852         }
5853 #if TG3_VLAN_TAG_USED
5854         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5855                 base_flags |= (TXD_FLAG_VLAN |
5856                                (vlan_tx_tag_get(skb) << 16));
5857 #endif
5858
5859         if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5860             !mss && skb->len > ETH_DATA_LEN)
5861                 base_flags |= TXD_FLAG_JMB_PKT;
5862
5863         len = skb_headlen(skb);
5864
5865         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5866         if (pci_dma_mapping_error(tp->pdev, mapping)) {
5867                 dev_kfree_skb(skb);
5868                 goto out_unlock;
5869         }
5870
5871         tnapi->tx_buffers[entry].skb = skb;
5872         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5873
5874         would_hit_hwbug = 0;
5875
5876         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5877                 would_hit_hwbug = 1;
5878
5879         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5880             tg3_4g_overflow_test(mapping, len))
5881                 would_hit_hwbug = 1;
5882
5883         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5884             tg3_40bit_overflow_test(tp, mapping, len))
5885                 would_hit_hwbug = 1;
5886
5887         if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5888                 would_hit_hwbug = 1;
5889
5890         tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5891                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5892
5893         entry = NEXT_TX(entry);
5894
5895         /* Now loop through additional data fragments, and queue them. */
5896         if (skb_shinfo(skb)->nr_frags > 0) {
5897                 last = skb_shinfo(skb)->nr_frags - 1;
5898                 for (i = 0; i <= last; i++) {
5899                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5900
5901                         len = frag->size;
5902                         mapping = pci_map_page(tp->pdev,
5903                                                frag->page,
5904                                                frag->page_offset,
5905                                                len, PCI_DMA_TODEVICE);
5906
5907                         tnapi->tx_buffers[entry].skb = NULL;
5908                         dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5909                                            mapping);
5910                         if (pci_dma_mapping_error(tp->pdev, mapping))
5911                                 goto dma_error;
5912
5913                         if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5914                             len <= 8)
5915                                 would_hit_hwbug = 1;
5916
5917                         if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5918                             tg3_4g_overflow_test(mapping, len))
5919                                 would_hit_hwbug = 1;
5920
5921                         if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5922                             tg3_40bit_overflow_test(tp, mapping, len))
5923                                 would_hit_hwbug = 1;
5924
5925                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5926                                 tg3_set_txd(tnapi, entry, mapping, len,
5927                                             base_flags, (i == last)|(mss << 1));
5928                         else
5929                                 tg3_set_txd(tnapi, entry, mapping, len,
5930                                             base_flags, (i == last));
5931
5932                         entry = NEXT_TX(entry);
5933                 }
5934         }
5935
5936         if (would_hit_hwbug) {
5937                 u32 last_plus_one = entry;
5938                 u32 start;
5939
5940                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5941                 start &= (TG3_TX_RING_SIZE - 1);
5942
5943                 /* If the workaround fails due to memory/mapping
5944                  * failure, silently drop this packet.
5945                  */
5946                 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5947                                                 &start, base_flags, mss))
5948                         goto out_unlock;
5949
5950                 entry = start;
5951         }
5952
5953         /* Packets are ready, update Tx producer idx local and on card. */
5954         tw32_tx_mbox(tnapi->prodmbox, entry);
5955
5956         tnapi->tx_prod = entry;
5957         if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5958                 netif_tx_stop_queue(txq);
5959
5960                 /* netif_tx_stop_queue() must be done before checking
5961                  * checking tx index in tg3_tx_avail() below, because in
5962                  * tg3_tx(), we update tx index before checking for
5963                  * netif_tx_queue_stopped().
5964                  */
5965                 smp_mb();
5966                 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5967                         netif_tx_wake_queue(txq);
5968         }
5969
5970 out_unlock:
5971         mmiowb();
5972
5973         return NETDEV_TX_OK;
5974
5975 dma_error:
5976         last = i;
5977         entry = tnapi->tx_prod;
5978         tnapi->tx_buffers[entry].skb = NULL;
5979         pci_unmap_single(tp->pdev,
5980                          dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5981                          skb_headlen(skb),
5982                          PCI_DMA_TODEVICE);
5983         for (i = 0; i <= last; i++) {
5984                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5985                 entry = NEXT_TX(entry);
5986
5987                 pci_unmap_page(tp->pdev,
5988                                dma_unmap_addr(&tnapi->tx_buffers[entry],
5989                                               mapping),
5990                                frag->size, PCI_DMA_TODEVICE);
5991         }
5992
5993         dev_kfree_skb(skb);
5994         return NETDEV_TX_OK;
5995 }
5996
5997 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5998                                int new_mtu)
5999 {
6000         dev->mtu = new_mtu;
6001
6002         if (new_mtu > ETH_DATA_LEN) {
6003                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6004                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
6005                         ethtool_op_set_tso(dev, 0);
6006                 } else {
6007                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
6008                 }
6009         } else {
6010                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6011                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
6012                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
6013         }
6014 }
6015
6016 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
6017 {
6018         struct tg3 *tp = netdev_priv(dev);
6019         int err;
6020
6021         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
6022                 return -EINVAL;
6023
6024         if (!netif_running(dev)) {
6025                 /* We'll just catch it later when the
6026                  * device is up'd.
6027                  */
6028                 tg3_set_mtu(dev, tp, new_mtu);
6029                 return 0;
6030         }
6031
6032         tg3_phy_stop(tp);
6033
6034         tg3_netif_stop(tp);
6035
6036         tg3_full_lock(tp, 1);
6037
6038         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6039
6040         tg3_set_mtu(dev, tp, new_mtu);
6041
6042         err = tg3_restart_hw(tp, 0);
6043
6044         if (!err)
6045                 tg3_netif_start(tp);
6046
6047         tg3_full_unlock(tp);
6048
6049         if (!err)
6050                 tg3_phy_start(tp);
6051
6052         return err;
6053 }
6054
6055 static void tg3_rx_prodring_free(struct tg3 *tp,
6056                                  struct tg3_rx_prodring_set *tpr)
6057 {
6058         int i;
6059
6060         if (tpr != &tp->napi[0].prodring) {
6061                 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
6062                      i = (i + 1) % TG3_RX_RING_SIZE)
6063                         tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6064                                         tp->rx_pkt_map_sz);
6065
6066                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6067                         for (i = tpr->rx_jmb_cons_idx;
6068                              i != tpr->rx_jmb_prod_idx;
6069                              i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
6070                                 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6071                                                 TG3_RX_JMB_MAP_SZ);
6072                         }
6073                 }
6074
6075                 return;
6076         }
6077
6078         for (i = 0; i < TG3_RX_RING_SIZE; i++)
6079                 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
6080                                 tp->rx_pkt_map_sz);
6081
6082         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6083                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
6084                         tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
6085                                         TG3_RX_JMB_MAP_SZ);
6086         }
6087 }
6088
6089 /* Initialize rx rings for packet processing.
6090  *
6091  * The chip has been shut down and the driver detached from
6092  * the networking, so no interrupts or new tx packets will
6093  * end up in the driver.  tp->{tx,}lock are held and thus
6094  * we may not sleep.
6095  */
6096 static int tg3_rx_prodring_alloc(struct tg3 *tp,
6097                                  struct tg3_rx_prodring_set *tpr)
6098 {
6099         u32 i, rx_pkt_dma_sz;
6100
6101         tpr->rx_std_cons_idx = 0;
6102         tpr->rx_std_prod_idx = 0;
6103         tpr->rx_jmb_cons_idx = 0;
6104         tpr->rx_jmb_prod_idx = 0;
6105
6106         if (tpr != &tp->napi[0].prodring) {
6107                 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
6108                 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
6109                         memset(&tpr->rx_jmb_buffers[0], 0,
6110                                TG3_RX_JMB_BUFF_RING_SIZE);
6111                 goto done;
6112         }
6113
6114         /* Zero out all descriptors. */
6115         memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
6116
6117         rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
6118         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
6119             tp->dev->mtu > ETH_DATA_LEN)
6120                 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
6121         tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
6122
6123         /* Initialize invariants of the rings, we only set this
6124          * stuff once.  This works because the card does not
6125          * write into the rx buffer posting rings.
6126          */
6127         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
6128                 struct tg3_rx_buffer_desc *rxd;
6129
6130                 rxd = &tpr->rx_std[i];
6131                 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6132                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6133                 rxd->opaque = (RXD_OPAQUE_RING_STD |
6134                                (i << RXD_OPAQUE_INDEX_SHIFT));
6135         }
6136
6137         /* Now allocate fresh SKBs for each rx ring. */
6138         for (i = 0; i < tp->rx_pending; i++) {
6139                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6140                         netdev_warn(tp->dev,
6141                                     "Using a smaller RX standard ring. Only "
6142                                     "%d out of %d buffers were allocated "
6143                                     "successfully\n", i, tp->rx_pending);
6144                         if (i == 0)
6145                                 goto initfail;
6146                         tp->rx_pending = i;
6147                         break;
6148                 }
6149         }
6150
6151         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6152                 goto done;
6153
6154         memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6155
6156         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE))
6157                 goto done;
6158
6159         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6160                 struct tg3_rx_buffer_desc *rxd;
6161
6162                 rxd = &tpr->rx_jmb[i].std;
6163                 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6164                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6165                                   RXD_FLAG_JUMBO;
6166                 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6167                        (i << RXD_OPAQUE_INDEX_SHIFT));
6168         }
6169
6170         for (i = 0; i < tp->rx_jumbo_pending; i++) {
6171                 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO, i) < 0) {
6172                         netdev_warn(tp->dev,
6173                                     "Using a smaller RX jumbo ring. Only %d "
6174                                     "out of %d buffers were allocated "
6175                                     "successfully\n", i, tp->rx_jumbo_pending);
6176                         if (i == 0)
6177                                 goto initfail;
6178                         tp->rx_jumbo_pending = i;
6179                         break;
6180                 }
6181         }
6182
6183 done:
6184         return 0;
6185
6186 initfail:
6187         tg3_rx_prodring_free(tp, tpr);
6188         return -ENOMEM;
6189 }
6190
6191 static void tg3_rx_prodring_fini(struct tg3 *tp,
6192                                  struct tg3_rx_prodring_set *tpr)
6193 {
6194         kfree(tpr->rx_std_buffers);
6195         tpr->rx_std_buffers = NULL;
6196         kfree(tpr->rx_jmb_buffers);
6197         tpr->rx_jmb_buffers = NULL;
6198         if (tpr->rx_std) {
6199                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6200                                     tpr->rx_std, tpr->rx_std_mapping);
6201                 tpr->rx_std = NULL;
6202         }
6203         if (tpr->rx_jmb) {
6204                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6205                                     tpr->rx_jmb, tpr->rx_jmb_mapping);
6206                 tpr->rx_jmb = NULL;
6207         }
6208 }
6209
6210 static int tg3_rx_prodring_init(struct tg3 *tp,
6211                                 struct tg3_rx_prodring_set *tpr)
6212 {
6213         tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6214         if (!tpr->rx_std_buffers)
6215                 return -ENOMEM;
6216
6217         tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6218                                            &tpr->rx_std_mapping);
6219         if (!tpr->rx_std)
6220                 goto err_out;
6221
6222         if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6223                 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6224                                               GFP_KERNEL);
6225                 if (!tpr->rx_jmb_buffers)
6226                         goto err_out;
6227
6228                 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6229                                                    TG3_RX_JUMBO_RING_BYTES,
6230                                                    &tpr->rx_jmb_mapping);
6231                 if (!tpr->rx_jmb)
6232                         goto err_out;
6233         }
6234
6235         return 0;
6236
6237 err_out:
6238         tg3_rx_prodring_fini(tp, tpr);
6239         return -ENOMEM;
6240 }
6241
6242 /* Free up pending packets in all rx/tx rings.
6243  *
6244  * The chip has been shut down and the driver detached from
6245  * the networking, so no interrupts or new tx packets will
6246  * end up in the driver.  tp->{tx,}lock is not held and we are not
6247  * in an interrupt context and thus may sleep.
6248  */
6249 static void tg3_free_rings(struct tg3 *tp)
6250 {
6251         int i, j;
6252
6253         for (j = 0; j < tp->irq_cnt; j++) {
6254                 struct tg3_napi *tnapi = &tp->napi[j];
6255
6256                 tg3_rx_prodring_free(tp, &tnapi->prodring);
6257
6258                 if (!tnapi->tx_buffers)
6259                         continue;
6260
6261                 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6262                         struct ring_info *txp;
6263                         struct sk_buff *skb;
6264                         unsigned int k;
6265
6266                         txp = &tnapi->tx_buffers[i];
6267                         skb = txp->skb;
6268
6269                         if (skb == NULL) {
6270                                 i++;
6271                                 continue;
6272                         }
6273
6274                         pci_unmap_single(tp->pdev,
6275                                          dma_unmap_addr(txp, mapping),
6276                                          skb_headlen(skb),
6277                                          PCI_DMA_TODEVICE);
6278                         txp->skb = NULL;
6279
6280                         i++;
6281
6282                         for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6283                                 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6284                                 pci_unmap_page(tp->pdev,
6285                                                dma_unmap_addr(txp, mapping),
6286                                                skb_shinfo(skb)->frags[k].size,
6287                                                PCI_DMA_TODEVICE);
6288                                 i++;
6289                         }
6290
6291                         dev_kfree_skb_any(skb);
6292                 }
6293         }
6294 }
6295
6296 /* Initialize tx/rx rings for packet processing.
6297  *
6298  * The chip has been shut down and the driver detached from
6299  * the networking, so no interrupts or new tx packets will
6300  * end up in the driver.  tp->{tx,}lock are held and thus
6301  * we may not sleep.
6302  */
6303 static int tg3_init_rings(struct tg3 *tp)
6304 {
6305         int i;
6306
6307         /* Free up all the SKBs. */
6308         tg3_free_rings(tp);
6309
6310         for (i = 0; i < tp->irq_cnt; i++) {
6311                 struct tg3_napi *tnapi = &tp->napi[i];
6312
6313                 tnapi->last_tag = 0;
6314                 tnapi->last_irq_tag = 0;
6315                 tnapi->hw_status->status = 0;
6316                 tnapi->hw_status->status_tag = 0;
6317                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6318
6319                 tnapi->tx_prod = 0;
6320                 tnapi->tx_cons = 0;
6321                 if (tnapi->tx_ring)
6322                         memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6323
6324                 tnapi->rx_rcb_ptr = 0;
6325                 if (tnapi->rx_rcb)
6326                         memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6327
6328                 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
6329                         tg3_free_rings(tp);
6330                         return -ENOMEM;
6331                 }
6332         }
6333
6334         return 0;
6335 }
6336
6337 /*
6338  * Must not be invoked with interrupt sources disabled and
6339  * the hardware shutdown down.
6340  */
6341 static void tg3_free_consistent(struct tg3 *tp)
6342 {
6343         int i;
6344
6345         for (i = 0; i < tp->irq_cnt; i++) {
6346                 struct tg3_napi *tnapi = &tp->napi[i];
6347
6348                 if (tnapi->tx_ring) {
6349                         pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6350                                 tnapi->tx_ring, tnapi->tx_desc_mapping);
6351                         tnapi->tx_ring = NULL;
6352                 }
6353
6354                 kfree(tnapi->tx_buffers);
6355                 tnapi->tx_buffers = NULL;
6356
6357                 if (tnapi->rx_rcb) {
6358                         pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6359                                             tnapi->rx_rcb,
6360                                             tnapi->rx_rcb_mapping);
6361                         tnapi->rx_rcb = NULL;
6362                 }
6363
6364                 tg3_rx_prodring_fini(tp, &tnapi->prodring);
6365
6366                 if (tnapi->hw_status) {
6367                         pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6368                                             tnapi->hw_status,
6369                                             tnapi->status_mapping);
6370                         tnapi->hw_status = NULL;
6371                 }
6372         }
6373
6374         if (tp->hw_stats) {
6375                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6376                                     tp->hw_stats, tp->stats_mapping);
6377                 tp->hw_stats = NULL;
6378         }
6379 }
6380
6381 /*
6382  * Must not be invoked with interrupt sources disabled and
6383  * the hardware shutdown down.  Can sleep.
6384  */
6385 static int tg3_alloc_consistent(struct tg3 *tp)
6386 {
6387         int i;
6388
6389         tp->hw_stats = pci_alloc_consistent(tp->pdev,
6390                                             sizeof(struct tg3_hw_stats),
6391                                             &tp->stats_mapping);
6392         if (!tp->hw_stats)
6393                 goto err_out;
6394
6395         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6396
6397         for (i = 0; i < tp->irq_cnt; i++) {
6398                 struct tg3_napi *tnapi = &tp->napi[i];
6399                 struct tg3_hw_status *sblk;
6400
6401                 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6402                                                         TG3_HW_STATUS_SIZE,
6403                                                         &tnapi->status_mapping);
6404                 if (!tnapi->hw_status)
6405                         goto err_out;
6406
6407                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6408                 sblk = tnapi->hw_status;
6409
6410                 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
6411                         goto err_out;
6412
6413                 /* If multivector TSS is enabled, vector 0 does not handle
6414                  * tx interrupts.  Don't allocate any resources for it.
6415                  */
6416                 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6417                     (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6418                         tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6419                                                     TG3_TX_RING_SIZE,
6420                                                     GFP_KERNEL);
6421                         if (!tnapi->tx_buffers)
6422                                 goto err_out;
6423
6424                         tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6425                                                               TG3_TX_RING_BYTES,
6426                                                        &tnapi->tx_desc_mapping);
6427                         if (!tnapi->tx_ring)
6428                                 goto err_out;
6429                 }
6430
6431                 /*
6432                  * When RSS is enabled, the status block format changes
6433                  * slightly.  The "rx_jumbo_consumer", "reserved",
6434                  * and "rx_mini_consumer" members get mapped to the
6435                  * other three rx return ring producer indexes.
6436                  */
6437                 switch (i) {
6438                 default:
6439                         tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6440                         break;
6441                 case 2:
6442                         tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6443                         break;
6444                 case 3:
6445                         tnapi->rx_rcb_prod_idx = &sblk->reserved;
6446                         break;
6447                 case 4:
6448                         tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6449                         break;
6450                 }
6451
6452                 /*
6453                  * If multivector RSS is enabled, vector 0 does not handle
6454                  * rx or tx interrupts.  Don't allocate any resources for it.
6455                  */
6456                 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6457                         continue;
6458
6459                 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6460                                                      TG3_RX_RCB_RING_BYTES(tp),
6461                                                      &tnapi->rx_rcb_mapping);
6462                 if (!tnapi->rx_rcb)
6463                         goto err_out;
6464
6465                 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6466         }
6467
6468         return 0;
6469
6470 err_out:
6471         tg3_free_consistent(tp);
6472         return -ENOMEM;
6473 }
6474
6475 #define MAX_WAIT_CNT 1000
6476
6477 /* To stop a block, clear the enable bit and poll till it
6478  * clears.  tp->lock is held.
6479  */
6480 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6481 {
6482         unsigned int i;
6483         u32 val;
6484
6485         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6486                 switch (ofs) {
6487                 case RCVLSC_MODE:
6488                 case DMAC_MODE:
6489                 case MBFREE_MODE:
6490                 case BUFMGR_MODE:
6491                 case MEMARB_MODE:
6492                         /* We can't enable/disable these bits of the
6493                          * 5705/5750, just say success.
6494                          */
6495                         return 0;
6496
6497                 default:
6498                         break;
6499                 }
6500         }
6501
6502         val = tr32(ofs);
6503         val &= ~enable_bit;
6504         tw32_f(ofs, val);
6505
6506         for (i = 0; i < MAX_WAIT_CNT; i++) {
6507                 udelay(100);
6508                 val = tr32(ofs);
6509                 if ((val & enable_bit) == 0)
6510                         break;
6511         }
6512
6513         if (i == MAX_WAIT_CNT && !silent) {
6514                 dev_err(&tp->pdev->dev,
6515                         "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
6516                         ofs, enable_bit);
6517                 return -ENODEV;
6518         }
6519
6520         return 0;
6521 }
6522
6523 /* tp->lock is held. */
6524 static int tg3_abort_hw(struct tg3 *tp, int silent)
6525 {
6526         int i, err;
6527
6528         tg3_disable_ints(tp);
6529
6530         tp->rx_mode &= ~RX_MODE_ENABLE;
6531         tw32_f(MAC_RX_MODE, tp->rx_mode);
6532         udelay(10);
6533
6534         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6535         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6536         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6537         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6538         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6539         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6540
6541         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6542         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6543         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6544         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6545         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6546         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6547         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6548
6549         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6550         tw32_f(MAC_MODE, tp->mac_mode);
6551         udelay(40);
6552
6553         tp->tx_mode &= ~TX_MODE_ENABLE;
6554         tw32_f(MAC_TX_MODE, tp->tx_mode);
6555
6556         for (i = 0; i < MAX_WAIT_CNT; i++) {
6557                 udelay(100);
6558                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6559                         break;
6560         }
6561         if (i >= MAX_WAIT_CNT) {
6562                 dev_err(&tp->pdev->dev,
6563                         "%s timed out, TX_MODE_ENABLE will not clear "
6564                         "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
6565                 err |= -ENODEV;
6566         }
6567
6568         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6569         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6570         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6571
6572         tw32(FTQ_RESET, 0xffffffff);
6573         tw32(FTQ_RESET, 0x00000000);
6574
6575         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6576         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6577
6578         for (i = 0; i < tp->irq_cnt; i++) {
6579                 struct tg3_napi *tnapi = &tp->napi[i];
6580                 if (tnapi->hw_status)
6581                         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6582         }
6583         if (tp->hw_stats)
6584                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6585
6586         return err;
6587 }
6588
6589 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6590 {
6591         int i;
6592         u32 apedata;
6593
6594         /* NCSI does not support APE events */
6595         if (tp->tg3_flags3 & TG3_FLG3_APE_HAS_NCSI)
6596                 return;
6597
6598         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6599         if (apedata != APE_SEG_SIG_MAGIC)
6600                 return;
6601
6602         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6603         if (!(apedata & APE_FW_STATUS_READY))
6604                 return;
6605
6606         /* Wait for up to 1 millisecond for APE to service previous event. */
6607         for (i = 0; i < 10; i++) {
6608                 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6609                         return;
6610
6611                 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6612
6613                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6614                         tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6615                                         event | APE_EVENT_STATUS_EVENT_PENDING);
6616
6617                 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6618
6619                 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6620                         break;
6621
6622                 udelay(100);
6623         }
6624
6625         if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6626                 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6627 }
6628
6629 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6630 {
6631         u32 event;
6632         u32 apedata;
6633
6634         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6635                 return;
6636
6637         switch (kind) {
6638         case RESET_KIND_INIT:
6639                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6640                                 APE_HOST_SEG_SIG_MAGIC);
6641                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6642                                 APE_HOST_SEG_LEN_MAGIC);
6643                 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6644                 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6645                 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6646                         APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
6647                 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6648                                 APE_HOST_BEHAV_NO_PHYLOCK);
6649                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
6650                                     TG3_APE_HOST_DRVR_STATE_START);
6651
6652                 event = APE_EVENT_STATUS_STATE_START;
6653                 break;
6654         case RESET_KIND_SHUTDOWN:
6655                 /* With the interface we are currently using,
6656                  * APE does not track driver state.  Wiping
6657                  * out the HOST SEGMENT SIGNATURE forces
6658                  * the APE to assume OS absent status.
6659                  */
6660                 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6661
6662                 if (device_may_wakeup(&tp->pdev->dev) &&
6663                     (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)) {
6664                         tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
6665                                             TG3_APE_HOST_WOL_SPEED_AUTO);
6666                         apedata = TG3_APE_HOST_DRVR_STATE_WOL;
6667                 } else
6668                         apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
6669
6670                 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
6671
6672                 event = APE_EVENT_STATUS_STATE_UNLOAD;
6673                 break;
6674         case RESET_KIND_SUSPEND:
6675                 event = APE_EVENT_STATUS_STATE_SUSPEND;
6676                 break;
6677         default:
6678                 return;
6679         }
6680
6681         event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6682
6683         tg3_ape_send_event(tp, event);
6684 }
6685
6686 /* tp->lock is held. */
6687 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6688 {
6689         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6690                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6691
6692         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6693                 switch (kind) {
6694                 case RESET_KIND_INIT:
6695                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6696                                       DRV_STATE_START);
6697                         break;
6698
6699                 case RESET_KIND_SHUTDOWN:
6700                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6701                                       DRV_STATE_UNLOAD);
6702                         break;
6703
6704                 case RESET_KIND_SUSPEND:
6705                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6706                                       DRV_STATE_SUSPEND);
6707                         break;
6708
6709                 default:
6710                         break;
6711                 }
6712         }
6713
6714         if (kind == RESET_KIND_INIT ||
6715             kind == RESET_KIND_SUSPEND)
6716                 tg3_ape_driver_state_change(tp, kind);
6717 }
6718
6719 /* tp->lock is held. */
6720 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6721 {
6722         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6723                 switch (kind) {
6724                 case RESET_KIND_INIT:
6725                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6726                                       DRV_STATE_START_DONE);
6727                         break;
6728
6729                 case RESET_KIND_SHUTDOWN:
6730                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6731                                       DRV_STATE_UNLOAD_DONE);
6732                         break;
6733
6734                 default:
6735                         break;
6736                 }
6737         }
6738
6739         if (kind == RESET_KIND_SHUTDOWN)
6740                 tg3_ape_driver_state_change(tp, kind);
6741 }
6742
6743 /* tp->lock is held. */
6744 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6745 {
6746         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6747                 switch (kind) {
6748                 case RESET_KIND_INIT:
6749                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6750                                       DRV_STATE_START);
6751                         break;
6752
6753                 case RESET_KIND_SHUTDOWN:
6754                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6755                                       DRV_STATE_UNLOAD);
6756                         break;
6757
6758                 case RESET_KIND_SUSPEND:
6759                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6760                                       DRV_STATE_SUSPEND);
6761                         break;
6762
6763                 default:
6764                         break;
6765                 }
6766         }
6767 }
6768
6769 static int tg3_poll_fw(struct tg3 *tp)
6770 {
6771         int i;
6772         u32 val;
6773
6774         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6775                 /* Wait up to 20ms for init done. */
6776                 for (i = 0; i < 200; i++) {
6777                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6778                                 return 0;
6779                         udelay(100);
6780                 }
6781                 return -ENODEV;
6782         }
6783
6784         /* Wait for firmware initialization to complete. */
6785         for (i = 0; i < 100000; i++) {
6786                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6787                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6788                         break;
6789                 udelay(10);
6790         }
6791
6792         /* Chip might not be fitted with firmware.  Some Sun onboard
6793          * parts are configured like that.  So don't signal the timeout
6794          * of the above loop as an error, but do report the lack of
6795          * running firmware once.
6796          */
6797         if (i >= 100000 &&
6798             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6799                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6800
6801                 netdev_info(tp->dev, "No firmware running\n");
6802         }
6803
6804         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
6805                 /* The 57765 A0 needs a little more
6806                  * time to do some important work.
6807                  */
6808                 mdelay(10);
6809         }
6810
6811         return 0;
6812 }
6813
6814 /* Save PCI command register before chip reset */
6815 static void tg3_save_pci_state(struct tg3 *tp)
6816 {
6817         pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6818 }
6819
6820 /* Restore PCI state after chip reset */
6821 static void tg3_restore_pci_state(struct tg3 *tp)
6822 {
6823         u32 val;
6824
6825         /* Re-enable indirect register accesses. */
6826         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6827                                tp->misc_host_ctrl);
6828
6829         /* Set MAX PCI retry to zero. */
6830         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6831         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6832             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6833                 val |= PCISTATE_RETRY_SAME_DMA;
6834         /* Allow reads and writes to the APE register and memory space. */
6835         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6836                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6837                        PCISTATE_ALLOW_APE_SHMEM_WR |
6838                        PCISTATE_ALLOW_APE_PSPACE_WR;
6839         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6840
6841         pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6842
6843         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6844                 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6845                         pcie_set_readrq(tp->pdev, 4096);
6846                 else {
6847                         pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6848                                               tp->pci_cacheline_sz);
6849                         pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6850                                               tp->pci_lat_timer);
6851                 }
6852         }
6853
6854         /* Make sure PCI-X relaxed ordering bit is clear. */
6855         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6856                 u16 pcix_cmd;
6857
6858                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6859                                      &pcix_cmd);
6860                 pcix_cmd &= ~PCI_X_CMD_ERO;
6861                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6862                                       pcix_cmd);
6863         }
6864
6865         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6866
6867                 /* Chip reset on 5780 will reset MSI enable bit,
6868                  * so need to restore it.
6869                  */
6870                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6871                         u16 ctrl;
6872
6873                         pci_read_config_word(tp->pdev,
6874                                              tp->msi_cap + PCI_MSI_FLAGS,
6875                                              &ctrl);
6876                         pci_write_config_word(tp->pdev,
6877                                               tp->msi_cap + PCI_MSI_FLAGS,
6878                                               ctrl | PCI_MSI_FLAGS_ENABLE);
6879                         val = tr32(MSGINT_MODE);
6880                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6881                 }
6882         }
6883 }
6884
6885 static void tg3_stop_fw(struct tg3 *);
6886
6887 /* tp->lock is held. */
6888 static int tg3_chip_reset(struct tg3 *tp)
6889 {
6890         u32 val;
6891         void (*write_op)(struct tg3 *, u32, u32);
6892         int i, err;
6893
6894         tg3_nvram_lock(tp);
6895
6896         tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6897
6898         /* No matching tg3_nvram_unlock() after this because
6899          * chip reset below will undo the nvram lock.
6900          */
6901         tp->nvram_lock_cnt = 0;
6902
6903         /* GRC_MISC_CFG core clock reset will clear the memory
6904          * enable bit in PCI register 4 and the MSI enable bit
6905          * on some chips, so we save relevant registers here.
6906          */
6907         tg3_save_pci_state(tp);
6908
6909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6910             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6911                 tw32(GRC_FASTBOOT_PC, 0);
6912
6913         /*
6914          * We must avoid the readl() that normally takes place.
6915          * It locks machines, causes machine checks, and other
6916          * fun things.  So, temporarily disable the 5701
6917          * hardware workaround, while we do the reset.
6918          */
6919         write_op = tp->write32;
6920         if (write_op == tg3_write_flush_reg32)
6921                 tp->write32 = tg3_write32;
6922
6923         /* Prevent the irq handler from reading or writing PCI registers
6924          * during chip reset when the memory enable bit in the PCI command
6925          * register may be cleared.  The chip does not generate interrupt
6926          * at this time, but the irq handler may still be called due to irq
6927          * sharing or irqpoll.
6928          */
6929         tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6930         for (i = 0; i < tp->irq_cnt; i++) {
6931                 struct tg3_napi *tnapi = &tp->napi[i];
6932                 if (tnapi->hw_status) {
6933                         tnapi->hw_status->status = 0;
6934                         tnapi->hw_status->status_tag = 0;
6935                 }
6936                 tnapi->last_tag = 0;
6937                 tnapi->last_irq_tag = 0;
6938         }
6939         smp_mb();
6940
6941         for (i = 0; i < tp->irq_cnt; i++)
6942                 synchronize_irq(tp->napi[i].irq_vec);
6943
6944         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6945                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6946                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6947         }
6948
6949         /* do the reset */
6950         val = GRC_MISC_CFG_CORECLK_RESET;
6951
6952         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6953                 /* Force PCIe 1.0a mode */
6954                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6955                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
6956                     tr32(TG3_PCIE_PHY_TSTCTL) ==
6957                     (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
6958                         tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
6959
6960                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6961                         tw32(GRC_MISC_CFG, (1 << 29));
6962                         val |= (1 << 29);
6963                 }
6964         }
6965
6966         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6967                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6968                 tw32(GRC_VCPU_EXT_CTRL,
6969                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6970         }
6971
6972         /* Manage gphy power for all CPMU absent PCIe devices. */
6973         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6974             !(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
6975                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6976
6977         tw32(GRC_MISC_CFG, val);
6978
6979         /* restore 5701 hardware bug workaround write method */
6980         tp->write32 = write_op;
6981
6982         /* Unfortunately, we have to delay before the PCI read back.
6983          * Some 575X chips even will not respond to a PCI cfg access
6984          * when the reset command is given to the chip.
6985          *
6986          * How do these hardware designers expect things to work
6987          * properly if the PCI write is posted for a long period
6988          * of time?  It is always necessary to have some method by
6989          * which a register read back can occur to push the write
6990          * out which does the reset.
6991          *
6992          * For most tg3 variants the trick below was working.
6993          * Ho hum...
6994          */
6995         udelay(120);
6996
6997         /* Flush PCI posted writes.  The normal MMIO registers
6998          * are inaccessible at this time so this is the only
6999          * way to make this reliably (actually, this is no longer
7000          * the case, see above).  I tried to use indirect
7001          * register read/write but this upset some 5701 variants.
7002          */
7003         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
7004
7005         udelay(120);
7006
7007         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
7008                 u16 val16;
7009
7010                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
7011                         int i;
7012                         u32 cfg_val;
7013
7014                         /* Wait for link training to complete.  */
7015                         for (i = 0; i < 5000; i++)
7016                                 udelay(100);
7017
7018                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
7019                         pci_write_config_dword(tp->pdev, 0xc4,
7020                                                cfg_val | (1 << 15));
7021                 }
7022
7023                 /* Clear the "no snoop" and "relaxed ordering" bits. */
7024                 pci_read_config_word(tp->pdev,
7025                                      tp->pcie_cap + PCI_EXP_DEVCTL,
7026                                      &val16);
7027                 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
7028                            PCI_EXP_DEVCTL_NOSNOOP_EN);
7029                 /*
7030                  * Older PCIe devices only support the 128 byte
7031                  * MPS setting.  Enforce the restriction.
7032                  */
7033                 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
7034                         val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
7035                 pci_write_config_word(tp->pdev,
7036                                       tp->pcie_cap + PCI_EXP_DEVCTL,
7037                                       val16);
7038
7039                 pcie_set_readrq(tp->pdev, 4096);
7040
7041                 /* Clear error status */
7042                 pci_write_config_word(tp->pdev,
7043                                       tp->pcie_cap + PCI_EXP_DEVSTA,
7044                                       PCI_EXP_DEVSTA_CED |
7045                                       PCI_EXP_DEVSTA_NFED |
7046                                       PCI_EXP_DEVSTA_FED |
7047                                       PCI_EXP_DEVSTA_URD);
7048         }
7049
7050         tg3_restore_pci_state(tp);
7051
7052         tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
7053
7054         val = 0;
7055         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
7056                 val = tr32(MEMARB_MODE);
7057         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
7058
7059         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
7060                 tg3_stop_fw(tp);
7061                 tw32(0x5000, 0x400);
7062         }
7063
7064         tw32(GRC_MODE, tp->grc_mode);
7065
7066         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
7067                 val = tr32(0xc4);
7068
7069                 tw32(0xc4, val | (1 << 15));
7070         }
7071
7072         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
7073             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7074                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
7075                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
7076                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
7077                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7078         }
7079
7080         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
7081                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
7082                 tw32_f(MAC_MODE, tp->mac_mode);
7083         } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
7084                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
7085                 tw32_f(MAC_MODE, tp->mac_mode);
7086         } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7087                 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
7088                 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
7089                         tp->mac_mode |= MAC_MODE_TDE_ENABLE;
7090                 tw32_f(MAC_MODE, tp->mac_mode);
7091         } else
7092                 tw32_f(MAC_MODE, 0);
7093         udelay(40);
7094
7095         tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
7096
7097         err = tg3_poll_fw(tp);
7098         if (err)
7099                 return err;
7100
7101         tg3_mdio_start(tp);
7102
7103         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
7104             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
7105             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
7106             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
7107                 val = tr32(0x7c00);
7108
7109                 tw32(0x7c00, val | (1 << 25));
7110         }
7111
7112         /* Reprobe ASF enable state.  */
7113         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
7114         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
7115         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
7116         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
7117                 u32 nic_cfg;
7118
7119                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
7120                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7121                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7122                         tp->last_event_jiffies = jiffies;
7123                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7124                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7125                 }
7126         }
7127
7128         return 0;
7129 }
7130
7131 /* tp->lock is held. */
7132 static void tg3_stop_fw(struct tg3 *tp)
7133 {
7134         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7135            !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7136                 /* Wait for RX cpu to ACK the previous event. */
7137                 tg3_wait_for_event_ack(tp);
7138
7139                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7140
7141                 tg3_generate_fw_event(tp);
7142
7143                 /* Wait for RX cpu to ACK this event. */
7144                 tg3_wait_for_event_ack(tp);
7145         }
7146 }
7147
7148 /* tp->lock is held. */
7149 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7150 {
7151         int err;
7152
7153         tg3_stop_fw(tp);
7154
7155         tg3_write_sig_pre_reset(tp, kind);
7156
7157         tg3_abort_hw(tp, silent);
7158         err = tg3_chip_reset(tp);
7159
7160         __tg3_set_mac_addr(tp, 0);
7161
7162         tg3_write_sig_legacy(tp, kind);
7163         tg3_write_sig_post_reset(tp, kind);
7164
7165         if (err)
7166                 return err;
7167
7168         return 0;
7169 }
7170
7171 #define RX_CPU_SCRATCH_BASE     0x30000
7172 #define RX_CPU_SCRATCH_SIZE     0x04000
7173 #define TX_CPU_SCRATCH_BASE     0x34000
7174 #define TX_CPU_SCRATCH_SIZE     0x04000
7175
7176 /* tp->lock is held. */
7177 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7178 {
7179         int i;
7180
7181         BUG_ON(offset == TX_CPU_BASE &&
7182             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7183
7184         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7185                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7186
7187                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7188                 return 0;
7189         }
7190         if (offset == RX_CPU_BASE) {
7191                 for (i = 0; i < 10000; i++) {
7192                         tw32(offset + CPU_STATE, 0xffffffff);
7193                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7194                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7195                                 break;
7196                 }
7197
7198                 tw32(offset + CPU_STATE, 0xffffffff);
7199                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
7200                 udelay(10);
7201         } else {
7202                 for (i = 0; i < 10000; i++) {
7203                         tw32(offset + CPU_STATE, 0xffffffff);
7204                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
7205                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7206                                 break;
7207                 }
7208         }
7209
7210         if (i >= 10000) {
7211                 netdev_err(tp->dev, "%s timed out, %s CPU\n",
7212                            __func__, offset == RX_CPU_BASE ? "RX" : "TX");
7213                 return -ENODEV;
7214         }
7215
7216         /* Clear firmware's nvram arbitration. */
7217         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7218                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7219         return 0;
7220 }
7221
7222 struct fw_info {
7223         unsigned int fw_base;
7224         unsigned int fw_len;
7225         const __be32 *fw_data;
7226 };
7227
7228 /* tp->lock is held. */
7229 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7230                                  int cpu_scratch_size, struct fw_info *info)
7231 {
7232         int err, lock_err, i;
7233         void (*write_op)(struct tg3 *, u32, u32);
7234
7235         if (cpu_base == TX_CPU_BASE &&
7236             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7237                 netdev_err(tp->dev,
7238                            "%s: Trying to load TX cpu firmware which is 5705\n",
7239                            __func__);
7240                 return -EINVAL;
7241         }
7242
7243         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7244                 write_op = tg3_write_mem;
7245         else
7246                 write_op = tg3_write_indirect_reg32;
7247
7248         /* It is possible that bootcode is still loading at this point.
7249          * Get the nvram lock first before halting the cpu.
7250          */
7251         lock_err = tg3_nvram_lock(tp);
7252         err = tg3_halt_cpu(tp, cpu_base);
7253         if (!lock_err)
7254                 tg3_nvram_unlock(tp);
7255         if (err)
7256                 goto out;
7257
7258         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7259                 write_op(tp, cpu_scratch_base + i, 0);
7260         tw32(cpu_base + CPU_STATE, 0xffffffff);
7261         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7262         for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7263                 write_op(tp, (cpu_scratch_base +
7264                               (info->fw_base & 0xffff) +
7265                               (i * sizeof(u32))),
7266                               be32_to_cpu(info->fw_data[i]));
7267
7268         err = 0;
7269
7270 out:
7271         return err;
7272 }
7273
7274 /* tp->lock is held. */
7275 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7276 {
7277         struct fw_info info;
7278         const __be32 *fw_data;
7279         int err, i;
7280
7281         fw_data = (void *)tp->fw->data;
7282
7283         /* Firmware blob starts with version numbers, followed by
7284            start address and length. We are setting complete length.
7285            length = end_address_of_bss - start_address_of_text.
7286            Remainder is the blob to be loaded contiguously
7287            from start address. */
7288
7289         info.fw_base = be32_to_cpu(fw_data[1]);
7290         info.fw_len = tp->fw->size - 12;
7291         info.fw_data = &fw_data[3];
7292
7293         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7294                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7295                                     &info);
7296         if (err)
7297                 return err;
7298
7299         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7300                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7301                                     &info);
7302         if (err)
7303                 return err;
7304
7305         /* Now startup only the RX cpu. */
7306         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7307         tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7308
7309         for (i = 0; i < 5; i++) {
7310                 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7311                         break;
7312                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7313                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
7314                 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7315                 udelay(1000);
7316         }
7317         if (i >= 5) {
7318                 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
7319                            "should be %08x\n", __func__,
7320                            tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
7321                 return -ENODEV;
7322         }
7323         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7324         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
7325
7326         return 0;
7327 }
7328
7329 /* 5705 needs a special version of the TSO firmware.  */
7330
7331 /* tp->lock is held. */
7332 static int tg3_load_tso_firmware(struct tg3 *tp)
7333 {
7334         struct fw_info info;
7335         const __be32 *fw_data;
7336         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7337         int err, i;
7338
7339         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7340                 return 0;
7341
7342         fw_data = (void *)tp->fw->data;
7343
7344         /* Firmware blob starts with version numbers, followed by
7345            start address and length. We are setting complete length.
7346            length = end_address_of_bss - start_address_of_text.
7347            Remainder is the blob to be loaded contiguously
7348            from start address. */
7349
7350         info.fw_base = be32_to_cpu(fw_data[1]);
7351         cpu_scratch_size = tp->fw_len;
7352         info.fw_len = tp->fw->size - 12;
7353         info.fw_data = &fw_data[3];
7354
7355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7356                 cpu_base = RX_CPU_BASE;
7357                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7358         } else {
7359                 cpu_base = TX_CPU_BASE;
7360                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7361                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7362         }
7363
7364         err = tg3_load_firmware_cpu(tp, cpu_base,
7365                                     cpu_scratch_base, cpu_scratch_size,
7366                                     &info);
7367         if (err)
7368                 return err;
7369
7370         /* Now startup the cpu. */
7371         tw32(cpu_base + CPU_STATE, 0xffffffff);
7372         tw32_f(cpu_base + CPU_PC, info.fw_base);
7373
7374         for (i = 0; i < 5; i++) {
7375                 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7376                         break;
7377                 tw32(cpu_base + CPU_STATE, 0xffffffff);
7378                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
7379                 tw32_f(cpu_base + CPU_PC, info.fw_base);
7380                 udelay(1000);
7381         }
7382         if (i >= 5) {
7383                 netdev_err(tp->dev,
7384                            "%s fails to set CPU PC, is %08x should be %08x\n",
7385                            __func__, tr32(cpu_base + CPU_PC), info.fw_base);
7386                 return -ENODEV;
7387         }
7388         tw32(cpu_base + CPU_STATE, 0xffffffff);
7389         tw32_f(cpu_base + CPU_MODE,  0x00000000);
7390         return 0;
7391 }
7392
7393
7394 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7395 {
7396         struct tg3 *tp = netdev_priv(dev);
7397         struct sockaddr *addr = p;
7398         int err = 0, skip_mac_1 = 0;
7399
7400         if (!is_valid_ether_addr(addr->sa_data))
7401                 return -EINVAL;
7402
7403         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7404
7405         if (!netif_running(dev))
7406                 return 0;
7407
7408         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7409                 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7410
7411                 addr0_high = tr32(MAC_ADDR_0_HIGH);
7412                 addr0_low = tr32(MAC_ADDR_0_LOW);
7413                 addr1_high = tr32(MAC_ADDR_1_HIGH);
7414                 addr1_low = tr32(MAC_ADDR_1_LOW);
7415
7416                 /* Skip MAC addr 1 if ASF is using it. */
7417                 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7418                     !(addr1_high == 0 && addr1_low == 0))
7419                         skip_mac_1 = 1;
7420         }
7421         spin_lock_bh(&tp->lock);
7422         __tg3_set_mac_addr(tp, skip_mac_1);
7423         spin_unlock_bh(&tp->lock);
7424
7425         return err;
7426 }
7427
7428 /* tp->lock is held. */
7429 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7430                            dma_addr_t mapping, u32 maxlen_flags,
7431                            u32 nic_addr)
7432 {
7433         tg3_write_mem(tp,
7434                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7435                       ((u64) mapping >> 32));
7436         tg3_write_mem(tp,
7437                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7438                       ((u64) mapping & 0xffffffff));
7439         tg3_write_mem(tp,
7440                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7441                        maxlen_flags);
7442
7443         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7444                 tg3_write_mem(tp,
7445                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7446                               nic_addr);
7447 }
7448
7449 static void __tg3_set_rx_mode(struct net_device *);
7450 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7451 {
7452         int i;
7453
7454         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7455                 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7456                 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7457                 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7458         } else {
7459                 tw32(HOSTCC_TXCOL_TICKS, 0);
7460                 tw32(HOSTCC_TXMAX_FRAMES, 0);
7461                 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7462         }
7463
7464         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)) {
7465                 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7466                 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7467                 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7468         } else {
7469                 tw32(HOSTCC_RXCOL_TICKS, 0);
7470                 tw32(HOSTCC_RXMAX_FRAMES, 0);
7471                 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7472         }
7473
7474         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7475                 u32 val = ec->stats_block_coalesce_usecs;
7476
7477                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7478                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7479
7480                 if (!netif_carrier_ok(tp->dev))
7481                         val = 0;
7482
7483                 tw32(HOSTCC_STAT_COAL_TICKS, val);
7484         }
7485
7486         for (i = 0; i < tp->irq_cnt - 1; i++) {
7487                 u32 reg;
7488
7489                 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7490                 tw32(reg, ec->rx_coalesce_usecs);
7491                 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7492                 tw32(reg, ec->rx_max_coalesced_frames);
7493                 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7494                 tw32(reg, ec->rx_max_coalesced_frames_irq);
7495
7496                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7497                         reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7498                         tw32(reg, ec->tx_coalesce_usecs);
7499                         reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7500                         tw32(reg, ec->tx_max_coalesced_frames);
7501                         reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7502                         tw32(reg, ec->tx_max_coalesced_frames_irq);
7503                 }
7504         }
7505
7506         for (; i < tp->irq_max - 1; i++) {
7507                 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7508                 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7509                 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7510
7511                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7512                         tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7513                         tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7514                         tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7515                 }
7516         }
7517 }
7518
7519 /* tp->lock is held. */
7520 static void tg3_rings_reset(struct tg3 *tp)
7521 {
7522         int i;
7523         u32 stblk, txrcb, rxrcb, limit;
7524         struct tg3_napi *tnapi = &tp->napi[0];
7525
7526         /* Disable all transmit rings but the first. */
7527         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7528                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7529         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7530                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7531         else
7532                 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7533
7534         for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7535              txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7536                 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7537                               BDINFO_FLAGS_DISABLED);
7538
7539
7540         /* Disable all receive return rings but the first. */
7541         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7542             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7543                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7544         else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7545                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7546         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7547                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7548                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7549         else
7550                 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7551
7552         for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7553              rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7554                 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7555                               BDINFO_FLAGS_DISABLED);
7556
7557         /* Disable interrupts */
7558         tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7559
7560         /* Zero mailbox registers. */
7561         if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7562                 for (i = 1; i < tp->irq_max; i++) {
7563                         tp->napi[i].tx_prod = 0;
7564                         tp->napi[i].tx_cons = 0;
7565                         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7566                                 tw32_mailbox(tp->napi[i].prodmbox, 0);
7567                         tw32_rx_mbox(tp->napi[i].consmbox, 0);
7568                         tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7569                 }
7570                 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7571                         tw32_mailbox(tp->napi[0].prodmbox, 0);
7572         } else {
7573                 tp->napi[0].tx_prod = 0;
7574                 tp->napi[0].tx_cons = 0;
7575                 tw32_mailbox(tp->napi[0].prodmbox, 0);
7576                 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7577         }
7578
7579         /* Make sure the NIC-based send BD rings are disabled. */
7580         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7581                 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7582                 for (i = 0; i < 16; i++)
7583                         tw32_tx_mbox(mbox + i * 8, 0);
7584         }
7585
7586         txrcb = NIC_SRAM_SEND_RCB;
7587         rxrcb = NIC_SRAM_RCV_RET_RCB;
7588
7589         /* Clear status block in ram. */
7590         memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7591
7592         /* Set status block DMA address */
7593         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7594              ((u64) tnapi->status_mapping >> 32));
7595         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7596              ((u64) tnapi->status_mapping & 0xffffffff));
7597
7598         if (tnapi->tx_ring) {
7599                 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7600                                (TG3_TX_RING_SIZE <<
7601                                 BDINFO_FLAGS_MAXLEN_SHIFT),
7602                                NIC_SRAM_TX_BUFFER_DESC);
7603                 txrcb += TG3_BDINFO_SIZE;
7604         }
7605
7606         if (tnapi->rx_rcb) {
7607                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7608                                (TG3_RX_RCB_RING_SIZE(tp) <<
7609                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7610                 rxrcb += TG3_BDINFO_SIZE;
7611         }
7612
7613         stblk = HOSTCC_STATBLCK_RING1;
7614
7615         for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7616                 u64 mapping = (u64)tnapi->status_mapping;
7617                 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7618                 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7619
7620                 /* Clear status block in ram. */
7621                 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7622
7623                 if (tnapi->tx_ring) {
7624                         tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7625                                        (TG3_TX_RING_SIZE <<
7626                                         BDINFO_FLAGS_MAXLEN_SHIFT),
7627                                        NIC_SRAM_TX_BUFFER_DESC);
7628                         txrcb += TG3_BDINFO_SIZE;
7629                 }
7630
7631                 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7632                                (TG3_RX_RCB_RING_SIZE(tp) <<
7633                                 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7634
7635                 stblk += 8;
7636                 rxrcb += TG3_BDINFO_SIZE;
7637         }
7638 }
7639
7640 /* tp->lock is held. */
7641 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7642 {
7643         u32 val, rdmac_mode;
7644         int i, err, limit;
7645         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
7646
7647         tg3_disable_ints(tp);
7648
7649         tg3_stop_fw(tp);
7650
7651         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7652
7653         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
7654                 tg3_abort_hw(tp, 1);
7655
7656         if (reset_phy)
7657                 tg3_phy_reset(tp);
7658
7659         err = tg3_chip_reset(tp);
7660         if (err)
7661                 return err;
7662
7663         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7664
7665         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7666                 val = tr32(TG3_CPMU_CTRL);
7667                 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7668                 tw32(TG3_CPMU_CTRL, val);
7669
7670                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7671                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7672                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7673                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7674
7675                 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7676                 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7677                 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7678                 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7679
7680                 val = tr32(TG3_CPMU_HST_ACC);
7681                 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7682                 val |= CPMU_HST_ACC_MACCLK_6_25;
7683                 tw32(TG3_CPMU_HST_ACC, val);
7684         }
7685
7686         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7687                 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7688                 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7689                        PCIE_PWR_MGMT_L1_THRESH_4MS;
7690                 tw32(PCIE_PWR_MGMT_THRESH, val);
7691
7692                 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7693                 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7694
7695                 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7696
7697                 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7698                 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7699         }
7700
7701         if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7702                 u32 grc_mode = tr32(GRC_MODE);
7703
7704                 /* Access the lower 1K of PL PCIE block registers. */
7705                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7706                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7707
7708                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7709                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7710                      val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7711
7712                 tw32(GRC_MODE, grc_mode);
7713         }
7714
7715         if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
7716                 u32 grc_mode = tr32(GRC_MODE);
7717
7718                 /* Access the lower 1K of PL PCIE block registers. */
7719                 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7720                 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7721
7722                 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
7723                 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
7724                      val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
7725
7726                 tw32(GRC_MODE, grc_mode);
7727
7728                 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7729                 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7730                 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7731                 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7732         }
7733
7734         /* This works around an issue with Athlon chipsets on
7735          * B3 tigon3 silicon.  This bit has no effect on any
7736          * other revision.  But do not set this on PCI Express
7737          * chips and don't even touch the clocks if the CPMU is present.
7738          */
7739         if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7740                 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7741                         tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7742                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7743         }
7744
7745         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7746             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7747                 val = tr32(TG3PCI_PCISTATE);
7748                 val |= PCISTATE_RETRY_SAME_DMA;
7749                 tw32(TG3PCI_PCISTATE, val);
7750         }
7751
7752         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7753                 /* Allow reads and writes to the
7754                  * APE register and memory space.
7755                  */
7756                 val = tr32(TG3PCI_PCISTATE);
7757                 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7758                        PCISTATE_ALLOW_APE_SHMEM_WR |
7759                        PCISTATE_ALLOW_APE_PSPACE_WR;
7760                 tw32(TG3PCI_PCISTATE, val);
7761         }
7762
7763         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7764                 /* Enable some hw fixes.  */
7765                 val = tr32(TG3PCI_MSI_DATA);
7766                 val |= (1 << 26) | (1 << 28) | (1 << 29);
7767                 tw32(TG3PCI_MSI_DATA, val);
7768         }
7769
7770         /* Descriptor ring init may make accesses to the
7771          * NIC SRAM area to setup the TX descriptors, so we
7772          * can only do this after the hardware has been
7773          * successfully reset.
7774          */
7775         err = tg3_init_rings(tp);
7776         if (err)
7777                 return err;
7778
7779         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7780                 val = tr32(TG3PCI_DMA_RW_CTRL) &
7781                       ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7782                 if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
7783                         val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
7784                 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7785         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7786                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7787                 /* This value is determined during the probe time DMA
7788                  * engine test, tg3_test_dma.
7789                  */
7790                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7791         }
7792
7793         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7794                           GRC_MODE_4X_NIC_SEND_RINGS |
7795                           GRC_MODE_NO_TX_PHDR_CSUM |
7796                           GRC_MODE_NO_RX_PHDR_CSUM);
7797         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7798
7799         /* Pseudo-header checksum is done by hardware logic and not
7800          * the offload processers, so make the chip do the pseudo-
7801          * header checksums on receive.  For transmit it is more
7802          * convenient to do the pseudo-header checksum in software
7803          * as Linux does that on transmit for us in all cases.
7804          */
7805         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7806
7807         tw32(GRC_MODE,
7808              tp->grc_mode |
7809              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7810
7811         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
7812         val = tr32(GRC_MISC_CFG);
7813         val &= ~0xff;
7814         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7815         tw32(GRC_MISC_CFG, val);
7816
7817         /* Initialize MBUF/DESC pool. */
7818         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7819                 /* Do nothing.  */
7820         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7821                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7822                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7823                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7824                 else
7825                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7826                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7827                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7828         } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7829                 int fw_len;
7830
7831                 fw_len = tp->fw_len;
7832                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7833                 tw32(BUFMGR_MB_POOL_ADDR,
7834                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7835                 tw32(BUFMGR_MB_POOL_SIZE,
7836                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7837         }
7838
7839         if (tp->dev->mtu <= ETH_DATA_LEN) {
7840                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7841                      tp->bufmgr_config.mbuf_read_dma_low_water);
7842                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7843                      tp->bufmgr_config.mbuf_mac_rx_low_water);
7844                 tw32(BUFMGR_MB_HIGH_WATER,
7845                      tp->bufmgr_config.mbuf_high_water);
7846         } else {
7847                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7848                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7849                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7850                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7851                 tw32(BUFMGR_MB_HIGH_WATER,
7852                      tp->bufmgr_config.mbuf_high_water_jumbo);
7853         }
7854         tw32(BUFMGR_DMA_LOW_WATER,
7855              tp->bufmgr_config.dma_low_water);
7856         tw32(BUFMGR_DMA_HIGH_WATER,
7857              tp->bufmgr_config.dma_high_water);
7858
7859         val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7860         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7861                 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7862         tw32(BUFMGR_MODE, val);
7863         for (i = 0; i < 2000; i++) {
7864                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7865                         break;
7866                 udelay(10);
7867         }
7868         if (i >= 2000) {
7869                 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
7870                 return -ENODEV;
7871         }
7872
7873         /* Setup replenish threshold. */
7874         val = tp->rx_pending / 8;
7875         if (val == 0)
7876                 val = 1;
7877         else if (val > tp->rx_std_max_post)
7878                 val = tp->rx_std_max_post;
7879         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7880                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7881                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7882
7883                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7884                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7885         }
7886
7887         tw32(RCVBDI_STD_THRESH, val);
7888
7889         /* Initialize TG3_BDINFO's at:
7890          *  RCVDBDI_STD_BD:     standard eth size rx ring
7891          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
7892          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
7893          *
7894          * like so:
7895          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
7896          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
7897          *                              ring attribute flags
7898          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
7899          *
7900          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7901          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7902          *
7903          * The size of each ring is fixed in the firmware, but the location is
7904          * configurable.
7905          */
7906         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7907              ((u64) tpr->rx_std_mapping >> 32));
7908         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7909              ((u64) tpr->rx_std_mapping & 0xffffffff));
7910         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
7911             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
7912                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7913                      NIC_SRAM_RX_BUFFER_DESC);
7914
7915         /* Disable the mini ring */
7916         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7917                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7918                      BDINFO_FLAGS_DISABLED);
7919
7920         /* Program the jumbo buffer descriptor ring control
7921          * blocks on those devices that have them.
7922          */
7923         if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7924             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7925                 /* Setup replenish threshold. */
7926                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7927
7928                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7929                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7930                              ((u64) tpr->rx_jmb_mapping >> 32));
7931                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7932                              ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7933                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7934                              (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7935                              BDINFO_FLAGS_USE_EXT_RECV);
7936                         if (!(tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) ||
7937                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7938                                 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7939                                      NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7940                 } else {
7941                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7942                              BDINFO_FLAGS_DISABLED);
7943                 }
7944
7945                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
7946                         val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7947                               (TG3_RX_STD_DMA_SZ << 2);
7948                 else
7949                         val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
7950         } else
7951                 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7952
7953         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7954
7955         tpr->rx_std_prod_idx = tp->rx_pending;
7956         tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7957
7958         tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7959                           tp->rx_jumbo_pending : 0;
7960         tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7961
7962         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
7963                 tw32(STD_REPLENISH_LWM, 32);
7964                 tw32(JMB_REPLENISH_LWM, 16);
7965         }
7966
7967         tg3_rings_reset(tp);
7968
7969         /* Initialize MAC address and backoff seed. */
7970         __tg3_set_mac_addr(tp, 0);
7971
7972         /* MTU + ethernet header + FCS + optional VLAN tag */
7973         tw32(MAC_RX_MTU_SIZE,
7974              tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7975
7976         /* The slot time is changed by tg3_setup_phy if we
7977          * run at gigabit with half duplex.
7978          */
7979         tw32(MAC_TX_LENGTHS,
7980              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7981              (6 << TX_LENGTHS_IPG_SHIFT) |
7982              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7983
7984         /* Receive rules. */
7985         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7986         tw32(RCVLPC_CONFIG, 0x0181);
7987
7988         /* Calculate RDMAC_MODE setting early, we need it to determine
7989          * the RCVLPC_STATE_ENABLE mask.
7990          */
7991         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7992                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7993                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7994                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7995                       RDMAC_MODE_LNGREAD_ENAB);
7996
7997         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7998             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7999                 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
8000
8001         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8002             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8003             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8004                 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
8005                               RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
8006                               RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
8007
8008         /* If statement applies to 5705 and 5750 PCI devices only */
8009         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8010              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8011             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
8012                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
8013                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
8014                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
8015                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8016                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
8017                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8018                 }
8019         }
8020
8021         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
8022                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
8023
8024         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8025                 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
8026
8027         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
8028             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8029             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
8030                 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
8031
8032         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
8033             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
8034             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
8035             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
8036             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
8037                 val = tr32(TG3_RDMA_RSRVCTRL_REG);
8038                 tw32(TG3_RDMA_RSRVCTRL_REG,
8039                      val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8040         }
8041
8042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8043                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8044                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8045                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8046                      TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8047         }
8048
8049         /* Receive/send statistics. */
8050         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8051                 val = tr32(RCVLPC_STATS_ENABLE);
8052                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
8053                 tw32(RCVLPC_STATS_ENABLE, val);
8054         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
8055                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8056                 val = tr32(RCVLPC_STATS_ENABLE);
8057                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
8058                 tw32(RCVLPC_STATS_ENABLE, val);
8059         } else {
8060                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
8061         }
8062         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
8063         tw32(SNDDATAI_STATSENAB, 0xffffff);
8064         tw32(SNDDATAI_STATSCTRL,
8065              (SNDDATAI_SCTRL_ENABLE |
8066               SNDDATAI_SCTRL_FASTUPD));
8067
8068         /* Setup host coalescing engine. */
8069         tw32(HOSTCC_MODE, 0);
8070         for (i = 0; i < 2000; i++) {
8071                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
8072                         break;
8073                 udelay(10);
8074         }
8075
8076         __tg3_set_coalesce(tp, &tp->coal);
8077
8078         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8079                 /* Status/statistics block address.  See tg3_timer,
8080                  * the tg3_periodic_fetch_stats call there, and
8081                  * tg3_get_stats to see how this works for 5705/5750 chips.
8082                  */
8083                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
8084                      ((u64) tp->stats_mapping >> 32));
8085                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
8086                      ((u64) tp->stats_mapping & 0xffffffff));
8087                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
8088
8089                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
8090
8091                 /* Clear statistics and status block memory areas */
8092                 for (i = NIC_SRAM_STATS_BLK;
8093                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
8094                      i += sizeof(u32)) {
8095                         tg3_write_mem(tp, i, 0);
8096                         udelay(40);
8097                 }
8098         }
8099
8100         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
8101
8102         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
8103         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
8104         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8105                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
8106
8107         if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
8108                 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
8109                 /* reset to prevent losing 1st rx packet intermittently */
8110                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8111                 udelay(10);
8112         }
8113
8114         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8115                 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
8116         else
8117                 tp->mac_mode = 0;
8118         tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
8119                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
8120         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8121             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8122             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
8123                 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8124         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
8125         udelay(40);
8126
8127         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
8128          * If TG3_FLG2_IS_NIC is zero, we should read the
8129          * register to preserve the GPIO settings for LOMs. The GPIOs,
8130          * whether used as inputs or outputs, are set by boot code after
8131          * reset.
8132          */
8133         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
8134                 u32 gpio_mask;
8135
8136                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
8137                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
8138                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
8139
8140                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8141                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
8142                                      GRC_LCLCTRL_GPIO_OUTPUT3;
8143
8144                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
8145                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
8146
8147                 tp->grc_local_ctrl &= ~gpio_mask;
8148                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
8149
8150                 /* GPIO1 must be driven high for eeprom write protect */
8151                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
8152                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8153                                                GRC_LCLCTRL_GPIO_OUTPUT1);
8154         }
8155         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8156         udelay(100);
8157
8158         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
8159                 val = tr32(MSGINT_MODE);
8160                 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
8161                 tw32(MSGINT_MODE, val);
8162         }
8163
8164         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8165                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8166                 udelay(40);
8167         }
8168
8169         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8170                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8171                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8172                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8173                WDMAC_MODE_LNGREAD_ENAB);
8174
8175         /* If statement applies to 5705 and 5750 PCI devices only */
8176         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8177              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8178             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8179                 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8180                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8181                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8182                         /* nothing */
8183                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8184                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8185                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8186                         val |= WDMAC_MODE_RX_ACCEL;
8187                 }
8188         }
8189
8190         /* Enable host coalescing bug fix */
8191         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8192                 val |= WDMAC_MODE_STATUS_TAG_FIX;
8193
8194         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8195                 val |= WDMAC_MODE_BURST_ALL_DATA;
8196
8197         tw32_f(WDMAC_MODE, val);
8198         udelay(40);
8199
8200         if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8201                 u16 pcix_cmd;
8202
8203                 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8204                                      &pcix_cmd);
8205                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8206                         pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8207                         pcix_cmd |= PCI_X_CMD_READ_2K;
8208                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8209                         pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8210                         pcix_cmd |= PCI_X_CMD_READ_2K;
8211                 }
8212                 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8213                                       pcix_cmd);
8214         }
8215
8216         tw32_f(RDMAC_MODE, rdmac_mode);
8217         udelay(40);
8218
8219         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8220         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8221                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8222
8223         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8224                 tw32(SNDDATAC_MODE,
8225                      SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8226         else
8227                 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8228
8229         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8230         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8231         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8232         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8233         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8234                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8235         val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8236         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8237                 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8238         tw32(SNDBDI_MODE, val);
8239         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8240
8241         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8242                 err = tg3_load_5701_a0_firmware_fix(tp);
8243                 if (err)
8244                         return err;
8245         }
8246
8247         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8248                 err = tg3_load_tso_firmware(tp);
8249                 if (err)
8250                         return err;
8251         }
8252
8253         tp->tx_mode = TX_MODE_ENABLE;
8254         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
8255             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8256                 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
8257         tw32_f(MAC_TX_MODE, tp->tx_mode);
8258         udelay(100);
8259
8260         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8261                 u32 reg = MAC_RSS_INDIR_TBL_0;
8262                 u8 *ent = (u8 *)&val;
8263
8264                 /* Setup the indirection table */
8265                 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8266                         int idx = i % sizeof(val);
8267
8268                         ent[idx] = i % (tp->irq_cnt - 1);
8269                         if (idx == sizeof(val) - 1) {
8270                                 tw32(reg, val);
8271                                 reg += 4;
8272                         }
8273                 }
8274
8275                 /* Setup the "secret" hash key. */
8276                 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8277                 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8278                 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8279                 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8280                 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8281                 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8282                 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8283                 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8284                 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8285                 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8286         }
8287
8288         tp->rx_mode = RX_MODE_ENABLE;
8289         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8290                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8291
8292         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8293                 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8294                                RX_MODE_RSS_ITBL_HASH_BITS_7 |
8295                                RX_MODE_RSS_IPV6_HASH_EN |
8296                                RX_MODE_RSS_TCP_IPV6_HASH_EN |
8297                                RX_MODE_RSS_IPV4_HASH_EN |
8298                                RX_MODE_RSS_TCP_IPV4_HASH_EN;
8299
8300         tw32_f(MAC_RX_MODE, tp->rx_mode);
8301         udelay(10);
8302
8303         tw32(MAC_LED_CTRL, tp->led_ctrl);
8304
8305         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8306         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8307                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8308                 udelay(10);
8309         }
8310         tw32_f(MAC_RX_MODE, tp->rx_mode);
8311         udelay(10);
8312
8313         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
8314                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8315                         !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
8316                         /* Set drive transmission level to 1.2V  */
8317                         /* only if the signal pre-emphasis bit is not set  */
8318                         val = tr32(MAC_SERDES_CFG);
8319                         val &= 0xfffff000;
8320                         val |= 0x880;
8321                         tw32(MAC_SERDES_CFG, val);
8322                 }
8323                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8324                         tw32(MAC_SERDES_CFG, 0x616000);
8325         }
8326
8327         /* Prevent chip from dropping frames when flow control
8328          * is enabled.
8329          */
8330         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8331                 val = 1;
8332         else
8333                 val = 2;
8334         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8335
8336         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8337             (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
8338                 /* Use hardware link auto-negotiation */
8339                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8340         }
8341
8342         if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8344                 u32 tmp;
8345
8346                 tmp = tr32(SERDES_RX_CTRL);
8347                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8348                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8349                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8350                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8351         }
8352
8353         if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8354                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
8355                         tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
8356                         tp->link_config.speed = tp->link_config.orig_speed;
8357                         tp->link_config.duplex = tp->link_config.orig_duplex;
8358                         tp->link_config.autoneg = tp->link_config.orig_autoneg;
8359                 }
8360
8361                 err = tg3_setup_phy(tp, 0);
8362                 if (err)
8363                         return err;
8364
8365                 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
8366                     !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8367                         u32 tmp;
8368
8369                         /* Clear CRC stats. */
8370                         if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8371                                 tg3_writephy(tp, MII_TG3_TEST1,
8372                                              tmp | MII_TG3_TEST1_CRC_EN);
8373                                 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
8374                         }
8375                 }
8376         }
8377
8378         __tg3_set_rx_mode(tp->dev);
8379
8380         /* Initialize receive rules. */
8381         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
8382         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8383         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
8384         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8385
8386         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8387             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8388                 limit = 8;
8389         else
8390                 limit = 16;
8391         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8392                 limit -= 4;
8393         switch (limit) {
8394         case 16:
8395                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
8396         case 15:
8397                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
8398         case 14:
8399                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
8400         case 13:
8401                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
8402         case 12:
8403                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
8404         case 11:
8405                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
8406         case 10:
8407                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
8408         case 9:
8409                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
8410         case 8:
8411                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
8412         case 7:
8413                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
8414         case 6:
8415                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
8416         case 5:
8417                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
8418         case 4:
8419                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
8420         case 3:
8421                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
8422         case 2:
8423         case 1:
8424
8425         default:
8426                 break;
8427         }
8428
8429         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8430                 /* Write our heartbeat update interval to APE. */
8431                 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8432                                 APE_HOST_HEARTBEAT_INT_DISABLE);
8433
8434         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8435
8436         return 0;
8437 }
8438
8439 /* Called at device open time to get the chip ready for
8440  * packet processing.  Invoked with tp->lock held.
8441  */
8442 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8443 {
8444         tg3_switch_clocks(tp);
8445
8446         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8447
8448         return tg3_reset_hw(tp, reset_phy);
8449 }
8450
8451 #define TG3_STAT_ADD32(PSTAT, REG) \
8452 do {    u32 __val = tr32(REG); \
8453         (PSTAT)->low += __val; \
8454         if ((PSTAT)->low < __val) \
8455                 (PSTAT)->high += 1; \
8456 } while (0)
8457
8458 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8459 {
8460         struct tg3_hw_stats *sp = tp->hw_stats;
8461
8462         if (!netif_carrier_ok(tp->dev))
8463                 return;
8464
8465         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8466         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8467         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8468         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8469         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8470         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8471         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8472         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8473         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8474         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8475         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8476         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8477         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8478
8479         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8480         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8481         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8482         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8483         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8484         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8485         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8486         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8487         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8488         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8489         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8490         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8491         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8492         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8493
8494         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8495         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8496         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8497 }
8498
8499 static void tg3_timer(unsigned long __opaque)
8500 {
8501         struct tg3 *tp = (struct tg3 *) __opaque;
8502
8503         if (tp->irq_sync)
8504                 goto restart_timer;
8505
8506         spin_lock(&tp->lock);
8507
8508         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8509                 /* All of this garbage is because when using non-tagged
8510                  * IRQ status the mailbox/status_block protocol the chip
8511                  * uses with the cpu is race prone.
8512                  */
8513                 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8514                         tw32(GRC_LOCAL_CTRL,
8515                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8516                 } else {
8517                         tw32(HOSTCC_MODE, tp->coalesce_mode |
8518                              HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8519                 }
8520
8521                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8522                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8523                         spin_unlock(&tp->lock);
8524                         schedule_work(&tp->reset_task);
8525                         return;
8526                 }
8527         }
8528
8529         /* This part only runs once per second. */
8530         if (!--tp->timer_counter) {
8531                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8532                         tg3_periodic_fetch_stats(tp);
8533
8534                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8535                         u32 mac_stat;
8536                         int phy_event;
8537
8538                         mac_stat = tr32(MAC_STATUS);
8539
8540                         phy_event = 0;
8541                         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
8542                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8543                                         phy_event = 1;
8544                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8545                                 phy_event = 1;
8546
8547                         if (phy_event)
8548                                 tg3_setup_phy(tp, 0);
8549                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8550                         u32 mac_stat = tr32(MAC_STATUS);
8551                         int need_setup = 0;
8552
8553                         if (netif_carrier_ok(tp->dev) &&
8554                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8555                                 need_setup = 1;
8556                         }
8557                         if (!netif_carrier_ok(tp->dev) &&
8558                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
8559                                          MAC_STATUS_SIGNAL_DET))) {
8560                                 need_setup = 1;
8561                         }
8562                         if (need_setup) {
8563                                 if (!tp->serdes_counter) {
8564                                         tw32_f(MAC_MODE,
8565                                              (tp->mac_mode &
8566                                               ~MAC_MODE_PORT_MODE_MASK));
8567                                         udelay(40);
8568                                         tw32_f(MAC_MODE, tp->mac_mode);
8569                                         udelay(40);
8570                                 }
8571                                 tg3_setup_phy(tp, 0);
8572                         }
8573                 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8574                            (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8575                         tg3_serdes_parallel_detect(tp);
8576                 }
8577
8578                 tp->timer_counter = tp->timer_multiplier;
8579         }
8580
8581         /* Heartbeat is only sent once every 2 seconds.
8582          *
8583          * The heartbeat is to tell the ASF firmware that the host
8584          * driver is still alive.  In the event that the OS crashes,
8585          * ASF needs to reset the hardware to free up the FIFO space
8586          * that may be filled with rx packets destined for the host.
8587          * If the FIFO is full, ASF will no longer function properly.
8588          *
8589          * Unintended resets have been reported on real time kernels
8590          * where the timer doesn't run on time.  Netpoll will also have
8591          * same problem.
8592          *
8593          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8594          * to check the ring condition when the heartbeat is expiring
8595          * before doing the reset.  This will prevent most unintended
8596          * resets.
8597          */
8598         if (!--tp->asf_counter) {
8599                 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8600                     !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8601                         tg3_wait_for_event_ack(tp);
8602
8603                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8604                                       FWCMD_NICDRV_ALIVE3);
8605                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8606                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
8607                                       TG3_FW_UPDATE_TIMEOUT_SEC);
8608
8609                         tg3_generate_fw_event(tp);
8610                 }
8611                 tp->asf_counter = tp->asf_multiplier;
8612         }
8613
8614         spin_unlock(&tp->lock);
8615
8616 restart_timer:
8617         tp->timer.expires = jiffies + tp->timer_offset;
8618         add_timer(&tp->timer);
8619 }
8620
8621 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8622 {
8623         irq_handler_t fn;
8624         unsigned long flags;
8625         char *name;
8626         struct tg3_napi *tnapi = &tp->napi[irq_num];
8627
8628         if (tp->irq_cnt == 1)
8629                 name = tp->dev->name;
8630         else {
8631                 name = &tnapi->irq_lbl[0];
8632                 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8633                 name[IFNAMSIZ-1] = 0;
8634         }
8635
8636         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8637                 fn = tg3_msi;
8638                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8639                         fn = tg3_msi_1shot;
8640                 flags = IRQF_SAMPLE_RANDOM;
8641         } else {
8642                 fn = tg3_interrupt;
8643                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8644                         fn = tg3_interrupt_tagged;
8645                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8646         }
8647
8648         return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8649 }
8650
8651 static int tg3_test_interrupt(struct tg3 *tp)
8652 {
8653         struct tg3_napi *tnapi = &tp->napi[0];
8654         struct net_device *dev = tp->dev;
8655         int err, i, intr_ok = 0;
8656         u32 val;
8657
8658         if (!netif_running(dev))
8659                 return -ENODEV;
8660
8661         tg3_disable_ints(tp);
8662
8663         free_irq(tnapi->irq_vec, tnapi);
8664
8665         /*
8666          * Turn off MSI one shot mode.  Otherwise this test has no
8667          * observable way to know whether the interrupt was delivered.
8668          */
8669         if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8670             (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8671                 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8672                 tw32(MSGINT_MODE, val);
8673         }
8674
8675         err = request_irq(tnapi->irq_vec, tg3_test_isr,
8676                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8677         if (err)
8678                 return err;
8679
8680         tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8681         tg3_enable_ints(tp);
8682
8683         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8684                tnapi->coal_now);
8685
8686         for (i = 0; i < 5; i++) {
8687                 u32 int_mbox, misc_host_ctrl;
8688
8689                 int_mbox = tr32_mailbox(tnapi->int_mbox);
8690                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8691
8692                 if ((int_mbox != 0) ||
8693                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8694                         intr_ok = 1;
8695                         break;
8696                 }
8697
8698                 msleep(10);
8699         }
8700
8701         tg3_disable_ints(tp);
8702
8703         free_irq(tnapi->irq_vec, tnapi);
8704
8705         err = tg3_request_irq(tp, 0);
8706
8707         if (err)
8708                 return err;
8709
8710         if (intr_ok) {
8711                 /* Reenable MSI one shot mode. */
8712                 if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
8713                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8714                         val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8715                         tw32(MSGINT_MODE, val);
8716                 }
8717                 return 0;
8718         }
8719
8720         return -EIO;
8721 }
8722
8723 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8724  * successfully restored
8725  */
8726 static int tg3_test_msi(struct tg3 *tp)
8727 {
8728         int err;
8729         u16 pci_cmd;
8730
8731         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8732                 return 0;
8733
8734         /* Turn off SERR reporting in case MSI terminates with Master
8735          * Abort.
8736          */
8737         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8738         pci_write_config_word(tp->pdev, PCI_COMMAND,
8739                               pci_cmd & ~PCI_COMMAND_SERR);
8740
8741         err = tg3_test_interrupt(tp);
8742
8743         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8744
8745         if (!err)
8746                 return 0;
8747
8748         /* other failures */
8749         if (err != -EIO)
8750                 return err;
8751
8752         /* MSI test failed, go back to INTx mode */
8753         netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
8754                     "to INTx mode. Please report this failure to the PCI "
8755                     "maintainer and include system chipset information\n");
8756
8757         free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8758
8759         pci_disable_msi(tp->pdev);
8760
8761         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8762         tp->napi[0].irq_vec = tp->pdev->irq;
8763
8764         err = tg3_request_irq(tp, 0);
8765         if (err)
8766                 return err;
8767
8768         /* Need to reset the chip because the MSI cycle may have terminated
8769          * with Master Abort.
8770          */
8771         tg3_full_lock(tp, 1);
8772
8773         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8774         err = tg3_init_hw(tp, 1);
8775
8776         tg3_full_unlock(tp);
8777
8778         if (err)
8779                 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8780
8781         return err;
8782 }
8783
8784 static int tg3_request_firmware(struct tg3 *tp)
8785 {
8786         const __be32 *fw_data;
8787
8788         if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8789                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
8790                            tp->fw_needed);
8791                 return -ENOENT;
8792         }
8793
8794         fw_data = (void *)tp->fw->data;
8795
8796         /* Firmware blob starts with version numbers, followed by
8797          * start address and _full_ length including BSS sections
8798          * (which must be longer than the actual data, of course
8799          */
8800
8801         tp->fw_len = be32_to_cpu(fw_data[2]);   /* includes bss */
8802         if (tp->fw_len < (tp->fw->size - 12)) {
8803                 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
8804                            tp->fw_len, tp->fw_needed);
8805                 release_firmware(tp->fw);
8806                 tp->fw = NULL;
8807                 return -EINVAL;
8808         }
8809
8810         /* We no longer need firmware; we have it. */
8811         tp->fw_needed = NULL;
8812         return 0;
8813 }
8814
8815 static bool tg3_enable_msix(struct tg3 *tp)
8816 {
8817         int i, rc, cpus = num_online_cpus();
8818         struct msix_entry msix_ent[tp->irq_max];
8819
8820         if (cpus == 1)
8821                 /* Just fallback to the simpler MSI mode. */
8822                 return false;
8823
8824         /*
8825          * We want as many rx rings enabled as there are cpus.
8826          * The first MSIX vector only deals with link interrupts, etc,
8827          * so we add one to the number of vectors we are requesting.
8828          */
8829         tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8830
8831         for (i = 0; i < tp->irq_max; i++) {
8832                 msix_ent[i].entry  = i;
8833                 msix_ent[i].vector = 0;
8834         }
8835
8836         rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8837         if (rc < 0) {
8838                 return false;
8839         } else if (rc != 0) {
8840                 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8841                         return false;
8842                 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
8843                               tp->irq_cnt, rc);
8844                 tp->irq_cnt = rc;
8845         }
8846
8847         for (i = 0; i < tp->irq_max; i++)
8848                 tp->napi[i].irq_vec = msix_ent[i].vector;
8849
8850         netif_set_real_num_tx_queues(tp->dev, 1);
8851         rc = tp->irq_cnt > 1 ? tp->irq_cnt - 1 : 1;
8852         if (netif_set_real_num_rx_queues(tp->dev, rc)) {
8853                 pci_disable_msix(tp->pdev);
8854                 return false;
8855         }
8856         if (tp->irq_cnt > 1)
8857                 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8858
8859         return true;
8860 }
8861
8862 static void tg3_ints_init(struct tg3 *tp)
8863 {
8864         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8865             !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8866                 /* All MSI supporting chips should support tagged
8867                  * status.  Assert that this is the case.
8868                  */
8869                 netdev_warn(tp->dev,
8870                             "MSI without TAGGED_STATUS? Not using MSI\n");
8871                 goto defcfg;
8872         }
8873
8874         if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8875                 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8876         else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8877                  pci_enable_msi(tp->pdev) == 0)
8878                 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8879
8880         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8881                 u32 msi_mode = tr32(MSGINT_MODE);
8882                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8883                         msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8884                 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8885         }
8886 defcfg:
8887         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8888                 tp->irq_cnt = 1;
8889                 tp->napi[0].irq_vec = tp->pdev->irq;
8890                 netif_set_real_num_tx_queues(tp->dev, 1);
8891         }
8892 }
8893
8894 static void tg3_ints_fini(struct tg3 *tp)
8895 {
8896         if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8897                 pci_disable_msix(tp->pdev);
8898         else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8899                 pci_disable_msi(tp->pdev);
8900         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8901         tp->tg3_flags3 &= ~(TG3_FLG3_ENABLE_RSS | TG3_FLG3_ENABLE_TSS);
8902 }
8903
8904 static int tg3_open(struct net_device *dev)
8905 {
8906         struct tg3 *tp = netdev_priv(dev);
8907         int i, err;
8908
8909         if (tp->fw_needed) {
8910                 err = tg3_request_firmware(tp);
8911                 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8912                         if (err)
8913                                 return err;
8914                 } else if (err) {
8915                         netdev_warn(tp->dev, "TSO capability disabled\n");
8916                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8917                 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8918                         netdev_notice(tp->dev, "TSO capability restored\n");
8919                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8920                 }
8921         }
8922
8923         netif_carrier_off(tp->dev);
8924
8925         err = tg3_set_power_state(tp, PCI_D0);
8926         if (err)
8927                 return err;
8928
8929         tg3_full_lock(tp, 0);
8930
8931         tg3_disable_ints(tp);
8932         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8933
8934         tg3_full_unlock(tp);
8935
8936         /*
8937          * Setup interrupts first so we know how
8938          * many NAPI resources to allocate
8939          */
8940         tg3_ints_init(tp);
8941
8942         /* The placement of this call is tied
8943          * to the setup and use of Host TX descriptors.
8944          */
8945         err = tg3_alloc_consistent(tp);
8946         if (err)
8947                 goto err_out1;
8948
8949         tg3_napi_init(tp);
8950
8951         tg3_napi_enable(tp);
8952
8953         for (i = 0; i < tp->irq_cnt; i++) {
8954                 struct tg3_napi *tnapi = &tp->napi[i];
8955                 err = tg3_request_irq(tp, i);
8956                 if (err) {
8957                         for (i--; i >= 0; i--)
8958                                 free_irq(tnapi->irq_vec, tnapi);
8959                         break;
8960                 }
8961         }
8962
8963         if (err)
8964                 goto err_out2;
8965
8966         tg3_full_lock(tp, 0);
8967
8968         err = tg3_init_hw(tp, 1);
8969         if (err) {
8970                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8971                 tg3_free_rings(tp);
8972         } else {
8973                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8974                         tp->timer_offset = HZ;
8975                 else
8976                         tp->timer_offset = HZ / 10;
8977
8978                 BUG_ON(tp->timer_offset > HZ);
8979                 tp->timer_counter = tp->timer_multiplier =
8980                         (HZ / tp->timer_offset);
8981                 tp->asf_counter = tp->asf_multiplier =
8982                         ((HZ / tp->timer_offset) * 2);
8983
8984                 init_timer(&tp->timer);
8985                 tp->timer.expires = jiffies + tp->timer_offset;
8986                 tp->timer.data = (unsigned long) tp;
8987                 tp->timer.function = tg3_timer;
8988         }
8989
8990         tg3_full_unlock(tp);
8991
8992         if (err)
8993                 goto err_out3;
8994
8995         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8996                 err = tg3_test_msi(tp);
8997
8998                 if (err) {
8999                         tg3_full_lock(tp, 0);
9000                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9001                         tg3_free_rings(tp);
9002                         tg3_full_unlock(tp);
9003
9004                         goto err_out2;
9005                 }
9006
9007                 if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) &&
9008                     (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
9009                         u32 val = tr32(PCIE_TRANSACTION_CFG);
9010
9011                         tw32(PCIE_TRANSACTION_CFG,
9012                              val | PCIE_TRANS_CFG_1SHOT_MSI);
9013                 }
9014         }
9015
9016         tg3_phy_start(tp);
9017
9018         tg3_full_lock(tp, 0);
9019
9020         add_timer(&tp->timer);
9021         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9022         tg3_enable_ints(tp);
9023
9024         tg3_full_unlock(tp);
9025
9026         netif_tx_start_all_queues(dev);
9027
9028         return 0;
9029
9030 err_out3:
9031         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9032                 struct tg3_napi *tnapi = &tp->napi[i];
9033                 free_irq(tnapi->irq_vec, tnapi);
9034         }
9035
9036 err_out2:
9037         tg3_napi_disable(tp);
9038         tg3_napi_fini(tp);
9039         tg3_free_consistent(tp);
9040
9041 err_out1:
9042         tg3_ints_fini(tp);
9043         return err;
9044 }
9045
9046 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *,
9047                                                  struct rtnl_link_stats64 *);
9048 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9049
9050 static int tg3_close(struct net_device *dev)
9051 {
9052         int i;
9053         struct tg3 *tp = netdev_priv(dev);
9054
9055         tg3_napi_disable(tp);
9056         cancel_work_sync(&tp->reset_task);
9057
9058         netif_tx_stop_all_queues(dev);
9059
9060         del_timer_sync(&tp->timer);
9061
9062         tg3_phy_stop(tp);
9063
9064         tg3_full_lock(tp, 1);
9065
9066         tg3_disable_ints(tp);
9067
9068         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9069         tg3_free_rings(tp);
9070         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9071
9072         tg3_full_unlock(tp);
9073
9074         for (i = tp->irq_cnt - 1; i >= 0; i--) {
9075                 struct tg3_napi *tnapi = &tp->napi[i];
9076                 free_irq(tnapi->irq_vec, tnapi);
9077         }
9078
9079         tg3_ints_fini(tp);
9080
9081         tg3_get_stats64(tp->dev, &tp->net_stats_prev);
9082
9083         memcpy(&tp->estats_prev, tg3_get_estats(tp),
9084                sizeof(tp->estats_prev));
9085
9086         tg3_napi_fini(tp);
9087
9088         tg3_free_consistent(tp);
9089
9090         tg3_set_power_state(tp, PCI_D3hot);
9091
9092         netif_carrier_off(tp->dev);
9093
9094         return 0;
9095 }
9096
9097 static inline u64 get_stat64(tg3_stat64_t *val)
9098 {
9099        return ((u64)val->high << 32) | ((u64)val->low);
9100 }
9101
9102 static u64 calc_crc_errors(struct tg3 *tp)
9103 {
9104         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9105
9106         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
9107             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9108              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9109                 u32 val;
9110
9111                 spin_lock_bh(&tp->lock);
9112                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9113                         tg3_writephy(tp, MII_TG3_TEST1,
9114                                      val | MII_TG3_TEST1_CRC_EN);
9115                         tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
9116                 } else
9117                         val = 0;
9118                 spin_unlock_bh(&tp->lock);
9119
9120                 tp->phy_crc_errors += val;
9121
9122                 return tp->phy_crc_errors;
9123         }
9124
9125         return get_stat64(&hw_stats->rx_fcs_errors);
9126 }
9127
9128 #define ESTAT_ADD(member) \
9129         estats->member =        old_estats->member + \
9130                                 get_stat64(&hw_stats->member)
9131
9132 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9133 {
9134         struct tg3_ethtool_stats *estats = &tp->estats;
9135         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9136         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9137
9138         if (!hw_stats)
9139                 return old_estats;
9140
9141         ESTAT_ADD(rx_octets);
9142         ESTAT_ADD(rx_fragments);
9143         ESTAT_ADD(rx_ucast_packets);
9144         ESTAT_ADD(rx_mcast_packets);
9145         ESTAT_ADD(rx_bcast_packets);
9146         ESTAT_ADD(rx_fcs_errors);
9147         ESTAT_ADD(rx_align_errors);
9148         ESTAT_ADD(rx_xon_pause_rcvd);
9149         ESTAT_ADD(rx_xoff_pause_rcvd);
9150         ESTAT_ADD(rx_mac_ctrl_rcvd);
9151         ESTAT_ADD(rx_xoff_entered);
9152         ESTAT_ADD(rx_frame_too_long_errors);
9153         ESTAT_ADD(rx_jabbers);
9154         ESTAT_ADD(rx_undersize_packets);
9155         ESTAT_ADD(rx_in_length_errors);
9156         ESTAT_ADD(rx_out_length_errors);
9157         ESTAT_ADD(rx_64_or_less_octet_packets);
9158         ESTAT_ADD(rx_65_to_127_octet_packets);
9159         ESTAT_ADD(rx_128_to_255_octet_packets);
9160         ESTAT_ADD(rx_256_to_511_octet_packets);
9161         ESTAT_ADD(rx_512_to_1023_octet_packets);
9162         ESTAT_ADD(rx_1024_to_1522_octet_packets);
9163         ESTAT_ADD(rx_1523_to_2047_octet_packets);
9164         ESTAT_ADD(rx_2048_to_4095_octet_packets);
9165         ESTAT_ADD(rx_4096_to_8191_octet_packets);
9166         ESTAT_ADD(rx_8192_to_9022_octet_packets);
9167
9168         ESTAT_ADD(tx_octets);
9169         ESTAT_ADD(tx_collisions);
9170         ESTAT_ADD(tx_xon_sent);
9171         ESTAT_ADD(tx_xoff_sent);
9172         ESTAT_ADD(tx_flow_control);
9173         ESTAT_ADD(tx_mac_errors);
9174         ESTAT_ADD(tx_single_collisions);
9175         ESTAT_ADD(tx_mult_collisions);
9176         ESTAT_ADD(tx_deferred);
9177         ESTAT_ADD(tx_excessive_collisions);
9178         ESTAT_ADD(tx_late_collisions);
9179         ESTAT_ADD(tx_collide_2times);
9180         ESTAT_ADD(tx_collide_3times);
9181         ESTAT_ADD(tx_collide_4times);
9182         ESTAT_ADD(tx_collide_5times);
9183         ESTAT_ADD(tx_collide_6times);
9184         ESTAT_ADD(tx_collide_7times);
9185         ESTAT_ADD(tx_collide_8times);
9186         ESTAT_ADD(tx_collide_9times);
9187         ESTAT_ADD(tx_collide_10times);
9188         ESTAT_ADD(tx_collide_11times);
9189         ESTAT_ADD(tx_collide_12times);
9190         ESTAT_ADD(tx_collide_13times);
9191         ESTAT_ADD(tx_collide_14times);
9192         ESTAT_ADD(tx_collide_15times);
9193         ESTAT_ADD(tx_ucast_packets);
9194         ESTAT_ADD(tx_mcast_packets);
9195         ESTAT_ADD(tx_bcast_packets);
9196         ESTAT_ADD(tx_carrier_sense_errors);
9197         ESTAT_ADD(tx_discards);
9198         ESTAT_ADD(tx_errors);
9199
9200         ESTAT_ADD(dma_writeq_full);
9201         ESTAT_ADD(dma_write_prioq_full);
9202         ESTAT_ADD(rxbds_empty);
9203         ESTAT_ADD(rx_discards);
9204         ESTAT_ADD(rx_errors);
9205         ESTAT_ADD(rx_threshold_hit);
9206
9207         ESTAT_ADD(dma_readq_full);
9208         ESTAT_ADD(dma_read_prioq_full);
9209         ESTAT_ADD(tx_comp_queue_full);
9210
9211         ESTAT_ADD(ring_set_send_prod_index);
9212         ESTAT_ADD(ring_status_update);
9213         ESTAT_ADD(nic_irqs);
9214         ESTAT_ADD(nic_avoided_irqs);
9215         ESTAT_ADD(nic_tx_threshold_hit);
9216
9217         return estats;
9218 }
9219
9220 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
9221                                                  struct rtnl_link_stats64 *stats)
9222 {
9223         struct tg3 *tp = netdev_priv(dev);
9224         struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
9225         struct tg3_hw_stats *hw_stats = tp->hw_stats;
9226
9227         if (!hw_stats)
9228                 return old_stats;
9229
9230         stats->rx_packets = old_stats->rx_packets +
9231                 get_stat64(&hw_stats->rx_ucast_packets) +
9232                 get_stat64(&hw_stats->rx_mcast_packets) +
9233                 get_stat64(&hw_stats->rx_bcast_packets);
9234
9235         stats->tx_packets = old_stats->tx_packets +
9236                 get_stat64(&hw_stats->tx_ucast_packets) +
9237                 get_stat64(&hw_stats->tx_mcast_packets) +
9238                 get_stat64(&hw_stats->tx_bcast_packets);
9239
9240         stats->rx_bytes = old_stats->rx_bytes +
9241                 get_stat64(&hw_stats->rx_octets);
9242         stats->tx_bytes = old_stats->tx_bytes +
9243                 get_stat64(&hw_stats->tx_octets);
9244
9245         stats->rx_errors = old_stats->rx_errors +
9246                 get_stat64(&hw_stats->rx_errors);
9247         stats->tx_errors = old_stats->tx_errors +
9248                 get_stat64(&hw_stats->tx_errors) +
9249                 get_stat64(&hw_stats->tx_mac_errors) +
9250                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9251                 get_stat64(&hw_stats->tx_discards);
9252
9253         stats->multicast = old_stats->multicast +
9254                 get_stat64(&hw_stats->rx_mcast_packets);
9255         stats->collisions = old_stats->collisions +
9256                 get_stat64(&hw_stats->tx_collisions);
9257
9258         stats->rx_length_errors = old_stats->rx_length_errors +
9259                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9260                 get_stat64(&hw_stats->rx_undersize_packets);
9261
9262         stats->rx_over_errors = old_stats->rx_over_errors +
9263                 get_stat64(&hw_stats->rxbds_empty);
9264         stats->rx_frame_errors = old_stats->rx_frame_errors +
9265                 get_stat64(&hw_stats->rx_align_errors);
9266         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9267                 get_stat64(&hw_stats->tx_discards);
9268         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9269                 get_stat64(&hw_stats->tx_carrier_sense_errors);
9270
9271         stats->rx_crc_errors = old_stats->rx_crc_errors +
9272                 calc_crc_errors(tp);
9273
9274         stats->rx_missed_errors = old_stats->rx_missed_errors +
9275                 get_stat64(&hw_stats->rx_discards);
9276
9277         return stats;
9278 }
9279
9280 static inline u32 calc_crc(unsigned char *buf, int len)
9281 {
9282         u32 reg;
9283         u32 tmp;
9284         int j, k;
9285
9286         reg = 0xffffffff;
9287
9288         for (j = 0; j < len; j++) {
9289                 reg ^= buf[j];
9290
9291                 for (k = 0; k < 8; k++) {
9292                         tmp = reg & 0x01;
9293
9294                         reg >>= 1;
9295
9296                         if (tmp)
9297                                 reg ^= 0xedb88320;
9298                 }
9299         }
9300
9301         return ~reg;
9302 }
9303
9304 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9305 {
9306         /* accept or reject all multicast frames */
9307         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9308         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9309         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9310         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9311 }
9312
9313 static void __tg3_set_rx_mode(struct net_device *dev)
9314 {
9315         struct tg3 *tp = netdev_priv(dev);
9316         u32 rx_mode;
9317
9318         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9319                                   RX_MODE_KEEP_VLAN_TAG);
9320
9321         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9322          * flag clear.
9323          */
9324 #if TG3_VLAN_TAG_USED
9325         if (!tp->vlgrp &&
9326             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9327                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9328 #else
9329         /* By definition, VLAN is disabled always in this
9330          * case.
9331          */
9332         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9333                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9334 #endif
9335
9336         if (dev->flags & IFF_PROMISC) {
9337                 /* Promiscuous mode. */
9338                 rx_mode |= RX_MODE_PROMISC;
9339         } else if (dev->flags & IFF_ALLMULTI) {
9340                 /* Accept all multicast. */
9341                 tg3_set_multi(tp, 1);
9342         } else if (netdev_mc_empty(dev)) {
9343                 /* Reject all multicast. */
9344                 tg3_set_multi(tp, 0);
9345         } else {
9346                 /* Accept one or more multicast(s). */
9347                 struct netdev_hw_addr *ha;
9348                 u32 mc_filter[4] = { 0, };
9349                 u32 regidx;
9350                 u32 bit;
9351                 u32 crc;
9352
9353                 netdev_for_each_mc_addr(ha, dev) {
9354                         crc = calc_crc(ha->addr, ETH_ALEN);
9355                         bit = ~crc & 0x7f;
9356                         regidx = (bit & 0x60) >> 5;
9357                         bit &= 0x1f;
9358                         mc_filter[regidx] |= (1 << bit);
9359                 }
9360
9361                 tw32(MAC_HASH_REG_0, mc_filter[0]);
9362                 tw32(MAC_HASH_REG_1, mc_filter[1]);
9363                 tw32(MAC_HASH_REG_2, mc_filter[2]);
9364                 tw32(MAC_HASH_REG_3, mc_filter[3]);
9365         }
9366
9367         if (rx_mode != tp->rx_mode) {
9368                 tp->rx_mode = rx_mode;
9369                 tw32_f(MAC_RX_MODE, rx_mode);
9370                 udelay(10);
9371         }
9372 }
9373
9374 static void tg3_set_rx_mode(struct net_device *dev)
9375 {
9376         struct tg3 *tp = netdev_priv(dev);
9377
9378         if (!netif_running(dev))
9379                 return;
9380
9381         tg3_full_lock(tp, 0);
9382         __tg3_set_rx_mode(dev);
9383         tg3_full_unlock(tp);
9384 }
9385
9386 #define TG3_REGDUMP_LEN         (32 * 1024)
9387
9388 static int tg3_get_regs_len(struct net_device *dev)
9389 {
9390         return TG3_REGDUMP_LEN;
9391 }
9392
9393 static void tg3_get_regs(struct net_device *dev,
9394                 struct ethtool_regs *regs, void *_p)
9395 {
9396         u32 *p = _p;
9397         struct tg3 *tp = netdev_priv(dev);
9398         u8 *orig_p = _p;
9399         int i;
9400
9401         regs->version = 0;
9402
9403         memset(p, 0, TG3_REGDUMP_LEN);
9404
9405         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9406                 return;
9407
9408         tg3_full_lock(tp, 0);
9409
9410 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
9411 #define GET_REG32_LOOP(base, len)               \
9412 do {    p = (u32 *)(orig_p + (base));           \
9413         for (i = 0; i < len; i += 4)            \
9414                 __GET_REG32((base) + i);        \
9415 } while (0)
9416 #define GET_REG32_1(reg)                        \
9417 do {    p = (u32 *)(orig_p + (reg));            \
9418         __GET_REG32((reg));                     \
9419 } while (0)
9420
9421         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9422         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9423         GET_REG32_LOOP(MAC_MODE, 0x4f0);
9424         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9425         GET_REG32_1(SNDDATAC_MODE);
9426         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9427         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9428         GET_REG32_1(SNDBDC_MODE);
9429         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9430         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9431         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9432         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9433         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9434         GET_REG32_1(RCVDCC_MODE);
9435         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9436         GET_REG32_LOOP(RCVCC_MODE, 0x14);
9437         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9438         GET_REG32_1(MBFREE_MODE);
9439         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9440         GET_REG32_LOOP(MEMARB_MODE, 0x10);
9441         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9442         GET_REG32_LOOP(RDMAC_MODE, 0x08);
9443         GET_REG32_LOOP(WDMAC_MODE, 0x08);
9444         GET_REG32_1(RX_CPU_MODE);
9445         GET_REG32_1(RX_CPU_STATE);
9446         GET_REG32_1(RX_CPU_PGMCTR);
9447         GET_REG32_1(RX_CPU_HWBKPT);
9448         GET_REG32_1(TX_CPU_MODE);
9449         GET_REG32_1(TX_CPU_STATE);
9450         GET_REG32_1(TX_CPU_PGMCTR);
9451         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9452         GET_REG32_LOOP(FTQ_RESET, 0x120);
9453         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9454         GET_REG32_1(DMAC_MODE);
9455         GET_REG32_LOOP(GRC_MODE, 0x4c);
9456         if (tp->tg3_flags & TG3_FLAG_NVRAM)
9457                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9458
9459 #undef __GET_REG32
9460 #undef GET_REG32_LOOP
9461 #undef GET_REG32_1
9462
9463         tg3_full_unlock(tp);
9464 }
9465
9466 static int tg3_get_eeprom_len(struct net_device *dev)
9467 {
9468         struct tg3 *tp = netdev_priv(dev);
9469
9470         return tp->nvram_size;
9471 }
9472
9473 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9474 {
9475         struct tg3 *tp = netdev_priv(dev);
9476         int ret;
9477         u8  *pd;
9478         u32 i, offset, len, b_offset, b_count;
9479         __be32 val;
9480
9481         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9482                 return -EINVAL;
9483
9484         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9485                 return -EAGAIN;
9486
9487         offset = eeprom->offset;
9488         len = eeprom->len;
9489         eeprom->len = 0;
9490
9491         eeprom->magic = TG3_EEPROM_MAGIC;
9492
9493         if (offset & 3) {
9494                 /* adjustments to start on required 4 byte boundary */
9495                 b_offset = offset & 3;
9496                 b_count = 4 - b_offset;
9497                 if (b_count > len) {
9498                         /* i.e. offset=1 len=2 */
9499                         b_count = len;
9500                 }
9501                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9502                 if (ret)
9503                         return ret;
9504                 memcpy(data, ((char *)&val) + b_offset, b_count);
9505                 len -= b_count;
9506                 offset += b_count;
9507                 eeprom->len += b_count;
9508         }
9509
9510         /* read bytes upto the last 4 byte boundary */
9511         pd = &data[eeprom->len];
9512         for (i = 0; i < (len - (len & 3)); i += 4) {
9513                 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9514                 if (ret) {
9515                         eeprom->len += i;
9516                         return ret;
9517                 }
9518                 memcpy(pd + i, &val, 4);
9519         }
9520         eeprom->len += i;
9521
9522         if (len & 3) {
9523                 /* read last bytes not ending on 4 byte boundary */
9524                 pd = &data[eeprom->len];
9525                 b_count = len & 3;
9526                 b_offset = offset + len - b_count;
9527                 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9528                 if (ret)
9529                         return ret;
9530                 memcpy(pd, &val, b_count);
9531                 eeprom->len += b_count;
9532         }
9533         return 0;
9534 }
9535
9536 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9537
9538 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9539 {
9540         struct tg3 *tp = netdev_priv(dev);
9541         int ret;
9542         u32 offset, len, b_offset, odd_len;
9543         u8 *buf;
9544         __be32 start, end;
9545
9546         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
9547                 return -EAGAIN;
9548
9549         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9550             eeprom->magic != TG3_EEPROM_MAGIC)
9551                 return -EINVAL;
9552
9553         offset = eeprom->offset;
9554         len = eeprom->len;
9555
9556         if ((b_offset = (offset & 3))) {
9557                 /* adjustments to start on required 4 byte boundary */
9558                 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9559                 if (ret)
9560                         return ret;
9561                 len += b_offset;
9562                 offset &= ~3;
9563                 if (len < 4)
9564                         len = 4;
9565         }
9566
9567         odd_len = 0;
9568         if (len & 3) {
9569                 /* adjustments to end on required 4 byte boundary */
9570                 odd_len = 1;
9571                 len = (len + 3) & ~3;
9572                 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9573                 if (ret)
9574                         return ret;
9575         }
9576
9577         buf = data;
9578         if (b_offset || odd_len) {
9579                 buf = kmalloc(len, GFP_KERNEL);
9580                 if (!buf)
9581                         return -ENOMEM;
9582                 if (b_offset)
9583                         memcpy(buf, &start, 4);
9584                 if (odd_len)
9585                         memcpy(buf+len-4, &end, 4);
9586                 memcpy(buf + b_offset, data, eeprom->len);
9587         }
9588
9589         ret = tg3_nvram_write_block(tp, offset, len, buf);
9590
9591         if (buf != data)
9592                 kfree(buf);
9593
9594         return ret;
9595 }
9596
9597 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9598 {
9599         struct tg3 *tp = netdev_priv(dev);
9600
9601         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9602                 struct phy_device *phydev;
9603                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9604                         return -EAGAIN;
9605                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9606                 return phy_ethtool_gset(phydev, cmd);
9607         }
9608
9609         cmd->supported = (SUPPORTED_Autoneg);
9610
9611         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9612                 cmd->supported |= (SUPPORTED_1000baseT_Half |
9613                                    SUPPORTED_1000baseT_Full);
9614
9615         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
9616                 cmd->supported |= (SUPPORTED_100baseT_Half |
9617                                   SUPPORTED_100baseT_Full |
9618                                   SUPPORTED_10baseT_Half |
9619                                   SUPPORTED_10baseT_Full |
9620                                   SUPPORTED_TP);
9621                 cmd->port = PORT_TP;
9622         } else {
9623                 cmd->supported |= SUPPORTED_FIBRE;
9624                 cmd->port = PORT_FIBRE;
9625         }
9626
9627         cmd->advertising = tp->link_config.advertising;
9628         if (netif_running(dev)) {
9629                 cmd->speed = tp->link_config.active_speed;
9630                 cmd->duplex = tp->link_config.active_duplex;
9631         }
9632         cmd->phy_address = tp->phy_addr;
9633         cmd->transceiver = XCVR_INTERNAL;
9634         cmd->autoneg = tp->link_config.autoneg;
9635         cmd->maxtxpkt = 0;
9636         cmd->maxrxpkt = 0;
9637         return 0;
9638 }
9639
9640 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9641 {
9642         struct tg3 *tp = netdev_priv(dev);
9643
9644         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9645                 struct phy_device *phydev;
9646                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9647                         return -EAGAIN;
9648                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9649                 return phy_ethtool_sset(phydev, cmd);
9650         }
9651
9652         if (cmd->autoneg != AUTONEG_ENABLE &&
9653             cmd->autoneg != AUTONEG_DISABLE)
9654                 return -EINVAL;
9655
9656         if (cmd->autoneg == AUTONEG_DISABLE &&
9657             cmd->duplex != DUPLEX_FULL &&
9658             cmd->duplex != DUPLEX_HALF)
9659                 return -EINVAL;
9660
9661         if (cmd->autoneg == AUTONEG_ENABLE) {
9662                 u32 mask = ADVERTISED_Autoneg |
9663                            ADVERTISED_Pause |
9664                            ADVERTISED_Asym_Pause;
9665
9666                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
9667                         mask |= ADVERTISED_1000baseT_Half |
9668                                 ADVERTISED_1000baseT_Full;
9669
9670                 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
9671                         mask |= ADVERTISED_100baseT_Half |
9672                                 ADVERTISED_100baseT_Full |
9673                                 ADVERTISED_10baseT_Half |
9674                                 ADVERTISED_10baseT_Full |
9675                                 ADVERTISED_TP;
9676                 else
9677                         mask |= ADVERTISED_FIBRE;
9678
9679                 if (cmd->advertising & ~mask)
9680                         return -EINVAL;
9681
9682                 mask &= (ADVERTISED_1000baseT_Half |
9683                          ADVERTISED_1000baseT_Full |
9684                          ADVERTISED_100baseT_Half |
9685                          ADVERTISED_100baseT_Full |
9686                          ADVERTISED_10baseT_Half |
9687                          ADVERTISED_10baseT_Full);
9688
9689                 cmd->advertising &= mask;
9690         } else {
9691                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
9692                         if (cmd->speed != SPEED_1000)
9693                                 return -EINVAL;
9694
9695                         if (cmd->duplex != DUPLEX_FULL)
9696                                 return -EINVAL;
9697                 } else {
9698                         if (cmd->speed != SPEED_100 &&
9699                             cmd->speed != SPEED_10)
9700                                 return -EINVAL;
9701                 }
9702         }
9703
9704         tg3_full_lock(tp, 0);
9705
9706         tp->link_config.autoneg = cmd->autoneg;
9707         if (cmd->autoneg == AUTONEG_ENABLE) {
9708                 tp->link_config.advertising = (cmd->advertising |
9709                                               ADVERTISED_Autoneg);
9710                 tp->link_config.speed = SPEED_INVALID;
9711                 tp->link_config.duplex = DUPLEX_INVALID;
9712         } else {
9713                 tp->link_config.advertising = 0;
9714                 tp->link_config.speed = cmd->speed;
9715                 tp->link_config.duplex = cmd->duplex;
9716         }
9717
9718         tp->link_config.orig_speed = tp->link_config.speed;
9719         tp->link_config.orig_duplex = tp->link_config.duplex;
9720         tp->link_config.orig_autoneg = tp->link_config.autoneg;
9721
9722         if (netif_running(dev))
9723                 tg3_setup_phy(tp, 1);
9724
9725         tg3_full_unlock(tp);
9726
9727         return 0;
9728 }
9729
9730 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9731 {
9732         struct tg3 *tp = netdev_priv(dev);
9733
9734         strcpy(info->driver, DRV_MODULE_NAME);
9735         strcpy(info->version, DRV_MODULE_VERSION);
9736         strcpy(info->fw_version, tp->fw_ver);
9737         strcpy(info->bus_info, pci_name(tp->pdev));
9738 }
9739
9740 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9741 {
9742         struct tg3 *tp = netdev_priv(dev);
9743
9744         if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9745             device_can_wakeup(&tp->pdev->dev))
9746                 wol->supported = WAKE_MAGIC;
9747         else
9748                 wol->supported = 0;
9749         wol->wolopts = 0;
9750         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9751             device_can_wakeup(&tp->pdev->dev))
9752                 wol->wolopts = WAKE_MAGIC;
9753         memset(&wol->sopass, 0, sizeof(wol->sopass));
9754 }
9755
9756 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9757 {
9758         struct tg3 *tp = netdev_priv(dev);
9759         struct device *dp = &tp->pdev->dev;
9760
9761         if (wol->wolopts & ~WAKE_MAGIC)
9762                 return -EINVAL;
9763         if ((wol->wolopts & WAKE_MAGIC) &&
9764             !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9765                 return -EINVAL;
9766
9767         spin_lock_bh(&tp->lock);
9768         if (wol->wolopts & WAKE_MAGIC) {
9769                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9770                 device_set_wakeup_enable(dp, true);
9771         } else {
9772                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9773                 device_set_wakeup_enable(dp, false);
9774         }
9775         spin_unlock_bh(&tp->lock);
9776
9777         return 0;
9778 }
9779
9780 static u32 tg3_get_msglevel(struct net_device *dev)
9781 {
9782         struct tg3 *tp = netdev_priv(dev);
9783         return tp->msg_enable;
9784 }
9785
9786 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9787 {
9788         struct tg3 *tp = netdev_priv(dev);
9789         tp->msg_enable = value;
9790 }
9791
9792 static int tg3_set_tso(struct net_device *dev, u32 value)
9793 {
9794         struct tg3 *tp = netdev_priv(dev);
9795
9796         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9797                 if (value)
9798                         return -EINVAL;
9799                 return 0;
9800         }
9801         if ((dev->features & NETIF_F_IPV6_CSUM) &&
9802             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9803              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9804                 if (value) {
9805                         dev->features |= NETIF_F_TSO6;
9806                         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9807                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9808                             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9809                              GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9810                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9811                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9812                                 dev->features |= NETIF_F_TSO_ECN;
9813                 } else
9814                         dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9815         }
9816         return ethtool_op_set_tso(dev, value);
9817 }
9818
9819 static int tg3_nway_reset(struct net_device *dev)
9820 {
9821         struct tg3 *tp = netdev_priv(dev);
9822         int r;
9823
9824         if (!netif_running(dev))
9825                 return -EAGAIN;
9826
9827         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
9828                 return -EINVAL;
9829
9830         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9831                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
9832                         return -EAGAIN;
9833                 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9834         } else {
9835                 u32 bmcr;
9836
9837                 spin_lock_bh(&tp->lock);
9838                 r = -EINVAL;
9839                 tg3_readphy(tp, MII_BMCR, &bmcr);
9840                 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9841                     ((bmcr & BMCR_ANENABLE) ||
9842                      (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
9843                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9844                                                    BMCR_ANENABLE);
9845                         r = 0;
9846                 }
9847                 spin_unlock_bh(&tp->lock);
9848         }
9849
9850         return r;
9851 }
9852
9853 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9854 {
9855         struct tg3 *tp = netdev_priv(dev);
9856
9857         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9858         ering->rx_mini_max_pending = 0;
9859         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9860                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9861         else
9862                 ering->rx_jumbo_max_pending = 0;
9863
9864         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9865
9866         ering->rx_pending = tp->rx_pending;
9867         ering->rx_mini_pending = 0;
9868         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9869                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9870         else
9871                 ering->rx_jumbo_pending = 0;
9872
9873         ering->tx_pending = tp->napi[0].tx_pending;
9874 }
9875
9876 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9877 {
9878         struct tg3 *tp = netdev_priv(dev);
9879         int i, irq_sync = 0, err = 0;
9880
9881         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9882             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9883             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9884             (ering->tx_pending <= MAX_SKB_FRAGS) ||
9885             ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9886              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9887                 return -EINVAL;
9888
9889         if (netif_running(dev)) {
9890                 tg3_phy_stop(tp);
9891                 tg3_netif_stop(tp);
9892                 irq_sync = 1;
9893         }
9894
9895         tg3_full_lock(tp, irq_sync);
9896
9897         tp->rx_pending = ering->rx_pending;
9898
9899         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9900             tp->rx_pending > 63)
9901                 tp->rx_pending = 63;
9902         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9903
9904         for (i = 0; i < tp->irq_max; i++)
9905                 tp->napi[i].tx_pending = ering->tx_pending;
9906
9907         if (netif_running(dev)) {
9908                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9909                 err = tg3_restart_hw(tp, 1);
9910                 if (!err)
9911                         tg3_netif_start(tp);
9912         }
9913
9914         tg3_full_unlock(tp);
9915
9916         if (irq_sync && !err)
9917                 tg3_phy_start(tp);
9918
9919         return err;
9920 }
9921
9922 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9923 {
9924         struct tg3 *tp = netdev_priv(dev);
9925
9926         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
9927
9928         if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
9929                 epause->rx_pause = 1;
9930         else
9931                 epause->rx_pause = 0;
9932
9933         if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
9934                 epause->tx_pause = 1;
9935         else
9936                 epause->tx_pause = 0;
9937 }
9938
9939 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
9940 {
9941         struct tg3 *tp = netdev_priv(dev);
9942         int err = 0;
9943
9944         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9945                 u32 newadv;
9946                 struct phy_device *phydev;
9947
9948                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9949
9950                 if (!(phydev->supported & SUPPORTED_Pause) ||
9951                     (!(phydev->supported & SUPPORTED_Asym_Pause) &&
9952                      ((epause->rx_pause && !epause->tx_pause) ||
9953                       (!epause->rx_pause && epause->tx_pause))))
9954                         return -EINVAL;
9955
9956                 tp->link_config.flowctrl = 0;
9957                 if (epause->rx_pause) {
9958                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
9959
9960                         if (epause->tx_pause) {
9961                                 tp->link_config.flowctrl |= FLOW_CTRL_TX;
9962                                 newadv = ADVERTISED_Pause;
9963                         } else
9964                                 newadv = ADVERTISED_Pause |
9965                                          ADVERTISED_Asym_Pause;
9966                 } else if (epause->tx_pause) {
9967                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
9968                         newadv = ADVERTISED_Asym_Pause;
9969                 } else
9970                         newadv = 0;
9971
9972                 if (epause->autoneg)
9973                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
9974                 else
9975                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
9976
9977                 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
9978                         u32 oldadv = phydev->advertising &
9979                                      (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
9980                         if (oldadv != newadv) {
9981                                 phydev->advertising &=
9982                                         ~(ADVERTISED_Pause |
9983                                           ADVERTISED_Asym_Pause);
9984                                 phydev->advertising |= newadv;
9985                                 if (phydev->autoneg) {
9986                                         /*
9987                                          * Always renegotiate the link to
9988                                          * inform our link partner of our
9989                                          * flow control settings, even if the
9990                                          * flow control is forced.  Let
9991                                          * tg3_adjust_link() do the final
9992                                          * flow control setup.
9993                                          */
9994                                         return phy_start_aneg(phydev);
9995                                 }
9996                         }
9997
9998                         if (!epause->autoneg)
9999                                 tg3_setup_flow_control(tp, 0, 0);
10000                 } else {
10001                         tp->link_config.orig_advertising &=
10002                                         ~(ADVERTISED_Pause |
10003                                           ADVERTISED_Asym_Pause);
10004                         tp->link_config.orig_advertising |= newadv;
10005                 }
10006         } else {
10007                 int irq_sync = 0;
10008
10009                 if (netif_running(dev)) {
10010                         tg3_netif_stop(tp);
10011                         irq_sync = 1;
10012                 }
10013
10014                 tg3_full_lock(tp, irq_sync);
10015
10016                 if (epause->autoneg)
10017                         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10018                 else
10019                         tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10020                 if (epause->rx_pause)
10021                         tp->link_config.flowctrl |= FLOW_CTRL_RX;
10022                 else
10023                         tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10024                 if (epause->tx_pause)
10025                         tp->link_config.flowctrl |= FLOW_CTRL_TX;
10026                 else
10027                         tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10028
10029                 if (netif_running(dev)) {
10030                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10031                         err = tg3_restart_hw(tp, 1);
10032                         if (!err)
10033                                 tg3_netif_start(tp);
10034                 }
10035
10036                 tg3_full_unlock(tp);
10037         }
10038
10039         return err;
10040 }
10041
10042 static u32 tg3_get_rx_csum(struct net_device *dev)
10043 {
10044         struct tg3 *tp = netdev_priv(dev);
10045         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10046 }
10047
10048 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10049 {
10050         struct tg3 *tp = netdev_priv(dev);
10051
10052         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10053                 if (data != 0)
10054                         return -EINVAL;
10055                 return 0;
10056         }
10057
10058         spin_lock_bh(&tp->lock);
10059         if (data)
10060                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10061         else
10062                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10063         spin_unlock_bh(&tp->lock);
10064
10065         return 0;
10066 }
10067
10068 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10069 {
10070         struct tg3 *tp = netdev_priv(dev);
10071
10072         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10073                 if (data != 0)
10074                         return -EINVAL;
10075                 return 0;
10076         }
10077
10078         if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10079                 ethtool_op_set_tx_ipv6_csum(dev, data);
10080         else
10081                 ethtool_op_set_tx_csum(dev, data);
10082
10083         return 0;
10084 }
10085
10086 static int tg3_get_sset_count(struct net_device *dev, int sset)
10087 {
10088         switch (sset) {
10089         case ETH_SS_TEST:
10090                 return TG3_NUM_TEST;
10091         case ETH_SS_STATS:
10092                 return TG3_NUM_STATS;
10093         default:
10094                 return -EOPNOTSUPP;
10095         }
10096 }
10097
10098 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
10099 {
10100         switch (stringset) {
10101         case ETH_SS_STATS:
10102                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
10103                 break;
10104         case ETH_SS_TEST:
10105                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
10106                 break;
10107         default:
10108                 WARN_ON(1);     /* we need a WARN() */
10109                 break;
10110         }
10111 }
10112
10113 static int tg3_phys_id(struct net_device *dev, u32 data)
10114 {
10115         struct tg3 *tp = netdev_priv(dev);
10116         int i;
10117
10118         if (!netif_running(tp->dev))
10119                 return -EAGAIN;
10120
10121         if (data == 0)
10122                 data = UINT_MAX / 2;
10123
10124         for (i = 0; i < (data * 2); i++) {
10125                 if ((i % 2) == 0)
10126                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10127                                            LED_CTRL_1000MBPS_ON |
10128                                            LED_CTRL_100MBPS_ON |
10129                                            LED_CTRL_10MBPS_ON |
10130                                            LED_CTRL_TRAFFIC_OVERRIDE |
10131                                            LED_CTRL_TRAFFIC_BLINK |
10132                                            LED_CTRL_TRAFFIC_LED);
10133
10134                 else
10135                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10136                                            LED_CTRL_TRAFFIC_OVERRIDE);
10137
10138                 if (msleep_interruptible(500))
10139                         break;
10140         }
10141         tw32(MAC_LED_CTRL, tp->led_ctrl);
10142         return 0;
10143 }
10144
10145 static void tg3_get_ethtool_stats(struct net_device *dev,
10146                                    struct ethtool_stats *estats, u64 *tmp_stats)
10147 {
10148         struct tg3 *tp = netdev_priv(dev);
10149         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10150 }
10151
10152 #define NVRAM_TEST_SIZE 0x100
10153 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE   0x14
10154 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE   0x18
10155 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE   0x1c
10156 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10157 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10158
10159 static int tg3_test_nvram(struct tg3 *tp)
10160 {
10161         u32 csum, magic;
10162         __be32 *buf;
10163         int i, j, k, err = 0, size;
10164
10165         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10166                 return 0;
10167
10168         if (tg3_nvram_read(tp, 0, &magic) != 0)
10169                 return -EIO;
10170
10171         if (magic == TG3_EEPROM_MAGIC)
10172                 size = NVRAM_TEST_SIZE;
10173         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10174                 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10175                     TG3_EEPROM_SB_FORMAT_1) {
10176                         switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10177                         case TG3_EEPROM_SB_REVISION_0:
10178                                 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10179                                 break;
10180                         case TG3_EEPROM_SB_REVISION_2:
10181                                 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10182                                 break;
10183                         case TG3_EEPROM_SB_REVISION_3:
10184                                 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10185                                 break;
10186                         default:
10187                                 return 0;
10188                         }
10189                 } else
10190                         return 0;
10191         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10192                 size = NVRAM_SELFBOOT_HW_SIZE;
10193         else
10194                 return -EIO;
10195
10196         buf = kmalloc(size, GFP_KERNEL);
10197         if (buf == NULL)
10198                 return -ENOMEM;
10199
10200         err = -EIO;
10201         for (i = 0, j = 0; i < size; i += 4, j++) {
10202                 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10203                 if (err)
10204                         break;
10205         }
10206         if (i < size)
10207                 goto out;
10208
10209         /* Selfboot format */
10210         magic = be32_to_cpu(buf[0]);
10211         if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10212             TG3_EEPROM_MAGIC_FW) {
10213                 u8 *buf8 = (u8 *) buf, csum8 = 0;
10214
10215                 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10216                     TG3_EEPROM_SB_REVISION_2) {
10217                         /* For rev 2, the csum doesn't include the MBA. */
10218                         for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10219                                 csum8 += buf8[i];
10220                         for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10221                                 csum8 += buf8[i];
10222                 } else {
10223                         for (i = 0; i < size; i++)
10224                                 csum8 += buf8[i];
10225                 }
10226
10227                 if (csum8 == 0) {
10228                         err = 0;
10229                         goto out;
10230                 }
10231
10232                 err = -EIO;
10233                 goto out;
10234         }
10235
10236         if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10237             TG3_EEPROM_MAGIC_HW) {
10238                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10239                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10240                 u8 *buf8 = (u8 *) buf;
10241
10242                 /* Separate the parity bits and the data bytes.  */
10243                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10244                         if ((i == 0) || (i == 8)) {
10245                                 int l;
10246                                 u8 msk;
10247
10248                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10249                                         parity[k++] = buf8[i] & msk;
10250                                 i++;
10251                         } else if (i == 16) {
10252                                 int l;
10253                                 u8 msk;
10254
10255                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10256                                         parity[k++] = buf8[i] & msk;
10257                                 i++;
10258
10259                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10260                                         parity[k++] = buf8[i] & msk;
10261                                 i++;
10262                         }
10263                         data[j++] = buf8[i];
10264                 }
10265
10266                 err = -EIO;
10267                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10268                         u8 hw8 = hweight8(data[i]);
10269
10270                         if ((hw8 & 0x1) && parity[i])
10271                                 goto out;
10272                         else if (!(hw8 & 0x1) && !parity[i])
10273                                 goto out;
10274                 }
10275                 err = 0;
10276                 goto out;
10277         }
10278
10279         /* Bootstrap checksum at offset 0x10 */
10280         csum = calc_crc((unsigned char *) buf, 0x10);
10281         if (csum != be32_to_cpu(buf[0x10/4]))
10282                 goto out;
10283
10284         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10285         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10286         if (csum != be32_to_cpu(buf[0xfc/4]))
10287                 goto out;
10288
10289         err = 0;
10290
10291 out:
10292         kfree(buf);
10293         return err;
10294 }
10295
10296 #define TG3_SERDES_TIMEOUT_SEC  2
10297 #define TG3_COPPER_TIMEOUT_SEC  6
10298
10299 static int tg3_test_link(struct tg3 *tp)
10300 {
10301         int i, max;
10302
10303         if (!netif_running(tp->dev))
10304                 return -ENODEV;
10305
10306         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
10307                 max = TG3_SERDES_TIMEOUT_SEC;
10308         else
10309                 max = TG3_COPPER_TIMEOUT_SEC;
10310
10311         for (i = 0; i < max; i++) {
10312                 if (netif_carrier_ok(tp->dev))
10313                         return 0;
10314
10315                 if (msleep_interruptible(1000))
10316                         break;
10317         }
10318
10319         return -EIO;
10320 }
10321
10322 /* Only test the commonly used registers */
10323 static int tg3_test_registers(struct tg3 *tp)
10324 {
10325         int i, is_5705, is_5750;
10326         u32 offset, read_mask, write_mask, val, save_val, read_val;
10327         static struct {
10328                 u16 offset;
10329                 u16 flags;
10330 #define TG3_FL_5705     0x1
10331 #define TG3_FL_NOT_5705 0x2
10332 #define TG3_FL_NOT_5788 0x4
10333 #define TG3_FL_NOT_5750 0x8
10334                 u32 read_mask;
10335                 u32 write_mask;
10336         } reg_tbl[] = {
10337                 /* MAC Control Registers */
10338                 { MAC_MODE, TG3_FL_NOT_5705,
10339                         0x00000000, 0x00ef6f8c },
10340                 { MAC_MODE, TG3_FL_5705,
10341                         0x00000000, 0x01ef6b8c },
10342                 { MAC_STATUS, TG3_FL_NOT_5705,
10343                         0x03800107, 0x00000000 },
10344                 { MAC_STATUS, TG3_FL_5705,
10345                         0x03800100, 0x00000000 },
10346                 { MAC_ADDR_0_HIGH, 0x0000,
10347                         0x00000000, 0x0000ffff },
10348                 { MAC_ADDR_0_LOW, 0x0000,
10349                         0x00000000, 0xffffffff },
10350                 { MAC_RX_MTU_SIZE, 0x0000,
10351                         0x00000000, 0x0000ffff },
10352                 { MAC_TX_MODE, 0x0000,
10353                         0x00000000, 0x00000070 },
10354                 { MAC_TX_LENGTHS, 0x0000,
10355                         0x00000000, 0x00003fff },
10356                 { MAC_RX_MODE, TG3_FL_NOT_5705,
10357                         0x00000000, 0x000007fc },
10358                 { MAC_RX_MODE, TG3_FL_5705,
10359                         0x00000000, 0x000007dc },
10360                 { MAC_HASH_REG_0, 0x0000,
10361                         0x00000000, 0xffffffff },
10362                 { MAC_HASH_REG_1, 0x0000,
10363                         0x00000000, 0xffffffff },
10364                 { MAC_HASH_REG_2, 0x0000,
10365                         0x00000000, 0xffffffff },
10366                 { MAC_HASH_REG_3, 0x0000,
10367                         0x00000000, 0xffffffff },
10368
10369                 /* Receive Data and Receive BD Initiator Control Registers. */
10370                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10371                         0x00000000, 0xffffffff },
10372                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10373                         0x00000000, 0xffffffff },
10374                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10375                         0x00000000, 0x00000003 },
10376                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10377                         0x00000000, 0xffffffff },
10378                 { RCVDBDI_STD_BD+0, 0x0000,
10379                         0x00000000, 0xffffffff },
10380                 { RCVDBDI_STD_BD+4, 0x0000,
10381                         0x00000000, 0xffffffff },
10382                 { RCVDBDI_STD_BD+8, 0x0000,
10383                         0x00000000, 0xffff0002 },
10384                 { RCVDBDI_STD_BD+0xc, 0x0000,
10385                         0x00000000, 0xffffffff },
10386
10387                 /* Receive BD Initiator Control Registers. */
10388                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10389                         0x00000000, 0xffffffff },
10390                 { RCVBDI_STD_THRESH, TG3_FL_5705,
10391                         0x00000000, 0x000003ff },
10392                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10393                         0x00000000, 0xffffffff },
10394
10395                 /* Host Coalescing Control Registers. */
10396                 { HOSTCC_MODE, TG3_FL_NOT_5705,
10397                         0x00000000, 0x00000004 },
10398                 { HOSTCC_MODE, TG3_FL_5705,
10399                         0x00000000, 0x000000f6 },
10400                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10401                         0x00000000, 0xffffffff },
10402                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10403                         0x00000000, 0x000003ff },
10404                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10405                         0x00000000, 0xffffffff },
10406                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10407                         0x00000000, 0x000003ff },
10408                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10409                         0x00000000, 0xffffffff },
10410                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10411                         0x00000000, 0x000000ff },
10412                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10413                         0x00000000, 0xffffffff },
10414                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10415                         0x00000000, 0x000000ff },
10416                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10417                         0x00000000, 0xffffffff },
10418                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10419                         0x00000000, 0xffffffff },
10420                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10421                         0x00000000, 0xffffffff },
10422                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10423                         0x00000000, 0x000000ff },
10424                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10425                         0x00000000, 0xffffffff },
10426                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10427                         0x00000000, 0x000000ff },
10428                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10429                         0x00000000, 0xffffffff },
10430                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10431                         0x00000000, 0xffffffff },
10432                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10433                         0x00000000, 0xffffffff },
10434                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10435                         0x00000000, 0xffffffff },
10436                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10437                         0x00000000, 0xffffffff },
10438                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10439                         0xffffffff, 0x00000000 },
10440                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10441                         0xffffffff, 0x00000000 },
10442
10443                 /* Buffer Manager Control Registers. */
10444                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10445                         0x00000000, 0x007fff80 },
10446                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10447                         0x00000000, 0x007fffff },
10448                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10449                         0x00000000, 0x0000003f },
10450                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10451                         0x00000000, 0x000001ff },
10452                 { BUFMGR_MB_HIGH_WATER, 0x0000,
10453                         0x00000000, 0x000001ff },
10454                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10455                         0xffffffff, 0x00000000 },
10456                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10457                         0xffffffff, 0x00000000 },
10458
10459                 /* Mailbox Registers */
10460                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10461                         0x00000000, 0x000001ff },
10462                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10463                         0x00000000, 0x000001ff },
10464                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10465                         0x00000000, 0x000007ff },
10466                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10467                         0x00000000, 0x000001ff },
10468
10469                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10470         };
10471
10472         is_5705 = is_5750 = 0;
10473         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10474                 is_5705 = 1;
10475                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10476                         is_5750 = 1;
10477         }
10478
10479         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10480                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10481                         continue;
10482
10483                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10484                         continue;
10485
10486                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10487                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
10488                         continue;
10489
10490                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10491                         continue;
10492
10493                 offset = (u32) reg_tbl[i].offset;
10494                 read_mask = reg_tbl[i].read_mask;
10495                 write_mask = reg_tbl[i].write_mask;
10496
10497                 /* Save the original register content */
10498                 save_val = tr32(offset);
10499
10500                 /* Determine the read-only value. */
10501                 read_val = save_val & read_mask;
10502
10503                 /* Write zero to the register, then make sure the read-only bits
10504                  * are not changed and the read/write bits are all zeros.
10505                  */
10506                 tw32(offset, 0);
10507
10508                 val = tr32(offset);
10509
10510                 /* Test the read-only and read/write bits. */
10511                 if (((val & read_mask) != read_val) || (val & write_mask))
10512                         goto out;
10513
10514                 /* Write ones to all the bits defined by RdMask and WrMask, then
10515                  * make sure the read-only bits are not changed and the
10516                  * read/write bits are all ones.
10517                  */
10518                 tw32(offset, read_mask | write_mask);
10519
10520                 val = tr32(offset);
10521
10522                 /* Test the read-only bits. */
10523                 if ((val & read_mask) != read_val)
10524                         goto out;
10525
10526                 /* Test the read/write bits. */
10527                 if ((val & write_mask) != write_mask)
10528                         goto out;
10529
10530                 tw32(offset, save_val);
10531         }
10532
10533         return 0;
10534
10535 out:
10536         if (netif_msg_hw(tp))
10537                 netdev_err(tp->dev,
10538                            "Register test failed at offset %x\n", offset);
10539         tw32(offset, save_val);
10540         return -EIO;
10541 }
10542
10543 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10544 {
10545         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10546         int i;
10547         u32 j;
10548
10549         for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10550                 for (j = 0; j < len; j += 4) {
10551                         u32 val;
10552
10553                         tg3_write_mem(tp, offset + j, test_pattern[i]);
10554                         tg3_read_mem(tp, offset + j, &val);
10555                         if (val != test_pattern[i])
10556                                 return -EIO;
10557                 }
10558         }
10559         return 0;
10560 }
10561
10562 static int tg3_test_memory(struct tg3 *tp)
10563 {
10564         static struct mem_entry {
10565                 u32 offset;
10566                 u32 len;
10567         } mem_tbl_570x[] = {
10568                 { 0x00000000, 0x00b50},
10569                 { 0x00002000, 0x1c000},
10570                 { 0xffffffff, 0x00000}
10571         }, mem_tbl_5705[] = {
10572                 { 0x00000100, 0x0000c},
10573                 { 0x00000200, 0x00008},
10574                 { 0x00004000, 0x00800},
10575                 { 0x00006000, 0x01000},
10576                 { 0x00008000, 0x02000},
10577                 { 0x00010000, 0x0e000},
10578                 { 0xffffffff, 0x00000}
10579         }, mem_tbl_5755[] = {
10580                 { 0x00000200, 0x00008},
10581                 { 0x00004000, 0x00800},
10582                 { 0x00006000, 0x00800},
10583                 { 0x00008000, 0x02000},
10584                 { 0x00010000, 0x0c000},
10585                 { 0xffffffff, 0x00000}
10586         }, mem_tbl_5906[] = {
10587                 { 0x00000200, 0x00008},
10588                 { 0x00004000, 0x00400},
10589                 { 0x00006000, 0x00400},
10590                 { 0x00008000, 0x01000},
10591                 { 0x00010000, 0x01000},
10592                 { 0xffffffff, 0x00000}
10593         }, mem_tbl_5717[] = {
10594                 { 0x00000200, 0x00008},
10595                 { 0x00010000, 0x0a000},
10596                 { 0x00020000, 0x13c00},
10597                 { 0xffffffff, 0x00000}
10598         }, mem_tbl_57765[] = {
10599                 { 0x00000200, 0x00008},
10600                 { 0x00004000, 0x00800},
10601                 { 0x00006000, 0x09800},
10602                 { 0x00010000, 0x0a000},
10603                 { 0xffffffff, 0x00000}
10604         };
10605         struct mem_entry *mem_tbl;
10606         int err = 0;
10607         int i;
10608
10609         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
10610             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
10611                 mem_tbl = mem_tbl_5717;
10612         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10613                 mem_tbl = mem_tbl_57765;
10614         else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10615                 mem_tbl = mem_tbl_5755;
10616         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10617                 mem_tbl = mem_tbl_5906;
10618         else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10619                 mem_tbl = mem_tbl_5705;
10620         else
10621                 mem_tbl = mem_tbl_570x;
10622
10623         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10624                 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
10625                 if (err)
10626                         break;
10627         }
10628
10629         return err;
10630 }
10631
10632 #define TG3_MAC_LOOPBACK        0
10633 #define TG3_PHY_LOOPBACK        1
10634
10635 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10636 {
10637         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10638         u32 desc_idx, coal_now;
10639         struct sk_buff *skb, *rx_skb;
10640         u8 *tx_data;
10641         dma_addr_t map;
10642         int num_pkts, tx_len, rx_len, i, err;
10643         struct tg3_rx_buffer_desc *desc;
10644         struct tg3_napi *tnapi, *rnapi;
10645         struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
10646
10647         tnapi = &tp->napi[0];
10648         rnapi = &tp->napi[0];
10649         if (tp->irq_cnt > 1) {
10650                 rnapi = &tp->napi[1];
10651                 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
10652                         tnapi = &tp->napi[1];
10653         }
10654         coal_now = tnapi->coal_now | rnapi->coal_now;
10655
10656         if (loopback_mode == TG3_MAC_LOOPBACK) {
10657                 /* HW errata - mac loopback fails in some cases on 5780.
10658                  * Normal traffic and PHY loopback are not affected by
10659                  * errata.
10660                  */
10661                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10662                         return 0;
10663
10664                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10665                            MAC_MODE_PORT_INT_LPBACK;
10666                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10667                         mac_mode |= MAC_MODE_LINK_POLARITY;
10668                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
10669                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10670                 else
10671                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10672                 tw32(MAC_MODE, mac_mode);
10673         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10674                 u32 val;
10675
10676                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10677                         tg3_phy_fet_toggle_apd(tp, false);
10678                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10679                 } else
10680                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10681
10682                 tg3_phy_toggle_automdix(tp, 0);
10683
10684                 tg3_writephy(tp, MII_BMCR, val);
10685                 udelay(40);
10686
10687                 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10688                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
10689                         tg3_writephy(tp, MII_TG3_FET_PTEST,
10690                                      MII_TG3_FET_PTEST_FRC_TX_LINK |
10691                                      MII_TG3_FET_PTEST_FRC_TX_LOCK);
10692                         /* The write needs to be flushed for the AC131 */
10693                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
10694                                 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
10695                         mac_mode |= MAC_MODE_PORT_MODE_MII;
10696                 } else
10697                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
10698
10699                 /* reset to prevent losing 1st rx packet intermittently */
10700                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10701                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10702                         udelay(10);
10703                         tw32_f(MAC_RX_MODE, tp->rx_mode);
10704                 }
10705                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10706                         u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
10707                         if (masked_phy_id == TG3_PHY_ID_BCM5401)
10708                                 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10709                         else if (masked_phy_id == TG3_PHY_ID_BCM5411)
10710                                 mac_mode |= MAC_MODE_LINK_POLARITY;
10711                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
10712                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10713                 }
10714                 tw32(MAC_MODE, mac_mode);
10715         } else {
10716                 return -EINVAL;
10717         }
10718
10719         err = -EIO;
10720
10721         tx_len = 1514;
10722         skb = netdev_alloc_skb(tp->dev, tx_len);
10723         if (!skb)
10724                 return -ENOMEM;
10725
10726         tx_data = skb_put(skb, tx_len);
10727         memcpy(tx_data, tp->dev->dev_addr, 6);
10728         memset(tx_data + 6, 0x0, 8);
10729
10730         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10731
10732         for (i = 14; i < tx_len; i++)
10733                 tx_data[i] = (u8) (i & 0xff);
10734
10735         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10736         if (pci_dma_mapping_error(tp->pdev, map)) {
10737                 dev_kfree_skb(skb);
10738                 return -EIO;
10739         }
10740
10741         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10742                rnapi->coal_now);
10743
10744         udelay(10);
10745
10746         rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10747
10748         num_pkts = 0;
10749
10750         tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10751
10752         tnapi->tx_prod++;
10753         num_pkts++;
10754
10755         tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10756         tr32_mailbox(tnapi->prodmbox);
10757
10758         udelay(10);
10759
10760         /* 350 usec to allow enough time on some 10/100 Mbps devices.  */
10761         for (i = 0; i < 35; i++) {
10762                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10763                        coal_now);
10764
10765                 udelay(10);
10766
10767                 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10768                 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10769                 if ((tx_idx == tnapi->tx_prod) &&
10770                     (rx_idx == (rx_start_idx + num_pkts)))
10771                         break;
10772         }
10773
10774         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10775         dev_kfree_skb(skb);
10776
10777         if (tx_idx != tnapi->tx_prod)
10778                 goto out;
10779
10780         if (rx_idx != rx_start_idx + num_pkts)
10781                 goto out;
10782
10783         desc = &rnapi->rx_rcb[rx_start_idx];
10784         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10785         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10786         if (opaque_key != RXD_OPAQUE_RING_STD)
10787                 goto out;
10788
10789         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10790             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10791                 goto out;
10792
10793         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10794         if (rx_len != tx_len)
10795                 goto out;
10796
10797         rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10798
10799         map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10800         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10801
10802         for (i = 14; i < tx_len; i++) {
10803                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10804                         goto out;
10805         }
10806         err = 0;
10807
10808         /* tg3_free_rings will unmap and free the rx_skb */
10809 out:
10810         return err;
10811 }
10812
10813 #define TG3_MAC_LOOPBACK_FAILED         1
10814 #define TG3_PHY_LOOPBACK_FAILED         2
10815 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
10816                                          TG3_PHY_LOOPBACK_FAILED)
10817
10818 static int tg3_test_loopback(struct tg3 *tp)
10819 {
10820         int err = 0;
10821         u32 cpmuctrl = 0;
10822
10823         if (!netif_running(tp->dev))
10824                 return TG3_LOOPBACK_FAILED;
10825
10826         err = tg3_reset_hw(tp, 1);
10827         if (err)
10828                 return TG3_LOOPBACK_FAILED;
10829
10830         /* Turn off gphy autopowerdown. */
10831         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10832                 tg3_phy_toggle_apd(tp, false);
10833
10834         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10835                 int i;
10836                 u32 status;
10837
10838                 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10839
10840                 /* Wait for up to 40 microseconds to acquire lock. */
10841                 for (i = 0; i < 4; i++) {
10842                         status = tr32(TG3_CPMU_MUTEX_GNT);
10843                         if (status == CPMU_MUTEX_GNT_DRIVER)
10844                                 break;
10845                         udelay(10);
10846                 }
10847
10848                 if (status != CPMU_MUTEX_GNT_DRIVER)
10849                         return TG3_LOOPBACK_FAILED;
10850
10851                 /* Turn off link-based power management. */
10852                 cpmuctrl = tr32(TG3_CPMU_CTRL);
10853                 tw32(TG3_CPMU_CTRL,
10854                      cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10855                                   CPMU_CTRL_LINK_AWARE_MODE));
10856         }
10857
10858         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10859                 err |= TG3_MAC_LOOPBACK_FAILED;
10860
10861         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10862                 tw32(TG3_CPMU_CTRL, cpmuctrl);
10863
10864                 /* Release the mutex */
10865                 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10866         }
10867
10868         if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10869             !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10870                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10871                         err |= TG3_PHY_LOOPBACK_FAILED;
10872         }
10873
10874         /* Re-enable gphy autopowerdown. */
10875         if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
10876                 tg3_phy_toggle_apd(tp, true);
10877
10878         return err;
10879 }
10880
10881 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10882                           u64 *data)
10883 {
10884         struct tg3 *tp = netdev_priv(dev);
10885
10886         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10887                 tg3_set_power_state(tp, PCI_D0);
10888
10889         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10890
10891         if (tg3_test_nvram(tp) != 0) {
10892                 etest->flags |= ETH_TEST_FL_FAILED;
10893                 data[0] = 1;
10894         }
10895         if (tg3_test_link(tp) != 0) {
10896                 etest->flags |= ETH_TEST_FL_FAILED;
10897                 data[1] = 1;
10898         }
10899         if (etest->flags & ETH_TEST_FL_OFFLINE) {
10900                 int err, err2 = 0, irq_sync = 0;
10901
10902                 if (netif_running(dev)) {
10903                         tg3_phy_stop(tp);
10904                         tg3_netif_stop(tp);
10905                         irq_sync = 1;
10906                 }
10907
10908                 tg3_full_lock(tp, irq_sync);
10909
10910                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10911                 err = tg3_nvram_lock(tp);
10912                 tg3_halt_cpu(tp, RX_CPU_BASE);
10913                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10914                         tg3_halt_cpu(tp, TX_CPU_BASE);
10915                 if (!err)
10916                         tg3_nvram_unlock(tp);
10917
10918                 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
10919                         tg3_phy_reset(tp);
10920
10921                 if (tg3_test_registers(tp) != 0) {
10922                         etest->flags |= ETH_TEST_FL_FAILED;
10923                         data[2] = 1;
10924                 }
10925                 if (tg3_test_memory(tp) != 0) {
10926                         etest->flags |= ETH_TEST_FL_FAILED;
10927                         data[3] = 1;
10928                 }
10929                 if ((data[4] = tg3_test_loopback(tp)) != 0)
10930                         etest->flags |= ETH_TEST_FL_FAILED;
10931
10932                 tg3_full_unlock(tp);
10933
10934                 if (tg3_test_interrupt(tp) != 0) {
10935                         etest->flags |= ETH_TEST_FL_FAILED;
10936                         data[5] = 1;
10937                 }
10938
10939                 tg3_full_lock(tp, 0);
10940
10941                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10942                 if (netif_running(dev)) {
10943                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10944                         err2 = tg3_restart_hw(tp, 1);
10945                         if (!err2)
10946                                 tg3_netif_start(tp);
10947                 }
10948
10949                 tg3_full_unlock(tp);
10950
10951                 if (irq_sync && !err2)
10952                         tg3_phy_start(tp);
10953         }
10954         if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10955                 tg3_set_power_state(tp, PCI_D3hot);
10956
10957 }
10958
10959 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
10960 {
10961         struct mii_ioctl_data *data = if_mii(ifr);
10962         struct tg3 *tp = netdev_priv(dev);
10963         int err;
10964
10965         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10966                 struct phy_device *phydev;
10967                 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
10968                         return -EAGAIN;
10969                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10970                 return phy_mii_ioctl(phydev, ifr, cmd);
10971         }
10972
10973         switch (cmd) {
10974         case SIOCGMIIPHY:
10975                 data->phy_id = tp->phy_addr;
10976
10977                 /* fallthru */
10978         case SIOCGMIIREG: {
10979                 u32 mii_regval;
10980
10981                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10982                         break;                  /* We have no PHY */
10983
10984                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10985                         return -EAGAIN;
10986
10987                 spin_lock_bh(&tp->lock);
10988                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
10989                 spin_unlock_bh(&tp->lock);
10990
10991                 data->val_out = mii_regval;
10992
10993                 return err;
10994         }
10995
10996         case SIOCSMIIREG:
10997                 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
10998                         break;                  /* We have no PHY */
10999
11000                 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11001                         return -EAGAIN;
11002
11003                 spin_lock_bh(&tp->lock);
11004                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11005                 spin_unlock_bh(&tp->lock);
11006
11007                 return err;
11008
11009         default:
11010                 /* do nothing */
11011                 break;
11012         }
11013         return -EOPNOTSUPP;
11014 }
11015
11016 #if TG3_VLAN_TAG_USED
11017 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11018 {
11019         struct tg3 *tp = netdev_priv(dev);
11020
11021         if (!netif_running(dev)) {
11022                 tp->vlgrp = grp;
11023                 return;
11024         }
11025
11026         tg3_netif_stop(tp);
11027
11028         tg3_full_lock(tp, 0);
11029
11030         tp->vlgrp = grp;
11031
11032         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11033         __tg3_set_rx_mode(dev);
11034
11035         tg3_netif_start(tp);
11036
11037         tg3_full_unlock(tp);
11038 }
11039 #endif
11040
11041 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11042 {
11043         struct tg3 *tp = netdev_priv(dev);
11044
11045         memcpy(ec, &tp->coal, sizeof(*ec));
11046         return 0;
11047 }
11048
11049 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11050 {
11051         struct tg3 *tp = netdev_priv(dev);
11052         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11053         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11054
11055         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11056                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11057                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11058                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11059                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11060         }
11061
11062         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11063             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11064             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11065             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11066             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11067             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11068             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11069             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11070             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11071             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11072                 return -EINVAL;
11073
11074         /* No rx interrupts will be generated if both are zero */
11075         if ((ec->rx_coalesce_usecs == 0) &&
11076             (ec->rx_max_coalesced_frames == 0))
11077                 return -EINVAL;
11078
11079         /* No tx interrupts will be generated if both are zero */
11080         if ((ec->tx_coalesce_usecs == 0) &&
11081             (ec->tx_max_coalesced_frames == 0))
11082                 return -EINVAL;
11083
11084         /* Only copy relevant parameters, ignore all others. */
11085         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11086         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11087         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11088         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11089         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11090         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11091         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11092         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11093         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11094
11095         if (netif_running(dev)) {
11096                 tg3_full_lock(tp, 0);
11097                 __tg3_set_coalesce(tp, &tp->coal);
11098                 tg3_full_unlock(tp);
11099         }
11100         return 0;
11101 }
11102
11103 static const struct ethtool_ops tg3_ethtool_ops = {
11104         .get_settings           = tg3_get_settings,
11105         .set_settings           = tg3_set_settings,
11106         .get_drvinfo            = tg3_get_drvinfo,
11107         .get_regs_len           = tg3_get_regs_len,
11108         .get_regs               = tg3_get_regs,
11109         .get_wol                = tg3_get_wol,
11110         .set_wol                = tg3_set_wol,
11111         .get_msglevel           = tg3_get_msglevel,
11112         .set_msglevel           = tg3_set_msglevel,
11113         .nway_reset             = tg3_nway_reset,
11114         .get_link               = ethtool_op_get_link,
11115         .get_eeprom_len         = tg3_get_eeprom_len,
11116         .get_eeprom             = tg3_get_eeprom,
11117         .set_eeprom             = tg3_set_eeprom,
11118         .get_ringparam          = tg3_get_ringparam,
11119         .set_ringparam          = tg3_set_ringparam,
11120         .get_pauseparam         = tg3_get_pauseparam,
11121         .set_pauseparam         = tg3_set_pauseparam,
11122         .get_rx_csum            = tg3_get_rx_csum,
11123         .set_rx_csum            = tg3_set_rx_csum,
11124         .set_tx_csum            = tg3_set_tx_csum,
11125         .set_sg                 = ethtool_op_set_sg,
11126         .set_tso                = tg3_set_tso,
11127         .self_test              = tg3_self_test,
11128         .get_strings            = tg3_get_strings,
11129         .phys_id                = tg3_phys_id,
11130         .get_ethtool_stats      = tg3_get_ethtool_stats,
11131         .get_coalesce           = tg3_get_coalesce,
11132         .set_coalesce           = tg3_set_coalesce,
11133         .get_sset_count         = tg3_get_sset_count,
11134 };
11135
11136 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11137 {
11138         u32 cursize, val, magic;
11139
11140         tp->nvram_size = EEPROM_CHIP_SIZE;
11141
11142         if (tg3_nvram_read(tp, 0, &magic) != 0)
11143                 return;
11144
11145         if ((magic != TG3_EEPROM_MAGIC) &&
11146             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11147             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11148                 return;
11149
11150         /*
11151          * Size the chip by reading offsets at increasing powers of two.
11152          * When we encounter our validation signature, we know the addressing
11153          * has wrapped around, and thus have our chip size.
11154          */
11155         cursize = 0x10;
11156
11157         while (cursize < tp->nvram_size) {
11158                 if (tg3_nvram_read(tp, cursize, &val) != 0)
11159                         return;
11160
11161                 if (val == magic)
11162                         break;
11163
11164                 cursize <<= 1;
11165         }
11166
11167         tp->nvram_size = cursize;
11168 }
11169
11170 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11171 {
11172         u32 val;
11173
11174         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11175             tg3_nvram_read(tp, 0, &val) != 0)
11176                 return;
11177
11178         /* Selfboot format */
11179         if (val != TG3_EEPROM_MAGIC) {
11180                 tg3_get_eeprom_size(tp);
11181                 return;
11182         }
11183
11184         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11185                 if (val != 0) {
11186                         /* This is confusing.  We want to operate on the
11187                          * 16-bit value at offset 0xf2.  The tg3_nvram_read()
11188                          * call will read from NVRAM and byteswap the data
11189                          * according to the byteswapping settings for all
11190                          * other register accesses.  This ensures the data we
11191                          * want will always reside in the lower 16-bits.
11192                          * However, the data in NVRAM is in LE format, which
11193                          * means the data from the NVRAM read will always be
11194                          * opposite the endianness of the CPU.  The 16-bit
11195                          * byteswap then brings the data to CPU endianness.
11196                          */
11197                         tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11198                         return;
11199                 }
11200         }
11201         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11202 }
11203
11204 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11205 {
11206         u32 nvcfg1;
11207
11208         nvcfg1 = tr32(NVRAM_CFG1);
11209         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11210                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11211         } else {
11212                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11213                 tw32(NVRAM_CFG1, nvcfg1);
11214         }
11215
11216         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11217             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11218                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11219                 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11220                         tp->nvram_jedecnum = JEDEC_ATMEL;
11221                         tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11222                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11223                         break;
11224                 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11225                         tp->nvram_jedecnum = JEDEC_ATMEL;
11226                         tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11227                         break;
11228                 case FLASH_VENDOR_ATMEL_EEPROM:
11229                         tp->nvram_jedecnum = JEDEC_ATMEL;
11230                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11231                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11232                         break;
11233                 case FLASH_VENDOR_ST:
11234                         tp->nvram_jedecnum = JEDEC_ST;
11235                         tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11236                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11237                         break;
11238                 case FLASH_VENDOR_SAIFUN:
11239                         tp->nvram_jedecnum = JEDEC_SAIFUN;
11240                         tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11241                         break;
11242                 case FLASH_VENDOR_SST_SMALL:
11243                 case FLASH_VENDOR_SST_LARGE:
11244                         tp->nvram_jedecnum = JEDEC_SST;
11245                         tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11246                         break;
11247                 }
11248         } else {
11249                 tp->nvram_jedecnum = JEDEC_ATMEL;
11250                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11251                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11252         }
11253 }
11254
11255 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11256 {
11257         switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11258         case FLASH_5752PAGE_SIZE_256:
11259                 tp->nvram_pagesize = 256;
11260                 break;
11261         case FLASH_5752PAGE_SIZE_512:
11262                 tp->nvram_pagesize = 512;
11263                 break;
11264         case FLASH_5752PAGE_SIZE_1K:
11265                 tp->nvram_pagesize = 1024;
11266                 break;
11267         case FLASH_5752PAGE_SIZE_2K:
11268                 tp->nvram_pagesize = 2048;
11269                 break;
11270         case FLASH_5752PAGE_SIZE_4K:
11271                 tp->nvram_pagesize = 4096;
11272                 break;
11273         case FLASH_5752PAGE_SIZE_264:
11274                 tp->nvram_pagesize = 264;
11275                 break;
11276         case FLASH_5752PAGE_SIZE_528:
11277                 tp->nvram_pagesize = 528;
11278                 break;
11279         }
11280 }
11281
11282 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11283 {
11284         u32 nvcfg1;
11285
11286         nvcfg1 = tr32(NVRAM_CFG1);
11287
11288         /* NVRAM protection for TPM */
11289         if (nvcfg1 & (1 << 27))
11290                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11291
11292         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11293         case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11294         case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11295                 tp->nvram_jedecnum = JEDEC_ATMEL;
11296                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11297                 break;
11298         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11299                 tp->nvram_jedecnum = JEDEC_ATMEL;
11300                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11301                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11302                 break;
11303         case FLASH_5752VENDOR_ST_M45PE10:
11304         case FLASH_5752VENDOR_ST_M45PE20:
11305         case FLASH_5752VENDOR_ST_M45PE40:
11306                 tp->nvram_jedecnum = JEDEC_ST;
11307                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11308                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11309                 break;
11310         }
11311
11312         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11313                 tg3_nvram_get_pagesize(tp, nvcfg1);
11314         } else {
11315                 /* For eeprom, set pagesize to maximum eeprom size */
11316                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11317
11318                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11319                 tw32(NVRAM_CFG1, nvcfg1);
11320         }
11321 }
11322
11323 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11324 {
11325         u32 nvcfg1, protect = 0;
11326
11327         nvcfg1 = tr32(NVRAM_CFG1);
11328
11329         /* NVRAM protection for TPM */
11330         if (nvcfg1 & (1 << 27)) {
11331                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11332                 protect = 1;
11333         }
11334
11335         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11336         switch (nvcfg1) {
11337         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11338         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11339         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11340         case FLASH_5755VENDOR_ATMEL_FLASH_5:
11341                 tp->nvram_jedecnum = JEDEC_ATMEL;
11342                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11343                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11344                 tp->nvram_pagesize = 264;
11345                 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11346                     nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11347                         tp->nvram_size = (protect ? 0x3e200 :
11348                                           TG3_NVRAM_SIZE_512KB);
11349                 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11350                         tp->nvram_size = (protect ? 0x1f200 :
11351                                           TG3_NVRAM_SIZE_256KB);
11352                 else
11353                         tp->nvram_size = (protect ? 0x1f200 :
11354                                           TG3_NVRAM_SIZE_128KB);
11355                 break;
11356         case FLASH_5752VENDOR_ST_M45PE10:
11357         case FLASH_5752VENDOR_ST_M45PE20:
11358         case FLASH_5752VENDOR_ST_M45PE40:
11359                 tp->nvram_jedecnum = JEDEC_ST;
11360                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11361                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11362                 tp->nvram_pagesize = 256;
11363                 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11364                         tp->nvram_size = (protect ?
11365                                           TG3_NVRAM_SIZE_64KB :
11366                                           TG3_NVRAM_SIZE_128KB);
11367                 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11368                         tp->nvram_size = (protect ?
11369                                           TG3_NVRAM_SIZE_64KB :
11370                                           TG3_NVRAM_SIZE_256KB);
11371                 else
11372                         tp->nvram_size = (protect ?
11373                                           TG3_NVRAM_SIZE_128KB :
11374                                           TG3_NVRAM_SIZE_512KB);
11375                 break;
11376         }
11377 }
11378
11379 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11380 {
11381         u32 nvcfg1;
11382
11383         nvcfg1 = tr32(NVRAM_CFG1);
11384
11385         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11386         case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11387         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11388         case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11389         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11390                 tp->nvram_jedecnum = JEDEC_ATMEL;
11391                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11392                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11393
11394                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11395                 tw32(NVRAM_CFG1, nvcfg1);
11396                 break;
11397         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11398         case FLASH_5755VENDOR_ATMEL_FLASH_1:
11399         case FLASH_5755VENDOR_ATMEL_FLASH_2:
11400         case FLASH_5755VENDOR_ATMEL_FLASH_3:
11401                 tp->nvram_jedecnum = JEDEC_ATMEL;
11402                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11403                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11404                 tp->nvram_pagesize = 264;
11405                 break;
11406         case FLASH_5752VENDOR_ST_M45PE10:
11407         case FLASH_5752VENDOR_ST_M45PE20:
11408         case FLASH_5752VENDOR_ST_M45PE40:
11409                 tp->nvram_jedecnum = JEDEC_ST;
11410                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11411                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11412                 tp->nvram_pagesize = 256;
11413                 break;
11414         }
11415 }
11416
11417 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11418 {
11419         u32 nvcfg1, protect = 0;
11420
11421         nvcfg1 = tr32(NVRAM_CFG1);
11422
11423         /* NVRAM protection for TPM */
11424         if (nvcfg1 & (1 << 27)) {
11425                 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11426                 protect = 1;
11427         }
11428
11429         nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11430         switch (nvcfg1) {
11431         case FLASH_5761VENDOR_ATMEL_ADB021D:
11432         case FLASH_5761VENDOR_ATMEL_ADB041D:
11433         case FLASH_5761VENDOR_ATMEL_ADB081D:
11434         case FLASH_5761VENDOR_ATMEL_ADB161D:
11435         case FLASH_5761VENDOR_ATMEL_MDB021D:
11436         case FLASH_5761VENDOR_ATMEL_MDB041D:
11437         case FLASH_5761VENDOR_ATMEL_MDB081D:
11438         case FLASH_5761VENDOR_ATMEL_MDB161D:
11439                 tp->nvram_jedecnum = JEDEC_ATMEL;
11440                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11441                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11442                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11443                 tp->nvram_pagesize = 256;
11444                 break;
11445         case FLASH_5761VENDOR_ST_A_M45PE20:
11446         case FLASH_5761VENDOR_ST_A_M45PE40:
11447         case FLASH_5761VENDOR_ST_A_M45PE80:
11448         case FLASH_5761VENDOR_ST_A_M45PE16:
11449         case FLASH_5761VENDOR_ST_M_M45PE20:
11450         case FLASH_5761VENDOR_ST_M_M45PE40:
11451         case FLASH_5761VENDOR_ST_M_M45PE80:
11452         case FLASH_5761VENDOR_ST_M_M45PE16:
11453                 tp->nvram_jedecnum = JEDEC_ST;
11454                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11455                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11456                 tp->nvram_pagesize = 256;
11457                 break;
11458         }
11459
11460         if (protect) {
11461                 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11462         } else {
11463                 switch (nvcfg1) {
11464                 case FLASH_5761VENDOR_ATMEL_ADB161D:
11465                 case FLASH_5761VENDOR_ATMEL_MDB161D:
11466                 case FLASH_5761VENDOR_ST_A_M45PE16:
11467                 case FLASH_5761VENDOR_ST_M_M45PE16:
11468                         tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11469                         break;
11470                 case FLASH_5761VENDOR_ATMEL_ADB081D:
11471                 case FLASH_5761VENDOR_ATMEL_MDB081D:
11472                 case FLASH_5761VENDOR_ST_A_M45PE80:
11473                 case FLASH_5761VENDOR_ST_M_M45PE80:
11474                         tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11475                         break;
11476                 case FLASH_5761VENDOR_ATMEL_ADB041D:
11477                 case FLASH_5761VENDOR_ATMEL_MDB041D:
11478                 case FLASH_5761VENDOR_ST_A_M45PE40:
11479                 case FLASH_5761VENDOR_ST_M_M45PE40:
11480                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11481                         break;
11482                 case FLASH_5761VENDOR_ATMEL_ADB021D:
11483                 case FLASH_5761VENDOR_ATMEL_MDB021D:
11484                 case FLASH_5761VENDOR_ST_A_M45PE20:
11485                 case FLASH_5761VENDOR_ST_M_M45PE20:
11486                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11487                         break;
11488                 }
11489         }
11490 }
11491
11492 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11493 {
11494         tp->nvram_jedecnum = JEDEC_ATMEL;
11495         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11496         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11497 }
11498
11499 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11500 {
11501         u32 nvcfg1;
11502
11503         nvcfg1 = tr32(NVRAM_CFG1);
11504
11505         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11506         case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11507         case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11508                 tp->nvram_jedecnum = JEDEC_ATMEL;
11509                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11510                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11511
11512                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11513                 tw32(NVRAM_CFG1, nvcfg1);
11514                 return;
11515         case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11516         case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11517         case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11518         case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11519         case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11520         case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11521         case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11522                 tp->nvram_jedecnum = JEDEC_ATMEL;
11523                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11524                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11525
11526                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11527                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11528                 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11529                 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11530                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11531                         break;
11532                 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11533                 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11534                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11535                         break;
11536                 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11537                 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11538                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11539                         break;
11540                 }
11541                 break;
11542         case FLASH_5752VENDOR_ST_M45PE10:
11543         case FLASH_5752VENDOR_ST_M45PE20:
11544         case FLASH_5752VENDOR_ST_M45PE40:
11545                 tp->nvram_jedecnum = JEDEC_ST;
11546                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11547                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11548
11549                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11550                 case FLASH_5752VENDOR_ST_M45PE10:
11551                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11552                         break;
11553                 case FLASH_5752VENDOR_ST_M45PE20:
11554                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11555                         break;
11556                 case FLASH_5752VENDOR_ST_M45PE40:
11557                         tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11558                         break;
11559                 }
11560                 break;
11561         default:
11562                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11563                 return;
11564         }
11565
11566         tg3_nvram_get_pagesize(tp, nvcfg1);
11567         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11568                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11569 }
11570
11571
11572 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11573 {
11574         u32 nvcfg1;
11575
11576         nvcfg1 = tr32(NVRAM_CFG1);
11577
11578         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11579         case FLASH_5717VENDOR_ATMEL_EEPROM:
11580         case FLASH_5717VENDOR_MICRO_EEPROM:
11581                 tp->nvram_jedecnum = JEDEC_ATMEL;
11582                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11583                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11584
11585                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11586                 tw32(NVRAM_CFG1, nvcfg1);
11587                 return;
11588         case FLASH_5717VENDOR_ATMEL_MDB011D:
11589         case FLASH_5717VENDOR_ATMEL_ADB011B:
11590         case FLASH_5717VENDOR_ATMEL_ADB011D:
11591         case FLASH_5717VENDOR_ATMEL_MDB021D:
11592         case FLASH_5717VENDOR_ATMEL_ADB021B:
11593         case FLASH_5717VENDOR_ATMEL_ADB021D:
11594         case FLASH_5717VENDOR_ATMEL_45USPT:
11595                 tp->nvram_jedecnum = JEDEC_ATMEL;
11596                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11597                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11598
11599                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11600                 case FLASH_5717VENDOR_ATMEL_MDB021D:
11601                 case FLASH_5717VENDOR_ATMEL_ADB021B:
11602                 case FLASH_5717VENDOR_ATMEL_ADB021D:
11603                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11604                         break;
11605                 default:
11606                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11607                         break;
11608                 }
11609                 break;
11610         case FLASH_5717VENDOR_ST_M_M25PE10:
11611         case FLASH_5717VENDOR_ST_A_M25PE10:
11612         case FLASH_5717VENDOR_ST_M_M45PE10:
11613         case FLASH_5717VENDOR_ST_A_M45PE10:
11614         case FLASH_5717VENDOR_ST_M_M25PE20:
11615         case FLASH_5717VENDOR_ST_A_M25PE20:
11616         case FLASH_5717VENDOR_ST_M_M45PE20:
11617         case FLASH_5717VENDOR_ST_A_M45PE20:
11618         case FLASH_5717VENDOR_ST_25USPT:
11619         case FLASH_5717VENDOR_ST_45USPT:
11620                 tp->nvram_jedecnum = JEDEC_ST;
11621                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11622                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11623
11624                 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11625                 case FLASH_5717VENDOR_ST_M_M25PE20:
11626                 case FLASH_5717VENDOR_ST_A_M25PE20:
11627                 case FLASH_5717VENDOR_ST_M_M45PE20:
11628                 case FLASH_5717VENDOR_ST_A_M45PE20:
11629                         tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11630                         break;
11631                 default:
11632                         tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11633                         break;
11634                 }
11635                 break;
11636         default:
11637                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11638                 return;
11639         }
11640
11641         tg3_nvram_get_pagesize(tp, nvcfg1);
11642         if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11643                 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11644 }
11645
11646 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11647 static void __devinit tg3_nvram_init(struct tg3 *tp)
11648 {
11649         tw32_f(GRC_EEPROM_ADDR,
11650              (EEPROM_ADDR_FSM_RESET |
11651               (EEPROM_DEFAULT_CLOCK_PERIOD <<
11652                EEPROM_ADDR_CLKPERD_SHIFT)));
11653
11654         msleep(1);
11655
11656         /* Enable seeprom accesses. */
11657         tw32_f(GRC_LOCAL_CTRL,
11658              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11659         udelay(100);
11660
11661         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11662             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11663                 tp->tg3_flags |= TG3_FLAG_NVRAM;
11664
11665                 if (tg3_nvram_lock(tp)) {
11666                         netdev_warn(tp->dev,
11667                                     "Cannot get nvram lock, %s failed\n",
11668                                     __func__);
11669                         return;
11670                 }
11671                 tg3_enable_nvram_access(tp);
11672
11673                 tp->nvram_size = 0;
11674
11675                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11676                         tg3_get_5752_nvram_info(tp);
11677                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11678                         tg3_get_5755_nvram_info(tp);
11679                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11680                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11681                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11682                         tg3_get_5787_nvram_info(tp);
11683                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11684                         tg3_get_5761_nvram_info(tp);
11685                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11686                         tg3_get_5906_nvram_info(tp);
11687                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11688                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11689                         tg3_get_57780_nvram_info(tp);
11690                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
11691                          GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11692                         tg3_get_5717_nvram_info(tp);
11693                 else
11694                         tg3_get_nvram_info(tp);
11695
11696                 if (tp->nvram_size == 0)
11697                         tg3_get_nvram_size(tp);
11698
11699                 tg3_disable_nvram_access(tp);
11700                 tg3_nvram_unlock(tp);
11701
11702         } else {
11703                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11704
11705                 tg3_get_eeprom_size(tp);
11706         }
11707 }
11708
11709 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11710                                     u32 offset, u32 len, u8 *buf)
11711 {
11712         int i, j, rc = 0;
11713         u32 val;
11714
11715         for (i = 0; i < len; i += 4) {
11716                 u32 addr;
11717                 __be32 data;
11718
11719                 addr = offset + i;
11720
11721                 memcpy(&data, buf + i, 4);
11722
11723                 /*
11724                  * The SEEPROM interface expects the data to always be opposite
11725                  * the native endian format.  We accomplish this by reversing
11726                  * all the operations that would have been performed on the
11727                  * data from a call to tg3_nvram_read_be32().
11728                  */
11729                 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11730
11731                 val = tr32(GRC_EEPROM_ADDR);
11732                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11733
11734                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11735                         EEPROM_ADDR_READ);
11736                 tw32(GRC_EEPROM_ADDR, val |
11737                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
11738                         (addr & EEPROM_ADDR_ADDR_MASK) |
11739                         EEPROM_ADDR_START |
11740                         EEPROM_ADDR_WRITE);
11741
11742                 for (j = 0; j < 1000; j++) {
11743                         val = tr32(GRC_EEPROM_ADDR);
11744
11745                         if (val & EEPROM_ADDR_COMPLETE)
11746                                 break;
11747                         msleep(1);
11748                 }
11749                 if (!(val & EEPROM_ADDR_COMPLETE)) {
11750                         rc = -EBUSY;
11751                         break;
11752                 }
11753         }
11754
11755         return rc;
11756 }
11757
11758 /* offset and length are dword aligned */
11759 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11760                 u8 *buf)
11761 {
11762         int ret = 0;
11763         u32 pagesize = tp->nvram_pagesize;
11764         u32 pagemask = pagesize - 1;
11765         u32 nvram_cmd;
11766         u8 *tmp;
11767
11768         tmp = kmalloc(pagesize, GFP_KERNEL);
11769         if (tmp == NULL)
11770                 return -ENOMEM;
11771
11772         while (len) {
11773                 int j;
11774                 u32 phy_addr, page_off, size;
11775
11776                 phy_addr = offset & ~pagemask;
11777
11778                 for (j = 0; j < pagesize; j += 4) {
11779                         ret = tg3_nvram_read_be32(tp, phy_addr + j,
11780                                                   (__be32 *) (tmp + j));
11781                         if (ret)
11782                                 break;
11783                 }
11784                 if (ret)
11785                         break;
11786
11787                 page_off = offset & pagemask;
11788                 size = pagesize;
11789                 if (len < size)
11790                         size = len;
11791
11792                 len -= size;
11793
11794                 memcpy(tmp + page_off, buf, size);
11795
11796                 offset = offset + (pagesize - page_off);
11797
11798                 tg3_enable_nvram_access(tp);
11799
11800                 /*
11801                  * Before we can erase the flash page, we need
11802                  * to issue a special "write enable" command.
11803                  */
11804                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11805
11806                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11807                         break;
11808
11809                 /* Erase the target page */
11810                 tw32(NVRAM_ADDR, phy_addr);
11811
11812                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11813                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11814
11815                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11816                         break;
11817
11818                 /* Issue another write enable to start the write. */
11819                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11820
11821                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11822                         break;
11823
11824                 for (j = 0; j < pagesize; j += 4) {
11825                         __be32 data;
11826
11827                         data = *((__be32 *) (tmp + j));
11828
11829                         tw32(NVRAM_WRDATA, be32_to_cpu(data));
11830
11831                         tw32(NVRAM_ADDR, phy_addr + j);
11832
11833                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11834                                 NVRAM_CMD_WR;
11835
11836                         if (j == 0)
11837                                 nvram_cmd |= NVRAM_CMD_FIRST;
11838                         else if (j == (pagesize - 4))
11839                                 nvram_cmd |= NVRAM_CMD_LAST;
11840
11841                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11842                                 break;
11843                 }
11844                 if (ret)
11845                         break;
11846         }
11847
11848         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11849         tg3_nvram_exec_cmd(tp, nvram_cmd);
11850
11851         kfree(tmp);
11852
11853         return ret;
11854 }
11855
11856 /* offset and length are dword aligned */
11857 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11858                 u8 *buf)
11859 {
11860         int i, ret = 0;
11861
11862         for (i = 0; i < len; i += 4, offset += 4) {
11863                 u32 page_off, phy_addr, nvram_cmd;
11864                 __be32 data;
11865
11866                 memcpy(&data, buf + i, 4);
11867                 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11868
11869                 page_off = offset % tp->nvram_pagesize;
11870
11871                 phy_addr = tg3_nvram_phys_addr(tp, offset);
11872
11873                 tw32(NVRAM_ADDR, phy_addr);
11874
11875                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11876
11877                 if (page_off == 0 || i == 0)
11878                         nvram_cmd |= NVRAM_CMD_FIRST;
11879                 if (page_off == (tp->nvram_pagesize - 4))
11880                         nvram_cmd |= NVRAM_CMD_LAST;
11881
11882                 if (i == (len - 4))
11883                         nvram_cmd |= NVRAM_CMD_LAST;
11884
11885                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11886                     !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11887                     (tp->nvram_jedecnum == JEDEC_ST) &&
11888                     (nvram_cmd & NVRAM_CMD_FIRST)) {
11889
11890                         if ((ret = tg3_nvram_exec_cmd(tp,
11891                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11892                                 NVRAM_CMD_DONE)))
11893
11894                                 break;
11895                 }
11896                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11897                         /* We always do complete word writes to eeprom. */
11898                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11899                 }
11900
11901                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11902                         break;
11903         }
11904         return ret;
11905 }
11906
11907 /* offset and length are dword aligned */
11908 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11909 {
11910         int ret;
11911
11912         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11913                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11914                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
11915                 udelay(40);
11916         }
11917
11918         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11919                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11920         } else {
11921                 u32 grc_mode;
11922
11923                 ret = tg3_nvram_lock(tp);
11924                 if (ret)
11925                         return ret;
11926
11927                 tg3_enable_nvram_access(tp);
11928                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11929                     !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11930                         tw32(NVRAM_WRITE1, 0x406);
11931
11932                 grc_mode = tr32(GRC_MODE);
11933                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
11934
11935                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
11936                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11937
11938                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
11939                                 buf);
11940                 } else {
11941                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
11942                                 buf);
11943                 }
11944
11945                 grc_mode = tr32(GRC_MODE);
11946                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
11947
11948                 tg3_disable_nvram_access(tp);
11949                 tg3_nvram_unlock(tp);
11950         }
11951
11952         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11953                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
11954                 udelay(40);
11955         }
11956
11957         return ret;
11958 }
11959
11960 struct subsys_tbl_ent {
11961         u16 subsys_vendor, subsys_devid;
11962         u32 phy_id;
11963 };
11964
11965 static struct subsys_tbl_ent subsys_id_to_phy_id[] __devinitdata = {
11966         /* Broadcom boards. */
11967         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11968           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
11969         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11970           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
11971         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11972           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
11973         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11974           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
11975         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11976           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
11977         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11978           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
11979         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11980           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
11981         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11982           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
11983         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11984           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
11985         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11986           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
11987         { TG3PCI_SUBVENDOR_ID_BROADCOM,
11988           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
11989
11990         /* 3com boards. */
11991         { TG3PCI_SUBVENDOR_ID_3COM,
11992           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
11993         { TG3PCI_SUBVENDOR_ID_3COM,
11994           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
11995         { TG3PCI_SUBVENDOR_ID_3COM,
11996           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
11997         { TG3PCI_SUBVENDOR_ID_3COM,
11998           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
11999         { TG3PCI_SUBVENDOR_ID_3COM,
12000           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
12001
12002         /* DELL boards. */
12003         { TG3PCI_SUBVENDOR_ID_DELL,
12004           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
12005         { TG3PCI_SUBVENDOR_ID_DELL,
12006           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
12007         { TG3PCI_SUBVENDOR_ID_DELL,
12008           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
12009         { TG3PCI_SUBVENDOR_ID_DELL,
12010           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
12011
12012         /* Compaq boards. */
12013         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12014           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
12015         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12016           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
12017         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12018           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
12019         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12020           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
12021         { TG3PCI_SUBVENDOR_ID_COMPAQ,
12022           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
12023
12024         /* IBM boards. */
12025         { TG3PCI_SUBVENDOR_ID_IBM,
12026           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
12027 };
12028
12029 static struct subsys_tbl_ent * __devinit tg3_lookup_by_subsys(struct tg3 *tp)
12030 {
12031         int i;
12032
12033         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12034                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12035                      tp->pdev->subsystem_vendor) &&
12036                     (subsys_id_to_phy_id[i].subsys_devid ==
12037                      tp->pdev->subsystem_device))
12038                         return &subsys_id_to_phy_id[i];
12039         }
12040         return NULL;
12041 }
12042
12043 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12044 {
12045         u32 val;
12046         u16 pmcsr;
12047
12048         /* On some early chips the SRAM cannot be accessed in D3hot state,
12049          * so need make sure we're in D0.
12050          */
12051         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12052         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12053         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12054         msleep(1);
12055
12056         /* Make sure register accesses (indirect or otherwise)
12057          * will function correctly.
12058          */
12059         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12060                                tp->misc_host_ctrl);
12061
12062         /* The memory arbiter has to be enabled in order for SRAM accesses
12063          * to succeed.  Normally on powerup the tg3 chip firmware will make
12064          * sure it is enabled, but other entities such as system netboot
12065          * code might disable it.
12066          */
12067         val = tr32(MEMARB_MODE);
12068         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12069
12070         tp->phy_id = TG3_PHY_ID_INVALID;
12071         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12072
12073         /* Assume an onboard device and WOL capable by default.  */
12074         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12075
12076         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12077                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12078                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12079                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12080                 }
12081                 val = tr32(VCPU_CFGSHDW);
12082                 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12083                         tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12084                 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12085                     (val & VCPU_CFGSHDW_WOL_MAGPKT))
12086                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12087                 goto done;
12088         }
12089
12090         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12091         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12092                 u32 nic_cfg, led_cfg;
12093                 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12094                 int eeprom_phy_serdes = 0;
12095
12096                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12097                 tp->nic_sram_data_cfg = nic_cfg;
12098
12099                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12100                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12101                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12102                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12103                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12104                     (ver > 0) && (ver < 0x100))
12105                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12106
12107                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12108                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12109
12110                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12111                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12112                         eeprom_phy_serdes = 1;
12113
12114                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12115                 if (nic_phy_id != 0) {
12116                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12117                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12118
12119                         eeprom_phy_id  = (id1 >> 16) << 10;
12120                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
12121                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
12122                 } else
12123                         eeprom_phy_id = 0;
12124
12125                 tp->phy_id = eeprom_phy_id;
12126                 if (eeprom_phy_serdes) {
12127                         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12128                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12129                         else
12130                                 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
12131                 }
12132
12133                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12134                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12135                                     SHASTA_EXT_LED_MODE_MASK);
12136                 else
12137                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12138
12139                 switch (led_cfg) {
12140                 default:
12141                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12142                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12143                         break;
12144
12145                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12146                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12147                         break;
12148
12149                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12150                         tp->led_ctrl = LED_CTRL_MODE_MAC;
12151
12152                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12153                          * read on some older 5700/5701 bootcode.
12154                          */
12155                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12156                             ASIC_REV_5700 ||
12157                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
12158                             ASIC_REV_5701)
12159                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12160
12161                         break;
12162
12163                 case SHASTA_EXT_LED_SHARED:
12164                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
12165                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12166                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12167                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12168                                                  LED_CTRL_MODE_PHY_2);
12169                         break;
12170
12171                 case SHASTA_EXT_LED_MAC:
12172                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12173                         break;
12174
12175                 case SHASTA_EXT_LED_COMBO:
12176                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
12177                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12178                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12179                                                  LED_CTRL_MODE_PHY_2);
12180                         break;
12181
12182                 }
12183
12184                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12185                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12186                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12187                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12188
12189                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12190                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12191
12192                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12193                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12194                         if ((tp->pdev->subsystem_vendor ==
12195                              PCI_VENDOR_ID_ARIMA) &&
12196                             (tp->pdev->subsystem_device == 0x205a ||
12197                              tp->pdev->subsystem_device == 0x2063))
12198                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12199                 } else {
12200                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12201                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12202                 }
12203
12204                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12205                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12206                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12207                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12208                 }
12209
12210                 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12211                         (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12212                         tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12213
12214                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
12215                     !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12216                         tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12217
12218                 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12219                     (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12220                         tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12221
12222                 if (cfg2 & (1 << 17))
12223                         tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
12224
12225                 /* serdes signal pre-emphasis in register 0x590 set by */
12226                 /* bootcode if bit 18 is set */
12227                 if (cfg2 & (1 << 18))
12228                         tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
12229
12230                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12231                       GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12232                     (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12233                         tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
12234
12235                 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
12236                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
12237                     !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
12238                         u32 cfg3;
12239
12240                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12241                         if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12242                                 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12243                 }
12244
12245                 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
12246                         tp->tg3_flags3 |= TG3_FLG3_RGMII_INBAND_DISABLE;
12247                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12248                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12249                 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12250                         tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12251         }
12252 done:
12253         device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12254         device_set_wakeup_enable(&tp->pdev->dev,
12255                                  tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12256 }
12257
12258 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12259 {
12260         int i;
12261         u32 val;
12262
12263         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12264         tw32(OTP_CTRL, cmd);
12265
12266         /* Wait for up to 1 ms for command to execute. */
12267         for (i = 0; i < 100; i++) {
12268                 val = tr32(OTP_STATUS);
12269                 if (val & OTP_STATUS_CMD_DONE)
12270                         break;
12271                 udelay(10);
12272         }
12273
12274         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12275 }
12276
12277 /* Read the gphy configuration from the OTP region of the chip.  The gphy
12278  * configuration is a 32-bit value that straddles the alignment boundary.
12279  * We do two 32-bit reads and then shift and merge the results.
12280  */
12281 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12282 {
12283         u32 bhalf_otp, thalf_otp;
12284
12285         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12286
12287         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12288                 return 0;
12289
12290         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12291
12292         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12293                 return 0;
12294
12295         thalf_otp = tr32(OTP_READ_DATA);
12296
12297         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12298
12299         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12300                 return 0;
12301
12302         bhalf_otp = tr32(OTP_READ_DATA);
12303
12304         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12305 }
12306
12307 static int __devinit tg3_phy_probe(struct tg3 *tp)
12308 {
12309         u32 hw_phy_id_1, hw_phy_id_2;
12310         u32 hw_phy_id, hw_phy_id_masked;
12311         int err;
12312
12313         if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12314                 return tg3_phy_init(tp);
12315
12316         /* Reading the PHY ID register can conflict with ASF
12317          * firmware access to the PHY hardware.
12318          */
12319         err = 0;
12320         if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12321             (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12322                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
12323         } else {
12324                 /* Now read the physical PHY_ID from the chip and verify
12325                  * that it is sane.  If it doesn't look good, we fall back
12326                  * to either the hard-coded table based PHY_ID and failing
12327                  * that the value found in the eeprom area.
12328                  */
12329                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12330                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12331
12332                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
12333                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12334                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
12335
12336                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
12337         }
12338
12339         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
12340                 tp->phy_id = hw_phy_id;
12341                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
12342                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12343                 else
12344                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
12345         } else {
12346                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
12347                         /* Do nothing, phy ID already set up in
12348                          * tg3_get_eeprom_hw_cfg().
12349                          */
12350                 } else {
12351                         struct subsys_tbl_ent *p;
12352
12353                         /* No eeprom signature?  Try the hardcoded
12354                          * subsys device table.
12355                          */
12356                         p = tg3_lookup_by_subsys(tp);
12357                         if (!p)
12358                                 return -ENODEV;
12359
12360                         tp->phy_id = p->phy_id;
12361                         if (!tp->phy_id ||
12362                             tp->phy_id == TG3_PHY_ID_BCM8002)
12363                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
12364                 }
12365         }
12366
12367         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
12368             !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12369             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12370                 u32 bmsr, adv_reg, tg3_ctrl, mask;
12371
12372                 tg3_readphy(tp, MII_BMSR, &bmsr);
12373                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12374                     (bmsr & BMSR_LSTATUS))
12375                         goto skip_phy_reset;
12376
12377                 err = tg3_phy_reset(tp);
12378                 if (err)
12379                         return err;
12380
12381                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12382                            ADVERTISE_100HALF | ADVERTISE_100FULL |
12383                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12384                 tg3_ctrl = 0;
12385                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
12386                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12387                                     MII_TG3_CTRL_ADV_1000_FULL);
12388                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12389                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12390                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12391                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
12392                 }
12393
12394                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12395                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12396                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12397                 if (!tg3_copper_is_advertising_all(tp, mask)) {
12398                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12399
12400                         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12401                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12402
12403                         tg3_writephy(tp, MII_BMCR,
12404                                      BMCR_ANENABLE | BMCR_ANRESTART);
12405                 }
12406                 tg3_phy_set_wirespeed(tp);
12407
12408                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12409                 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12410                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12411         }
12412
12413 skip_phy_reset:
12414         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
12415                 err = tg3_init_5401phy_dsp(tp);
12416                 if (err)
12417                         return err;
12418
12419                 err = tg3_init_5401phy_dsp(tp);
12420         }
12421
12422         if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12423                 tp->link_config.advertising =
12424                         (ADVERTISED_1000baseT_Half |
12425                          ADVERTISED_1000baseT_Full |
12426                          ADVERTISED_Autoneg |
12427                          ADVERTISED_FIBRE);
12428         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
12429                 tp->link_config.advertising &=
12430                         ~(ADVERTISED_1000baseT_Half |
12431                           ADVERTISED_1000baseT_Full);
12432
12433         return err;
12434 }
12435
12436 static void __devinit tg3_read_vpd(struct tg3 *tp)
12437 {
12438         u8 *vpd_data;
12439         unsigned int block_end, rosize, len;
12440         int j, i = 0;
12441         u32 magic;
12442
12443         if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12444             tg3_nvram_read(tp, 0x0, &magic))
12445                 goto out_no_vpd;
12446
12447         vpd_data = kmalloc(TG3_NVM_VPD_LEN, GFP_KERNEL);
12448         if (!vpd_data)
12449                 goto out_no_vpd;
12450
12451         if (magic == TG3_EEPROM_MAGIC) {
12452                 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12453                         u32 tmp;
12454
12455                         /* The data is in little-endian format in NVRAM.
12456                          * Use the big-endian read routines to preserve
12457                          * the byte order as it exists in NVRAM.
12458                          */
12459                         if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12460                                 goto out_not_found;
12461
12462                         memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12463                 }
12464         } else {
12465                 ssize_t cnt;
12466                 unsigned int pos = 0;
12467
12468                 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12469                         cnt = pci_read_vpd(tp->pdev, pos,
12470                                            TG3_NVM_VPD_LEN - pos,
12471                                            &vpd_data[pos]);
12472                         if (cnt == -ETIMEDOUT || -EINTR)
12473                                 cnt = 0;
12474                         else if (cnt < 0)
12475                                 goto out_not_found;
12476                 }
12477                 if (pos != TG3_NVM_VPD_LEN)
12478                         goto out_not_found;
12479         }
12480
12481         i = pci_vpd_find_tag(vpd_data, 0, TG3_NVM_VPD_LEN,
12482                              PCI_VPD_LRDT_RO_DATA);
12483         if (i < 0)
12484                 goto out_not_found;
12485
12486         rosize = pci_vpd_lrdt_size(&vpd_data[i]);
12487         block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
12488         i += PCI_VPD_LRDT_TAG_SIZE;
12489
12490         if (block_end > TG3_NVM_VPD_LEN)
12491                 goto out_not_found;
12492
12493         j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12494                                       PCI_VPD_RO_KEYWORD_MFR_ID);
12495         if (j > 0) {
12496                 len = pci_vpd_info_field_size(&vpd_data[j]);
12497
12498                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12499                 if (j + len > block_end || len != 4 ||
12500                     memcmp(&vpd_data[j], "1028", 4))
12501                         goto partno;
12502
12503                 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12504                                               PCI_VPD_RO_KEYWORD_VENDOR0);
12505                 if (j < 0)
12506                         goto partno;
12507
12508                 len = pci_vpd_info_field_size(&vpd_data[j]);
12509
12510                 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12511                 if (j + len > block_end)
12512                         goto partno;
12513
12514                 memcpy(tp->fw_ver, &vpd_data[j], len);
12515                 strncat(tp->fw_ver, " bc ", TG3_NVM_VPD_LEN - len - 1);
12516         }
12517
12518 partno:
12519         i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
12520                                       PCI_VPD_RO_KEYWORD_PARTNO);
12521         if (i < 0)
12522                 goto out_not_found;
12523
12524         len = pci_vpd_info_field_size(&vpd_data[i]);
12525
12526         i += PCI_VPD_INFO_FLD_HDR_SIZE;
12527         if (len > TG3_BPN_SIZE ||
12528             (len + i) > TG3_NVM_VPD_LEN)
12529                 goto out_not_found;
12530
12531         memcpy(tp->board_part_number, &vpd_data[i], len);
12532
12533 out_not_found:
12534         kfree(vpd_data);
12535         if (!tp->board_part_number[0])
12536                 return;
12537
12538 out_no_vpd:
12539         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12540                 strcpy(tp->board_part_number, "BCM95906");
12541         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12542                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12543                 strcpy(tp->board_part_number, "BCM57780");
12544         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12545                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12546                 strcpy(tp->board_part_number, "BCM57760");
12547         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12548                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12549                 strcpy(tp->board_part_number, "BCM57790");
12550         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12551                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12552                 strcpy(tp->board_part_number, "BCM57788");
12553         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12554                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
12555                 strcpy(tp->board_part_number, "BCM57761");
12556         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12557                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
12558                 strcpy(tp->board_part_number, "BCM57765");
12559         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12560                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
12561                 strcpy(tp->board_part_number, "BCM57781");
12562         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12563                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
12564                 strcpy(tp->board_part_number, "BCM57785");
12565         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12566                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
12567                 strcpy(tp->board_part_number, "BCM57791");
12568         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
12569                  tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12570                 strcpy(tp->board_part_number, "BCM57795");
12571         else
12572                 strcpy(tp->board_part_number, "none");
12573 }
12574
12575 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12576 {
12577         u32 val;
12578
12579         if (tg3_nvram_read(tp, offset, &val) ||
12580             (val & 0xfc000000) != 0x0c000000 ||
12581             tg3_nvram_read(tp, offset + 4, &val) ||
12582             val != 0)
12583                 return 0;
12584
12585         return 1;
12586 }
12587
12588 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12589 {
12590         u32 val, offset, start, ver_offset;
12591         int i, dst_off;
12592         bool newver = false;
12593
12594         if (tg3_nvram_read(tp, 0xc, &offset) ||
12595             tg3_nvram_read(tp, 0x4, &start))
12596                 return;
12597
12598         offset = tg3_nvram_logical_addr(tp, offset);
12599
12600         if (tg3_nvram_read(tp, offset, &val))
12601                 return;
12602
12603         if ((val & 0xfc000000) == 0x0c000000) {
12604                 if (tg3_nvram_read(tp, offset + 4, &val))
12605                         return;
12606
12607                 if (val == 0)
12608                         newver = true;
12609         }
12610
12611         dst_off = strlen(tp->fw_ver);
12612
12613         if (newver) {
12614                 if (TG3_VER_SIZE - dst_off < 16 ||
12615                     tg3_nvram_read(tp, offset + 8, &ver_offset))
12616                         return;
12617
12618                 offset = offset + ver_offset - start;
12619                 for (i = 0; i < 16; i += 4) {
12620                         __be32 v;
12621                         if (tg3_nvram_read_be32(tp, offset + i, &v))
12622                                 return;
12623
12624                         memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
12625                 }
12626         } else {
12627                 u32 major, minor;
12628
12629                 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12630                         return;
12631
12632                 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12633                         TG3_NVM_BCVER_MAJSFT;
12634                 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12635                 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
12636                          "v%d.%02d", major, minor);
12637         }
12638 }
12639
12640 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12641 {
12642         u32 val, major, minor;
12643
12644         /* Use native endian representation */
12645         if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12646                 return;
12647
12648         major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12649                 TG3_NVM_HWSB_CFG1_MAJSFT;
12650         minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12651                 TG3_NVM_HWSB_CFG1_MINSFT;
12652
12653         snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12654 }
12655
12656 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12657 {
12658         u32 offset, major, minor, build;
12659
12660         strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
12661
12662         if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12663                 return;
12664
12665         switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12666         case TG3_EEPROM_SB_REVISION_0:
12667                 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12668                 break;
12669         case TG3_EEPROM_SB_REVISION_2:
12670                 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12671                 break;
12672         case TG3_EEPROM_SB_REVISION_3:
12673                 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12674                 break;
12675         case TG3_EEPROM_SB_REVISION_4:
12676                 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
12677                 break;
12678         case TG3_EEPROM_SB_REVISION_5:
12679                 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
12680                 break;
12681         default:
12682                 return;
12683         }
12684
12685         if (tg3_nvram_read(tp, offset, &val))
12686                 return;
12687
12688         build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12689                 TG3_EEPROM_SB_EDH_BLD_SHFT;
12690         major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12691                 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12692         minor =  val & TG3_EEPROM_SB_EDH_MIN_MASK;
12693
12694         if (minor > 99 || build > 26)
12695                 return;
12696
12697         offset = strlen(tp->fw_ver);
12698         snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
12699                  " v%d.%02d", major, minor);
12700
12701         if (build > 0) {
12702                 offset = strlen(tp->fw_ver);
12703                 if (offset < TG3_VER_SIZE - 1)
12704                         tp->fw_ver[offset] = 'a' + build - 1;
12705         }
12706 }
12707
12708 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12709 {
12710         u32 val, offset, start;
12711         int i, vlen;
12712
12713         for (offset = TG3_NVM_DIR_START;
12714              offset < TG3_NVM_DIR_END;
12715              offset += TG3_NVM_DIRENT_SIZE) {
12716                 if (tg3_nvram_read(tp, offset, &val))
12717                         return;
12718
12719                 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12720                         break;
12721         }
12722
12723         if (offset == TG3_NVM_DIR_END)
12724                 return;
12725
12726         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12727                 start = 0x08000000;
12728         else if (tg3_nvram_read(tp, offset - 4, &start))
12729                 return;
12730
12731         if (tg3_nvram_read(tp, offset + 4, &offset) ||
12732             !tg3_fw_img_is_valid(tp, offset) ||
12733             tg3_nvram_read(tp, offset + 8, &val))
12734                 return;
12735
12736         offset += val - start;
12737
12738         vlen = strlen(tp->fw_ver);
12739
12740         tp->fw_ver[vlen++] = ',';
12741         tp->fw_ver[vlen++] = ' ';
12742
12743         for (i = 0; i < 4; i++) {
12744                 __be32 v;
12745                 if (tg3_nvram_read_be32(tp, offset, &v))
12746                         return;
12747
12748                 offset += sizeof(v);
12749
12750                 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12751                         memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12752                         break;
12753                 }
12754
12755                 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12756                 vlen += sizeof(v);
12757         }
12758 }
12759
12760 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12761 {
12762         int vlen;
12763         u32 apedata;
12764         char *fwtype;
12765
12766         if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12767             !(tp->tg3_flags  & TG3_FLAG_ENABLE_ASF))
12768                 return;
12769
12770         apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12771         if (apedata != APE_SEG_SIG_MAGIC)
12772                 return;
12773
12774         apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12775         if (!(apedata & APE_FW_STATUS_READY))
12776                 return;
12777
12778         apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12779
12780         if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) {
12781                 tp->tg3_flags3 |= TG3_FLG3_APE_HAS_NCSI;
12782                 fwtype = "NCSI";
12783         } else {
12784                 fwtype = "DASH";
12785         }
12786
12787         vlen = strlen(tp->fw_ver);
12788
12789         snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
12790                  fwtype,
12791                  (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12792                  (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12793                  (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12794                  (apedata & APE_FW_VERSION_BLDMSK));
12795 }
12796
12797 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12798 {
12799         u32 val;
12800         bool vpd_vers = false;
12801
12802         if (tp->fw_ver[0] != 0)
12803                 vpd_vers = true;
12804
12805         if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12806                 strcat(tp->fw_ver, "sb");
12807                 return;
12808         }
12809
12810         if (tg3_nvram_read(tp, 0, &val))
12811                 return;
12812
12813         if (val == TG3_EEPROM_MAGIC)
12814                 tg3_read_bc_ver(tp);
12815         else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12816                 tg3_read_sb_ver(tp, val);
12817         else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12818                 tg3_read_hwsb_ver(tp);
12819         else
12820                 return;
12821
12822         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12823              (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) || vpd_vers)
12824                 goto done;
12825
12826         tg3_read_mgmtfw_ver(tp);
12827
12828 done:
12829         tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12830 }
12831
12832 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12833
12834 static void inline vlan_features_add(struct net_device *dev, unsigned long flags)
12835 {
12836 #if TG3_VLAN_TAG_USED
12837         dev->vlan_features |= flags;
12838 #endif
12839 }
12840
12841 static int __devinit tg3_get_invariants(struct tg3 *tp)
12842 {
12843         static struct pci_device_id write_reorder_chipsets[] = {
12844                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12845                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12846                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12847                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12848                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12849                              PCI_DEVICE_ID_VIA_8385_0) },
12850                 { },
12851         };
12852         u32 misc_ctrl_reg;
12853         u32 pci_state_reg, grc_misc_cfg;
12854         u32 val;
12855         u16 pci_cmd;
12856         int err;
12857
12858         /* Force memory write invalidate off.  If we leave it on,
12859          * then on 5700_BX chips we have to enable a workaround.
12860          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12861          * to match the cacheline size.  The Broadcom driver have this
12862          * workaround but turns MWI off all the times so never uses
12863          * it.  This seems to suggest that the workaround is insufficient.
12864          */
12865         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12866         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12867         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12868
12869         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12870          * has the register indirect write enable bit set before
12871          * we try to access any of the MMIO registers.  It is also
12872          * critical that the PCI-X hw workaround situation is decided
12873          * before that as well.
12874          */
12875         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12876                               &misc_ctrl_reg);
12877
12878         tp->pci_chip_rev_id = (misc_ctrl_reg >>
12879                                MISC_HOST_CTRL_CHIPREV_SHIFT);
12880         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12881                 u32 prod_id_asic_rev;
12882
12883                 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12884                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12885                     tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719)
12886                         pci_read_config_dword(tp->pdev,
12887                                               TG3PCI_GEN2_PRODID_ASICREV,
12888                                               &prod_id_asic_rev);
12889                 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12890                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12891                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12892                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12893                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12894                          tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12895                         pci_read_config_dword(tp->pdev,
12896                                               TG3PCI_GEN15_PRODID_ASICREV,
12897                                               &prod_id_asic_rev);
12898                 else
12899                         pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12900                                               &prod_id_asic_rev);
12901
12902                 tp->pci_chip_rev_id = prod_id_asic_rev;
12903         }
12904
12905         /* Wrong chip ID in 5752 A0. This code can be removed later
12906          * as A0 is not in production.
12907          */
12908         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12909                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12910
12911         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12912          * we need to disable memory and use config. cycles
12913          * only to access all registers. The 5702/03 chips
12914          * can mistakenly decode the special cycles from the
12915          * ICH chipsets as memory write cycles, causing corruption
12916          * of register and memory space. Only certain ICH bridges
12917          * will drive special cycles with non-zero data during the
12918          * address phase which can fall within the 5703's address
12919          * range. This is not an ICH bug as the PCI spec allows
12920          * non-zero address during special cycles. However, only
12921          * these ICH bridges are known to drive non-zero addresses
12922          * during special cycles.
12923          *
12924          * Since special cycles do not cross PCI bridges, we only
12925          * enable this workaround if the 5703 is on the secondary
12926          * bus of these ICH bridges.
12927          */
12928         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12929             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12930                 static struct tg3_dev_id {
12931                         u32     vendor;
12932                         u32     device;
12933                         u32     rev;
12934                 } ich_chipsets[] = {
12935                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12936                           PCI_ANY_ID },
12937                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12938                           PCI_ANY_ID },
12939                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12940                           0xa },
12941                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12942                           PCI_ANY_ID },
12943                         { },
12944                 };
12945                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12946                 struct pci_dev *bridge = NULL;
12947
12948                 while (pci_id->vendor != 0) {
12949                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
12950                                                 bridge);
12951                         if (!bridge) {
12952                                 pci_id++;
12953                                 continue;
12954                         }
12955                         if (pci_id->rev != PCI_ANY_ID) {
12956                                 if (bridge->revision > pci_id->rev)
12957                                         continue;
12958                         }
12959                         if (bridge->subordinate &&
12960                             (bridge->subordinate->number ==
12961                              tp->pdev->bus->number)) {
12962
12963                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12964                                 pci_dev_put(bridge);
12965                                 break;
12966                         }
12967                 }
12968         }
12969
12970         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12971                 static struct tg3_dev_id {
12972                         u32     vendor;
12973                         u32     device;
12974                 } bridge_chipsets[] = {
12975                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12976                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12977                         { },
12978                 };
12979                 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12980                 struct pci_dev *bridge = NULL;
12981
12982                 while (pci_id->vendor != 0) {
12983                         bridge = pci_get_device(pci_id->vendor,
12984                                                 pci_id->device,
12985                                                 bridge);
12986                         if (!bridge) {
12987                                 pci_id++;
12988                                 continue;
12989                         }
12990                         if (bridge->subordinate &&
12991                             (bridge->subordinate->number <=
12992                              tp->pdev->bus->number) &&
12993                             (bridge->subordinate->subordinate >=
12994                              tp->pdev->bus->number)) {
12995                                 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12996                                 pci_dev_put(bridge);
12997                                 break;
12998                         }
12999                 }
13000         }
13001
13002         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
13003          * DMA addresses > 40-bit. This bridge may have other additional
13004          * 57xx devices behind it in some 4-port NIC designs for example.
13005          * Any tg3 device found behind the bridge will also need the 40-bit
13006          * DMA workaround.
13007          */
13008         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
13009             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13010                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
13011                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13012                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
13013         } else {
13014                 struct pci_dev *bridge = NULL;
13015
13016                 do {
13017                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
13018                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
13019                                                 bridge);
13020                         if (bridge && bridge->subordinate &&
13021                             (bridge->subordinate->number <=
13022                              tp->pdev->bus->number) &&
13023                             (bridge->subordinate->subordinate >=
13024                              tp->pdev->bus->number)) {
13025                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13026                                 pci_dev_put(bridge);
13027                                 break;
13028                         }
13029                 } while (bridge);
13030         }
13031
13032         /* Initialize misc host control in PCI block. */
13033         tp->misc_host_ctrl |= (misc_ctrl_reg &
13034                                MISC_HOST_CTRL_CHIPREV);
13035         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13036                                tp->misc_host_ctrl);
13037
13038         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13039             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13040             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13041                 tp->pdev_peer = tg3_find_peer(tp);
13042
13043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13044             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13045             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13046                 tp->tg3_flags3 |= TG3_FLG3_5717_PLUS;
13047
13048         /* Intentionally exclude ASIC_REV_5906 */
13049         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13050             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13051             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13052             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13053             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13054             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13055             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13056                 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13057
13058         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13059             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13060             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13061             (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13062             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13063                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13064
13065         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13066             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13067                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13068
13069         /* 5700 B0 chips do not support checksumming correctly due
13070          * to hardware bugs.
13071          */
13072         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13073                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13074         else {
13075                 unsigned long features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_GRO;
13076
13077                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13078                 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13079                         features |= NETIF_F_IPV6_CSUM;
13080                 tp->dev->features |= features;
13081                 vlan_features_add(tp->dev, features);
13082         }
13083
13084         /* Determine TSO capabilities */
13085         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13086                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13087         else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13088                  GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13089                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13090         else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13091                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13093                     tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13094                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13095         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13096                    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13097                    tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13098                 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13099                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13100                         tp->fw_needed = FIRMWARE_TG3TSO5;
13101                 else
13102                         tp->fw_needed = FIRMWARE_TG3TSO;
13103         }
13104
13105         tp->irq_max = 1;
13106
13107         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13108                 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13109                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13110                     GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13111                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13112                      tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13113                      tp->pdev_peer == tp->pdev))
13114                         tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13115
13116                 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13117                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13118                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13119                 }
13120
13121                 if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13122                         tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13123                         tp->irq_max = TG3_IRQ_MAX_VECS;
13124                 }
13125         }
13126
13127         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13128             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
13129             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13130                 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13131         else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13132                 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13133                 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13134         }
13135
13136         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13137                 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13138
13139         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13140             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13141             (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13142                 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13143
13144         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13145                               &pci_state_reg);
13146
13147         tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13148         if (tp->pcie_cap != 0) {
13149                 u16 lnkctl;
13150
13151                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13152
13153                 pcie_set_readrq(tp->pdev, 4096);
13154
13155                 pci_read_config_word(tp->pdev,
13156                                      tp->pcie_cap + PCI_EXP_LNKCTL,
13157                                      &lnkctl);
13158                 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13159                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13160                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13161                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13162                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13163                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13164                             tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13165                                 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13166                 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13167                         tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13168                 }
13169         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13170                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13171         } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13172                    (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13173                 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13174                 if (!tp->pcix_cap) {
13175                         dev_err(&tp->pdev->dev,
13176                                 "Cannot find PCI-X capability, aborting\n");
13177                         return -EIO;
13178                 }
13179
13180                 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13181                         tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13182         }
13183
13184         /* If we have an AMD 762 or VIA K8T800 chipset, write
13185          * reordering to the mailbox registers done by the host
13186          * controller can cause major troubles.  We read back from
13187          * every mailbox register write to force the writes to be
13188          * posted to the chip in order.
13189          */
13190         if (pci_dev_present(write_reorder_chipsets) &&
13191             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13192                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13193
13194         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13195                              &tp->pci_cacheline_sz);
13196         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13197                              &tp->pci_lat_timer);
13198         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13199             tp->pci_lat_timer < 64) {
13200                 tp->pci_lat_timer = 64;
13201                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13202                                       tp->pci_lat_timer);
13203         }
13204
13205         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13206                 /* 5700 BX chips need to have their TX producer index
13207                  * mailboxes written twice to workaround a bug.
13208                  */
13209                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13210
13211                 /* If we are in PCI-X mode, enable register write workaround.
13212                  *
13213                  * The workaround is to use indirect register accesses
13214                  * for all chip writes not to mailbox registers.
13215                  */
13216                 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13217                         u32 pm_reg;
13218
13219                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13220
13221                         /* The chip can have it's power management PCI config
13222                          * space registers clobbered due to this bug.
13223                          * So explicitly force the chip into D0 here.
13224                          */
13225                         pci_read_config_dword(tp->pdev,
13226                                               tp->pm_cap + PCI_PM_CTRL,
13227                                               &pm_reg);
13228                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13229                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13230                         pci_write_config_dword(tp->pdev,
13231                                                tp->pm_cap + PCI_PM_CTRL,
13232                                                pm_reg);
13233
13234                         /* Also, force SERR#/PERR# in PCI command. */
13235                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13236                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13237                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13238                 }
13239         }
13240
13241         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13242                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13243         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13244                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13245
13246         /* Chip-specific fixup from Broadcom driver */
13247         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13248             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13249                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13250                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13251         }
13252
13253         /* Default fast path register access methods */
13254         tp->read32 = tg3_read32;
13255         tp->write32 = tg3_write32;
13256         tp->read32_mbox = tg3_read32;
13257         tp->write32_mbox = tg3_write32;
13258         tp->write32_tx_mbox = tg3_write32;
13259         tp->write32_rx_mbox = tg3_write32;
13260
13261         /* Various workaround register access methods */
13262         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13263                 tp->write32 = tg3_write_indirect_reg32;
13264         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13265                  ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13266                   tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13267                 /*
13268                  * Back to back register writes can cause problems on these
13269                  * chips, the workaround is to read back all reg writes
13270                  * except those to mailbox regs.
13271                  *
13272                  * See tg3_write_indirect_reg32().
13273                  */
13274                 tp->write32 = tg3_write_flush_reg32;
13275         }
13276
13277         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13278             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13279                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13280                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13281                         tp->write32_rx_mbox = tg3_write_flush_reg32;
13282         }
13283
13284         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13285                 tp->read32 = tg3_read_indirect_reg32;
13286                 tp->write32 = tg3_write_indirect_reg32;
13287                 tp->read32_mbox = tg3_read_indirect_mbox;
13288                 tp->write32_mbox = tg3_write_indirect_mbox;
13289                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13290                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13291
13292                 iounmap(tp->regs);
13293                 tp->regs = NULL;
13294
13295                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13296                 pci_cmd &= ~PCI_COMMAND_MEMORY;
13297                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13298         }
13299         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13300                 tp->read32_mbox = tg3_read32_mbox_5906;
13301                 tp->write32_mbox = tg3_write32_mbox_5906;
13302                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13303                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13304         }
13305
13306         if (tp->write32 == tg3_write_indirect_reg32 ||
13307             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13308              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13309               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13310                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13311
13312         /* Get eeprom hw config before calling tg3_set_power_state().
13313          * In particular, the TG3_FLG2_IS_NIC flag must be
13314          * determined before calling tg3_set_power_state() so that
13315          * we know whether or not to switch out of Vaux power.
13316          * When the flag is set, it means that GPIO1 is used for eeprom
13317          * write protect and also implies that it is a LOM where GPIOs
13318          * are not used to switch power.
13319          */
13320         tg3_get_eeprom_hw_cfg(tp);
13321
13322         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13323                 /* Allow reads and writes to the
13324                  * APE register and memory space.
13325                  */
13326                 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13327                                  PCISTATE_ALLOW_APE_SHMEM_WR |
13328                                  PCISTATE_ALLOW_APE_PSPACE_WR;
13329                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13330                                        pci_state_reg);
13331         }
13332
13333         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13334             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13335             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13336             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13337             (tp->tg3_flags3 & TG3_FLG3_5717_PLUS))
13338                 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13339
13340         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13341          * GPIO1 driven high will bring 5700's external PHY out of reset.
13342          * It is also used as eeprom write protect on LOMs.
13343          */
13344         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13345         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13346             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13347                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13348                                        GRC_LCLCTRL_GPIO_OUTPUT1);
13349         /* Unused GPIO3 must be driven as output on 5752 because there
13350          * are no pull-up resistors on unused GPIO pins.
13351          */
13352         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13353                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13354
13355         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13356             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13357             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13358                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13359
13360         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13361             tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13362                 /* Turn off the debug UART. */
13363                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13364                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13365                         /* Keep VMain power. */
13366                         tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13367                                               GRC_LCLCTRL_GPIO_OUTPUT0;
13368         }
13369
13370         /* Force the chip into D0. */
13371         err = tg3_set_power_state(tp, PCI_D0);
13372         if (err) {
13373                 dev_err(&tp->pdev->dev, "Transition to D0 failed\n");
13374                 return err;
13375         }
13376
13377         /* Derive initial jumbo mode from MTU assigned in
13378          * ether_setup() via the alloc_etherdev() call
13379          */
13380         if (tp->dev->mtu > ETH_DATA_LEN &&
13381             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13382                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13383
13384         /* Determine WakeOnLan speed to use. */
13385         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13386             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13387             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13388             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13389                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13390         } else {
13391                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13392         }
13393
13394         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13395                 tp->phy_flags |= TG3_PHYFLG_IS_FET;
13396
13397         /* A few boards don't want Ethernet@WireSpeed phy feature */
13398         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13399             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13400              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13401              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13402             (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
13403             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
13404                 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
13405
13406         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13407             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13408                 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
13409         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13410                 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
13411
13412         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13413             !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
13414             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13415             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13416             !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) {
13417                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13418                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13419                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13420                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13421                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13422                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13423                                 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
13424                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13425                                 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
13426                 } else
13427                         tp->phy_flags |= TG3_PHYFLG_BER_BUG;
13428         }
13429
13430         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13431             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13432                 tp->phy_otp = tg3_read_otp_phycfg(tp);
13433                 if (tp->phy_otp == 0)
13434                         tp->phy_otp = TG3_OTP_DEFAULT;
13435         }
13436
13437         if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13438                 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13439         else
13440                 tp->mi_mode = MAC_MI_MODE_BASE;
13441
13442         tp->coalesce_mode = 0;
13443         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13444             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13445                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13446
13447         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13448             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13449                 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13450
13451         err = tg3_mdio_init(tp);
13452         if (err)
13453                 return err;
13454
13455         /* Initialize data/descriptor byte/word swapping. */
13456         val = tr32(GRC_MODE);
13457         val &= GRC_MODE_HOST_STACKUP;
13458         tw32(GRC_MODE, val | tp->grc_mode);
13459
13460         tg3_switch_clocks(tp);
13461
13462         /* Clear this out for sanity. */
13463         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13464
13465         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13466                               &pci_state_reg);
13467         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13468             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13469                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13470
13471                 if (chiprevid == CHIPREV_ID_5701_A0 ||
13472                     chiprevid == CHIPREV_ID_5701_B0 ||
13473                     chiprevid == CHIPREV_ID_5701_B2 ||
13474                     chiprevid == CHIPREV_ID_5701_B5) {
13475                         void __iomem *sram_base;
13476
13477                         /* Write some dummy words into the SRAM status block
13478                          * area, see if it reads back correctly.  If the return
13479                          * value is bad, force enable the PCIX workaround.
13480                          */
13481                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13482
13483                         writel(0x00000000, sram_base);
13484                         writel(0x00000000, sram_base + 4);
13485                         writel(0xffffffff, sram_base + 4);
13486                         if (readl(sram_base) != 0x00000000)
13487                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13488                 }
13489         }
13490
13491         udelay(50);
13492         tg3_nvram_init(tp);
13493
13494         grc_misc_cfg = tr32(GRC_MISC_CFG);
13495         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13496
13497         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13498             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13499              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13500                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13501
13502         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13503             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13504                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13505         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13506                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13507                                       HOSTCC_MODE_CLRTICK_TXBD);
13508
13509                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13510                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13511                                        tp->misc_host_ctrl);
13512         }
13513
13514         /* Preserve the APE MAC_MODE bits */
13515         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13516                 tp->mac_mode = tr32(MAC_MODE) |
13517                                MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13518         else
13519                 tp->mac_mode = TG3_DEF_MAC_MODE;
13520
13521         /* these are limited to 10/100 only */
13522         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13523              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13524             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13525              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13526              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13527               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13528               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13529             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13530              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13531               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13532               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13533             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13534             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
13535             tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
13536             (tp->phy_flags & TG3_PHYFLG_IS_FET))
13537                 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
13538
13539         err = tg3_phy_probe(tp);
13540         if (err) {
13541                 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
13542                 /* ... but do not return immediately ... */
13543                 tg3_mdio_fini(tp);
13544         }
13545
13546         tg3_read_vpd(tp);
13547         tg3_read_fw_ver(tp);
13548
13549         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
13550                 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13551         } else {
13552                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13553                         tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13554                 else
13555                         tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
13556         }
13557
13558         /* 5700 {AX,BX} chips have a broken status block link
13559          * change bit implementation, so we must use the
13560          * status register in those cases.
13561          */
13562         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13563                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13564         else
13565                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13566
13567         /* The led_ctrl is set during tg3_phy_probe, here we might
13568          * have to force the link status polling mechanism based
13569          * upon subsystem IDs.
13570          */
13571         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13572             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13573             !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
13574                 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
13575                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13576         }
13577
13578         /* For all SERDES we poll the MAC status register. */
13579         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13580                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13581         else
13582                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13583
13584         tp->rx_offset = NET_IP_ALIGN + TG3_RX_HEADROOM;
13585         tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
13586         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13587             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
13588                 tp->rx_offset -= NET_IP_ALIGN;
13589 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
13590                 tp->rx_copy_thresh = ~(u16)0;
13591 #endif
13592         }
13593
13594         tp->rx_std_max_post = TG3_RX_RING_SIZE;
13595
13596         /* Increment the rx prod index on the rx std ring by at most
13597          * 8 for these chips to workaround hw errata.
13598          */
13599         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13600             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13601             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13602                 tp->rx_std_max_post = 8;
13603
13604         if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13605                 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13606                                      PCIE_PWR_MGMT_L1_THRESH_MSK;
13607
13608         return err;
13609 }
13610
13611 #ifdef CONFIG_SPARC
13612 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13613 {
13614         struct net_device *dev = tp->dev;
13615         struct pci_dev *pdev = tp->pdev;
13616         struct device_node *dp = pci_device_to_OF_node(pdev);
13617         const unsigned char *addr;
13618         int len;
13619
13620         addr = of_get_property(dp, "local-mac-address", &len);
13621         if (addr && len == 6) {
13622                 memcpy(dev->dev_addr, addr, 6);
13623                 memcpy(dev->perm_addr, dev->dev_addr, 6);
13624                 return 0;
13625         }
13626         return -ENODEV;
13627 }
13628
13629 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13630 {
13631         struct net_device *dev = tp->dev;
13632
13633         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13634         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13635         return 0;
13636 }
13637 #endif
13638
13639 static int __devinit tg3_get_device_address(struct tg3 *tp)
13640 {
13641         struct net_device *dev = tp->dev;
13642         u32 hi, lo, mac_offset;
13643         int addr_ok = 0;
13644
13645 #ifdef CONFIG_SPARC
13646         if (!tg3_get_macaddr_sparc(tp))
13647                 return 0;
13648 #endif
13649
13650         mac_offset = 0x7c;
13651         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13652             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13653                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13654                         mac_offset = 0xcc;
13655                 if (tg3_nvram_lock(tp))
13656                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13657                 else
13658                         tg3_nvram_unlock(tp);
13659         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13660                    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
13661                 if (PCI_FUNC(tp->pdev->devfn) & 1)
13662                         mac_offset = 0xcc;
13663                 if (PCI_FUNC(tp->pdev->devfn) > 1)
13664                         mac_offset += 0x18c;
13665         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13666                 mac_offset = 0x10;
13667
13668         /* First try to get it from MAC address mailbox. */
13669         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13670         if ((hi >> 16) == 0x484b) {
13671                 dev->dev_addr[0] = (hi >>  8) & 0xff;
13672                 dev->dev_addr[1] = (hi >>  0) & 0xff;
13673
13674                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13675                 dev->dev_addr[2] = (lo >> 24) & 0xff;
13676                 dev->dev_addr[3] = (lo >> 16) & 0xff;
13677                 dev->dev_addr[4] = (lo >>  8) & 0xff;
13678                 dev->dev_addr[5] = (lo >>  0) & 0xff;
13679
13680                 /* Some old bootcode may report a 0 MAC address in SRAM */
13681                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13682         }
13683         if (!addr_ok) {
13684                 /* Next, try NVRAM. */
13685                 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13686                     !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13687                     !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13688                         memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13689                         memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13690                 }
13691                 /* Finally just fetch it out of the MAC control regs. */
13692                 else {
13693                         hi = tr32(MAC_ADDR_0_HIGH);
13694                         lo = tr32(MAC_ADDR_0_LOW);
13695
13696                         dev->dev_addr[5] = lo & 0xff;
13697                         dev->dev_addr[4] = (lo >> 8) & 0xff;
13698                         dev->dev_addr[3] = (lo >> 16) & 0xff;
13699                         dev->dev_addr[2] = (lo >> 24) & 0xff;
13700                         dev->dev_addr[1] = hi & 0xff;
13701                         dev->dev_addr[0] = (hi >> 8) & 0xff;
13702                 }
13703         }
13704
13705         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13706 #ifdef CONFIG_SPARC
13707                 if (!tg3_get_default_macaddr_sparc(tp))
13708                         return 0;
13709 #endif
13710                 return -EINVAL;
13711         }
13712         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13713         return 0;
13714 }
13715
13716 #define BOUNDARY_SINGLE_CACHELINE       1
13717 #define BOUNDARY_MULTI_CACHELINE        2
13718
13719 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13720 {
13721         int cacheline_size;
13722         u8 byte;
13723         int goal;
13724
13725         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13726         if (byte == 0)
13727                 cacheline_size = 1024;
13728         else
13729                 cacheline_size = (int) byte * 4;
13730
13731         /* On 5703 and later chips, the boundary bits have no
13732          * effect.
13733          */
13734         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13735             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13736             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13737                 goto out;
13738
13739 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13740         goal = BOUNDARY_MULTI_CACHELINE;
13741 #else
13742 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13743         goal = BOUNDARY_SINGLE_CACHELINE;
13744 #else
13745         goal = 0;
13746 #endif
13747 #endif
13748
13749         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
13750                 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13751                 goto out;
13752         }
13753
13754         if (!goal)
13755                 goto out;
13756
13757         /* PCI controllers on most RISC systems tend to disconnect
13758          * when a device tries to burst across a cache-line boundary.
13759          * Therefore, letting tg3 do so just wastes PCI bandwidth.
13760          *
13761          * Unfortunately, for PCI-E there are only limited
13762          * write-side controls for this, and thus for reads
13763          * we will still get the disconnects.  We'll also waste
13764          * these PCI cycles for both read and write for chips
13765          * other than 5700 and 5701 which do not implement the
13766          * boundary bits.
13767          */
13768         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13769             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13770                 switch (cacheline_size) {
13771                 case 16:
13772                 case 32:
13773                 case 64:
13774                 case 128:
13775                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13776                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13777                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13778                         } else {
13779                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13780                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13781                         }
13782                         break;
13783
13784                 case 256:
13785                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13786                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13787                         break;
13788
13789                 default:
13790                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13791                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13792                         break;
13793                 }
13794         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13795                 switch (cacheline_size) {
13796                 case 16:
13797                 case 32:
13798                 case 64:
13799                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13800                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13801                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13802                                 break;
13803                         }
13804                         /* fallthrough */
13805                 case 128:
13806                 default:
13807                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13808                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13809                         break;
13810                 }
13811         } else {
13812                 switch (cacheline_size) {
13813                 case 16:
13814                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13815                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13816                                         DMA_RWCTRL_WRITE_BNDRY_16);
13817                                 break;
13818                         }
13819                         /* fallthrough */
13820                 case 32:
13821                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13822                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13823                                         DMA_RWCTRL_WRITE_BNDRY_32);
13824                                 break;
13825                         }
13826                         /* fallthrough */
13827                 case 64:
13828                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13829                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13830                                         DMA_RWCTRL_WRITE_BNDRY_64);
13831                                 break;
13832                         }
13833                         /* fallthrough */
13834                 case 128:
13835                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
13836                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13837                                         DMA_RWCTRL_WRITE_BNDRY_128);
13838                                 break;
13839                         }
13840                         /* fallthrough */
13841                 case 256:
13842                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
13843                                 DMA_RWCTRL_WRITE_BNDRY_256);
13844                         break;
13845                 case 512:
13846                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
13847                                 DMA_RWCTRL_WRITE_BNDRY_512);
13848                         break;
13849                 case 1024:
13850                 default:
13851                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13852                                 DMA_RWCTRL_WRITE_BNDRY_1024);
13853                         break;
13854                 }
13855         }
13856
13857 out:
13858         return val;
13859 }
13860
13861 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13862 {
13863         struct tg3_internal_buffer_desc test_desc;
13864         u32 sram_dma_descs;
13865         int i, ret;
13866
13867         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13868
13869         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13870         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13871         tw32(RDMAC_STATUS, 0);
13872         tw32(WDMAC_STATUS, 0);
13873
13874         tw32(BUFMGR_MODE, 0);
13875         tw32(FTQ_RESET, 0);
13876
13877         test_desc.addr_hi = ((u64) buf_dma) >> 32;
13878         test_desc.addr_lo = buf_dma & 0xffffffff;
13879         test_desc.nic_mbuf = 0x00002100;
13880         test_desc.len = size;
13881
13882         /*
13883          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13884          * the *second* time the tg3 driver was getting loaded after an
13885          * initial scan.
13886          *
13887          * Broadcom tells me:
13888          *   ...the DMA engine is connected to the GRC block and a DMA
13889          *   reset may affect the GRC block in some unpredictable way...
13890          *   The behavior of resets to individual blocks has not been tested.
13891          *
13892          * Broadcom noted the GRC reset will also reset all sub-components.
13893          */
13894         if (to_device) {
13895                 test_desc.cqid_sqid = (13 << 8) | 2;
13896
13897                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13898                 udelay(40);
13899         } else {
13900                 test_desc.cqid_sqid = (16 << 8) | 7;
13901
13902                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13903                 udelay(40);
13904         }
13905         test_desc.flags = 0x00000005;
13906
13907         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13908                 u32 val;
13909
13910                 val = *(((u32 *)&test_desc) + i);
13911                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13912                                        sram_dma_descs + (i * sizeof(u32)));
13913                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13914         }
13915         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13916
13917         if (to_device)
13918                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13919         else
13920                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13921
13922         ret = -ENODEV;
13923         for (i = 0; i < 40; i++) {
13924                 u32 val;
13925
13926                 if (to_device)
13927                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13928                 else
13929                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13930                 if ((val & 0xffff) == sram_dma_descs) {
13931                         ret = 0;
13932                         break;
13933                 }
13934
13935                 udelay(100);
13936         }
13937
13938         return ret;
13939 }
13940
13941 #define TEST_BUFFER_SIZE        0x2000
13942
13943 static int __devinit tg3_test_dma(struct tg3 *tp)
13944 {
13945         dma_addr_t buf_dma;
13946         u32 *buf, saved_dma_rwctrl;
13947         int ret = 0;
13948
13949         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13950         if (!buf) {
13951                 ret = -ENOMEM;
13952                 goto out_nofree;
13953         }
13954
13955         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13956                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13957
13958         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13959
13960         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)
13961                 goto out;
13962
13963         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13964                 /* DMA read watermark not used on PCIE */
13965                 tp->dma_rwctrl |= 0x00180000;
13966         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13967                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13968                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13969                         tp->dma_rwctrl |= 0x003f0000;
13970                 else
13971                         tp->dma_rwctrl |= 0x003f000f;
13972         } else {
13973                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13974                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13975                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13976                         u32 read_water = 0x7;
13977
13978                         /* If the 5704 is behind the EPB bridge, we can
13979                          * do the less restrictive ONE_DMA workaround for
13980                          * better performance.
13981                          */
13982                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13983                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13984                                 tp->dma_rwctrl |= 0x8000;
13985                         else if (ccval == 0x6 || ccval == 0x7)
13986                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13987
13988                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13989                                 read_water = 4;
13990                         /* Set bit 23 to enable PCIX hw bug fix */
13991                         tp->dma_rwctrl |=
13992                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13993                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13994                                 (1 << 23);
13995                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13996                         /* 5780 always in PCIX mode */
13997                         tp->dma_rwctrl |= 0x00144000;
13998                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13999                         /* 5714 always in PCIX mode */
14000                         tp->dma_rwctrl |= 0x00148000;
14001                 } else {
14002                         tp->dma_rwctrl |= 0x001b000f;
14003                 }
14004         }
14005
14006         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
14007             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
14008                 tp->dma_rwctrl &= 0xfffffff0;
14009
14010         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
14011             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
14012                 /* Remove this if it causes problems for some boards. */
14013                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
14014
14015                 /* On 5700/5701 chips, we need to set this bit.
14016                  * Otherwise the chip will issue cacheline transactions
14017                  * to streamable DMA memory with not all the byte
14018                  * enables turned on.  This is an error on several
14019                  * RISC PCI controllers, in particular sparc64.
14020                  *
14021                  * On 5703/5704 chips, this bit has been reassigned
14022                  * a different meaning.  In particular, it is used
14023                  * on those chips to enable a PCI-X workaround.
14024                  */
14025                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
14026         }
14027
14028         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14029
14030 #if 0
14031         /* Unneeded, already done by tg3_get_invariants.  */
14032         tg3_switch_clocks(tp);
14033 #endif
14034
14035         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14036             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14037                 goto out;
14038
14039         /* It is best to perform DMA test with maximum write burst size
14040          * to expose the 5700/5701 write DMA bug.
14041          */
14042         saved_dma_rwctrl = tp->dma_rwctrl;
14043         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14044         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14045
14046         while (1) {
14047                 u32 *p = buf, i;
14048
14049                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14050                         p[i] = i;
14051
14052                 /* Send the buffer to the chip. */
14053                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14054                 if (ret) {
14055                         dev_err(&tp->pdev->dev,
14056                                 "%s: Buffer write failed. err = %d\n",
14057                                 __func__, ret);
14058                         break;
14059                 }
14060
14061 #if 0
14062                 /* validate data reached card RAM correctly. */
14063                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14064                         u32 val;
14065                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
14066                         if (le32_to_cpu(val) != p[i]) {
14067                                 dev_err(&tp->pdev->dev,
14068                                         "%s: Buffer corrupted on device! "
14069                                         "(%d != %d)\n", __func__, val, i);
14070                                 /* ret = -ENODEV here? */
14071                         }
14072                         p[i] = 0;
14073                 }
14074 #endif
14075                 /* Now read it back. */
14076                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14077                 if (ret) {
14078                         dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
14079                                 "err = %d\n", __func__, ret);
14080                         break;
14081                 }
14082
14083                 /* Verify it. */
14084                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14085                         if (p[i] == i)
14086                                 continue;
14087
14088                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14089                             DMA_RWCTRL_WRITE_BNDRY_16) {
14090                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14091                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14092                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14093                                 break;
14094                         } else {
14095                                 dev_err(&tp->pdev->dev,
14096                                         "%s: Buffer corrupted on read back! "
14097                                         "(%d != %d)\n", __func__, p[i], i);
14098                                 ret = -ENODEV;
14099                                 goto out;
14100                         }
14101                 }
14102
14103                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14104                         /* Success. */
14105                         ret = 0;
14106                         break;
14107                 }
14108         }
14109         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14110             DMA_RWCTRL_WRITE_BNDRY_16) {
14111                 static struct pci_device_id dma_wait_state_chipsets[] = {
14112                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14113                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14114                         { },
14115                 };
14116
14117                 /* DMA test passed without adjusting DMA boundary,
14118                  * now look for chipsets that are known to expose the
14119                  * DMA bug without failing the test.
14120                  */
14121                 if (pci_dev_present(dma_wait_state_chipsets)) {
14122                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14123                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14124                 } else {
14125                         /* Safe to use the calculated DMA boundary. */
14126                         tp->dma_rwctrl = saved_dma_rwctrl;
14127                 }
14128
14129                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14130         }
14131
14132 out:
14133         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14134 out_nofree:
14135         return ret;
14136 }
14137
14138 static void __devinit tg3_init_link_config(struct tg3 *tp)
14139 {
14140         tp->link_config.advertising =
14141                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14142                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14143                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14144                  ADVERTISED_Autoneg | ADVERTISED_MII);
14145         tp->link_config.speed = SPEED_INVALID;
14146         tp->link_config.duplex = DUPLEX_INVALID;
14147         tp->link_config.autoneg = AUTONEG_ENABLE;
14148         tp->link_config.active_speed = SPEED_INVALID;
14149         tp->link_config.active_duplex = DUPLEX_INVALID;
14150         tp->link_config.orig_speed = SPEED_INVALID;
14151         tp->link_config.orig_duplex = DUPLEX_INVALID;
14152         tp->link_config.orig_autoneg = AUTONEG_INVALID;
14153 }
14154
14155 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14156 {
14157         if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) {
14158                 tp->bufmgr_config.mbuf_read_dma_low_water =
14159                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14160                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14161                         DEFAULT_MB_MACRX_LOW_WATER_57765;
14162                 tp->bufmgr_config.mbuf_high_water =
14163                         DEFAULT_MB_HIGH_WATER_57765;
14164
14165                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14166                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14167                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14168                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14169                 tp->bufmgr_config.mbuf_high_water_jumbo =
14170                         DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14171         } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14172                 tp->bufmgr_config.mbuf_read_dma_low_water =
14173                         DEFAULT_MB_RDMA_LOW_WATER_5705;
14174                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14175                         DEFAULT_MB_MACRX_LOW_WATER_5705;
14176                 tp->bufmgr_config.mbuf_high_water =
14177                         DEFAULT_MB_HIGH_WATER_5705;
14178                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14179                         tp->bufmgr_config.mbuf_mac_rx_low_water =
14180                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
14181                         tp->bufmgr_config.mbuf_high_water =
14182                                 DEFAULT_MB_HIGH_WATER_5906;
14183                 }
14184
14185                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14186                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14187                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14188                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14189                 tp->bufmgr_config.mbuf_high_water_jumbo =
14190                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14191         } else {
14192                 tp->bufmgr_config.mbuf_read_dma_low_water =
14193                         DEFAULT_MB_RDMA_LOW_WATER;
14194                 tp->bufmgr_config.mbuf_mac_rx_low_water =
14195                         DEFAULT_MB_MACRX_LOW_WATER;
14196                 tp->bufmgr_config.mbuf_high_water =
14197                         DEFAULT_MB_HIGH_WATER;
14198
14199                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14200                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14201                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14202                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14203                 tp->bufmgr_config.mbuf_high_water_jumbo =
14204                         DEFAULT_MB_HIGH_WATER_JUMBO;
14205         }
14206
14207         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14208         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14209 }
14210
14211 static char * __devinit tg3_phy_string(struct tg3 *tp)
14212 {
14213         switch (tp->phy_id & TG3_PHY_ID_MASK) {
14214         case TG3_PHY_ID_BCM5400:        return "5400";
14215         case TG3_PHY_ID_BCM5401:        return "5401";
14216         case TG3_PHY_ID_BCM5411:        return "5411";
14217         case TG3_PHY_ID_BCM5701:        return "5701";
14218         case TG3_PHY_ID_BCM5703:        return "5703";
14219         case TG3_PHY_ID_BCM5704:        return "5704";
14220         case TG3_PHY_ID_BCM5705:        return "5705";
14221         case TG3_PHY_ID_BCM5750:        return "5750";
14222         case TG3_PHY_ID_BCM5752:        return "5752";
14223         case TG3_PHY_ID_BCM5714:        return "5714";
14224         case TG3_PHY_ID_BCM5780:        return "5780";
14225         case TG3_PHY_ID_BCM5755:        return "5755";
14226         case TG3_PHY_ID_BCM5787:        return "5787";
14227         case TG3_PHY_ID_BCM5784:        return "5784";
14228         case TG3_PHY_ID_BCM5756:        return "5722/5756";
14229         case TG3_PHY_ID_BCM5906:        return "5906";
14230         case TG3_PHY_ID_BCM5761:        return "5761";
14231         case TG3_PHY_ID_BCM5718C:       return "5718C";
14232         case TG3_PHY_ID_BCM5718S:       return "5718S";
14233         case TG3_PHY_ID_BCM57765:       return "57765";
14234         case TG3_PHY_ID_BCM5719C:       return "5719C";
14235         case TG3_PHY_ID_BCM8002:        return "8002/serdes";
14236         case 0:                 return "serdes";
14237         default:                return "unknown";
14238         }
14239 }
14240
14241 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14242 {
14243         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14244                 strcpy(str, "PCI Express");
14245                 return str;
14246         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14247                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14248
14249                 strcpy(str, "PCIX:");
14250
14251                 if ((clock_ctrl == 7) ||
14252                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14253                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14254                         strcat(str, "133MHz");
14255                 else if (clock_ctrl == 0)
14256                         strcat(str, "33MHz");
14257                 else if (clock_ctrl == 2)
14258                         strcat(str, "50MHz");
14259                 else if (clock_ctrl == 4)
14260                         strcat(str, "66MHz");
14261                 else if (clock_ctrl == 6)
14262                         strcat(str, "100MHz");
14263         } else {
14264                 strcpy(str, "PCI:");
14265                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14266                         strcat(str, "66MHz");
14267                 else
14268                         strcat(str, "33MHz");
14269         }
14270         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14271                 strcat(str, ":32-bit");
14272         else
14273                 strcat(str, ":64-bit");
14274         return str;
14275 }
14276
14277 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14278 {
14279         struct pci_dev *peer;
14280         unsigned int func, devnr = tp->pdev->devfn & ~7;
14281
14282         for (func = 0; func < 8; func++) {
14283                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14284                 if (peer && peer != tp->pdev)
14285                         break;
14286                 pci_dev_put(peer);
14287         }
14288         /* 5704 can be configured in single-port mode, set peer to
14289          * tp->pdev in that case.
14290          */
14291         if (!peer) {
14292                 peer = tp->pdev;
14293                 return peer;
14294         }
14295
14296         /*
14297          * We don't need to keep the refcount elevated; there's no way
14298          * to remove one half of this device without removing the other
14299          */
14300         pci_dev_put(peer);
14301
14302         return peer;
14303 }
14304
14305 static void __devinit tg3_init_coal(struct tg3 *tp)
14306 {
14307         struct ethtool_coalesce *ec = &tp->coal;
14308
14309         memset(ec, 0, sizeof(*ec));
14310         ec->cmd = ETHTOOL_GCOALESCE;
14311         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14312         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14313         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14314         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14315         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14316         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14317         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14318         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14319         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14320
14321         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14322                                  HOSTCC_MODE_CLRTICK_TXBD)) {
14323                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14324                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14325                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14326                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14327         }
14328
14329         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14330                 ec->rx_coalesce_usecs_irq = 0;
14331                 ec->tx_coalesce_usecs_irq = 0;
14332                 ec->stats_block_coalesce_usecs = 0;
14333         }
14334 }
14335
14336 static const struct net_device_ops tg3_netdev_ops = {
14337         .ndo_open               = tg3_open,
14338         .ndo_stop               = tg3_close,
14339         .ndo_start_xmit         = tg3_start_xmit,
14340         .ndo_get_stats64        = tg3_get_stats64,
14341         .ndo_validate_addr      = eth_validate_addr,
14342         .ndo_set_multicast_list = tg3_set_rx_mode,
14343         .ndo_set_mac_address    = tg3_set_mac_addr,
14344         .ndo_do_ioctl           = tg3_ioctl,
14345         .ndo_tx_timeout         = tg3_tx_timeout,
14346         .ndo_change_mtu         = tg3_change_mtu,
14347 #if TG3_VLAN_TAG_USED
14348         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14349 #endif
14350 #ifdef CONFIG_NET_POLL_CONTROLLER
14351         .ndo_poll_controller    = tg3_poll_controller,
14352 #endif
14353 };
14354
14355 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14356         .ndo_open               = tg3_open,
14357         .ndo_stop               = tg3_close,
14358         .ndo_start_xmit         = tg3_start_xmit_dma_bug,
14359         .ndo_get_stats64        = tg3_get_stats64,
14360         .ndo_validate_addr      = eth_validate_addr,
14361         .ndo_set_multicast_list = tg3_set_rx_mode,
14362         .ndo_set_mac_address    = tg3_set_mac_addr,
14363         .ndo_do_ioctl           = tg3_ioctl,
14364         .ndo_tx_timeout         = tg3_tx_timeout,
14365         .ndo_change_mtu         = tg3_change_mtu,
14366 #if TG3_VLAN_TAG_USED
14367         .ndo_vlan_rx_register   = tg3_vlan_rx_register,
14368 #endif
14369 #ifdef CONFIG_NET_POLL_CONTROLLER
14370         .ndo_poll_controller    = tg3_poll_controller,
14371 #endif
14372 };
14373
14374 static int __devinit tg3_init_one(struct pci_dev *pdev,
14375                                   const struct pci_device_id *ent)
14376 {
14377         struct net_device *dev;
14378         struct tg3 *tp;
14379         int i, err, pm_cap;
14380         u32 sndmbx, rcvmbx, intmbx;
14381         char str[40];
14382         u64 dma_mask, persist_dma_mask;
14383
14384         printk_once(KERN_INFO "%s\n", version);
14385
14386         err = pci_enable_device(pdev);
14387         if (err) {
14388                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
14389                 return err;
14390         }
14391
14392         err = pci_request_regions(pdev, DRV_MODULE_NAME);
14393         if (err) {
14394                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
14395                 goto err_out_disable_pdev;
14396         }
14397
14398         pci_set_master(pdev);
14399
14400         /* Find power-management capability. */
14401         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14402         if (pm_cap == 0) {
14403                 dev_err(&pdev->dev,
14404                         "Cannot find Power Management capability, aborting\n");
14405                 err = -EIO;
14406                 goto err_out_free_res;
14407         }
14408
14409         dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14410         if (!dev) {
14411                 dev_err(&pdev->dev, "Etherdev alloc failed, aborting\n");
14412                 err = -ENOMEM;
14413                 goto err_out_free_res;
14414         }
14415
14416         SET_NETDEV_DEV(dev, &pdev->dev);
14417
14418 #if TG3_VLAN_TAG_USED
14419         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14420 #endif
14421
14422         tp = netdev_priv(dev);
14423         tp->pdev = pdev;
14424         tp->dev = dev;
14425         tp->pm_cap = pm_cap;
14426         tp->rx_mode = TG3_DEF_RX_MODE;
14427         tp->tx_mode = TG3_DEF_TX_MODE;
14428
14429         if (tg3_debug > 0)
14430                 tp->msg_enable = tg3_debug;
14431         else
14432                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14433
14434         /* The word/byte swap controls here control register access byte
14435          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
14436          * setting below.
14437          */
14438         tp->misc_host_ctrl =
14439                 MISC_HOST_CTRL_MASK_PCI_INT |
14440                 MISC_HOST_CTRL_WORD_SWAP |
14441                 MISC_HOST_CTRL_INDIR_ACCESS |
14442                 MISC_HOST_CTRL_PCISTATE_RW;
14443
14444         /* The NONFRM (non-frame) byte/word swap controls take effect
14445          * on descriptor entries, anything which isn't packet data.
14446          *
14447          * The StrongARM chips on the board (one for tx, one for rx)
14448          * are running in big-endian mode.
14449          */
14450         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14451                         GRC_MODE_WSWAP_NONFRM_DATA);
14452 #ifdef __BIG_ENDIAN
14453         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14454 #endif
14455         spin_lock_init(&tp->lock);
14456         spin_lock_init(&tp->indirect_lock);
14457         INIT_WORK(&tp->reset_task, tg3_reset_task);
14458
14459         tp->regs = pci_ioremap_bar(pdev, BAR_0);
14460         if (!tp->regs) {
14461                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
14462                 err = -ENOMEM;
14463                 goto err_out_free_dev;
14464         }
14465
14466         tg3_init_link_config(tp);
14467
14468         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14469         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14470
14471         dev->ethtool_ops = &tg3_ethtool_ops;
14472         dev->watchdog_timeo = TG3_TX_TIMEOUT;
14473         dev->irq = pdev->irq;
14474
14475         err = tg3_get_invariants(tp);
14476         if (err) {
14477                 dev_err(&pdev->dev,
14478                         "Problem fetching invariants of chip, aborting\n");
14479                 goto err_out_iounmap;
14480         }
14481
14482         if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14483             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
14484             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719)
14485                 dev->netdev_ops = &tg3_netdev_ops;
14486         else
14487                 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14488
14489
14490         /* The EPB bridge inside 5714, 5715, and 5780 and any
14491          * device behind the EPB cannot support DMA addresses > 40-bit.
14492          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14493          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14494          * do DMA address check in tg3_start_xmit().
14495          */
14496         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14497                 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14498         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14499                 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14500 #ifdef CONFIG_HIGHMEM
14501                 dma_mask = DMA_BIT_MASK(64);
14502 #endif
14503         } else
14504                 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14505
14506         /* Configure DMA attributes. */
14507         if (dma_mask > DMA_BIT_MASK(32)) {
14508                 err = pci_set_dma_mask(pdev, dma_mask);
14509                 if (!err) {
14510                         dev->features |= NETIF_F_HIGHDMA;
14511                         err = pci_set_consistent_dma_mask(pdev,
14512                                                           persist_dma_mask);
14513                         if (err < 0) {
14514                                 dev_err(&pdev->dev, "Unable to obtain 64 bit "
14515                                         "DMA for consistent allocations\n");
14516                                 goto err_out_iounmap;
14517                         }
14518                 }
14519         }
14520         if (err || dma_mask == DMA_BIT_MASK(32)) {
14521                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14522                 if (err) {
14523                         dev_err(&pdev->dev,
14524                                 "No usable DMA configuration, aborting\n");
14525                         goto err_out_iounmap;
14526                 }
14527         }
14528
14529         tg3_init_bufmgr_config(tp);
14530
14531         /* Selectively allow TSO based on operating conditions */
14532         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14533             (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14534                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14535         else {
14536                 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14537                 tp->fw_needed = NULL;
14538         }
14539
14540         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14541                 tp->fw_needed = FIRMWARE_TG3;
14542
14543         /* TSO is on by default on chips that support hardware TSO.
14544          * Firmware TSO on older chips gives lower performance, so it
14545          * is off by default, but can be enabled using ethtool.
14546          */
14547         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14548             (dev->features & NETIF_F_IP_CSUM)) {
14549                 dev->features |= NETIF_F_TSO;
14550                 vlan_features_add(dev, NETIF_F_TSO);
14551         }
14552         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14553             (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14554                 if (dev->features & NETIF_F_IPV6_CSUM) {
14555                         dev->features |= NETIF_F_TSO6;
14556                         vlan_features_add(dev, NETIF_F_TSO6);
14557                 }
14558                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14559                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14560                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14561                      GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14562                         GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14563                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
14564                         dev->features |= NETIF_F_TSO_ECN;
14565                         vlan_features_add(dev, NETIF_F_TSO_ECN);
14566                 }
14567         }
14568
14569         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14570             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14571             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14572                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14573                 tp->rx_pending = 63;
14574         }
14575
14576         err = tg3_get_device_address(tp);
14577         if (err) {
14578                 dev_err(&pdev->dev,
14579                         "Could not obtain valid ethernet address, aborting\n");
14580                 goto err_out_iounmap;
14581         }
14582
14583         if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14584                 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14585                 if (!tp->aperegs) {
14586                         dev_err(&pdev->dev,
14587                                 "Cannot map APE registers, aborting\n");
14588                         err = -ENOMEM;
14589                         goto err_out_iounmap;
14590                 }
14591
14592                 tg3_ape_lock_init(tp);
14593
14594                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14595                         tg3_read_dash_ver(tp);
14596         }
14597
14598         /*
14599          * Reset chip in case UNDI or EFI driver did not shutdown
14600          * DMA self test will enable WDMAC and we'll see (spurious)
14601          * pending DMA on the PCI bus at that point.
14602          */
14603         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14604             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14605                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14606                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14607         }
14608
14609         err = tg3_test_dma(tp);
14610         if (err) {
14611                 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
14612                 goto err_out_apeunmap;
14613         }
14614
14615         /* flow control autonegotiation is default behavior */
14616         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14617         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14618
14619         intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14620         rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14621         sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14622         for (i = 0; i < tp->irq_max; i++) {
14623                 struct tg3_napi *tnapi = &tp->napi[i];
14624
14625                 tnapi->tp = tp;
14626                 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14627
14628                 tnapi->int_mbox = intmbx;
14629                 if (i < 4)
14630                         intmbx += 0x8;
14631                 else
14632                         intmbx += 0x4;
14633
14634                 tnapi->consmbox = rcvmbx;
14635                 tnapi->prodmbox = sndmbx;
14636
14637                 if (i)
14638                         tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14639                 else
14640                         tnapi->coal_now = HOSTCC_MODE_NOW;
14641
14642                 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14643                         break;
14644
14645                 /*
14646                  * If we support MSIX, we'll be using RSS.  If we're using
14647                  * RSS, the first vector only handles link interrupts and the
14648                  * remaining vectors handle rx and tx interrupts.  Reuse the
14649                  * mailbox values for the next iteration.  The values we setup
14650                  * above are still useful for the single vectored mode.
14651                  */
14652                 if (!i)
14653                         continue;
14654
14655                 rcvmbx += 0x8;
14656
14657                 if (sndmbx & 0x4)
14658                         sndmbx -= 0x4;
14659                 else
14660                         sndmbx += 0xc;
14661         }
14662
14663         tg3_init_coal(tp);
14664
14665         pci_set_drvdata(pdev, dev);
14666
14667         err = register_netdev(dev);
14668         if (err) {
14669                 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
14670                 goto err_out_apeunmap;
14671         }
14672
14673         netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14674                     tp->board_part_number,
14675                     tp->pci_chip_rev_id,
14676                     tg3_bus_string(tp, str),
14677                     dev->dev_addr);
14678
14679         if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
14680                 struct phy_device *phydev;
14681                 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14682                 netdev_info(dev,
14683                             "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14684                             phydev->drv->name, dev_name(&phydev->dev));
14685         } else {
14686                 char *ethtype;
14687
14688                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
14689                         ethtype = "10/100Base-TX";
14690                 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
14691                         ethtype = "1000Base-SX";
14692                 else
14693                         ethtype = "10/100/1000Base-T";
14694
14695                 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
14696                             "(WireSpeed[%d])\n", tg3_phy_string(tp), ethtype,
14697                           (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0);
14698         }
14699
14700         netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14701                     (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14702                     (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14703                     (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
14704                     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14705                     (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14706         netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14707                     tp->dma_rwctrl,
14708                     pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
14709                     ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
14710
14711         return 0;
14712
14713 err_out_apeunmap:
14714         if (tp->aperegs) {
14715                 iounmap(tp->aperegs);
14716                 tp->aperegs = NULL;
14717         }
14718
14719 err_out_iounmap:
14720         if (tp->regs) {
14721                 iounmap(tp->regs);
14722                 tp->regs = NULL;
14723         }
14724
14725 err_out_free_dev:
14726         free_netdev(dev);
14727
14728 err_out_free_res:
14729         pci_release_regions(pdev);
14730
14731 err_out_disable_pdev:
14732         pci_disable_device(pdev);
14733         pci_set_drvdata(pdev, NULL);
14734         return err;
14735 }
14736
14737 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14738 {
14739         struct net_device *dev = pci_get_drvdata(pdev);
14740
14741         if (dev) {
14742                 struct tg3 *tp = netdev_priv(dev);
14743
14744                 if (tp->fw)
14745                         release_firmware(tp->fw);
14746
14747                 flush_scheduled_work();
14748
14749                 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14750                         tg3_phy_fini(tp);
14751                         tg3_mdio_fini(tp);
14752                 }
14753
14754                 unregister_netdev(dev);
14755                 if (tp->aperegs) {
14756                         iounmap(tp->aperegs);
14757                         tp->aperegs = NULL;
14758                 }
14759                 if (tp->regs) {
14760                         iounmap(tp->regs);
14761                         tp->regs = NULL;
14762                 }
14763                 free_netdev(dev);
14764                 pci_release_regions(pdev);
14765                 pci_disable_device(pdev);
14766                 pci_set_drvdata(pdev, NULL);
14767         }
14768 }
14769
14770 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14771 {
14772         struct net_device *dev = pci_get_drvdata(pdev);
14773         struct tg3 *tp = netdev_priv(dev);
14774         pci_power_t target_state;
14775         int err;
14776
14777         /* PCI register 4 needs to be saved whether netif_running() or not.
14778          * MSI address and data need to be saved if using MSI and
14779          * netif_running().
14780          */
14781         pci_save_state(pdev);
14782
14783         if (!netif_running(dev))
14784                 return 0;
14785
14786         flush_scheduled_work();
14787         tg3_phy_stop(tp);
14788         tg3_netif_stop(tp);
14789
14790         del_timer_sync(&tp->timer);
14791
14792         tg3_full_lock(tp, 1);
14793         tg3_disable_ints(tp);
14794         tg3_full_unlock(tp);
14795
14796         netif_device_detach(dev);
14797
14798         tg3_full_lock(tp, 0);
14799         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14800         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14801         tg3_full_unlock(tp);
14802
14803         target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14804
14805         err = tg3_set_power_state(tp, target_state);
14806         if (err) {
14807                 int err2;
14808
14809                 tg3_full_lock(tp, 0);
14810
14811                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14812                 err2 = tg3_restart_hw(tp, 1);
14813                 if (err2)
14814                         goto out;
14815
14816                 tp->timer.expires = jiffies + tp->timer_offset;
14817                 add_timer(&tp->timer);
14818
14819                 netif_device_attach(dev);
14820                 tg3_netif_start(tp);
14821
14822 out:
14823                 tg3_full_unlock(tp);
14824
14825                 if (!err2)
14826                         tg3_phy_start(tp);
14827         }
14828
14829         return err;
14830 }
14831
14832 static int tg3_resume(struct pci_dev *pdev)
14833 {
14834         struct net_device *dev = pci_get_drvdata(pdev);
14835         struct tg3 *tp = netdev_priv(dev);
14836         int err;
14837
14838         pci_restore_state(tp->pdev);
14839
14840         if (!netif_running(dev))
14841                 return 0;
14842
14843         err = tg3_set_power_state(tp, PCI_D0);
14844         if (err)
14845                 return err;
14846
14847         netif_device_attach(dev);
14848
14849         tg3_full_lock(tp, 0);
14850
14851         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14852         err = tg3_restart_hw(tp, 1);
14853         if (err)
14854                 goto out;
14855
14856         tp->timer.expires = jiffies + tp->timer_offset;
14857         add_timer(&tp->timer);
14858
14859         tg3_netif_start(tp);
14860
14861 out:
14862         tg3_full_unlock(tp);
14863
14864         if (!err)
14865                 tg3_phy_start(tp);
14866
14867         return err;
14868 }
14869
14870 static struct pci_driver tg3_driver = {
14871         .name           = DRV_MODULE_NAME,
14872         .id_table       = tg3_pci_tbl,
14873         .probe          = tg3_init_one,
14874         .remove         = __devexit_p(tg3_remove_one),
14875         .suspend        = tg3_suspend,
14876         .resume         = tg3_resume
14877 };
14878
14879 static int __init tg3_init(void)
14880 {
14881         return pci_register_driver(&tg3_driver);
14882 }
14883
14884 static void __exit tg3_cleanup(void)
14885 {
14886         pci_unregister_driver(&tg3_driver);
14887 }
14888
14889 module_init(tg3_init);
14890 module_exit(tg3_cleanup);