drivers/net/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5   Copyright (C) 2007-2009  STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/kernel.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/ip.h>
  39 #include <linux/tcp.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_ether.h>
  43 #include <linux/crc32.h>
  44 #include <linux/mii.h>
  45 #include <linux/phy.h>
  46 #include <linux/if_vlan.h>
  47 #include <linux/dma-mapping.h>
  48 #include "stmmac.h"
  49
  50 #define STMMAC_RESOURCE_NAME    "stmmaceth"
  51 #define PHY_RESOURCE_NAME       "stmmacphy"
  52
  53 #undef STMMAC_DEBUG
  54 /*#define STMMAC_DEBUG*/
  55 #ifdef STMMAC_DEBUG
  56 #define DBG(nlevel, klevel, fmt, args...) \
  57                 ((void)(netif_msg_##nlevel(priv) && \
  58                 printk(KERN_##klevel fmt, ## args)))
  59 #else
  60 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  61 #endif
  62
  63 #undef STMMAC_RX_DEBUG
  64 /*#define STMMAC_RX_DEBUG*/
  65 #ifdef STMMAC_RX_DEBUG
  66 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  67 #else
  68 #define RX_DBG(fmt, args...)  do { } while (0)
  69 #endif
  70
  71 #undef STMMAC_XMIT_DEBUG
  72 /*#define STMMAC_XMIT_DEBUG*/
  73 #ifdef STMMAC_TX_DEBUG
  74 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  75 #else
  76 #define TX_DBG(fmt, args...)  do { } while (0)
  77 #endif
  78
  79 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  80 #define JUMBO_LEN       9000
  81
  82 /* Module parameters */
  83 #define TX_TIMEO 5000 /* default 5 seconds */
  84 static int watchdog = TX_TIMEO;
  85 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  86 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  87
  88 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  89 module_param(debug, int, S_IRUGO | S_IWUSR);
  90 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  91
  92 static int phyaddr = -1;
  93 module_param(phyaddr, int, S_IRUGO);
  94 MODULE_PARM_DESC(phyaddr, "Physical device address");
  95
  96 #define DMA_TX_SIZE 256
  97 static int dma_txsize = DMA_TX_SIZE;
  98 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  99 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
 100
 101 #define DMA_RX_SIZE 256
 102 static int dma_rxsize = DMA_RX_SIZE;
 103 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 104 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 105
 106 static int flow_ctrl = FLOW_OFF;
 107 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 108 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 109
 110 static int pause = PAUSE_TIME;
 111 module_param(pause, int, S_IRUGO | S_IWUSR);
 112 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 113
 114 #define TC_DEFAULT 64
 115 static int tc = TC_DEFAULT;
 116 module_param(tc, int, S_IRUGO | S_IWUSR);
 117 MODULE_PARM_DESC(tc, "DMA threshold control value");
 118
 119 #define RX_NO_COALESCE  1       /* Always interrupt on completion */
 120 #define TX_NO_COALESCE  -1      /* No moderation by default */
 121
 122 /* Pay attention to tune this parameter; take care of both
 123  * hardware capability and network stabitily/performance impact.
 124  * Many tests showed that ~4ms latency seems to be good enough. */
 125 #ifdef CONFIG_STMMAC_TIMER
 126 #define DEFAULT_PERIODIC_RATE   256
 127 static int tmrate = DEFAULT_PERIODIC_RATE;
 128 module_param(tmrate, int, S_IRUGO | S_IWUSR);
 129 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)");
 130 #endif
 131
 132 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 133 static int buf_sz = DMA_BUFFER_SIZE;
 134 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 135 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 136
 137 /* In case of Giga ETH, we can enable/disable the COE for the
 138  * transmit HW checksum computation.
 139  * Note that, if tx csum is off in HW, SG will be still supported. */
 140 static int tx_coe = HW_CSUM;
 141 module_param(tx_coe, int, S_IRUGO | S_IWUSR);
 142 MODULE_PARM_DESC(tx_coe, "GMAC COE type 2 [on/off]");
 143
 144 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 145                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 146                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 147
 148 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 149 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev);
 150
 151 /**
 152  * stmmac_verify_args - verify the driver parameters.
 153  * Description: it verifies if some wrong parameter is passed to the driver.
 154  * Note that wrong parameters are replaced with the default values.
 155  */
 156 static void stmmac_verify_args(void)
 157 {
 158         if (unlikely(watchdog < 0))
 159                 watchdog = TX_TIMEO;
 160         if (unlikely(dma_rxsize < 0))
 161                 dma_rxsize = DMA_RX_SIZE;
 162         if (unlikely(dma_txsize < 0))
 163                 dma_txsize = DMA_TX_SIZE;
 164         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 165                 buf_sz = DMA_BUFFER_SIZE;
 166         if (unlikely(flow_ctrl > 1))
 167                 flow_ctrl = FLOW_AUTO;
 168         else if (likely(flow_ctrl < 0))
 169                 flow_ctrl = FLOW_OFF;
 170         if (unlikely((pause < 0) || (pause > 0xffff)))
 171                 pause = PAUSE_TIME;
 172
 173         return;
 174 }
 175
 176 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 177 static void print_pkt(unsigned char *buf, int len)
 178 {
 179         int j;
 180         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 181         for (j = 0; j < len; j++) {
 182                 if ((j % 16) == 0)
 183                         pr_info("\n %03x:", j);
 184                 pr_info(" %02x", buf[j]);
 185         }
 186         pr_info("\n");
 187         return;
 188 }
 189 #endif
 190
 191 /* minimum number of free TX descriptors required to wake up TX process */
 192 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 193
 194 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 195 {
 196         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 197 }
 198
 199 /**
 200  * stmmac_adjust_link
 201  * @dev: net device structure
 202  * Description: it adjusts the link parameters.
 203  */
 204 static void stmmac_adjust_link(struct net_device *dev)
 205 {
 206         struct stmmac_priv *priv = netdev_priv(dev);
 207         struct phy_device *phydev = priv->phydev;
 208         unsigned long ioaddr = dev->base_addr;
 209         unsigned long flags;
 210         int new_state = 0;
 211         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 212
 213         if (phydev == NULL)
 214                 return;
 215
 216         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 217             phydev->addr, phydev->link);
 218
 219         spin_lock_irqsave(&priv->lock, flags);
 220         if (phydev->link) {
 221                 u32 ctrl = readl(ioaddr + MAC_CTRL_REG);
 222
 223                 /* Now we make sure that we can be in full duplex mode.
 224                  * If not, we operate in half-duplex mode. */
 225                 if (phydev->duplex != priv->oldduplex) {
 226                         new_state = 1;
 227                         if (!(phydev->duplex))
 228                                 ctrl &= ~priv->hw->link.duplex;
 229                         else
 230                                 ctrl |= priv->hw->link.duplex;
 231                         priv->oldduplex = phydev->duplex;
 232                 }
 233                 /* Flow Control operation */
 234                 if (phydev->pause)
 235                         priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex,
 236                                                  fc, pause_time);
 237
 238                 if (phydev->speed != priv->speed) {
 239                         new_state = 1;
 240                         switch (phydev->speed) {
 241                         case 1000:
 242                                 if (likely(priv->is_gmac))
 243                                         ctrl &= ~priv->hw->link.port;
 244                                 break;
 245                         case 100:
 246                         case 10:
 247                                 if (priv->is_gmac) {
 248                                         ctrl |= priv->hw->link.port;
 249                                         if (phydev->speed == SPEED_100) {
 250                                                 ctrl |= priv->hw->link.speed;
 251                                         } else {
 252                                                 ctrl &= ~(priv->hw->link.speed);
 253                                         }
 254                                 } else {
 255                                         ctrl &= ~priv->hw->link.port;
 256                                 }
 257                                 if (likely(priv->fix_mac_speed))
 258                                         priv->fix_mac_speed(priv->bsp_priv,
 259                                                             phydev->speed);
 260                                 break;
 261                         default:
 262                                 if (netif_msg_link(priv))
 263                                         pr_warning("%s: Speed (%d) is not 10"
 264                                        " or 100!\n", dev->name, phydev->speed);
 265                                 break;
 266                         }
 267
 268                         priv->speed = phydev->speed;
 269                 }
 270
 271                 writel(ctrl, ioaddr + MAC_CTRL_REG);
 272
 273                 if (!priv->oldlink) {
 274                         new_state = 1;
 275                         priv->oldlink = 1;
 276                 }
 277         } else if (priv->oldlink) {
 278                 new_state = 1;
 279                 priv->oldlink = 0;
 280                 priv->speed = 0;
 281                 priv->oldduplex = -1;
 282         }
 283
 284         if (new_state && netif_msg_link(priv))
 285                 phy_print_status(phydev);
 286
 287         spin_unlock_irqrestore(&priv->lock, flags);
 288
 289         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 290 }
 291
 292 /**
 293  * stmmac_init_phy - PHY initialization
 294  * @dev: net device structure
 295  * Description: it initializes the driver's PHY state, and attaches the PHY
 296  * to the mac driver.
 297  *  Return value:
 298  *  0 on success
 299  */
 300 static int stmmac_init_phy(struct net_device *dev)
 301 {
 302         struct stmmac_priv *priv = netdev_priv(dev);
 303         struct phy_device *phydev;
 304         char phy_id[MII_BUS_ID_SIZE + 3];
 305         char bus_id[MII_BUS_ID_SIZE];
 306
 307         priv->oldlink = 0;
 308         priv->speed = 0;
 309         priv->oldduplex = -1;
 310
 311         if (priv->phy_addr == -1) {
 312                 /* We don't have a PHY, so do nothing */
 313                 return 0;
 314         }
 315
 316         snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
 317         snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 318                  priv->phy_addr);
 319         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id);
 320
 321         phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
 322                         priv->phy_interface);
 323
 324         if (IS_ERR(phydev)) {
 325                 pr_err("%s: Could not attach to PHY\n", dev->name);
 326                 return PTR_ERR(phydev);
 327         }
 328
 329         /*
 330          * Broken HW is sometimes missing the pull-up resistor on the
 331          * MDIO line, which results in reads to non-existent devices returning
 332          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 333          * device as well.
 334          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 335          */
 336         if (phydev->phy_id == 0) {
 337                 phy_disconnect(phydev);
 338                 return -ENODEV;
 339         }
 340         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 341                " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 342
 343         priv->phydev = phydev;
 344
 345         return 0;
 346 }
 347
 348 static inline void stmmac_mac_enable_rx(unsigned long ioaddr)
 349 {
 350         u32 value = readl(ioaddr + MAC_CTRL_REG);
 351         value |= MAC_RNABLE_RX;
 352         /* Set the RE (receive enable bit into the MAC CTRL register).  */
 353         writel(value, ioaddr + MAC_CTRL_REG);
 354 }
 355
 356 static inline void stmmac_mac_enable_tx(unsigned long ioaddr)
 357 {
 358         u32 value = readl(ioaddr + MAC_CTRL_REG);
 359         value |= MAC_ENABLE_TX;
 360         /* Set the TE (transmit enable bit into the MAC CTRL register).  */
 361         writel(value, ioaddr + MAC_CTRL_REG);
 362 }
 363
 364 static inline void stmmac_mac_disable_rx(unsigned long ioaddr)
 365 {
 366         u32 value = readl(ioaddr + MAC_CTRL_REG);
 367         value &= ~MAC_RNABLE_RX;
 368         writel(value, ioaddr + MAC_CTRL_REG);
 369 }
 370
 371 static inline void stmmac_mac_disable_tx(unsigned long ioaddr)
 372 {
 373         u32 value = readl(ioaddr + MAC_CTRL_REG);
 374         value &= ~MAC_ENABLE_TX;
 375         writel(value, ioaddr + MAC_CTRL_REG);
 376 }
 377
 378 /**
 379  * display_ring
 380  * @p: pointer to the ring.
 381  * @size: size of the ring.
 382  * Description: display all the descriptors within the ring.
 383  */
 384 static void display_ring(struct dma_desc *p, int size)
 385 {
 386         struct tmp_s {
 387                 u64 a;
 388                 unsigned int b;
 389                 unsigned int c;
 390         };
 391         int i;
 392         for (i = 0; i < size; i++) {
 393                 struct tmp_s *x = (struct tmp_s *)(p + i);
 394                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 395                        i, (unsigned int)virt_to_phys(&p[i]),
 396                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 397                        x->b, x->c);
 398                 pr_info("\n");
 399         }
 400 }
 401
 402 /**
 403  * init_dma_desc_rings - init the RX/TX descriptor rings
 404  * @dev: net device structure
 405  * Description:  this function initializes the DMA RX/TX descriptors
 406  * and allocates the socket buffers.
 407  */
 408 static void init_dma_desc_rings(struct net_device *dev)
 409 {
 410         int i;
 411         struct stmmac_priv *priv = netdev_priv(dev);
 412         struct sk_buff *skb;
 413         unsigned int txsize = priv->dma_tx_size;
 414         unsigned int rxsize = priv->dma_rx_size;
 415         unsigned int bfsize = priv->dma_buf_sz;
 416         int buff2_needed = 0, dis_ic = 0;
 417
 418         /* Set the Buffer size according to the MTU;
 419          * indeed, in case of jumbo we need to bump-up the buffer sizes.
 420          */
 421         if (unlikely(dev->mtu >= BUF_SIZE_8KiB))
 422                 bfsize = BUF_SIZE_16KiB;
 423         else if (unlikely(dev->mtu >= BUF_SIZE_4KiB))
 424                 bfsize = BUF_SIZE_8KiB;
 425         else if (unlikely(dev->mtu >= BUF_SIZE_2KiB))
 426                 bfsize = BUF_SIZE_4KiB;
 427         else if (unlikely(dev->mtu >= DMA_BUFFER_SIZE))
 428                 bfsize = BUF_SIZE_2KiB;
 429         else
 430                 bfsize = DMA_BUFFER_SIZE;
 431
 432 #ifdef CONFIG_STMMAC_TIMER
 433         /* Disable interrupts on completion for the reception if timer is on */
 434         if (likely(priv->tm->enable))
 435                 dis_ic = 1;
 436 #endif
 437         /* If the MTU exceeds 8k so use the second buffer in the chain */
 438         if (bfsize >= BUF_SIZE_8KiB)
 439                 buff2_needed = 1;
 440
 441         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 442             txsize, rxsize, bfsize);
 443
 444         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
 445         priv->rx_skbuff =
 446             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
 447         priv->dma_rx =
 448             (struct dma_desc *)dma_alloc_coherent(priv->device,
 449                                                   rxsize *
 450                                                   sizeof(struct dma_desc),
 451                                                   &priv->dma_rx_phy,
 452                                                   GFP_KERNEL);
 453         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
 454                                        GFP_KERNEL);
 455         priv->dma_tx =
 456             (struct dma_desc *)dma_alloc_coherent(priv->device,
 457                                                   txsize *
 458                                                   sizeof(struct dma_desc),
 459                                                   &priv->dma_tx_phy,
 460                                                   GFP_KERNEL);
 461
 462         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
 463                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
 464                 return;
 465         }
 466
 467         DBG(probe, INFO, "stmmac (%s) DMA desc rings: virt addr (Rx %p, "
 468             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 469             dev->name, priv->dma_rx, priv->dma_tx,
 470             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 471
 472         /* RX INITIALIZATION */
 473         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 474                          "skb\t\tskb data\tdma data\n");
 475
 476         for (i = 0; i < rxsize; i++) {
 477                 struct dma_desc *p = priv->dma_rx + i;
 478
 479                 skb = netdev_alloc_skb_ip_align(dev, bfsize);
 480                 if (unlikely(skb == NULL)) {
 481                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 482                         break;
 483                 }
 484                 priv->rx_skbuff[i] = skb;
 485                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 486                                                 bfsize, DMA_FROM_DEVICE);
 487
 488                 p->des2 = priv->rx_skbuff_dma[i];
 489                 if (unlikely(buff2_needed))
 490                         p->des3 = p->des2 + BUF_SIZE_8KiB;
 491                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 492                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 493         }
 494         priv->cur_rx = 0;
 495         priv->dirty_rx = (unsigned int)(i - rxsize);
 496         priv->dma_buf_sz = bfsize;
 497         buf_sz = bfsize;
 498
 499         /* TX INITIALIZATION */
 500         for (i = 0; i < txsize; i++) {
 501                 priv->tx_skbuff[i] = NULL;
 502                 priv->dma_tx[i].des2 = 0;
 503         }
 504         priv->dirty_tx = 0;
 505         priv->cur_tx = 0;
 506
 507         /* Clear the Rx/Tx descriptors */
 508         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 509         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
 510
 511         if (netif_msg_hw(priv)) {
 512                 pr_info("RX descriptor ring:\n");
 513                 display_ring(priv->dma_rx, rxsize);
 514                 pr_info("TX descriptor ring:\n");
 515                 display_ring(priv->dma_tx, txsize);
 516         }
 517         return;
 518 }
 519
 520 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 521 {
 522         int i;
 523
 524         for (i = 0; i < priv->dma_rx_size; i++) {
 525                 if (priv->rx_skbuff[i]) {
 526                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 527                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 528                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 529                 }
 530                 priv->rx_skbuff[i] = NULL;
 531         }
 532         return;
 533 }
 534
 535 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 536 {
 537         int i;
 538
 539         for (i = 0; i < priv->dma_tx_size; i++) {
 540                 if (priv->tx_skbuff[i] != NULL) {
 541                         struct dma_desc *p = priv->dma_tx + i;
 542                         if (p->des2)
 543                                 dma_unmap_single(priv->device, p->des2,
 544                                                  priv->hw->desc->get_tx_len(p),
 545                                                  DMA_TO_DEVICE);
 546                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 547                         priv->tx_skbuff[i] = NULL;
 548                 }
 549         }
 550         return;
 551 }
 552
 553 static void free_dma_desc_resources(struct stmmac_priv *priv)
 554 {
 555         /* Release the DMA TX/RX socket buffers */
 556         dma_free_rx_skbufs(priv);
 557         dma_free_tx_skbufs(priv);
 558
 559         /* Free the region of consistent memory previously allocated for
 560          * the DMA */
 561         dma_free_coherent(priv->device,
 562                           priv->dma_tx_size * sizeof(struct dma_desc),
 563                           priv->dma_tx, priv->dma_tx_phy);
 564         dma_free_coherent(priv->device,
 565                           priv->dma_rx_size * sizeof(struct dma_desc),
 566                           priv->dma_rx, priv->dma_rx_phy);
 567         kfree(priv->rx_skbuff_dma);
 568         kfree(priv->rx_skbuff);
 569         kfree(priv->tx_skbuff);
 570
 571         return;
 572 }
 573
 574 /**
 575  * stmmac_dma_start_tx
 576  * @ioaddr: device I/O address
 577  * Description:  this function starts the DMA tx process.
 578  */
 579 static void stmmac_dma_start_tx(unsigned long ioaddr)
 580 {
 581         u32 value = readl(ioaddr + DMA_CONTROL);
 582         value |= DMA_CONTROL_ST;
 583         writel(value, ioaddr + DMA_CONTROL);
 584         return;
 585 }
 586
 587 static void stmmac_dma_stop_tx(unsigned long ioaddr)
 588 {
 589         u32 value = readl(ioaddr + DMA_CONTROL);
 590         value &= ~DMA_CONTROL_ST;
 591         writel(value, ioaddr + DMA_CONTROL);
 592         return;
 593 }
 594
 595 /**
 596  * stmmac_dma_start_rx
 597  * @ioaddr: device I/O address
 598  * Description:  this function starts the DMA rx process.
 599  */
 600 static void stmmac_dma_start_rx(unsigned long ioaddr)
 601 {
 602         u32 value = readl(ioaddr + DMA_CONTROL);
 603         value |= DMA_CONTROL_SR;
 604         writel(value, ioaddr + DMA_CONTROL);
 605
 606         return;
 607 }
 608
 609 static void stmmac_dma_stop_rx(unsigned long ioaddr)
 610 {
 611         u32 value = readl(ioaddr + DMA_CONTROL);
 612         value &= ~DMA_CONTROL_SR;
 613         writel(value, ioaddr + DMA_CONTROL);
 614
 615         return;
 616 }
 617
 618 /**
 619  *  stmmac_dma_operation_mode - HW DMA operation mode
 620  *  @priv : pointer to the private device structure.
 621  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 622  *  or Store-And-Forward capability. It also verifies the COE for the
 623  *  transmission in case of Giga ETH.
 624  */
 625 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 626 {
 627         if (!priv->is_gmac) {
 628                 /* MAC 10/100 */
 629                 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0);
 630                 priv->tx_coe = NO_HW_CSUM;
 631         } else {
 632                 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
 633                         priv->hw->dma->dma_mode(priv->dev->base_addr,
 634                                                 SF_DMA_MODE, SF_DMA_MODE);
 635                         tc = SF_DMA_MODE;
 636                         priv->tx_coe = HW_CSUM;
 637                 } else {
 638                         /* Checksum computation is performed in software. */
 639                         priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
 640                                                 SF_DMA_MODE);
 641                         priv->tx_coe = NO_HW_CSUM;
 642                 }
 643         }
 644         tx_coe = priv->tx_coe;
 645
 646         return;
 647 }
 648
 649 #ifdef STMMAC_DEBUG
 650 /**
 651  * show_tx_process_state
 652  * @status: tx descriptor status field
 653  * Description: it shows the Transmit Process State for CSR5[22:20]
 654  */
 655 static void show_tx_process_state(unsigned int status)
 656 {
 657         unsigned int state;
 658         state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
 659
 660         switch (state) {
 661         case 0:
 662                 pr_info("- TX (Stopped): Reset or Stop command\n");
 663                 break;
 664         case 1:
 665                 pr_info("- TX (Running):Fetching the Tx desc\n");
 666                 break;
 667         case 2:
 668                 pr_info("- TX (Running): Waiting for end of tx\n");
 669                 break;
 670         case 3:
 671                 pr_info("- TX (Running): Reading the data "
 672                        "and queuing the data into the Tx buf\n");
 673                 break;
 674         case 6:
 675                 pr_info("- TX (Suspended): Tx Buff Underflow "
 676                        "or an unavailable Transmit descriptor\n");
 677                 break;
 678         case 7:
 679                 pr_info("- TX (Running): Closing Tx descriptor\n");
 680                 break;
 681         default:
 682                 break;
 683         }
 684         return;
 685 }
 686
 687 /**
 688  * show_rx_process_state
 689  * @status: rx descriptor status field
 690  * Description: it shows the  Receive Process State for CSR5[19:17]
 691  */
 692 static void show_rx_process_state(unsigned int status)
 693 {
 694         unsigned int state;
 695         state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
 696
 697         switch (state) {
 698         case 0:
 699                 pr_info("- RX (Stopped): Reset or Stop command\n");
 700                 break;
 701         case 1:
 702                 pr_info("- RX (Running): Fetching the Rx desc\n");
 703                 break;
 704         case 2:
 705                 pr_info("- RX (Running):Checking for end of pkt\n");
 706                 break;
 707         case 3:
 708                 pr_info("- RX (Running): Waiting for Rx pkt\n");
 709                 break;
 710         case 4:
 711                 pr_info("- RX (Suspended): Unavailable Rx buf\n");
 712                 break;
 713         case 5:
 714                 pr_info("- RX (Running): Closing Rx descriptor\n");
 715                 break;
 716         case 6:
 717                 pr_info("- RX(Running): Flushing the current frame"
 718                        " from the Rx buf\n");
 719                 break;
 720         case 7:
 721                 pr_info("- RX (Running): Queuing the Rx frame"
 722                        " from the Rx buf into memory\n");
 723                 break;
 724         default:
 725                 break;
 726         }
 727         return;
 728 }
 729 #endif
 730
 731 /**
 732  * stmmac_tx:
 733  * @priv: private driver structure
 734  * Description: it reclaims resources after transmission completes.
 735  */
 736 static void stmmac_tx(struct stmmac_priv *priv)
 737 {
 738         unsigned int txsize = priv->dma_tx_size;
 739         unsigned long ioaddr = priv->dev->base_addr;
 740
 741         while (priv->dirty_tx != priv->cur_tx) {
 742                 int last;
 743                 unsigned int entry = priv->dirty_tx % txsize;
 744                 struct sk_buff *skb = priv->tx_skbuff[entry];
 745                 struct dma_desc *p = priv->dma_tx + entry;
 746
 747                 /* Check if the descriptor is owned by the DMA. */
 748                 if (priv->hw->desc->get_tx_owner(p))
 749                         break;
 750
 751                 /* Verify tx error by looking at the last segment */
 752                 last = priv->hw->desc->get_tx_ls(p);
 753                 if (likely(last)) {
 754                         int tx_error =
 755                                 priv->hw->desc->tx_status(&priv->dev->stats,
 756                                                           &priv->xstats, p,
 757                                                           ioaddr);
 758                         if (likely(tx_error == 0)) {
 759                                 priv->dev->stats.tx_packets++;
 760                                 priv->xstats.tx_pkt_n++;
 761                         } else
 762                                 priv->dev->stats.tx_errors++;
 763                 }
 764                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 765                         priv->cur_tx, priv->dirty_tx);
 766
 767                 if (likely(p->des2))
 768                         dma_unmap_single(priv->device, p->des2,
 769                                          priv->hw->desc->get_tx_len(p),
 770                                          DMA_TO_DEVICE);
 771                 if (unlikely(p->des3))
 772                         p->des3 = 0;
 773
 774                 if (likely(skb != NULL)) {
 775                         /*
 776                          * If there's room in the queue (limit it to size)
 777                          * we add this skb back into the pool,
 778                          * if it's the right size.
 779                          */
 780                         if ((skb_queue_len(&priv->rx_recycle) <
 781                                 priv->dma_rx_size) &&
 782                                 skb_recycle_check(skb, priv->dma_buf_sz))
 783                                 __skb_queue_head(&priv->rx_recycle, skb);
 784                         else
 785                                 dev_kfree_skb(skb);
 786
 787                         priv->tx_skbuff[entry] = NULL;
 788                 }
 789
 790                 priv->hw->desc->release_tx_desc(p);
 791
 792                 entry = (++priv->dirty_tx) % txsize;
 793         }
 794         if (unlikely(netif_queue_stopped(priv->dev) &&
 795                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 796                 netif_tx_lock(priv->dev);
 797                 if (netif_queue_stopped(priv->dev) &&
 798                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 799                         TX_DBG("%s: restart transmit\n", __func__);
 800                         netif_wake_queue(priv->dev);
 801                 }
 802                 netif_tx_unlock(priv->dev);
 803         }
 804         return;
 805 }
 806
 807 static inline void stmmac_enable_irq(struct stmmac_priv *priv)
 808 {
 809 #ifdef CONFIG_STMMAC_TIMER
 810         if (likely(priv->tm->enable))
 811                 priv->tm->timer_start(tmrate);
 812         else
 813 #endif
 814         writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA);
 815 }
 816
 817 static inline void stmmac_disable_irq(struct stmmac_priv *priv)
 818 {
 819 #ifdef CONFIG_STMMAC_TIMER
 820         if (likely(priv->tm->enable))
 821                 priv->tm->timer_stop();
 822         else
 823 #endif
 824         writel(0, priv->dev->base_addr + DMA_INTR_ENA);
 825 }
 826
 827 static int stmmac_has_work(struct stmmac_priv *priv)
 828 {
 829         unsigned int has_work = 0;
 830         int rxret, tx_work = 0;
 831
 832         rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
 833                 (priv->cur_rx % priv->dma_rx_size));
 834
 835         if (priv->dirty_tx != priv->cur_tx)
 836                 tx_work = 1;
 837
 838         if (likely(!rxret || tx_work))
 839                 has_work = 1;
 840
 841         return has_work;
 842 }
 843
 844 static inline void _stmmac_schedule(struct stmmac_priv *priv)
 845 {
 846         if (likely(stmmac_has_work(priv))) {
 847                 stmmac_disable_irq(priv);
 848                 napi_schedule(&priv->napi);
 849         }
 850 }
 851
 852 #ifdef CONFIG_STMMAC_TIMER
 853 void stmmac_schedule(struct net_device *dev)
 854 {
 855         struct stmmac_priv *priv = netdev_priv(dev);
 856
 857         priv->xstats.sched_timer_n++;
 858
 859         _stmmac_schedule(priv);
 860
 861         return;
 862 }
 863
 864 static void stmmac_no_timer_started(unsigned int x)
 865 {;
 866 };
 867
 868 static void stmmac_no_timer_stopped(void)
 869 {;
 870 };
 871 #endif
 872
 873 /**
 874  * stmmac_tx_err:
 875  * @priv: pointer to the private device structure
 876  * Description: it cleans the descriptors and restarts the transmission
 877  * in case of errors.
 878  */
 879 static void stmmac_tx_err(struct stmmac_priv *priv)
 880 {
 881         netif_stop_queue(priv->dev);
 882
 883         stmmac_dma_stop_tx(priv->dev->base_addr);
 884         dma_free_tx_skbufs(priv);
 885         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 886         priv->dirty_tx = 0;
 887         priv->cur_tx = 0;
 888         stmmac_dma_start_tx(priv->dev->base_addr);
 889
 890         priv->dev->stats.tx_errors++;
 891         netif_wake_queue(priv->dev);
 892
 893         return;
 894 }
 895
 896 /**
 897  * stmmac_dma_interrupt - Interrupt handler for the driver
 898  * @dev: net device structure
 899  * Description: Interrupt handler for the driver (DMA).
 900  */
 901 static void stmmac_dma_interrupt(struct net_device *dev)
 902 {
 903         unsigned long ioaddr = dev->base_addr;
 904         struct stmmac_priv *priv = netdev_priv(dev);
 905         /* read the status register (CSR5) */
 906         u32 intr_status = readl(ioaddr + DMA_STATUS);
 907
 908         DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
 909
 910 #ifdef STMMAC_DEBUG
 911         /* It displays the DMA transmit process state (CSR5 register) */
 912         if (netif_msg_tx_done(priv))
 913                 show_tx_process_state(intr_status);
 914         if (netif_msg_rx_status(priv))
 915                 show_rx_process_state(intr_status);
 916 #endif
 917         /* ABNORMAL interrupts */
 918         if (unlikely(intr_status & DMA_STATUS_AIS)) {
 919                 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
 920                 if (unlikely(intr_status & DMA_STATUS_UNF)) {
 921                         DBG(intr, INFO, "transmit underflow\n");
 922                         if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 923                                 /* Try to bump up the threshold */
 924                                 tc += 64;
 925                                 priv->hw->dma->dma_mode(ioaddr, tc,
 926                                                         SF_DMA_MODE);
 927                                 priv->xstats.threshold = tc;
 928                         }
 929                         stmmac_tx_err(priv);
 930                         priv->xstats.tx_undeflow_irq++;
 931                 }
 932                 if (unlikely(intr_status & DMA_STATUS_TJT)) {
 933                         DBG(intr, INFO, "transmit jabber\n");
 934                         priv->xstats.tx_jabber_irq++;
 935                 }
 936                 if (unlikely(intr_status & DMA_STATUS_OVF)) {
 937                         DBG(intr, INFO, "recv overflow\n");
 938                         priv->xstats.rx_overflow_irq++;
 939                 }
 940                 if (unlikely(intr_status & DMA_STATUS_RU)) {
 941                         DBG(intr, INFO, "receive buffer unavailable\n");
 942                         priv->xstats.rx_buf_unav_irq++;
 943                 }
 944                 if (unlikely(intr_status & DMA_STATUS_RPS)) {
 945                         DBG(intr, INFO, "receive process stopped\n");
 946                         priv->xstats.rx_process_stopped_irq++;
 947                 }
 948                 if (unlikely(intr_status & DMA_STATUS_RWT)) {
 949                         DBG(intr, INFO, "receive watchdog\n");
 950                         priv->xstats.rx_watchdog_irq++;
 951                 }
 952                 if (unlikely(intr_status & DMA_STATUS_ETI)) {
 953                         DBG(intr, INFO, "transmit early interrupt\n");
 954                         priv->xstats.tx_early_irq++;
 955                 }
 956                 if (unlikely(intr_status & DMA_STATUS_TPS)) {
 957                         DBG(intr, INFO, "transmit process stopped\n");
 958                         priv->xstats.tx_process_stopped_irq++;
 959                         stmmac_tx_err(priv);
 960                 }
 961                 if (unlikely(intr_status & DMA_STATUS_FBI)) {
 962                         DBG(intr, INFO, "fatal bus error\n");
 963                         priv->xstats.fatal_bus_error_irq++;
 964                         stmmac_tx_err(priv);
 965                 }
 966         }
 967
 968         /* TX/RX NORMAL interrupts */
 969         if (intr_status & DMA_STATUS_NIS) {
 970                 priv->xstats.normal_irq_n++;
 971                 if (likely((intr_status & DMA_STATUS_RI) ||
 972                          (intr_status & (DMA_STATUS_TI))))
 973                                 _stmmac_schedule(priv);
 974         }
 975
 976         /* Optional hardware blocks, interrupts should be disabled */
 977         if (unlikely(intr_status &
 978                      (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
 979                 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
 980
 981         /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
 982         writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
 983
 984         DBG(intr, INFO, "\n\n");
 985
 986         return;
 987 }
 988
 989 /**
 990  *  stmmac_open - open entry point of the driver
 991  *  @dev : pointer to the device structure.
 992  *  Description:
 993  *  This function is the open entry point of the driver.
 994  *  Return value:
 995  *  0 on success and an appropriate (-)ve integer as defined in errno.h
 996  *  file on failure.
 997  */
 998 static int stmmac_open(struct net_device *dev)
 999 {
1000         struct stmmac_priv *priv = netdev_priv(dev);
1001         unsigned long ioaddr = dev->base_addr;
1002         int ret;
1003
1004         /* Check that the MAC address is valid.  If its not, refuse
1005          * to bring the device up. The user must specify an
1006          * address using the following linux command:
1007          *      ifconfig eth0 hw ether xx:xx:xx:xx:xx:xx  */
1008         if (!is_valid_ether_addr(dev->dev_addr)) {
1009                 random_ether_addr(dev->dev_addr);
1010                 pr_warning("%s: generated random MAC address %pM\n", dev->name,
1011                         dev->dev_addr);
1012         }
1013
1014         stmmac_verify_args();
1015
1016         ret = stmmac_init_phy(dev);
1017         if (unlikely(ret)) {
1018                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1019                 return ret;
1020         }
1021
1022         /* Request the IRQ lines */
1023         ret = request_irq(dev->irq, stmmac_interrupt,
1024                           IRQF_SHARED, dev->name, dev);
1025         if (unlikely(ret < 0)) {
1026                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1027                        __func__, dev->irq, ret);
1028                 return ret;
1029         }
1030
1031 #ifdef CONFIG_STMMAC_TIMER
1032         priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL);
1033         if (unlikely(priv->tm == NULL)) {
1034                 pr_err("%s: ERROR: timer memory alloc failed \n", __func__);
1035                 return -ENOMEM;
1036         }
1037         priv->tm->freq = tmrate;
1038
1039         /* Test if the external timer can be actually used.
1040          * In case of failure continue without timer. */
1041         if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) {
1042                 pr_warning("stmmaceth: cannot attach the external timer.\n");
1043                 tmrate = 0;
1044                 priv->tm->freq = 0;
1045                 priv->tm->timer_start = stmmac_no_timer_started;
1046                 priv->tm->timer_stop = stmmac_no_timer_stopped;
1047         } else
1048                 priv->tm->enable = 1;
1049 #endif
1050
1051         /* Create and initialize the TX/RX descriptors chains. */
1052         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1053         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1054         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1055         init_dma_desc_rings(dev);
1056
1057         /* DMA initialization and SW reset */
1058         if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy,
1059                                          priv->dma_rx_phy) < 0)) {
1060
1061                 pr_err("%s: DMA initialization failed\n", __func__);
1062                 return -1;
1063         }
1064
1065         /* Copy the MAC addr into the HW  */
1066         priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0);
1067         /* If required, perform hw setup of the bus. */
1068         if (priv->bus_setup)
1069                 priv->bus_setup(ioaddr);
1070         /* Initialize the MAC Core */
1071         priv->hw->mac->core_init(ioaddr);
1072
1073         priv->shutdown = 0;
1074
1075         /* Initialise the MMC (if present) to disable all interrupts. */
1076         writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK);
1077         writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK);
1078
1079         /* Enable the MAC Rx/Tx */
1080         stmmac_mac_enable_rx(ioaddr);
1081         stmmac_mac_enable_tx(ioaddr);
1082
1083         /* Set the HW DMA mode and the COE */
1084         stmmac_dma_operation_mode(priv);
1085
1086         /* Extra statistics */
1087         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1088         priv->xstats.threshold = tc;
1089
1090         /* Start the ball rolling... */
1091         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1092         stmmac_dma_start_tx(ioaddr);
1093         stmmac_dma_start_rx(ioaddr);
1094
1095 #ifdef CONFIG_STMMAC_TIMER
1096         priv->tm->timer_start(tmrate);
1097 #endif
1098         /* Dump DMA/MAC registers */
1099         if (netif_msg_hw(priv)) {
1100                 priv->hw->mac->dump_regs(ioaddr);
1101                 priv->hw->dma->dump_regs(ioaddr);
1102         }
1103
1104         if (priv->phydev)
1105                 phy_start(priv->phydev);
1106
1107         napi_enable(&priv->napi);
1108         skb_queue_head_init(&priv->rx_recycle);
1109         netif_start_queue(dev);
1110         return 0;
1111 }
1112
1113 /**
1114  *  stmmac_release - close entry point of the driver
1115  *  @dev : device pointer.
1116  *  Description:
1117  *  This is the stop entry point of the driver.
1118  */
1119 static int stmmac_release(struct net_device *dev)
1120 {
1121         struct stmmac_priv *priv = netdev_priv(dev);
1122
1123         /* Stop and disconnect the PHY */
1124         if (priv->phydev) {
1125                 phy_stop(priv->phydev);
1126                 phy_disconnect(priv->phydev);
1127                 priv->phydev = NULL;
1128         }
1129
1130         netif_stop_queue(dev);
1131
1132 #ifdef CONFIG_STMMAC_TIMER
1133         /* Stop and release the timer */
1134         stmmac_close_ext_timer();
1135         if (priv->tm != NULL)
1136                 kfree(priv->tm);
1137 #endif
1138         napi_disable(&priv->napi);
1139         skb_queue_purge(&priv->rx_recycle);
1140
1141         /* Free the IRQ lines */
1142         free_irq(dev->irq, dev);
1143
1144         /* Stop TX/RX DMA and clear the descriptors */
1145         stmmac_dma_stop_tx(dev->base_addr);
1146         stmmac_dma_stop_rx(dev->base_addr);
1147
1148         /* Release and free the Rx/Tx resources */
1149         free_dma_desc_resources(priv);
1150
1151         /* Disable the MAC core */
1152         stmmac_mac_disable_tx(dev->base_addr);
1153         stmmac_mac_disable_rx(dev->base_addr);
1154
1155         netif_carrier_off(dev);
1156
1157         return 0;
1158 }
1159
1160 /*
1161  * To perform emulated hardware segmentation on skb.
1162  */
1163 static int stmmac_sw_tso(struct stmmac_priv *priv, struct sk_buff *skb)
1164 {
1165         struct sk_buff *segs, *curr_skb;
1166         int gso_segs = skb_shinfo(skb)->gso_segs;
1167
1168         /* Estimate the number of fragments in the worst case */
1169         if (unlikely(stmmac_tx_avail(priv) < gso_segs)) {
1170                 netif_stop_queue(priv->dev);
1171                 TX_DBG(KERN_ERR "%s: TSO BUG! Tx Ring full when queue awake\n",
1172                        __func__);
1173                 if (stmmac_tx_avail(priv) < gso_segs)
1174                         return NETDEV_TX_BUSY;
1175
1176                 netif_wake_queue(priv->dev);
1177         }
1178         TX_DBG("\tstmmac_sw_tso: segmenting: skb %p (len %d)\n",
1179                skb, skb->len);
1180
1181         segs = skb_gso_segment(skb, priv->dev->features & ~NETIF_F_TSO);
1182         if (unlikely(IS_ERR(segs)))
1183                 goto sw_tso_end;
1184
1185         do {
1186                 curr_skb = segs;
1187                 segs = segs->next;
1188                 TX_DBG("\t\tcurrent skb->len: %d, *curr %p,"
1189                        "*next %p\n", curr_skb->len, curr_skb, segs);
1190                 curr_skb->next = NULL;
1191                 stmmac_xmit(curr_skb, priv->dev);
1192         } while (segs);
1193
1194 sw_tso_end:
1195         dev_kfree_skb(skb);
1196
1197         return NETDEV_TX_OK;
1198 }
1199
1200 static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1201                                                struct net_device *dev,
1202                                                int csum_insertion)
1203 {
1204         struct stmmac_priv *priv = netdev_priv(dev);
1205         unsigned int nopaged_len = skb_headlen(skb);
1206         unsigned int txsize = priv->dma_tx_size;
1207         unsigned int entry = priv->cur_tx % txsize;
1208         struct dma_desc *desc = priv->dma_tx + entry;
1209
1210         if (nopaged_len > BUF_SIZE_8KiB) {
1211
1212                 int buf2_size = nopaged_len - BUF_SIZE_8KiB;
1213
1214                 desc->des2 = dma_map_single(priv->device, skb->data,
1215                                             BUF_SIZE_8KiB, DMA_TO_DEVICE);
1216                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1217                 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1218                                                 csum_insertion);
1219
1220                 entry = (++priv->cur_tx) % txsize;
1221                 desc = priv->dma_tx + entry;
1222
1223                 desc->des2 = dma_map_single(priv->device,
1224                                         skb->data + BUF_SIZE_8KiB,
1225                                         buf2_size, DMA_TO_DEVICE);
1226                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1227                 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1228                                                 csum_insertion);
1229                 priv->hw->desc->set_tx_owner(desc);
1230
1231                 priv->tx_skbuff[entry] = NULL;
1232         } else {
1233                 desc->des2 = dma_map_single(priv->device, skb->data,
1234                                         nopaged_len, DMA_TO_DEVICE);
1235                 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1236                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1237                                                 csum_insertion);
1238         }
1239         return entry;
1240 }
1241
1242 /**
1243  *  stmmac_xmit:
1244  *  @skb : the socket buffer
1245  *  @dev : device pointer
1246  *  Description : Tx entry point of the driver.
1247  */
1248 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1249 {
1250         struct stmmac_priv *priv = netdev_priv(dev);
1251         unsigned int txsize = priv->dma_tx_size;
1252         unsigned int entry;
1253         int i, csum_insertion = 0;
1254         int nfrags = skb_shinfo(skb)->nr_frags;
1255         struct dma_desc *desc, *first;
1256
1257         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1258                 if (!netif_queue_stopped(dev)) {
1259                         netif_stop_queue(dev);
1260                         /* This is a hard error, log it. */
1261                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1262                                 __func__);
1263                 }
1264                 return NETDEV_TX_BUSY;
1265         }
1266
1267         entry = priv->cur_tx % txsize;
1268
1269 #ifdef STMMAC_XMIT_DEBUG
1270         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1271                 pr_info("stmmac xmit:\n"
1272                        "\tskb addr %p - len: %d - nopaged_len: %d\n"
1273                        "\tn_frags: %d - ip_summed: %d - %s gso\n",
1274                        skb, skb->len, skb_headlen(skb), nfrags, skb->ip_summed,
1275                        !skb_is_gso(skb) ? "isn't" : "is");
1276 #endif
1277
1278         if (unlikely(skb_is_gso(skb)))
1279                 return stmmac_sw_tso(priv, skb);
1280
1281         if (likely((skb->ip_summed == CHECKSUM_PARTIAL))) {
1282                 if (likely(priv->tx_coe == NO_HW_CSUM))
1283                         skb_checksum_help(skb);
1284                 else
1285                         csum_insertion = 1;
1286         }
1287
1288         desc = priv->dma_tx + entry;
1289         first = desc;
1290
1291 #ifdef STMMAC_XMIT_DEBUG
1292         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1293                 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n"
1294                        "\t\tn_frags: %d, ip_summed: %d\n",
1295                        skb->len, skb_headlen(skb), nfrags, skb->ip_summed);
1296 #endif
1297         priv->tx_skbuff[entry] = skb;
1298         if (unlikely(skb->len >= BUF_SIZE_4KiB)) {
1299                 entry = stmmac_handle_jumbo_frames(skb, dev, csum_insertion);
1300                 desc = priv->dma_tx + entry;
1301         } else {
1302                 unsigned int nopaged_len = skb_headlen(skb);
1303                 desc->des2 = dma_map_single(priv->device, skb->data,
1304                                         nopaged_len, DMA_TO_DEVICE);
1305                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1306                                                 csum_insertion);
1307         }
1308
1309         for (i = 0; i < nfrags; i++) {
1310                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1311                 int len = frag->size;
1312
1313                 entry = (++priv->cur_tx) % txsize;
1314                 desc = priv->dma_tx + entry;
1315
1316                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1317                 desc->des2 = dma_map_page(priv->device, frag->page,
1318                                           frag->page_offset,
1319                                           len, DMA_TO_DEVICE);
1320                 priv->tx_skbuff[entry] = NULL;
1321                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1322                 priv->hw->desc->set_tx_owner(desc);
1323         }
1324
1325         /* Interrupt on completition only for the latest segment */
1326         priv->hw->desc->close_tx_desc(desc);
1327
1328 #ifdef CONFIG_STMMAC_TIMER
1329         /* Clean IC while using timer */
1330         if (likely(priv->tm->enable))
1331                 priv->hw->desc->clear_tx_ic(desc);
1332 #endif
1333         /* To avoid raise condition */
1334         priv->hw->desc->set_tx_owner(first);
1335
1336         priv->cur_tx++;
1337
1338 #ifdef STMMAC_XMIT_DEBUG
1339         if (netif_msg_pktdata(priv)) {
1340                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1341                        "first=%p, nfrags=%d\n",
1342                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1343                        entry, first, nfrags);
1344                 display_ring(priv->dma_tx, txsize);
1345                 pr_info(">>> frame to be transmitted: ");
1346                 print_pkt(skb->data, skb->len);
1347         }
1348 #endif
1349         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1350                 TX_DBG("%s: stop transmitted packets\n", __func__);
1351                 netif_stop_queue(dev);
1352         }
1353
1354         dev->stats.tx_bytes += skb->len;
1355
1356         /* CSR1 enables the transmit DMA to check for new descriptor */
1357         writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1358
1359         return NETDEV_TX_OK;
1360 }
1361
1362 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1363 {
1364         unsigned int rxsize = priv->dma_rx_size;
1365         int bfsize = priv->dma_buf_sz;
1366         struct dma_desc *p = priv->dma_rx;
1367
1368         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1369                 unsigned int entry = priv->dirty_rx % rxsize;
1370                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1371                         struct sk_buff *skb;
1372
1373                         skb = __skb_dequeue(&priv->rx_recycle);
1374                         if (skb == NULL)
1375                                 skb = netdev_alloc_skb_ip_align(priv->dev,
1376                                                                 bfsize);
1377
1378                         if (unlikely(skb == NULL))
1379                                 break;
1380
1381                         priv->rx_skbuff[entry] = skb;
1382                         priv->rx_skbuff_dma[entry] =
1383                             dma_map_single(priv->device, skb->data, bfsize,
1384                                            DMA_FROM_DEVICE);
1385
1386                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1387                         if (unlikely(priv->is_gmac)) {
1388                                 if (bfsize >= BUF_SIZE_8KiB)
1389                                         (p + entry)->des3 =
1390                                             (p + entry)->des2 + BUF_SIZE_8KiB;
1391                         }
1392                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1393                 }
1394                 priv->hw->desc->set_rx_owner(p + entry);
1395         }
1396         return;
1397 }
1398
1399 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1400 {
1401         unsigned int rxsize = priv->dma_rx_size;
1402         unsigned int entry = priv->cur_rx % rxsize;
1403         unsigned int next_entry;
1404         unsigned int count = 0;
1405         struct dma_desc *p = priv->dma_rx + entry;
1406         struct dma_desc *p_next;
1407
1408 #ifdef STMMAC_RX_DEBUG
1409         if (netif_msg_hw(priv)) {
1410                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1411                 display_ring(priv->dma_rx, rxsize);
1412         }
1413 #endif
1414         count = 0;
1415         while (!priv->hw->desc->get_rx_owner(p)) {
1416                 int status;
1417
1418                 if (count >= limit)
1419                         break;
1420
1421                 count++;
1422
1423                 next_entry = (++priv->cur_rx) % rxsize;
1424                 p_next = priv->dma_rx + next_entry;
1425                 prefetch(p_next);
1426
1427                 /* read the status of the incoming frame */
1428                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1429                                                     &priv->xstats, p));
1430                 if (unlikely(status == discard_frame))
1431                         priv->dev->stats.rx_errors++;
1432                 else {
1433                         struct sk_buff *skb;
1434                         /* Length should omit the CRC */
1435                         int frame_len = priv->hw->desc->get_rx_frame_len(p) - 4;
1436
1437 #ifdef STMMAC_RX_DEBUG
1438                         if (frame_len > ETH_FRAME_LEN)
1439                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1440                                         frame_len, status);
1441
1442                         if (netif_msg_hw(priv))
1443                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1444                                         p, entry, p->des2);
1445 #endif
1446                         skb = priv->rx_skbuff[entry];
1447                         if (unlikely(!skb)) {
1448                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1449                                         priv->dev->name);
1450                                 priv->dev->stats.rx_dropped++;
1451                                 break;
1452                         }
1453                         prefetch(skb->data - NET_IP_ALIGN);
1454                         priv->rx_skbuff[entry] = NULL;
1455
1456                         skb_put(skb, frame_len);
1457                         dma_unmap_single(priv->device,
1458                                          priv->rx_skbuff_dma[entry],
1459                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1460 #ifdef STMMAC_RX_DEBUG
1461                         if (netif_msg_pktdata(priv)) {
1462                                 pr_info(" frame received (%dbytes)", frame_len);
1463                                 print_pkt(skb->data, frame_len);
1464                         }
1465 #endif
1466                         skb->protocol = eth_type_trans(skb, priv->dev);
1467
1468                         if (unlikely(status == csum_none)) {
1469                                 /* always for the old mac 10/100 */
1470                                 skb->ip_summed = CHECKSUM_NONE;
1471                                 netif_receive_skb(skb);
1472                         } else {
1473                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1474                                 napi_gro_receive(&priv->napi, skb);
1475                         }
1476
1477                         priv->dev->stats.rx_packets++;
1478                         priv->dev->stats.rx_bytes += frame_len;
1479                         priv->dev->last_rx = jiffies;
1480                 }
1481                 entry = next_entry;
1482                 p = p_next;     /* use prefetched values */
1483         }
1484
1485         stmmac_rx_refill(priv);
1486
1487         priv->xstats.rx_pkt_n += count;
1488
1489         return count;
1490 }
1491
1492 /**
1493  *  stmmac_poll - stmmac poll method (NAPI)
1494  *  @napi : pointer to the napi structure.
1495  *  @budget : maximum number of packets that the current CPU can receive from
1496  *            all interfaces.
1497  *  Description :
1498  *   This function implements the the reception process.
1499  *   Also it runs the TX completion thread
1500  */
1501 static int stmmac_poll(struct napi_struct *napi, int budget)
1502 {
1503         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1504         int work_done = 0;
1505
1506         priv->xstats.poll_n++;
1507         stmmac_tx(priv);
1508         work_done = stmmac_rx(priv, budget);
1509
1510         if (work_done < budget) {
1511                 napi_complete(napi);
1512                 stmmac_enable_irq(priv);
1513         }
1514         return work_done;
1515 }
1516
1517 /**
1518  *  stmmac_tx_timeout
1519  *  @dev : Pointer to net device structure
1520  *  Description: this function is called when a packet transmission fails to
1521  *   complete within a reasonable tmrate. The driver will mark the error in the
1522  *   netdev structure and arrange for the device to be reset to a sane state
1523  *   in order to transmit a new packet.
1524  */
1525 static void stmmac_tx_timeout(struct net_device *dev)
1526 {
1527         struct stmmac_priv *priv = netdev_priv(dev);
1528
1529         /* Clear Tx resources and restart transmitting again */
1530         stmmac_tx_err(priv);
1531         return;
1532 }
1533
1534 /* Configuration changes (passed on by ifconfig) */
1535 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1536 {
1537         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1538                 return -EBUSY;
1539
1540         /* Don't allow changing the I/O address */
1541         if (map->base_addr != dev->base_addr) {
1542                 pr_warning("%s: can't change I/O address\n", dev->name);
1543                 return -EOPNOTSUPP;
1544         }
1545
1546         /* Don't allow changing the IRQ */
1547         if (map->irq != dev->irq) {
1548                 pr_warning("%s: can't change IRQ number %d\n",
1549                        dev->name, dev->irq);
1550                 return -EOPNOTSUPP;
1551         }
1552
1553         /* ignore other fields */
1554         return 0;
1555 }
1556
1557 /**
1558  *  stmmac_multicast_list - entry point for multicast addressing
1559  *  @dev : pointer to the device structure
1560  *  Description:
1561  *  This function is a driver entry point which gets called by the kernel
1562  *  whenever multicast addresses must be enabled/disabled.
1563  *  Return value:
1564  *  void.
1565  */
1566 static void stmmac_multicast_list(struct net_device *dev)
1567 {
1568         struct stmmac_priv *priv = netdev_priv(dev);
1569
1570         spin_lock(&priv->lock);
1571         priv->hw->mac->set_filter(dev);
1572         spin_unlock(&priv->lock);
1573         return;
1574 }
1575
1576 /**
1577  *  stmmac_change_mtu - entry point to change MTU size for the device.
1578  *  @dev : device pointer.
1579  *  @new_mtu : the new MTU size for the device.
1580  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1581  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1582  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1583  *  Return value:
1584  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1585  *  file on failure.
1586  */
1587 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1588 {
1589         struct stmmac_priv *priv = netdev_priv(dev);
1590         int max_mtu;
1591
1592         if (netif_running(dev)) {
1593                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1594                 return -EBUSY;
1595         }
1596
1597         if (priv->is_gmac)
1598                 max_mtu = JUMBO_LEN;
1599         else
1600                 max_mtu = ETH_DATA_LEN;
1601
1602         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1603                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1604                 return -EINVAL;
1605         }
1606
1607         dev->mtu = new_mtu;
1608
1609         return 0;
1610 }
1611
1612 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1613 {
1614         struct net_device *dev = (struct net_device *)dev_id;
1615         struct stmmac_priv *priv = netdev_priv(dev);
1616
1617         if (unlikely(!dev)) {
1618                 pr_err("%s: invalid dev pointer\n", __func__);
1619                 return IRQ_NONE;
1620         }
1621
1622         if (priv->is_gmac) {
1623                 unsigned long ioaddr = dev->base_addr;
1624                 /* To handle GMAC own interrupts */
1625                 priv->hw->mac->host_irq_status(ioaddr);
1626         }
1627         stmmac_dma_interrupt(dev);
1628
1629         return IRQ_HANDLED;
1630 }
1631
1632 #ifdef CONFIG_NET_POLL_CONTROLLER
1633 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1634  * to allow network I/O with interrupts disabled. */
1635 static void stmmac_poll_controller(struct net_device *dev)
1636 {
1637         disable_irq(dev->irq);
1638         stmmac_interrupt(dev->irq, dev);
1639         enable_irq(dev->irq);
1640 }
1641 #endif
1642
1643 /**
1644  *  stmmac_ioctl - Entry point for the Ioctl
1645  *  @dev: Device pointer.
1646  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1647  *  a proprietary structure used to pass information to the driver.
1648  *  @cmd: IOCTL command
1649  *  Description:
1650  *  Currently there are no special functionality supported in IOCTL, just the
1651  *  phy_mii_ioctl(...) can be invoked.
1652  */
1653 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1654 {
1655         struct stmmac_priv *priv = netdev_priv(dev);
1656         int ret = -EOPNOTSUPP;
1657
1658         if (!netif_running(dev))
1659                 return -EINVAL;
1660
1661         switch (cmd) {
1662         case SIOCGMIIPHY:
1663         case SIOCGMIIREG:
1664         case SIOCSMIIREG:
1665                 if (!priv->phydev)
1666                         return -EINVAL;
1667
1668                 spin_lock(&priv->lock);
1669                 ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
1670                 spin_unlock(&priv->lock);
1671         default:
1672                 break;
1673         }
1674         return ret;
1675 }
1676
1677 #ifdef STMMAC_VLAN_TAG_USED
1678 static void stmmac_vlan_rx_register(struct net_device *dev,
1679                                     struct vlan_group *grp)
1680 {
1681         struct stmmac_priv *priv = netdev_priv(dev);
1682
1683         DBG(probe, INFO, "%s: Setting vlgrp to %p\n", dev->name, grp);
1684
1685         spin_lock(&priv->lock);
1686         priv->vlgrp = grp;
1687         spin_unlock(&priv->lock);
1688
1689         return;
1690 }
1691 #endif
1692
1693 static const struct net_device_ops stmmac_netdev_ops = {
1694         .ndo_open = stmmac_open,
1695         .ndo_start_xmit = stmmac_xmit,
1696         .ndo_stop = stmmac_release,
1697         .ndo_change_mtu = stmmac_change_mtu,
1698         .ndo_set_multicast_list = stmmac_multicast_list,
1699         .ndo_tx_timeout = stmmac_tx_timeout,
1700         .ndo_do_ioctl = stmmac_ioctl,
1701         .ndo_set_config = stmmac_config,
1702 #ifdef STMMAC_VLAN_TAG_USED
1703         .ndo_vlan_rx_register = stmmac_vlan_rx_register,
1704 #endif
1705 #ifdef CONFIG_NET_POLL_CONTROLLER
1706         .ndo_poll_controller = stmmac_poll_controller,
1707 #endif
1708         .ndo_set_mac_address = eth_mac_addr,
1709 };
1710
1711 /**
1712  * stmmac_probe - Initialization of the adapter .
1713  * @dev : device pointer
1714  * Description: The function initializes the network device structure for
1715  * the STMMAC driver. It also calls the low level routines
1716  * in order to init the HW (i.e. the DMA engine)
1717  */
1718 static int stmmac_probe(struct net_device *dev)
1719 {
1720         int ret = 0;
1721         struct stmmac_priv *priv = netdev_priv(dev);
1722
1723         ether_setup(dev);
1724
1725         dev->netdev_ops = &stmmac_netdev_ops;
1726         stmmac_set_ethtool_ops(dev);
1727
1728         dev->features |= (NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA);
1729         dev->watchdog_timeo = msecs_to_jiffies(watchdog);
1730 #ifdef STMMAC_VLAN_TAG_USED
1731         /* Both mac100 and gmac support receive VLAN tag detection */
1732         dev->features |= NETIF_F_HW_VLAN_RX;
1733 #endif
1734         priv->msg_enable = netif_msg_init(debug, default_msg_level);
1735
1736         if (priv->is_gmac)
1737                 priv->rx_csum = 1;
1738
1739         if (flow_ctrl)
1740                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
1741
1742         priv->pause = pause;
1743         netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1744
1745         /* Get the MAC address */
1746         priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
1747
1748         if (!is_valid_ether_addr(dev->dev_addr))
1749                 pr_warning("\tno valid MAC address;"
1750                         "please, use ifconfig or nwhwconfig!\n");
1751
1752         ret = register_netdev(dev);
1753         if (ret) {
1754                 pr_err("%s: ERROR %i registering the device\n",
1755                        __func__, ret);
1756                 return -ENODEV;
1757         }
1758
1759         DBG(probe, DEBUG, "%s: Scatter/Gather: %s - HW checksums: %s\n",
1760             dev->name, (dev->features & NETIF_F_SG) ? "on" : "off",
1761             (dev->features & NETIF_F_HW_CSUM) ? "on" : "off");
1762
1763         spin_lock_init(&priv->lock);
1764
1765         return ret;
1766 }
1767
1768 /**
1769  * stmmac_mac_device_setup
1770  * @dev : device pointer
1771  * Description: select and initialise the mac device (mac100 or Gmac).
1772  */
1773 static int stmmac_mac_device_setup(struct net_device *dev)
1774 {
1775         struct stmmac_priv *priv = netdev_priv(dev);
1776         unsigned long ioaddr = dev->base_addr;
1777
1778         struct mac_device_info *device;
1779
1780         if (priv->is_gmac)
1781                 device = gmac_setup(ioaddr);
1782         else
1783                 device = mac100_setup(ioaddr);
1784
1785         if (!device)
1786                 return -ENOMEM;
1787
1788         priv->hw = device;
1789
1790         priv->wolenabled = priv->hw->pmt;       /* PMT supported */
1791         if (priv->wolenabled == PMT_SUPPORTED)
1792                 priv->wolopts = WAKE_MAGIC;             /* Magic Frame */
1793
1794         return 0;
1795 }
1796
1797 static int stmmacphy_dvr_probe(struct platform_device *pdev)
1798 {
1799         struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
1800
1801         pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1802                plat_dat->bus_id);
1803
1804         return 0;
1805 }
1806
1807 static int stmmacphy_dvr_remove(struct platform_device *pdev)
1808 {
1809         return 0;
1810 }
1811
1812 static struct platform_driver stmmacphy_driver = {
1813         .driver = {
1814                    .name = PHY_RESOURCE_NAME,
1815                    },
1816         .probe = stmmacphy_dvr_probe,
1817         .remove = stmmacphy_dvr_remove,
1818 };
1819
1820 /**
1821  * stmmac_associate_phy
1822  * @dev: pointer to device structure
1823  * @data: points to the private structure.
1824  * Description: Scans through all the PHYs we have registered and checks if
1825  * any are associated with our MAC.  If so, then just fill in
1826  * the blanks in our local context structure
1827  */
1828 static int stmmac_associate_phy(struct device *dev, void *data)
1829 {
1830         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1831         struct plat_stmmacphy_data *plat_dat = dev->platform_data;
1832
1833         DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1834                 plat_dat->bus_id);
1835
1836         /* Check that this phy is for the MAC being initialised */
1837         if (priv->bus_id != plat_dat->bus_id)
1838                 return 0;
1839
1840         /* OK, this PHY is connected to the MAC.
1841            Go ahead and get the parameters */
1842         DBG(probe, DEBUG, "%s: OK. Found PHY config\n", __func__);
1843         priv->phy_irq =
1844             platform_get_irq_byname(to_platform_device(dev), "phyirq");
1845         DBG(probe, DEBUG, "%s: PHY irq on bus %d is %d\n", __func__,
1846             plat_dat->bus_id, priv->phy_irq);
1847
1848         /* Override with kernel parameters if supplied XXX CRS XXX
1849          * this needs to have multiple instances */
1850         if ((phyaddr >= 0) && (phyaddr <= 31))
1851                 plat_dat->phy_addr = phyaddr;
1852
1853         priv->phy_addr = plat_dat->phy_addr;
1854         priv->phy_mask = plat_dat->phy_mask;
1855         priv->phy_interface = plat_dat->interface;
1856         priv->phy_reset = plat_dat->phy_reset;
1857
1858         DBG(probe, DEBUG, "%s: exiting\n", __func__);
1859         return 1;       /* forces exit of driver_for_each_device() */
1860 }
1861
1862 /**
1863  * stmmac_dvr_probe
1864  * @pdev: platform device pointer
1865  * Description: the driver is initialized through platform_device.
1866  */
1867 static int stmmac_dvr_probe(struct platform_device *pdev)
1868 {
1869         int ret = 0;
1870         struct resource *res;
1871         unsigned int *addr = NULL;
1872         struct net_device *ndev = NULL;
1873         struct stmmac_priv *priv;
1874         struct plat_stmmacenet_data *plat_dat;
1875
1876         pr_info("STMMAC driver:\n\tplatform registration... ");
1877         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1878         if (!res) {
1879                 ret = -ENODEV;
1880                 goto out;
1881         }
1882         pr_info("done!\n");
1883
1884         if (!request_mem_region(res->start, (res->end - res->start),
1885                                 pdev->name)) {
1886                 pr_err("%s: ERROR: memory allocation failed"
1887                        "cannot get the I/O addr 0x%x\n",
1888                        __func__, (unsigned int)res->start);
1889                 ret = -EBUSY;
1890                 goto out;
1891         }
1892
1893         addr = ioremap(res->start, (res->end - res->start));
1894         if (!addr) {
1895                 pr_err("%s: ERROR: memory mapping failed \n", __func__);
1896                 ret = -ENOMEM;
1897                 goto out;
1898         }
1899
1900         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1901         if (!ndev) {
1902                 pr_err("%s: ERROR: allocating the device\n", __func__);
1903                 ret = -ENOMEM;
1904                 goto out;
1905         }
1906
1907         SET_NETDEV_DEV(ndev, &pdev->dev);
1908
1909         /* Get the MAC information */
1910         ndev->irq = platform_get_irq_byname(pdev, "macirq");
1911         if (ndev->irq == -ENXIO) {
1912                 pr_err("%s: ERROR: MAC IRQ configuration "
1913                        "information not found\n", __func__);
1914                 ret = -ENODEV;
1915                 goto out;
1916         }
1917
1918         priv = netdev_priv(ndev);
1919         priv->device = &(pdev->dev);
1920         priv->dev = ndev;
1921         plat_dat = pdev->dev.platform_data;
1922         priv->bus_id = plat_dat->bus_id;
1923         priv->pbl = plat_dat->pbl;      /* TLI */
1924         priv->is_gmac = plat_dat->has_gmac;     /* GMAC is on board */
1925
1926         platform_set_drvdata(pdev, ndev);
1927
1928         /* Set the I/O base addr */
1929         ndev->base_addr = (unsigned long)addr;
1930
1931         /* Verify embedded resource for the platform */
1932         ret = stmmac_claim_resource(pdev);
1933         if (ret < 0)
1934                 goto out;
1935
1936         /* MAC HW revice detection */
1937         ret = stmmac_mac_device_setup(ndev);
1938         if (ret < 0)
1939                 goto out;
1940
1941         /* Network Device Registration */
1942         ret = stmmac_probe(ndev);
1943         if (ret < 0)
1944                 goto out;
1945
1946         /* associate a PHY - it is provided by another platform bus */
1947         if (!driver_for_each_device
1948             (&(stmmacphy_driver.driver), NULL, (void *)priv,
1949              stmmac_associate_phy)) {
1950                 pr_err("No PHY device is associated with this MAC!\n");
1951                 ret = -ENODEV;
1952                 goto out;
1953         }
1954
1955         priv->fix_mac_speed = plat_dat->fix_mac_speed;
1956         priv->bus_setup = plat_dat->bus_setup;
1957         priv->bsp_priv = plat_dat->bsp_priv;
1958
1959         pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
1960                "\tIO base addr: 0x%08x)\n", ndev->name, pdev->name,
1961                pdev->id, ndev->irq, (unsigned int)addr);
1962
1963         /* MDIO bus Registration */
1964         pr_debug("\tMDIO bus (id: %d)...", priv->bus_id);
1965         ret = stmmac_mdio_register(ndev);
1966         if (ret < 0)
1967                 goto out;
1968         pr_debug("registered!\n");
1969
1970 out:
1971         if (ret < 0) {
1972                 platform_set_drvdata(pdev, NULL);
1973                 release_mem_region(res->start, (res->end - res->start));
1974                 if (addr != NULL)
1975                         iounmap(addr);
1976         }
1977
1978         return ret;
1979 }
1980
1981 /**
1982  * stmmac_dvr_remove
1983  * @pdev: platform device pointer
1984  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
1985  * changes the link status, releases the DMA descriptor rings,
1986  * unregisters the MDIO bus and unmaps the allocated memory.
1987  */
1988 static int stmmac_dvr_remove(struct platform_device *pdev)
1989 {
1990         struct net_device *ndev = platform_get_drvdata(pdev);
1991         struct resource *res;
1992
1993         pr_info("%s:\n\tremoving driver", __func__);
1994
1995         stmmac_dma_stop_rx(ndev->base_addr);
1996         stmmac_dma_stop_tx(ndev->base_addr);
1997
1998         stmmac_mac_disable_rx(ndev->base_addr);
1999         stmmac_mac_disable_tx(ndev->base_addr);
2000
2001         netif_carrier_off(ndev);
2002
2003         stmmac_mdio_unregister(ndev);
2004
2005         platform_set_drvdata(pdev, NULL);
2006         unregister_netdev(ndev);
2007
2008         iounmap((void *)ndev->base_addr);
2009         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2010         release_mem_region(res->start, (res->end - res->start));
2011
2012         free_netdev(ndev);
2013
2014         return 0;
2015 }
2016
2017 #ifdef CONFIG_PM
2018 static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2019 {
2020         struct net_device *dev = platform_get_drvdata(pdev);
2021         struct stmmac_priv *priv = netdev_priv(dev);
2022         int dis_ic = 0;
2023
2024         if (!dev || !netif_running(dev))
2025                 return 0;
2026
2027         spin_lock(&priv->lock);
2028
2029         if (state.event == PM_EVENT_SUSPEND) {
2030                 netif_device_detach(dev);
2031                 netif_stop_queue(dev);
2032                 if (priv->phydev)
2033                         phy_stop(priv->phydev);
2034
2035 #ifdef CONFIG_STMMAC_TIMER
2036                 priv->tm->timer_stop();
2037                 if (likely(priv->tm->enable))
2038                         dis_ic = 1;
2039 #endif
2040                 napi_disable(&priv->napi);
2041
2042                 /* Stop TX/RX DMA */
2043                 stmmac_dma_stop_tx(dev->base_addr);
2044                 stmmac_dma_stop_rx(dev->base_addr);
2045                 /* Clear the Rx/Tx descriptors */
2046                 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2047                                              dis_ic);
2048                 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2049
2050                 stmmac_mac_disable_tx(dev->base_addr);
2051
2052                 if (device_may_wakeup(&(pdev->dev))) {
2053                         /* Enable Power down mode by programming the PMT regs */
2054                         if (priv->wolenabled == PMT_SUPPORTED)
2055                                 priv->hw->mac->pmt(dev->base_addr,
2056                                                    priv->wolopts);
2057                 } else {
2058                         stmmac_mac_disable_rx(dev->base_addr);
2059                 }
2060         } else {
2061                 priv->shutdown = 1;
2062                 /* Although this can appear slightly redundant it actually
2063                  * makes fast the standby operation and guarantees the driver
2064                  * working if hibernation is on media. */
2065                 stmmac_release(dev);
2066         }
2067
2068         spin_unlock(&priv->lock);
2069         return 0;
2070 }
2071
2072 static int stmmac_resume(struct platform_device *pdev)
2073 {
2074         struct net_device *dev = platform_get_drvdata(pdev);
2075         struct stmmac_priv *priv = netdev_priv(dev);
2076         unsigned long ioaddr = dev->base_addr;
2077
2078         if (!netif_running(dev))
2079                 return 0;
2080
2081         spin_lock(&priv->lock);
2082
2083         if (priv->shutdown) {
2084                 /* Re-open the interface and re-init the MAC/DMA
2085                    and the rings. */
2086                 stmmac_open(dev);
2087                 goto out_resume;
2088         }
2089
2090         /* Power Down bit, into the PM register, is cleared
2091          * automatically as soon as a magic packet or a Wake-up frame
2092          * is received. Anyway, it's better to manually clear
2093          * this bit because it can generate problems while resuming
2094          * from another devices (e.g. serial console). */
2095         if (device_may_wakeup(&(pdev->dev)))
2096                 if (priv->wolenabled == PMT_SUPPORTED)
2097                         priv->hw->mac->pmt(dev->base_addr, 0);
2098
2099         netif_device_attach(dev);
2100
2101         /* Enable the MAC and DMA */
2102         stmmac_mac_enable_rx(ioaddr);
2103         stmmac_mac_enable_tx(ioaddr);
2104         stmmac_dma_start_tx(ioaddr);
2105         stmmac_dma_start_rx(ioaddr);
2106
2107 #ifdef CONFIG_STMMAC_TIMER
2108         priv->tm->timer_start(tmrate);
2109 #endif
2110         napi_enable(&priv->napi);
2111
2112         if (priv->phydev)
2113                 phy_start(priv->phydev);
2114
2115         netif_start_queue(dev);
2116
2117 out_resume:
2118         spin_unlock(&priv->lock);
2119         return 0;
2120 }
2121 #endif
2122
2123 static struct platform_driver stmmac_driver = {
2124         .driver = {
2125                    .name = STMMAC_RESOURCE_NAME,
2126                    },
2127         .probe = stmmac_dvr_probe,
2128         .remove = stmmac_dvr_remove,
2129 #ifdef CONFIG_PM
2130         .suspend = stmmac_suspend,
2131         .resume = stmmac_resume,
2132 #endif
2133
2134 };
2135
2136 /**
2137  * stmmac_init_module - Entry point for the driver
2138  * Description: This function is the entry point for the driver.
2139  */
2140 static int __init stmmac_init_module(void)
2141 {
2142         int ret;
2143
2144         if (platform_driver_register(&stmmacphy_driver)) {
2145                 pr_err("No PHY devices registered!\n");
2146                 return -ENODEV;
2147         }
2148
2149         ret = platform_driver_register(&stmmac_driver);
2150         return ret;
2151 }
2152
2153 /**
2154  * stmmac_cleanup_module - Cleanup routine for the driver
2155  * Description: This function is the cleanup routine for the driver.
2156  */
2157 static void __exit stmmac_cleanup_module(void)
2158 {
2159         platform_driver_unregister(&stmmacphy_driver);
2160         platform_driver_unregister(&stmmac_driver);
2161 }
2162
2163 #ifndef MODULE
2164 static int __init stmmac_cmdline_opt(char *str)
2165 {
2166         char *opt;
2167
2168         if (!str || !*str)
2169                 return -EINVAL;
2170         while ((opt = strsep(&str, ",")) != NULL) {
2171                 if (!strncmp(opt, "debug:", 6))
2172                         strict_strtoul(opt + 6, 0, (unsigned long *)&debug);
2173                 else if (!strncmp(opt, "phyaddr:", 8))
2174                         strict_strtoul(opt + 8, 0, (unsigned long *)&phyaddr);
2175                 else if (!strncmp(opt, "dma_txsize:", 11))
2176                         strict_strtoul(opt + 11, 0,
2177                                        (unsigned long *)&dma_txsize);
2178                 else if (!strncmp(opt, "dma_rxsize:", 11))
2179                         strict_strtoul(opt + 11, 0,
2180                                        (unsigned long *)&dma_rxsize);
2181                 else if (!strncmp(opt, "buf_sz:", 7))
2182                         strict_strtoul(opt + 7, 0, (unsigned long *)&buf_sz);
2183                 else if (!strncmp(opt, "tc:", 3))
2184                         strict_strtoul(opt + 3, 0, (unsigned long *)&tc);
2185                 else if (!strncmp(opt, "tx_coe:", 7))
2186                         strict_strtoul(opt + 7, 0, (unsigned long *)&tx_coe);
2187                 else if (!strncmp(opt, "watchdog:", 9))
2188                         strict_strtoul(opt + 9, 0, (unsigned long *)&watchdog);
2189                 else if (!strncmp(opt, "flow_ctrl:", 10))
2190                         strict_strtoul(opt + 10, 0,
2191                                        (unsigned long *)&flow_ctrl);
2192                 else if (!strncmp(opt, "pause:", 6))
2193                         strict_strtoul(opt + 6, 0, (unsigned long *)&pause);
2194 #ifdef CONFIG_STMMAC_TIMER
2195                 else if (!strncmp(opt, "tmrate:", 7))
2196                         strict_strtoul(opt + 7, 0, (unsigned long *)&tmrate);
2197 #endif
2198         }
2199         return 0;
2200 }
2201
2202 __setup("stmmaceth=", stmmac_cmdline_opt);
2203 #endif
2204
2205 module_init(stmmac_init_module);
2206 module_exit(stmmac_cleanup_module);
2207
2208 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet driver");
2209 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2210 MODULE_LICENSE("GPL");