1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
25 #include <linux/netdevice.h>
28 #undef CHIP_DEBUG_PRINT
29 /* Turn-on extra printk debug for MAC core, dma and descriptors */
30 /* #define CHIP_DEBUG_PRINT */
32 #ifdef CHIP_DEBUG_PRINT
33 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
35 #define CHIP_DBG(fmt, args...) do { } while (0)
38 #undef FRAME_FILTER_DEBUG
39 /* #define FRAME_FILTER_DEBUG */
41 struct stmmac_extra_stats {
43 unsigned long tx_underflow ____cacheline_aligned;
44 unsigned long tx_carrier;
45 unsigned long tx_losscarrier;
46 unsigned long tx_heartbeat;
47 unsigned long tx_deferred;
48 unsigned long tx_vlan;
49 unsigned long tx_jabber;
50 unsigned long tx_frame_flushed;
51 unsigned long tx_payload_error;
52 unsigned long tx_ip_header_error;
54 unsigned long rx_desc;
55 unsigned long rx_partial;
56 unsigned long rx_runt;
57 unsigned long rx_toolong;
58 unsigned long rx_collision;
60 unsigned long rx_length;
62 unsigned long rx_multicast;
63 unsigned long rx_gmac_overflow;
64 unsigned long rx_watchdog;
65 unsigned long da_rx_filter_fail;
66 unsigned long sa_rx_filter_fail;
67 unsigned long rx_missed_cntr;
68 unsigned long rx_overflow_cntr;
69 unsigned long rx_vlan;
70 /* Tx/Rx IRQ errors */
71 unsigned long tx_undeflow_irq;
72 unsigned long tx_process_stopped_irq;
73 unsigned long tx_jabber_irq;
74 unsigned long rx_overflow_irq;
75 unsigned long rx_buf_unav_irq;
76 unsigned long rx_process_stopped_irq;
77 unsigned long rx_watchdog_irq;
78 unsigned long tx_early_irq;
79 unsigned long fatal_bus_error_irq;
81 unsigned long threshold;
82 unsigned long tx_pkt_n;
83 unsigned long rx_pkt_n;
85 unsigned long sched_timer_n;
86 unsigned long normal_irq_n;
89 #define HASH_TABLE_SIZE 64
90 #define PAUSE_TIME 0x200
92 /* Flow Control defines */
96 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
98 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
102 enum rx_frame_status { /* IPC status */
108 enum tx_dma_irq_status {
110 tx_hard_error_bump_tc = 2,
114 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
115 #define BUF_SIZE_16KiB 16384
116 #define BUF_SIZE_8KiB 8192
117 #define BUF_SIZE_4KiB 4096
118 #define BUF_SIZE_2KiB 2048
120 /* Power Down and WOL */
121 #define PMT_NOT_SUPPORTED 0
122 #define PMT_SUPPORTED 1
124 /* Common MAC defines */
125 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
126 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
127 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
129 /* MAC Management Counters register */
130 #define MMC_CONTROL 0x00000100 /* MMC Control */
131 #define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
132 #define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
133 #define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
134 #define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
136 #define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
137 #define MMC_CONTROL_MAX_FRM_SHIFT 3
138 #define MMC_CONTROL_MAX_FRAME 0x7FF
140 struct stmmac_desc_ops {
141 /* DMA RX descriptor ring initialization */
142 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
144 /* DMA TX descriptor ring initialization */
145 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
147 /* Invoked by the xmit function to prepare the tx descriptor */
148 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
150 /* Set/get the owner of the descriptor */
151 void (*set_tx_owner) (struct dma_desc *p);
152 int (*get_tx_owner) (struct dma_desc *p);
153 /* Invoked by the xmit function to close the tx descriptor */
154 void (*close_tx_desc) (struct dma_desc *p);
155 /* Clean the tx descriptor as soon as the tx irq is received */
156 void (*release_tx_desc) (struct dma_desc *p);
157 /* Clear interrupt on tx frame completion. When this bit is
158 * set an interrupt happens as soon as the frame is transmitted */
159 void (*clear_tx_ic) (struct dma_desc *p);
160 /* Last tx segment reports the transmit status */
161 int (*get_tx_ls) (struct dma_desc *p);
162 /* Return the transmit status looking at the TDES1 */
163 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
164 struct dma_desc *p, unsigned long ioaddr);
165 /* Get the buffer size from the descriptor */
166 int (*get_tx_len) (struct dma_desc *p);
167 /* Handle extra events on specific interrupts hw dependent */
168 int (*get_rx_owner) (struct dma_desc *p);
169 void (*set_rx_owner) (struct dma_desc *p);
170 /* Get the receive frame size */
171 int (*get_rx_frame_len) (struct dma_desc *p);
172 /* Return the reception status looking at the RDES1 */
173 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
177 struct stmmac_dma_ops {
178 /* DMA core initialization */
179 int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
180 /* Dump DMA registers */
181 void (*dump_regs) (unsigned long ioaddr);
182 /* Set tx/rx threshold in the csr6 register
183 * An invalid value enables the store-and-forward mode */
184 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
185 /* To track extra statistic (if supported) */
186 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
187 unsigned long ioaddr);
188 void (*enable_dma_transmission) (unsigned long ioaddr);
189 void (*enable_dma_irq) (unsigned long ioaddr);
190 void (*disable_dma_irq) (unsigned long ioaddr);
191 void (*start_tx) (unsigned long ioaddr);
192 void (*stop_tx) (unsigned long ioaddr);
193 void (*start_rx) (unsigned long ioaddr);
194 void (*stop_rx) (unsigned long ioaddr);
195 int (*dma_interrupt) (unsigned long ioaddr,
196 struct stmmac_extra_stats *x);
200 /* MAC core initialization */
201 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
202 /* Dump MAC registers */
203 void (*dump_regs) (unsigned long ioaddr);
204 /* Handle extra events on specific interrupts hw dependent */
205 void (*host_irq_status) (unsigned long ioaddr);
206 /* Multicast filter setting */
207 void (*set_filter) (struct net_device *dev);
208 /* Flow control setting */
209 void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex,
210 unsigned int fc, unsigned int pause_time);
211 /* Set power management mode (e.g. magic frame) */
212 void (*pmt) (unsigned long ioaddr, unsigned long mode);
213 /* Set/Get Unicast MAC addresses */
214 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
216 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
227 unsigned int addr; /* MII Address */
228 unsigned int data; /* MII Data */
231 struct mac_device_info {
232 struct stmmac_ops *mac;
233 struct stmmac_desc_ops *desc;
234 struct stmmac_dma_ops *dma;
235 unsigned int pmt; /* support Power-Down */
236 struct mii_regs mii; /* MII register Addresses */
237 struct mac_link link;
240 struct mac_device_info *dwmac1000_setup(unsigned long addr);
241 struct mac_device_info *dwmac100_setup(unsigned long addr);
243 extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
244 unsigned int high, unsigned int low);
245 extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
246 unsigned int high, unsigned int low);