1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #if defined(EFX_ENABLE_DEBUG) && !defined(DEBUG)
20 #include <linux/version.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_vlan.h>
25 #include <linux/timer.h>
26 #include <linux/mdio.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/device.h>
30 #include <linux/highmem.h>
31 #include <linux/workqueue.h>
32 #include <linux/i2c.h>
37 /**************************************************************************
41 **************************************************************************/
43 #define EFX_DRIVER_VERSION "3.0"
45 #ifdef EFX_ENABLE_DEBUG
46 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
47 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
49 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
50 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
53 /**************************************************************************
57 **************************************************************************/
59 #define EFX_MAX_CHANNELS 32
60 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 /* Checksum generation is a per-queue option in hardware, so each
63 * queue visible to the networking core is backed by two hardware TX
65 #define EFX_MAX_CORE_TX_QUEUES EFX_MAX_CHANNELS
66 #define EFX_TXQ_TYPE_OFFLOAD 1
67 #define EFX_TXQ_TYPES 2
68 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CORE_TX_QUEUES)
71 * struct efx_special_buffer - An Efx special buffer
72 * @addr: CPU base address of the buffer
73 * @dma_addr: DMA base address of the buffer
74 * @len: Buffer length, in bytes
75 * @index: Buffer index within controller;s buffer table
76 * @entries: Number of buffer table entries
78 * Special buffers are used for the event queues and the TX and RX
79 * descriptor queues for each channel. They are *not* used for the
80 * actual transmit and receive buffers.
82 struct efx_special_buffer {
90 enum efx_flush_state {
98 * struct efx_tx_buffer - An Efx TX buffer
99 * @skb: The associated socket buffer.
100 * Set only on the final fragment of a packet; %NULL for all other
101 * fragments. When this fragment completes, then we can free this
103 * @tsoh: The associated TSO header structure, or %NULL if this
104 * buffer is not a TSO header.
105 * @dma_addr: DMA address of the fragment.
106 * @len: Length of this fragment.
107 * This field is zero when the queue slot is empty.
108 * @continuation: True if this fragment is not the end of a packet.
109 * @unmap_single: True if pci_unmap_single should be used.
110 * @unmap_len: Length of this fragment to unmap
112 struct efx_tx_buffer {
113 const struct sk_buff *skb;
114 struct efx_tso_header *tsoh;
119 unsigned short unmap_len;
123 * struct efx_tx_queue - An Efx TX queue
125 * This is a ring buffer of TX fragments.
126 * Since the TX completion path always executes on the same
127 * CPU and the xmit path can operate on different CPUs,
128 * performance is increased by ensuring that the completion
129 * path and the xmit path operate on different cache lines.
130 * This is particularly important if the xmit path is always
131 * executing on one CPU which is different from the completion
132 * path. There is also a cache line for members which are
133 * read but not written on the fast path.
135 * @efx: The associated Efx NIC
136 * @queue: DMA queue number
137 * @channel: The associated channel
138 * @buffer: The software buffer ring
139 * @txd: The hardware descriptor ring
140 * @ptr_mask: The size of the ring minus 1.
141 * @flushed: Used when handling queue flushing
142 * @read_count: Current read pointer.
143 * This is the number of buffers that have been removed from both rings.
144 * @stopped: Stopped count.
145 * Set if this TX queue is currently stopping its port.
146 * @insert_count: Current insert pointer
147 * This is the number of buffers that have been added to the
149 * @write_count: Current write pointer
150 * This is the number of buffers that have been added to the
152 * @old_read_count: The value of read_count when last checked.
153 * This is here for performance reasons. The xmit path will
154 * only get the up-to-date value of read_count if this
155 * variable indicates that the queue is full. This is to
156 * avoid cache-line ping-pong between the xmit path and the
158 * @tso_headers_free: A list of TSO headers allocated for this TX queue
159 * that are not in use, and so available for new TSO sends. The list
160 * is protected by the TX queue lock.
161 * @tso_bursts: Number of times TSO xmit invoked by kernel
162 * @tso_long_headers: Number of packets with headers too long for standard
164 * @tso_packets: Number of packets via the TSO xmit path
166 struct efx_tx_queue {
167 /* Members which don't change on the fast path */
168 struct efx_nic *efx ____cacheline_aligned_in_smp;
170 struct efx_channel *channel;
172 struct efx_tx_buffer *buffer;
173 struct efx_special_buffer txd;
174 unsigned int ptr_mask;
175 enum efx_flush_state flushed;
177 /* Members used mainly on the completion path */
178 unsigned int read_count ____cacheline_aligned_in_smp;
181 /* Members used only on the xmit path */
182 unsigned int insert_count ____cacheline_aligned_in_smp;
183 unsigned int write_count;
184 unsigned int old_read_count;
185 struct efx_tso_header *tso_headers_free;
186 unsigned int tso_bursts;
187 unsigned int tso_long_headers;
188 unsigned int tso_packets;
192 * struct efx_rx_buffer - An Efx RX data buffer
193 * @dma_addr: DMA base address of the buffer
194 * @skb: The associated socket buffer, if any.
195 * If both this and page are %NULL, the buffer slot is currently free.
196 * @page: The associated page buffer, if any.
197 * If both this and skb are %NULL, the buffer slot is currently free.
198 * @data: Pointer to ethernet header
199 * @len: Buffer length, in bytes.
201 struct efx_rx_buffer {
210 * struct efx_rx_page_state - Page-based rx buffer state
212 * Inserted at the start of every page allocated for receive buffers.
213 * Used to facilitate sharing dma mappings between recycled rx buffers
214 * and those passed up to the kernel.
216 * @refcnt: Number of struct efx_rx_buffer's referencing this page.
217 * When refcnt falls to zero, the page is unmapped for dma
218 * @dma_addr: The dma address of this page.
220 struct efx_rx_page_state {
224 unsigned int __pad[0] ____cacheline_aligned;
228 * struct efx_rx_queue - An Efx RX queue
229 * @efx: The associated Efx NIC
230 * @buffer: The software buffer ring
231 * @rxd: The hardware descriptor ring
232 * @ptr_mask: The size of the ring minus 1.
233 * @added_count: Number of buffers added to the receive queue.
234 * @notified_count: Number of buffers given to NIC (<= @added_count).
235 * @removed_count: Number of buffers removed from the receive queue.
236 * @max_fill: RX descriptor maximum fill level (<= ring size)
237 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
239 * @fast_fill_limit: The level to which a fast fill will fill
240 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
241 * @min_fill: RX descriptor minimum non-zero fill level.
242 * This records the minimum fill level observed when a ring
243 * refill was triggered.
244 * @alloc_page_count: RX allocation strategy counter.
245 * @alloc_skb_count: RX allocation strategy counter.
246 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
247 * @flushed: Use when handling queue flushing
249 struct efx_rx_queue {
251 struct efx_rx_buffer *buffer;
252 struct efx_special_buffer rxd;
253 unsigned int ptr_mask;
258 unsigned int max_fill;
259 unsigned int fast_fill_trigger;
260 unsigned int fast_fill_limit;
261 unsigned int min_fill;
262 unsigned int min_overfill;
263 unsigned int alloc_page_count;
264 unsigned int alloc_skb_count;
265 struct timer_list slow_fill;
266 unsigned int slow_fill_count;
268 enum efx_flush_state flushed;
272 * struct efx_buffer - An Efx general-purpose buffer
273 * @addr: host base address of the buffer
274 * @dma_addr: DMA base address of the buffer
275 * @len: Buffer length, in bytes
277 * The NIC uses these buffers for its interrupt status registers and
287 enum efx_rx_alloc_method {
288 RX_ALLOC_METHOD_AUTO = 0,
289 RX_ALLOC_METHOD_SKB = 1,
290 RX_ALLOC_METHOD_PAGE = 2,
294 * struct efx_channel - An Efx channel
296 * A channel comprises an event queue, at least one TX queue, at least
297 * one RX queue, and an associated tasklet for processing the event
300 * @efx: Associated Efx NIC
301 * @channel: Channel instance number
302 * @enabled: Channel enabled indicator
303 * @irq: IRQ number (MSI and MSI-X only)
304 * @irq_moderation: IRQ moderation value (in hardware ticks)
305 * @napi_dev: Net device used with NAPI
306 * @napi_str: NAPI control structure
307 * @reset_work: Scheduled reset work thread
308 * @work_pending: Is work pending via NAPI?
309 * @eventq: Event queue buffer
310 * @eventq_mask: Event queue pointer mask
311 * @eventq_read_ptr: Event queue read pointer
312 * @last_eventq_read_ptr: Last event queue read pointer value.
313 * @magic_count: Event queue test event count
314 * @irq_count: Number of IRQs since last adaptive moderation decision
315 * @irq_mod_score: IRQ moderation score
316 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
317 * and diagnostic counters
318 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
320 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
321 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
322 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
323 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
324 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
325 * @n_rx_overlength: Count of RX_OVERLENGTH errors
326 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
327 * @rx_queue: RX queue for this channel
328 * @tx_stop_count: Core TX queue stop count
329 * @tx_stop_lock: Core TX queue stop lock
330 * @tx_queue: TX queues for this channel
337 unsigned int irq_moderation;
338 struct net_device *napi_dev;
339 struct napi_struct napi_str;
341 struct efx_special_buffer eventq;
342 unsigned int eventq_mask;
343 unsigned int eventq_read_ptr;
344 unsigned int last_eventq_read_ptr;
345 unsigned int magic_count;
347 unsigned int irq_count;
348 unsigned int irq_mod_score;
351 int rx_alloc_push_pages;
353 unsigned n_rx_tobe_disc;
354 unsigned n_rx_ip_hdr_chksum_err;
355 unsigned n_rx_tcp_udp_chksum_err;
356 unsigned n_rx_mcast_mismatch;
357 unsigned n_rx_frm_trunc;
358 unsigned n_rx_overlength;
359 unsigned n_skbuff_leaks;
361 /* Used to pipeline received packets in order to optimise memory
362 * access with prefetches.
364 struct efx_rx_buffer *rx_pkt;
367 struct efx_rx_queue rx_queue;
369 atomic_t tx_stop_count;
370 spinlock_t tx_stop_lock;
372 struct efx_tx_queue tx_queue[2];
381 #define STRING_TABLE_LOOKUP(val, member) \
382 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
384 extern const char *efx_loopback_mode_names[];
385 extern const unsigned int efx_loopback_mode_max;
386 #define LOOPBACK_MODE(efx) \
387 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
389 extern const char *efx_interrupt_mode_names[];
390 extern const unsigned int efx_interrupt_mode_max;
391 #define INT_MODE(efx) \
392 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
394 extern const char *efx_reset_type_names[];
395 extern const unsigned int efx_reset_type_max;
396 #define RESET_TYPE(type) \
397 STRING_TABLE_LOOKUP(type, efx_reset_type)
400 /* Be careful if altering to correct macro below */
401 EFX_INT_MODE_MSIX = 0,
402 EFX_INT_MODE_MSI = 1,
403 EFX_INT_MODE_LEGACY = 2,
404 EFX_INT_MODE_MAX /* Insert any new items before this */
406 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
408 #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
419 * Alignment of page-allocated RX buffers
421 * Controls the number of bytes inserted at the start of an RX buffer.
422 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
423 * of the skb->head for hardware DMA].
425 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
426 #define EFX_PAGE_IP_ALIGN 0
428 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
432 * Alignment of the skb->head which wraps a page-allocated RX buffer
434 * The skb allocated to wrap an rx_buffer can have this alignment. Since
435 * the data is memcpy'd from the rx_buf, it does not need to be equal to
438 #define EFX_PAGE_SKB_ALIGN 2
440 /* Forward declaration */
443 /* Pseudo bit-mask flow control field */
445 EFX_FC_RX = FLOW_CTRL_RX,
446 EFX_FC_TX = FLOW_CTRL_TX,
451 * struct efx_link_state - Current state of the link
453 * @fd: Link is full-duplex
454 * @fc: Actual flow control flags
455 * @speed: Link speed (Mbps)
457 struct efx_link_state {
464 static inline bool efx_link_state_equal(const struct efx_link_state *left,
465 const struct efx_link_state *right)
467 return left->up == right->up && left->fd == right->fd &&
468 left->fc == right->fc && left->speed == right->speed;
472 * struct efx_mac_operations - Efx MAC operations table
473 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
474 * @update_stats: Update statistics
475 * @check_fault: Check fault state. True if fault present.
477 struct efx_mac_operations {
478 int (*reconfigure) (struct efx_nic *efx);
479 void (*update_stats) (struct efx_nic *efx);
480 bool (*check_fault)(struct efx_nic *efx);
484 * struct efx_phy_operations - Efx PHY operations table
485 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
486 * efx->loopback_modes.
487 * @init: Initialise PHY
488 * @fini: Shut down PHY
489 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
490 * @poll: Update @link_state and report whether it changed.
491 * Serialised by the mac_lock.
492 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
493 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
494 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
495 * (only needed where AN bit is set in mmds)
496 * @test_alive: Test that PHY is 'alive' (online)
497 * @test_name: Get the name of a PHY-specific test/result
498 * @run_tests: Run tests and record results as appropriate (offline).
499 * Flags are the ethtool tests flags.
501 struct efx_phy_operations {
502 int (*probe) (struct efx_nic *efx);
503 int (*init) (struct efx_nic *efx);
504 void (*fini) (struct efx_nic *efx);
505 void (*remove) (struct efx_nic *efx);
506 int (*reconfigure) (struct efx_nic *efx);
507 bool (*poll) (struct efx_nic *efx);
508 void (*get_settings) (struct efx_nic *efx,
509 struct ethtool_cmd *ecmd);
510 int (*set_settings) (struct efx_nic *efx,
511 struct ethtool_cmd *ecmd);
512 void (*set_npage_adv) (struct efx_nic *efx, u32);
513 int (*test_alive) (struct efx_nic *efx);
514 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
515 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
519 * @enum efx_phy_mode - PHY operating mode flags
520 * @PHY_MODE_NORMAL: on and should pass traffic
521 * @PHY_MODE_TX_DISABLED: on with TX disabled
522 * @PHY_MODE_LOW_POWER: set to low power through MDIO
523 * @PHY_MODE_OFF: switched off through external control
524 * @PHY_MODE_SPECIAL: on but will not pass traffic
528 PHY_MODE_TX_DISABLED = 1,
529 PHY_MODE_LOW_POWER = 2,
531 PHY_MODE_SPECIAL = 8,
534 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
536 return !!(mode & ~PHY_MODE_TX_DISABLED);
540 * Efx extended statistics
542 * Not all statistics are provided by all supported MACs. The purpose
543 * is this structure is to contain the raw statistics provided by each
546 struct efx_mac_stats {
550 unsigned long tx_packets;
551 unsigned long tx_bad;
552 unsigned long tx_pause;
553 unsigned long tx_control;
554 unsigned long tx_unicast;
555 unsigned long tx_multicast;
556 unsigned long tx_broadcast;
557 unsigned long tx_lt64;
559 unsigned long tx_65_to_127;
560 unsigned long tx_128_to_255;
561 unsigned long tx_256_to_511;
562 unsigned long tx_512_to_1023;
563 unsigned long tx_1024_to_15xx;
564 unsigned long tx_15xx_to_jumbo;
565 unsigned long tx_gtjumbo;
566 unsigned long tx_collision;
567 unsigned long tx_single_collision;
568 unsigned long tx_multiple_collision;
569 unsigned long tx_excessive_collision;
570 unsigned long tx_deferred;
571 unsigned long tx_late_collision;
572 unsigned long tx_excessive_deferred;
573 unsigned long tx_non_tcpudp;
574 unsigned long tx_mac_src_error;
575 unsigned long tx_ip_src_error;
579 unsigned long rx_packets;
580 unsigned long rx_good;
581 unsigned long rx_bad;
582 unsigned long rx_pause;
583 unsigned long rx_control;
584 unsigned long rx_unicast;
585 unsigned long rx_multicast;
586 unsigned long rx_broadcast;
587 unsigned long rx_lt64;
589 unsigned long rx_65_to_127;
590 unsigned long rx_128_to_255;
591 unsigned long rx_256_to_511;
592 unsigned long rx_512_to_1023;
593 unsigned long rx_1024_to_15xx;
594 unsigned long rx_15xx_to_jumbo;
595 unsigned long rx_gtjumbo;
596 unsigned long rx_bad_lt64;
597 unsigned long rx_bad_64_to_15xx;
598 unsigned long rx_bad_15xx_to_jumbo;
599 unsigned long rx_bad_gtjumbo;
600 unsigned long rx_overflow;
601 unsigned long rx_missed;
602 unsigned long rx_false_carrier;
603 unsigned long rx_symbol_error;
604 unsigned long rx_align_error;
605 unsigned long rx_length_error;
606 unsigned long rx_internal_error;
607 unsigned long rx_good_lt64;
610 /* Number of bits used in a multicast filter hash address */
611 #define EFX_MCAST_HASH_BITS 8
613 /* Number of (single-bit) entries in a multicast filter hash */
614 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
616 /* An Efx multicast filter hash */
617 union efx_multicast_hash {
618 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
619 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
622 struct efx_filter_state;
625 * struct efx_nic - an Efx NIC
626 * @name: Device name (net device name or bus id before net device registered)
627 * @pci_dev: The PCI device
628 * @type: Controller type attributes
629 * @legacy_irq: IRQ number
630 * @workqueue: Workqueue for port reconfigures and the HW monitor.
631 * Work items do not hold and must not acquire RTNL.
632 * @workqueue_name: Name of workqueue
633 * @reset_work: Scheduled reset workitem
634 * @monitor_work: Hardware monitor workitem
635 * @membase_phys: Memory BAR value as physical address
636 * @membase: Memory BAR value
637 * @biu_lock: BIU (bus interface unit) lock
638 * @interrupt_mode: Interrupt mode
639 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
640 * @irq_rx_moderation: IRQ moderation time for RX event queues
641 * @msg_enable: Log message enable flags
642 * @state: Device state flag. Serialised by the rtnl_lock.
643 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
644 * @tx_queue: TX DMA queues
645 * @rx_queue: RX DMA queues
647 * @channel_name: Names for channels and their IRQs
648 * @rxq_entries: Size of receive queues requested by user.
649 * @txq_entries: Size of transmit queues requested by user.
650 * @next_buffer_table: First available buffer table id
651 * @n_channels: Number of channels in use
652 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
653 * @n_tx_channels: Number of channels used for TX
654 * @rx_buffer_len: RX buffer length
655 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
656 * @rx_indir_table: Indirection table for RSS
657 * @int_error_count: Number of internal errors seen recently
658 * @int_error_expire: Time at which error count will be expired
659 * @irq_status: Interrupt status buffer
660 * @last_irq_cpu: Last CPU to handle interrupt.
661 * This register is written with the SMP processor ID whenever an
662 * interrupt is handled. It is used by efx_nic_test_interrupt()
663 * to verify that an interrupt has occurred.
664 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
665 * @fatal_irq_level: IRQ level (bit number) used for serious errors
666 * @spi_flash: SPI flash device
667 * This field will be %NULL if no flash device is present (or for Siena).
668 * @spi_eeprom: SPI EEPROM device
669 * This field will be %NULL if no EEPROM device is present (or for Siena).
670 * @spi_lock: SPI bus lock
671 * @mtd_list: List of MTDs attached to the NIC
672 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
673 * @nic_data: Hardware dependant state
674 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
675 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
676 * @port_enabled: Port enabled indicator.
677 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
678 * efx_mac_work() with kernel interfaces. Safe to read under any
679 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
680 * be held to modify it.
681 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
682 * @port_initialized: Port initialized?
683 * @net_dev: Operating system network device. Consider holding the rtnl lock
684 * @rx_checksum_enabled: RX checksumming enabled
685 * @mac_stats: MAC statistics. These include all statistics the MACs
686 * can provide. Generic code converts these into a standard
687 * &struct net_device_stats.
688 * @stats_buffer: DMA buffer for statistics
689 * @stats_lock: Statistics update lock. Serialises statistics fetches
690 * @mac_op: MAC interface
691 * @mac_address: Permanent MAC address
692 * @phy_type: PHY type
693 * @mdio_lock: MDIO lock
694 * @phy_op: PHY interface
695 * @phy_data: PHY private data (including PHY-specific stats)
696 * @mdio: PHY MDIO interface
697 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
698 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
699 * @xmac_poll_required: XMAC link state needs polling
700 * @link_advertising: Autonegotiation advertising flags
701 * @link_state: Current state of the link
702 * @n_link_state_changes: Number of times the link has changed state
703 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
704 * @multicast_hash: Multicast hash table
705 * @wanted_fc: Wanted flow control flags
706 * @mac_work: Work item for changing MAC promiscuity and multicast hash
707 * @loopback_mode: Loopback status
708 * @loopback_modes: Supported loopback mode bitmask
709 * @loopback_selftest: Offline self-test private state
711 * This is stored in the private area of the &struct net_device.
715 struct pci_dev *pci_dev;
716 const struct efx_nic_type *type;
718 struct workqueue_struct *workqueue;
719 char workqueue_name[16];
720 struct work_struct reset_work;
721 struct delayed_work monitor_work;
722 resource_size_t membase_phys;
723 void __iomem *membase;
725 enum efx_int_mode interrupt_mode;
726 bool irq_rx_adaptive;
727 unsigned int irq_rx_moderation;
730 enum nic_state state;
731 enum reset_type reset_pending;
733 struct efx_channel *channel[EFX_MAX_CHANNELS];
734 char channel_name[EFX_MAX_CHANNELS][IFNAMSIZ + 6];
736 unsigned rxq_entries;
737 unsigned txq_entries;
738 unsigned next_buffer_table;
740 unsigned n_rx_channels;
741 unsigned n_tx_channels;
742 unsigned int rx_buffer_len;
743 unsigned int rx_buffer_order;
745 u32 rx_indir_table[128];
747 unsigned int_error_count;
748 unsigned long int_error_expire;
750 struct efx_buffer irq_status;
751 volatile signed int last_irq_cpu;
752 unsigned irq_zero_count;
753 unsigned fatal_irq_level;
755 struct efx_spi_device *spi_flash;
756 struct efx_spi_device *spi_eeprom;
757 struct mutex spi_lock;
758 #ifdef CONFIG_SFC_MTD
759 struct list_head mtd_list;
762 unsigned n_rx_nodesc_drop_cnt;
766 struct mutex mac_lock;
767 struct work_struct mac_work;
771 bool port_initialized;
772 struct net_device *net_dev;
773 bool rx_checksum_enabled;
775 struct efx_mac_stats mac_stats;
776 struct efx_buffer stats_buffer;
777 spinlock_t stats_lock;
779 struct efx_mac_operations *mac_op;
780 unsigned char mac_address[ETH_ALEN];
782 unsigned int phy_type;
783 struct mutex mdio_lock;
784 struct efx_phy_operations *phy_op;
786 struct mdio_if_info mdio;
787 unsigned int mdio_bus;
788 enum efx_phy_mode phy_mode;
790 bool xmac_poll_required;
791 u32 link_advertising;
792 struct efx_link_state link_state;
793 unsigned int n_link_state_changes;
796 union efx_multicast_hash multicast_hash;
797 enum efx_fc_type wanted_fc;
800 enum efx_loopback_mode loopback_mode;
803 void *loopback_selftest;
805 struct efx_filter_state *filter_state;
808 static inline int efx_dev_registered(struct efx_nic *efx)
810 return efx->net_dev->reg_state == NETREG_REGISTERED;
813 /* Net device name, for inclusion in log messages if it has been registered.
814 * Use efx->name not efx->net_dev->name so that races with (un)registration
817 static inline const char *efx_dev_name(struct efx_nic *efx)
819 return efx_dev_registered(efx) ? efx->name : "";
822 static inline unsigned int efx_port_num(struct efx_nic *efx)
824 return efx->net_dev->dev_id;
828 * struct efx_nic_type - Efx device type definition
829 * @probe: Probe the controller
830 * @remove: Free resources allocated by probe()
831 * @init: Initialise the controller
832 * @fini: Shut down the controller
833 * @monitor: Periodic function for polling link state and hardware monitor
834 * @reset: Reset the controller hardware and possibly the PHY. This will
835 * be called while the controller is uninitialised.
836 * @probe_port: Probe the MAC and PHY
837 * @remove_port: Free resources allocated by probe_port()
838 * @prepare_flush: Prepare the hardware for flushing the DMA queues
839 * @update_stats: Update statistics not provided by event handling
840 * @start_stats: Start the regular fetching of statistics
841 * @stop_stats: Stop the regular fetching of statistics
842 * @set_id_led: Set state of identifying LED or revert to automatic function
843 * @push_irq_moderation: Apply interrupt moderation value
844 * @push_multicast_hash: Apply multicast hash table
845 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
846 * @get_wol: Get WoL configuration from driver state
847 * @set_wol: Push WoL configuration to the NIC
848 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
849 * @test_registers: Test read/write functionality of control registers
850 * @test_nvram: Test validity of NVRAM contents
851 * @default_mac_ops: efx_mac_operations to set at startup
852 * @revision: Hardware architecture revision
853 * @mem_map_size: Memory BAR mapped size
854 * @txd_ptr_tbl_base: TX descriptor ring base address
855 * @rxd_ptr_tbl_base: RX descriptor ring base address
856 * @buf_tbl_base: Buffer table base address
857 * @evq_ptr_tbl_base: Event queue pointer table base address
858 * @evq_rptr_tbl_base: Event queue read-pointer table base address
859 * @max_dma_mask: Maximum possible DMA mask
860 * @rx_buffer_hash_size: Size of hash at start of RX buffer
861 * @rx_buffer_padding: Size of padding at end of RX buffer
862 * @max_interrupt_mode: Highest capability interrupt mode supported
863 * from &enum efx_init_mode.
864 * @phys_addr_channels: Number of channels with physically addressed
866 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
867 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
868 * @offload_features: net_device feature flags for protocol offload
869 * features implemented in hardware
870 * @reset_world_flags: Flags for additional components covered by
871 * reset method RESET_TYPE_WORLD
873 struct efx_nic_type {
874 int (*probe)(struct efx_nic *efx);
875 void (*remove)(struct efx_nic *efx);
876 int (*init)(struct efx_nic *efx);
877 void (*fini)(struct efx_nic *efx);
878 void (*monitor)(struct efx_nic *efx);
879 int (*reset)(struct efx_nic *efx, enum reset_type method);
880 int (*probe_port)(struct efx_nic *efx);
881 void (*remove_port)(struct efx_nic *efx);
882 void (*prepare_flush)(struct efx_nic *efx);
883 void (*update_stats)(struct efx_nic *efx);
884 void (*start_stats)(struct efx_nic *efx);
885 void (*stop_stats)(struct efx_nic *efx);
886 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
887 void (*push_irq_moderation)(struct efx_channel *channel);
888 void (*push_multicast_hash)(struct efx_nic *efx);
889 int (*reconfigure_port)(struct efx_nic *efx);
890 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
891 int (*set_wol)(struct efx_nic *efx, u32 type);
892 void (*resume_wol)(struct efx_nic *efx);
893 int (*test_registers)(struct efx_nic *efx);
894 int (*test_nvram)(struct efx_nic *efx);
895 struct efx_mac_operations *default_mac_ops;
898 unsigned int mem_map_size;
899 unsigned int txd_ptr_tbl_base;
900 unsigned int rxd_ptr_tbl_base;
901 unsigned int buf_tbl_base;
902 unsigned int evq_ptr_tbl_base;
903 unsigned int evq_rptr_tbl_base;
905 unsigned int rx_buffer_hash_size;
906 unsigned int rx_buffer_padding;
907 unsigned int max_interrupt_mode;
908 unsigned int phys_addr_channels;
909 unsigned int tx_dc_base;
910 unsigned int rx_dc_base;
911 unsigned long offload_features;
912 u32 reset_world_flags;
915 /**************************************************************************
917 * Prototypes and inline functions
919 *************************************************************************/
921 static inline struct efx_channel *
922 efx_get_channel(struct efx_nic *efx, unsigned index)
924 EFX_BUG_ON_PARANOID(index >= efx->n_channels);
925 return efx->channel[index];
928 /* Iterate over all used channels */
929 #define efx_for_each_channel(_channel, _efx) \
930 for (_channel = (_efx)->channel[0]; \
932 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
933 (_efx)->channel[_channel->channel + 1] : NULL)
935 extern struct efx_tx_queue *
936 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type);
938 static inline struct efx_tx_queue *
939 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
941 struct efx_tx_queue *tx_queue = channel->tx_queue;
942 EFX_BUG_ON_PARANOID(type >= EFX_TXQ_TYPES);
943 return tx_queue->channel ? tx_queue + type : NULL;
946 /* Iterate over all TX queues belonging to a channel */
947 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
948 for (_tx_queue = efx_channel_get_tx_queue(channel, 0); \
949 _tx_queue && _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
952 static inline struct efx_rx_queue *
953 efx_get_rx_queue(struct efx_nic *efx, unsigned index)
955 EFX_BUG_ON_PARANOID(index >= efx->n_rx_channels);
956 return &efx->channel[index]->rx_queue;
959 static inline struct efx_rx_queue *
960 efx_channel_get_rx_queue(struct efx_channel *channel)
962 return channel->channel < channel->efx->n_rx_channels ?
963 &channel->rx_queue : NULL;
966 /* Iterate over all RX queues belonging to a channel */
967 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
968 for (_rx_queue = efx_channel_get_rx_queue(channel); \
972 static inline struct efx_channel *
973 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
975 return container_of(rx_queue, struct efx_channel, rx_queue);
978 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
980 return efx_rx_queue_channel(rx_queue)->channel;
983 /* Returns a pointer to the specified receive buffer in the RX
986 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
989 return (&rx_queue->buffer[index]);
992 /* Set bit in a little-endian bitfield */
993 static inline void set_bit_le(unsigned nr, unsigned char *addr)
995 addr[nr / 8] |= (1 << (nr % 8));
998 /* Clear bit in a little-endian bitfield */
999 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
1001 addr[nr / 8] &= ~(1 << (nr % 8));
1006 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1008 * This calculates the maximum frame length that will be used for a
1009 * given MTU. The frame length will be equal to the MTU plus a
1010 * constant amount of header space and padding. This is the quantity
1011 * that the net driver will program into the MAC as the maximum frame
1014 * The 10G MAC requires 8-byte alignment on the frame
1015 * length, so we round up to the nearest 8.
1017 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1018 * XGMII cycle). If the frame length reaches the maximum value in the
1019 * same cycle, the XMAC can miss the IPG altogether. We work around
1020 * this by adding a further 16 bytes.
1022 #define EFX_MAX_FRAME_LEN(mtu) \
1023 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1026 #endif /* EFX_NET_DRIVER_H */