drivers/net/qlcnic/qlcnic_hw.c

   1 /*
   2  * Copyright (C) 2009 - QLogic Corporation.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called "COPYING".
  22  *
  23  */
  24
  25 #include "qlcnic.h"
  26
  27 #include <linux/slab.h>
  28 #include <net/ip.h>
  29
  30 #define MASK(n) ((1ULL<<(n))-1)
  31 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
  32
  33 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
  34
  35 #define CRB_BLK(off)    ((off >> 20) & 0x3f)
  36 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
  37 #define CRB_WINDOW_2M   (0x130060)
  38 #define CRB_HI(off)     ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
  39 #define CRB_INDIRECT_2M (0x1e0000UL)
  40
  41
  42 #ifndef readq
  43 static inline u64 readq(void __iomem *addr)
  44 {
  45         return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
  46 }
  47 #endif
  48
  49 #ifndef writeq
  50 static inline void writeq(u64 val, void __iomem *addr)
  51 {
  52         writel(((u32) (val)), (addr));
  53         writel(((u32) (val >> 32)), (addr + 4));
  54 }
  55 #endif
  56
  57 static const struct crb_128M_2M_block_map
  58 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
  59     {{{0, 0,         0,         0} } },         /* 0: PCI */
  60     {{{1, 0x0100000, 0x0102000, 0x120000},      /* 1: PCIE */
  61           {1, 0x0110000, 0x0120000, 0x130000},
  62           {1, 0x0120000, 0x0122000, 0x124000},
  63           {1, 0x0130000, 0x0132000, 0x126000},
  64           {1, 0x0140000, 0x0142000, 0x128000},
  65           {1, 0x0150000, 0x0152000, 0x12a000},
  66           {1, 0x0160000, 0x0170000, 0x110000},
  67           {1, 0x0170000, 0x0172000, 0x12e000},
  68           {0, 0x0000000, 0x0000000, 0x000000},
  69           {0, 0x0000000, 0x0000000, 0x000000},
  70           {0, 0x0000000, 0x0000000, 0x000000},
  71           {0, 0x0000000, 0x0000000, 0x000000},
  72           {0, 0x0000000, 0x0000000, 0x000000},
  73           {0, 0x0000000, 0x0000000, 0x000000},
  74           {1, 0x01e0000, 0x01e0800, 0x122000},
  75           {0, 0x0000000, 0x0000000, 0x000000} } },
  76         {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
  77     {{{0, 0,         0,         0} } },     /* 3: */
  78     {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
  79     {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
  80     {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
  81     {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
  82     {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
  83       {0, 0x0000000, 0x0000000, 0x000000},
  84       {0, 0x0000000, 0x0000000, 0x000000},
  85       {0, 0x0000000, 0x0000000, 0x000000},
  86       {0, 0x0000000, 0x0000000, 0x000000},
  87       {0, 0x0000000, 0x0000000, 0x000000},
  88       {0, 0x0000000, 0x0000000, 0x000000},
  89       {0, 0x0000000, 0x0000000, 0x000000},
  90       {0, 0x0000000, 0x0000000, 0x000000},
  91       {0, 0x0000000, 0x0000000, 0x000000},
  92       {0, 0x0000000, 0x0000000, 0x000000},
  93       {0, 0x0000000, 0x0000000, 0x000000},
  94       {0, 0x0000000, 0x0000000, 0x000000},
  95       {0, 0x0000000, 0x0000000, 0x000000},
  96       {0, 0x0000000, 0x0000000, 0x000000},
  97       {1, 0x08f0000, 0x08f2000, 0x172000} } },
  98     {{{1, 0x0900000, 0x0902000, 0x174000},      /* 9: SQM1*/
  99       {0, 0x0000000, 0x0000000, 0x000000},
 100       {0, 0x0000000, 0x0000000, 0x000000},
 101       {0, 0x0000000, 0x0000000, 0x000000},
 102       {0, 0x0000000, 0x0000000, 0x000000},
 103       {0, 0x0000000, 0x0000000, 0x000000},
 104       {0, 0x0000000, 0x0000000, 0x000000},
 105       {0, 0x0000000, 0x0000000, 0x000000},
 106       {0, 0x0000000, 0x0000000, 0x000000},
 107       {0, 0x0000000, 0x0000000, 0x000000},
 108       {0, 0x0000000, 0x0000000, 0x000000},
 109       {0, 0x0000000, 0x0000000, 0x000000},
 110       {0, 0x0000000, 0x0000000, 0x000000},
 111       {0, 0x0000000, 0x0000000, 0x000000},
 112       {0, 0x0000000, 0x0000000, 0x000000},
 113       {1, 0x09f0000, 0x09f2000, 0x176000} } },
 114     {{{0, 0x0a00000, 0x0a02000, 0x178000},      /* 10: SQM2*/
 115       {0, 0x0000000, 0x0000000, 0x000000},
 116       {0, 0x0000000, 0x0000000, 0x000000},
 117       {0, 0x0000000, 0x0000000, 0x000000},
 118       {0, 0x0000000, 0x0000000, 0x000000},
 119       {0, 0x0000000, 0x0000000, 0x000000},
 120       {0, 0x0000000, 0x0000000, 0x000000},
 121       {0, 0x0000000, 0x0000000, 0x000000},
 122       {0, 0x0000000, 0x0000000, 0x000000},
 123       {0, 0x0000000, 0x0000000, 0x000000},
 124       {0, 0x0000000, 0x0000000, 0x000000},
 125       {0, 0x0000000, 0x0000000, 0x000000},
 126       {0, 0x0000000, 0x0000000, 0x000000},
 127       {0, 0x0000000, 0x0000000, 0x000000},
 128       {0, 0x0000000, 0x0000000, 0x000000},
 129       {1, 0x0af0000, 0x0af2000, 0x17a000} } },
 130     {{{0, 0x0b00000, 0x0b02000, 0x17c000},      /* 11: SQM3*/
 131       {0, 0x0000000, 0x0000000, 0x000000},
 132       {0, 0x0000000, 0x0000000, 0x000000},
 133       {0, 0x0000000, 0x0000000, 0x000000},
 134       {0, 0x0000000, 0x0000000, 0x000000},
 135       {0, 0x0000000, 0x0000000, 0x000000},
 136       {0, 0x0000000, 0x0000000, 0x000000},
 137       {0, 0x0000000, 0x0000000, 0x000000},
 138       {0, 0x0000000, 0x0000000, 0x000000},
 139       {0, 0x0000000, 0x0000000, 0x000000},
 140       {0, 0x0000000, 0x0000000, 0x000000},
 141       {0, 0x0000000, 0x0000000, 0x000000},
 142       {0, 0x0000000, 0x0000000, 0x000000},
 143       {0, 0x0000000, 0x0000000, 0x000000},
 144       {0, 0x0000000, 0x0000000, 0x000000},
 145       {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
 146         {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
 147         {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
 148         {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
 149         {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
 150         {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
 151         {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
 152         {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
 153         {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
 154         {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
 155         {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
 156         {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
 157         {{{0, 0,         0,         0} } },     /* 23: */
 158         {{{0, 0,         0,         0} } },     /* 24: */
 159         {{{0, 0,         0,         0} } },     /* 25: */
 160         {{{0, 0,         0,         0} } },     /* 26: */
 161         {{{0, 0,         0,         0} } },     /* 27: */
 162         {{{0, 0,         0,         0} } },     /* 28: */
 163         {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
 164     {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
 165     {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
 166         {{{0} } },                              /* 32: PCI */
 167         {{{1, 0x2100000, 0x2102000, 0x120000},  /* 33: PCIE */
 168           {1, 0x2110000, 0x2120000, 0x130000},
 169           {1, 0x2120000, 0x2122000, 0x124000},
 170           {1, 0x2130000, 0x2132000, 0x126000},
 171           {1, 0x2140000, 0x2142000, 0x128000},
 172           {1, 0x2150000, 0x2152000, 0x12a000},
 173           {1, 0x2160000, 0x2170000, 0x110000},
 174           {1, 0x2170000, 0x2172000, 0x12e000},
 175           {0, 0x0000000, 0x0000000, 0x000000},
 176           {0, 0x0000000, 0x0000000, 0x000000},
 177           {0, 0x0000000, 0x0000000, 0x000000},
 178           {0, 0x0000000, 0x0000000, 0x000000},
 179           {0, 0x0000000, 0x0000000, 0x000000},
 180           {0, 0x0000000, 0x0000000, 0x000000},
 181           {0, 0x0000000, 0x0000000, 0x000000},
 182           {0, 0x0000000, 0x0000000, 0x000000} } },
 183         {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
 184         {{{0} } },                              /* 35: */
 185         {{{0} } },                              /* 36: */
 186         {{{0} } },                              /* 37: */
 187         {{{0} } },                              /* 38: */
 188         {{{0} } },                              /* 39: */
 189         {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
 190         {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
 191         {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
 192         {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
 193         {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
 194         {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
 195         {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
 196         {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
 197         {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
 198         {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
 199         {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
 200         {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
 201         {{{0} } },                              /* 52: */
 202         {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
 203         {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
 204         {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
 205         {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
 206         {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
 207         {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
 208         {{{0} } },                              /* 59: I2C0 */
 209         {{{0} } },                              /* 60: I2C1 */
 210         {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
 211         {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
 212         {{{1, 0x3f00000, 0x3f01000, 0x168000} } }       /* 63: P2NR0 */
 213 };
 214
 215 /*
 216  * top 12 bits of crb internal address (hub, agent)
 217  */
 218 static const unsigned crb_hub_agt[64] = {
 219         0,
 220         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 221         QLCNIC_HW_CRB_HUB_AGT_ADR_MN,
 222         QLCNIC_HW_CRB_HUB_AGT_ADR_MS,
 223         0,
 224         QLCNIC_HW_CRB_HUB_AGT_ADR_SRE,
 225         QLCNIC_HW_CRB_HUB_AGT_ADR_NIU,
 226         QLCNIC_HW_CRB_HUB_AGT_ADR_QMN,
 227         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN0,
 228         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN1,
 229         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN2,
 230         QLCNIC_HW_CRB_HUB_AGT_ADR_SQN3,
 231         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 232         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 233         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 234         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN4,
 235         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 236         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN0,
 237         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN1,
 238         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN2,
 239         QLCNIC_HW_CRB_HUB_AGT_ADR_PGN3,
 240         QLCNIC_HW_CRB_HUB_AGT_ADR_PGND,
 241         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNI,
 242         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS0,
 243         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS1,
 244         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS2,
 245         QLCNIC_HW_CRB_HUB_AGT_ADR_PGS3,
 246         0,
 247         QLCNIC_HW_CRB_HUB_AGT_ADR_PGSI,
 248         QLCNIC_HW_CRB_HUB_AGT_ADR_SN,
 249         0,
 250         QLCNIC_HW_CRB_HUB_AGT_ADR_EG,
 251         0,
 252         QLCNIC_HW_CRB_HUB_AGT_ADR_PS,
 253         QLCNIC_HW_CRB_HUB_AGT_ADR_CAM,
 254         0,
 255         0,
 256         0,
 257         0,
 258         0,
 259         QLCNIC_HW_CRB_HUB_AGT_ADR_TIMR,
 260         0,
 261         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX1,
 262         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX2,
 263         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX3,
 264         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX4,
 265         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX5,
 266         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX6,
 267         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX7,
 268         QLCNIC_HW_CRB_HUB_AGT_ADR_XDMA,
 269         QLCNIC_HW_CRB_HUB_AGT_ADR_I2Q,
 270         QLCNIC_HW_CRB_HUB_AGT_ADR_ROMUSB,
 271         0,
 272         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX0,
 273         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX8,
 274         QLCNIC_HW_CRB_HUB_AGT_ADR_RPMX9,
 275         QLCNIC_HW_CRB_HUB_AGT_ADR_OCM0,
 276         0,
 277         QLCNIC_HW_CRB_HUB_AGT_ADR_SMB,
 278         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C0,
 279         QLCNIC_HW_CRB_HUB_AGT_ADR_I2C1,
 280         0,
 281         QLCNIC_HW_CRB_HUB_AGT_ADR_PGNC,
 282         0,
 283 };
 284
 285 /*  PCI Windowing for DDR regions.  */
 286
 287 #define QLCNIC_PCIE_SEM_TIMEOUT 10000
 288
 289 int
 290 qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
 291 {
 292         int done = 0, timeout = 0;
 293
 294         while (!done) {
 295                 done = QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_LOCK(sem)));
 296                 if (done == 1)
 297                         break;
 298                 if (++timeout >= QLCNIC_PCIE_SEM_TIMEOUT) {
 299                         dev_err(&adapter->pdev->dev,
 300                                 "Failed to acquire sem=%d lock; holdby=%d\n",
 301                                 sem, id_reg ? QLCRD32(adapter, id_reg) : -1);
 302                         return -EIO;
 303                 }
 304                 msleep(1);
 305         }
 306
 307         if (id_reg)
 308                 QLCWR32(adapter, id_reg, adapter->portnum);
 309
 310         return 0;
 311 }
 312
 313 void
 314 qlcnic_pcie_sem_unlock(struct qlcnic_adapter *adapter, int sem)
 315 {
 316         QLCRD32(adapter, QLCNIC_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
 317 }
 318
 319 static int
 320 qlcnic_send_cmd_descs(struct qlcnic_adapter *adapter,
 321                 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
 322 {
 323         u32 i, producer, consumer;
 324         struct qlcnic_cmd_buffer *pbuf;
 325         struct cmd_desc_type0 *cmd_desc;
 326         struct qlcnic_host_tx_ring *tx_ring;
 327
 328         i = 0;
 329
 330         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 331                 return -EIO;
 332
 333         tx_ring = adapter->tx_ring;
 334         __netif_tx_lock_bh(tx_ring->txq);
 335
 336         producer = tx_ring->producer;
 337         consumer = tx_ring->sw_consumer;
 338
 339         if (nr_desc >= qlcnic_tx_avail(tx_ring)) {
 340                 netif_tx_stop_queue(tx_ring->txq);
 341                 smp_mb();
 342                 if (qlcnic_tx_avail(tx_ring) > nr_desc) {
 343                         if (qlcnic_tx_avail(tx_ring) > TX_STOP_THRESH)
 344                                 netif_tx_wake_queue(tx_ring->txq);
 345                 } else {
 346                         adapter->stats.xmit_off++;
 347                         __netif_tx_unlock_bh(tx_ring->txq);
 348                         return -EBUSY;
 349                 }
 350         }
 351
 352         do {
 353                 cmd_desc = &cmd_desc_arr[i];
 354
 355                 pbuf = &tx_ring->cmd_buf_arr[producer];
 356                 pbuf->skb = NULL;
 357                 pbuf->frag_count = 0;
 358
 359                 memcpy(&tx_ring->desc_head[producer],
 360                         &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
 361
 362                 producer = get_next_index(producer, tx_ring->num_desc);
 363                 i++;
 364
 365         } while (i != nr_desc);
 366
 367         tx_ring->producer = producer;
 368
 369         qlcnic_update_cmd_producer(adapter, tx_ring);
 370
 371         __netif_tx_unlock_bh(tx_ring->txq);
 372
 373         return 0;
 374 }
 375
 376 static int
 377 qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter, u8 *addr,
 378                                 __le16 vlan_id, unsigned op)
 379 {
 380         struct qlcnic_nic_req req;
 381         struct qlcnic_mac_req *mac_req;
 382         struct qlcnic_vlan_req *vlan_req;
 383         u64 word;
 384
 385         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 386         req.qhdr = cpu_to_le64(QLCNIC_REQUEST << 23);
 387
 388         word = QLCNIC_MAC_EVENT | ((u64)adapter->portnum << 16);
 389         req.req_hdr = cpu_to_le64(word);
 390
 391         mac_req = (struct qlcnic_mac_req *)&req.words[0];
 392         mac_req->op = op;
 393         memcpy(mac_req->mac_addr, addr, 6);
 394
 395         vlan_req = (struct qlcnic_vlan_req *)&req.words[1];
 396         vlan_req->vlan_id = vlan_id;
 397
 398         return qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 399 }
 400
 401 static int qlcnic_nic_add_mac(struct qlcnic_adapter *adapter, u8 *addr)
 402 {
 403         struct list_head *head;
 404         struct qlcnic_mac_list_s *cur;
 405
 406         /* look up if already exists */
 407         list_for_each(head, &adapter->mac_list) {
 408                 cur = list_entry(head, struct qlcnic_mac_list_s, list);
 409                 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
 410                         return 0;
 411         }
 412
 413         cur = kzalloc(sizeof(struct qlcnic_mac_list_s), GFP_ATOMIC);
 414         if (cur == NULL) {
 415                 dev_err(&adapter->netdev->dev,
 416                         "failed to add mac address filter\n");
 417                 return -ENOMEM;
 418         }
 419         memcpy(cur->mac_addr, addr, ETH_ALEN);
 420
 421         if (qlcnic_sre_macaddr_change(adapter,
 422                                 cur->mac_addr, 0, QLCNIC_MAC_ADD)) {
 423                 kfree(cur);
 424                 return -EIO;
 425         }
 426
 427         list_add_tail(&cur->list, &adapter->mac_list);
 428         return 0;
 429 }
 430
 431 void qlcnic_set_multi(struct net_device *netdev)
 432 {
 433         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 434         struct netdev_hw_addr *ha;
 435         u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 436         u32 mode = VPORT_MISS_MODE_DROP;
 437
 438         if (!test_bit(__QLCNIC_FW_ATTACHED, &adapter->state))
 439                 return;
 440
 441         qlcnic_nic_add_mac(adapter, adapter->mac_addr);
 442         qlcnic_nic_add_mac(adapter, bcast_addr);
 443
 444         if (netdev->flags & IFF_PROMISC) {
 445                 if (!(adapter->flags & QLCNIC_PROMISC_DISABLED))
 446                         mode = VPORT_MISS_MODE_ACCEPT_ALL;
 447                 goto send_fw_cmd;
 448         }
 449
 450         if ((netdev->flags & IFF_ALLMULTI) ||
 451             (netdev_mc_count(netdev) > adapter->max_mc_count)) {
 452                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
 453                 goto send_fw_cmd;
 454         }
 455
 456         if (!netdev_mc_empty(netdev)) {
 457                 netdev_for_each_mc_addr(ha, netdev) {
 458                         qlcnic_nic_add_mac(adapter, ha->addr);
 459                 }
 460         }
 461
 462 send_fw_cmd:
 463         qlcnic_nic_set_promisc(adapter, mode);
 464 }
 465
 466 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32 mode)
 467 {
 468         struct qlcnic_nic_req req;
 469         u64 word;
 470
 471         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 472
 473         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 474
 475         word = QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
 476                         ((u64)adapter->portnum << 16);
 477         req.req_hdr = cpu_to_le64(word);
 478
 479         req.words[0] = cpu_to_le64(mode);
 480
 481         return qlcnic_send_cmd_descs(adapter,
 482                                 (struct cmd_desc_type0 *)&req, 1);
 483 }
 484
 485 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
 486 {
 487         struct qlcnic_mac_list_s *cur;
 488         struct list_head *head = &adapter->mac_list;
 489
 490         while (!list_empty(head)) {
 491                 cur = list_entry(head->next, struct qlcnic_mac_list_s, list);
 492                 qlcnic_sre_macaddr_change(adapter,
 493                                 cur->mac_addr, 0, QLCNIC_MAC_DEL);
 494                 list_del(&cur->list);
 495                 kfree(cur);
 496         }
 497 }
 498
 499 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter)
 500 {
 501         struct qlcnic_filter *tmp_fil;
 502         struct hlist_node *tmp_hnode, *n;
 503         struct hlist_head *head;
 504         int i;
 505
 506         for (i = 0; i < adapter->fhash.fmax; i++) {
 507                 head = &(adapter->fhash.fhead[i]);
 508
 509                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode)
 510                 {
 511                         if (jiffies >
 512                                 (QLCNIC_FILTER_AGE * HZ + tmp_fil->ftime)) {
 513                                 qlcnic_sre_macaddr_change(adapter,
 514                                         tmp_fil->faddr, tmp_fil->vlan_id,
 515                                         tmp_fil->vlan_id ? QLCNIC_MAC_VLAN_DEL :
 516                                         QLCNIC_MAC_DEL);
 517                                 spin_lock_bh(&adapter->mac_learn_lock);
 518                                 adapter->fhash.fnum--;
 519                                 hlist_del(&tmp_fil->fnode);
 520                                 spin_unlock_bh(&adapter->mac_learn_lock);
 521                                 kfree(tmp_fil);
 522                         }
 523                 }
 524         }
 525 }
 526
 527 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter)
 528 {
 529         struct qlcnic_filter *tmp_fil;
 530         struct hlist_node *tmp_hnode, *n;
 531         struct hlist_head *head;
 532         int i;
 533
 534         for (i = 0; i < adapter->fhash.fmax; i++) {
 535                 head = &(adapter->fhash.fhead[i]);
 536
 537                 hlist_for_each_entry_safe(tmp_fil, tmp_hnode, n, head, fnode) {
 538                         qlcnic_sre_macaddr_change(adapter, tmp_fil->faddr,
 539                                 tmp_fil->vlan_id, tmp_fil->vlan_id ?
 540                                 QLCNIC_MAC_VLAN_DEL :  QLCNIC_MAC_DEL);
 541                         spin_lock_bh(&adapter->mac_learn_lock);
 542                         adapter->fhash.fnum--;
 543                         hlist_del(&tmp_fil->fnode);
 544                         spin_unlock_bh(&adapter->mac_learn_lock);
 545                         kfree(tmp_fil);
 546                 }
 547         }
 548 }
 549
 550 #define QLCNIC_CONFIG_INTR_COALESCE     3
 551
 552 /*
 553  * Send the interrupt coalescing parameter set by ethtool to the card.
 554  */
 555 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter)
 556 {
 557         struct qlcnic_nic_req req;
 558         u64 word[6];
 559         int rv, i;
 560
 561         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 562
 563         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 564
 565         word[0] = QLCNIC_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
 566         req.req_hdr = cpu_to_le64(word[0]);
 567
 568         memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
 569         for (i = 0; i < 6; i++)
 570                 req.words[i] = cpu_to_le64(word[i]);
 571
 572         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 573         if (rv != 0)
 574                 dev_err(&adapter->netdev->dev,
 575                         "Could not send interrupt coalescing parameters\n");
 576
 577         return rv;
 578 }
 579
 580 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable)
 581 {
 582         struct qlcnic_nic_req req;
 583         u64 word;
 584         int rv;
 585
 586         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 587
 588         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 589
 590         word = QLCNIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
 591         req.req_hdr = cpu_to_le64(word);
 592
 593         req.words[0] = cpu_to_le64(enable);
 594
 595         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 596         if (rv != 0)
 597                 dev_err(&adapter->netdev->dev,
 598                         "Could not send configure hw lro request\n");
 599
 600         return rv;
 601 }
 602
 603 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable)
 604 {
 605         struct qlcnic_nic_req req;
 606         u64 word;
 607         int rv;
 608
 609         if (!!(adapter->flags & QLCNIC_BRIDGE_ENABLED) == enable)
 610                 return 0;
 611
 612         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 613
 614         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 615
 616         word = QLCNIC_H2C_OPCODE_CONFIG_BRIDGING |
 617                 ((u64)adapter->portnum << 16);
 618         req.req_hdr = cpu_to_le64(word);
 619
 620         req.words[0] = cpu_to_le64(enable);
 621
 622         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 623         if (rv != 0)
 624                 dev_err(&adapter->netdev->dev,
 625                         "Could not send configure bridge mode request\n");
 626
 627         adapter->flags ^= QLCNIC_BRIDGE_ENABLED;
 628
 629         return rv;
 630 }
 631
 632
 633 #define RSS_HASHTYPE_IP_TCP     0x3
 634
 635 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
 636 {
 637         struct qlcnic_nic_req req;
 638         u64 word;
 639         int i, rv;
 640
 641         const u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
 642                         0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
 643                         0x255b0ec26d5a56daULL };
 644
 645
 646         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 647         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 648
 649         word = QLCNIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
 650         req.req_hdr = cpu_to_le64(word);
 651
 652         /*
 653          * RSS request:
 654          * bits 3-0: hash_method
 655          *      5-4: hash_type_ipv4
 656          *      7-6: hash_type_ipv6
 657          *        8: enable
 658          *        9: use indirection table
 659          *    47-10: reserved
 660          *    63-48: indirection table mask
 661          */
 662         word =  ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
 663                 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
 664                 ((u64)(enable & 0x1) << 8) |
 665                 ((0x7ULL) << 48);
 666         req.words[0] = cpu_to_le64(word);
 667         for (i = 0; i < 5; i++)
 668                 req.words[i+1] = cpu_to_le64(key[i]);
 669
 670         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 671         if (rv != 0)
 672                 dev_err(&adapter->netdev->dev, "could not configure RSS\n");
 673
 674         return rv;
 675 }
 676
 677 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd)
 678 {
 679         struct qlcnic_nic_req req;
 680         struct qlcnic_ipaddr *ipa;
 681         u64 word;
 682         int rv;
 683
 684         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 685         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 686
 687         word = QLCNIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
 688         req.req_hdr = cpu_to_le64(word);
 689
 690         req.words[0] = cpu_to_le64(cmd);
 691         ipa = (struct qlcnic_ipaddr *)&req.words[1];
 692         ipa->ipv4 = ip;
 693
 694         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 695         if (rv != 0)
 696                 dev_err(&adapter->netdev->dev,
 697                                 "could not notify %s IP 0x%x reuqest\n",
 698                                 (cmd == QLCNIC_IP_UP) ? "Add" : "Remove", ip);
 699
 700         return rv;
 701 }
 702
 703 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable)
 704 {
 705         struct qlcnic_nic_req req;
 706         u64 word;
 707         int rv;
 708
 709         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 710         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 711
 712         word = QLCNIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
 713         req.req_hdr = cpu_to_le64(word);
 714         req.words[0] = cpu_to_le64(enable | (enable << 8));
 715
 716         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 717         if (rv != 0)
 718                 dev_err(&adapter->netdev->dev,
 719                                 "could not configure link notification\n");
 720
 721         return rv;
 722 }
 723
 724 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter)
 725 {
 726         struct qlcnic_nic_req req;
 727         u64 word;
 728         int rv;
 729
 730         memset(&req, 0, sizeof(struct qlcnic_nic_req));
 731         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
 732
 733         word = QLCNIC_H2C_OPCODE_LRO_REQUEST |
 734                 ((u64)adapter->portnum << 16) |
 735                 ((u64)QLCNIC_LRO_REQUEST_CLEANUP << 56) ;
 736
 737         req.req_hdr = cpu_to_le64(word);
 738
 739         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
 740         if (rv != 0)
 741                 dev_err(&adapter->netdev->dev,
 742                                  "could not cleanup lro flows\n");
 743
 744         return rv;
 745 }
 746
 747 /*
 748  * qlcnic_change_mtu - Change the Maximum Transfer Unit
 749  * @returns 0 on success, negative on failure
 750  */
 751
 752 int qlcnic_change_mtu(struct net_device *netdev, int mtu)
 753 {
 754         struct qlcnic_adapter *adapter = netdev_priv(netdev);
 755         int rc = 0;
 756
 757         if (mtu < P3_MIN_MTU || mtu > P3_MAX_MTU) {
 758                 dev_err(&adapter->netdev->dev, "%d bytes < mtu < %d bytes"
 759                         " not supported\n", P3_MAX_MTU, P3_MIN_MTU);
 760                 return -EINVAL;
 761         }
 762
 763         rc = qlcnic_fw_cmd_set_mtu(adapter, mtu);
 764
 765         if (!rc)
 766                 netdev->mtu = mtu;
 767
 768         return rc;
 769 }
 770
 771 /*
 772  * Changes the CRB window to the specified window.
 773  */
 774  /* Returns < 0 if off is not valid,
 775  *       1 if window access is needed. 'off' is set to offset from
 776  *         CRB space in 128M pci map
 777  *       0 if no window access is needed. 'off' is set to 2M addr
 778  * In: 'off' is offset from base in 128M pci map
 779  */
 780 static int
 781 qlcnic_pci_get_crb_addr_2M(struct qlcnic_adapter *adapter,
 782                 ulong off, void __iomem **addr)
 783 {
 784         const struct crb_128M_2M_sub_block_map *m;
 785
 786         if ((off >= QLCNIC_CRB_MAX) || (off < QLCNIC_PCI_CRBSPACE))
 787                 return -EINVAL;
 788
 789         off -= QLCNIC_PCI_CRBSPACE;
 790
 791         /*
 792          * Try direct map
 793          */
 794         m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
 795
 796         if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
 797                 *addr = adapter->ahw.pci_base0 + m->start_2M +
 798                         (off - m->start_128M);
 799                 return 0;
 800         }
 801
 802         /*
 803          * Not in direct map, use crb window
 804          */
 805         *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M + (off & MASK(16));
 806         return 1;
 807 }
 808
 809 /*
 810  * In: 'off' is offset from CRB space in 128M pci map
 811  * Out: 'off' is 2M pci map addr
 812  * side effect: lock crb window
 813  */
 814 static int
 815 qlcnic_pci_set_crbwindow_2M(struct qlcnic_adapter *adapter, ulong off)
 816 {
 817         u32 window;
 818         void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
 819
 820         off -= QLCNIC_PCI_CRBSPACE;
 821
 822         window = CRB_HI(off);
 823         if (window == 0) {
 824                 dev_err(&adapter->pdev->dev, "Invalid offset 0x%lx\n", off);
 825                 return -EIO;
 826         }
 827
 828         writel(window, addr);
 829         if (readl(addr) != window) {
 830                 if (printk_ratelimit())
 831                         dev_warn(&adapter->pdev->dev,
 832                                 "failed to set CRB window to %d off 0x%lx\n",
 833                                 window, off);
 834                 return -EIO;
 835         }
 836         return 0;
 837 }
 838
 839 int
 840 qlcnic_hw_write_wx_2M(struct qlcnic_adapter *adapter, ulong off, u32 data)
 841 {
 842         unsigned long flags;
 843         int rv;
 844         void __iomem *addr = NULL;
 845
 846         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 847
 848         if (rv == 0) {
 849                 writel(data, addr);
 850                 return 0;
 851         }
 852
 853         if (rv > 0) {
 854                 /* indirect access */
 855                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 856                 crb_win_lock(adapter);
 857                 rv = qlcnic_pci_set_crbwindow_2M(adapter, off);
 858                 if (!rv)
 859                         writel(data, addr);
 860                 crb_win_unlock(adapter);
 861                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 862                 return rv;
 863         }
 864
 865         dev_err(&adapter->pdev->dev,
 866                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 867         dump_stack();
 868         return -EIO;
 869 }
 870
 871 u32
 872 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off)
 873 {
 874         unsigned long flags;
 875         int rv;
 876         u32 data = -1;
 877         void __iomem *addr = NULL;
 878
 879         rv = qlcnic_pci_get_crb_addr_2M(adapter, off, &addr);
 880
 881         if (rv == 0)
 882                 return readl(addr);
 883
 884         if (rv > 0) {
 885                 /* indirect access */
 886                 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
 887                 crb_win_lock(adapter);
 888                 if (!qlcnic_pci_set_crbwindow_2M(adapter, off))
 889                         data = readl(addr);
 890                 crb_win_unlock(adapter);
 891                 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
 892                 return data;
 893         }
 894
 895         dev_err(&adapter->pdev->dev,
 896                         "%s: invalid offset: 0x%016lx\n", __func__, off);
 897         dump_stack();
 898         return -1;
 899 }
 900
 901
 902 void __iomem *
 903 qlcnic_get_ioaddr(struct qlcnic_adapter *adapter, u32 offset)
 904 {
 905         void __iomem *addr = NULL;
 906
 907         WARN_ON(qlcnic_pci_get_crb_addr_2M(adapter, offset, &addr));
 908
 909         return addr;
 910 }
 911
 912
 913 static int
 914 qlcnic_pci_set_window_2M(struct qlcnic_adapter *adapter,
 915                 u64 addr, u32 *start)
 916 {
 917         u32 window;
 918
 919         window = OCM_WIN_P3P(addr);
 920
 921         writel(window, adapter->ahw.ocm_win_crb);
 922         /* read back to flush */
 923         readl(adapter->ahw.ocm_win_crb);
 924
 925         *start = QLCNIC_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
 926         return 0;
 927 }
 928
 929 static int
 930 qlcnic_pci_mem_access_direct(struct qlcnic_adapter *adapter, u64 off,
 931                 u64 *data, int op)
 932 {
 933         void __iomem *addr;
 934         int ret;
 935         u32 start;
 936
 937         mutex_lock(&adapter->ahw.mem_lock);
 938
 939         ret = qlcnic_pci_set_window_2M(adapter, off, &start);
 940         if (ret != 0)
 941                 goto unlock;
 942
 943         addr = adapter->ahw.pci_base0 + start;
 944
 945         if (op == 0)    /* read */
 946                 *data = readq(addr);
 947         else            /* write */
 948                 writeq(*data, addr);
 949
 950 unlock:
 951         mutex_unlock(&adapter->ahw.mem_lock);
 952
 953         return ret;
 954 }
 955
 956 void
 957 qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *adapter, u64 off, u64 *data)
 958 {
 959         void __iomem *addr = adapter->ahw.pci_base0 +
 960                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 961
 962         mutex_lock(&adapter->ahw.mem_lock);
 963         *data = readq(addr);
 964         mutex_unlock(&adapter->ahw.mem_lock);
 965 }
 966
 967 void
 968 qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *adapter, u64 off, u64 data)
 969 {
 970         void __iomem *addr = adapter->ahw.pci_base0 +
 971                 QLCNIC_PCI_CAMQM_2M_BASE + (off - QLCNIC_PCI_CAMQM);
 972
 973         mutex_lock(&adapter->ahw.mem_lock);
 974         writeq(data, addr);
 975         mutex_unlock(&adapter->ahw.mem_lock);
 976 }
 977
 978 #define MAX_CTL_CHECK   1000
 979
 980 int
 981 qlcnic_pci_mem_write_2M(struct qlcnic_adapter *adapter,
 982                 u64 off, u64 data)
 983 {
 984         int i, j, ret;
 985         u32 temp, off8;
 986         void __iomem *mem_crb;
 987
 988         /* Only 64-bit aligned access */
 989         if (off & 7)
 990                 return -EIO;
 991
 992         /* P3 onward, test agent base for MIU and SIU is same */
 993         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
 994                                 QLCNIC_ADDR_QDR_NET_MAX)) {
 995                 mem_crb = qlcnic_get_ioaddr(adapter,
 996                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
 997                 goto correct;
 998         }
 999
1000         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1001                 mem_crb = qlcnic_get_ioaddr(adapter,
1002                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1003                 goto correct;
1004         }
1005
1006         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX))
1007                 return qlcnic_pci_mem_access_direct(adapter, off, &data, 1);
1008
1009         return -EIO;
1010
1011 correct:
1012         off8 = off & ~0xf;
1013
1014         mutex_lock(&adapter->ahw.mem_lock);
1015
1016         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1017         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1018
1019         i = 0;
1020         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1021         writel((TA_CTL_START | TA_CTL_ENABLE),
1022                         (mem_crb + TEST_AGT_CTRL));
1023
1024         for (j = 0; j < MAX_CTL_CHECK; j++) {
1025                 temp = readl(mem_crb + TEST_AGT_CTRL);
1026                 if ((temp & TA_CTL_BUSY) == 0)
1027                         break;
1028         }
1029
1030         if (j >= MAX_CTL_CHECK) {
1031                 ret = -EIO;
1032                 goto done;
1033         }
1034
1035         i = (off & 0xf) ? 0 : 2;
1036         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1037                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1038         writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1039                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1040         i = (off & 0xf) ? 2 : 0;
1041
1042         writel(data & 0xffffffff,
1043                         mem_crb + MIU_TEST_AGT_WRDATA(i));
1044         writel((data >> 32) & 0xffffffff,
1045                         mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1046
1047         writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1048         writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1049                         (mem_crb + TEST_AGT_CTRL));
1050
1051         for (j = 0; j < MAX_CTL_CHECK; j++) {
1052                 temp = readl(mem_crb + TEST_AGT_CTRL);
1053                 if ((temp & TA_CTL_BUSY) == 0)
1054                         break;
1055         }
1056
1057         if (j >= MAX_CTL_CHECK) {
1058                 if (printk_ratelimit())
1059                         dev_err(&adapter->pdev->dev,
1060                                         "failed to write through agent\n");
1061                 ret = -EIO;
1062         } else
1063                 ret = 0;
1064
1065 done:
1066         mutex_unlock(&adapter->ahw.mem_lock);
1067
1068         return ret;
1069 }
1070
1071 int
1072 qlcnic_pci_mem_read_2M(struct qlcnic_adapter *adapter,
1073                 u64 off, u64 *data)
1074 {
1075         int j, ret;
1076         u32 temp, off8;
1077         u64 val;
1078         void __iomem *mem_crb;
1079
1080         /* Only 64-bit aligned access */
1081         if (off & 7)
1082                 return -EIO;
1083
1084         /* P3 onward, test agent base for MIU and SIU is same */
1085         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_QDR_NET,
1086                                 QLCNIC_ADDR_QDR_NET_MAX)) {
1087                 mem_crb = qlcnic_get_ioaddr(adapter,
1088                                 QLCNIC_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1089                 goto correct;
1090         }
1091
1092         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_DDR_NET, QLCNIC_ADDR_DDR_NET_MAX)) {
1093                 mem_crb = qlcnic_get_ioaddr(adapter,
1094                                 QLCNIC_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1095                 goto correct;
1096         }
1097
1098         if (ADDR_IN_RANGE(off, QLCNIC_ADDR_OCM0, QLCNIC_ADDR_OCM0_MAX)) {
1099                 return qlcnic_pci_mem_access_direct(adapter,
1100                                 off, data, 0);
1101         }
1102
1103         return -EIO;
1104
1105 correct:
1106         off8 = off & ~0xf;
1107
1108         mutex_lock(&adapter->ahw.mem_lock);
1109
1110         writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1111         writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1112         writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1113         writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1114
1115         for (j = 0; j < MAX_CTL_CHECK; j++) {
1116                 temp = readl(mem_crb + TEST_AGT_CTRL);
1117                 if ((temp & TA_CTL_BUSY) == 0)
1118                         break;
1119         }
1120
1121         if (j >= MAX_CTL_CHECK) {
1122                 if (printk_ratelimit())
1123                         dev_err(&adapter->pdev->dev,
1124                                         "failed to read through agent\n");
1125                 ret = -EIO;
1126         } else {
1127                 off8 = MIU_TEST_AGT_RDDATA_LO;
1128                 if (off & 0xf)
1129                         off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1130
1131                 temp = readl(mem_crb + off8 + 4);
1132                 val = (u64)temp << 32;
1133                 val |= readl(mem_crb + off8);
1134                 *data = val;
1135                 ret = 0;
1136         }
1137
1138         mutex_unlock(&adapter->ahw.mem_lock);
1139
1140         return ret;
1141 }
1142
1143 int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
1144 {
1145         int offset, board_type, magic;
1146         struct pci_dev *pdev = adapter->pdev;
1147
1148         offset = QLCNIC_FW_MAGIC_OFFSET;
1149         if (qlcnic_rom_fast_read(adapter, offset, &magic))
1150                 return -EIO;
1151
1152         if (magic != QLCNIC_BDINFO_MAGIC) {
1153                 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1154                         magic);
1155                 return -EIO;
1156         }
1157
1158         offset = QLCNIC_BRDTYPE_OFFSET;
1159         if (qlcnic_rom_fast_read(adapter, offset, &board_type))
1160                 return -EIO;
1161
1162         adapter->ahw.board_type = board_type;
1163
1164         if (board_type == QLCNIC_BRDTYPE_P3_4_GB_MM) {
1165                 u32 gpio = QLCRD32(adapter, QLCNIC_ROMUSB_GLB_PAD_GPIO_I);
1166                 if ((gpio & 0x8000) == 0)
1167                         board_type = QLCNIC_BRDTYPE_P3_10G_TP;
1168         }
1169
1170         switch (board_type) {
1171         case QLCNIC_BRDTYPE_P3_HMEZ:
1172         case QLCNIC_BRDTYPE_P3_XG_LOM:
1173         case QLCNIC_BRDTYPE_P3_10G_CX4:
1174         case QLCNIC_BRDTYPE_P3_10G_CX4_LP:
1175         case QLCNIC_BRDTYPE_P3_IMEZ:
1176         case QLCNIC_BRDTYPE_P3_10G_SFP_PLUS:
1177         case QLCNIC_BRDTYPE_P3_10G_SFP_CT:
1178         case QLCNIC_BRDTYPE_P3_10G_SFP_QT:
1179         case QLCNIC_BRDTYPE_P3_10G_XFP:
1180         case QLCNIC_BRDTYPE_P3_10000_BASE_T:
1181                 adapter->ahw.port_type = QLCNIC_XGBE;
1182                 break;
1183         case QLCNIC_BRDTYPE_P3_REF_QG:
1184         case QLCNIC_BRDTYPE_P3_4_GB:
1185         case QLCNIC_BRDTYPE_P3_4_GB_MM:
1186                 adapter->ahw.port_type = QLCNIC_GBE;
1187                 break;
1188         case QLCNIC_BRDTYPE_P3_10G_TP:
1189                 adapter->ahw.port_type = (adapter->portnum < 2) ?
1190                         QLCNIC_XGBE : QLCNIC_GBE;
1191                 break;
1192         default:
1193                 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1194                 adapter->ahw.port_type = QLCNIC_XGBE;
1195                 break;
1196         }
1197
1198         return 0;
1199 }
1200
1201 int
1202 qlcnic_wol_supported(struct qlcnic_adapter *adapter)
1203 {
1204         u32 wol_cfg;
1205
1206         wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG_NV);
1207         if (wol_cfg & (1UL << adapter->portnum)) {
1208                 wol_cfg = QLCRD32(adapter, QLCNIC_WOL_CONFIG);
1209                 if (wol_cfg & (1 << adapter->portnum))
1210                         return 1;
1211         }
1212
1213         return 0;
1214 }
1215
1216 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate)
1217 {
1218         struct qlcnic_nic_req   req;
1219         int rv;
1220         u64 word;
1221
1222         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1223         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1224
1225         word = QLCNIC_H2C_OPCODE_CONFIG_LED | ((u64)adapter->portnum << 16);
1226         req.req_hdr = cpu_to_le64(word);
1227
1228         req.words[0] = cpu_to_le64((u64)rate << 32);
1229         req.words[1] = cpu_to_le64(state);
1230
1231         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1232         if (rv)
1233                 dev_err(&adapter->pdev->dev, "LED configuration failed.\n");
1234
1235         return rv;
1236 }
1237
1238 static int qlcnic_set_fw_loopback(struct qlcnic_adapter *adapter, u32 flag)
1239 {
1240         struct qlcnic_nic_req   req;
1241         int                     rv;
1242         u64                     word;
1243
1244         memset(&req, 0, sizeof(struct qlcnic_nic_req));
1245         req.qhdr = cpu_to_le64(QLCNIC_HOST_REQUEST << 23);
1246
1247         word = QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK |
1248                         ((u64)adapter->portnum << 16);
1249         req.req_hdr = cpu_to_le64(word);
1250         req.words[0] = cpu_to_le64(flag);
1251
1252         rv = qlcnic_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
1253         if (rv)
1254                 dev_err(&adapter->pdev->dev,
1255                         "%sting loopback mode failed.\n",
1256                                         flag ? "Set" : "Reset");
1257         return rv;
1258 }
1259
1260 int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter)
1261 {
1262         if (qlcnic_set_fw_loopback(adapter, 1))
1263                 return -EIO;
1264
1265         if (qlcnic_nic_set_promisc(adapter,
1266                                 VPORT_MISS_MODE_ACCEPT_ALL)) {
1267                 qlcnic_set_fw_loopback(adapter, 0);
1268                 return -EIO;
1269         }
1270
1271         msleep(1000);
1272         return 0;
1273 }
1274
1275 void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter)
1276 {
1277         int mode = VPORT_MISS_MODE_DROP;
1278         struct net_device *netdev = adapter->netdev;
1279
1280         qlcnic_set_fw_loopback(adapter, 0);
1281
1282         if (netdev->flags & IFF_PROMISC)
1283                 mode = VPORT_MISS_MODE_ACCEPT_ALL;
1284         else if (netdev->flags & IFF_ALLMULTI)
1285                 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
1286
1287         qlcnic_nic_set_promisc(adapter, mode);
1288         msleep(1000);
1289 }