1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #ifndef _IXGBE_TYPE_H_
29 #define _IXGBE_TYPE_H_
31 #include <linux/types.h>
32 #include <linux/mdio.h>
33 #include <linux/netdevice.h>
36 #define IXGBE_INTEL_VENDOR_ID 0x8086
39 #define IXGBE_DEV_ID_82598 0x10B6
40 #define IXGBE_DEV_ID_82598_BX 0x1508
41 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
42 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
43 #define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
44 #define IXGBE_DEV_ID_82598AT 0x10C8
45 #define IXGBE_DEV_ID_82598AT2 0x150B
46 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
47 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
48 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
49 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
50 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
51 #define IXGBE_DEV_ID_82599_KX4 0x10F7
52 #define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
53 #define IXGBE_DEV_ID_82599_KR 0x1517
54 #define IXGBE_DEV_ID_82599_T3_LOM 0x151C
55 #define IXGBE_DEV_ID_82599_CX4 0x10F9
56 #define IXGBE_DEV_ID_82599_SFP 0x10FB
57 #define IXGBE_DEV_ID_82599_SFP_EM 0x1507
58 #define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
59 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
60 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
61 #define IXGBE_DEV_ID_X540T 0x1528
63 /* General Registers */
64 #define IXGBE_CTRL 0x00000
65 #define IXGBE_STATUS 0x00008
66 #define IXGBE_CTRL_EXT 0x00018
67 #define IXGBE_ESDP 0x00020
68 #define IXGBE_EODSDP 0x00028
69 #define IXGBE_I2CCTL 0x00028
70 #define IXGBE_LEDCTL 0x00200
71 #define IXGBE_FRTIMER 0x00048
72 #define IXGBE_TCPTIMER 0x0004C
73 #define IXGBE_CORESPARE 0x00600
74 #define IXGBE_EXVET 0x05078
77 #define IXGBE_EEC 0x10010
78 #define IXGBE_EERD 0x10014
79 #define IXGBE_EEWR 0x10018
80 #define IXGBE_FLA 0x1001C
81 #define IXGBE_EEMNGCTL 0x10110
82 #define IXGBE_EEMNGDATA 0x10114
83 #define IXGBE_FLMNGCTL 0x10118
84 #define IXGBE_FLMNGDATA 0x1011C
85 #define IXGBE_FLMNGCNT 0x10120
86 #define IXGBE_FLOP 0x1013C
87 #define IXGBE_GRC 0x10200
89 /* General Receive Control */
90 #define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */
91 #define IXGBE_GRC_APME 0x00000002 /* Advanced Power Management Enable */
93 #define IXGBE_VPDDIAG0 0x10204
94 #define IXGBE_VPDDIAG1 0x10208
96 /* I2CCTL Bit Masks */
97 #define IXGBE_I2C_CLK_IN 0x00000001
98 #define IXGBE_I2C_CLK_OUT 0x00000002
99 #define IXGBE_I2C_DATA_IN 0x00000004
100 #define IXGBE_I2C_DATA_OUT 0x00000008
102 /* Interrupt Registers */
103 #define IXGBE_EICR 0x00800
104 #define IXGBE_EICS 0x00808
105 #define IXGBE_EIMS 0x00880
106 #define IXGBE_EIMC 0x00888
107 #define IXGBE_EIAC 0x00810
108 #define IXGBE_EIAM 0x00890
109 #define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
110 #define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
111 #define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
112 #define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
114 * 82598 EITR is 16 bits but set the limits based on the max
115 * supported by all ixgbe hardware. 82599 EITR is only 12 bits,
116 * with the lower 3 always zero.
118 #define IXGBE_MAX_INT_RATE 488281
119 #define IXGBE_MIN_INT_RATE 956
120 #define IXGBE_MAX_EITR 0x00000FF8
121 #define IXGBE_MIN_EITR 8
122 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
123 (0x012300 + (((_i) - 24) * 4)))
124 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
125 #define IXGBE_EITR_LLI_MOD 0x00008000
126 #define IXGBE_EITR_CNT_WDIS 0x80000000
127 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
128 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
129 #define IXGBE_EITRSEL 0x00894
130 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
131 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
132 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
133 #define IXGBE_GPIE 0x00898
135 /* Flow Control Registers */
136 #define IXGBE_FCADBUL 0x03210
137 #define IXGBE_FCADBUH 0x03214
138 #define IXGBE_FCAMACL 0x04328
139 #define IXGBE_FCAMACH 0x0432C
140 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
141 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
142 #define IXGBE_PFCTOP 0x03008
143 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
144 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
145 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
146 #define IXGBE_FCRTV 0x032A0
147 #define IXGBE_FCCFG 0x03D00
148 #define IXGBE_TFCS 0x0CE00
150 /* Receive DMA Registers */
151 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
152 (0x0D000 + ((_i - 64) * 0x40)))
153 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
154 (0x0D004 + ((_i - 64) * 0x40)))
155 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
156 (0x0D008 + ((_i - 64) * 0x40)))
157 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
158 (0x0D010 + ((_i - 64) * 0x40)))
159 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
160 (0x0D018 + ((_i - 64) * 0x40)))
161 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
162 (0x0D028 + ((_i - 64) * 0x40)))
163 #define IXGBE_RDDCC 0x02F20
164 #define IXGBE_RXMEMWRAP 0x03190
165 #define IXGBE_STARCTRL 0x03024
167 * Split and Replication Receive Control Registers
168 * 00-15 : 0x02100 + n*4
169 * 16-64 : 0x01014 + n*0x40
170 * 64-127: 0x0D014 + (n-64)*0x40
172 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
173 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
174 (0x0D014 + ((_i - 64) * 0x40))))
176 * Rx DCA Control Register:
177 * 00-15 : 0x02200 + n*4
178 * 16-64 : 0x0100C + n*0x40
179 * 64-127: 0x0D00C + (n-64)*0x40
181 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
182 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
183 (0x0D00C + ((_i - 64) * 0x40))))
184 #define IXGBE_RDRXCTL 0x02F00
185 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
186 /* 8 of these 0x03C00 - 0x03C1C */
187 #define IXGBE_RXCTRL 0x03000
188 #define IXGBE_DROPEN 0x03D04
189 #define IXGBE_RXPBSIZE_SHIFT 10
191 /* Receive Registers */
192 #define IXGBE_RXCSUM 0x05000
193 #define IXGBE_RFCTL 0x05008
194 #define IXGBE_DRECCCTL 0x02F08
195 #define IXGBE_DRECCCTL_DISABLE 0
196 /* Multicast Table Array - 128 entries */
197 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
198 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
199 (0x0A200 + ((_i) * 8)))
200 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
201 (0x0A204 + ((_i) * 8)))
202 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
203 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
204 /* Packet split receive type */
205 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
206 (0x0EA00 + ((_i) * 4)))
207 /* array of 4096 1-bit vlan filters */
208 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
209 /*array of 4096 4-bit vlan vmdq indices */
210 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
211 #define IXGBE_FCTRL 0x05080
212 #define IXGBE_VLNCTRL 0x05088
213 #define IXGBE_MCSTCTRL 0x05090
214 #define IXGBE_MRQC 0x05818
215 #define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
216 #define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
217 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
218 #define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
219 #define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */
220 #define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
221 #define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */
222 #define IXGBE_RQTC 0x0EC70
223 #define IXGBE_MTQC 0x08120
224 #define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */
225 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */
226 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */
227 #define IXGBE_VT_CTL 0x051B0
228 #define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
229 #define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
230 #define IXGBE_QDE 0x2F04
231 #define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */
232 #define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
233 #define IXGBE_VMRCTL(_i) (0x0F600 + ((_i) * 4))
234 #define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
235 #define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
236 #define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
237 #define IXGBE_LLITHRESH 0x0EC90
238 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
239 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
240 #define IXGBE_IMIRVP 0x05AC0
241 #define IXGBE_VMD_CTL 0x0581C
242 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
243 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
245 /* Flow Director registers */
246 #define IXGBE_FDIRCTRL 0x0EE00
247 #define IXGBE_FDIRHKEY 0x0EE68
248 #define IXGBE_FDIRSKEY 0x0EE6C
249 #define IXGBE_FDIRDIP4M 0x0EE3C
250 #define IXGBE_FDIRSIP4M 0x0EE40
251 #define IXGBE_FDIRTCPM 0x0EE44
252 #define IXGBE_FDIRUDPM 0x0EE48
253 #define IXGBE_FDIRIP6M 0x0EE74
254 #define IXGBE_FDIRM 0x0EE70
256 /* Flow Director Stats registers */
257 #define IXGBE_FDIRFREE 0x0EE38
258 #define IXGBE_FDIRLEN 0x0EE4C
259 #define IXGBE_FDIRUSTAT 0x0EE50
260 #define IXGBE_FDIRFSTAT 0x0EE54
261 #define IXGBE_FDIRMATCH 0x0EE58
262 #define IXGBE_FDIRMISS 0x0EE5C
264 /* Flow Director Programming registers */
265 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
266 #define IXGBE_FDIRIPSA 0x0EE18
267 #define IXGBE_FDIRIPDA 0x0EE1C
268 #define IXGBE_FDIRPORT 0x0EE20
269 #define IXGBE_FDIRVLAN 0x0EE24
270 #define IXGBE_FDIRHASH 0x0EE28
271 #define IXGBE_FDIRCMD 0x0EE2C
273 /* Transmit DMA registers */
274 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
275 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
276 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
277 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
278 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
279 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
280 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
281 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
282 #define IXGBE_DTXCTL 0x07E00
284 #define IXGBE_DMATXCTL 0x04A80
285 #define IXGBE_PFDTXGSWC 0x08220
286 #define IXGBE_DTXMXSZRQ 0x08100
287 #define IXGBE_DTXTCPFLGL 0x04A88
288 #define IXGBE_DTXTCPFLGH 0x04A8C
289 #define IXGBE_LBDRPEN 0x0CA00
290 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
292 #define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
293 #define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */
294 #define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */
295 #define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */
297 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
298 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
299 /* Tx DCA Control register : 128 of these (0-127) */
300 #define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
301 #define IXGBE_TIPG 0x0CB00
302 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
303 #define IXGBE_MNGTXMAP 0x0CD10
304 #define IXGBE_TIPG_FIBER_DEFAULT 3
305 #define IXGBE_TXPBSIZE_SHIFT 10
307 /* Wake up registers */
308 #define IXGBE_WUC 0x05800
309 #define IXGBE_WUFC 0x05808
310 #define IXGBE_WUS 0x05810
311 #define IXGBE_IPAV 0x05838
312 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
313 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
315 #define IXGBE_WUPL 0x05900
316 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
317 #define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
318 #define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100)) /* Ext Flexible Host
321 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
322 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
324 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
325 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
326 #define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */
327 #define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */
329 /* Definitions for power management and wakeup registers */
330 /* Wake Up Control */
331 #define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */
332 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
333 #define IXGBE_WUC_ADVD3WUC 0x00000010 /* D3Cold wake up cap. enable*/
335 /* Wake Up Filter Control */
336 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
337 #define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
338 #define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
339 #define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
340 #define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
341 #define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
342 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
343 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
344 #define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */
346 #define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */
347 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
348 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
349 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
350 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
351 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
352 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
353 #define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */
354 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
355 #define IXGBE_WUFC_ALL_FILTERS 0x003F00FF /* Mask for all 6 wakeup filters*/
356 #define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
359 #define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
360 #define IXGBE_WUS_MAG IXGBE_WUFC_MAG
361 #define IXGBE_WUS_EX IXGBE_WUFC_EX
362 #define IXGBE_WUS_MC IXGBE_WUFC_MC
363 #define IXGBE_WUS_BC IXGBE_WUFC_BC
364 #define IXGBE_WUS_ARP IXGBE_WUFC_ARP
365 #define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
366 #define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
367 #define IXGBE_WUS_MNG IXGBE_WUFC_MNG
368 #define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
369 #define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
370 #define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
371 #define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
372 #define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
373 #define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
374 #define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
376 /* Wake Up Packet Length */
377 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
380 #define IXGBE_RMCS 0x03D00
381 #define IXGBE_DPMCS 0x07F40
382 #define IXGBE_PDPMCS 0x0CD00
383 #define IXGBE_RUPPBMR 0x050A0
384 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
385 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
386 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
387 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
388 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
389 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
392 /* Security Control Registers */
393 #define IXGBE_SECTXCTRL 0x08800
394 #define IXGBE_SECTXSTAT 0x08804
395 #define IXGBE_SECTXBUFFAF 0x08808
396 #define IXGBE_SECTXMINIFG 0x08810
397 #define IXGBE_SECTXSTAT 0x08804
398 #define IXGBE_SECRXCTRL 0x08D00
399 #define IXGBE_SECRXSTAT 0x08D04
401 /* Security Bit Fields and Masks */
402 #define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
403 #define IXGBE_SECTXCTRL_TX_DIS 0x00000002
404 #define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
406 #define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
407 #define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
409 #define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
410 #define IXGBE_SECRXCTRL_RX_DIS 0x00000002
412 #define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
413 #define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
415 /* LinkSec (MacSec) Registers */
416 #define IXGBE_LSECTXCAP 0x08A00
417 #define IXGBE_LSECRXCAP 0x08F00
418 #define IXGBE_LSECTXCTRL 0x08A04
419 #define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */
420 #define IXGBE_LSECTXSCH 0x08A0C /* SCI High */
421 #define IXGBE_LSECTXSA 0x08A10
422 #define IXGBE_LSECTXPN0 0x08A14
423 #define IXGBE_LSECTXPN1 0x08A18
424 #define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
425 #define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
426 #define IXGBE_LSECRXCTRL 0x08F04
427 #define IXGBE_LSECRXSCL 0x08F08
428 #define IXGBE_LSECRXSCH 0x08F0C
429 #define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
430 #define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
431 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
432 #define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */
433 #define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */
434 #define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */
435 #define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */
436 #define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */
437 #define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */
438 #define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */
439 #define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */
440 #define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */
441 #define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */
442 #define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */
443 #define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */
444 #define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */
445 #define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */
446 #define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */
447 #define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
448 #define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
449 #define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */
450 #define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */
452 /* LinkSec (MacSec) Bit Fields and Masks */
453 #define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
454 #define IXGBE_LSECTXCAP_SUM_SHIFT 16
455 #define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
456 #define IXGBE_LSECRXCAP_SUM_SHIFT 16
458 #define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
459 #define IXGBE_LSECTXCTRL_DISABLE 0x0
460 #define IXGBE_LSECTXCTRL_AUTH 0x1
461 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
462 #define IXGBE_LSECTXCTRL_AISCI 0x00000020
463 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
464 #define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
466 #define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
467 #define IXGBE_LSECRXCTRL_EN_SHIFT 2
468 #define IXGBE_LSECRXCTRL_DISABLE 0x0
469 #define IXGBE_LSECRXCTRL_CHECK 0x1
470 #define IXGBE_LSECRXCTRL_STRICT 0x2
471 #define IXGBE_LSECRXCTRL_DROP 0x3
472 #define IXGBE_LSECRXCTRL_PLSH 0x00000040
473 #define IXGBE_LSECRXCTRL_RP 0x00000080
474 #define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
476 /* IpSec Registers */
477 #define IXGBE_IPSTXIDX 0x08900
478 #define IXGBE_IPSTXSALT 0x08904
479 #define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
480 #define IXGBE_IPSRXIDX 0x08E00
481 #define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
482 #define IXGBE_IPSRXSPI 0x08E14
483 #define IXGBE_IPSRXIPIDX 0x08E18
484 #define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
485 #define IXGBE_IPSRXSALT 0x08E2C
486 #define IXGBE_IPSRXMOD 0x08E30
488 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
490 /* HW RSC registers */
491 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
492 (0x0D02C + ((_i - 64) * 0x40)))
493 #define IXGBE_RSCDBU 0x03028
494 #define IXGBE_RSCCTL_RSCEN 0x01
495 #define IXGBE_RSCCTL_MAXDESC_1 0x00
496 #define IXGBE_RSCCTL_MAXDESC_4 0x04
497 #define IXGBE_RSCCTL_MAXDESC_8 0x08
498 #define IXGBE_RSCCTL_MAXDESC_16 0x0C
499 #define IXGBE_RXDADV_RSCCNT_SHIFT 17
500 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
501 #define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
502 #define IXGBE_RSCDBU_RSCACKDIS 0x00000080
503 #define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
506 #define IXGBE_RTRPCS 0x02430
507 #define IXGBE_RTTDCS 0x04900
508 #define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
509 #define IXGBE_RTTPCS 0x0CD00
510 #define IXGBE_RTRUP2TC 0x03020
511 #define IXGBE_RTTUP2TC 0x0C800
512 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
513 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
514 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
515 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
516 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
517 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
518 #define IXGBE_RTTDQSEL 0x04904
519 #define IXGBE_RTTDT1C 0x04908
520 #define IXGBE_RTTDT1S 0x0490C
521 #define IXGBE_RTTDTECC 0x04990
522 #define IXGBE_RTTDTECC_NO_BCN 0x00000100
523 #define IXGBE_RTTBCNRC 0x04984
526 #define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */
527 #define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */
528 #define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */
529 #define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */
530 #define IXGBE_FCINVST0 0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
531 #define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
532 #define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */
533 #define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */
534 #define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */
535 #define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */
536 #define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */
537 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
538 #define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
539 #define IXGBE_FCBUFF_OFFSET_SHIFT 16
540 #define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */
541 #define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */
542 #define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */
543 #define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */
544 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
547 #define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */
548 #define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */
549 #define IXGBE_REOFF 0x05158 /* Rx FC EOF */
550 #define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */
551 /* FCoE Filter Context Registers */
552 #define IXGBE_FCFLT 0x05108 /* FC FLT Context */
553 #define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */
554 #define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */
555 #define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */
556 #define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */
557 #define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */
558 #define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */
559 #define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */
560 #define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */
561 #define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */
562 /* FCoE Receive Control */
563 #define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */
564 #define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */
565 #define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */
566 #define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */
567 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */
568 #define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */
569 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */
570 #define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */
571 #define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */
572 #define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */
573 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
574 /* FCoE Redirection */
575 #define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */
576 #define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */
577 #define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
578 #define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */
579 #define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */
580 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
582 /* Stats registers */
583 #define IXGBE_CRCERRS 0x04000
584 #define IXGBE_ILLERRC 0x04004
585 #define IXGBE_ERRBC 0x04008
586 #define IXGBE_MSPDC 0x04010
587 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
588 #define IXGBE_MLFC 0x04034
589 #define IXGBE_MRFC 0x04038
590 #define IXGBE_RLEC 0x04040
591 #define IXGBE_LXONTXC 0x03F60
592 #define IXGBE_LXONRXC 0x0CF60
593 #define IXGBE_LXOFFTXC 0x03F68
594 #define IXGBE_LXOFFRXC 0x0CF68
595 #define IXGBE_LXONRXCNT 0x041A4
596 #define IXGBE_LXOFFRXCNT 0x041A8
597 #define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */
598 #define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */
599 #define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */
600 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
601 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
602 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
603 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
604 #define IXGBE_PRC64 0x0405C
605 #define IXGBE_PRC127 0x04060
606 #define IXGBE_PRC255 0x04064
607 #define IXGBE_PRC511 0x04068
608 #define IXGBE_PRC1023 0x0406C
609 #define IXGBE_PRC1522 0x04070
610 #define IXGBE_GPRC 0x04074
611 #define IXGBE_BPRC 0x04078
612 #define IXGBE_MPRC 0x0407C
613 #define IXGBE_GPTC 0x04080
614 #define IXGBE_GORCL 0x04088
615 #define IXGBE_GORCH 0x0408C
616 #define IXGBE_GOTCL 0x04090
617 #define IXGBE_GOTCH 0x04094
618 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
619 #define IXGBE_RUC 0x040A4
620 #define IXGBE_RFC 0x040A8
621 #define IXGBE_ROC 0x040AC
622 #define IXGBE_RJC 0x040B0
623 #define IXGBE_MNGPRC 0x040B4
624 #define IXGBE_MNGPDC 0x040B8
625 #define IXGBE_MNGPTC 0x0CF90
626 #define IXGBE_TORL 0x040C0
627 #define IXGBE_TORH 0x040C4
628 #define IXGBE_TPR 0x040D0
629 #define IXGBE_TPT 0x040D4
630 #define IXGBE_PTC64 0x040D8
631 #define IXGBE_PTC127 0x040DC
632 #define IXGBE_PTC255 0x040E0
633 #define IXGBE_PTC511 0x040E4
634 #define IXGBE_PTC1023 0x040E8
635 #define IXGBE_PTC1522 0x040EC
636 #define IXGBE_MPTC 0x040F0
637 #define IXGBE_BPTC 0x040F4
638 #define IXGBE_XEC 0x04120
639 #define IXGBE_SSVPC 0x08780
641 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
642 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
643 (0x08600 + ((_i) * 4)))
644 #define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
646 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
647 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
648 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
649 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
650 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
651 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
652 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
653 #define IXGBE_FCCRC 0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
654 #define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */
655 #define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */
656 #define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */
657 #define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */
658 #define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */
659 #define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */
662 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
663 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
664 #define IXGBE_MANC 0x05820
665 #define IXGBE_MFVAL 0x05824
666 #define IXGBE_MANC2H 0x05860
667 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
668 #define IXGBE_MIPAF 0x058B0
669 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
670 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
671 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
672 #define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
673 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
674 #define IXGBE_LSWFW 0x15014
676 /* ARC Subsystem registers */
677 #define IXGBE_HICR 0x15F00
678 #define IXGBE_FWSTS 0x15F0C
679 #define IXGBE_HSMC0R 0x15F04
680 #define IXGBE_HSMC1R 0x15F08
681 #define IXGBE_SWSR 0x15F10
682 #define IXGBE_HFDR 0x15FE8
683 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
685 /* PCI-E registers */
686 #define IXGBE_GCR 0x11000
687 #define IXGBE_GTV 0x11004
688 #define IXGBE_FUNCTAG 0x11008
689 #define IXGBE_GLT 0x1100C
690 #define IXGBE_GSCL_1 0x11010
691 #define IXGBE_GSCL_2 0x11014
692 #define IXGBE_GSCL_3 0x11018
693 #define IXGBE_GSCL_4 0x1101C
694 #define IXGBE_GSCN_0 0x11020
695 #define IXGBE_GSCN_1 0x11024
696 #define IXGBE_GSCN_2 0x11028
697 #define IXGBE_GSCN_3 0x1102C
698 #define IXGBE_FACTPS 0x10150
699 #define IXGBE_PCIEANACTL 0x11040
700 #define IXGBE_SWSM 0x10140
701 #define IXGBE_FWSM 0x10148
702 #define IXGBE_GSSR 0x10160
703 #define IXGBE_MREVID 0x11064
704 #define IXGBE_DCA_ID 0x11070
705 #define IXGBE_DCA_CTRL 0x11074
706 #define IXGBE_SWFW_SYNC IXGBE_GSSR
708 /* PCIe registers 82599-specific */
709 #define IXGBE_GCR_EXT 0x11050
710 #define IXGBE_GSCL_5_82599 0x11030
711 #define IXGBE_GSCL_6_82599 0x11034
712 #define IXGBE_GSCL_7_82599 0x11038
713 #define IXGBE_GSCL_8_82599 0x1103C
714 #define IXGBE_PHYADR_82599 0x11040
715 #define IXGBE_PHYDAT_82599 0x11044
716 #define IXGBE_PHYCTL_82599 0x11048
717 #define IXGBE_PBACLR_82599 0x11068
718 #define IXGBE_CIAA_82599 0x11088
719 #define IXGBE_CIAD_82599 0x1108C
720 #define IXGBE_PCIE_DIAG_0_82599 0x11090
721 #define IXGBE_PCIE_DIAG_1_82599 0x11094
722 #define IXGBE_PCIE_DIAG_2_82599 0x11098
723 #define IXGBE_PCIE_DIAG_3_82599 0x1109C
724 #define IXGBE_PCIE_DIAG_4_82599 0x110A0
725 #define IXGBE_PCIE_DIAG_5_82599 0x110A4
726 #define IXGBE_PCIE_DIAG_6_82599 0x110A8
727 #define IXGBE_PCIE_DIAG_7_82599 0x110C0
728 #define IXGBE_INTRPT_CSR_82599 0x110B0
729 #define IXGBE_INTRPT_MASK_82599 0x110B8
730 #define IXGBE_CDQ_MBR_82599 0x110B4
731 #define IXGBE_MISC_REG_82599 0x110F0
732 #define IXGBE_ECC_CTRL_0_82599 0x11100
733 #define IXGBE_ECC_CTRL_1_82599 0x11104
734 #define IXGBE_ECC_STATUS_82599 0x110E0
735 #define IXGBE_BAR_CTRL_82599 0x110F4
737 /* PCI Express Control */
738 #define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
739 #define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
740 #define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
741 #define IXGBE_GCR_CAP_VER2 0x00040000
743 #define IXGBE_GCR_EXT_MSIX_EN 0x80000000
744 #define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
745 #define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
746 #define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
747 #define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
748 IXGBE_GCR_EXT_VT_MODE_64)
750 /* Time Sync Registers */
751 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
752 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
753 #define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */
754 #define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */
755 #define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */
756 #define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */
757 #define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */
758 #define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */
759 #define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */
760 #define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */
761 #define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */
762 #define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */
763 #define IXGBE_RXUDP 0x08C1C /* Time Sync Rx UDP Port - RW */
765 /* Diagnostic Registers */
766 #define IXGBE_RDSTATCTL 0x02C20
767 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
768 #define IXGBE_RDHMPN 0x02F08
769 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
770 #define IXGBE_RDPROBE 0x02F20
771 #define IXGBE_RDMAM 0x02F30
772 #define IXGBE_RDMAD 0x02F34
773 #define IXGBE_TDSTATCTL 0x07C20
774 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
775 #define IXGBE_TDHMPN 0x07F08
776 #define IXGBE_TDHMPN2 0x082FC
777 #define IXGBE_TXDESCIC 0x082CC
778 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
779 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
780 #define IXGBE_TDPROBE 0x07F20
781 #define IXGBE_TXBUFCTRL 0x0C600
782 #define IXGBE_TXBUFDATA0 0x0C610
783 #define IXGBE_TXBUFDATA1 0x0C614
784 #define IXGBE_TXBUFDATA2 0x0C618
785 #define IXGBE_TXBUFDATA3 0x0C61C
786 #define IXGBE_RXBUFCTRL 0x03600
787 #define IXGBE_RXBUFDATA0 0x03610
788 #define IXGBE_RXBUFDATA1 0x03614
789 #define IXGBE_RXBUFDATA2 0x03618
790 #define IXGBE_RXBUFDATA3 0x0361C
791 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
792 #define IXGBE_RFVAL 0x050A4
793 #define IXGBE_MDFTC1 0x042B8
794 #define IXGBE_MDFTC2 0x042C0
795 #define IXGBE_MDFTFIFO1 0x042C4
796 #define IXGBE_MDFTFIFO2 0x042C8
797 #define IXGBE_MDFTS 0x042CC
798 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
799 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
800 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
801 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
802 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
803 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
804 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
805 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
806 #define IXGBE_PCIEECCCTL 0x1106C
807 #define IXGBE_PCIEECCCTL0 0x11100
808 #define IXGBE_PCIEECCCTL1 0x11104
809 #define IXGBE_PBTXECC 0x0C300
810 #define IXGBE_PBRXECC 0x03300
811 #define IXGBE_GHECCR 0x110B0
814 #define IXGBE_PCS1GCFIG 0x04200
815 #define IXGBE_PCS1GLCTL 0x04208
816 #define IXGBE_PCS1GLSTA 0x0420C
817 #define IXGBE_PCS1GDBG0 0x04210
818 #define IXGBE_PCS1GDBG1 0x04214
819 #define IXGBE_PCS1GANA 0x04218
820 #define IXGBE_PCS1GANLP 0x0421C
821 #define IXGBE_PCS1GANNP 0x04220
822 #define IXGBE_PCS1GANLPNP 0x04224
823 #define IXGBE_HLREG0 0x04240
824 #define IXGBE_HLREG1 0x04244
825 #define IXGBE_PAP 0x04248
826 #define IXGBE_MACA 0x0424C
827 #define IXGBE_APAE 0x04250
828 #define IXGBE_ARD 0x04254
829 #define IXGBE_AIS 0x04258
830 #define IXGBE_MSCA 0x0425C
831 #define IXGBE_MSRWD 0x04260
832 #define IXGBE_MLADD 0x04264
833 #define IXGBE_MHADD 0x04268
834 #define IXGBE_MAXFRS 0x04268
835 #define IXGBE_TREG 0x0426C
836 #define IXGBE_PCSS1 0x04288
837 #define IXGBE_PCSS2 0x0428C
838 #define IXGBE_XPCSS 0x04290
839 #define IXGBE_MFLCN 0x04294
840 #define IXGBE_SERDESC 0x04298
841 #define IXGBE_MACS 0x0429C
842 #define IXGBE_AUTOC 0x042A0
843 #define IXGBE_LINKS 0x042A4
844 #define IXGBE_LINKS2 0x04324
845 #define IXGBE_AUTOC2 0x042A8
846 #define IXGBE_AUTOC3 0x042AC
847 #define IXGBE_ANLP1 0x042B0
848 #define IXGBE_ANLP2 0x042B4
849 #define IXGBE_ATLASCTL 0x04800
850 #define IXGBE_MMNGC 0x042D0
851 #define IXGBE_ANLPNP1 0x042D4
852 #define IXGBE_ANLPNP2 0x042D8
853 #define IXGBE_KRPCSFC 0x042E0
854 #define IXGBE_KRPCSS 0x042E4
855 #define IXGBE_FECS1 0x042E8
856 #define IXGBE_FECS2 0x042EC
857 #define IXGBE_SMADARCTL 0x14F10
858 #define IXGBE_MPVC 0x04318
859 #define IXGBE_SGMIIC 0x04314
861 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
864 #define IXGBE_CORECTL 0x014F00
866 #define IXGBE_BARCTRL 0x110F4
867 #define IXGBE_BARCTRL_FLSIZE 0x0700
868 #define IXGBE_BARCTRL_CSRSIZE 0x2000
870 /* RDRXCTL Bit Masks */
871 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
872 #define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
873 #define IXGBE_RDRXCTL_MVMEN 0x00000020
874 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
875 #define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */
876 #define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC enabled */
877 #define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC enabled */
879 /* RQTC Bit Masks and Shifts */
880 #define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
881 #define IXGBE_RQTC_TC0_MASK (0x7 << 0)
882 #define IXGBE_RQTC_TC1_MASK (0x7 << 4)
883 #define IXGBE_RQTC_TC2_MASK (0x7 << 8)
884 #define IXGBE_RQTC_TC3_MASK (0x7 << 12)
885 #define IXGBE_RQTC_TC4_MASK (0x7 << 16)
886 #define IXGBE_RQTC_TC5_MASK (0x7 << 20)
887 #define IXGBE_RQTC_TC6_MASK (0x7 << 24)
888 #define IXGBE_RQTC_TC7_MASK (0x7 << 28)
890 /* PSRTYPE.RQPL Bit masks and shift */
891 #define IXGBE_PSRTYPE_RQPL_MASK 0x7
892 #define IXGBE_PSRTYPE_RQPL_SHIFT 29
895 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
896 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
897 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
900 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
902 /* MHADD Bit Masks */
903 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
904 #define IXGBE_MHADD_MFS_SHIFT 16
906 /* Extended Device Control */
907 #define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */
908 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
909 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
910 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
912 /* Direct Cache Access (DCA) definitions */
913 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
914 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
916 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
917 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
919 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
920 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */
921 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
922 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
923 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
924 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
925 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
926 #define IXGBE_DCA_RXCTRL_DESC_WRO_EN (1 << 13) /* DCA Rx wr Desc Relax Order */
927 #define IXGBE_DCA_RXCTRL_DESC_HSRO_EN (1 << 15) /* DCA Rx Split Header RO */
929 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
930 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */
931 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
932 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
933 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
934 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
937 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
938 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
939 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
940 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
941 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
942 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
943 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
944 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
945 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
946 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
947 #define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
948 #define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
949 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
950 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
951 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
952 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
953 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
954 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
956 /* MSRWD bit masks */
957 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
958 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
959 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
960 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
962 /* Atlas registers */
963 #define IXGBE_ATLAS_PDN_LPBK 0x24
964 #define IXGBE_ATLAS_PDN_10G 0xB
965 #define IXGBE_ATLAS_PDN_1G 0xC
966 #define IXGBE_ATLAS_PDN_AN 0xD
968 /* Atlas bit masks */
969 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
970 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
971 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
972 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
973 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
976 #define IXGBE_CORECTL_WRITE_CMD 0x00010000
978 /* MDIO definitions */
980 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
982 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
983 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
984 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
985 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
986 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
987 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
989 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */
990 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
991 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
993 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
994 #define IXGBE_MAX_PHY_ADDR 32
997 #define TN1010_PHY_ID 0x00A19410
998 #define TNX_FW_REV 0xB
999 #define AQ1202_PHY_ID 0x03A1B440
1000 #define QT2022_PHY_ID 0x0043A400
1001 #define ATH_PHY_ID 0x03429050
1002 #define AQ_FW_REV 0x20
1005 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1007 /* Special PHY Init Routine */
1008 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1009 #define IXGBE_PHY_INIT_END_NL 0xFFFF
1010 #define IXGBE_CONTROL_MASK_NL 0xF000
1011 #define IXGBE_DATA_MASK_NL 0x0FFF
1012 #define IXGBE_CONTROL_SHIFT_NL 12
1013 #define IXGBE_DELAY_NL 0
1014 #define IXGBE_DATA_NL 1
1015 #define IXGBE_CONTROL_NL 0x000F
1016 #define IXGBE_CONTROL_EOL_NL 0x0FFF
1017 #define IXGBE_CONTROL_SOL_NL 0x0000
1019 /* General purpose Interrupt Enable */
1020 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
1021 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
1022 #define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */
1023 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
1024 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
1025 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
1026 #define IXGBE_GPIE_EIAME 0x40000000
1027 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1028 #define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */
1029 #define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */
1030 #define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */
1031 #define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */
1033 /* Transmit Flow Control status */
1034 #define IXGBE_TFCS_TXOFF 0x00000001
1035 #define IXGBE_TFCS_TXOFF0 0x00000100
1036 #define IXGBE_TFCS_TXOFF1 0x00000200
1037 #define IXGBE_TFCS_TXOFF2 0x00000400
1038 #define IXGBE_TFCS_TXOFF3 0x00000800
1039 #define IXGBE_TFCS_TXOFF4 0x00001000
1040 #define IXGBE_TFCS_TXOFF5 0x00002000
1041 #define IXGBE_TFCS_TXOFF6 0x00004000
1042 #define IXGBE_TFCS_TXOFF7 0x00008000
1045 #define IXGBE_TCPTIMER_KS 0x00000100
1046 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1047 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1048 #define IXGBE_TCPTIMER_LOOP 0x00000800
1049 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1051 /* HLREG0 Bit Masks */
1052 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
1053 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
1054 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
1055 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
1056 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
1057 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
1058 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
1059 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
1060 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
1061 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
1062 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
1063 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
1064 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
1065 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
1066 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
1068 /* VMD_CTL bitmasks */
1069 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1070 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1072 /* VT_CTL bitmasks */
1073 #define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */
1074 #define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */
1075 #define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */
1076 #define IXGBE_VT_CTL_POOL_SHIFT 7
1077 #define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1079 /* VMOLR bitmasks */
1080 #define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */
1081 #define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */
1082 #define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */
1083 #define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */
1084 #define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */
1087 #define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1089 #define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
1091 /* RDHMPN and TDHMPN bitmasks */
1092 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
1093 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1094 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1095 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
1096 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1097 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1099 #define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1100 #define IXGBE_RDMAM_DWORD_SHIFT 9
1101 #define IXGBE_RDMAM_DESC_COMP_FIFO 1
1102 #define IXGBE_RDMAM_DFC_CMD_FIFO 2
1103 #define IXGBE_RDMAM_TCN_STATUS_RAM 4
1104 #define IXGBE_RDMAM_WB_COLL_FIFO 5
1105 #define IXGBE_RDMAM_QSC_CNT_RAM 6
1106 #define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1107 #define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1108 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1109 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1110 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1111 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1112 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1113 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1114 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1115 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1116 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1117 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1118 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1119 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1120 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1121 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1123 #define IXGBE_TXDESCIC_READY 0x80000000
1125 /* Receive Checksum Control */
1126 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
1127 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
1129 /* FCRTL Bit Masks */
1130 #define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */
1131 #define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */
1134 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
1136 /* RMCS Bit Masks */
1137 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
1138 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
1139 #define IXGBE_RMCS_RAC 0x00000004
1140 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
1141 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */
1142 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */
1143 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
1145 /* FCCFG Bit Masks */
1146 #define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */
1147 #define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */
1149 /* Interrupt register bitmasks */
1151 /* Extended Interrupt Cause Read */
1152 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
1153 #define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */
1154 #define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */
1155 #define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */
1156 #define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */
1157 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
1158 #define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */
1159 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
1160 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
1161 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
1162 #define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */
1163 #define IXGBE_EICR_ECC 0x10000000 /* ECC Error */
1164 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
1165 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
1166 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
1167 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
1169 /* Extended Interrupt Cause Set */
1170 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1171 #define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1172 #define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */
1173 #define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */
1174 #define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1175 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
1176 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1177 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1178 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1179 #define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1180 #define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */
1181 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1182 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
1183 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1184 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1186 /* Extended Interrupt Mask Set */
1187 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1188 #define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1189 #define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1190 #define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */
1191 #define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1192 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
1193 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1194 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1195 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1196 #define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1197 #define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */
1198 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1199 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
1200 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1201 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1203 /* Extended Interrupt Mask Clear */
1204 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
1205 #define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */
1206 #define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */
1207 #define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */
1208 #define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */
1209 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
1210 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
1211 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
1212 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
1213 #define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */
1214 #define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */
1215 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
1216 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
1217 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
1218 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
1220 #define IXGBE_EIMS_ENABLE_MASK ( \
1221 IXGBE_EIMS_RTX_QUEUE | \
1223 IXGBE_EIMS_TCP_TIMER | \
1226 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
1227 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
1228 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
1229 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
1230 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
1231 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
1232 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
1233 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
1234 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
1235 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
1236 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
1237 #define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */
1238 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
1239 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
1240 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
1241 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
1242 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
1243 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
1244 #define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass check of control bits */
1245 #define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */
1246 #define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */
1247 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
1248 #define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */
1249 #define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */
1251 #define IXGBE_MAX_FTQF_FILTERS 128
1252 #define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1253 #define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1254 #define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1255 #define IXGBE_FTQF_PROTOCOL_SCTP 2
1256 #define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1257 #define IXGBE_FTQF_PRIORITY_SHIFT 2
1258 #define IXGBE_FTQF_POOL_MASK 0x0000003F
1259 #define IXGBE_FTQF_POOL_SHIFT 8
1260 #define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1261 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1262 #define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1263 #define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1265 /* Interrupt clear mask */
1266 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1268 /* Interrupt Vector Allocation Registers */
1269 #define IXGBE_IVAR_REG_NUM 25
1270 #define IXGBE_IVAR_REG_NUM_82599 64
1271 #define IXGBE_IVAR_TXRX_ENTRY 96
1272 #define IXGBE_IVAR_RX_ENTRY 64
1273 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1274 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1275 #define IXGBE_IVAR_TX_ENTRY 32
1277 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
1278 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
1280 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1282 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
1284 /* ETYPE Queue Filter/Select Bit Masks */
1285 #define IXGBE_MAX_ETQF_FILTERS 8
1286 #define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */
1287 #define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */
1288 #define IXGBE_ETQF_1588 0x40000000 /* bit 30 */
1289 #define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */
1290 #define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */
1292 #define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */
1293 #define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1294 #define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */
1295 #define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */
1298 * ETQF filter list: one static filter per filter consumer. This is
1299 * to avoid filter collisions later. Add new filters
1303 * EAPOL 802.1x (0x888e): Filter 0
1304 * BCN (0x8904): Filter 1
1305 * 1588 (0x88f7): Filter 3
1307 #define IXGBE_ETQF_FILTER_EAPOL 0
1308 #define IXGBE_ETQF_FILTER_BCN 1
1309 #define IXGBE_ETQF_FILTER_FCOE 2
1310 #define IXGBE_ETQF_FILTER_1588 3
1311 #define IXGBE_ETQF_FILTER_FIP 4
1312 /* VLAN Control Bit Masks */
1313 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
1314 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
1315 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
1316 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
1317 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
1319 /* VLAN pool filtering masks */
1320 #define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */
1321 #define IXGBE_VLVF_ENTRIES 64
1322 #define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1324 /* Per VF Port VLAN insertion rules */
1325 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
1326 #define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
1328 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
1330 /* STATUS Bit Masks */
1331 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
1332 #define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/
1333 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
1335 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
1336 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
1338 /* ESDP Bit Masks */
1339 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
1340 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
1341 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
1342 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
1343 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
1344 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
1345 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
1346 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
1347 #define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */
1349 /* LEDCTL Bit Masks */
1350 #define IXGBE_LED_IVRT_BASE 0x00000040
1351 #define IXGBE_LED_BLINK_BASE 0x00000080
1352 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1353 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1354 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
1355 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1356 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1357 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1360 #define IXGBE_LED_LINK_UP 0x0
1361 #define IXGBE_LED_LINK_10G 0x1
1362 #define IXGBE_LED_MAC 0x2
1363 #define IXGBE_LED_FILTER 0x3
1364 #define IXGBE_LED_LINK_ACTIVE 0x4
1365 #define IXGBE_LED_LINK_1G 0x5
1366 #define IXGBE_LED_ON 0xE
1367 #define IXGBE_LED_OFF 0xF
1369 /* AUTOC Bit Masks */
1370 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1371 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
1372 #define IXGBE_AUTOC_KX_SUPP 0x40000000
1373 #define IXGBE_AUTOC_PAUSE 0x30000000
1374 #define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1375 #define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1376 #define IXGBE_AUTOC_RF 0x08000000
1377 #define IXGBE_AUTOC_PD_TMR 0x06000000
1378 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1379 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1380 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1381 #define IXGBE_AUTOC_FECA 0x00040000
1382 #define IXGBE_AUTOC_FECR 0x00020000
1383 #define IXGBE_AUTOC_KR_SUPP 0x00010000
1384 #define IXGBE_AUTOC_AN_RESTART 0x00001000
1385 #define IXGBE_AUTOC_FLU 0x00000001
1386 #define IXGBE_AUTOC_LMS_SHIFT 13
1387 #define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1388 #define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1389 #define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1390 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1391 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1392 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1393 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1394 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1395 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1396 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1397 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1398 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1400 #define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1401 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1402 #define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1403 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1404 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1405 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1406 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1407 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1408 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1409 #define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1410 #define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1412 #define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1413 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1414 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1415 #define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1416 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1417 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1419 /* LINKS Bit Masks */
1420 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
1421 #define IXGBE_LINKS_UP 0x40000000
1422 #define IXGBE_LINKS_SPEED 0x20000000
1423 #define IXGBE_LINKS_MODE 0x18000000
1424 #define IXGBE_LINKS_RX_MODE 0x06000000
1425 #define IXGBE_LINKS_TX_MODE 0x01800000
1426 #define IXGBE_LINKS_XGXS_EN 0x00400000
1427 #define IXGBE_LINKS_SGMII_EN 0x02000000
1428 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
1429 #define IXGBE_LINKS_1G_AN_EN 0x00100000
1430 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1431 #define IXGBE_LINKS_1G_SYNC 0x00040000
1432 #define IXGBE_LINKS_10G_ALIGN 0x00020000
1433 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1434 #define IXGBE_LINKS_TL_FAULT 0x00001000
1435 #define IXGBE_LINKS_SIGNAL 0x00000F00
1437 #define IXGBE_LINKS_SPEED_82599 0x30000000
1438 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1439 #define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1440 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
1441 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
1442 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
1444 #define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1446 /* PCS1GLSTA Bit Masks */
1447 #define IXGBE_PCS1GLSTA_LINK_OK 1
1448 #define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1449 #define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1450 #define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1451 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1452 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1453 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1455 #define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1456 #define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1458 /* PCS1GLCTL Bit Masks */
1459 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */
1460 #define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1461 #define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1462 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1463 #define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1464 #define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1466 /* ANLP1 Bit Masks */
1467 #define IXGBE_ANLP1_PAUSE 0x0C00
1468 #define IXGBE_ANLP1_SYM_PAUSE 0x0400
1469 #define IXGBE_ANLP1_ASM_PAUSE 0x0800
1471 /* SW Semaphore Register bitmasks */
1472 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
1473 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
1474 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
1475 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
1477 /* SW_FW_SYNC/GSSR definitions */
1478 #define IXGBE_GSSR_EEP_SM 0x0001
1479 #define IXGBE_GSSR_PHY0_SM 0x0002
1480 #define IXGBE_GSSR_PHY1_SM 0x0004
1481 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
1482 #define IXGBE_GSSR_FLASH_SM 0x0010
1485 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
1486 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
1487 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
1488 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
1489 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
1490 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
1491 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
1492 #define IXGBE_EEC_FWE_SHIFT 4
1493 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
1494 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
1495 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
1496 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
1497 #define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */
1498 #define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */
1499 #define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */
1500 /* EEPROM Addressing bits based on type (0-small, 1-large) */
1501 #define IXGBE_EEC_ADDR_SIZE 0x00000400
1502 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
1504 #define IXGBE_EEC_SIZE_SHIFT 11
1505 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1506 #define IXGBE_EEPROM_OPCODE_BITS 8
1508 /* Checksum and EEPROM pointers */
1509 #define IXGBE_EEPROM_CHECKSUM 0x3F
1510 #define IXGBE_EEPROM_SUM 0xBABA
1511 #define IXGBE_PCIE_ANALOG_PTR 0x03
1512 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
1513 #define IXGBE_PHY_PTR 0x04
1514 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
1515 #define IXGBE_OPTION_ROM_PTR 0x05
1516 #define IXGBE_PCIE_GENERAL_PTR 0x06
1517 #define IXGBE_PCIE_CONFIG0_PTR 0x07
1518 #define IXGBE_PCIE_CONFIG1_PTR 0x08
1519 #define IXGBE_CORE0_PTR 0x09
1520 #define IXGBE_CORE1_PTR 0x0A
1521 #define IXGBE_MAC0_PTR 0x0B
1522 #define IXGBE_MAC1_PTR 0x0C
1523 #define IXGBE_CSR0_CONFIG_PTR 0x0D
1524 #define IXGBE_CSR1_CONFIG_PTR 0x0E
1525 #define IXGBE_FW_PTR 0x0F
1526 #define IXGBE_PBANUM0_PTR 0x15
1527 #define IXGBE_PBANUM1_PTR 0x16
1528 #define IXGBE_DEVICE_CAPS 0x2C
1529 #define IXGBE_SAN_MAC_ADDR_PTR 0x28
1530 #define IXGBE_PCIE_MSIX_82599_CAPS 0x72
1531 #define IXGBE_PCIE_MSIX_82598_CAPS 0x62
1533 /* MSI-X capability fields masks */
1534 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
1536 /* Legacy EEPROM word offsets */
1537 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
1538 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
1539 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
1541 /* EEPROM Commands - SPI */
1542 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
1543 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
1544 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
1545 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
1546 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
1547 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
1548 /* EEPROM reset Write Enable latch */
1549 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
1550 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
1551 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
1552 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
1553 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
1554 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
1556 /* EEPROM Read Register */
1557 #define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */
1558 #define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */
1559 #define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */
1560 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */
1561 #define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for write complete */
1562 #define IXGBE_NVM_POLL_READ 0 /* Flag for polling for read complete */
1564 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
1566 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
1567 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
1570 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
1571 /* Number of 5 microseconds we wait for EERD read and
1572 * EERW write to complete */
1573 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
1576 #ifndef IXGBE_FLUDONE_ATTEMPTS
1577 /* # attempts we wait for flush update to complete */
1578 #define IXGBE_FLUDONE_ATTEMPTS 20000
1581 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
1582 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
1583 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
1584 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
1585 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
1586 #define IXGBE_FW_PATCH_VERSION_4 0x7
1588 /* Alternative SAN MAC Address Block */
1589 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */
1590 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt. SAN MAC capability */
1591 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
1592 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
1593 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt. WWNN prefix offset */
1594 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt. WWPN prefix offset */
1595 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt. SAN MAC exists */
1596 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt. WWN base exists */
1599 #define IXGBE_PCI_LINK_STATUS 0xB2
1600 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
1601 #define IXGBE_PCI_LINK_WIDTH 0x3F0
1602 #define IXGBE_PCI_LINK_WIDTH_1 0x10
1603 #define IXGBE_PCI_LINK_WIDTH_2 0x20
1604 #define IXGBE_PCI_LINK_WIDTH_4 0x40
1605 #define IXGBE_PCI_LINK_WIDTH_8 0x80
1606 #define IXGBE_PCI_LINK_SPEED 0xF
1607 #define IXGBE_PCI_LINK_SPEED_2500 0x1
1608 #define IXGBE_PCI_LINK_SPEED_5000 0x2
1609 #define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
1610 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
1611 #define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
1613 /* Number of 100 microseconds we wait for PCI Express master disable */
1614 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
1616 /* Check whether address is multicast. This is little-endian specific check.*/
1617 #define IXGBE_IS_MULTICAST(Address) \
1618 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
1620 /* Check whether an address is broadcast. */
1621 #define IXGBE_IS_BROADCAST(Address) \
1622 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
1623 (((u8 *)(Address))[1] == ((u8)0xff)))
1626 #define IXGBE_RAH_VIND_MASK 0x003C0000
1627 #define IXGBE_RAH_VIND_SHIFT 18
1628 #define IXGBE_RAH_AV 0x80000000
1629 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
1631 /* Header split receive */
1632 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
1633 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
1634 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
1635 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
1636 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
1637 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
1638 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
1639 #define IXGBE_RFCTL_NFS_VER_2 0
1640 #define IXGBE_RFCTL_NFS_VER_3 1
1641 #define IXGBE_RFCTL_NFS_VER_4 2
1642 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
1643 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
1644 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
1645 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
1646 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
1648 /* Transmit Config masks */
1649 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
1650 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
1651 /* Enable short packet padding to 64 bytes */
1652 #define IXGBE_TX_PAD_ENABLE 0x00000400
1653 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
1654 /* This allows for 16K packets + 4k for vlan */
1655 #define IXGBE_MAX_FRAME_SZ 0x40040000
1657 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
1658 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
1660 /* Receive Config masks */
1661 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
1662 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
1663 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
1664 #define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */
1666 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
1667 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
1668 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
1669 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
1670 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
1671 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
1672 /* Receive Priority Flow Control Enable */
1673 #define IXGBE_FCTRL_RPFCE 0x00004000
1674 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
1675 #define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */
1676 #define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */
1677 #define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */
1678 #define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */
1680 /* Multiple Receive Queue Control */
1681 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
1682 #define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */
1683 #define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */
1684 #define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */
1685 #define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */
1686 #define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */
1687 #define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */
1688 #define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */
1689 #define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */
1690 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
1691 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
1692 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
1693 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
1694 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
1695 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
1696 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
1697 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
1698 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
1699 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
1700 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
1701 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
1702 #define IXGBE_MRQC_L3L4TXSWEN 0x00008000
1704 /* Queue Drop Enable */
1705 #define IXGBE_QDE_ENABLE 0x00000001
1706 #define IXGBE_QDE_IDX_MASK 0x00007F00
1707 #define IXGBE_QDE_IDX_SHIFT 8
1709 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
1710 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
1711 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
1712 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
1713 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
1714 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
1715 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
1716 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
1717 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
1719 #define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
1720 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
1721 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
1722 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
1723 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
1724 /* Multiple Transmit Queue Command Register */
1725 #define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */
1726 #define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */
1727 #define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */
1728 #define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */
1729 #define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */
1730 #define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
1732 /* Receive Descriptor bit definitions */
1733 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
1734 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
1735 #define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */
1736 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
1737 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
1738 #define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
1739 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
1740 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
1741 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
1742 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
1743 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
1744 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
1745 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
1746 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
1747 #define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */
1748 #define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */
1749 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
1750 #define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */
1751 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
1752 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
1753 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
1754 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
1755 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
1756 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
1757 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
1758 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
1759 #define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */
1760 #define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */
1761 #define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCoEFe/IPE */
1762 #define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */
1763 #define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */
1764 #define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */
1765 #define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */
1766 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
1767 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
1768 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
1769 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
1770 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
1771 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
1772 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
1773 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
1774 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
1775 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
1776 #define IXGBE_RXD_PRI_SHIFT 13
1777 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
1778 #define IXGBE_RXD_CFI_SHIFT 12
1780 #define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
1781 #define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
1782 #define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */
1783 #define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */
1784 #define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */
1785 #define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */
1786 #define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */
1787 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
1788 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */
1789 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
1790 #define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */
1792 /* PSRTYPE bit definitions */
1793 #define IXGBE_PSRTYPE_TCPHDR 0x00000010
1794 #define IXGBE_PSRTYPE_UDPHDR 0x00000020
1795 #define IXGBE_PSRTYPE_IPV4HDR 0x00000100
1796 #define IXGBE_PSRTYPE_IPV6HDR 0x00000200
1797 #define IXGBE_PSRTYPE_L2HDR 0x00001000
1799 /* SRRCTL bit definitions */
1800 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
1801 #define IXGBE_SRRCTL_RDMTS_SHIFT 22
1802 #define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
1803 #define IXGBE_SRRCTL_DROP_EN 0x10000000
1804 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
1805 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
1806 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
1807 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
1808 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
1809 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
1810 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
1811 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
1813 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
1814 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
1816 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
1817 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
1818 #define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
1819 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
1820 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
1821 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
1822 #define IXGBE_RXDADV_SPH 0x8000
1824 /* RSS Hash results */
1825 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
1826 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
1827 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
1828 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
1829 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
1830 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
1831 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1832 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1833 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1834 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1836 /* RSS Packet Types as indicated in the receive descriptor. */
1837 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1838 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1839 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1840 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1841 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1842 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1843 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1844 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1845 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1846 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */
1847 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */
1848 #define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */
1849 #define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */
1850 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */
1851 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */
1853 /* Security Processing bit Indication */
1854 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
1855 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
1856 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
1857 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
1858 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
1860 /* Masks to determine if packets should be dropped due to frame errors */
1861 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1862 IXGBE_RXD_ERR_CE | \
1863 IXGBE_RXD_ERR_LE | \
1864 IXGBE_RXD_ERR_PE | \
1865 IXGBE_RXD_ERR_OSE | \
1868 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1869 IXGBE_RXDADV_ERR_CE | \
1870 IXGBE_RXDADV_ERR_LE | \
1871 IXGBE_RXDADV_ERR_PE | \
1872 IXGBE_RXDADV_ERR_OSE | \
1873 IXGBE_RXDADV_ERR_USE)
1875 /* Multicast bit mask */
1876 #define IXGBE_MCSTCTRL_MFE 0x4
1878 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1879 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1880 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1881 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1883 /* Vlan-specific macros */
1884 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1885 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1886 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1887 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1889 /* SR-IOV specific macros */
1890 #define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
1891 #define IXGBE_MBVFICR(_i) (0x00710 + (_i * 4))
1892 #define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600))
1893 #define IXGBE_VFLREC(_i) (0x00700 + (_i * 4))
1895 /* Little Endian defines */
1904 enum ixgbe_fdir_pballoc_type {
1905 IXGBE_FDIR_PBALLOC_64K = 0,
1906 IXGBE_FDIR_PBALLOC_128K,
1907 IXGBE_FDIR_PBALLOC_256K,
1909 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
1911 /* Flow Director register values */
1912 #define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
1913 #define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
1914 #define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
1915 #define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
1916 #define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
1917 #define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
1918 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
1919 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
1920 #define IXGBE_FDIRCTRL_FLEX_SHIFT 16
1921 #define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
1922 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
1923 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
1924 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
1926 #define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
1927 #define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
1928 #define IXGBE_FDIRIP6M_DIPM_SHIFT 16
1929 #define IXGBE_FDIRM_VLANID 0x00000001
1930 #define IXGBE_FDIRM_VLANP 0x00000002
1931 #define IXGBE_FDIRM_POOL 0x00000004
1932 #define IXGBE_FDIRM_L3P 0x00000008
1933 #define IXGBE_FDIRM_L4P 0x00000010
1934 #define IXGBE_FDIRM_FLEX 0x00000020
1935 #define IXGBE_FDIRM_DIPv6 0x00000040
1937 #define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
1938 #define IXGBE_FDIRFREE_FREE_SHIFT 0
1939 #define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
1940 #define IXGBE_FDIRFREE_COLL_SHIFT 16
1941 #define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
1942 #define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
1943 #define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
1944 #define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
1945 #define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
1946 #define IXGBE_FDIRUSTAT_ADD_SHIFT 0
1947 #define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
1948 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
1949 #define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
1950 #define IXGBE_FDIRFSTAT_FADD_SHIFT 0
1951 #define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
1952 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
1953 #define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
1954 #define IXGBE_FDIRVLAN_FLEX_SHIFT 16
1955 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
1956 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
1958 #define IXGBE_FDIRCMD_CMD_MASK 0x00000003
1959 #define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
1960 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
1961 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
1962 #define IXGBE_FDIRCMD_CMD_QUERY_REM_HASH 0x00000007
1963 #define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
1964 #define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
1965 #define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
1966 #define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
1967 #define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
1968 #define IXGBE_FDIRCMD_IPV6 0x00000080
1969 #define IXGBE_FDIRCMD_CLEARHT 0x00000100
1970 #define IXGBE_FDIRCMD_DROP 0x00000200
1971 #define IXGBE_FDIRCMD_INT 0x00000400
1972 #define IXGBE_FDIRCMD_LAST 0x00000800
1973 #define IXGBE_FDIRCMD_COLLISION 0x00001000
1974 #define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
1975 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
1976 #define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
1977 #define IXGBE_FDIR_INIT_DONE_POLL 10
1978 #define IXGBE_FDIRCMD_CMD_POLL 10
1980 /* Transmit Descriptor - Advanced */
1981 union ixgbe_adv_tx_desc {
1983 __le64 buffer_addr; /* Address of descriptor's data buf */
1984 __le32 cmd_type_len;
1985 __le32 olinfo_status;
1988 __le64 rsvd; /* Reserved */
1994 /* Receive Descriptor - Advanced */
1995 union ixgbe_adv_rx_desc {
1997 __le64 pkt_addr; /* Packet buffer address */
1998 __le64 hdr_addr; /* Header buffer address */
2005 __le16 pkt_info; /* RSS, Pkt type */
2006 __le16 hdr_info; /* Splithdr, hdrlen */
2010 __le32 rss; /* RSS Hash */
2012 __le16 ip_id; /* IP id */
2013 __le16 csum; /* Packet Checksum */
2018 __le32 status_error; /* ext status/error */
2019 __le16 length; /* Packet length */
2020 __le16 vlan; /* VLAN tag */
2022 } wb; /* writeback */
2025 /* Context descriptors */
2026 struct ixgbe_adv_tx_context_desc {
2027 __le32 vlan_macip_lens;
2029 __le32 type_tucmd_mlhl;
2030 __le32 mss_l4len_idx;
2033 /* Adv Transmit Descriptor Config Masks */
2034 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
2035 #define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */
2036 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */
2037 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */
2038 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
2039 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
2040 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
2041 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
2042 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
2043 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
2044 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
2045 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
2046 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
2047 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
2048 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
2049 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
2050 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
2051 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
2052 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
2053 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
2054 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2055 IXGBE_ADVTXD_POPTS_SHIFT)
2056 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2057 IXGBE_ADVTXD_POPTS_SHIFT)
2058 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
2059 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
2060 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
2061 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
2062 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
2063 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
2064 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
2065 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
2066 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
2067 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
2068 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
2069 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
2070 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
2071 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
2072 #define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */
2073 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
2074 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
2075 #define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */
2076 #define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */
2077 #define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */
2078 #define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */
2079 #define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation: End */
2080 #define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation: Start */
2081 #define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */
2082 #define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */
2083 #define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */
2084 #define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */
2085 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
2086 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
2088 /* Autonegotiation advertised speeds */
2089 typedef u32 ixgbe_autoneg_advertised;
2091 typedef u32 ixgbe_link_speed;
2092 #define IXGBE_LINK_SPEED_UNKNOWN 0
2093 #define IXGBE_LINK_SPEED_100_FULL 0x0008
2094 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2095 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2096 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2097 IXGBE_LINK_SPEED_10GB_FULL)
2098 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2099 IXGBE_LINK_SPEED_1GB_FULL | \
2100 IXGBE_LINK_SPEED_10GB_FULL)
2102 #define IXGBE_PCIE_DEV_CTRL_2 0xC8
2103 #define PCIE_COMPL_TO_VALUE 0x05
2105 /* Physical layer type */
2106 typedef u32 ixgbe_physical_layer;
2107 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
2108 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
2109 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
2110 #define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004
2111 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
2112 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
2113 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
2114 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
2115 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
2116 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
2117 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
2118 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
2119 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800
2120 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
2121 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
2123 /* Flow Control Macros */
2125 #define PAUSE_MTU(MTU) ((MTU + 1024 - 1) / 1024)
2127 #define FC_HIGH_WATER(MTU) ((((PAUSE_RTT + PAUSE_MTU(MTU)) * 144) + 99) / 100 +\
2129 #define FC_LOW_WATER(MTU) (2 * (2 * PAUSE_MTU(MTU) + PAUSE_RTT))
2131 /* Software ATR hash keys */
2132 #define IXGBE_ATR_BUCKET_HASH_KEY 0xE214AD3D
2133 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x14364D17
2135 /* Software ATR input stream offsets and masks */
2136 #define IXGBE_ATR_VLAN_OFFSET 0
2137 #define IXGBE_ATR_SRC_IPV6_OFFSET 2
2138 #define IXGBE_ATR_SRC_IPV4_OFFSET 14
2139 #define IXGBE_ATR_DST_IPV6_OFFSET 18
2140 #define IXGBE_ATR_DST_IPV4_OFFSET 30
2141 #define IXGBE_ATR_SRC_PORT_OFFSET 34
2142 #define IXGBE_ATR_DST_PORT_OFFSET 36
2143 #define IXGBE_ATR_FLEX_BYTE_OFFSET 38
2144 #define IXGBE_ATR_VM_POOL_OFFSET 40
2145 #define IXGBE_ATR_L4TYPE_OFFSET 41
2147 #define IXGBE_ATR_L4TYPE_MASK 0x3
2148 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2149 #define IXGBE_ATR_L4TYPE_UDP 0x1
2150 #define IXGBE_ATR_L4TYPE_TCP 0x2
2151 #define IXGBE_ATR_L4TYPE_SCTP 0x3
2152 #define IXGBE_ATR_HASH_MASK 0x7fff
2154 /* Flow Director ATR input struct. */
2155 struct ixgbe_atr_input {
2156 /* Byte layout in order, all values with MSB first:
2161 * src_port - 2 bytes
2162 * dst_port - 2 bytes
2163 * flex_bytes - 2 bytes
2170 struct ixgbe_atr_input_masks {
2179 enum ixgbe_eeprom_type {
2180 ixgbe_eeprom_uninitialized = 0,
2183 ixgbe_eeprom_none /* No NVM support */
2186 enum ixgbe_mac_type {
2187 ixgbe_mac_unknown = 0,
2194 enum ixgbe_phy_type {
2195 ixgbe_phy_unknown = 0,
2198 ixgbe_phy_cu_unknown,
2202 ixgbe_phy_sfp_passive_tyco,
2203 ixgbe_phy_sfp_passive_unknown,
2204 ixgbe_phy_sfp_active_unknown,
2205 ixgbe_phy_sfp_avago,
2207 ixgbe_phy_sfp_ftl_active,
2208 ixgbe_phy_sfp_unknown,
2209 ixgbe_phy_sfp_intel,
2210 ixgbe_phy_sfp_unsupported,
2215 * SFP+ module type IDs:
2222 * 3 SFP_DA_CU_CORE0 - 82599-specific
2223 * 4 SFP_DA_CU_CORE1 - 82599-specific
2224 * 5 SFP_SR/LR_CORE0 - 82599-specific
2225 * 6 SFP_SR/LR_CORE1 - 82599-specific
2227 enum ixgbe_sfp_type {
2228 ixgbe_sfp_type_da_cu = 0,
2229 ixgbe_sfp_type_sr = 1,
2230 ixgbe_sfp_type_lr = 2,
2231 ixgbe_sfp_type_da_cu_core0 = 3,
2232 ixgbe_sfp_type_da_cu_core1 = 4,
2233 ixgbe_sfp_type_srlr_core0 = 5,
2234 ixgbe_sfp_type_srlr_core1 = 6,
2235 ixgbe_sfp_type_da_act_lmt_core0 = 7,
2236 ixgbe_sfp_type_da_act_lmt_core1 = 8,
2237 ixgbe_sfp_type_1g_cu_core0 = 9,
2238 ixgbe_sfp_type_1g_cu_core1 = 10,
2239 ixgbe_sfp_type_not_present = 0xFFFE,
2240 ixgbe_sfp_type_unknown = 0xFFFF
2243 enum ixgbe_media_type {
2244 ixgbe_media_type_unknown = 0,
2245 ixgbe_media_type_fiber,
2246 ixgbe_media_type_copper,
2247 ixgbe_media_type_backplane,
2248 ixgbe_media_type_cx4,
2249 ixgbe_media_type_virtual
2252 /* Flow Control Settings */
2253 enum ixgbe_fc_mode {
2264 /* Smart Speed Settings */
2265 #define IXGBE_SMARTSPEED_MAX_RETRIES 3
2266 enum ixgbe_smart_speed {
2267 ixgbe_smart_speed_auto = 0,
2268 ixgbe_smart_speed_on,
2269 ixgbe_smart_speed_off
2273 enum ixgbe_bus_type {
2274 ixgbe_bus_type_unknown = 0,
2276 ixgbe_bus_type_pcix,
2277 ixgbe_bus_type_pci_express,
2278 ixgbe_bus_type_reserved
2281 /* PCI bus speeds */
2282 enum ixgbe_bus_speed {
2283 ixgbe_bus_speed_unknown = 0,
2286 ixgbe_bus_speed_100,
2287 ixgbe_bus_speed_120,
2288 ixgbe_bus_speed_133,
2289 ixgbe_bus_speed_2500,
2290 ixgbe_bus_speed_5000,
2291 ixgbe_bus_speed_reserved
2294 /* PCI bus widths */
2295 enum ixgbe_bus_width {
2296 ixgbe_bus_width_unknown = 0,
2297 ixgbe_bus_width_pcie_x1,
2298 ixgbe_bus_width_pcie_x2,
2299 ixgbe_bus_width_pcie_x4 = 4,
2300 ixgbe_bus_width_pcie_x8 = 8,
2303 ixgbe_bus_width_reserved
2306 struct ixgbe_addr_filter_info {
2309 u32 mc_addr_in_rar_count;
2311 u32 overflow_promisc;
2312 bool uc_set_promisc;
2313 bool user_set_promisc;
2316 /* Bus parameters */
2317 struct ixgbe_bus_info {
2318 enum ixgbe_bus_speed speed;
2319 enum ixgbe_bus_width width;
2320 enum ixgbe_bus_type type;
2326 /* Flow control parameters */
2327 struct ixgbe_fc_info {
2328 u32 high_water; /* Flow Control High-water */
2329 u32 low_water; /* Flow Control Low-water */
2330 u16 pause_time; /* Flow Control Pause timer */
2331 bool send_xon; /* Flow control send XON */
2332 bool strict_ieee; /* Strict IEEE mode */
2333 bool disable_fc_autoneg; /* Do not autonegotiate FC */
2334 bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
2335 enum ixgbe_fc_mode current_mode; /* FC mode in effect */
2336 enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
2339 /* Statistics counters collected by the MAC */
2340 struct ixgbe_hw_stats {
2399 u64 fdirustat_remove;
2401 u64 fdirfstat_fremove;
2412 /* forward declaration */
2415 /* iterator type for walking multicast address lists */
2416 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
2419 /* Function pointer table */
2420 struct ixgbe_eeprom_operations {
2421 s32 (*init_params)(struct ixgbe_hw *);
2422 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
2423 s32 (*write)(struct ixgbe_hw *, u16, u16);
2424 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
2425 s32 (*update_checksum)(struct ixgbe_hw *);
2426 u16 (*calc_checksum)(struct ixgbe_hw *);
2429 struct ixgbe_mac_operations {
2430 s32 (*init_hw)(struct ixgbe_hw *);
2431 s32 (*reset_hw)(struct ixgbe_hw *);
2432 s32 (*start_hw)(struct ixgbe_hw *);
2433 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
2434 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
2435 u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
2436 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
2437 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
2438 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
2439 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
2440 s32 (*stop_adapter)(struct ixgbe_hw *);
2441 s32 (*get_bus_info)(struct ixgbe_hw *);
2442 void (*set_lan_id)(struct ixgbe_hw *);
2443 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
2444 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
2445 s32 (*setup_sfp)(struct ixgbe_hw *);
2446 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
2449 void (*disable_tx_laser)(struct ixgbe_hw *);
2450 void (*enable_tx_laser)(struct ixgbe_hw *);
2451 void (*flap_tx_laser)(struct ixgbe_hw *);
2452 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool, bool);
2453 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
2454 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
2458 s32 (*led_on)(struct ixgbe_hw *, u32);
2459 s32 (*led_off)(struct ixgbe_hw *, u32);
2460 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
2461 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
2463 /* RAR, Multicast, VLAN */
2464 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
2465 s32 (*clear_rar)(struct ixgbe_hw *, u32);
2466 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
2467 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
2468 s32 (*init_rx_addrs)(struct ixgbe_hw *);
2469 s32 (*update_uc_addr_list)(struct ixgbe_hw *, struct net_device *);
2470 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
2471 s32 (*enable_mc)(struct ixgbe_hw *);
2472 s32 (*disable_mc)(struct ixgbe_hw *);
2473 s32 (*clear_vfta)(struct ixgbe_hw *);
2474 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
2475 s32 (*init_uta_tables)(struct ixgbe_hw *);
2478 s32 (*fc_enable)(struct ixgbe_hw *, s32);
2481 struct ixgbe_phy_operations {
2482 s32 (*identify)(struct ixgbe_hw *);
2483 s32 (*identify_sfp)(struct ixgbe_hw *);
2484 s32 (*init)(struct ixgbe_hw *);
2485 s32 (*reset)(struct ixgbe_hw *);
2486 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
2487 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
2488 s32 (*setup_link)(struct ixgbe_hw *);
2489 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
2491 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
2492 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
2493 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
2494 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
2495 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
2496 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
2497 s32 (*check_overtemp)(struct ixgbe_hw *);
2500 struct ixgbe_eeprom_info {
2501 struct ixgbe_eeprom_operations ops;
2502 enum ixgbe_eeprom_type type;
2503 u32 semaphore_delay;
2508 struct ixgbe_mac_info {
2509 struct ixgbe_mac_operations ops;
2510 enum ixgbe_mac_type type;
2511 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2512 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2513 u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
2514 /* prefix for World Wide Node Name (WWNN) */
2516 /* prefix for World Wide Port Name (WWPN) */
2521 u32 num_rar_entries;
2525 u32 max_msix_vectors;
2528 bool orig_link_settings_stored;
2529 bool autotry_restart;
2532 struct ixgbe_phy_info {
2533 struct ixgbe_phy_operations ops;
2534 struct mdio_if_info mdio;
2535 enum ixgbe_phy_type type;
2537 enum ixgbe_sfp_type sfp_type;
2538 bool sfp_setup_needed;
2540 enum ixgbe_media_type media_type;
2542 ixgbe_autoneg_advertised autoneg_advertised;
2543 enum ixgbe_smart_speed smart_speed;
2544 bool smart_speed_active;
2545 bool multispeed_fiber;
2546 bool reset_if_overtemp;
2549 #include "ixgbe_mbx.h"
2551 struct ixgbe_mbx_operations {
2552 s32 (*init_params)(struct ixgbe_hw *hw);
2553 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
2554 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
2555 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2556 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
2557 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
2558 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
2559 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
2562 struct ixgbe_mbx_stats {
2571 struct ixgbe_mbx_info {
2572 struct ixgbe_mbx_operations ops;
2573 struct ixgbe_mbx_stats stats;
2581 u8 __iomem *hw_addr;
2583 struct ixgbe_mac_info mac;
2584 struct ixgbe_addr_filter_info addr_ctrl;
2585 struct ixgbe_fc_info fc;
2586 struct ixgbe_phy_info phy;
2587 struct ixgbe_eeprom_info eeprom;
2588 struct ixgbe_bus_info bus;
2589 struct ixgbe_mbx_info mbx;
2592 u16 subsystem_device_id;
2593 u16 subsystem_vendor_id;
2595 bool adapter_stopped;
2596 bool force_full_reset;
2600 enum ixgbe_mac_type mac;
2601 s32 (*get_invariants)(struct ixgbe_hw *);
2602 struct ixgbe_mac_operations *mac_ops;
2603 struct ixgbe_eeprom_operations *eeprom_ops;
2604 struct ixgbe_phy_operations *phy_ops;
2605 struct ixgbe_mbx_operations *mbx_ops;
2610 #define IXGBE_ERR_EEPROM -1
2611 #define IXGBE_ERR_EEPROM_CHECKSUM -2
2612 #define IXGBE_ERR_PHY -3
2613 #define IXGBE_ERR_CONFIG -4
2614 #define IXGBE_ERR_PARAM -5
2615 #define IXGBE_ERR_MAC_TYPE -6
2616 #define IXGBE_ERR_UNKNOWN_PHY -7
2617 #define IXGBE_ERR_LINK_SETUP -8
2618 #define IXGBE_ERR_ADAPTER_STOPPED -9
2619 #define IXGBE_ERR_INVALID_MAC_ADDR -10
2620 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
2621 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
2622 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
2623 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
2624 #define IXGBE_ERR_RESET_FAILED -15
2625 #define IXGBE_ERR_SWFW_SYNC -16
2626 #define IXGBE_ERR_PHY_ADDR_INVALID -17
2627 #define IXGBE_ERR_I2C -18
2628 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
2629 #define IXGBE_ERR_SFP_NOT_PRESENT -20
2630 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
2631 #define IXGBE_ERR_NO_SAN_ADDR_PTR -22
2632 #define IXGBE_ERR_FDIR_REINIT_FAILED -23
2633 #define IXGBE_ERR_EEPROM_VERSION -24
2634 #define IXGBE_ERR_NO_SPACE -25
2635 #define IXGBE_ERR_OVERTEMP -26
2636 #define IXGBE_ERR_RAR_INDEX -27
2637 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
2639 #endif /* _IXGBE_TYPE_H_ */