drivers/net/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe_common.h"
  33 #include "ixgbe_phy.h"
  34
  35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
  47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  49
  50 /**
  51  *  ixgbe_identify_phy_generic - Get physical layer module
  52  *  @hw: pointer to hardware structure
  53  *
  54  *  Determines the physical layer module found on the current adapter.
  55  **/
  56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  57 {
  58         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  59         u32 phy_addr;
  60
  61         if (hw->phy.type == ixgbe_phy_unknown) {
  62                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  63                         hw->phy.mdio.prtad = phy_addr;
  64                         if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
  65                                 ixgbe_get_phy_id(hw);
  66                                 hw->phy.type =
  67                                         ixgbe_get_phy_type_from_id(hw->phy.id);
  68                                 status = 0;
  69                                 break;
  70                         }
  71                 }
  72                 /* clear value if nothing found */
  73                 hw->phy.mdio.prtad = 0;
  74         } else {
  75                 status = 0;
  76         }
  77
  78         return status;
  79 }
  80
  81 /**
  82  *  ixgbe_get_phy_id - Get the phy type
  83  *  @hw: pointer to hardware structure
  84  *
  85  **/
  86 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
  87 {
  88         u32 status;
  89         u16 phy_id_high = 0;
  90         u16 phy_id_low = 0;
  91
  92         status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
  93                                       &phy_id_high);
  94
  95         if (status == 0) {
  96                 hw->phy.id = (u32)(phy_id_high << 16);
  97                 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
  98                                               &phy_id_low);
  99                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 100                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 101         }
 102         return status;
 103 }
 104
 105 /**
 106  *  ixgbe_get_phy_type_from_id - Get the phy type
 107  *  @hw: pointer to hardware structure
 108  *
 109  **/
 110 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 111 {
 112         enum ixgbe_phy_type phy_type;
 113
 114         switch (phy_id) {
 115         case TN1010_PHY_ID:
 116                 phy_type = ixgbe_phy_tn;
 117                 break;
 118         case QT2022_PHY_ID:
 119                 phy_type = ixgbe_phy_qt;
 120                 break;
 121         case ATH_PHY_ID:
 122                 phy_type = ixgbe_phy_nl;
 123                 break;
 124         default:
 125                 phy_type = ixgbe_phy_unknown;
 126                 break;
 127         }
 128
 129         return phy_type;
 130 }
 131
 132 /**
 133  *  ixgbe_reset_phy_generic - Performs a PHY reset
 134  *  @hw: pointer to hardware structure
 135  **/
 136 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 137 {
 138         /* Don't reset PHY if it's shut down due to overtemp. */
 139         if (!hw->phy.reset_if_overtemp &&
 140             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 141                 return 0;
 142
 143         /*
 144          * Perform soft PHY reset to the PHY_XS.
 145          * This will cause a soft reset to the PHY
 146          */
 147         return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 148                                      MDIO_CTRL1_RESET);
 149 }
 150
 151 /**
 152  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 153  *  @hw: pointer to hardware structure
 154  *  @reg_addr: 32 bit address of PHY register to read
 155  *  @phy_data: Pointer to read data from PHY register
 156  **/
 157 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 158                                u32 device_type, u16 *phy_data)
 159 {
 160         u32 command;
 161         u32 i;
 162         u32 data;
 163         s32 status = 0;
 164         u16 gssr;
 165
 166         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 167                 gssr = IXGBE_GSSR_PHY1_SM;
 168         else
 169                 gssr = IXGBE_GSSR_PHY0_SM;
 170
 171         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 172                 status = IXGBE_ERR_SWFW_SYNC;
 173
 174         if (status == 0) {
 175                 /* Setup and write the address cycle command */
 176                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 177                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 178                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 179                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 180
 181                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 182
 183                 /*
 184                  * Check every 10 usec to see if the address cycle completed.
 185                  * The MDI Command bit will clear when the operation is
 186                  * complete
 187                  */
 188                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 189                         udelay(10);
 190
 191                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 192
 193                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 194                                 break;
 195                 }
 196
 197                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 198                         hw_dbg(hw, "PHY address command did not complete.\n");
 199                         status = IXGBE_ERR_PHY;
 200                 }
 201
 202                 if (status == 0) {
 203                         /*
 204                          * Address cycle complete, setup and write the read
 205                          * command
 206                          */
 207                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 208                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 209                                    (hw->phy.mdio.prtad <<
 210                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 211                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 212
 213                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 214
 215                         /*
 216                          * Check every 10 usec to see if the address cycle
 217                          * completed. The MDI Command bit will clear when the
 218                          * operation is complete
 219                          */
 220                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 221                                 udelay(10);
 222
 223                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 224
 225                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 226                                         break;
 227                         }
 228
 229                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 230                                 hw_dbg(hw, "PHY read command didn't complete\n");
 231                                 status = IXGBE_ERR_PHY;
 232                         } else {
 233                                 /*
 234                                  * Read operation is complete.  Get the data
 235                                  * from MSRWD
 236                                  */
 237                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 238                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 239                                 *phy_data = (u16)(data);
 240                         }
 241                 }
 242
 243                 ixgbe_release_swfw_sync(hw, gssr);
 244         }
 245
 246         return status;
 247 }
 248
 249 /**
 250  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 251  *  @hw: pointer to hardware structure
 252  *  @reg_addr: 32 bit PHY register to write
 253  *  @device_type: 5 bit device type
 254  *  @phy_data: Data to write to the PHY register
 255  **/
 256 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 257                                 u32 device_type, u16 phy_data)
 258 {
 259         u32 command;
 260         u32 i;
 261         s32 status = 0;
 262         u16 gssr;
 263
 264         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 265                 gssr = IXGBE_GSSR_PHY1_SM;
 266         else
 267                 gssr = IXGBE_GSSR_PHY0_SM;
 268
 269         if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
 270                 status = IXGBE_ERR_SWFW_SYNC;
 271
 272         if (status == 0) {
 273                 /* Put the data in the MDI single read and write data register*/
 274                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 275
 276                 /* Setup and write the address cycle command */
 277                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 278                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 279                            (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 280                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 281
 282                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 283
 284                 /*
 285                  * Check every 10 usec to see if the address cycle completed.
 286                  * The MDI Command bit will clear when the operation is
 287                  * complete
 288                  */
 289                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 290                         udelay(10);
 291
 292                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 293
 294                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 295                                 break;
 296                 }
 297
 298                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 299                         hw_dbg(hw, "PHY address cmd didn't complete\n");
 300                         status = IXGBE_ERR_PHY;
 301                 }
 302
 303                 if (status == 0) {
 304                         /*
 305                          * Address cycle complete, setup and write the write
 306                          * command
 307                          */
 308                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 309                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 310                                    (hw->phy.mdio.prtad <<
 311                                     IXGBE_MSCA_PHY_ADDR_SHIFT) |
 312                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 313
 314                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 315
 316                         /*
 317                          * Check every 10 usec to see if the address cycle
 318                          * completed. The MDI Command bit will clear when the
 319                          * operation is complete
 320                          */
 321                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 322                                 udelay(10);
 323
 324                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 325
 326                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 327                                         break;
 328                         }
 329
 330                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 331                                 hw_dbg(hw, "PHY address cmd didn't complete\n");
 332                                 status = IXGBE_ERR_PHY;
 333                         }
 334                 }
 335
 336                 ixgbe_release_swfw_sync(hw, gssr);
 337         }
 338
 339         return status;
 340 }
 341
 342 /**
 343  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 344  *  @hw: pointer to hardware structure
 345  *
 346  *  Restart autonegotiation and PHY and waits for completion.
 347  **/
 348 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 349 {
 350         s32 status = IXGBE_NOT_IMPLEMENTED;
 351         u32 time_out;
 352         u32 max_time_out = 10;
 353         u16 autoneg_reg;
 354
 355         /*
 356          * Set advertisement settings in PHY based on autoneg_advertised
 357          * settings. If autoneg_advertised = 0, then advertise default values
 358          * tnx devices cannot be "forced" to a autoneg 10G and fail.  But can
 359          * for a 1G.
 360          */
 361         hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
 362
 363         if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
 364                 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
 365         else
 366                 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
 367
 368         hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
 369
 370         /* Restart PHY autonegotiation and wait for completion */
 371         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
 372
 373         autoneg_reg |= MDIO_AN_CTRL1_RESTART;
 374
 375         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
 376
 377         /* Wait for autonegotiation to finish */
 378         for (time_out = 0; time_out < max_time_out; time_out++) {
 379                 udelay(10);
 380                 /* Restart PHY autonegotiation and wait for completion */
 381                 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
 382                                               &autoneg_reg);
 383
 384                 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
 385                 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
 386                         status = 0;
 387                         break;
 388                 }
 389         }
 390
 391         if (time_out == max_time_out)
 392                 status = IXGBE_ERR_LINK_SETUP;
 393
 394         return status;
 395 }
 396
 397 /**
 398  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 399  *  @hw: pointer to hardware structure
 400  *  @speed: new link speed
 401  *  @autoneg: true if autonegotiation enabled
 402  **/
 403 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 404                                        ixgbe_link_speed speed,
 405                                        bool autoneg,
 406                                        bool autoneg_wait_to_complete)
 407 {
 408
 409         /*
 410          * Clear autoneg_advertised and set new values based on input link
 411          * speed.
 412          */
 413         hw->phy.autoneg_advertised = 0;
 414
 415         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 416                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 417
 418         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 419                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 420
 421         /* Setup link based on the new speed settings */
 422         hw->phy.ops.setup_link(hw);
 423
 424         return 0;
 425 }
 426
 427 /**
 428  * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 429  * @hw: pointer to hardware structure
 430  * @speed: pointer to link speed
 431  * @autoneg: boolean auto-negotiation value
 432  *
 433  * Determines the link capabilities by reading the AUTOC register.
 434  */
 435 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 436                                                       ixgbe_link_speed *speed,
 437                                                       bool *autoneg)
 438 {
 439         s32 status = IXGBE_ERR_LINK_SETUP;
 440         u16 speed_ability;
 441
 442         *speed = 0;
 443         *autoneg = true;
 444
 445         status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
 446                                       &speed_ability);
 447
 448         if (status == 0) {
 449                 if (speed_ability & MDIO_SPEED_10G)
 450                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 451                 if (speed_ability & MDIO_PMA_SPEED_1000)
 452                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 453                 if (speed_ability & MDIO_PMA_SPEED_100)
 454                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 455         }
 456
 457         return status;
 458 }
 459
 460 /**
 461  *  ixgbe_reset_phy_nl - Performs a PHY reset
 462  *  @hw: pointer to hardware structure
 463  **/
 464 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 465 {
 466         u16 phy_offset, control, eword, edata, block_crc;
 467         bool end_data = false;
 468         u16 list_offset, data_offset;
 469         u16 phy_data = 0;
 470         s32 ret_val = 0;
 471         u32 i;
 472
 473         hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
 474
 475         /* reset the PHY and poll for completion */
 476         hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 477                               (phy_data | MDIO_CTRL1_RESET));
 478
 479         for (i = 0; i < 100; i++) {
 480                 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
 481                                      &phy_data);
 482                 if ((phy_data & MDIO_CTRL1_RESET) == 0)
 483                         break;
 484                 msleep(10);
 485         }
 486
 487         if ((phy_data & MDIO_CTRL1_RESET) != 0) {
 488                 hw_dbg(hw, "PHY reset did not complete.\n");
 489                 ret_val = IXGBE_ERR_PHY;
 490                 goto out;
 491         }
 492
 493         /* Get init offsets */
 494         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 495                                                       &data_offset);
 496         if (ret_val != 0)
 497                 goto out;
 498
 499         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 500         data_offset++;
 501         while (!end_data) {
 502                 /*
 503                  * Read control word from PHY init contents offset
 504                  */
 505                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 506                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 507                            IXGBE_CONTROL_SHIFT_NL;
 508                 edata = eword & IXGBE_DATA_MASK_NL;
 509                 switch (control) {
 510                 case IXGBE_DELAY_NL:
 511                         data_offset++;
 512                         hw_dbg(hw, "DELAY: %d MS\n", edata);
 513                         msleep(edata);
 514                         break;
 515                 case IXGBE_DATA_NL:
 516                         hw_dbg(hw, "DATA:\n");
 517                         data_offset++;
 518                         hw->eeprom.ops.read(hw, data_offset++,
 519                                             &phy_offset);
 520                         for (i = 0; i < edata; i++) {
 521                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 522                                 hw->phy.ops.write_reg(hw, phy_offset,
 523                                                       MDIO_MMD_PMAPMD, eword);
 524                                 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
 525                                        phy_offset);
 526                                 data_offset++;
 527                                 phy_offset++;
 528                         }
 529                         break;
 530                 case IXGBE_CONTROL_NL:
 531                         data_offset++;
 532                         hw_dbg(hw, "CONTROL:\n");
 533                         if (edata == IXGBE_CONTROL_EOL_NL) {
 534                                 hw_dbg(hw, "EOL\n");
 535                                 end_data = true;
 536                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 537                                 hw_dbg(hw, "SOL\n");
 538                         } else {
 539                                 hw_dbg(hw, "Bad control value\n");
 540                                 ret_val = IXGBE_ERR_PHY;
 541                                 goto out;
 542                         }
 543                         break;
 544                 default:
 545                         hw_dbg(hw, "Bad control type\n");
 546                         ret_val = IXGBE_ERR_PHY;
 547                         goto out;
 548                 }
 549         }
 550
 551 out:
 552         return ret_val;
 553 }
 554
 555 /**
 556  *  ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
 557  *                                      the PHY type.
 558  *  @hw: pointer to hardware structure
 559  *
 560  *  Searches for and indentifies the SFP module.  Assings appropriate PHY type.
 561  **/
 562 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 563 {
 564         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 565         u32 vendor_oui = 0;
 566         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 567         u8 identifier = 0;
 568         u8 comp_codes_1g = 0;
 569         u8 comp_codes_10g = 0;
 570         u8 oui_bytes[3] = {0, 0, 0};
 571         u8 cable_tech = 0;
 572         u8 cable_spec = 0;
 573         u16 enforce_sfp = 0;
 574
 575         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 576                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 577                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 578                 goto out;
 579         }
 580
 581         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
 582                                              &identifier);
 583
 584         if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
 585                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 586                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 587                 if (hw->phy.type != ixgbe_phy_nl) {
 588                         hw->phy.id = 0;
 589                         hw->phy.type = ixgbe_phy_unknown;
 590                 }
 591                 goto out;
 592         }
 593
 594         if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
 595                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
 596                                             &comp_codes_1g);
 597                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
 598                                             &comp_codes_10g);
 599                 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
 600                                             &cable_tech);
 601
 602                 /* ID Module
 603                  * =========
 604                  * 0    SFP_DA_CU
 605                  * 1    SFP_SR
 606                  * 2    SFP_LR
 607                  * 3    SFP_DA_CORE0 - 82599-specific
 608                  * 4    SFP_DA_CORE1 - 82599-specific
 609                  * 5    SFP_SR/LR_CORE0 - 82599-specific
 610                  * 6    SFP_SR/LR_CORE1 - 82599-specific
 611                  * 7    SFP_act_lmt_DA_CORE0 - 82599-specific
 612                  * 8    SFP_act_lmt_DA_CORE1 - 82599-specific
 613                  * 9    SFP_1g_cu_CORE0 - 82599-specific
 614                  * 10   SFP_1g_cu_CORE1 - 82599-specific
 615                  */
 616                 if (hw->mac.type == ixgbe_mac_82598EB) {
 617                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 618                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
 619                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 620                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
 621                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 622                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
 623                         else
 624                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 625                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
 626                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
 627                                 if (hw->bus.lan_id == 0)
 628                                         hw->phy.sfp_type =
 629                                                      ixgbe_sfp_type_da_cu_core0;
 630                                 else
 631                                         hw->phy.sfp_type =
 632                                                      ixgbe_sfp_type_da_cu_core1;
 633                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
 634                                 hw->phy.ops.read_i2c_eeprom(
 635                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
 636                                                 &cable_spec);
 637                                 if (cable_spec &
 638                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
 639                                         if (hw->bus.lan_id == 0)
 640                                                 hw->phy.sfp_type =
 641                                                 ixgbe_sfp_type_da_act_lmt_core0;
 642                                         else
 643                                                 hw->phy.sfp_type =
 644                                                 ixgbe_sfp_type_da_act_lmt_core1;
 645                                 } else {
 646                                         hw->phy.sfp_type =
 647                                                 ixgbe_sfp_type_unknown;
 648                                 }
 649                         } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 650                                 if (hw->bus.lan_id == 0)
 651                                         hw->phy.sfp_type =
 652                                                       ixgbe_sfp_type_srlr_core0;
 653                                 else
 654                                         hw->phy.sfp_type =
 655                                                       ixgbe_sfp_type_srlr_core1;
 656                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 657                                 if (hw->bus.lan_id == 0)
 658                                         hw->phy.sfp_type =
 659                                                       ixgbe_sfp_type_srlr_core0;
 660                                 else
 661                                         hw->phy.sfp_type =
 662                                                       ixgbe_sfp_type_srlr_core1;
 663                         else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
 664                                 if (hw->bus.lan_id == 0)
 665                                         hw->phy.sfp_type =
 666                                                 ixgbe_sfp_type_1g_cu_core0;
 667                                 else
 668                                         hw->phy.sfp_type =
 669                                                 ixgbe_sfp_type_1g_cu_core1;
 670                         else
 671                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
 672                 }
 673
 674                 if (hw->phy.sfp_type != stored_sfp_type)
 675                         hw->phy.sfp_setup_needed = true;
 676
 677                 /* Determine if the SFP+ PHY is dual speed or not. */
 678                 hw->phy.multispeed_fiber = false;
 679                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
 680                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
 681                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
 682                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
 683                         hw->phy.multispeed_fiber = true;
 684
 685                 /* Determine PHY vendor */
 686                 if (hw->phy.type != ixgbe_phy_nl) {
 687                         hw->phy.id = identifier;
 688                         hw->phy.ops.read_i2c_eeprom(hw,
 689                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
 690                                                     &oui_bytes[0]);
 691                         hw->phy.ops.read_i2c_eeprom(hw,
 692                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
 693                                                     &oui_bytes[1]);
 694                         hw->phy.ops.read_i2c_eeprom(hw,
 695                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
 696                                                     &oui_bytes[2]);
 697
 698                         vendor_oui =
 699                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
 700                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
 701                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
 702
 703                         switch (vendor_oui) {
 704                         case IXGBE_SFF_VENDOR_OUI_TYCO:
 705                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 706                                         hw->phy.type =
 707                                                 ixgbe_phy_sfp_passive_tyco;
 708                                 break;
 709                         case IXGBE_SFF_VENDOR_OUI_FTL:
 710                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
 711                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
 712                                 else
 713                                         hw->phy.type = ixgbe_phy_sfp_ftl;
 714                                 break;
 715                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
 716                                 hw->phy.type = ixgbe_phy_sfp_avago;
 717                                 break;
 718                         case IXGBE_SFF_VENDOR_OUI_INTEL:
 719                                 hw->phy.type = ixgbe_phy_sfp_intel;
 720                                 break;
 721                         default:
 722                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
 723                                         hw->phy.type =
 724                                                 ixgbe_phy_sfp_passive_unknown;
 725                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
 726                                         hw->phy.type =
 727                                                 ixgbe_phy_sfp_active_unknown;
 728                                 else
 729                                         hw->phy.type = ixgbe_phy_sfp_unknown;
 730                                 break;
 731                         }
 732                 }
 733
 734                 /* All passive DA cables are supported */
 735                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
 736                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
 737                         status = 0;
 738                         goto out;
 739                 }
 740
 741                 /* Verify supported 1G SFP modules */
 742                 if (comp_codes_10g == 0 &&
 743                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
 744                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
 745                         hw->phy.type = ixgbe_phy_sfp_unsupported;
 746                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 747                         goto out;
 748                 }
 749
 750                 /* Anything else 82598-based is supported */
 751                 if (hw->mac.type == ixgbe_mac_82598EB) {
 752                         status = 0;
 753                         goto out;
 754                 }
 755
 756                 /* This is guaranteed to be 82599, no need to check for NULL */
 757                 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
 758                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
 759                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
 760                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
 761                         /* Make sure we're a supported PHY type */
 762                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
 763                                 status = 0;
 764                         } else {
 765                                 hw_dbg(hw, "SFP+ module not supported\n");
 766                                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 767                                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 768                         }
 769                 } else {
 770                         status = 0;
 771                 }
 772         }
 773
 774 out:
 775         return status;
 776 }
 777
 778 /**
 779  *  ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
 780  *  if it supports a given SFP+ module type, if so it returns the offsets to the
 781  *  phy init sequence block.
 782  *  @hw: pointer to hardware structure
 783  *  @list_offset: offset to the SFP ID list
 784  *  @data_offset: offset to the SFP data block
 785  **/
 786 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 787                                         u16 *list_offset,
 788                                         u16 *data_offset)
 789 {
 790         u16 sfp_id;
 791         u16 sfp_type = hw->phy.sfp_type;
 792
 793         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
 794                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 795
 796         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 797                 return IXGBE_ERR_SFP_NOT_PRESENT;
 798
 799         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
 800             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
 801                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 802
 803         /*
 804          * Limiting active cables and 1G Phys must be initialized as
 805          * SR modules
 806          */
 807         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
 808             sfp_type == ixgbe_sfp_type_1g_cu_core0)
 809                 sfp_type = ixgbe_sfp_type_srlr_core0;
 810         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
 811                  sfp_type == ixgbe_sfp_type_1g_cu_core1)
 812                 sfp_type = ixgbe_sfp_type_srlr_core1;
 813
 814         /* Read offset to PHY init contents */
 815         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
 816
 817         if ((!*list_offset) || (*list_offset == 0xFFFF))
 818                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
 819
 820         /* Shift offset to first ID word */
 821         (*list_offset)++;
 822
 823         /*
 824          * Find the matching SFP ID in the EEPROM
 825          * and program the init sequence
 826          */
 827         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
 828
 829         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
 830                 if (sfp_id == sfp_type) {
 831                         (*list_offset)++;
 832                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
 833                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
 834                                 hw_dbg(hw, "SFP+ module not supported\n");
 835                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 836                         } else {
 837                                 break;
 838                         }
 839                 } else {
 840                         (*list_offset) += 2;
 841                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
 842                                 return IXGBE_ERR_PHY;
 843                 }
 844         }
 845
 846         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
 847                 hw_dbg(hw, "No matching SFP+ module found\n");
 848                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
 849         }
 850
 851         return 0;
 852 }
 853
 854 /**
 855  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
 856  *  @hw: pointer to hardware structure
 857  *  @byte_offset: EEPROM byte offset to read
 858  *  @eeprom_data: value read
 859  *
 860  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 861  **/
 862 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 863                                   u8 *eeprom_data)
 864 {
 865         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
 866                                          IXGBE_I2C_EEPROM_DEV_ADDR,
 867                                          eeprom_data);
 868 }
 869
 870 /**
 871  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
 872  *  @hw: pointer to hardware structure
 873  *  @byte_offset: EEPROM byte offset to write
 874  *  @eeprom_data: value to write
 875  *
 876  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
 877  **/
 878 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 879                                    u8 eeprom_data)
 880 {
 881         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
 882                                           IXGBE_I2C_EEPROM_DEV_ADDR,
 883                                           eeprom_data);
 884 }
 885
 886 /**
 887  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
 888  *  @hw: pointer to hardware structure
 889  *  @byte_offset: byte offset to read
 890  *  @data: value read
 891  *
 892  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
 893  *  a specified deivce address.
 894  **/
 895 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 896                                 u8 dev_addr, u8 *data)
 897 {
 898         s32 status = 0;
 899         u32 max_retry = 1;
 900         u32 retry = 0;
 901         bool nack = 1;
 902
 903         do {
 904                 ixgbe_i2c_start(hw);
 905
 906                 /* Device Address and write indication */
 907                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 908                 if (status != 0)
 909                         goto fail;
 910
 911                 status = ixgbe_get_i2c_ack(hw);
 912                 if (status != 0)
 913                         goto fail;
 914
 915                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 916                 if (status != 0)
 917                         goto fail;
 918
 919                 status = ixgbe_get_i2c_ack(hw);
 920                 if (status != 0)
 921                         goto fail;
 922
 923                 ixgbe_i2c_start(hw);
 924
 925                 /* Device Address and read indication */
 926                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
 927                 if (status != 0)
 928                         goto fail;
 929
 930                 status = ixgbe_get_i2c_ack(hw);
 931                 if (status != 0)
 932                         goto fail;
 933
 934                 status = ixgbe_clock_in_i2c_byte(hw, data);
 935                 if (status != 0)
 936                         goto fail;
 937
 938                 status = ixgbe_clock_out_i2c_bit(hw, nack);
 939                 if (status != 0)
 940                         goto fail;
 941
 942                 ixgbe_i2c_stop(hw);
 943                 break;
 944
 945 fail:
 946                 ixgbe_i2c_bus_clear(hw);
 947                 retry++;
 948                 if (retry < max_retry)
 949                         hw_dbg(hw, "I2C byte read error - Retrying.\n");
 950                 else
 951                         hw_dbg(hw, "I2C byte read error.\n");
 952
 953         } while (retry < max_retry);
 954
 955         return status;
 956 }
 957
 958 /**
 959  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
 960  *  @hw: pointer to hardware structure
 961  *  @byte_offset: byte offset to write
 962  *  @data: value to write
 963  *
 964  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
 965  *  a specified device address.
 966  **/
 967 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 968                                  u8 dev_addr, u8 data)
 969 {
 970         s32 status = 0;
 971         u32 max_retry = 1;
 972         u32 retry = 0;
 973
 974         do {
 975                 ixgbe_i2c_start(hw);
 976
 977                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
 978                 if (status != 0)
 979                         goto fail;
 980
 981                 status = ixgbe_get_i2c_ack(hw);
 982                 if (status != 0)
 983                         goto fail;
 984
 985                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
 986                 if (status != 0)
 987                         goto fail;
 988
 989                 status = ixgbe_get_i2c_ack(hw);
 990                 if (status != 0)
 991                         goto fail;
 992
 993                 status = ixgbe_clock_out_i2c_byte(hw, data);
 994                 if (status != 0)
 995                         goto fail;
 996
 997                 status = ixgbe_get_i2c_ack(hw);
 998                 if (status != 0)
 999                         goto fail;
1000
1001                 ixgbe_i2c_stop(hw);
1002                 break;
1003
1004 fail:
1005                 ixgbe_i2c_bus_clear(hw);
1006                 retry++;
1007                 if (retry < max_retry)
1008                         hw_dbg(hw, "I2C byte write error - Retrying.\n");
1009                 else
1010                         hw_dbg(hw, "I2C byte write error.\n");
1011         } while (retry < max_retry);
1012
1013         return status;
1014 }
1015
1016 /**
1017  *  ixgbe_i2c_start - Sets I2C start condition
1018  *  @hw: pointer to hardware structure
1019  *
1020  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1021  **/
1022 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1023 {
1024         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1025
1026         /* Start condition must begin with data and clock high */
1027         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1028         ixgbe_raise_i2c_clk(hw, &i2cctl);
1029
1030         /* Setup time for start condition (4.7us) */
1031         udelay(IXGBE_I2C_T_SU_STA);
1032
1033         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1034
1035         /* Hold time for start condition (4us) */
1036         udelay(IXGBE_I2C_T_HD_STA);
1037
1038         ixgbe_lower_i2c_clk(hw, &i2cctl);
1039
1040         /* Minimum low period of clock is 4.7 us */
1041         udelay(IXGBE_I2C_T_LOW);
1042
1043 }
1044
1045 /**
1046  *  ixgbe_i2c_stop - Sets I2C stop condition
1047  *  @hw: pointer to hardware structure
1048  *
1049  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1050  **/
1051 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1052 {
1053         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1054
1055         /* Stop condition must begin with data low and clock high */
1056         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1057         ixgbe_raise_i2c_clk(hw, &i2cctl);
1058
1059         /* Setup time for stop condition (4us) */
1060         udelay(IXGBE_I2C_T_SU_STO);
1061
1062         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1063
1064         /* bus free time between stop and start (4.7us)*/
1065         udelay(IXGBE_I2C_T_BUF);
1066 }
1067
1068 /**
1069  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1070  *  @hw: pointer to hardware structure
1071  *  @data: data byte to clock in
1072  *
1073  *  Clocks in one byte data via I2C data/clock
1074  **/
1075 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1076 {
1077         s32 status = 0;
1078         s32 i;
1079         bool bit = 0;
1080
1081         for (i = 7; i >= 0; i--) {
1082                 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1083                 *data |= bit << i;
1084
1085                 if (status != 0)
1086                         break;
1087         }
1088
1089         return status;
1090 }
1091
1092 /**
1093  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1094  *  @hw: pointer to hardware structure
1095  *  @data: data byte clocked out
1096  *
1097  *  Clocks out one byte data via I2C data/clock
1098  **/
1099 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1100 {
1101         s32 status = 0;
1102         s32 i;
1103         u32 i2cctl;
1104         bool bit = 0;
1105
1106         for (i = 7; i >= 0; i--) {
1107                 bit = (data >> i) & 0x1;
1108                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1109
1110                 if (status != 0)
1111                         break;
1112         }
1113
1114         /* Release SDA line (set high) */
1115         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1116         i2cctl |= IXGBE_I2C_DATA_OUT;
1117         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1118
1119         return status;
1120 }
1121
1122 /**
1123  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1124  *  @hw: pointer to hardware structure
1125  *
1126  *  Clocks in/out one bit via I2C data/clock
1127  **/
1128 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1129 {
1130         s32 status;
1131         u32 i = 0;
1132         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1133         u32 timeout = 10;
1134         bool ack = 1;
1135
1136         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1137
1138         if (status != 0)
1139                 goto out;
1140
1141         /* Minimum high period of clock is 4us */
1142         udelay(IXGBE_I2C_T_HIGH);
1143
1144         /* Poll for ACK.  Note that ACK in I2C spec is
1145          * transition from 1 to 0 */
1146         for (i = 0; i < timeout; i++) {
1147                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1148                 ack = ixgbe_get_i2c_data(&i2cctl);
1149
1150                 udelay(1);
1151                 if (ack == 0)
1152                         break;
1153         }
1154
1155         if (ack == 1) {
1156                 hw_dbg(hw, "I2C ack was not received.\n");
1157                 status = IXGBE_ERR_I2C;
1158         }
1159
1160         ixgbe_lower_i2c_clk(hw, &i2cctl);
1161
1162         /* Minimum low period of clock is 4.7 us */
1163         udelay(IXGBE_I2C_T_LOW);
1164
1165 out:
1166         return status;
1167 }
1168
1169 /**
1170  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1171  *  @hw: pointer to hardware structure
1172  *  @data: read data value
1173  *
1174  *  Clocks in one bit via I2C data/clock
1175  **/
1176 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1177 {
1178         s32 status;
1179         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1180
1181         status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1182
1183         /* Minimum high period of clock is 4us */
1184         udelay(IXGBE_I2C_T_HIGH);
1185
1186         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1187         *data = ixgbe_get_i2c_data(&i2cctl);
1188
1189         ixgbe_lower_i2c_clk(hw, &i2cctl);
1190
1191         /* Minimum low period of clock is 4.7 us */
1192         udelay(IXGBE_I2C_T_LOW);
1193
1194         return status;
1195 }
1196
1197 /**
1198  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1199  *  @hw: pointer to hardware structure
1200  *  @data: data value to write
1201  *
1202  *  Clocks out one bit via I2C data/clock
1203  **/
1204 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1205 {
1206         s32 status;
1207         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1208
1209         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1210         if (status == 0) {
1211                 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1212
1213                 /* Minimum high period of clock is 4us */
1214                 udelay(IXGBE_I2C_T_HIGH);
1215
1216                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1217
1218                 /* Minimum low period of clock is 4.7 us.
1219                  * This also takes care of the data hold time.
1220                  */
1221                 udelay(IXGBE_I2C_T_LOW);
1222         } else {
1223                 status = IXGBE_ERR_I2C;
1224                 hw_dbg(hw, "I2C data was not set to %X\n", data);
1225         }
1226
1227         return status;
1228 }
1229 /**
1230  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1231  *  @hw: pointer to hardware structure
1232  *  @i2cctl: Current value of I2CCTL register
1233  *
1234  *  Raises the I2C clock line '0'->'1'
1235  **/
1236 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1237 {
1238         s32 status = 0;
1239
1240         *i2cctl |= IXGBE_I2C_CLK_OUT;
1241
1242         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1243
1244         /* SCL rise time (1000ns) */
1245         udelay(IXGBE_I2C_T_RISE);
1246
1247         return status;
1248 }
1249
1250 /**
1251  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1252  *  @hw: pointer to hardware structure
1253  *  @i2cctl: Current value of I2CCTL register
1254  *
1255  *  Lowers the I2C clock line '1'->'0'
1256  **/
1257 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1258 {
1259
1260         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1261
1262         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1263
1264         /* SCL fall time (300ns) */
1265         udelay(IXGBE_I2C_T_FALL);
1266 }
1267
1268 /**
1269  *  ixgbe_set_i2c_data - Sets the I2C data bit
1270  *  @hw: pointer to hardware structure
1271  *  @i2cctl: Current value of I2CCTL register
1272  *  @data: I2C data value (0 or 1) to set
1273  *
1274  *  Sets the I2C data bit
1275  **/
1276 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1277 {
1278         s32 status = 0;
1279
1280         if (data)
1281                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1282         else
1283                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1284
1285         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1286
1287         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1288         udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1289
1290         /* Verify data was set correctly */
1291         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1292         if (data != ixgbe_get_i2c_data(i2cctl)) {
1293                 status = IXGBE_ERR_I2C;
1294                 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1295         }
1296
1297         return status;
1298 }
1299
1300 /**
1301  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1302  *  @hw: pointer to hardware structure
1303  *  @i2cctl: Current value of I2CCTL register
1304  *
1305  *  Returns the I2C data bit value
1306  **/
1307 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1308 {
1309         bool data;
1310
1311         if (*i2cctl & IXGBE_I2C_DATA_IN)
1312                 data = 1;
1313         else
1314                 data = 0;
1315
1316         return data;
1317 }
1318
1319 /**
1320  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1321  *  @hw: pointer to hardware structure
1322  *
1323  *  Clears the I2C bus by sending nine clock pulses.
1324  *  Used when data line is stuck low.
1325  **/
1326 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1327 {
1328         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1329         u32 i;
1330
1331         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1332
1333         for (i = 0; i < 9; i++) {
1334                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1335
1336                 /* Min high period of clock is 4us */
1337                 udelay(IXGBE_I2C_T_HIGH);
1338
1339                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1340
1341                 /* Min low period of clock is 4.7us*/
1342                 udelay(IXGBE_I2C_T_LOW);
1343         }
1344
1345         /* Put the i2c bus back to default state */
1346         ixgbe_i2c_stop(hw);
1347 }
1348
1349 /**
1350  *  ixgbe_check_phy_link_tnx - Determine link and speed status
1351  *  @hw: pointer to hardware structure
1352  *
1353  *  Reads the VS1 register to determine if link is up and the current speed for
1354  *  the PHY.
1355  **/
1356 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1357                              bool *link_up)
1358 {
1359         s32 status = 0;
1360         u32 time_out;
1361         u32 max_time_out = 10;
1362         u16 phy_link = 0;
1363         u16 phy_speed = 0;
1364         u16 phy_data = 0;
1365
1366         /* Initialize speed and link to default case */
1367         *link_up = false;
1368         *speed = IXGBE_LINK_SPEED_10GB_FULL;
1369
1370         /*
1371          * Check current speed and link status of the PHY register.
1372          * This is a vendor specific register and may have to
1373          * be changed for other copper PHYs.
1374          */
1375         for (time_out = 0; time_out < max_time_out; time_out++) {
1376                 udelay(10);
1377                 status = hw->phy.ops.read_reg(hw,
1378                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1379                                         MDIO_MMD_VEND1,
1380                                         &phy_data);
1381                 phy_link = phy_data &
1382                            IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1383                 phy_speed = phy_data &
1384                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1385                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1386                         *link_up = true;
1387                         if (phy_speed ==
1388                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1389                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1390                         break;
1391                 }
1392         }
1393
1394         return status;
1395 }
1396
1397 /**
1398  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1399  *  @hw: pointer to hardware structure
1400  *  @firmware_version: pointer to the PHY Firmware Version
1401  **/
1402 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1403                                        u16 *firmware_version)
1404 {
1405         s32 status = 0;
1406
1407         status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1408                                       firmware_version);
1409
1410         return status;
1411 }
1412
1413 /**
1414  *  ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1415  *  @hw: pointer to hardware structure
1416  *
1417  *  Checks if the LASI temp alarm status was triggered due to overtemp
1418  **/
1419 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1420 {
1421         s32 status = 0;
1422         u16 phy_data = 0;
1423
1424         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1425                 goto out;
1426
1427         /* Check that the LASI temp alarm status was triggered */
1428         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1429                              MDIO_MMD_PMAPMD, &phy_data);
1430
1431         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1432                 goto out;
1433
1434         status = IXGBE_ERR_OVERTEMP;
1435 out:
1436         return status;
1437 }