drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         switch (adapter->hw.mac.type) {
 593         case ixgbe_mac_82598EB:
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596                 break;
 597         case ixgbe_mac_82599EB:
 598                 mask = (qmask & 0xFFFFFFFF);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 600                 mask = (qmask >> 32);
 601                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 602                 break;
 603         default:
 604                 break;
 605         }
 606 }
 607
 608 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 609                                       struct ixgbe_tx_buffer *tx_buffer_info)
 610 {
 611         if (tx_buffer_info->dma) {
 612                 if (tx_buffer_info->mapped_as_page)
 613                         dma_unmap_page(tx_ring->dev,
 614                                        tx_buffer_info->dma,
 615                                        tx_buffer_info->length,
 616                                        DMA_TO_DEVICE);
 617                 else
 618                         dma_unmap_single(tx_ring->dev,
 619                                          tx_buffer_info->dma,
 620                                          tx_buffer_info->length,
 621                                          DMA_TO_DEVICE);
 622                 tx_buffer_info->dma = 0;
 623         }
 624         if (tx_buffer_info->skb) {
 625                 dev_kfree_skb_any(tx_buffer_info->skb);
 626                 tx_buffer_info->skb = NULL;
 627         }
 628         tx_buffer_info->time_stamp = 0;
 629         /* tx_buffer_info must be completely set up in the transmit path */
 630 }
 631
 632 /**
 633  * ixgbe_tx_xon_state - check the tx ring xon state
 634  * @adapter: the ixgbe adapter
 635  * @tx_ring: the corresponding tx_ring
 636  *
 637  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 638  * corresponding TC of this tx_ring when checking TFCS.
 639  *
 640  * Returns : true if in xon state (currently not paused)
 641  */
 642 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 643                                       struct ixgbe_ring *tx_ring)
 644 {
 645         u32 txoff = IXGBE_TFCS_TXOFF;
 646
 647 #ifdef CONFIG_IXGBE_DCB
 648         if (adapter->dcb_cfg.pfc_mode_enable) {
 649                 int tc;
 650                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 651                 u8 reg_idx = tx_ring->reg_idx;
 652
 653                 switch (adapter->hw.mac.type) {
 654                 case ixgbe_mac_82598EB:
 655                         tc = reg_idx >> 2;
 656                         txoff = IXGBE_TFCS_TXOFF0;
 657                         break;
 658                 case ixgbe_mac_82599EB:
 659                         tc = 0;
 660                         txoff = IXGBE_TFCS_TXOFF;
 661                         if (dcb_i == 8) {
 662                                 /* TC0, TC1 */
 663                                 tc = reg_idx >> 5;
 664                                 if (tc == 2) /* TC2, TC3 */
 665                                         tc += (reg_idx - 64) >> 4;
 666                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 667                                         tc += 1 + ((reg_idx - 96) >> 3);
 668                         } else if (dcb_i == 4) {
 669                                 /* TC0, TC1 */
 670                                 tc = reg_idx >> 6;
 671                                 if (tc == 1) {
 672                                         tc += (reg_idx - 64) >> 5;
 673                                         if (tc == 2) /* TC2, TC3 */
 674                                                 tc += (reg_idx - 96) >> 4;
 675                                 }
 676                         }
 677                         break;
 678                 default:
 679                         tc = 0;
 680                         break;
 681                 }
 682                 txoff <<= tc;
 683         }
 684 #endif
 685         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 686 }
 687
 688 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 689                                        struct ixgbe_ring *tx_ring,
 690                                        unsigned int eop)
 691 {
 692         struct ixgbe_hw *hw = &adapter->hw;
 693
 694         /* Detect a transmit hang in hardware, this serializes the
 695          * check with the clearing of time_stamp and movement of eop */
 696         clear_check_for_tx_hang(tx_ring);
 697         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 698             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 699             ixgbe_tx_xon_state(adapter, tx_ring)) {
 700                 /* detected Tx unit hang */
 701                 union ixgbe_adv_tx_desc *tx_desc;
 702                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 703                 e_err(drv, "Detected Tx Unit Hang\n"
 704                       "  Tx Queue             <%d>\n"
 705                       "  TDH, TDT             <%x>, <%x>\n"
 706                       "  next_to_use          <%x>\n"
 707                       "  next_to_clean        <%x>\n"
 708                       "tx_buffer_info[next_to_clean]\n"
 709                       "  time_stamp           <%lx>\n"
 710                       "  jiffies              <%lx>\n",
 711                       tx_ring->queue_index,
 712                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 713                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 714                       tx_ring->next_to_use, eop,
 715                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 716                 return true;
 717         }
 718
 719         return false;
 720 }
 721
 722 #define IXGBE_MAX_TXD_PWR       14
 723 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 724
 725 /* Tx Descriptors needed, worst case */
 726 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 727                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 728 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 729         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 730
 731 static void ixgbe_tx_timeout(struct net_device *netdev);
 732
 733 /**
 734  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 735  * @q_vector: structure containing interrupt and ring information
 736  * @tx_ring: tx ring to clean
 737  **/
 738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 739                                struct ixgbe_ring *tx_ring)
 740 {
 741         struct ixgbe_adapter *adapter = q_vector->adapter;
 742         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 743         struct ixgbe_tx_buffer *tx_buffer_info;
 744         unsigned int total_bytes = 0, total_packets = 0;
 745         u16 i, eop, count = 0;
 746
 747         i = tx_ring->next_to_clean;
 748         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 749         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 750
 751         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 752                (count < tx_ring->work_limit)) {
 753                 bool cleaned = false;
 754                 rmb(); /* read buffer_info after eop_desc */
 755                 for ( ; !cleaned; count++) {
 756                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 757                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 758
 759                         tx_desc->wb.status = 0;
 760                         cleaned = (i == eop);
 761
 762                         i++;
 763                         if (i == tx_ring->count)
 764                                 i = 0;
 765
 766                         if (cleaned && tx_buffer_info->skb) {
 767                                 total_bytes += tx_buffer_info->bytecount;
 768                                 total_packets += tx_buffer_info->gso_segs;
 769                         }
 770
 771                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 772                                                          tx_buffer_info);
 773                 }
 774
 775                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 776                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 777         }
 778
 779         tx_ring->next_to_clean = i;
 780         tx_ring->total_bytes += total_bytes;
 781         tx_ring->total_packets += total_packets;
 782         u64_stats_update_begin(&tx_ring->syncp);
 783         tx_ring->stats.packets += total_packets;
 784         tx_ring->stats.bytes += total_bytes;
 785         u64_stats_update_end(&tx_ring->syncp);
 786
 787         if (check_for_tx_hang(tx_ring) &&
 788             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 789                 /* schedule immediate reset if we believe we hung */
 790                 e_info(probe, "tx hang %d detected, resetting "
 791                        "adapter\n", adapter->tx_timeout_count + 1);
 792                 ixgbe_tx_timeout(adapter->netdev);
 793
 794                 /* the adapter is about to reset, no point in enabling stuff */
 795                 return true;
 796         }
 797
 798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 799         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 800                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 801                 /* Make sure that anybody stopping the queue after this
 802                  * sees the new next_to_clean.
 803                  */
 804                 smp_mb();
 805                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 806                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 807                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 808                         ++tx_ring->tx_stats.restart_queue;
 809                 }
 810         }
 811
 812         return count < tx_ring->work_limit;
 813 }
 814
 815 #ifdef CONFIG_IXGBE_DCA
 816 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 817                                 struct ixgbe_ring *rx_ring,
 818                                 int cpu)
 819 {
 820         struct ixgbe_hw *hw = &adapter->hw;
 821         u32 rxctrl;
 822         u8 reg_idx = rx_ring->reg_idx;
 823
 824         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 825         switch (hw->mac.type) {
 826         case ixgbe_mac_82598EB:
 827                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 828                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 829                 break;
 830         case ixgbe_mac_82599EB:
 831                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 832                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 833                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 834                 break;
 835         default:
 836                 break;
 837         }
 838         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 839         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 840         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 841         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 842                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 843         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 844 }
 845
 846 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 847                                 struct ixgbe_ring *tx_ring,
 848                                 int cpu)
 849 {
 850         struct ixgbe_hw *hw = &adapter->hw;
 851         u32 txctrl;
 852         u8 reg_idx = tx_ring->reg_idx;
 853
 854         switch (hw->mac.type) {
 855         case ixgbe_mac_82598EB:
 856                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 857                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 858                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 859                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 860                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 861                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 862                 break;
 863         case ixgbe_mac_82599EB:
 864                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 865                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 866                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 867                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 868                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 869                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 870                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 871                 break;
 872         default:
 873                 break;
 874         }
 875 }
 876
 877 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 878 {
 879         struct ixgbe_adapter *adapter = q_vector->adapter;
 880         int cpu = get_cpu();
 881         long r_idx;
 882         int i;
 883
 884         if (q_vector->cpu == cpu)
 885                 goto out_no_update;
 886
 887         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 888         for (i = 0; i < q_vector->txr_count; i++) {
 889                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 890                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 891                                       r_idx + 1);
 892         }
 893
 894         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 895         for (i = 0; i < q_vector->rxr_count; i++) {
 896                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 897                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 898                                       r_idx + 1);
 899         }
 900
 901         q_vector->cpu = cpu;
 902 out_no_update:
 903         put_cpu();
 904 }
 905
 906 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 907 {
 908         int num_q_vectors;
 909         int i;
 910
 911         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 912                 return;
 913
 914         /* always use CB2 mode, difference is masked in the CB driver */
 915         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 916
 917         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 918                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 919         else
 920                 num_q_vectors = 1;
 921
 922         for (i = 0; i < num_q_vectors; i++) {
 923                 adapter->q_vector[i]->cpu = -1;
 924                 ixgbe_update_dca(adapter->q_vector[i]);
 925         }
 926 }
 927
 928 static int __ixgbe_notify_dca(struct device *dev, void *data)
 929 {
 930         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 931         unsigned long event = *(unsigned long *)data;
 932
 933         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 934                 return 0;
 935
 936         switch (event) {
 937         case DCA_PROVIDER_ADD:
 938                 /* if we're already enabled, don't do it again */
 939                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 940                         break;
 941                 if (dca_add_requester(dev) == 0) {
 942                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 943                         ixgbe_setup_dca(adapter);
 944                         break;
 945                 }
 946                 /* Fall Through since DCA is disabled. */
 947         case DCA_PROVIDER_REMOVE:
 948                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 949                         dca_remove_requester(dev);
 950                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 951                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 952                 }
 953                 break;
 954         }
 955
 956         return 0;
 957 }
 958
 959 #endif /* CONFIG_IXGBE_DCA */
 960 /**
 961  * ixgbe_receive_skb - Send a completed packet up the stack
 962  * @adapter: board private structure
 963  * @skb: packet to send up
 964  * @status: hardware indication of status of receive
 965  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 966  * @rx_desc: rx descriptor
 967  **/
 968 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 969                               struct sk_buff *skb, u8 status,
 970                               struct ixgbe_ring *ring,
 971                               union ixgbe_adv_rx_desc *rx_desc)
 972 {
 973         struct ixgbe_adapter *adapter = q_vector->adapter;
 974         struct napi_struct *napi = &q_vector->napi;
 975         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 976         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 977
 978         if (is_vlan && (tag & VLAN_VID_MASK))
 979                 __vlan_hwaccel_put_tag(skb, tag);
 980
 981         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 982                 napi_gro_receive(napi, skb);
 983         else
 984                 netif_rx(skb);
 985 }
 986
 987 /**
 988  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 989  * @adapter: address of board private structure
 990  * @status_err: hardware indication of status of receive
 991  * @skb: skb currently being received and modified
 992  **/
 993 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 994                                      union ixgbe_adv_rx_desc *rx_desc,
 995                                      struct sk_buff *skb)
 996 {
 997         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 998
 999         skb_checksum_none_assert(skb);
1000
1001         /* Rx csum disabled */
1002         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1003                 return;
1004
1005         /* if IP and error */
1006         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1007             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1008                 adapter->hw_csum_rx_error++;
1009                 return;
1010         }
1011
1012         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1013                 return;
1014
1015         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1016                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1017
1018                 /*
1019                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1020                  * checksum errors.
1021                  */
1022                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1023                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1024                         return;
1025
1026                 adapter->hw_csum_rx_error++;
1027                 return;
1028         }
1029
1030         /* It must be a TCP or UDP packet with a valid checksum */
1031         skb->ip_summed = CHECKSUM_UNNECESSARY;
1032 }
1033
1034 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1035 {
1036         /*
1037          * Force memory writes to complete before letting h/w
1038          * know there are new descriptors to fetch.  (Only
1039          * applicable for weak-ordered memory model archs,
1040          * such as IA-64).
1041          */
1042         wmb();
1043         writel(val, rx_ring->tail);
1044 }
1045
1046 /**
1047  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1048  * @rx_ring: ring to place buffers on
1049  * @cleaned_count: number of buffers to replace
1050  **/
1051 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1052 {
1053         union ixgbe_adv_rx_desc *rx_desc;
1054         struct ixgbe_rx_buffer *bi;
1055         struct sk_buff *skb;
1056         u16 i = rx_ring->next_to_use;
1057
1058         /* do nothing if no valid netdev defined */
1059         if (!rx_ring->netdev)
1060                 return;
1061
1062         while (cleaned_count--) {
1063                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1064                 bi = &rx_ring->rx_buffer_info[i];
1065                 skb = bi->skb;
1066
1067                 if (!skb) {
1068                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1069                                                         rx_ring->rx_buf_len);
1070                         if (!skb) {
1071                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1072                                 goto no_buffers;
1073                         }
1074                         /* initialize queue mapping */
1075                         skb_record_rx_queue(skb, rx_ring->queue_index);
1076                         bi->skb = skb;
1077                 }
1078
1079                 if (!bi->dma) {
1080                         bi->dma = dma_map_single(rx_ring->dev,
1081                                                  skb->data,
1082                                                  rx_ring->rx_buf_len,
1083                                                  DMA_FROM_DEVICE);
1084                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1085                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1086                                 bi->dma = 0;
1087                                 goto no_buffers;
1088                         }
1089                 }
1090
1091                 if (ring_is_ps_enabled(rx_ring)) {
1092                         if (!bi->page) {
1093                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1094                                 if (!bi->page) {
1095                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1096                                         goto no_buffers;
1097                                 }
1098                         }
1099
1100                         if (!bi->page_dma) {
1101                                 /* use a half page if we're re-using */
1102                                 bi->page_offset ^= PAGE_SIZE / 2;
1103                                 bi->page_dma = dma_map_page(rx_ring->dev,
1104                                                             bi->page,
1105                                                             bi->page_offset,
1106                                                             PAGE_SIZE / 2,
1107                                                             DMA_FROM_DEVICE);
1108                                 if (dma_mapping_error(rx_ring->dev,
1109                                                       bi->page_dma)) {
1110                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1111                                         bi->page_dma = 0;
1112                                         goto no_buffers;
1113                                 }
1114                         }
1115
1116                         /* Refresh the desc even if buffer_addrs didn't change
1117                          * because each write-back erases this info. */
1118                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1119                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1120                 } else {
1121                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1122                         rx_desc->read.hdr_addr = 0;
1123                 }
1124
1125                 i++;
1126                 if (i == rx_ring->count)
1127                         i = 0;
1128         }
1129
1130 no_buffers:
1131         if (rx_ring->next_to_use != i) {
1132                 rx_ring->next_to_use = i;
1133                 ixgbe_release_rx_desc(rx_ring, i);
1134         }
1135 }
1136
1137 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1138 {
1139         /* HW will not DMA in data larger than the given buffer, even if it
1140          * parses the (NFS, of course) header to be larger.  In that case, it
1141          * fills the header buffer and spills the rest into the page.
1142          */
1143         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1144         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1145                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1146         if (hlen > IXGBE_RX_HDR_SIZE)
1147                 hlen = IXGBE_RX_HDR_SIZE;
1148         return hlen;
1149 }
1150
1151 /**
1152  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1153  * @skb: pointer to the last skb in the rsc queue
1154  *
1155  * This function changes a queue full of hw rsc buffers into a completed
1156  * packet.  It uses the ->prev pointers to find the first packet and then
1157  * turns it into the frag list owner.
1158  **/
1159 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1160 {
1161         unsigned int frag_list_size = 0;
1162         unsigned int skb_cnt = 1;
1163
1164         while (skb->prev) {
1165                 struct sk_buff *prev = skb->prev;
1166                 frag_list_size += skb->len;
1167                 skb->prev = NULL;
1168                 skb = prev;
1169                 skb_cnt++;
1170         }
1171
1172         skb_shinfo(skb)->frag_list = skb->next;
1173         skb->next = NULL;
1174         skb->len += frag_list_size;
1175         skb->data_len += frag_list_size;
1176         skb->truesize += frag_list_size;
1177         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1178
1179         return skb;
1180 }
1181
1182 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1183 {
1184         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1185                 IXGBE_RXDADV_RSCCNT_MASK);
1186 }
1187
1188 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1189                                struct ixgbe_ring *rx_ring,
1190                                int *work_done, int work_to_do)
1191 {
1192         struct ixgbe_adapter *adapter = q_vector->adapter;
1193         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1194         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1195         struct sk_buff *skb;
1196         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197         const int current_node = numa_node_id();
1198 #ifdef IXGBE_FCOE
1199         int ddp_bytes = 0;
1200 #endif /* IXGBE_FCOE */
1201         u32 staterr;
1202         u16 i;
1203         u16 cleaned_count = 0;
1204         bool pkt_is_rsc = false;
1205
1206         i = rx_ring->next_to_clean;
1207         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1208         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1209
1210         while (staterr & IXGBE_RXD_STAT_DD) {
1211                 u32 upper_len = 0;
1212
1213                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1214
1215                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1216
1217                 skb = rx_buffer_info->skb;
1218                 rx_buffer_info->skb = NULL;
1219                 prefetch(skb->data);
1220
1221                 if (ring_is_rsc_enabled(rx_ring))
1222                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1223
1224                 /* if this is a skb from previous receive DMA will be 0 */
1225                 if (rx_buffer_info->dma) {
1226                         u16 hlen;
1227                         if (pkt_is_rsc &&
1228                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1229                             !skb->prev) {
1230                                 /*
1231                                  * When HWRSC is enabled, delay unmapping
1232                                  * of the first packet. It carries the
1233                                  * header information, HW may still
1234                                  * access the header after the writeback.
1235                                  * Only unmap it when EOP is reached
1236                                  */
1237                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1238                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1239                         } else {
1240                                 dma_unmap_single(rx_ring->dev,
1241                                                  rx_buffer_info->dma,
1242                                                  rx_ring->rx_buf_len,
1243                                                  DMA_FROM_DEVICE);
1244                         }
1245                         rx_buffer_info->dma = 0;
1246
1247                         if (ring_is_ps_enabled(rx_ring)) {
1248                                 hlen = ixgbe_get_hlen(rx_desc);
1249                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1250                         } else {
1251                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1252                         }
1253
1254                         skb_put(skb, hlen);
1255                 } else {
1256                         /* assume packet split since header is unmapped */
1257                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1258                 }
1259
1260                 if (upper_len) {
1261                         dma_unmap_page(rx_ring->dev,
1262                                        rx_buffer_info->page_dma,
1263                                        PAGE_SIZE / 2,
1264                                        DMA_FROM_DEVICE);
1265                         rx_buffer_info->page_dma = 0;
1266                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1267                                            rx_buffer_info->page,
1268                                            rx_buffer_info->page_offset,
1269                                            upper_len);
1270
1271                         if ((page_count(rx_buffer_info->page) == 1) &&
1272                             (page_to_nid(rx_buffer_info->page) == current_node))
1273                                 get_page(rx_buffer_info->page);
1274                         else
1275                                 rx_buffer_info->page = NULL;
1276
1277                         skb->len += upper_len;
1278                         skb->data_len += upper_len;
1279                         skb->truesize += upper_len;
1280                 }
1281
1282                 i++;
1283                 if (i == rx_ring->count)
1284                         i = 0;
1285
1286                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1287                 prefetch(next_rxd);
1288                 cleaned_count++;
1289
1290                 if (pkt_is_rsc) {
1291                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1292                                      IXGBE_RXDADV_NEXTP_SHIFT;
1293                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1294                 } else {
1295                         next_buffer = &rx_ring->rx_buffer_info[i];
1296                 }
1297
1298                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1299                         if (ring_is_ps_enabled(rx_ring)) {
1300                                 rx_buffer_info->skb = next_buffer->skb;
1301                                 rx_buffer_info->dma = next_buffer->dma;
1302                                 next_buffer->skb = skb;
1303                                 next_buffer->dma = 0;
1304                         } else {
1305                                 skb->next = next_buffer->skb;
1306                                 skb->next->prev = skb;
1307                         }
1308                         rx_ring->rx_stats.non_eop_descs++;
1309                         goto next_desc;
1310                 }
1311
1312                 if (skb->prev) {
1313                         skb = ixgbe_transform_rsc_queue(skb);
1314                         /* if we got here without RSC the packet is invalid */
1315                         if (!pkt_is_rsc) {
1316                                 __pskb_trim(skb, 0);
1317                                 rx_buffer_info->skb = skb;
1318                                 goto next_desc;
1319                         }
1320                 }
1321
1322                 if (ring_is_rsc_enabled(rx_ring)) {
1323                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1324                                 dma_unmap_single(rx_ring->dev,
1325                                                  IXGBE_RSC_CB(skb)->dma,
1326                                                  rx_ring->rx_buf_len,
1327                                                  DMA_FROM_DEVICE);
1328                                 IXGBE_RSC_CB(skb)->dma = 0;
1329                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1330                         }
1331                 }
1332                 if (pkt_is_rsc) {
1333                         if (ring_is_ps_enabled(rx_ring))
1334                                 rx_ring->rx_stats.rsc_count +=
1335                                         skb_shinfo(skb)->nr_frags;
1336                         else
1337                                 rx_ring->rx_stats.rsc_count +=
1338                                         IXGBE_RSC_CB(skb)->skb_cnt;
1339                         rx_ring->rx_stats.rsc_flush++;
1340                 }
1341
1342                 /* ERR_MASK will only have valid bits if EOP set */
1343                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1344                         /* trim packet back to size 0 and recycle it */
1345                         __pskb_trim(skb, 0);
1346                         rx_buffer_info->skb = skb;
1347                         goto next_desc;
1348                 }
1349
1350                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1351
1352                 /* probably a little skewed due to removing CRC */
1353                 total_rx_bytes += skb->len;
1354                 total_rx_packets++;
1355
1356                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1357 #ifdef IXGBE_FCOE
1358                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1359                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1360                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1361                         if (!ddp_bytes)
1362                                 goto next_desc;
1363                 }
1364 #endif /* IXGBE_FCOE */
1365                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1366
1367 next_desc:
1368                 rx_desc->wb.upper.status_error = 0;
1369
1370                 (*work_done)++;
1371                 if (*work_done >= work_to_do)
1372                         break;
1373
1374                 /* return some buffers to hardware, one at a time is too slow */
1375                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1376                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1377                         cleaned_count = 0;
1378                 }
1379
1380                 /* use prefetched values */
1381                 rx_desc = next_rxd;
1382                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1383         }
1384
1385         rx_ring->next_to_clean = i;
1386         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1387
1388         if (cleaned_count)
1389                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1390
1391 #ifdef IXGBE_FCOE
1392         /* include DDPed FCoE data */
1393         if (ddp_bytes > 0) {
1394                 unsigned int mss;
1395
1396                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1397                         sizeof(struct fc_frame_header) -
1398                         sizeof(struct fcoe_crc_eof);
1399                 if (mss > 512)
1400                         mss &= ~511;
1401                 total_rx_bytes += ddp_bytes;
1402                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1403         }
1404 #endif /* IXGBE_FCOE */
1405
1406         rx_ring->total_packets += total_rx_packets;
1407         rx_ring->total_bytes += total_rx_bytes;
1408         u64_stats_update_begin(&rx_ring->syncp);
1409         rx_ring->stats.packets += total_rx_packets;
1410         rx_ring->stats.bytes += total_rx_bytes;
1411         u64_stats_update_end(&rx_ring->syncp);
1412 }
1413
1414 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1415 /**
1416  * ixgbe_configure_msix - Configure MSI-X hardware
1417  * @adapter: board private structure
1418  *
1419  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1420  * interrupts.
1421  **/
1422 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1423 {
1424         struct ixgbe_q_vector *q_vector;
1425         int i, q_vectors, v_idx, r_idx;
1426         u32 mask;
1427
1428         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1429
1430         /*
1431          * Populate the IVAR table and set the ITR values to the
1432          * corresponding register.
1433          */
1434         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1435                 q_vector = adapter->q_vector[v_idx];
1436                 /* XXX for_each_set_bit(...) */
1437                 r_idx = find_first_bit(q_vector->rxr_idx,
1438                                        adapter->num_rx_queues);
1439
1440                 for (i = 0; i < q_vector->rxr_count; i++) {
1441                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1442                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1443                         r_idx = find_next_bit(q_vector->rxr_idx,
1444                                               adapter->num_rx_queues,
1445                                               r_idx + 1);
1446                 }
1447                 r_idx = find_first_bit(q_vector->txr_idx,
1448                                        adapter->num_tx_queues);
1449
1450                 for (i = 0; i < q_vector->txr_count; i++) {
1451                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1452                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1453                         r_idx = find_next_bit(q_vector->txr_idx,
1454                                               adapter->num_tx_queues,
1455                                               r_idx + 1);
1456                 }
1457
1458                 if (q_vector->txr_count && !q_vector->rxr_count)
1459                         /* tx only */
1460                         q_vector->eitr = adapter->tx_eitr_param;
1461                 else if (q_vector->rxr_count)
1462                         /* rx or mixed */
1463                         q_vector->eitr = adapter->rx_eitr_param;
1464
1465                 ixgbe_write_eitr(q_vector);
1466                 /* If Flow Director is enabled, set interrupt affinity */
1467                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1468                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1469                         /*
1470                          * Allocate the affinity_hint cpumask, assign the mask
1471                          * for this vector, and set our affinity_hint for
1472                          * this irq.
1473                          */
1474                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1475                                                GFP_KERNEL))
1476                                 return;
1477                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1478                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1479                                               q_vector->affinity_mask);
1480                 }
1481         }
1482
1483         switch (adapter->hw.mac.type) {
1484         case ixgbe_mac_82598EB:
1485                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1486                                v_idx);
1487                 break;
1488         case ixgbe_mac_82599EB:
1489                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1490                 break;
1491
1492         default:
1493                 break;
1494         }
1495         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1496
1497         /* set up to autoclear timer, and the vectors */
1498         mask = IXGBE_EIMS_ENABLE_MASK;
1499         if (adapter->num_vfs)
1500                 mask &= ~(IXGBE_EIMS_OTHER |
1501                           IXGBE_EIMS_MAILBOX |
1502                           IXGBE_EIMS_LSC);
1503         else
1504                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1505         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1506 }
1507
1508 enum latency_range {
1509         lowest_latency = 0,
1510         low_latency = 1,
1511         bulk_latency = 2,
1512         latency_invalid = 255
1513 };
1514
1515 /**
1516  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1517  * @adapter: pointer to adapter
1518  * @eitr: eitr setting (ints per sec) to give last timeslice
1519  * @itr_setting: current throttle rate in ints/second
1520  * @packets: the number of packets during this measurement interval
1521  * @bytes: the number of bytes during this measurement interval
1522  *
1523  *      Stores a new ITR value based on packets and byte
1524  *      counts during the last interrupt.  The advantage of per interrupt
1525  *      computation is faster updates and more accurate ITR for the current
1526  *      traffic pattern.  Constants in this function were computed
1527  *      based on theoretical maximum wire speed and thresholds were set based
1528  *      on testing data as well as attempting to minimize response time
1529  *      while increasing bulk throughput.
1530  *      this functionality is controlled by the InterruptThrottleRate module
1531  *      parameter (see ixgbe_param.c)
1532  **/
1533 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1534                            u32 eitr, u8 itr_setting,
1535                            int packets, int bytes)
1536 {
1537         unsigned int retval = itr_setting;
1538         u32 timepassed_us;
1539         u64 bytes_perint;
1540
1541         if (packets == 0)
1542                 goto update_itr_done;
1543
1544
1545         /* simple throttlerate management
1546          *    0-20MB/s lowest (100000 ints/s)
1547          *   20-100MB/s low   (20000 ints/s)
1548          *  100-1249MB/s bulk (8000 ints/s)
1549          */
1550         /* what was last interrupt timeslice? */
1551         timepassed_us = 1000000/eitr;
1552         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1553
1554         switch (itr_setting) {
1555         case lowest_latency:
1556                 if (bytes_perint > adapter->eitr_low)
1557                         retval = low_latency;
1558                 break;
1559         case low_latency:
1560                 if (bytes_perint > adapter->eitr_high)
1561                         retval = bulk_latency;
1562                 else if (bytes_perint <= adapter->eitr_low)
1563                         retval = lowest_latency;
1564                 break;
1565         case bulk_latency:
1566                 if (bytes_perint <= adapter->eitr_high)
1567                         retval = low_latency;
1568                 break;
1569         }
1570
1571 update_itr_done:
1572         return retval;
1573 }
1574
1575 /**
1576  * ixgbe_write_eitr - write EITR register in hardware specific way
1577  * @q_vector: structure containing interrupt and ring information
1578  *
1579  * This function is made to be called by ethtool and by the driver
1580  * when it needs to update EITR registers at runtime.  Hardware
1581  * specific quirks/differences are taken care of here.
1582  */
1583 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1584 {
1585         struct ixgbe_adapter *adapter = q_vector->adapter;
1586         struct ixgbe_hw *hw = &adapter->hw;
1587         int v_idx = q_vector->v_idx;
1588         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1589
1590         switch (adapter->hw.mac.type) {
1591         case ixgbe_mac_82598EB:
1592                 /* must write high and low 16 bits to reset counter */
1593                 itr_reg |= (itr_reg << 16);
1594                 break;
1595         case ixgbe_mac_82599EB:
1596                 /*
1597                  * 82599 can support a value of zero, so allow it for
1598                  * max interrupt rate, but there is an errata where it can
1599                  * not be zero with RSC
1600                  */
1601                 if (itr_reg == 8 &&
1602                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1603                         itr_reg = 0;
1604
1605                 /*
1606                  * set the WDIS bit to not clear the timer bits and cause an
1607                  * immediate assertion of the interrupt
1608                  */
1609                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1610                 break;
1611         default:
1612                 break;
1613         }
1614         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1615 }
1616
1617 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1618 {
1619         struct ixgbe_adapter *adapter = q_vector->adapter;
1620         u32 new_itr;
1621         u8 current_itr, ret_itr;
1622         int i, r_idx;
1623         struct ixgbe_ring *rx_ring, *tx_ring;
1624
1625         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1626         for (i = 0; i < q_vector->txr_count; i++) {
1627                 tx_ring = adapter->tx_ring[r_idx];
1628                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1629                                            q_vector->tx_itr,
1630                                            tx_ring->total_packets,
1631                                            tx_ring->total_bytes);
1632                 /* if the result for this queue would decrease interrupt
1633                  * rate for this vector then use that result */
1634                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1635                                     q_vector->tx_itr - 1 : ret_itr);
1636                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1637                                       r_idx + 1);
1638         }
1639
1640         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1641         for (i = 0; i < q_vector->rxr_count; i++) {
1642                 rx_ring = adapter->rx_ring[r_idx];
1643                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1644                                            q_vector->rx_itr,
1645                                            rx_ring->total_packets,
1646                                            rx_ring->total_bytes);
1647                 /* if the result for this queue would decrease interrupt
1648                  * rate for this vector then use that result */
1649                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1650                                     q_vector->rx_itr - 1 : ret_itr);
1651                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1652                                       r_idx + 1);
1653         }
1654
1655         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1656
1657         switch (current_itr) {
1658         /* counts and packets in update_itr are dependent on these numbers */
1659         case lowest_latency:
1660                 new_itr = 100000;
1661                 break;
1662         case low_latency:
1663                 new_itr = 20000; /* aka hwitr = ~200 */
1664                 break;
1665         case bulk_latency:
1666         default:
1667                 new_itr = 8000;
1668                 break;
1669         }
1670
1671         if (new_itr != q_vector->eitr) {
1672                 /* do an exponential smoothing */
1673                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1674
1675                 /* save the algorithm value here, not the smoothed one */
1676                 q_vector->eitr = new_itr;
1677
1678                 ixgbe_write_eitr(q_vector);
1679         }
1680 }
1681
1682 /**
1683  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1684  * @work: pointer to work_struct containing our data
1685  **/
1686 static void ixgbe_check_overtemp_task(struct work_struct *work)
1687 {
1688         struct ixgbe_adapter *adapter = container_of(work,
1689                                                      struct ixgbe_adapter,
1690                                                      check_overtemp_task);
1691         struct ixgbe_hw *hw = &adapter->hw;
1692         u32 eicr = adapter->interrupt_event;
1693
1694         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1695                 return;
1696
1697         switch (hw->device_id) {
1698         case IXGBE_DEV_ID_82599_T3_LOM: {
1699                 u32 autoneg;
1700                 bool link_up = false;
1701
1702                 if (hw->mac.ops.check_link)
1703                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1704
1705                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1706                     (eicr & IXGBE_EICR_LSC))
1707                         /* Check if this is due to overtemp */
1708                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1709                                 break;
1710                 return;
1711         }
1712         default:
1713                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1714                         return;
1715                 break;
1716         }
1717         e_crit(drv,
1718                "Network adapter has been stopped because it has over heated. "
1719                "Restart the computer. If the problem persists, "
1720                "power off the system and replace the adapter\n");
1721         /* write to clear the interrupt */
1722         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1723 }
1724
1725 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1726 {
1727         struct ixgbe_hw *hw = &adapter->hw;
1728
1729         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1730             (eicr & IXGBE_EICR_GPI_SDP1)) {
1731                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1732                 /* write to clear the interrupt */
1733                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1734         }
1735 }
1736
1737 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1738 {
1739         struct ixgbe_hw *hw = &adapter->hw;
1740
1741         if (eicr & IXGBE_EICR_GPI_SDP2) {
1742                 /* Clear the interrupt */
1743                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1744                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1745                         schedule_work(&adapter->sfp_config_module_task);
1746         }
1747
1748         if (eicr & IXGBE_EICR_GPI_SDP1) {
1749                 /* Clear the interrupt */
1750                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1751                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1752                         schedule_work(&adapter->multispeed_fiber_task);
1753         }
1754 }
1755
1756 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1757 {
1758         struct ixgbe_hw *hw = &adapter->hw;
1759
1760         adapter->lsc_int++;
1761         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1762         adapter->link_check_timeout = jiffies;
1763         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1764                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1765                 IXGBE_WRITE_FLUSH(hw);
1766                 schedule_work(&adapter->watchdog_task);
1767         }
1768 }
1769
1770 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1771 {
1772         struct net_device *netdev = data;
1773         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1774         struct ixgbe_hw *hw = &adapter->hw;
1775         u32 eicr;
1776
1777         /*
1778          * Workaround for Silicon errata.  Use clear-by-write instead
1779          * of clear-by-read.  Reading with EICS will return the
1780          * interrupt causes without clearing, which later be done
1781          * with the write to EICR.
1782          */
1783         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1784         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1785
1786         if (eicr & IXGBE_EICR_LSC)
1787                 ixgbe_check_lsc(adapter);
1788
1789         if (eicr & IXGBE_EICR_MAILBOX)
1790                 ixgbe_msg_task(adapter);
1791
1792         switch (hw->mac.type) {
1793         case ixgbe_mac_82599EB:
1794                 /* Handle Flow Director Full threshold interrupt */
1795                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1796                         int i;
1797                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1798                         /* Disable transmits before FDIR Re-initialization */
1799                         netif_tx_stop_all_queues(netdev);
1800                         for (i = 0; i < adapter->num_tx_queues; i++) {
1801                                 struct ixgbe_ring *tx_ring =
1802                                                             adapter->tx_ring[i];
1803                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1804                                                        &tx_ring->state))
1805                                         schedule_work(&adapter->fdir_reinit_task);
1806                         }
1807                 }
1808                 ixgbe_check_sfp_event(adapter, eicr);
1809                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1810                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1811                         adapter->interrupt_event = eicr;
1812                         schedule_work(&adapter->check_overtemp_task);
1813                 }
1814                 break;
1815         default:
1816                 break;
1817         }
1818
1819         ixgbe_check_fan_failure(adapter, eicr);
1820
1821         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1822                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1823
1824         return IRQ_HANDLED;
1825 }
1826
1827 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1828                                            u64 qmask)
1829 {
1830         u32 mask;
1831         struct ixgbe_hw *hw = &adapter->hw;
1832
1833         switch (hw->mac.type) {
1834         case ixgbe_mac_82598EB:
1835                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1836                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1837                 break;
1838         case ixgbe_mac_82599EB:
1839                 mask = (qmask & 0xFFFFFFFF);
1840                 if (mask)
1841                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1842                 mask = (qmask >> 32);
1843                 if (mask)
1844                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1845                 break;
1846         default:
1847                 break;
1848         }
1849         /* skip the flush */
1850 }
1851
1852 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1853                                             u64 qmask)
1854 {
1855         u32 mask;
1856         struct ixgbe_hw *hw = &adapter->hw;
1857
1858         switch (hw->mac.type) {
1859         case ixgbe_mac_82598EB:
1860                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1861                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1862                 break;
1863         case ixgbe_mac_82599EB:
1864                 mask = (qmask & 0xFFFFFFFF);
1865                 if (mask)
1866                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1867                 mask = (qmask >> 32);
1868                 if (mask)
1869                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1870                 break;
1871         default:
1872                 break;
1873         }
1874         /* skip the flush */
1875 }
1876
1877 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1878 {
1879         struct ixgbe_q_vector *q_vector = data;
1880         struct ixgbe_adapter  *adapter = q_vector->adapter;
1881         struct ixgbe_ring     *tx_ring;
1882         int i, r_idx;
1883
1884         if (!q_vector->txr_count)
1885                 return IRQ_HANDLED;
1886
1887         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1888         for (i = 0; i < q_vector->txr_count; i++) {
1889                 tx_ring = adapter->tx_ring[r_idx];
1890                 tx_ring->total_bytes = 0;
1891                 tx_ring->total_packets = 0;
1892                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1893                                       r_idx + 1);
1894         }
1895
1896         /* EIAM disabled interrupts (on this vector) for us */
1897         napi_schedule(&q_vector->napi);
1898
1899         return IRQ_HANDLED;
1900 }
1901
1902 /**
1903  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1904  * @irq: unused
1905  * @data: pointer to our q_vector struct for this interrupt vector
1906  **/
1907 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1908 {
1909         struct ixgbe_q_vector *q_vector = data;
1910         struct ixgbe_adapter  *adapter = q_vector->adapter;
1911         struct ixgbe_ring  *rx_ring;
1912         int r_idx;
1913         int i;
1914
1915 #ifdef CONFIG_IXGBE_DCA
1916         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1917                 ixgbe_update_dca(q_vector);
1918 #endif
1919
1920         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1921         for (i = 0; i < q_vector->rxr_count; i++) {
1922                 rx_ring = adapter->rx_ring[r_idx];
1923                 rx_ring->total_bytes = 0;
1924                 rx_ring->total_packets = 0;
1925                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1926                                       r_idx + 1);
1927         }
1928
1929         if (!q_vector->rxr_count)
1930                 return IRQ_HANDLED;
1931
1932         /* EIAM disabled interrupts (on this vector) for us */
1933         napi_schedule(&q_vector->napi);
1934
1935         return IRQ_HANDLED;
1936 }
1937
1938 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1939 {
1940         struct ixgbe_q_vector *q_vector = data;
1941         struct ixgbe_adapter  *adapter = q_vector->adapter;
1942         struct ixgbe_ring  *ring;
1943         int r_idx;
1944         int i;
1945
1946         if (!q_vector->txr_count && !q_vector->rxr_count)
1947                 return IRQ_HANDLED;
1948
1949         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1950         for (i = 0; i < q_vector->txr_count; i++) {
1951                 ring = adapter->tx_ring[r_idx];
1952                 ring->total_bytes = 0;
1953                 ring->total_packets = 0;
1954                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1955                                       r_idx + 1);
1956         }
1957
1958         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1959         for (i = 0; i < q_vector->rxr_count; i++) {
1960                 ring = adapter->rx_ring[r_idx];
1961                 ring->total_bytes = 0;
1962                 ring->total_packets = 0;
1963                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1964                                       r_idx + 1);
1965         }
1966
1967         /* EIAM disabled interrupts (on this vector) for us */
1968         napi_schedule(&q_vector->napi);
1969
1970         return IRQ_HANDLED;
1971 }
1972
1973 /**
1974  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1975  * @napi: napi struct with our devices info in it
1976  * @budget: amount of work driver is allowed to do this pass, in packets
1977  *
1978  * This function is optimized for cleaning one queue only on a single
1979  * q_vector!!!
1980  **/
1981 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1982 {
1983         struct ixgbe_q_vector *q_vector =
1984                                container_of(napi, struct ixgbe_q_vector, napi);
1985         struct ixgbe_adapter *adapter = q_vector->adapter;
1986         struct ixgbe_ring *rx_ring = NULL;
1987         int work_done = 0;
1988         long r_idx;
1989
1990 #ifdef CONFIG_IXGBE_DCA
1991         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1992                 ixgbe_update_dca(q_vector);
1993 #endif
1994
1995         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1996         rx_ring = adapter->rx_ring[r_idx];
1997
1998         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1999
2000         /* If all Rx work done, exit the polling mode */
2001         if (work_done < budget) {
2002                 napi_complete(napi);
2003                 if (adapter->rx_itr_setting & 1)
2004                         ixgbe_set_itr_msix(q_vector);
2005                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2006                         ixgbe_irq_enable_queues(adapter,
2007                                                 ((u64)1 << q_vector->v_idx));
2008         }
2009
2010         return work_done;
2011 }
2012
2013 /**
2014  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2015  * @napi: napi struct with our devices info in it
2016  * @budget: amount of work driver is allowed to do this pass, in packets
2017  *
2018  * This function will clean more than one rx queue associated with a
2019  * q_vector.
2020  **/
2021 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2022 {
2023         struct ixgbe_q_vector *q_vector =
2024                                container_of(napi, struct ixgbe_q_vector, napi);
2025         struct ixgbe_adapter *adapter = q_vector->adapter;
2026         struct ixgbe_ring *ring = NULL;
2027         int work_done = 0, i;
2028         long r_idx;
2029         bool tx_clean_complete = true;
2030
2031 #ifdef CONFIG_IXGBE_DCA
2032         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2033                 ixgbe_update_dca(q_vector);
2034 #endif
2035
2036         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2037         for (i = 0; i < q_vector->txr_count; i++) {
2038                 ring = adapter->tx_ring[r_idx];
2039                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2040                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2041                                       r_idx + 1);
2042         }
2043
2044         /* attempt to distribute budget to each queue fairly, but don't allow
2045          * the budget to go below 1 because we'll exit polling */
2046         budget /= (q_vector->rxr_count ?: 1);
2047         budget = max(budget, 1);
2048         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2049         for (i = 0; i < q_vector->rxr_count; i++) {
2050                 ring = adapter->rx_ring[r_idx];
2051                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2052                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2053                                       r_idx + 1);
2054         }
2055
2056         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2057         ring = adapter->rx_ring[r_idx];
2058         /* If all Rx work done, exit the polling mode */
2059         if (work_done < budget) {
2060                 napi_complete(napi);
2061                 if (adapter->rx_itr_setting & 1)
2062                         ixgbe_set_itr_msix(q_vector);
2063                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2064                         ixgbe_irq_enable_queues(adapter,
2065                                                 ((u64)1 << q_vector->v_idx));
2066                 return 0;
2067         }
2068
2069         return work_done;
2070 }
2071
2072 /**
2073  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2074  * @napi: napi struct with our devices info in it
2075  * @budget: amount of work driver is allowed to do this pass, in packets
2076  *
2077  * This function is optimized for cleaning one queue only on a single
2078  * q_vector!!!
2079  **/
2080 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2081 {
2082         struct ixgbe_q_vector *q_vector =
2083                                container_of(napi, struct ixgbe_q_vector, napi);
2084         struct ixgbe_adapter *adapter = q_vector->adapter;
2085         struct ixgbe_ring *tx_ring = NULL;
2086         int work_done = 0;
2087         long r_idx;
2088
2089 #ifdef CONFIG_IXGBE_DCA
2090         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2091                 ixgbe_update_dca(q_vector);
2092 #endif
2093
2094         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2095         tx_ring = adapter->tx_ring[r_idx];
2096
2097         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2098                 work_done = budget;
2099
2100         /* If all Tx work done, exit the polling mode */
2101         if (work_done < budget) {
2102                 napi_complete(napi);
2103                 if (adapter->tx_itr_setting & 1)
2104                         ixgbe_set_itr_msix(q_vector);
2105                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2106                         ixgbe_irq_enable_queues(adapter,
2107                                                 ((u64)1 << q_vector->v_idx));
2108         }
2109
2110         return work_done;
2111 }
2112
2113 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2114                                      int r_idx)
2115 {
2116         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2117
2118         set_bit(r_idx, q_vector->rxr_idx);
2119         q_vector->rxr_count++;
2120 }
2121
2122 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2123                                      int t_idx)
2124 {
2125         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2126
2127         set_bit(t_idx, q_vector->txr_idx);
2128         q_vector->txr_count++;
2129 }
2130
2131 /**
2132  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2133  * @adapter: board private structure to initialize
2134  * @vectors: allotted vector count for descriptor rings
2135  *
2136  * This function maps descriptor rings to the queue-specific vectors
2137  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2138  * one vector per ring/queue, but on a constrained vector budget, we
2139  * group the rings as "efficiently" as possible.  You would add new
2140  * mapping configurations in here.
2141  **/
2142 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2143                                       int vectors)
2144 {
2145         int v_start = 0;
2146         int rxr_idx = 0, txr_idx = 0;
2147         int rxr_remaining = adapter->num_rx_queues;
2148         int txr_remaining = adapter->num_tx_queues;
2149         int i, j;
2150         int rqpv, tqpv;
2151         int err = 0;
2152
2153         /* No mapping required if MSI-X is disabled. */
2154         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2155                 goto out;
2156
2157         /*
2158          * The ideal configuration...
2159          * We have enough vectors to map one per queue.
2160          */
2161         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2162                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2163                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2164
2165                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2166                         map_vector_to_txq(adapter, v_start, txr_idx);
2167
2168                 goto out;
2169         }
2170
2171         /*
2172          * If we don't have enough vectors for a 1-to-1
2173          * mapping, we'll have to group them so there are
2174          * multiple queues per vector.
2175          */
2176         /* Re-adjusting *qpv takes care of the remainder. */
2177         for (i = v_start; i < vectors; i++) {
2178                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2179                 for (j = 0; j < rqpv; j++) {
2180                         map_vector_to_rxq(adapter, i, rxr_idx);
2181                         rxr_idx++;
2182                         rxr_remaining--;
2183                 }
2184         }
2185         for (i = v_start; i < vectors; i++) {
2186                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2187                 for (j = 0; j < tqpv; j++) {
2188                         map_vector_to_txq(adapter, i, txr_idx);
2189                         txr_idx++;
2190                         txr_remaining--;
2191                 }
2192         }
2193
2194 out:
2195         return err;
2196 }
2197
2198 /**
2199  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2200  * @adapter: board private structure
2201  *
2202  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2203  * interrupts from the kernel.
2204  **/
2205 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2206 {
2207         struct net_device *netdev = adapter->netdev;
2208         irqreturn_t (*handler)(int, void *);
2209         int i, vector, q_vectors, err;
2210         int ri = 0, ti = 0;
2211
2212         /* Decrement for Other and TCP Timer vectors */
2213         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2214
2215         /* Map the Tx/Rx rings to the vectors we were allotted. */
2216         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2217         if (err)
2218                 goto out;
2219
2220 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2221                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2222                          &ixgbe_msix_clean_many)
2223         for (vector = 0; vector < q_vectors; vector++) {
2224                 handler = SET_HANDLER(adapter->q_vector[vector]);
2225
2226                 if (handler == &ixgbe_msix_clean_rx) {
2227                         sprintf(adapter->name[vector], "%s-%s-%d",
2228                                 netdev->name, "rx", ri++);
2229                 } else if (handler == &ixgbe_msix_clean_tx) {
2230                         sprintf(adapter->name[vector], "%s-%s-%d",
2231                                 netdev->name, "tx", ti++);
2232                 } else {
2233                         sprintf(adapter->name[vector], "%s-%s-%d",
2234                                 netdev->name, "TxRx", ri++);
2235                         ti++;
2236                 }
2237
2238                 err = request_irq(adapter->msix_entries[vector].vector,
2239                                   handler, 0, adapter->name[vector],
2240                                   adapter->q_vector[vector]);
2241                 if (err) {
2242                         e_err(probe, "request_irq failed for MSIX interrupt "
2243                               "Error: %d\n", err);
2244                         goto free_queue_irqs;
2245                 }
2246         }
2247
2248         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2249         err = request_irq(adapter->msix_entries[vector].vector,
2250                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2251         if (err) {
2252                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2253                 goto free_queue_irqs;
2254         }
2255
2256         return 0;
2257
2258 free_queue_irqs:
2259         for (i = vector - 1; i >= 0; i--)
2260                 free_irq(adapter->msix_entries[--vector].vector,
2261                          adapter->q_vector[i]);
2262         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2263         pci_disable_msix(adapter->pdev);
2264         kfree(adapter->msix_entries);
2265         adapter->msix_entries = NULL;
2266 out:
2267         return err;
2268 }
2269
2270 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2271 {
2272         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2273         u8 current_itr;
2274         u32 new_itr = q_vector->eitr;
2275         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2276         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2277
2278         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2279                                             q_vector->tx_itr,
2280                                             tx_ring->total_packets,
2281                                             tx_ring->total_bytes);
2282         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2283                                             q_vector->rx_itr,
2284                                             rx_ring->total_packets,
2285                                             rx_ring->total_bytes);
2286
2287         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2288
2289         switch (current_itr) {
2290         /* counts and packets in update_itr are dependent on these numbers */
2291         case lowest_latency:
2292                 new_itr = 100000;
2293                 break;
2294         case low_latency:
2295                 new_itr = 20000; /* aka hwitr = ~200 */
2296                 break;
2297         case bulk_latency:
2298                 new_itr = 8000;
2299                 break;
2300         default:
2301                 break;
2302         }
2303
2304         if (new_itr != q_vector->eitr) {
2305                 /* do an exponential smoothing */
2306                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2307
2308                 /* save the algorithm value here, not the smoothed one */
2309                 q_vector->eitr = new_itr;
2310
2311                 ixgbe_write_eitr(q_vector);
2312         }
2313 }
2314
2315 /**
2316  * ixgbe_irq_enable - Enable default interrupt generation settings
2317  * @adapter: board private structure
2318  **/
2319 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2320                                     bool flush)
2321 {
2322         u32 mask;
2323
2324         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2325         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2326                 mask |= IXGBE_EIMS_GPI_SDP0;
2327         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2328                 mask |= IXGBE_EIMS_GPI_SDP1;
2329         switch (adapter->hw.mac.type) {
2330         case ixgbe_mac_82599EB:
2331                 mask |= IXGBE_EIMS_ECC;
2332                 mask |= IXGBE_EIMS_GPI_SDP1;
2333                 mask |= IXGBE_EIMS_GPI_SDP2;
2334                 if (adapter->num_vfs)
2335                         mask |= IXGBE_EIMS_MAILBOX;
2336                 break;
2337         default:
2338                 break;
2339         }
2340         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2341             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2342                 mask |= IXGBE_EIMS_FLOW_DIR;
2343
2344         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2345         if (queues)
2346                 ixgbe_irq_enable_queues(adapter, ~0);
2347         if (flush)
2348                 IXGBE_WRITE_FLUSH(&adapter->hw);
2349
2350         if (adapter->num_vfs > 32) {
2351                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2352                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2353         }
2354 }
2355
2356 /**
2357  * ixgbe_intr - legacy mode Interrupt Handler
2358  * @irq: interrupt number
2359  * @data: pointer to a network interface device structure
2360  **/
2361 static irqreturn_t ixgbe_intr(int irq, void *data)
2362 {
2363         struct net_device *netdev = data;
2364         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2365         struct ixgbe_hw *hw = &adapter->hw;
2366         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2367         u32 eicr;
2368
2369         /*
2370          * Workaround for silicon errata on 82598.  Mask the interrupts
2371          * before the read of EICR.
2372          */
2373         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2374
2375         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2376          * therefore no explict interrupt disable is necessary */
2377         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2378         if (!eicr) {
2379                 /*
2380                  * shared interrupt alert!
2381                  * make sure interrupts are enabled because the read will
2382                  * have disabled interrupts due to EIAM
2383                  * finish the workaround of silicon errata on 82598.  Unmask
2384                  * the interrupt that we masked before the EICR read.
2385                  */
2386                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2387                         ixgbe_irq_enable(adapter, true, true);
2388                 return IRQ_NONE;        /* Not our interrupt */
2389         }
2390
2391         if (eicr & IXGBE_EICR_LSC)
2392                 ixgbe_check_lsc(adapter);
2393
2394         switch (hw->mac.type) {
2395         case ixgbe_mac_82599EB:
2396                 ixgbe_check_sfp_event(adapter, eicr);
2397                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2398                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2399                         adapter->interrupt_event = eicr;
2400                         schedule_work(&adapter->check_overtemp_task);
2401                 }
2402                 break;
2403         default:
2404                 break;
2405         }
2406
2407         ixgbe_check_fan_failure(adapter, eicr);
2408
2409         if (napi_schedule_prep(&(q_vector->napi))) {
2410                 adapter->tx_ring[0]->total_packets = 0;
2411                 adapter->tx_ring[0]->total_bytes = 0;
2412                 adapter->rx_ring[0]->total_packets = 0;
2413                 adapter->rx_ring[0]->total_bytes = 0;
2414                 /* would disable interrupts here but EIAM disabled it */
2415                 __napi_schedule(&(q_vector->napi));
2416         }
2417
2418         /*
2419          * re-enable link(maybe) and non-queue interrupts, no flush.
2420          * ixgbe_poll will re-enable the queue interrupts
2421          */
2422
2423         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2424                 ixgbe_irq_enable(adapter, false, false);
2425
2426         return IRQ_HANDLED;
2427 }
2428
2429 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2430 {
2431         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2432
2433         for (i = 0; i < q_vectors; i++) {
2434                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2435                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2436                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2437                 q_vector->rxr_count = 0;
2438                 q_vector->txr_count = 0;
2439         }
2440 }
2441
2442 /**
2443  * ixgbe_request_irq - initialize interrupts
2444  * @adapter: board private structure
2445  *
2446  * Attempts to configure interrupts using the best available
2447  * capabilities of the hardware and kernel.
2448  **/
2449 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2450 {
2451         struct net_device *netdev = adapter->netdev;
2452         int err;
2453
2454         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2455                 err = ixgbe_request_msix_irqs(adapter);
2456         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2457                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2458                                   netdev->name, netdev);
2459         } else {
2460                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2461                                   netdev->name, netdev);
2462         }
2463
2464         if (err)
2465                 e_err(probe, "request_irq failed, Error %d\n", err);
2466
2467         return err;
2468 }
2469
2470 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2471 {
2472         struct net_device *netdev = adapter->netdev;
2473
2474         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2475                 int i, q_vectors;
2476
2477                 q_vectors = adapter->num_msix_vectors;
2478
2479                 i = q_vectors - 1;
2480                 free_irq(adapter->msix_entries[i].vector, netdev);
2481
2482                 i--;
2483                 for (; i >= 0; i--) {
2484                         free_irq(adapter->msix_entries[i].vector,
2485                                  adapter->q_vector[i]);
2486                 }
2487
2488                 ixgbe_reset_q_vectors(adapter);
2489         } else {
2490                 free_irq(adapter->pdev->irq, netdev);
2491         }
2492 }
2493
2494 /**
2495  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2496  * @adapter: board private structure
2497  **/
2498 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2499 {
2500         switch (adapter->hw.mac.type) {
2501         case ixgbe_mac_82598EB:
2502                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2503                 break;
2504         case ixgbe_mac_82599EB:
2505                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2506                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2507                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2508                 if (adapter->num_vfs > 32)
2509                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2510                 break;
2511         default:
2512                 break;
2513         }
2514         IXGBE_WRITE_FLUSH(&adapter->hw);
2515         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2516                 int i;
2517                 for (i = 0; i < adapter->num_msix_vectors; i++)
2518                         synchronize_irq(adapter->msix_entries[i].vector);
2519         } else {
2520                 synchronize_irq(adapter->pdev->irq);
2521         }
2522 }
2523
2524 /**
2525  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2526  *
2527  **/
2528 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2529 {
2530         struct ixgbe_hw *hw = &adapter->hw;
2531
2532         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2533                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2534
2535         ixgbe_set_ivar(adapter, 0, 0, 0);
2536         ixgbe_set_ivar(adapter, 1, 0, 0);
2537
2538         map_vector_to_rxq(adapter, 0, 0);
2539         map_vector_to_txq(adapter, 0, 0);
2540
2541         e_info(hw, "Legacy interrupt IVAR setup done\n");
2542 }
2543
2544 /**
2545  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2546  * @adapter: board private structure
2547  * @ring: structure containing ring specific data
2548  *
2549  * Configure the Tx descriptor ring after a reset.
2550  **/
2551 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2552                              struct ixgbe_ring *ring)
2553 {
2554         struct ixgbe_hw *hw = &adapter->hw;
2555         u64 tdba = ring->dma;
2556         int wait_loop = 10;
2557         u32 txdctl;
2558         u8 reg_idx = ring->reg_idx;
2559
2560         /* disable queue to avoid issues while updating state */
2561         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2562         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2563                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2564         IXGBE_WRITE_FLUSH(hw);
2565
2566         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2567                         (tdba & DMA_BIT_MASK(32)));
2568         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2569         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2570                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2571         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2572         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2573         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2574
2575         /* configure fetching thresholds */
2576         if (adapter->rx_itr_setting == 0) {
2577                 /* cannot set wthresh when itr==0 */
2578                 txdctl &= ~0x007F0000;
2579         } else {
2580                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2581                 txdctl |= (8 << 16);
2582         }
2583         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2584                 /* PThresh workaround for Tx hang with DFP enabled. */
2585                 txdctl |= 32;
2586         }
2587
2588         /* reinitialize flowdirector state */
2589         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2590             adapter->atr_sample_rate) {
2591                 ring->atr_sample_rate = adapter->atr_sample_rate;
2592                 ring->atr_count = 0;
2593                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2594         } else {
2595                 ring->atr_sample_rate = 0;
2596         }
2597
2598         /* enable queue */
2599         txdctl |= IXGBE_TXDCTL_ENABLE;
2600         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2601
2602         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2603         if (hw->mac.type == ixgbe_mac_82598EB &&
2604             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2605                 return;
2606
2607         /* poll to verify queue is enabled */
2608         do {
2609                 msleep(1);
2610                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2611         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2612         if (!wait_loop)
2613                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2614 }
2615
2616 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2617 {
2618         struct ixgbe_hw *hw = &adapter->hw;
2619         u32 rttdcs;
2620         u32 mask;
2621
2622         if (hw->mac.type == ixgbe_mac_82598EB)
2623                 return;
2624
2625         /* disable the arbiter while setting MTQC */
2626         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2627         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2628         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2629
2630         /* set transmit pool layout */
2631         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2632         switch (adapter->flags & mask) {
2633
2634         case (IXGBE_FLAG_SRIOV_ENABLED):
2635                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2636                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2637                 break;
2638
2639         case (IXGBE_FLAG_DCB_ENABLED):
2640                 /* We enable 8 traffic classes, DCB only */
2641                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2642                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2643                 break;
2644
2645         default:
2646                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2647                 break;
2648         }
2649
2650         /* re-enable the arbiter */
2651         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2652         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2653 }
2654
2655 /**
2656  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2657  * @adapter: board private structure
2658  *
2659  * Configure the Tx unit of the MAC after a reset.
2660  **/
2661 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2662 {
2663         struct ixgbe_hw *hw = &adapter->hw;
2664         u32 dmatxctl;
2665         u32 i;
2666
2667         ixgbe_setup_mtqc(adapter);
2668
2669         if (hw->mac.type != ixgbe_mac_82598EB) {
2670                 /* DMATXCTL.EN must be before Tx queues are enabled */
2671                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2672                 dmatxctl |= IXGBE_DMATXCTL_TE;
2673                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2674         }
2675
2676         /* Setup the HW Tx Head and Tail descriptor pointers */
2677         for (i = 0; i < adapter->num_tx_queues; i++)
2678                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2679 }
2680
2681 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2682
2683 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2684                                    struct ixgbe_ring *rx_ring)
2685 {
2686         u32 srrctl;
2687         u8 reg_idx = rx_ring->reg_idx;
2688
2689         switch (adapter->hw.mac.type) {
2690         case ixgbe_mac_82598EB: {
2691                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2692                 const int mask = feature[RING_F_RSS].mask;
2693                 reg_idx = reg_idx & mask;
2694         }
2695                 break;
2696         case ixgbe_mac_82599EB:
2697         default:
2698                 break;
2699         }
2700
2701         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2702
2703         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2704         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2705         if (adapter->num_vfs)
2706                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2707
2708         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2709                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2710
2711         if (ring_is_ps_enabled(rx_ring)) {
2712 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2713                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2714 #else
2715                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2716 #endif
2717                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2718         } else {
2719                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2720                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2721                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2722         }
2723
2724         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2725 }
2726
2727 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2728 {
2729         struct ixgbe_hw *hw = &adapter->hw;
2730         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2731                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2732                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2733         u32 mrqc = 0, reta = 0;
2734         u32 rxcsum;
2735         int i, j;
2736         int mask;
2737
2738         /* Fill out hash function seeds */
2739         for (i = 0; i < 10; i++)
2740                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2741
2742         /* Fill out redirection table */
2743         for (i = 0, j = 0; i < 128; i++, j++) {
2744                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2745                         j = 0;
2746                 /* reta = 4-byte sliding window of
2747                  * 0x00..(indices-1)(indices-1)00..etc. */
2748                 reta = (reta << 8) | (j * 0x11);
2749                 if ((i & 3) == 3)
2750                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2751         }
2752
2753         /* Disable indicating checksum in descriptor, enables RSS hash */
2754         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2755         rxcsum |= IXGBE_RXCSUM_PCSD;
2756         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2757
2758         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2759                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2760         else
2761                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2762 #ifdef CONFIG_IXGBE_DCB
2763                                          | IXGBE_FLAG_DCB_ENABLED
2764 #endif
2765                                          | IXGBE_FLAG_SRIOV_ENABLED
2766                                         );
2767
2768         switch (mask) {
2769         case (IXGBE_FLAG_RSS_ENABLED):
2770                 mrqc = IXGBE_MRQC_RSSEN;
2771                 break;
2772         case (IXGBE_FLAG_SRIOV_ENABLED):
2773                 mrqc = IXGBE_MRQC_VMDQEN;
2774                 break;
2775 #ifdef CONFIG_IXGBE_DCB
2776         case (IXGBE_FLAG_DCB_ENABLED):
2777                 mrqc = IXGBE_MRQC_RT8TCEN;
2778                 break;
2779 #endif /* CONFIG_IXGBE_DCB */
2780         default:
2781                 break;
2782         }
2783
2784         /* Perform hash on these packet types */
2785         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2786               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2787               | IXGBE_MRQC_RSS_FIELD_IPV6
2788               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2789
2790         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2791 }
2792
2793 /**
2794  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2795  * @adapter:    address of board private structure
2796  * @index:      index of ring to set
2797  **/
2798 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2799                                    struct ixgbe_ring *ring)
2800 {
2801         struct ixgbe_hw *hw = &adapter->hw;
2802         u32 rscctrl;
2803         int rx_buf_len;
2804         u8 reg_idx = ring->reg_idx;
2805
2806         if (!ring_is_rsc_enabled(ring))
2807                 return;
2808
2809         rx_buf_len = ring->rx_buf_len;
2810         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2811         rscctrl |= IXGBE_RSCCTL_RSCEN;
2812         /*
2813          * we must limit the number of descriptors so that the
2814          * total size of max desc * buf_len is not greater
2815          * than 65535
2816          */
2817         if (ring_is_ps_enabled(ring)) {
2818 #if (MAX_SKB_FRAGS > 16)
2819                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2820 #elif (MAX_SKB_FRAGS > 8)
2821                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2822 #elif (MAX_SKB_FRAGS > 4)
2823                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2824 #else
2825                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2826 #endif
2827         } else {
2828                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2829                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2830                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2831                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2832                 else
2833                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2834         }
2835         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2836 }
2837
2838 /**
2839  *  ixgbe_set_uta - Set unicast filter table address
2840  *  @adapter: board private structure
2841  *
2842  *  The unicast table address is a register array of 32-bit registers.
2843  *  The table is meant to be used in a way similar to how the MTA is used
2844  *  however due to certain limitations in the hardware it is necessary to
2845  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2846  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2847  **/
2848 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2849 {
2850         struct ixgbe_hw *hw = &adapter->hw;
2851         int i;
2852
2853         /* The UTA table only exists on 82599 hardware and newer */
2854         if (hw->mac.type < ixgbe_mac_82599EB)
2855                 return;
2856
2857         /* we only need to do this if VMDq is enabled */
2858         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2859                 return;
2860
2861         for (i = 0; i < 128; i++)
2862                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2863 }
2864
2865 #define IXGBE_MAX_RX_DESC_POLL 10
2866 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2867                                        struct ixgbe_ring *ring)
2868 {
2869         struct ixgbe_hw *hw = &adapter->hw;
2870         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2871         u32 rxdctl;
2872         u8 reg_idx = ring->reg_idx;
2873
2874         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2875         if (hw->mac.type == ixgbe_mac_82598EB &&
2876             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2877                 return;
2878
2879         do {
2880                 msleep(1);
2881                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2882         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2883
2884         if (!wait_loop) {
2885                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2886                       "the polling period\n", reg_idx);
2887         }
2888 }
2889
2890 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2891                              struct ixgbe_ring *ring)
2892 {
2893         struct ixgbe_hw *hw = &adapter->hw;
2894         u64 rdba = ring->dma;
2895         u32 rxdctl;
2896         u8 reg_idx = ring->reg_idx;
2897
2898         /* disable queue to avoid issues while updating state */
2899         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2900         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2901                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2902         IXGBE_WRITE_FLUSH(hw);
2903
2904         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2905         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2906         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2907                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2908         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2909         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2910         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2911
2912         ixgbe_configure_srrctl(adapter, ring);
2913         ixgbe_configure_rscctl(adapter, ring);
2914
2915         if (hw->mac.type == ixgbe_mac_82598EB) {
2916                 /*
2917                  * enable cache line friendly hardware writes:
2918                  * PTHRESH=32 descriptors (half the internal cache),
2919                  * this also removes ugly rx_no_buffer_count increment
2920                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2921                  * WTHRESH=8 burst writeback up to two cache lines
2922                  */
2923                 rxdctl &= ~0x3FFFFF;
2924                 rxdctl |=  0x080420;
2925         }
2926
2927         /* enable receive descriptor ring */
2928         rxdctl |= IXGBE_RXDCTL_ENABLE;
2929         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2930
2931         ixgbe_rx_desc_queue_enable(adapter, ring);
2932         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2933 }
2934
2935 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2936 {
2937         struct ixgbe_hw *hw = &adapter->hw;
2938         int p;
2939
2940         /* PSRTYPE must be initialized in non 82598 adapters */
2941         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2942                       IXGBE_PSRTYPE_UDPHDR |
2943                       IXGBE_PSRTYPE_IPV4HDR |
2944                       IXGBE_PSRTYPE_L2HDR |
2945                       IXGBE_PSRTYPE_IPV6HDR;
2946
2947         if (hw->mac.type == ixgbe_mac_82598EB)
2948                 return;
2949
2950         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2951                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2952
2953         for (p = 0; p < adapter->num_rx_pools; p++)
2954                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2955                                 psrtype);
2956 }
2957
2958 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2959 {
2960         struct ixgbe_hw *hw = &adapter->hw;
2961         u32 gcr_ext;
2962         u32 vt_reg_bits;
2963         u32 reg_offset, vf_shift;
2964         u32 vmdctl;
2965
2966         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2967                 return;
2968
2969         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2970         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2971         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2972         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2973
2974         vf_shift = adapter->num_vfs % 32;
2975         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2976
2977         /* Enable only the PF's pool for Tx/Rx */
2978         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2979         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2980         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2981         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2982         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2983
2984         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2985         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2986
2987         /*
2988          * Set up VF register offsets for selected VT Mode,
2989          * i.e. 32 or 64 VFs for SR-IOV
2990          */
2991         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2992         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2993         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2994         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2995
2996         /* enable Tx loopback for VF/PF communication */
2997         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2998 }
2999
3000 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3001 {
3002         struct ixgbe_hw *hw = &adapter->hw;
3003         struct net_device *netdev = adapter->netdev;
3004         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3005         int rx_buf_len;
3006         struct ixgbe_ring *rx_ring;
3007         int i;
3008         u32 mhadd, hlreg0;
3009
3010         /* Decide whether to use packet split mode or not */
3011         /* Do not use packet split if we're in SR-IOV Mode */
3012         if (!adapter->num_vfs)
3013                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3014
3015         /* Set the RX buffer length according to the mode */
3016         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3017                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3018         } else {
3019                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3020                     (netdev->mtu <= ETH_DATA_LEN))
3021                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3022                 else
3023                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3024         }
3025
3026 #ifdef IXGBE_FCOE
3027         /* adjust max frame to be able to do baby jumbo for FCoE */
3028         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3029             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3030                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3031
3032 #endif /* IXGBE_FCOE */
3033         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3034         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3035                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3036                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3037
3038                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3039         }
3040
3041         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3042         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3043         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3044         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3045
3046         /*
3047          * Setup the HW Rx Head and Tail Descriptor Pointers and
3048          * the Base and Length of the Rx Descriptor Ring
3049          */
3050         for (i = 0; i < adapter->num_rx_queues; i++) {
3051                 rx_ring = adapter->rx_ring[i];
3052                 rx_ring->rx_buf_len = rx_buf_len;
3053
3054                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3055                         set_ring_ps_enabled(rx_ring);
3056                 else
3057                         clear_ring_ps_enabled(rx_ring);
3058
3059                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3060                         set_ring_rsc_enabled(rx_ring);
3061                 else
3062                         clear_ring_rsc_enabled(rx_ring);
3063
3064 #ifdef IXGBE_FCOE
3065                 if (netdev->features & NETIF_F_FCOE_MTU) {
3066                         struct ixgbe_ring_feature *f;
3067                         f = &adapter->ring_feature[RING_F_FCOE];
3068                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3069                                 clear_ring_ps_enabled(rx_ring);
3070                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3071                                         rx_ring->rx_buf_len =
3072                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3073                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3074                                    !ring_is_ps_enabled(rx_ring)) {
3075                                 rx_ring->rx_buf_len =
3076                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3077                         }
3078                 }
3079 #endif /* IXGBE_FCOE */
3080         }
3081 }
3082
3083 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3084 {
3085         struct ixgbe_hw *hw = &adapter->hw;
3086         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3087
3088         switch (hw->mac.type) {
3089         case ixgbe_mac_82598EB:
3090                 /*
3091                  * For VMDq support of different descriptor types or
3092                  * buffer sizes through the use of multiple SRRCTL
3093                  * registers, RDRXCTL.MVMEN must be set to 1
3094                  *
3095                  * also, the manual doesn't mention it clearly but DCA hints
3096                  * will only use queue 0's tags unless this bit is set.  Side
3097                  * effects of setting this bit are only that SRRCTL must be
3098                  * fully programmed [0..15]
3099                  */
3100                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3101                 break;
3102         case ixgbe_mac_82599EB:
3103                 /* Disable RSC for ACK packets */
3104                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3105                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3106                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3107                 /* hardware requires some bits to be set by default */
3108                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3109                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3110                 break;
3111         default:
3112                 /* We should do nothing since we don't know this hardware */
3113                 return;
3114         }
3115
3116         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3117 }
3118
3119 /**
3120  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3121  * @adapter: board private structure
3122  *
3123  * Configure the Rx unit of the MAC after a reset.
3124  **/
3125 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3126 {
3127         struct ixgbe_hw *hw = &adapter->hw;
3128         int i;
3129         u32 rxctrl;
3130
3131         /* disable receives while setting up the descriptors */
3132         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3133         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3134
3135         ixgbe_setup_psrtype(adapter);
3136         ixgbe_setup_rdrxctl(adapter);
3137
3138         /* Program registers for the distribution of queues */
3139         ixgbe_setup_mrqc(adapter);
3140
3141         ixgbe_set_uta(adapter);
3142
3143         /* set_rx_buffer_len must be called before ring initialization */
3144         ixgbe_set_rx_buffer_len(adapter);
3145
3146         /*
3147          * Setup the HW Rx Head and Tail Descriptor Pointers and
3148          * the Base and Length of the Rx Descriptor Ring
3149          */
3150         for (i = 0; i < adapter->num_rx_queues; i++)
3151                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3152
3153         /* disable drop enable for 82598 parts */
3154         if (hw->mac.type == ixgbe_mac_82598EB)
3155                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3156
3157         /* enable all receives */
3158         rxctrl |= IXGBE_RXCTRL_RXEN;
3159         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3160 }
3161
3162 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3163 {
3164         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3165         struct ixgbe_hw *hw = &adapter->hw;
3166         int pool_ndx = adapter->num_vfs;
3167
3168         /* add VID to filter table */
3169         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3170         set_bit(vid, adapter->active_vlans);
3171 }
3172
3173 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3174 {
3175         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3176         struct ixgbe_hw *hw = &adapter->hw;
3177         int pool_ndx = adapter->num_vfs;
3178
3179         /* remove VID from filter table */
3180         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3181         clear_bit(vid, adapter->active_vlans);
3182 }
3183
3184 /**
3185  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3186  * @adapter: driver data
3187  */
3188 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3189 {
3190         struct ixgbe_hw *hw = &adapter->hw;
3191         u32 vlnctrl;
3192
3193         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3194         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3195         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3196 }
3197
3198 /**
3199  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3200  * @adapter: driver data
3201  */
3202 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3203 {
3204         struct ixgbe_hw *hw = &adapter->hw;
3205         u32 vlnctrl;
3206
3207         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3208         vlnctrl |= IXGBE_VLNCTRL_VFE;
3209         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3210         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3211 }
3212
3213 /**
3214  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3215  * @adapter: driver data
3216  */
3217 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3218 {
3219         struct ixgbe_hw *hw = &adapter->hw;
3220         u32 vlnctrl;
3221         int i, j;
3222
3223         switch (hw->mac.type) {
3224         case ixgbe_mac_82598EB:
3225                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3226                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3227                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3228                 break;
3229         case ixgbe_mac_82599EB:
3230                 for (i = 0; i < adapter->num_rx_queues; i++) {
3231                         j = adapter->rx_ring[i]->reg_idx;
3232                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3233                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3234                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3235                 }
3236                 break;
3237         default:
3238                 break;
3239         }
3240 }
3241
3242 /**
3243  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3244  * @adapter: driver data
3245  */
3246 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3247 {
3248         struct ixgbe_hw *hw = &adapter->hw;
3249         u32 vlnctrl;
3250         int i, j;
3251
3252         switch (hw->mac.type) {
3253         case ixgbe_mac_82598EB:
3254                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3255                 vlnctrl |= IXGBE_VLNCTRL_VME;
3256                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3257                 break;
3258         case ixgbe_mac_82599EB:
3259                 for (i = 0; i < adapter->num_rx_queues; i++) {
3260                         j = adapter->rx_ring[i]->reg_idx;
3261                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3262                         vlnctrl |= IXGBE_RXDCTL_VME;
3263                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3264                 }
3265                 break;
3266         default:
3267                 break;
3268         }
3269 }
3270
3271 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3272 {
3273         u16 vid;
3274
3275         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3276
3277         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3278                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3279 }
3280
3281 /**
3282  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3283  * @netdev: network interface device structure
3284  *
3285  * Writes unicast address list to the RAR table.
3286  * Returns: -ENOMEM on failure/insufficient address space
3287  *                0 on no addresses written
3288  *                X on writing X addresses to the RAR table
3289  **/
3290 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3291 {
3292         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3293         struct ixgbe_hw *hw = &adapter->hw;
3294         unsigned int vfn = adapter->num_vfs;
3295         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3296         int count = 0;
3297
3298         /* return ENOMEM indicating insufficient memory for addresses */
3299         if (netdev_uc_count(netdev) > rar_entries)
3300                 return -ENOMEM;
3301
3302         if (!netdev_uc_empty(netdev) && rar_entries) {
3303                 struct netdev_hw_addr *ha;
3304                 /* return error if we do not support writing to RAR table */
3305                 if (!hw->mac.ops.set_rar)
3306                         return -ENOMEM;
3307
3308                 netdev_for_each_uc_addr(ha, netdev) {
3309                         if (!rar_entries)
3310                                 break;
3311                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3312                                             vfn, IXGBE_RAH_AV);
3313                         count++;
3314                 }
3315         }
3316         /* write the addresses in reverse order to avoid write combining */
3317         for (; rar_entries > 0 ; rar_entries--)
3318                 hw->mac.ops.clear_rar(hw, rar_entries);
3319
3320         return count;
3321 }
3322
3323 /**
3324  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3325  * @netdev: network interface device structure
3326  *
3327  * The set_rx_method entry point is called whenever the unicast/multicast
3328  * address list or the network interface flags are updated.  This routine is
3329  * responsible for configuring the hardware for proper unicast, multicast and
3330  * promiscuous mode.
3331  **/
3332 void ixgbe_set_rx_mode(struct net_device *netdev)
3333 {
3334         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3335         struct ixgbe_hw *hw = &adapter->hw;
3336         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3337         int count;
3338
3339         /* Check for Promiscuous and All Multicast modes */
3340
3341         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3342
3343         /* set all bits that we expect to always be set */
3344         fctrl |= IXGBE_FCTRL_BAM;
3345         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3346         fctrl |= IXGBE_FCTRL_PMCF;
3347
3348         /* clear the bits we are changing the status of */
3349         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3350
3351         if (netdev->flags & IFF_PROMISC) {
3352                 hw->addr_ctrl.user_set_promisc = true;
3353                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3354                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3355                 /* don't hardware filter vlans in promisc mode */
3356                 ixgbe_vlan_filter_disable(adapter);
3357         } else {
3358                 if (netdev->flags & IFF_ALLMULTI) {
3359                         fctrl |= IXGBE_FCTRL_MPE;
3360                         vmolr |= IXGBE_VMOLR_MPE;
3361                 } else {
3362                         /*
3363                          * Write addresses to the MTA, if the attempt fails
3364                          * then we should just turn on promiscous mode so
3365                          * that we can at least receive multicast traffic
3366                          */
3367                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3368                         vmolr |= IXGBE_VMOLR_ROMPE;
3369                 }
3370                 ixgbe_vlan_filter_enable(adapter);
3371                 hw->addr_ctrl.user_set_promisc = false;
3372                 /*
3373                  * Write addresses to available RAR registers, if there is not
3374                  * sufficient space to store all the addresses then enable
3375                  * unicast promiscous mode
3376                  */
3377                 count = ixgbe_write_uc_addr_list(netdev);
3378                 if (count < 0) {
3379                         fctrl |= IXGBE_FCTRL_UPE;
3380                         vmolr |= IXGBE_VMOLR_ROPE;
3381                 }
3382         }
3383
3384         if (adapter->num_vfs) {
3385                 ixgbe_restore_vf_multicasts(adapter);
3386                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3387                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3388                            IXGBE_VMOLR_ROPE);
3389                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3390         }
3391
3392         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3393
3394         if (netdev->features & NETIF_F_HW_VLAN_RX)
3395                 ixgbe_vlan_strip_enable(adapter);
3396         else
3397                 ixgbe_vlan_strip_disable(adapter);
3398 }
3399
3400 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3401 {
3402         int q_idx;
3403         struct ixgbe_q_vector *q_vector;
3404         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3405
3406         /* legacy and MSI only use one vector */
3407         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3408                 q_vectors = 1;
3409
3410         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3411                 struct napi_struct *napi;
3412                 q_vector = adapter->q_vector[q_idx];
3413                 napi = &q_vector->napi;
3414                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3415                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3416                                 if (q_vector->txr_count == 1)
3417                                         napi->poll = &ixgbe_clean_txonly;
3418                                 else if (q_vector->rxr_count == 1)
3419                                         napi->poll = &ixgbe_clean_rxonly;
3420                         }
3421                 }
3422
3423                 napi_enable(napi);
3424         }
3425 }
3426
3427 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3428 {
3429         int q_idx;
3430         struct ixgbe_q_vector *q_vector;
3431         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3432
3433         /* legacy and MSI only use one vector */
3434         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3435                 q_vectors = 1;
3436
3437         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3438                 q_vector = adapter->q_vector[q_idx];
3439                 napi_disable(&q_vector->napi);
3440         }
3441 }
3442
3443 #ifdef CONFIG_IXGBE_DCB
3444 /*
3445  * ixgbe_configure_dcb - Configure DCB hardware
3446  * @adapter: ixgbe adapter struct
3447  *
3448  * This is called by the driver on open to configure the DCB hardware.
3449  * This is also called by the gennetlink interface when reconfiguring
3450  * the DCB state.
3451  */
3452 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3453 {
3454         struct ixgbe_hw *hw = &adapter->hw;
3455         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3456
3457         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3458                 if (hw->mac.type == ixgbe_mac_82598EB)
3459                         netif_set_gso_max_size(adapter->netdev, 65536);
3460                 return;
3461         }
3462
3463         if (hw->mac.type == ixgbe_mac_82598EB)
3464                 netif_set_gso_max_size(adapter->netdev, 32768);
3465
3466 #ifdef CONFIG_FCOE
3467         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3468                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3469 #endif
3470
3471         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3472                                         DCB_TX_CONFIG);
3473         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3474                                         DCB_RX_CONFIG);
3475
3476         /* Enable VLAN tag insert/strip */
3477         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3478
3479         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3480
3481         /* reconfigure the hardware */
3482         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3483 }
3484
3485 #endif
3486 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3487 {
3488         struct net_device *netdev = adapter->netdev;
3489         struct ixgbe_hw *hw = &adapter->hw;
3490         int i;
3491
3492 #ifdef CONFIG_IXGBE_DCB
3493         ixgbe_configure_dcb(adapter);
3494 #endif
3495
3496         ixgbe_set_rx_mode(netdev);
3497         ixgbe_restore_vlan(adapter);
3498
3499 #ifdef IXGBE_FCOE
3500         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3501                 ixgbe_configure_fcoe(adapter);
3502
3503 #endif /* IXGBE_FCOE */
3504         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3505                 for (i = 0; i < adapter->num_tx_queues; i++)
3506                         adapter->tx_ring[i]->atr_sample_rate =
3507                                                        adapter->atr_sample_rate;
3508                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3509         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3510                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3511         }
3512         ixgbe_configure_virtualization(adapter);
3513
3514         ixgbe_configure_tx(adapter);
3515         ixgbe_configure_rx(adapter);
3516 }
3517
3518 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3519 {
3520         switch (hw->phy.type) {
3521         case ixgbe_phy_sfp_avago:
3522         case ixgbe_phy_sfp_ftl:
3523         case ixgbe_phy_sfp_intel:
3524         case ixgbe_phy_sfp_unknown:
3525         case ixgbe_phy_sfp_passive_tyco:
3526         case ixgbe_phy_sfp_passive_unknown:
3527         case ixgbe_phy_sfp_active_unknown:
3528         case ixgbe_phy_sfp_ftl_active:
3529                 return true;
3530         default:
3531                 return false;
3532         }
3533 }
3534
3535 /**
3536  * ixgbe_sfp_link_config - set up SFP+ link
3537  * @adapter: pointer to private adapter struct
3538  **/
3539 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3540 {
3541         struct ixgbe_hw *hw = &adapter->hw;
3542
3543                 if (hw->phy.multispeed_fiber) {
3544                         /*
3545                          * In multispeed fiber setups, the device may not have
3546                          * had a physical connection when the driver loaded.
3547                          * If that's the case, the initial link configuration
3548                          * couldn't get the MAC into 10G or 1G mode, so we'll
3549                          * never have a link status change interrupt fire.
3550                          * We need to try and force an autonegotiation
3551                          * session, then bring up link.
3552                          */
3553                         hw->mac.ops.setup_sfp(hw);
3554                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3555                                 schedule_work(&adapter->multispeed_fiber_task);
3556                 } else {
3557                         /*
3558                          * Direct Attach Cu and non-multispeed fiber modules
3559                          * still need to be configured properly prior to
3560                          * attempting link.
3561                          */
3562                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3563                                 schedule_work(&adapter->sfp_config_module_task);
3564                 }
3565 }
3566
3567 /**
3568  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3569  * @hw: pointer to private hardware struct
3570  *
3571  * Returns 0 on success, negative on failure
3572  **/
3573 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3574 {
3575         u32 autoneg;
3576         bool negotiation, link_up = false;
3577         u32 ret = IXGBE_ERR_LINK_SETUP;
3578
3579         if (hw->mac.ops.check_link)
3580                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3581
3582         if (ret)
3583                 goto link_cfg_out;
3584
3585         if (hw->mac.ops.get_link_capabilities)
3586                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3587                                                         &negotiation);
3588         if (ret)
3589                 goto link_cfg_out;
3590
3591         if (hw->mac.ops.setup_link)
3592                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3593 link_cfg_out:
3594         return ret;
3595 }
3596
3597 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3598 {
3599         struct ixgbe_hw *hw = &adapter->hw;
3600         u32 gpie = 0;
3601
3602         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3603                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3604                        IXGBE_GPIE_OCD;
3605                 gpie |= IXGBE_GPIE_EIAME;
3606                 /*
3607                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3608                  * this saves a register write for every interrupt
3609                  */
3610                 switch (hw->mac.type) {
3611                 case ixgbe_mac_82598EB:
3612                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3613                         break;
3614                 default:
3615                 case ixgbe_mac_82599EB:
3616                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3617                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3618                         break;
3619                 }
3620         } else {
3621                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3622                  * specifically only auto mask tx and rx interrupts */
3623                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3624         }
3625
3626         /* XXX: to interrupt immediately for EICS writes, enable this */
3627         /* gpie |= IXGBE_GPIE_EIMEN; */
3628
3629         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3630                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3631                 gpie |= IXGBE_GPIE_VTMODE_64;
3632         }
3633
3634         /* Enable fan failure interrupt */
3635         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3636                 gpie |= IXGBE_SDP1_GPIEN;
3637
3638         if (hw->mac.type == ixgbe_mac_82599EB)
3639                 gpie |= IXGBE_SDP1_GPIEN;
3640                 gpie |= IXGBE_SDP2_GPIEN;
3641
3642         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3643 }
3644
3645 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3646 {
3647         struct ixgbe_hw *hw = &adapter->hw;
3648         int err;
3649         u32 ctrl_ext;
3650
3651         ixgbe_get_hw_control(adapter);
3652         ixgbe_setup_gpie(adapter);
3653
3654         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3655                 ixgbe_configure_msix(adapter);
3656         else
3657                 ixgbe_configure_msi_and_legacy(adapter);
3658
3659         /* enable the optics */
3660         if (hw->phy.multispeed_fiber)
3661                 hw->mac.ops.enable_tx_laser(hw);
3662
3663         clear_bit(__IXGBE_DOWN, &adapter->state);
3664         ixgbe_napi_enable_all(adapter);
3665
3666         if (ixgbe_is_sfp(hw)) {
3667                 ixgbe_sfp_link_config(adapter);
3668         } else {
3669                 err = ixgbe_non_sfp_link_config(hw);
3670                 if (err)
3671                         e_err(probe, "link_config FAILED %d\n", err);
3672         }
3673
3674         /* clear any pending interrupts, may auto mask */
3675         IXGBE_READ_REG(hw, IXGBE_EICR);
3676         ixgbe_irq_enable(adapter, true, true);
3677
3678         /*
3679          * If this adapter has a fan, check to see if we had a failure
3680          * before we enabled the interrupt.
3681          */
3682         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3683                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3684                 if (esdp & IXGBE_ESDP_SDP1)
3685                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3686         }
3687
3688         /*
3689          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3690          * arrived before interrupts were enabled but after probe.  Such
3691          * devices wouldn't have their type identified yet. We need to
3692          * kick off the SFP+ module setup first, then try to bring up link.
3693          * If we're not hot-pluggable SFP+, we just need to configure link
3694          * and bring it up.
3695          */
3696         if (hw->phy.type == ixgbe_phy_unknown)
3697                 schedule_work(&adapter->sfp_config_module_task);
3698
3699         /* enable transmits */
3700         netif_tx_start_all_queues(adapter->netdev);
3701
3702         /* bring the link up in the watchdog, this could race with our first
3703          * link up interrupt but shouldn't be a problem */
3704         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3705         adapter->link_check_timeout = jiffies;
3706         mod_timer(&adapter->watchdog_timer, jiffies);
3707
3708         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3709         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3710         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3711         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3712
3713         return 0;
3714 }
3715
3716 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3717 {
3718         WARN_ON(in_interrupt());
3719         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3720                 msleep(1);
3721         ixgbe_down(adapter);
3722         /*
3723          * If SR-IOV enabled then wait a bit before bringing the adapter
3724          * back up to give the VFs time to respond to the reset.  The
3725          * two second wait is based upon the watchdog timer cycle in
3726          * the VF driver.
3727          */
3728         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3729                 msleep(2000);
3730         ixgbe_up(adapter);
3731         clear_bit(__IXGBE_RESETTING, &adapter->state);
3732 }
3733
3734 int ixgbe_up(struct ixgbe_adapter *adapter)
3735 {
3736         /* hardware has been reset, we need to reload some things */
3737         ixgbe_configure(adapter);
3738
3739         return ixgbe_up_complete(adapter);
3740 }
3741
3742 void ixgbe_reset(struct ixgbe_adapter *adapter)
3743 {
3744         struct ixgbe_hw *hw = &adapter->hw;
3745         int err;
3746
3747         err = hw->mac.ops.init_hw(hw);
3748         switch (err) {
3749         case 0:
3750         case IXGBE_ERR_SFP_NOT_PRESENT:
3751                 break;
3752         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3753                 e_dev_err("master disable timed out\n");
3754                 break;
3755         case IXGBE_ERR_EEPROM_VERSION:
3756                 /* We are running on a pre-production device, log a warning */
3757                 e_dev_warn("This device is a pre-production adapter/LOM. "
3758                            "Please be aware there may be issuesassociated with "
3759                            "your hardware.  If you are experiencing problems "
3760                            "please contact your Intel or hardware "
3761                            "representative who provided you with this "
3762                            "hardware.\n");
3763                 break;
3764         default:
3765                 e_dev_err("Hardware Error: %d\n", err);
3766         }
3767
3768         /* reprogram the RAR[0] in case user changed it. */
3769         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3770                             IXGBE_RAH_AV);
3771 }
3772
3773 /**
3774  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3775  * @rx_ring: ring to free buffers from
3776  **/
3777 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3778 {
3779         struct device *dev = rx_ring->dev;
3780         unsigned long size;
3781         u16 i;
3782
3783         /* ring already cleared, nothing to do */
3784         if (!rx_ring->rx_buffer_info)
3785                 return;
3786
3787         /* Free all the Rx ring sk_buffs */
3788         for (i = 0; i < rx_ring->count; i++) {
3789                 struct ixgbe_rx_buffer *rx_buffer_info;
3790
3791                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3792                 if (rx_buffer_info->dma) {
3793                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3794                                          rx_ring->rx_buf_len,
3795                                          DMA_FROM_DEVICE);
3796                         rx_buffer_info->dma = 0;
3797                 }
3798                 if (rx_buffer_info->skb) {
3799                         struct sk_buff *skb = rx_buffer_info->skb;
3800                         rx_buffer_info->skb = NULL;
3801                         do {
3802                                 struct sk_buff *this = skb;
3803                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3804                                         dma_unmap_single(dev,
3805                                                          IXGBE_RSC_CB(this)->dma,
3806                                                          rx_ring->rx_buf_len,
3807                                                          DMA_FROM_DEVICE);
3808                                         IXGBE_RSC_CB(this)->dma = 0;
3809                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3810                                 }
3811                                 skb = skb->prev;
3812                                 dev_kfree_skb(this);
3813                         } while (skb);
3814                 }
3815                 if (!rx_buffer_info->page)
3816                         continue;
3817                 if (rx_buffer_info->page_dma) {
3818                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3819                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3820                         rx_buffer_info->page_dma = 0;
3821                 }
3822                 put_page(rx_buffer_info->page);
3823                 rx_buffer_info->page = NULL;
3824                 rx_buffer_info->page_offset = 0;
3825         }
3826
3827         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3828         memset(rx_ring->rx_buffer_info, 0, size);
3829
3830         /* Zero out the descriptor ring */
3831         memset(rx_ring->desc, 0, rx_ring->size);
3832
3833         rx_ring->next_to_clean = 0;
3834         rx_ring->next_to_use = 0;
3835 }
3836
3837 /**
3838  * ixgbe_clean_tx_ring - Free Tx Buffers
3839  * @tx_ring: ring to be cleaned
3840  **/
3841 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3842 {
3843         struct ixgbe_tx_buffer *tx_buffer_info;
3844         unsigned long size;
3845         u16 i;
3846
3847         /* ring already cleared, nothing to do */
3848         if (!tx_ring->tx_buffer_info)
3849                 return;
3850
3851         /* Free all the Tx ring sk_buffs */
3852         for (i = 0; i < tx_ring->count; i++) {
3853                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3854                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3855         }
3856
3857         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3858         memset(tx_ring->tx_buffer_info, 0, size);
3859
3860         /* Zero out the descriptor ring */
3861         memset(tx_ring->desc, 0, tx_ring->size);
3862
3863         tx_ring->next_to_use = 0;
3864         tx_ring->next_to_clean = 0;
3865 }
3866
3867 /**
3868  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3869  * @adapter: board private structure
3870  **/
3871 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3872 {
3873         int i;
3874
3875         for (i = 0; i < adapter->num_rx_queues; i++)
3876                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3877 }
3878
3879 /**
3880  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3881  * @adapter: board private structure
3882  **/
3883 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3884 {
3885         int i;
3886
3887         for (i = 0; i < adapter->num_tx_queues; i++)
3888                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3889 }
3890
3891 void ixgbe_down(struct ixgbe_adapter *adapter)
3892 {
3893         struct net_device *netdev = adapter->netdev;
3894         struct ixgbe_hw *hw = &adapter->hw;
3895         u32 rxctrl;
3896         u32 txdctl;
3897         int i;
3898         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3899
3900         /* signal that we are down to the interrupt handler */
3901         set_bit(__IXGBE_DOWN, &adapter->state);
3902
3903         /* disable receive for all VFs and wait one second */
3904         if (adapter->num_vfs) {
3905                 /* ping all the active vfs to let them know we are going down */
3906                 ixgbe_ping_all_vfs(adapter);
3907
3908                 /* Disable all VFTE/VFRE TX/RX */
3909                 ixgbe_disable_tx_rx(adapter);
3910
3911                 /* Mark all the VFs as inactive */
3912                 for (i = 0 ; i < adapter->num_vfs; i++)
3913                         adapter->vfinfo[i].clear_to_send = 0;
3914         }
3915
3916         /* disable receives */
3917         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3918         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3919
3920         IXGBE_WRITE_FLUSH(hw);
3921         msleep(10);
3922
3923         netif_tx_stop_all_queues(netdev);
3924
3925         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3926         del_timer_sync(&adapter->sfp_timer);
3927         del_timer_sync(&adapter->watchdog_timer);
3928         cancel_work_sync(&adapter->watchdog_task);
3929
3930         netif_carrier_off(netdev);
3931         netif_tx_disable(netdev);
3932
3933         ixgbe_irq_disable(adapter);
3934
3935         ixgbe_napi_disable_all(adapter);
3936
3937         /* Cleanup the affinity_hint CPU mask memory and callback */
3938         for (i = 0; i < num_q_vectors; i++) {
3939                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3940                 /* clear the affinity_mask in the IRQ descriptor */
3941                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3942                 /* release the CPU mask memory */
3943                 free_cpumask_var(q_vector->affinity_mask);
3944         }
3945
3946         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3947             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3948                 cancel_work_sync(&adapter->fdir_reinit_task);
3949
3950         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3951                 cancel_work_sync(&adapter->check_overtemp_task);
3952
3953         /* disable transmits in the hardware now that interrupts are off */
3954         for (i = 0; i < adapter->num_tx_queues; i++) {
3955                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3956                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3957                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
3958                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3959         }
3960         /* Disable the Tx DMA engine on 82599 */
3961         switch (hw->mac.type) {
3962         case ixgbe_mac_82599EB:
3963                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3964                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3965                                  ~IXGBE_DMATXCTL_TE));
3966                 break;
3967         default:
3968                 break;
3969         }
3970
3971         /* power down the optics */
3972         if (hw->phy.multispeed_fiber)
3973                 hw->mac.ops.disable_tx_laser(hw);
3974
3975         /* clear n-tuple filters that are cached */
3976         ethtool_ntuple_flush(netdev);
3977
3978         if (!pci_channel_offline(adapter->pdev))
3979                 ixgbe_reset(adapter);
3980         ixgbe_clean_all_tx_rings(adapter);
3981         ixgbe_clean_all_rx_rings(adapter);
3982
3983 #ifdef CONFIG_IXGBE_DCA
3984         /* since we reset the hardware DCA settings were cleared */
3985         ixgbe_setup_dca(adapter);
3986 #endif
3987 }
3988
3989 /**
3990  * ixgbe_poll - NAPI Rx polling callback
3991  * @napi: structure for representing this polling device
3992  * @budget: how many packets driver is allowed to clean
3993  *
3994  * This function is used for legacy and MSI, NAPI mode
3995  **/
3996 static int ixgbe_poll(struct napi_struct *napi, int budget)
3997 {
3998         struct ixgbe_q_vector *q_vector =
3999                                 container_of(napi, struct ixgbe_q_vector, napi);
4000         struct ixgbe_adapter *adapter = q_vector->adapter;
4001         int tx_clean_complete, work_done = 0;
4002
4003 #ifdef CONFIG_IXGBE_DCA
4004         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4005                 ixgbe_update_dca(q_vector);
4006 #endif
4007
4008         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4009         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4010
4011         if (!tx_clean_complete)
4012                 work_done = budget;
4013
4014         /* If budget not fully consumed, exit the polling mode */
4015         if (work_done < budget) {
4016                 napi_complete(napi);
4017                 if (adapter->rx_itr_setting & 1)
4018                         ixgbe_set_itr(adapter);
4019                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4020                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4021         }
4022         return work_done;
4023 }
4024
4025 /**
4026  * ixgbe_tx_timeout - Respond to a Tx Hang
4027  * @netdev: network interface device structure
4028  **/
4029 static void ixgbe_tx_timeout(struct net_device *netdev)
4030 {
4031         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4032
4033         /* Do the reset outside of interrupt context */
4034         schedule_work(&adapter->reset_task);
4035 }
4036
4037 static void ixgbe_reset_task(struct work_struct *work)
4038 {
4039         struct ixgbe_adapter *adapter;
4040         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4041
4042         /* If we're already down or resetting, just bail */
4043         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4044             test_bit(__IXGBE_RESETTING, &adapter->state))
4045                 return;
4046
4047         adapter->tx_timeout_count++;
4048
4049         ixgbe_dump(adapter);
4050         netdev_err(adapter->netdev, "Reset adapter\n");
4051         ixgbe_reinit_locked(adapter);
4052 }
4053
4054 #ifdef CONFIG_IXGBE_DCB
4055 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4056 {
4057         bool ret = false;
4058         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4059
4060         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4061                 return ret;
4062
4063         f->mask = 0x7 << 3;
4064         adapter->num_rx_queues = f->indices;
4065         adapter->num_tx_queues = f->indices;
4066         ret = true;
4067
4068         return ret;
4069 }
4070 #endif
4071
4072 /**
4073  * ixgbe_set_rss_queues: Allocate queues for RSS
4074  * @adapter: board private structure to initialize
4075  *
4076  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4077  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4078  *
4079  **/
4080 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4081 {
4082         bool ret = false;
4083         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4084
4085         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4086                 f->mask = 0xF;
4087                 adapter->num_rx_queues = f->indices;
4088                 adapter->num_tx_queues = f->indices;
4089                 ret = true;
4090         } else {
4091                 ret = false;
4092         }
4093
4094         return ret;
4095 }
4096
4097 /**
4098  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4099  * @adapter: board private structure to initialize
4100  *
4101  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4102  * to the original CPU that initiated the Tx session.  This runs in addition
4103  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4104  * Rx load across CPUs using RSS.
4105  *
4106  **/
4107 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4108 {
4109         bool ret = false;
4110         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4111
4112         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4113         f_fdir->mask = 0;
4114
4115         /* Flow Director must have RSS enabled */
4116         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4117             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4118              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4119                 adapter->num_tx_queues = f_fdir->indices;
4120                 adapter->num_rx_queues = f_fdir->indices;
4121                 ret = true;
4122         } else {
4123                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4124                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4125         }
4126         return ret;
4127 }
4128
4129 #ifdef IXGBE_FCOE
4130 /**
4131  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4132  * @adapter: board private structure to initialize
4133  *
4134  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4135  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4136  * rx queues out of the max number of rx queues, instead, it is used as the
4137  * index of the first rx queue used by FCoE.
4138  *
4139  **/
4140 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4141 {
4142         bool ret = false;
4143         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4144
4145         f->indices = min((int)num_online_cpus(), f->indices);
4146         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4147                 adapter->num_rx_queues = 1;
4148                 adapter->num_tx_queues = 1;
4149 #ifdef CONFIG_IXGBE_DCB
4150                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4151                         e_info(probe, "FCoE enabled with DCB\n");
4152                         ixgbe_set_dcb_queues(adapter);
4153                 }
4154 #endif
4155                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4156                         e_info(probe, "FCoE enabled with RSS\n");
4157                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4158                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4159                                 ixgbe_set_fdir_queues(adapter);
4160                         else
4161                                 ixgbe_set_rss_queues(adapter);
4162                 }
4163                 /* adding FCoE rx rings to the end */
4164                 f->mask = adapter->num_rx_queues;
4165                 adapter->num_rx_queues += f->indices;
4166                 adapter->num_tx_queues += f->indices;
4167
4168                 ret = true;
4169         }
4170
4171         return ret;
4172 }
4173
4174 #endif /* IXGBE_FCOE */
4175 /**
4176  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4177  * @adapter: board private structure to initialize
4178  *
4179  * IOV doesn't actually use anything, so just NAK the
4180  * request for now and let the other queue routines
4181  * figure out what to do.
4182  */
4183 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4184 {
4185         return false;
4186 }
4187
4188 /*
4189  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4190  * @adapter: board private structure to initialize
4191  *
4192  * This is the top level queue allocation routine.  The order here is very
4193  * important, starting with the "most" number of features turned on at once,
4194  * and ending with the smallest set of features.  This way large combinations
4195  * can be allocated if they're turned on, and smaller combinations are the
4196  * fallthrough conditions.
4197  *
4198  **/
4199 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4200 {
4201         /* Start with base case */
4202         adapter->num_rx_queues = 1;
4203         adapter->num_tx_queues = 1;
4204         adapter->num_rx_pools = adapter->num_rx_queues;
4205         adapter->num_rx_queues_per_pool = 1;
4206
4207         if (ixgbe_set_sriov_queues(adapter))
4208                 goto done;
4209
4210 #ifdef IXGBE_FCOE
4211         if (ixgbe_set_fcoe_queues(adapter))
4212                 goto done;
4213
4214 #endif /* IXGBE_FCOE */
4215 #ifdef CONFIG_IXGBE_DCB
4216         if (ixgbe_set_dcb_queues(adapter))
4217                 goto done;
4218
4219 #endif
4220         if (ixgbe_set_fdir_queues(adapter))
4221                 goto done;
4222
4223         if (ixgbe_set_rss_queues(adapter))
4224                 goto done;
4225
4226         /* fallback to base case */
4227         adapter->num_rx_queues = 1;
4228         adapter->num_tx_queues = 1;
4229
4230 done:
4231         /* Notify the stack of the (possibly) reduced queue counts. */
4232         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4233         return netif_set_real_num_rx_queues(adapter->netdev,
4234                                             adapter->num_rx_queues);
4235 }
4236
4237 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4238                                        int vectors)
4239 {
4240         int err, vector_threshold;
4241
4242         /* We'll want at least 3 (vector_threshold):
4243          * 1) TxQ[0] Cleanup
4244          * 2) RxQ[0] Cleanup
4245          * 3) Other (Link Status Change, etc.)
4246          * 4) TCP Timer (optional)
4247          */
4248         vector_threshold = MIN_MSIX_COUNT;
4249
4250         /* The more we get, the more we will assign to Tx/Rx Cleanup
4251          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4252          * Right now, we simply care about how many we'll get; we'll
4253          * set them up later while requesting irq's.
4254          */
4255         while (vectors >= vector_threshold) {
4256                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4257                                       vectors);
4258                 if (!err) /* Success in acquiring all requested vectors. */
4259                         break;
4260                 else if (err < 0)
4261                         vectors = 0; /* Nasty failure, quit now */
4262                 else /* err == number of vectors we should try again with */
4263                         vectors = err;
4264         }
4265
4266         if (vectors < vector_threshold) {
4267                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4268                  * This just means we'll go with either a single MSI
4269                  * vector or fall back to legacy interrupts.
4270                  */
4271                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4272                              "Unable to allocate MSI-X interrupts\n");
4273                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4274                 kfree(adapter->msix_entries);
4275                 adapter->msix_entries = NULL;
4276         } else {
4277                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4278                 /*
4279                  * Adjust for only the vectors we'll use, which is minimum
4280                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4281                  * vectors we were allocated.
4282                  */
4283                 adapter->num_msix_vectors = min(vectors,
4284                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4285         }
4286 }
4287
4288 /**
4289  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4290  * @adapter: board private structure to initialize
4291  *
4292  * Cache the descriptor ring offsets for RSS to the assigned rings.
4293  *
4294  **/
4295 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4296 {
4297         int i;
4298
4299         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4300                 return false;
4301
4302         for (i = 0; i < adapter->num_rx_queues; i++)
4303                 adapter->rx_ring[i]->reg_idx = i;
4304         for (i = 0; i < adapter->num_tx_queues; i++)
4305                 adapter->tx_ring[i]->reg_idx = i;
4306
4307         return true;
4308 }
4309
4310 #ifdef CONFIG_IXGBE_DCB
4311 /**
4312  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4313  * @adapter: board private structure to initialize
4314  *
4315  * Cache the descriptor ring offsets for DCB to the assigned rings.
4316  *
4317  **/
4318 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4319 {
4320         int i;
4321         bool ret = false;
4322         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4323
4324         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4325                 return false;
4326
4327         /* the number of queues is assumed to be symmetric */
4328         switch (adapter->hw.mac.type) {
4329         case ixgbe_mac_82598EB:
4330                 for (i = 0; i < dcb_i; i++) {
4331                         adapter->rx_ring[i]->reg_idx = i << 3;
4332                         adapter->tx_ring[i]->reg_idx = i << 2;
4333                 }
4334                 ret = true;
4335                 break;
4336         case ixgbe_mac_82599EB:
4337                 if (dcb_i == 8) {
4338                         /*
4339                          * Tx TC0 starts at: descriptor queue 0
4340                          * Tx TC1 starts at: descriptor queue 32
4341                          * Tx TC2 starts at: descriptor queue 64
4342                          * Tx TC3 starts at: descriptor queue 80
4343                          * Tx TC4 starts at: descriptor queue 96
4344                          * Tx TC5 starts at: descriptor queue 104
4345                          * Tx TC6 starts at: descriptor queue 112
4346                          * Tx TC7 starts at: descriptor queue 120
4347                          *
4348                          * Rx TC0-TC7 are offset by 16 queues each
4349                          */
4350                         for (i = 0; i < 3; i++) {
4351                                 adapter->tx_ring[i]->reg_idx = i << 5;
4352                                 adapter->rx_ring[i]->reg_idx = i << 4;
4353                         }
4354                         for ( ; i < 5; i++) {
4355                                 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4356                                 adapter->rx_ring[i]->reg_idx = i << 4;
4357                         }
4358                         for ( ; i < dcb_i; i++) {
4359                                 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4360                                 adapter->rx_ring[i]->reg_idx = i << 4;
4361                         }
4362                         ret = true;
4363                 } else if (dcb_i == 4) {
4364                         /*
4365                          * Tx TC0 starts at: descriptor queue 0
4366                          * Tx TC1 starts at: descriptor queue 64
4367                          * Tx TC2 starts at: descriptor queue 96
4368                          * Tx TC3 starts at: descriptor queue 112
4369                          *
4370                          * Rx TC0-TC3 are offset by 32 queues each
4371                          */
4372                         adapter->tx_ring[0]->reg_idx = 0;
4373                         adapter->tx_ring[1]->reg_idx = 64;
4374                         adapter->tx_ring[2]->reg_idx = 96;
4375                         adapter->tx_ring[3]->reg_idx = 112;
4376                         for (i = 0 ; i < dcb_i; i++)
4377                                 adapter->rx_ring[i]->reg_idx = i << 5;
4378                         ret = true;
4379                 }
4380                 break;
4381         default:
4382                 break;
4383         }
4384         return ret;
4385 }
4386 #endif
4387
4388 /**
4389  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4390  * @adapter: board private structure to initialize
4391  *
4392  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4393  *
4394  **/
4395 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4396 {
4397         int i;
4398         bool ret = false;
4399
4400         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4401             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4402              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4403                 for (i = 0; i < adapter->num_rx_queues; i++)
4404                         adapter->rx_ring[i]->reg_idx = i;
4405                 for (i = 0; i < adapter->num_tx_queues; i++)
4406                         adapter->tx_ring[i]->reg_idx = i;
4407                 ret = true;
4408         }
4409
4410         return ret;
4411 }
4412
4413 #ifdef IXGBE_FCOE
4414 /**
4415  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4416  * @adapter: board private structure to initialize
4417  *
4418  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4419  *
4420  */
4421 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4422 {
4423         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4424         int i;
4425         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4426
4427         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4428                 return false;
4429
4430 #ifdef CONFIG_IXGBE_DCB
4431         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4432                 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4433
4434                 ixgbe_cache_ring_dcb(adapter);
4435                 /* find out queues in TC for FCoE */
4436                 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4437                 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4438                 /*
4439                  * In 82599, the number of Tx queues for each traffic
4440                  * class for both 8-TC and 4-TC modes are:
4441                  * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4442                  * 8 TCs:  32  32  16  16   8   8   8   8
4443                  * 4 TCs:  64  64  32  32
4444                  * We have max 8 queues for FCoE, where 8 the is
4445                  * FCoE redirection table size. If TC for FCoE is
4446                  * less than or equal to TC3, we have enough queues
4447                  * to add max of 8 queues for FCoE, so we start FCoE
4448                  * Tx queue from the next one, i.e., reg_idx + 1.
4449                  * If TC for FCoE is above TC3, implying 8 TC mode,
4450                  * and we need 8 for FCoE, we have to take all queues
4451                  * in that traffic class for FCoE.
4452                  */
4453                 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4454                         fcoe_tx_i--;
4455         }
4456 #endif /* CONFIG_IXGBE_DCB */
4457         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4458                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4459                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4460                         ixgbe_cache_ring_fdir(adapter);
4461                 else
4462                         ixgbe_cache_ring_rss(adapter);
4463
4464                 fcoe_rx_i = f->mask;
4465                 fcoe_tx_i = f->mask;
4466         }
4467         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4468                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4469                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4470         }
4471         return true;
4472 }
4473
4474 #endif /* IXGBE_FCOE */
4475 /**
4476  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4477  * @adapter: board private structure to initialize
4478  *
4479  * SR-IOV doesn't use any descriptor rings but changes the default if
4480  * no other mapping is used.
4481  *
4482  */
4483 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4484 {
4485         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4486         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4487         if (adapter->num_vfs)
4488                 return true;
4489         else
4490                 return false;
4491 }
4492
4493 /**
4494  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4495  * @adapter: board private structure to initialize
4496  *
4497  * Once we know the feature-set enabled for the device, we'll cache
4498  * the register offset the descriptor ring is assigned to.
4499  *
4500  * Note, the order the various feature calls is important.  It must start with
4501  * the "most" features enabled at the same time, then trickle down to the
4502  * least amount of features turned on at once.
4503  **/
4504 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4505 {
4506         /* start with default case */
4507         adapter->rx_ring[0]->reg_idx = 0;
4508         adapter->tx_ring[0]->reg_idx = 0;
4509
4510         if (ixgbe_cache_ring_sriov(adapter))
4511                 return;
4512
4513 #ifdef IXGBE_FCOE
4514         if (ixgbe_cache_ring_fcoe(adapter))
4515                 return;
4516
4517 #endif /* IXGBE_FCOE */
4518 #ifdef CONFIG_IXGBE_DCB
4519         if (ixgbe_cache_ring_dcb(adapter))
4520                 return;
4521
4522 #endif
4523         if (ixgbe_cache_ring_fdir(adapter))
4524                 return;
4525
4526         if (ixgbe_cache_ring_rss(adapter))
4527                 return;
4528 }
4529
4530 /**
4531  * ixgbe_alloc_queues - Allocate memory for all rings
4532  * @adapter: board private structure to initialize
4533  *
4534  * We allocate one ring per queue at run-time since we don't know the
4535  * number of queues at compile-time.  The polling_netdev array is
4536  * intended for Multiqueue, but should work fine with a single queue.
4537  **/
4538 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4539 {
4540         int i;
4541         int rx_count;
4542         int orig_node = adapter->node;
4543
4544         for (i = 0; i < adapter->num_tx_queues; i++) {
4545                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4546                 if (orig_node == -1) {
4547                         int cur_node = next_online_node(adapter->node);
4548                         if (cur_node == MAX_NUMNODES)
4549                                 cur_node = first_online_node;
4550                         adapter->node = cur_node;
4551                 }
4552                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4553                                     adapter->node);
4554                 if (!ring)
4555                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4556                 if (!ring)
4557                         goto err_tx_ring_allocation;
4558                 ring->count = adapter->tx_ring_count;
4559                 ring->queue_index = i;
4560                 ring->dev = &adapter->pdev->dev;
4561                 ring->netdev = adapter->netdev;
4562                 ring->numa_node = adapter->node;
4563
4564                 adapter->tx_ring[i] = ring;
4565         }
4566
4567         /* Restore the adapter's original node */
4568         adapter->node = orig_node;
4569
4570         rx_count = adapter->rx_ring_count;
4571         for (i = 0; i < adapter->num_rx_queues; i++) {
4572                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4573                 if (orig_node == -1) {
4574                         int cur_node = next_online_node(adapter->node);
4575                         if (cur_node == MAX_NUMNODES)
4576                                 cur_node = first_online_node;
4577                         adapter->node = cur_node;
4578                 }
4579                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4580                                     adapter->node);
4581                 if (!ring)
4582                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4583                 if (!ring)
4584                         goto err_rx_ring_allocation;
4585                 ring->count = rx_count;
4586                 ring->queue_index = i;
4587                 ring->dev = &adapter->pdev->dev;
4588                 ring->netdev = adapter->netdev;
4589                 ring->numa_node = adapter->node;
4590
4591                 adapter->rx_ring[i] = ring;
4592         }
4593
4594         /* Restore the adapter's original node */
4595         adapter->node = orig_node;
4596
4597         ixgbe_cache_ring_register(adapter);
4598
4599         return 0;
4600
4601 err_rx_ring_allocation:
4602         for (i = 0; i < adapter->num_tx_queues; i++)
4603                 kfree(adapter->tx_ring[i]);
4604 err_tx_ring_allocation:
4605         return -ENOMEM;
4606 }
4607
4608 /**
4609  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4610  * @adapter: board private structure to initialize
4611  *
4612  * Attempt to configure the interrupts using the best available
4613  * capabilities of the hardware and the kernel.
4614  **/
4615 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4616 {
4617         struct ixgbe_hw *hw = &adapter->hw;
4618         int err = 0;
4619         int vector, v_budget;
4620
4621         /*
4622          * It's easy to be greedy for MSI-X vectors, but it really
4623          * doesn't do us much good if we have a lot more vectors
4624          * than CPU's.  So let's be conservative and only ask for
4625          * (roughly) the same number of vectors as there are CPU's.
4626          */
4627         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4628                        (int)num_online_cpus()) + NON_Q_VECTORS;
4629
4630         /*
4631          * At the same time, hardware can only support a maximum of
4632          * hw.mac->max_msix_vectors vectors.  With features
4633          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4634          * descriptor queues supported by our device.  Thus, we cap it off in
4635          * those rare cases where the cpu count also exceeds our vector limit.
4636          */
4637         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4638
4639         /* A failure in MSI-X entry allocation isn't fatal, but it does
4640          * mean we disable MSI-X capabilities of the adapter. */
4641         adapter->msix_entries = kcalloc(v_budget,
4642                                         sizeof(struct msix_entry), GFP_KERNEL);
4643         if (adapter->msix_entries) {
4644                 for (vector = 0; vector < v_budget; vector++)
4645                         adapter->msix_entries[vector].entry = vector;
4646
4647                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4648
4649                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4650                         goto out;
4651         }
4652
4653         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4654         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4655         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4656         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4657         adapter->atr_sample_rate = 0;
4658         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4659                 ixgbe_disable_sriov(adapter);
4660
4661         err = ixgbe_set_num_queues(adapter);
4662         if (err)
4663                 return err;
4664
4665         err = pci_enable_msi(adapter->pdev);
4666         if (!err) {
4667                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4668         } else {
4669                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4670                              "Unable to allocate MSI interrupt, "
4671                              "falling back to legacy.  Error: %d\n", err);
4672                 /* reset err */
4673                 err = 0;
4674         }
4675
4676 out:
4677         return err;
4678 }
4679
4680 /**
4681  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4682  * @adapter: board private structure to initialize
4683  *
4684  * We allocate one q_vector per queue interrupt.  If allocation fails we
4685  * return -ENOMEM.
4686  **/
4687 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4688 {
4689         int q_idx, num_q_vectors;
4690         struct ixgbe_q_vector *q_vector;
4691         int napi_vectors;
4692         int (*poll)(struct napi_struct *, int);
4693
4694         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4695                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4696                 napi_vectors = adapter->num_rx_queues;
4697                 poll = &ixgbe_clean_rxtx_many;
4698         } else {
4699                 num_q_vectors = 1;
4700                 napi_vectors = 1;
4701                 poll = &ixgbe_poll;
4702         }
4703
4704         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4705                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4706                                         GFP_KERNEL, adapter->node);
4707                 if (!q_vector)
4708                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4709                                            GFP_KERNEL);
4710                 if (!q_vector)
4711                         goto err_out;
4712                 q_vector->adapter = adapter;
4713                 if (q_vector->txr_count && !q_vector->rxr_count)
4714                         q_vector->eitr = adapter->tx_eitr_param;
4715                 else
4716                         q_vector->eitr = adapter->rx_eitr_param;
4717                 q_vector->v_idx = q_idx;
4718                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4719                 adapter->q_vector[q_idx] = q_vector;
4720         }
4721
4722         return 0;
4723
4724 err_out:
4725         while (q_idx) {
4726                 q_idx--;
4727                 q_vector = adapter->q_vector[q_idx];
4728                 netif_napi_del(&q_vector->napi);
4729                 kfree(q_vector);
4730                 adapter->q_vector[q_idx] = NULL;
4731         }
4732         return -ENOMEM;
4733 }
4734
4735 /**
4736  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4737  * @adapter: board private structure to initialize
4738  *
4739  * This function frees the memory allocated to the q_vectors.  In addition if
4740  * NAPI is enabled it will delete any references to the NAPI struct prior
4741  * to freeing the q_vector.
4742  **/
4743 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4744 {
4745         int q_idx, num_q_vectors;
4746
4747         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4748                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4749         else
4750                 num_q_vectors = 1;
4751
4752         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4753                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4754                 adapter->q_vector[q_idx] = NULL;
4755                 netif_napi_del(&q_vector->napi);
4756                 kfree(q_vector);
4757         }
4758 }
4759
4760 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4761 {
4762         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4763                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4764                 pci_disable_msix(adapter->pdev);
4765                 kfree(adapter->msix_entries);
4766                 adapter->msix_entries = NULL;
4767         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4768                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4769                 pci_disable_msi(adapter->pdev);
4770         }
4771 }
4772
4773 /**
4774  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4775  * @adapter: board private structure to initialize
4776  *
4777  * We determine which interrupt scheme to use based on...
4778  * - Kernel support (MSI, MSI-X)
4779  *   - which can be user-defined (via MODULE_PARAM)
4780  * - Hardware queue count (num_*_queues)
4781  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4782  **/
4783 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4784 {
4785         int err;
4786
4787         /* Number of supported queues */
4788         err = ixgbe_set_num_queues(adapter);
4789         if (err)
4790                 return err;
4791
4792         err = ixgbe_set_interrupt_capability(adapter);
4793         if (err) {
4794                 e_dev_err("Unable to setup interrupt capabilities\n");
4795                 goto err_set_interrupt;
4796         }
4797
4798         err = ixgbe_alloc_q_vectors(adapter);
4799         if (err) {
4800                 e_dev_err("Unable to allocate memory for queue vectors\n");
4801                 goto err_alloc_q_vectors;
4802         }
4803
4804         err = ixgbe_alloc_queues(adapter);
4805         if (err) {
4806                 e_dev_err("Unable to allocate memory for queues\n");
4807                 goto err_alloc_queues;
4808         }
4809
4810         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4811                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4812                    adapter->num_rx_queues, adapter->num_tx_queues);
4813
4814         set_bit(__IXGBE_DOWN, &adapter->state);
4815
4816         return 0;
4817
4818 err_alloc_queues:
4819         ixgbe_free_q_vectors(adapter);
4820 err_alloc_q_vectors:
4821         ixgbe_reset_interrupt_capability(adapter);
4822 err_set_interrupt:
4823         return err;
4824 }
4825
4826 static void ring_free_rcu(struct rcu_head *head)
4827 {
4828         kfree(container_of(head, struct ixgbe_ring, rcu));
4829 }
4830
4831 /**
4832  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4833  * @adapter: board private structure to clear interrupt scheme on
4834  *
4835  * We go through and clear interrupt specific resources and reset the structure
4836  * to pre-load conditions
4837  **/
4838 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4839 {
4840         int i;
4841
4842         for (i = 0; i < adapter->num_tx_queues; i++) {
4843                 kfree(adapter->tx_ring[i]);
4844                 adapter->tx_ring[i] = NULL;
4845         }
4846         for (i = 0; i < adapter->num_rx_queues; i++) {
4847                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4848
4849                 /* ixgbe_get_stats64() might access this ring, we must wait
4850                  * a grace period before freeing it.
4851                  */
4852                 call_rcu(&ring->rcu, ring_free_rcu);
4853                 adapter->rx_ring[i] = NULL;
4854         }
4855
4856         ixgbe_free_q_vectors(adapter);
4857         ixgbe_reset_interrupt_capability(adapter);
4858 }
4859
4860 /**
4861  * ixgbe_sfp_timer - worker thread to find a missing module
4862  * @data: pointer to our adapter struct
4863  **/
4864 static void ixgbe_sfp_timer(unsigned long data)
4865 {
4866         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4867
4868         /*
4869          * Do the sfp_timer outside of interrupt context due to the
4870          * delays that sfp+ detection requires
4871          */
4872         schedule_work(&adapter->sfp_task);
4873 }
4874
4875 /**
4876  * ixgbe_sfp_task - worker thread to find a missing module
4877  * @work: pointer to work_struct containing our data
4878  **/
4879 static void ixgbe_sfp_task(struct work_struct *work)
4880 {
4881         struct ixgbe_adapter *adapter = container_of(work,
4882                                                      struct ixgbe_adapter,
4883                                                      sfp_task);
4884         struct ixgbe_hw *hw = &adapter->hw;
4885
4886         if ((hw->phy.type == ixgbe_phy_nl) &&
4887             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4888                 s32 ret = hw->phy.ops.identify_sfp(hw);
4889                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4890                         goto reschedule;
4891                 ret = hw->phy.ops.reset(hw);
4892                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4893                         e_dev_err("failed to initialize because an unsupported "
4894                                   "SFP+ module type was detected.\n");
4895                         e_dev_err("Reload the driver after installing a "
4896                                   "supported module.\n");
4897                         unregister_netdev(adapter->netdev);
4898                 } else {
4899                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4900                 }
4901                 /* don't need this routine any more */
4902                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4903         }
4904         return;
4905 reschedule:
4906         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4907                 mod_timer(&adapter->sfp_timer,
4908                           round_jiffies(jiffies + (2 * HZ)));
4909 }
4910
4911 /**
4912  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4913  * @adapter: board private structure to initialize
4914  *
4915  * ixgbe_sw_init initializes the Adapter private data structure.
4916  * Fields are initialized based on PCI device information and
4917  * OS network device settings (MTU size).
4918  **/
4919 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4920 {
4921         struct ixgbe_hw *hw = &adapter->hw;
4922         struct pci_dev *pdev = adapter->pdev;
4923         struct net_device *dev = adapter->netdev;
4924         unsigned int rss;
4925 #ifdef CONFIG_IXGBE_DCB
4926         int j;
4927         struct tc_configuration *tc;
4928 #endif
4929         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4930
4931         /* PCI config space info */
4932
4933         hw->vendor_id = pdev->vendor;
4934         hw->device_id = pdev->device;
4935         hw->revision_id = pdev->revision;
4936         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4937         hw->subsystem_device_id = pdev->subsystem_device;
4938
4939         /* Set capability flags */
4940         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4941         adapter->ring_feature[RING_F_RSS].indices = rss;
4942         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4943         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4944         switch (hw->mac.type) {
4945         case ixgbe_mac_82598EB:
4946                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4947                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4948                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4949                 break;
4950         case ixgbe_mac_82599EB:
4951                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4952                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4953                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4954                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4955                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4956                 if (dev->features & NETIF_F_NTUPLE) {
4957                         /* Flow Director perfect filter enabled */
4958                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4959                         adapter->atr_sample_rate = 0;
4960                         spin_lock_init(&adapter->fdir_perfect_lock);
4961                 } else {
4962                         /* Flow Director hash filters enabled */
4963                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4964                         adapter->atr_sample_rate = 20;
4965                 }
4966                 adapter->ring_feature[RING_F_FDIR].indices =
4967                                                          IXGBE_MAX_FDIR_INDICES;
4968                 adapter->fdir_pballoc = 0;
4969 #ifdef IXGBE_FCOE
4970                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4971                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4972                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4973 #ifdef CONFIG_IXGBE_DCB
4974                 /* Default traffic class to use for FCoE */
4975                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4976                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4977 #endif
4978 #endif /* IXGBE_FCOE */
4979                 break;
4980         default:
4981                 break;
4982         }
4983
4984 #ifdef CONFIG_IXGBE_DCB
4985         /* Configure DCB traffic classes */
4986         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4987                 tc = &adapter->dcb_cfg.tc_config[j];
4988                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4989                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4990                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4991                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4992                 tc->dcb_pfc = pfc_disabled;
4993         }
4994         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4995         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4996         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4997         adapter->dcb_cfg.pfc_mode_enable = false;
4998         adapter->dcb_cfg.round_robin_enable = false;
4999         adapter->dcb_set_bitmap = 0x00;
5000         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5001                            adapter->ring_feature[RING_F_DCB].indices);
5002
5003 #endif
5004
5005         /* default flow control settings */
5006         hw->fc.requested_mode = ixgbe_fc_full;
5007         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5008 #ifdef CONFIG_DCB
5009         adapter->last_lfc_mode = hw->fc.current_mode;
5010 #endif
5011         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5012         hw->fc.low_water = FC_LOW_WATER(max_frame);
5013         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5014         hw->fc.send_xon = true;
5015         hw->fc.disable_fc_autoneg = false;
5016
5017         /* enable itr by default in dynamic mode */
5018         adapter->rx_itr_setting = 1;
5019         adapter->rx_eitr_param = 20000;
5020         adapter->tx_itr_setting = 1;
5021         adapter->tx_eitr_param = 10000;
5022
5023         /* set defaults for eitr in MegaBytes */
5024         adapter->eitr_low = 10;
5025         adapter->eitr_high = 20;
5026
5027         /* set default ring sizes */
5028         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5029         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5030
5031         /* initialize eeprom parameters */
5032         if (ixgbe_init_eeprom_params_generic(hw)) {
5033                 e_dev_err("EEPROM initialization failed\n");
5034                 return -EIO;
5035         }
5036
5037         /* enable rx csum by default */
5038         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5039
5040         /* get assigned NUMA node */
5041         adapter->node = dev_to_node(&pdev->dev);
5042
5043         set_bit(__IXGBE_DOWN, &adapter->state);
5044
5045         return 0;
5046 }
5047
5048 /**
5049  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5050  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5051  *
5052  * Return 0 on success, negative on failure
5053  **/
5054 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5055 {
5056         struct device *dev = tx_ring->dev;
5057         int size;
5058
5059         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5060         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
5061         if (!tx_ring->tx_buffer_info)
5062                 tx_ring->tx_buffer_info = vmalloc(size);
5063         if (!tx_ring->tx_buffer_info)
5064                 goto err;
5065         memset(tx_ring->tx_buffer_info, 0, size);
5066
5067         /* round up to nearest 4K */
5068         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5069         tx_ring->size = ALIGN(tx_ring->size, 4096);
5070
5071         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5072                                            &tx_ring->dma, GFP_KERNEL);
5073         if (!tx_ring->desc)
5074                 goto err;
5075
5076         tx_ring->next_to_use = 0;
5077         tx_ring->next_to_clean = 0;
5078         tx_ring->work_limit = tx_ring->count;
5079         return 0;
5080
5081 err:
5082         vfree(tx_ring->tx_buffer_info);
5083         tx_ring->tx_buffer_info = NULL;
5084         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5085         return -ENOMEM;
5086 }
5087
5088 /**
5089  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5090  * @adapter: board private structure
5091  *
5092  * If this function returns with an error, then it's possible one or
5093  * more of the rings is populated (while the rest are not).  It is the
5094  * callers duty to clean those orphaned rings.
5095  *
5096  * Return 0 on success, negative on failure
5097  **/
5098 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5099 {
5100         int i, err = 0;
5101
5102         for (i = 0; i < adapter->num_tx_queues; i++) {
5103                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5104                 if (!err)
5105                         continue;
5106                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5107                 break;
5108         }
5109
5110         return err;
5111 }
5112
5113 /**
5114  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5115  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5116  *
5117  * Returns 0 on success, negative on failure
5118  **/
5119 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5120 {
5121         struct device *dev = rx_ring->dev;
5122         int size;
5123
5124         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5125         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5126         if (!rx_ring->rx_buffer_info)
5127                 rx_ring->rx_buffer_info = vmalloc(size);
5128         if (!rx_ring->rx_buffer_info)
5129                 goto err;
5130         memset(rx_ring->rx_buffer_info, 0, size);
5131
5132         /* Round up to nearest 4K */
5133         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5134         rx_ring->size = ALIGN(rx_ring->size, 4096);
5135
5136         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5137                                            &rx_ring->dma, GFP_KERNEL);
5138
5139         if (!rx_ring->desc)
5140                 goto err;
5141
5142         rx_ring->next_to_clean = 0;
5143         rx_ring->next_to_use = 0;
5144
5145         return 0;
5146 err:
5147         vfree(rx_ring->rx_buffer_info);
5148         rx_ring->rx_buffer_info = NULL;
5149         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5150         return -ENOMEM;
5151 }
5152
5153 /**
5154  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5155  * @adapter: board private structure
5156  *
5157  * If this function returns with an error, then it's possible one or
5158  * more of the rings is populated (while the rest are not).  It is the
5159  * callers duty to clean those orphaned rings.
5160  *
5161  * Return 0 on success, negative on failure
5162  **/
5163 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5164 {
5165         int i, err = 0;
5166
5167         for (i = 0; i < adapter->num_rx_queues; i++) {
5168                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5169                 if (!err)
5170                         continue;
5171                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5172                 break;
5173         }
5174
5175         return err;
5176 }
5177
5178 /**
5179  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5180  * @tx_ring: Tx descriptor ring for a specific queue
5181  *
5182  * Free all transmit software resources
5183  **/
5184 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5185 {
5186         ixgbe_clean_tx_ring(tx_ring);
5187
5188         vfree(tx_ring->tx_buffer_info);
5189         tx_ring->tx_buffer_info = NULL;
5190
5191         /* if not set, then don't free */
5192         if (!tx_ring->desc)
5193                 return;
5194
5195         dma_free_coherent(tx_ring->dev, tx_ring->size,
5196                           tx_ring->desc, tx_ring->dma);
5197
5198         tx_ring->desc = NULL;
5199 }
5200
5201 /**
5202  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5203  * @adapter: board private structure
5204  *
5205  * Free all transmit software resources
5206  **/
5207 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5208 {
5209         int i;
5210
5211         for (i = 0; i < adapter->num_tx_queues; i++)
5212                 if (adapter->tx_ring[i]->desc)
5213                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5214 }
5215
5216 /**
5217  * ixgbe_free_rx_resources - Free Rx Resources
5218  * @rx_ring: ring to clean the resources from
5219  *
5220  * Free all receive software resources
5221  **/
5222 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5223 {
5224         ixgbe_clean_rx_ring(rx_ring);
5225
5226         vfree(rx_ring->rx_buffer_info);
5227         rx_ring->rx_buffer_info = NULL;
5228
5229         /* if not set, then don't free */
5230         if (!rx_ring->desc)
5231                 return;
5232
5233         dma_free_coherent(rx_ring->dev, rx_ring->size,
5234                           rx_ring->desc, rx_ring->dma);
5235
5236         rx_ring->desc = NULL;
5237 }
5238
5239 /**
5240  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5241  * @adapter: board private structure
5242  *
5243  * Free all receive software resources
5244  **/
5245 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5246 {
5247         int i;
5248
5249         for (i = 0; i < adapter->num_rx_queues; i++)
5250                 if (adapter->rx_ring[i]->desc)
5251                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5252 }
5253
5254 /**
5255  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5256  * @netdev: network interface device structure
5257  * @new_mtu: new value for maximum frame size
5258  *
5259  * Returns 0 on success, negative on failure
5260  **/
5261 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5262 {
5263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5264         struct ixgbe_hw *hw = &adapter->hw;
5265         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5266
5267         /* MTU < 68 is an error and causes problems on some kernels */
5268         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5269                 return -EINVAL;
5270
5271         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5272         /* must set new MTU before calling down or up */
5273         netdev->mtu = new_mtu;
5274
5275         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5276         hw->fc.low_water = FC_LOW_WATER(max_frame);
5277
5278         if (netif_running(netdev))
5279                 ixgbe_reinit_locked(adapter);
5280
5281         return 0;
5282 }
5283
5284 /**
5285  * ixgbe_open - Called when a network interface is made active
5286  * @netdev: network interface device structure
5287  *
5288  * Returns 0 on success, negative value on failure
5289  *
5290  * The open entry point is called when a network interface is made
5291  * active by the system (IFF_UP).  At this point all resources needed
5292  * for transmit and receive operations are allocated, the interrupt
5293  * handler is registered with the OS, the watchdog timer is started,
5294  * and the stack is notified that the interface is ready.
5295  **/
5296 static int ixgbe_open(struct net_device *netdev)
5297 {
5298         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5299         int err;
5300
5301         /* disallow open during test */
5302         if (test_bit(__IXGBE_TESTING, &adapter->state))
5303                 return -EBUSY;
5304
5305         netif_carrier_off(netdev);
5306
5307         /* allocate transmit descriptors */
5308         err = ixgbe_setup_all_tx_resources(adapter);
5309         if (err)
5310                 goto err_setup_tx;
5311
5312         /* allocate receive descriptors */
5313         err = ixgbe_setup_all_rx_resources(adapter);
5314         if (err)
5315                 goto err_setup_rx;
5316
5317         ixgbe_configure(adapter);
5318
5319         err = ixgbe_request_irq(adapter);
5320         if (err)
5321                 goto err_req_irq;
5322
5323         err = ixgbe_up_complete(adapter);
5324         if (err)
5325                 goto err_up;
5326
5327         netif_tx_start_all_queues(netdev);
5328
5329         return 0;
5330
5331 err_up:
5332         ixgbe_release_hw_control(adapter);
5333         ixgbe_free_irq(adapter);
5334 err_req_irq:
5335 err_setup_rx:
5336         ixgbe_free_all_rx_resources(adapter);
5337 err_setup_tx:
5338         ixgbe_free_all_tx_resources(adapter);
5339         ixgbe_reset(adapter);
5340
5341         return err;
5342 }
5343
5344 /**
5345  * ixgbe_close - Disables a network interface
5346  * @netdev: network interface device structure
5347  *
5348  * Returns 0, this is not allowed to fail
5349  *
5350  * The close entry point is called when an interface is de-activated
5351  * by the OS.  The hardware is still under the drivers control, but
5352  * needs to be disabled.  A global MAC reset is issued to stop the
5353  * hardware, and all transmit and receive resources are freed.
5354  **/
5355 static int ixgbe_close(struct net_device *netdev)
5356 {
5357         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5358
5359         ixgbe_down(adapter);
5360         ixgbe_free_irq(adapter);
5361
5362         ixgbe_free_all_tx_resources(adapter);
5363         ixgbe_free_all_rx_resources(adapter);
5364
5365         ixgbe_release_hw_control(adapter);
5366
5367         return 0;
5368 }
5369
5370 #ifdef CONFIG_PM
5371 static int ixgbe_resume(struct pci_dev *pdev)
5372 {
5373         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5374         struct net_device *netdev = adapter->netdev;
5375         u32 err;
5376
5377         pci_set_power_state(pdev, PCI_D0);
5378         pci_restore_state(pdev);
5379         /*
5380          * pci_restore_state clears dev->state_saved so call
5381          * pci_save_state to restore it.
5382          */
5383         pci_save_state(pdev);
5384
5385         err = pci_enable_device_mem(pdev);
5386         if (err) {
5387                 e_dev_err("Cannot enable PCI device from suspend\n");
5388                 return err;
5389         }
5390         pci_set_master(pdev);
5391
5392         pci_wake_from_d3(pdev, false);
5393
5394         err = ixgbe_init_interrupt_scheme(adapter);
5395         if (err) {
5396                 e_dev_err("Cannot initialize interrupts for device\n");
5397                 return err;
5398         }
5399
5400         ixgbe_reset(adapter);
5401
5402         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5403
5404         if (netif_running(netdev)) {
5405                 err = ixgbe_open(netdev);
5406                 if (err)
5407                         return err;
5408         }
5409
5410         netif_device_attach(netdev);
5411
5412         return 0;
5413 }
5414 #endif /* CONFIG_PM */
5415
5416 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5417 {
5418         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5419         struct net_device *netdev = adapter->netdev;
5420         struct ixgbe_hw *hw = &adapter->hw;
5421         u32 ctrl, fctrl;
5422         u32 wufc = adapter->wol;
5423 #ifdef CONFIG_PM
5424         int retval = 0;
5425 #endif
5426
5427         netif_device_detach(netdev);
5428
5429         if (netif_running(netdev)) {
5430                 ixgbe_down(adapter);
5431                 ixgbe_free_irq(adapter);
5432                 ixgbe_free_all_tx_resources(adapter);
5433                 ixgbe_free_all_rx_resources(adapter);
5434         }
5435
5436         ixgbe_clear_interrupt_scheme(adapter);
5437
5438 #ifdef CONFIG_PM
5439         retval = pci_save_state(pdev);
5440         if (retval)
5441                 return retval;
5442
5443 #endif
5444         if (wufc) {
5445                 ixgbe_set_rx_mode(netdev);
5446
5447                 /* turn on all-multi mode if wake on multicast is enabled */
5448                 if (wufc & IXGBE_WUFC_MC) {
5449                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5450                         fctrl |= IXGBE_FCTRL_MPE;
5451                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5452                 }
5453
5454                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5455                 ctrl |= IXGBE_CTRL_GIO_DIS;
5456                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5457
5458                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5459         } else {
5460                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5461                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5462         }
5463
5464         switch (hw->mac.type) {
5465         case ixgbe_mac_82598EB:
5466                 pci_wake_from_d3(pdev, false);
5467                 break;
5468         case ixgbe_mac_82599EB:
5469                 pci_wake_from_d3(pdev, !!wufc);
5470                 break;
5471         default:
5472                 break;
5473         }
5474
5475         *enable_wake = !!wufc;
5476
5477         ixgbe_release_hw_control(adapter);
5478
5479         pci_disable_device(pdev);
5480
5481         return 0;
5482 }
5483
5484 #ifdef CONFIG_PM
5485 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5486 {
5487         int retval;
5488         bool wake;
5489
5490         retval = __ixgbe_shutdown(pdev, &wake);
5491         if (retval)
5492                 return retval;
5493
5494         if (wake) {
5495                 pci_prepare_to_sleep(pdev);
5496         } else {
5497                 pci_wake_from_d3(pdev, false);
5498                 pci_set_power_state(pdev, PCI_D3hot);
5499         }
5500
5501         return 0;
5502 }
5503 #endif /* CONFIG_PM */
5504
5505 static void ixgbe_shutdown(struct pci_dev *pdev)
5506 {
5507         bool wake;
5508
5509         __ixgbe_shutdown(pdev, &wake);
5510
5511         if (system_state == SYSTEM_POWER_OFF) {
5512                 pci_wake_from_d3(pdev, wake);
5513                 pci_set_power_state(pdev, PCI_D3hot);
5514         }
5515 }
5516
5517 /**
5518  * ixgbe_update_stats - Update the board statistics counters.
5519  * @adapter: board private structure
5520  **/
5521 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5522 {
5523         struct net_device *netdev = adapter->netdev;
5524         struct ixgbe_hw *hw = &adapter->hw;
5525         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5526         u64 total_mpc = 0;
5527         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5528         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5529         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5530         u64 bytes = 0, packets = 0;
5531
5532         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5533             test_bit(__IXGBE_RESETTING, &adapter->state))
5534                 return;
5535
5536         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5537                 u64 rsc_count = 0;
5538                 u64 rsc_flush = 0;
5539                 for (i = 0; i < 16; i++)
5540                         adapter->hw_rx_no_dma_resources +=
5541                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5542                 for (i = 0; i < adapter->num_rx_queues; i++) {
5543                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5544                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5545                 }
5546                 adapter->rsc_total_count = rsc_count;
5547                 adapter->rsc_total_flush = rsc_flush;
5548         }
5549
5550         for (i = 0; i < adapter->num_rx_queues; i++) {
5551                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5552                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5553                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5554                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5555                 bytes += rx_ring->stats.bytes;
5556                 packets += rx_ring->stats.packets;
5557         }
5558         adapter->non_eop_descs = non_eop_descs;
5559         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5560         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5561         netdev->stats.rx_bytes = bytes;
5562         netdev->stats.rx_packets = packets;
5563
5564         bytes = 0;
5565         packets = 0;
5566         /* gather some stats to the adapter struct that are per queue */
5567         for (i = 0; i < adapter->num_tx_queues; i++) {
5568                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5569                 restart_queue += tx_ring->tx_stats.restart_queue;
5570                 tx_busy += tx_ring->tx_stats.tx_busy;
5571                 bytes += tx_ring->stats.bytes;
5572                 packets += tx_ring->stats.packets;
5573         }
5574         adapter->restart_queue = restart_queue;
5575         adapter->tx_busy = tx_busy;
5576         netdev->stats.tx_bytes = bytes;
5577         netdev->stats.tx_packets = packets;
5578
5579         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5580         for (i = 0; i < 8; i++) {
5581                 /* for packet buffers not used, the register should read 0 */
5582                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5583                 missed_rx += mpc;
5584                 hwstats->mpc[i] += mpc;
5585                 total_mpc += hwstats->mpc[i];
5586                 if (hw->mac.type == ixgbe_mac_82598EB)
5587                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5588                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5589                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5590                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5591                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5592                 switch (hw->mac.type) {
5593                 case ixgbe_mac_82598EB:
5594                         hwstats->pxonrxc[i] +=
5595                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5596                         hwstats->pxoffrxc[i] +=
5597                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5598                         break;
5599                 case ixgbe_mac_82599EB:
5600                         hwstats->pxonrxc[i] +=
5601                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5602                         hwstats->pxoffrxc[i] +=
5603                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5604                         break;
5605                 default:
5606                         break;
5607                 }
5608                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5609                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5610         }
5611         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5612         /* work around hardware counting issue */
5613         hwstats->gprc -= missed_rx;
5614
5615         /* 82598 hardware only has a 32 bit counter in the high register */
5616         switch (hw->mac.type) {
5617         case ixgbe_mac_82598EB:
5618                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5619                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5620                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5621                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5622                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5623                 break;
5624         case ixgbe_mac_82599EB:
5625                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5626                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5627                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5628                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5629                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5630                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5631                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5632                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5633                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5634                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5635 #ifdef IXGBE_FCOE
5636                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5637                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5638                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5639                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5640                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5641                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5642 #endif /* IXGBE_FCOE */
5643                 break;
5644         default:
5645                 break;
5646         }
5647         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5648         hwstats->bprc += bprc;
5649         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5650         if (hw->mac.type == ixgbe_mac_82598EB)
5651                 hwstats->mprc -= bprc;
5652         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5653         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5654         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5655         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5656         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5657         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5658         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5659         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5660         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5661         hwstats->lxontxc += lxon;
5662         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5663         hwstats->lxofftxc += lxoff;
5664         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5665         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5666         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5667         /*
5668          * 82598 errata - tx of flow control packets is included in tx counters
5669          */
5670         xon_off_tot = lxon + lxoff;
5671         hwstats->gptc -= xon_off_tot;
5672         hwstats->mptc -= xon_off_tot;
5673         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5674         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5675         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5676         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5677         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5678         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5679         hwstats->ptc64 -= xon_off_tot;
5680         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5681         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5682         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5683         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5684         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5685         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5686
5687         /* Fill out the OS statistics structure */
5688         netdev->stats.multicast = hwstats->mprc;
5689
5690         /* Rx Errors */
5691         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5692         netdev->stats.rx_dropped = 0;
5693         netdev->stats.rx_length_errors = hwstats->rlec;
5694         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5695         netdev->stats.rx_missed_errors = total_mpc;
5696 }
5697
5698 /**
5699  * ixgbe_watchdog - Timer Call-back
5700  * @data: pointer to adapter cast into an unsigned long
5701  **/
5702 static void ixgbe_watchdog(unsigned long data)
5703 {
5704         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5705         struct ixgbe_hw *hw = &adapter->hw;
5706         u64 eics = 0;
5707         int i;
5708
5709         /*
5710          *  Do the watchdog outside of interrupt context due to the lovely
5711          * delays that some of the newer hardware requires
5712          */
5713
5714         if (test_bit(__IXGBE_DOWN, &adapter->state))
5715                 goto watchdog_short_circuit;
5716
5717         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5718                 /*
5719                  * for legacy and MSI interrupts don't set any bits
5720                  * that are enabled for EIAM, because this operation
5721                  * would set *both* EIMS and EICS for any bit in EIAM
5722                  */
5723                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5724                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5725                 goto watchdog_reschedule;
5726         }
5727
5728         /* get one bit for every active tx/rx interrupt vector */
5729         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5730                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5731                 if (qv->rxr_count || qv->txr_count)
5732                         eics |= ((u64)1 << i);
5733         }
5734
5735         /* Cause software interrupt to ensure rx rings are cleaned */
5736         ixgbe_irq_rearm_queues(adapter, eics);
5737
5738 watchdog_reschedule:
5739         /* Reset the timer */
5740         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5741
5742 watchdog_short_circuit:
5743         schedule_work(&adapter->watchdog_task);
5744 }
5745
5746 /**
5747  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5748  * @work: pointer to work_struct containing our data
5749  **/
5750 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5751 {
5752         struct ixgbe_adapter *adapter = container_of(work,
5753                                                      struct ixgbe_adapter,
5754                                                      multispeed_fiber_task);
5755         struct ixgbe_hw *hw = &adapter->hw;
5756         u32 autoneg;
5757         bool negotiation;
5758
5759         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5760         autoneg = hw->phy.autoneg_advertised;
5761         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5762                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5763         hw->mac.autotry_restart = false;
5764         if (hw->mac.ops.setup_link)
5765                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5766         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5767         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5768 }
5769
5770 /**
5771  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5772  * @work: pointer to work_struct containing our data
5773  **/
5774 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5775 {
5776         struct ixgbe_adapter *adapter = container_of(work,
5777                                                      struct ixgbe_adapter,
5778                                                      sfp_config_module_task);
5779         struct ixgbe_hw *hw = &adapter->hw;
5780         u32 err;
5781
5782         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5783
5784         /* Time for electrical oscillations to settle down */
5785         msleep(100);
5786         err = hw->phy.ops.identify_sfp(hw);
5787
5788         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5789                 e_dev_err("failed to initialize because an unsupported SFP+ "
5790                           "module type was detected.\n");
5791                 e_dev_err("Reload the driver after installing a supported "
5792                           "module.\n");
5793                 unregister_netdev(adapter->netdev);
5794                 return;
5795         }
5796         hw->mac.ops.setup_sfp(hw);
5797
5798         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5799                 /* This will also work for DA Twinax connections */
5800                 schedule_work(&adapter->multispeed_fiber_task);
5801         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5802 }
5803
5804 /**
5805  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5806  * @work: pointer to work_struct containing our data
5807  **/
5808 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5809 {
5810         struct ixgbe_adapter *adapter = container_of(work,
5811                                                      struct ixgbe_adapter,
5812                                                      fdir_reinit_task);
5813         struct ixgbe_hw *hw = &adapter->hw;
5814         int i;
5815
5816         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5817                 for (i = 0; i < adapter->num_tx_queues; i++)
5818                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5819                                 &(adapter->tx_ring[i]->state));
5820         } else {
5821                 e_err(probe, "failed to finish FDIR re-initialization, "
5822                       "ignored adding FDIR ATR filters\n");
5823         }
5824         /* Done FDIR Re-initialization, enable transmits */
5825         netif_tx_start_all_queues(adapter->netdev);
5826 }
5827
5828 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5829
5830 /**
5831  * ixgbe_watchdog_task - worker thread to bring link up
5832  * @work: pointer to work_struct containing our data
5833  **/
5834 static void ixgbe_watchdog_task(struct work_struct *work)
5835 {
5836         struct ixgbe_adapter *adapter = container_of(work,
5837                                                      struct ixgbe_adapter,
5838                                                      watchdog_task);
5839         struct net_device *netdev = adapter->netdev;
5840         struct ixgbe_hw *hw = &adapter->hw;
5841         u32 link_speed;
5842         bool link_up;
5843         int i;
5844         struct ixgbe_ring *tx_ring;
5845         int some_tx_pending = 0;
5846
5847         mutex_lock(&ixgbe_watchdog_lock);
5848
5849         link_up = adapter->link_up;
5850         link_speed = adapter->link_speed;
5851
5852         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5853                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5854                 if (link_up) {
5855 #ifdef CONFIG_DCB
5856                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5857                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5858                                         hw->mac.ops.fc_enable(hw, i);
5859                         } else {
5860                                 hw->mac.ops.fc_enable(hw, 0);
5861                         }
5862 #else
5863                         hw->mac.ops.fc_enable(hw, 0);
5864 #endif
5865                 }
5866
5867                 if (link_up ||
5868                     time_after(jiffies, (adapter->link_check_timeout +
5869                                          IXGBE_TRY_LINK_TIMEOUT))) {
5870                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5871                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5872                 }
5873                 adapter->link_up = link_up;
5874                 adapter->link_speed = link_speed;
5875         }
5876
5877         if (link_up) {
5878                 if (!netif_carrier_ok(netdev)) {
5879                         bool flow_rx, flow_tx;
5880
5881                         switch (hw->mac.type) {
5882                         case ixgbe_mac_82598EB: {
5883                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5884                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5885                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5886                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5887                         }
5888                                 break;
5889                         case ixgbe_mac_82599EB: {
5890                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5891                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5892                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5893                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5894                         }
5895                                 break;
5896                         default:
5897                                 flow_tx = false;
5898                                 flow_rx = false;
5899                                 break;
5900                         }
5901
5902                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5903                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5904                                "10 Gbps" :
5905                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5906                                "1 Gbps" : "unknown speed")),
5907                                ((flow_rx && flow_tx) ? "RX/TX" :
5908                                (flow_rx ? "RX" :
5909                                (flow_tx ? "TX" : "None"))));
5910
5911                         netif_carrier_on(netdev);
5912                 } else {
5913                         /* Force detection of hung controller */
5914                         for (i = 0; i < adapter->num_tx_queues; i++) {
5915                                 tx_ring = adapter->tx_ring[i];
5916                                 set_check_for_tx_hang(tx_ring);
5917                         }
5918                 }
5919         } else {
5920                 adapter->link_up = false;
5921                 adapter->link_speed = 0;
5922                 if (netif_carrier_ok(netdev)) {
5923                         e_info(drv, "NIC Link is Down\n");
5924                         netif_carrier_off(netdev);
5925                 }
5926         }
5927
5928         if (!netif_carrier_ok(netdev)) {
5929                 for (i = 0; i < adapter->num_tx_queues; i++) {
5930                         tx_ring = adapter->tx_ring[i];
5931                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5932                                 some_tx_pending = 1;
5933                                 break;
5934                         }
5935                 }
5936
5937                 if (some_tx_pending) {
5938                         /* We've lost link, so the controller stops DMA,
5939                          * but we've got queued Tx work that's never going
5940                          * to get done, so reset controller to flush Tx.
5941                          * (Do the reset outside of interrupt context).
5942                          */
5943                          schedule_work(&adapter->reset_task);
5944                 }
5945         }
5946
5947         ixgbe_update_stats(adapter);
5948         mutex_unlock(&ixgbe_watchdog_lock);
5949 }
5950
5951 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5952                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5953                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5954 {
5955         struct ixgbe_adv_tx_context_desc *context_desc;
5956         unsigned int i;
5957         int err;
5958         struct ixgbe_tx_buffer *tx_buffer_info;
5959         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5960         u32 mss_l4len_idx, l4len;
5961
5962         if (skb_is_gso(skb)) {
5963                 if (skb_header_cloned(skb)) {
5964                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5965                         if (err)
5966                                 return err;
5967                 }
5968                 l4len = tcp_hdrlen(skb);
5969                 *hdr_len += l4len;
5970
5971                 if (protocol == htons(ETH_P_IP)) {
5972                         struct iphdr *iph = ip_hdr(skb);
5973                         iph->tot_len = 0;
5974                         iph->check = 0;
5975                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5976                                                                  iph->daddr, 0,
5977                                                                  IPPROTO_TCP,
5978                                                                  0);
5979                 } else if (skb_is_gso_v6(skb)) {
5980                         ipv6_hdr(skb)->payload_len = 0;
5981                         tcp_hdr(skb)->check =
5982                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5983                                              &ipv6_hdr(skb)->daddr,
5984                                              0, IPPROTO_TCP, 0);
5985                 }
5986
5987                 i = tx_ring->next_to_use;
5988
5989                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5990                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5991
5992                 /* VLAN MACLEN IPLEN */
5993                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5994                         vlan_macip_lens |=
5995                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5996                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5997                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5998                 *hdr_len += skb_network_offset(skb);
5999                 vlan_macip_lens |=
6000                     (skb_transport_header(skb) - skb_network_header(skb));
6001                 *hdr_len +=
6002                     (skb_transport_header(skb) - skb_network_header(skb));
6003                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6004                 context_desc->seqnum_seed = 0;
6005
6006                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6007                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6008                                    IXGBE_ADVTXD_DTYP_CTXT);
6009
6010                 if (protocol == htons(ETH_P_IP))
6011                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6012                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6013                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6014
6015                 /* MSS L4LEN IDX */
6016                 mss_l4len_idx =
6017                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6018                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6019                 /* use index 1 for TSO */
6020                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6021                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6022
6023                 tx_buffer_info->time_stamp = jiffies;
6024                 tx_buffer_info->next_to_watch = i;
6025
6026                 i++;
6027                 if (i == tx_ring->count)
6028                         i = 0;
6029                 tx_ring->next_to_use = i;
6030
6031                 return true;
6032         }
6033         return false;
6034 }
6035
6036 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6037                       __be16 protocol)
6038 {
6039         u32 rtn = 0;
6040
6041         switch (protocol) {
6042         case cpu_to_be16(ETH_P_IP):
6043                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6044                 switch (ip_hdr(skb)->protocol) {
6045                 case IPPROTO_TCP:
6046                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6047                         break;
6048                 case IPPROTO_SCTP:
6049                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6050                         break;
6051                 }
6052                 break;
6053         case cpu_to_be16(ETH_P_IPV6):
6054                 /* XXX what about other V6 headers?? */
6055                 switch (ipv6_hdr(skb)->nexthdr) {
6056                 case IPPROTO_TCP:
6057                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6058                         break;
6059                 case IPPROTO_SCTP:
6060                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6061                         break;
6062                 }
6063                 break;
6064         default:
6065                 if (unlikely(net_ratelimit()))
6066                         e_warn(probe, "partial checksum but proto=%x!\n",
6067                                protocol);
6068                 break;
6069         }
6070
6071         return rtn;
6072 }
6073
6074 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6075                           struct ixgbe_ring *tx_ring,
6076                           struct sk_buff *skb, u32 tx_flags,
6077                           __be16 protocol)
6078 {
6079         struct ixgbe_adv_tx_context_desc *context_desc;
6080         unsigned int i;
6081         struct ixgbe_tx_buffer *tx_buffer_info;
6082         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6083
6084         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6085             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6086                 i = tx_ring->next_to_use;
6087                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6088                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6089
6090                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6091                         vlan_macip_lens |=
6092                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6093                 vlan_macip_lens |= (skb_network_offset(skb) <<
6094                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6095                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6096                         vlan_macip_lens |= (skb_transport_header(skb) -
6097                                             skb_network_header(skb));
6098
6099                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6100                 context_desc->seqnum_seed = 0;
6101
6102                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6103                                     IXGBE_ADVTXD_DTYP_CTXT);
6104
6105                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6106                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6107
6108                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6109                 /* use index zero for tx checksum offload */
6110                 context_desc->mss_l4len_idx = 0;
6111
6112                 tx_buffer_info->time_stamp = jiffies;
6113                 tx_buffer_info->next_to_watch = i;
6114
6115                 i++;
6116                 if (i == tx_ring->count)
6117                         i = 0;
6118                 tx_ring->next_to_use = i;
6119
6120                 return true;
6121         }
6122
6123         return false;
6124 }
6125
6126 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6127                         struct ixgbe_ring *tx_ring,
6128                         struct sk_buff *skb, u32 tx_flags,
6129                         unsigned int first, const u8 hdr_len)
6130 {
6131         struct device *dev = tx_ring->dev;
6132         struct ixgbe_tx_buffer *tx_buffer_info;
6133         unsigned int len;
6134         unsigned int total = skb->len;
6135         unsigned int offset = 0, size, count = 0, i;
6136         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6137         unsigned int f;
6138         unsigned int bytecount = skb->len;
6139         u16 gso_segs = 1;
6140
6141         i = tx_ring->next_to_use;
6142
6143         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6144                 /* excluding fcoe_crc_eof for FCoE */
6145                 total -= sizeof(struct fcoe_crc_eof);
6146
6147         len = min(skb_headlen(skb), total);
6148         while (len) {
6149                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6150                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6151
6152                 tx_buffer_info->length = size;
6153                 tx_buffer_info->mapped_as_page = false;
6154                 tx_buffer_info->dma = dma_map_single(dev,
6155                                                      skb->data + offset,
6156                                                      size, DMA_TO_DEVICE);
6157                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6158                         goto dma_error;
6159                 tx_buffer_info->time_stamp = jiffies;
6160                 tx_buffer_info->next_to_watch = i;
6161
6162                 len -= size;
6163                 total -= size;
6164                 offset += size;
6165                 count++;
6166
6167                 if (len) {
6168                         i++;
6169                         if (i == tx_ring->count)
6170                                 i = 0;
6171                 }
6172         }
6173
6174         for (f = 0; f < nr_frags; f++) {
6175                 struct skb_frag_struct *frag;
6176
6177                 frag = &skb_shinfo(skb)->frags[f];
6178                 len = min((unsigned int)frag->size, total);
6179                 offset = frag->page_offset;
6180
6181                 while (len) {
6182                         i++;
6183                         if (i == tx_ring->count)
6184                                 i = 0;
6185
6186                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6187                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6188
6189                         tx_buffer_info->length = size;
6190                         tx_buffer_info->dma = dma_map_page(dev,
6191                                                            frag->page,
6192                                                            offset, size,
6193                                                            DMA_TO_DEVICE);
6194                         tx_buffer_info->mapped_as_page = true;
6195                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6196                                 goto dma_error;
6197                         tx_buffer_info->time_stamp = jiffies;
6198                         tx_buffer_info->next_to_watch = i;
6199
6200                         len -= size;
6201                         total -= size;
6202                         offset += size;
6203                         count++;
6204                 }
6205                 if (total == 0)
6206                         break;
6207         }
6208
6209         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6210                 gso_segs = skb_shinfo(skb)->gso_segs;
6211 #ifdef IXGBE_FCOE
6212         /* adjust for FCoE Sequence Offload */
6213         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6214                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6215                                         skb_shinfo(skb)->gso_size);
6216 #endif /* IXGBE_FCOE */
6217         bytecount += (gso_segs - 1) * hdr_len;
6218
6219         /* multiply data chunks by size of headers */
6220         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6221         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6222         tx_ring->tx_buffer_info[i].skb = skb;
6223         tx_ring->tx_buffer_info[first].next_to_watch = i;
6224
6225         return count;
6226
6227 dma_error:
6228         e_dev_err("TX DMA map failed\n");
6229
6230         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6231         tx_buffer_info->dma = 0;
6232         tx_buffer_info->time_stamp = 0;
6233         tx_buffer_info->next_to_watch = 0;
6234         if (count)
6235                 count--;
6236
6237         /* clear timestamp and dma mappings for remaining portion of packet */
6238         while (count--) {
6239                 if (i == 0)
6240                         i += tx_ring->count;
6241                 i--;
6242                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6243                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6244         }
6245
6246         return 0;
6247 }
6248
6249 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6250                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6251 {
6252         union ixgbe_adv_tx_desc *tx_desc = NULL;
6253         struct ixgbe_tx_buffer *tx_buffer_info;
6254         u32 olinfo_status = 0, cmd_type_len = 0;
6255         unsigned int i;
6256         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6257
6258         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6259
6260         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6261
6262         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6263                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6264
6265         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6266                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6267
6268                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6269                                  IXGBE_ADVTXD_POPTS_SHIFT;
6270
6271                 /* use index 1 context for tso */
6272                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6273                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6274                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6275                                          IXGBE_ADVTXD_POPTS_SHIFT;
6276
6277         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6278                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6279                                  IXGBE_ADVTXD_POPTS_SHIFT;
6280
6281         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6282                 olinfo_status |= IXGBE_ADVTXD_CC;
6283                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6284                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6285                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6286         }
6287
6288         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6289
6290         i = tx_ring->next_to_use;
6291         while (count--) {
6292                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6293                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6294                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6295                 tx_desc->read.cmd_type_len =
6296                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6297                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6298                 i++;
6299                 if (i == tx_ring->count)
6300                         i = 0;
6301         }
6302
6303         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6304
6305         /*
6306          * Force memory writes to complete before letting h/w
6307          * know there are new descriptors to fetch.  (Only
6308          * applicable for weak-ordered memory model archs,
6309          * such as IA-64).
6310          */
6311         wmb();
6312
6313         tx_ring->next_to_use = i;
6314         writel(i, tx_ring->tail);
6315 }
6316
6317 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6318                       u8 queue, u32 tx_flags, __be16 protocol)
6319 {
6320         struct ixgbe_atr_input atr_input;
6321         struct iphdr *iph = ip_hdr(skb);
6322         struct ethhdr *eth = (struct ethhdr *)skb->data;
6323         struct tcphdr *th;
6324         u16 vlan_id;
6325
6326         /* Right now, we support IPv4 w/ TCP only */
6327         if (protocol != htons(ETH_P_IP) ||
6328             iph->protocol != IPPROTO_TCP)
6329                 return;
6330
6331         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6332
6333         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6334                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6335
6336         th = tcp_hdr(skb);
6337
6338         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6339         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6340         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6341         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6342         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6343         /* src and dst are inverted, think how the receiver sees them */
6344         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6345         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6346
6347         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6348         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6349 }
6350
6351 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6352 {
6353         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6354         /* Herbert's original patch had:
6355          *  smp_mb__after_netif_stop_queue();
6356          * but since that doesn't exist yet, just open code it. */
6357         smp_mb();
6358
6359         /* We need to check again in a case another CPU has just
6360          * made room available. */
6361         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6362                 return -EBUSY;
6363
6364         /* A reprieve! - use start_queue because it doesn't call schedule */
6365         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6366         ++tx_ring->tx_stats.restart_queue;
6367         return 0;
6368 }
6369
6370 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6371 {
6372         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6373                 return 0;
6374         return __ixgbe_maybe_stop_tx(tx_ring, size);
6375 }
6376
6377 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6378 {
6379         struct ixgbe_adapter *adapter = netdev_priv(dev);
6380         int txq = smp_processor_id();
6381 #ifdef IXGBE_FCOE
6382         __be16 protocol;
6383
6384         protocol = vlan_get_protocol(skb);
6385
6386         if ((protocol == htons(ETH_P_FCOE)) ||
6387             (protocol == htons(ETH_P_FIP))) {
6388                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6389                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6390                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6391                         return txq;
6392 #ifdef CONFIG_IXGBE_DCB
6393                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6394                         txq = adapter->fcoe.up;
6395                         return txq;
6396 #endif
6397                 }
6398         }
6399 #endif
6400
6401         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6402                 while (unlikely(txq >= dev->real_num_tx_queues))
6403                         txq -= dev->real_num_tx_queues;
6404                 return txq;
6405         }
6406
6407         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6408                 if (skb->priority == TC_PRIO_CONTROL)
6409                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6410                 else
6411                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6412                                >> 13;
6413                 return txq;
6414         }
6415
6416         return skb_tx_hash(dev, skb);
6417 }
6418
6419 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6420                           struct ixgbe_adapter *adapter,
6421                           struct ixgbe_ring *tx_ring)
6422 {
6423         struct net_device *netdev = tx_ring->netdev;
6424         struct netdev_queue *txq;
6425         unsigned int first;
6426         unsigned int tx_flags = 0;
6427         u8 hdr_len = 0;
6428         int tso;
6429         int count = 0;
6430         unsigned int f;
6431         __be16 protocol;
6432
6433         protocol = vlan_get_protocol(skb);
6434
6435         if (vlan_tx_tag_present(skb)) {
6436                 tx_flags |= vlan_tx_tag_get(skb);
6437                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6438                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6439                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6440                 }
6441                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6442                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6443         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6444                    skb->priority != TC_PRIO_CONTROL) {
6445                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6446                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6447                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6448         }
6449
6450 #ifdef IXGBE_FCOE
6451         /* for FCoE with DCB, we force the priority to what
6452          * was specified by the switch */
6453         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6454             (protocol == htons(ETH_P_FCOE) ||
6455              protocol == htons(ETH_P_FIP))) {
6456 #ifdef CONFIG_IXGBE_DCB
6457                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6458                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6459                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6460                         tx_flags |= ((adapter->fcoe.up << 13)
6461                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6462                 }
6463 #endif
6464                 /* flag for FCoE offloads */
6465                 if (protocol == htons(ETH_P_FCOE))
6466                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6467         }
6468 #endif
6469
6470         /* four things can cause us to need a context descriptor */
6471         if (skb_is_gso(skb) ||
6472             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6473             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6474             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6475                 count++;
6476
6477         count += TXD_USE_COUNT(skb_headlen(skb));
6478         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6479                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6480
6481         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6482                 tx_ring->tx_stats.tx_busy++;
6483                 return NETDEV_TX_BUSY;
6484         }
6485
6486         first = tx_ring->next_to_use;
6487         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6488 #ifdef IXGBE_FCOE
6489                 /* setup tx offload for FCoE */
6490                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6491                 if (tso < 0) {
6492                         dev_kfree_skb_any(skb);
6493                         return NETDEV_TX_OK;
6494                 }
6495                 if (tso)
6496                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6497 #endif /* IXGBE_FCOE */
6498         } else {
6499                 if (protocol == htons(ETH_P_IP))
6500                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6501                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6502                                 protocol);
6503                 if (tso < 0) {
6504                         dev_kfree_skb_any(skb);
6505                         return NETDEV_TX_OK;
6506                 }
6507
6508                 if (tso)
6509                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6510                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6511                                        protocol) &&
6512                          (skb->ip_summed == CHECKSUM_PARTIAL))
6513                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6514         }
6515
6516         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6517         if (count) {
6518                 /* add the ATR filter if ATR is on */
6519                 if (tx_ring->atr_sample_rate) {
6520                         ++tx_ring->atr_count;
6521                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6522                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6523                                       &tx_ring->state)) {
6524                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6525                                           tx_flags, protocol);
6526                                 tx_ring->atr_count = 0;
6527                         }
6528                 }
6529                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6530                 txq->tx_bytes += skb->len;
6531                 txq->tx_packets++;
6532                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6533                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6534
6535         } else {
6536                 dev_kfree_skb_any(skb);
6537                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6538                 tx_ring->next_to_use = first;
6539         }
6540
6541         return NETDEV_TX_OK;
6542 }
6543
6544 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6545 {
6546         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6547         struct ixgbe_ring *tx_ring;
6548
6549         tx_ring = adapter->tx_ring[skb->queue_mapping];
6550         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6551 }
6552
6553 /**
6554  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6555  * @netdev: network interface device structure
6556  * @p: pointer to an address structure
6557  *
6558  * Returns 0 on success, negative on failure
6559  **/
6560 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6561 {
6562         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6563         struct ixgbe_hw *hw = &adapter->hw;
6564         struct sockaddr *addr = p;
6565
6566         if (!is_valid_ether_addr(addr->sa_data))
6567                 return -EADDRNOTAVAIL;
6568
6569         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6570         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6571
6572         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6573                             IXGBE_RAH_AV);
6574
6575         return 0;
6576 }
6577
6578 static int
6579 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6580 {
6581         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6582         struct ixgbe_hw *hw = &adapter->hw;
6583         u16 value;
6584         int rc;
6585
6586         if (prtad != hw->phy.mdio.prtad)
6587                 return -EINVAL;
6588         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6589         if (!rc)
6590                 rc = value;
6591         return rc;
6592 }
6593
6594 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6595                             u16 addr, u16 value)
6596 {
6597         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6598         struct ixgbe_hw *hw = &adapter->hw;
6599
6600         if (prtad != hw->phy.mdio.prtad)
6601                 return -EINVAL;
6602         return hw->phy.ops.write_reg(hw, addr, devad, value);
6603 }
6604
6605 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6606 {
6607         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6608
6609         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6610 }
6611
6612 /**
6613  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6614  * netdev->dev_addrs
6615  * @netdev: network interface device structure
6616  *
6617  * Returns non-zero on failure
6618  **/
6619 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6620 {
6621         int err = 0;
6622         struct ixgbe_adapter *adapter = netdev_priv(dev);
6623         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6624
6625         if (is_valid_ether_addr(mac->san_addr)) {
6626                 rtnl_lock();
6627                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6628                 rtnl_unlock();
6629         }
6630         return err;
6631 }
6632
6633 /**
6634  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6635  * netdev->dev_addrs
6636  * @netdev: network interface device structure
6637  *
6638  * Returns non-zero on failure
6639  **/
6640 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6641 {
6642         int err = 0;
6643         struct ixgbe_adapter *adapter = netdev_priv(dev);
6644         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6645
6646         if (is_valid_ether_addr(mac->san_addr)) {
6647                 rtnl_lock();
6648                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6649                 rtnl_unlock();
6650         }
6651         return err;
6652 }
6653
6654 #ifdef CONFIG_NET_POLL_CONTROLLER
6655 /*
6656  * Polling 'interrupt' - used by things like netconsole to send skbs
6657  * without having to re-enable interrupts. It's not called while
6658  * the interrupt routine is executing.
6659  */
6660 static void ixgbe_netpoll(struct net_device *netdev)
6661 {
6662         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6663         int i;
6664
6665         /* if interface is down do nothing */
6666         if (test_bit(__IXGBE_DOWN, &adapter->state))
6667                 return;
6668
6669         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6670         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6671                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6672                 for (i = 0; i < num_q_vectors; i++) {
6673                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6674                         ixgbe_msix_clean_many(0, q_vector);
6675                 }
6676         } else {
6677                 ixgbe_intr(adapter->pdev->irq, netdev);
6678         }
6679         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6680 }
6681 #endif
6682
6683 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6684                                                    struct rtnl_link_stats64 *stats)
6685 {
6686         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6687         int i;
6688
6689         /* accurate rx/tx bytes/packets stats */
6690         dev_txq_stats_fold(netdev, stats);
6691         rcu_read_lock();
6692         for (i = 0; i < adapter->num_rx_queues; i++) {
6693                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6694                 u64 bytes, packets;
6695                 unsigned int start;
6696
6697                 if (ring) {
6698                         do {
6699                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6700                                 packets = ring->stats.packets;
6701                                 bytes   = ring->stats.bytes;
6702                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6703                         stats->rx_packets += packets;
6704                         stats->rx_bytes   += bytes;
6705                 }
6706         }
6707         rcu_read_unlock();
6708         /* following stats updated by ixgbe_watchdog_task() */
6709         stats->multicast        = netdev->stats.multicast;
6710         stats->rx_errors        = netdev->stats.rx_errors;
6711         stats->rx_length_errors = netdev->stats.rx_length_errors;
6712         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6713         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6714         return stats;
6715 }
6716
6717
6718 static const struct net_device_ops ixgbe_netdev_ops = {
6719         .ndo_open               = ixgbe_open,
6720         .ndo_stop               = ixgbe_close,
6721         .ndo_start_xmit         = ixgbe_xmit_frame,
6722         .ndo_select_queue       = ixgbe_select_queue,
6723         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6724         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6725         .ndo_validate_addr      = eth_validate_addr,
6726         .ndo_set_mac_address    = ixgbe_set_mac,
6727         .ndo_change_mtu         = ixgbe_change_mtu,
6728         .ndo_tx_timeout         = ixgbe_tx_timeout,
6729         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6730         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6731         .ndo_do_ioctl           = ixgbe_ioctl,
6732         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6733         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6734         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6735         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6736         .ndo_get_stats64        = ixgbe_get_stats64,
6737 #ifdef CONFIG_NET_POLL_CONTROLLER
6738         .ndo_poll_controller    = ixgbe_netpoll,
6739 #endif
6740 #ifdef IXGBE_FCOE
6741         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6742         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6743         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6744         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6745         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6746 #endif /* IXGBE_FCOE */
6747 };
6748
6749 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6750                            const struct ixgbe_info *ii)
6751 {
6752 #ifdef CONFIG_PCI_IOV
6753         struct ixgbe_hw *hw = &adapter->hw;
6754         int err;
6755
6756         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6757                 return;
6758
6759         /* The 82599 supports up to 64 VFs per physical function
6760          * but this implementation limits allocation to 63 so that
6761          * basic networking resources are still available to the
6762          * physical function
6763          */
6764         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6765         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6766         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6767         if (err) {
6768                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6769                 goto err_novfs;
6770         }
6771         /* If call to enable VFs succeeded then allocate memory
6772          * for per VF control structures.
6773          */
6774         adapter->vfinfo =
6775                 kcalloc(adapter->num_vfs,
6776                         sizeof(struct vf_data_storage), GFP_KERNEL);
6777         if (adapter->vfinfo) {
6778                 /* Now that we're sure SR-IOV is enabled
6779                  * and memory allocated set up the mailbox parameters
6780                  */
6781                 ixgbe_init_mbx_params_pf(hw);
6782                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6783                        sizeof(hw->mbx.ops));
6784
6785                 /* Disable RSC when in SR-IOV mode */
6786                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6787                                      IXGBE_FLAG2_RSC_ENABLED);
6788                 return;
6789         }
6790
6791         /* Oh oh */
6792         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6793               "SRIOV disabled\n");
6794         pci_disable_sriov(adapter->pdev);
6795
6796 err_novfs:
6797         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6798         adapter->num_vfs = 0;
6799 #endif /* CONFIG_PCI_IOV */
6800 }
6801
6802 /**
6803  * ixgbe_probe - Device Initialization Routine
6804  * @pdev: PCI device information struct
6805  * @ent: entry in ixgbe_pci_tbl
6806  *
6807  * Returns 0 on success, negative on failure
6808  *
6809  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6810  * The OS initialization, configuring of the adapter private structure,
6811  * and a hardware reset occur.
6812  **/
6813 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6814                                  const struct pci_device_id *ent)
6815 {
6816         struct net_device *netdev;
6817         struct ixgbe_adapter *adapter = NULL;
6818         struct ixgbe_hw *hw;
6819         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6820         static int cards_found;
6821         int i, err, pci_using_dac;
6822         unsigned int indices = num_possible_cpus();
6823 #ifdef IXGBE_FCOE
6824         u16 device_caps;
6825 #endif
6826         u32 part_num, eec;
6827
6828         /* Catch broken hardware that put the wrong VF device ID in
6829          * the PCIe SR-IOV capability.
6830          */
6831         if (pdev->is_virtfn) {
6832                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6833                      pci_name(pdev), pdev->vendor, pdev->device);
6834                 return -EINVAL;
6835         }
6836
6837         err = pci_enable_device_mem(pdev);
6838         if (err)
6839                 return err;
6840
6841         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6842             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6843                 pci_using_dac = 1;
6844         } else {
6845                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6846                 if (err) {
6847                         err = dma_set_coherent_mask(&pdev->dev,
6848                                                     DMA_BIT_MASK(32));
6849                         if (err) {
6850                                 dev_err(&pdev->dev,
6851                                         "No usable DMA configuration, aborting\n");
6852                                 goto err_dma;
6853                         }
6854                 }
6855                 pci_using_dac = 0;
6856         }
6857
6858         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6859                                            IORESOURCE_MEM), ixgbe_driver_name);
6860         if (err) {
6861                 dev_err(&pdev->dev,
6862                         "pci_request_selected_regions failed 0x%x\n", err);
6863                 goto err_pci_reg;
6864         }
6865
6866         pci_enable_pcie_error_reporting(pdev);
6867
6868         pci_set_master(pdev);
6869         pci_save_state(pdev);
6870
6871         if (ii->mac == ixgbe_mac_82598EB)
6872                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6873         else
6874                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6875
6876         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6877 #ifdef IXGBE_FCOE
6878         indices += min_t(unsigned int, num_possible_cpus(),
6879                          IXGBE_MAX_FCOE_INDICES);
6880 #endif
6881         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6882         if (!netdev) {
6883                 err = -ENOMEM;
6884                 goto err_alloc_etherdev;
6885         }
6886
6887         SET_NETDEV_DEV(netdev, &pdev->dev);
6888
6889         adapter = netdev_priv(netdev);
6890         pci_set_drvdata(pdev, adapter);
6891
6892         adapter->netdev = netdev;
6893         adapter->pdev = pdev;
6894         hw = &adapter->hw;
6895         hw->back = adapter;
6896         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6897
6898         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6899                               pci_resource_len(pdev, 0));
6900         if (!hw->hw_addr) {
6901                 err = -EIO;
6902                 goto err_ioremap;
6903         }
6904
6905         for (i = 1; i <= 5; i++) {
6906                 if (pci_resource_len(pdev, i) == 0)
6907                         continue;
6908         }
6909
6910         netdev->netdev_ops = &ixgbe_netdev_ops;
6911         ixgbe_set_ethtool_ops(netdev);
6912         netdev->watchdog_timeo = 5 * HZ;
6913         strcpy(netdev->name, pci_name(pdev));
6914
6915         adapter->bd_number = cards_found;
6916
6917         /* Setup hw api */
6918         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6919         hw->mac.type  = ii->mac;
6920
6921         /* EEPROM */
6922         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6923         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6924         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6925         if (!(eec & (1 << 8)))
6926                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6927
6928         /* PHY */
6929         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6930         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6931         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6932         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6933         hw->phy.mdio.mmds = 0;
6934         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6935         hw->phy.mdio.dev = netdev;
6936         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6937         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6938
6939         /* set up this timer and work struct before calling get_invariants
6940          * which might start the timer
6941          */
6942         init_timer(&adapter->sfp_timer);
6943         adapter->sfp_timer.function = ixgbe_sfp_timer;
6944         adapter->sfp_timer.data = (unsigned long) adapter;
6945
6946         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6947
6948         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6949         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6950
6951         /* a new SFP+ module arrival, called from GPI SDP2 context */
6952         INIT_WORK(&adapter->sfp_config_module_task,
6953                   ixgbe_sfp_config_module_task);
6954
6955         ii->get_invariants(hw);
6956
6957         /* setup the private structure */
6958         err = ixgbe_sw_init(adapter);
6959         if (err)
6960                 goto err_sw_init;
6961
6962         /* Make it possible the adapter to be woken up via WOL */
6963         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6964                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6965
6966         /*
6967          * If there is a fan on this device and it has failed log the
6968          * failure.
6969          */
6970         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6971                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6972                 if (esdp & IXGBE_ESDP_SDP1)
6973                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6974         }
6975
6976         /* reset_hw fills in the perm_addr as well */
6977         hw->phy.reset_if_overtemp = true;
6978         err = hw->mac.ops.reset_hw(hw);
6979         hw->phy.reset_if_overtemp = false;
6980         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6981             hw->mac.type == ixgbe_mac_82598EB) {
6982                 /*
6983                  * Start a kernel thread to watch for a module to arrive.
6984                  * Only do this for 82598, since 82599 will generate
6985                  * interrupts on module arrival.
6986                  */
6987                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6988                 mod_timer(&adapter->sfp_timer,
6989                           round_jiffies(jiffies + (2 * HZ)));
6990                 err = 0;
6991         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6992                 e_dev_err("failed to initialize because an unsupported SFP+ "
6993                           "module type was detected.\n");
6994                 e_dev_err("Reload the driver after installing a supported "
6995                           "module.\n");
6996                 goto err_sw_init;
6997         } else if (err) {
6998                 e_dev_err("HW Init failed: %d\n", err);
6999                 goto err_sw_init;
7000         }
7001
7002         ixgbe_probe_vf(adapter, ii);
7003
7004         netdev->features = NETIF_F_SG |
7005                            NETIF_F_IP_CSUM |
7006                            NETIF_F_HW_VLAN_TX |
7007                            NETIF_F_HW_VLAN_RX |
7008                            NETIF_F_HW_VLAN_FILTER;
7009
7010         netdev->features |= NETIF_F_IPV6_CSUM;
7011         netdev->features |= NETIF_F_TSO;
7012         netdev->features |= NETIF_F_TSO6;
7013         netdev->features |= NETIF_F_GRO;
7014
7015         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7016                 netdev->features |= NETIF_F_SCTP_CSUM;
7017
7018         netdev->vlan_features |= NETIF_F_TSO;
7019         netdev->vlan_features |= NETIF_F_TSO6;
7020         netdev->vlan_features |= NETIF_F_IP_CSUM;
7021         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7022         netdev->vlan_features |= NETIF_F_SG;
7023
7024         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7025                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7026                                     IXGBE_FLAG_DCB_ENABLED);
7027         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7028                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7029
7030 #ifdef CONFIG_IXGBE_DCB
7031         netdev->dcbnl_ops = &dcbnl_ops;
7032 #endif
7033
7034 #ifdef IXGBE_FCOE
7035         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7036                 if (hw->mac.ops.get_device_caps) {
7037                         hw->mac.ops.get_device_caps(hw, &device_caps);
7038                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7039                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7040                 }
7041         }
7042         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7043                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7044                 netdev->vlan_features |= NETIF_F_FSO;
7045                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7046         }
7047 #endif /* IXGBE_FCOE */
7048         if (pci_using_dac) {
7049                 netdev->features |= NETIF_F_HIGHDMA;
7050                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7051         }
7052
7053         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7054                 netdev->features |= NETIF_F_LRO;
7055
7056         /* make sure the EEPROM is good */
7057         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7058                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7059                 err = -EIO;
7060                 goto err_eeprom;
7061         }
7062
7063         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7064         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7065
7066         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7067                 e_dev_err("invalid MAC address\n");
7068                 err = -EIO;
7069                 goto err_eeprom;
7070         }
7071
7072         /* power down the optics */
7073         if (hw->phy.multispeed_fiber)
7074                 hw->mac.ops.disable_tx_laser(hw);
7075
7076         init_timer(&adapter->watchdog_timer);
7077         adapter->watchdog_timer.function = ixgbe_watchdog;
7078         adapter->watchdog_timer.data = (unsigned long)adapter;
7079
7080         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7081         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7082
7083         err = ixgbe_init_interrupt_scheme(adapter);
7084         if (err)
7085                 goto err_sw_init;
7086
7087         switch (pdev->device) {
7088         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7089                 /* All except this subdevice support WOL */
7090                 if (pdev->subsystem_device ==
7091                     IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7092                         adapter->wol = 0;
7093                         break;
7094                 }
7095         case IXGBE_DEV_ID_82599_KX4:
7096                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7097                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7098                 break;
7099         default:
7100                 adapter->wol = 0;
7101                 break;
7102         }
7103         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7104
7105         /* pick up the PCI bus settings for reporting later */
7106         hw->mac.ops.get_bus_info(hw);
7107
7108         /* print bus type/speed/width info */
7109         e_dev_info("(PCI Express:%s:%s) %pM\n",
7110                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7111                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7112                     "Unknown"),
7113                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7114                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7115                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7116                     "Unknown"),
7117                    netdev->dev_addr);
7118         ixgbe_read_pba_num_generic(hw, &part_num);
7119         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7120                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7121                            "PBA No: %06x-%03x\n",
7122                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7123                            (part_num >> 8), (part_num & 0xff));
7124         else
7125                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7126                            hw->mac.type, hw->phy.type,
7127                            (part_num >> 8), (part_num & 0xff));
7128
7129         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7130                 e_dev_warn("PCI-Express bandwidth available for this card is "
7131                            "not sufficient for optimal performance.\n");
7132                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7133                            "is required.\n");
7134         }
7135
7136         /* save off EEPROM version number */
7137         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7138
7139         /* reset the hardware with the new settings */
7140         err = hw->mac.ops.start_hw(hw);
7141
7142         if (err == IXGBE_ERR_EEPROM_VERSION) {
7143                 /* We are running on a pre-production device, log a warning */
7144                 e_dev_warn("This device is a pre-production adapter/LOM. "
7145                            "Please be aware there may be issues associated "
7146                            "with your hardware.  If you are experiencing "
7147                            "problems please contact your Intel or hardware "
7148                            "representative who provided you with this "
7149                            "hardware.\n");
7150         }
7151         strcpy(netdev->name, "eth%d");
7152         err = register_netdev(netdev);
7153         if (err)
7154                 goto err_register;
7155
7156         /* carrier off reporting is important to ethtool even BEFORE open */
7157         netif_carrier_off(netdev);
7158
7159         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7160             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7161                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7162
7163         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7164                 INIT_WORK(&adapter->check_overtemp_task,
7165                           ixgbe_check_overtemp_task);
7166 #ifdef CONFIG_IXGBE_DCA
7167         if (dca_add_requester(&pdev->dev) == 0) {
7168                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7169                 ixgbe_setup_dca(adapter);
7170         }
7171 #endif
7172         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7173                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7174                 for (i = 0; i < adapter->num_vfs; i++)
7175                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7176         }
7177
7178         /* add san mac addr to netdev */
7179         ixgbe_add_sanmac_netdev(netdev);
7180
7181         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7182         cards_found++;
7183         return 0;
7184
7185 err_register:
7186         ixgbe_release_hw_control(adapter);
7187         ixgbe_clear_interrupt_scheme(adapter);
7188 err_sw_init:
7189 err_eeprom:
7190         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7191                 ixgbe_disable_sriov(adapter);
7192         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7193         del_timer_sync(&adapter->sfp_timer);
7194         cancel_work_sync(&adapter->sfp_task);
7195         cancel_work_sync(&adapter->multispeed_fiber_task);
7196         cancel_work_sync(&adapter->sfp_config_module_task);
7197         iounmap(hw->hw_addr);
7198 err_ioremap:
7199         free_netdev(netdev);
7200 err_alloc_etherdev:
7201         pci_release_selected_regions(pdev,
7202                                      pci_select_bars(pdev, IORESOURCE_MEM));
7203 err_pci_reg:
7204 err_dma:
7205         pci_disable_device(pdev);
7206         return err;
7207 }
7208
7209 /**
7210  * ixgbe_remove - Device Removal Routine
7211  * @pdev: PCI device information struct
7212  *
7213  * ixgbe_remove is called by the PCI subsystem to alert the driver
7214  * that it should release a PCI device.  The could be caused by a
7215  * Hot-Plug event, or because the driver is going to be removed from
7216  * memory.
7217  **/
7218 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7219 {
7220         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7221         struct net_device *netdev = adapter->netdev;
7222
7223         set_bit(__IXGBE_DOWN, &adapter->state);
7224         /* clear the module not found bit to make sure the worker won't
7225          * reschedule
7226          */
7227         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7228         del_timer_sync(&adapter->watchdog_timer);
7229
7230         del_timer_sync(&adapter->sfp_timer);
7231         cancel_work_sync(&adapter->watchdog_task);
7232         cancel_work_sync(&adapter->sfp_task);
7233         cancel_work_sync(&adapter->multispeed_fiber_task);
7234         cancel_work_sync(&adapter->sfp_config_module_task);
7235         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7236             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7237                 cancel_work_sync(&adapter->fdir_reinit_task);
7238         flush_scheduled_work();
7239
7240 #ifdef CONFIG_IXGBE_DCA
7241         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7242                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7243                 dca_remove_requester(&pdev->dev);
7244                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7245         }
7246
7247 #endif
7248 #ifdef IXGBE_FCOE
7249         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7250                 ixgbe_cleanup_fcoe(adapter);
7251
7252 #endif /* IXGBE_FCOE */
7253
7254         /* remove the added san mac */
7255         ixgbe_del_sanmac_netdev(netdev);
7256
7257         if (netdev->reg_state == NETREG_REGISTERED)
7258                 unregister_netdev(netdev);
7259
7260         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7261                 ixgbe_disable_sriov(adapter);
7262
7263         ixgbe_clear_interrupt_scheme(adapter);
7264
7265         ixgbe_release_hw_control(adapter);
7266
7267         iounmap(adapter->hw.hw_addr);
7268         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7269                                      IORESOURCE_MEM));
7270
7271         e_dev_info("complete\n");
7272
7273         free_netdev(netdev);
7274
7275         pci_disable_pcie_error_reporting(pdev);
7276
7277         pci_disable_device(pdev);
7278 }
7279
7280 /**
7281  * ixgbe_io_error_detected - called when PCI error is detected
7282  * @pdev: Pointer to PCI device
7283  * @state: The current pci connection state
7284  *
7285  * This function is called after a PCI bus error affecting
7286  * this device has been detected.
7287  */
7288 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7289                                                 pci_channel_state_t state)
7290 {
7291         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7292         struct net_device *netdev = adapter->netdev;
7293
7294         netif_device_detach(netdev);
7295
7296         if (state == pci_channel_io_perm_failure)
7297                 return PCI_ERS_RESULT_DISCONNECT;
7298
7299         if (netif_running(netdev))
7300                 ixgbe_down(adapter);
7301         pci_disable_device(pdev);
7302
7303         /* Request a slot reset. */
7304         return PCI_ERS_RESULT_NEED_RESET;
7305 }
7306
7307 /**
7308  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7309  * @pdev: Pointer to PCI device
7310  *
7311  * Restart the card from scratch, as if from a cold-boot.
7312  */
7313 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7314 {
7315         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7316         pci_ers_result_t result;
7317         int err;
7318
7319         if (pci_enable_device_mem(pdev)) {
7320                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7321                 result = PCI_ERS_RESULT_DISCONNECT;
7322         } else {
7323                 pci_set_master(pdev);
7324                 pci_restore_state(pdev);
7325                 pci_save_state(pdev);
7326
7327                 pci_wake_from_d3(pdev, false);
7328
7329                 ixgbe_reset(adapter);
7330                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7331                 result = PCI_ERS_RESULT_RECOVERED;
7332         }
7333
7334         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7335         if (err) {
7336                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7337                           "failed 0x%0x\n", err);
7338                 /* non-fatal, continue */
7339         }
7340
7341         return result;
7342 }
7343
7344 /**
7345  * ixgbe_io_resume - called when traffic can start flowing again.
7346  * @pdev: Pointer to PCI device
7347  *
7348  * This callback is called when the error recovery driver tells us that
7349  * its OK to resume normal operation.
7350  */
7351 static void ixgbe_io_resume(struct pci_dev *pdev)
7352 {
7353         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7354         struct net_device *netdev = adapter->netdev;
7355
7356         if (netif_running(netdev)) {
7357                 if (ixgbe_up(adapter)) {
7358                         e_info(probe, "ixgbe_up failed after reset\n");
7359                         return;
7360                 }
7361         }
7362
7363         netif_device_attach(netdev);
7364 }
7365
7366 static struct pci_error_handlers ixgbe_err_handler = {
7367         .error_detected = ixgbe_io_error_detected,
7368         .slot_reset = ixgbe_io_slot_reset,
7369         .resume = ixgbe_io_resume,
7370 };
7371
7372 static struct pci_driver ixgbe_driver = {
7373         .name     = ixgbe_driver_name,
7374         .id_table = ixgbe_pci_tbl,
7375         .probe    = ixgbe_probe,
7376         .remove   = __devexit_p(ixgbe_remove),
7377 #ifdef CONFIG_PM
7378         .suspend  = ixgbe_suspend,
7379         .resume   = ixgbe_resume,
7380 #endif
7381         .shutdown = ixgbe_shutdown,
7382         .err_handler = &ixgbe_err_handler
7383 };
7384
7385 /**
7386  * ixgbe_init_module - Driver Registration Routine
7387  *
7388  * ixgbe_init_module is the first routine called when the driver is
7389  * loaded. All it does is register with the PCI subsystem.
7390  **/
7391 static int __init ixgbe_init_module(void)
7392 {
7393         int ret;
7394         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7395         pr_info("%s\n", ixgbe_copyright);
7396
7397 #ifdef CONFIG_IXGBE_DCA
7398         dca_register_notify(&dca_notifier);
7399 #endif
7400
7401         ret = pci_register_driver(&ixgbe_driver);
7402         return ret;
7403 }
7404
7405 module_init(ixgbe_init_module);
7406
7407 /**
7408  * ixgbe_exit_module - Driver Exit Cleanup Routine
7409  *
7410  * ixgbe_exit_module is called just before the driver is removed
7411  * from memory.
7412  **/
7413 static void __exit ixgbe_exit_module(void)
7414 {
7415 #ifdef CONFIG_IXGBE_DCA
7416         dca_unregister_notify(&dca_notifier);
7417 #endif
7418         pci_unregister_driver(&ixgbe_driver);
7419         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7420 }
7421
7422 #ifdef CONFIG_IXGBE_DCA
7423 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7424                             void *p)
7425 {
7426         int ret_val;
7427
7428         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7429                                          __ixgbe_notify_dca);
7430
7431         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7432 }
7433
7434 #endif /* CONFIG_IXGBE_DCA */
7435
7436 /**
7437  * ixgbe_get_hw_dev return device
7438  * used by hardware layer to print debugging information
7439  **/
7440 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7441 {
7442         struct ixgbe_adapter *adapter = hw->back;
7443         return adapter->netdev;
7444 }
7445
7446 module_exit(ixgbe_exit_module);
7447
7448 /* ixgbe_main.c */