drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 604                                       struct ixgbe_tx_buffer
 605                                       *tx_buffer_info)
 606 {
 607         if (tx_buffer_info->dma) {
 608                 if (tx_buffer_info->mapped_as_page)
 609                         dma_unmap_page(&adapter->pdev->dev,
 610                                        tx_buffer_info->dma,
 611                                        tx_buffer_info->length,
 612                                        DMA_TO_DEVICE);
 613                 else
 614                         dma_unmap_single(&adapter->pdev->dev,
 615                                          tx_buffer_info->dma,
 616                                          tx_buffer_info->length,
 617                                          DMA_TO_DEVICE);
 618                 tx_buffer_info->dma = 0;
 619         }
 620         if (tx_buffer_info->skb) {
 621                 dev_kfree_skb_any(tx_buffer_info->skb);
 622                 tx_buffer_info->skb = NULL;
 623         }
 624         tx_buffer_info->time_stamp = 0;
 625         /* tx_buffer_info must be completely set up in the transmit path */
 626 }
 627
 628 /**
 629  * ixgbe_tx_xon_state - check the tx ring xon state
 630  * @adapter: the ixgbe adapter
 631  * @tx_ring: the corresponding tx_ring
 632  *
 633  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 634  * corresponding TC of this tx_ring when checking TFCS.
 635  *
 636  * Returns : true if in xon state (currently not paused)
 637  */
 638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 639                                       struct ixgbe_ring *tx_ring)
 640 {
 641         u32 txoff = IXGBE_TFCS_TXOFF;
 642
 643 #ifdef CONFIG_IXGBE_DCB
 644         if (adapter->dcb_cfg.pfc_mode_enable) {
 645                 int tc;
 646                 int reg_idx = tx_ring->reg_idx;
 647                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 648
 649                 switch (adapter->hw.mac.type) {
 650                 case ixgbe_mac_82598EB:
 651                         tc = reg_idx >> 2;
 652                         txoff = IXGBE_TFCS_TXOFF0;
 653                         break;
 654                 case ixgbe_mac_82599EB:
 655                         tc = 0;
 656                         txoff = IXGBE_TFCS_TXOFF;
 657                         if (dcb_i == 8) {
 658                                 /* TC0, TC1 */
 659                                 tc = reg_idx >> 5;
 660                                 if (tc == 2) /* TC2, TC3 */
 661                                         tc += (reg_idx - 64) >> 4;
 662                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 663                                         tc += 1 + ((reg_idx - 96) >> 3);
 664                         } else if (dcb_i == 4) {
 665                                 /* TC0, TC1 */
 666                                 tc = reg_idx >> 6;
 667                                 if (tc == 1) {
 668                                         tc += (reg_idx - 64) >> 5;
 669                                         if (tc == 2) /* TC2, TC3 */
 670                                                 tc += (reg_idx - 96) >> 4;
 671                                 }
 672                         }
 673                         break;
 674                 default:
 675                         tc = 0;
 676                 }
 677                 txoff <<= tc;
 678         }
 679 #endif
 680         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 681 }
 682
 683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 684                                        struct ixgbe_ring *tx_ring,
 685                                        unsigned int eop)
 686 {
 687         struct ixgbe_hw *hw = &adapter->hw;
 688
 689         /* Detect a transmit hang in hardware, this serializes the
 690          * check with the clearing of time_stamp and movement of eop */
 691         adapter->detect_tx_hung = false;
 692         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 693             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 694             ixgbe_tx_xon_state(adapter, tx_ring)) {
 695                 /* detected Tx unit hang */
 696                 union ixgbe_adv_tx_desc *tx_desc;
 697                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 698                 e_err(drv, "Detected Tx Unit Hang\n"
 699                       "  Tx Queue             <%d>\n"
 700                       "  TDH, TDT             <%x>, <%x>\n"
 701                       "  next_to_use          <%x>\n"
 702                       "  next_to_clean        <%x>\n"
 703                       "tx_buffer_info[next_to_clean]\n"
 704                       "  time_stamp           <%lx>\n"
 705                       "  jiffies              <%lx>\n",
 706                       tx_ring->queue_index,
 707                       IXGBE_READ_REG(hw, tx_ring->head),
 708                       IXGBE_READ_REG(hw, tx_ring->tail),
 709                       tx_ring->next_to_use, eop,
 710                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 711                 return true;
 712         }
 713
 714         return false;
 715 }
 716
 717 #define IXGBE_MAX_TXD_PWR       14
 718 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 719
 720 /* Tx Descriptors needed, worst case */
 721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 722                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 724         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 725
 726 static void ixgbe_tx_timeout(struct net_device *netdev);
 727
 728 /**
 729  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 730  * @q_vector: structure containing interrupt and ring information
 731  * @tx_ring: tx ring to clean
 732  **/
 733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 734                                struct ixgbe_ring *tx_ring)
 735 {
 736         struct ixgbe_adapter *adapter = q_vector->adapter;
 737         struct net_device *netdev = adapter->netdev;
 738         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 739         struct ixgbe_tx_buffer *tx_buffer_info;
 740         unsigned int i, eop, count = 0;
 741         unsigned int total_bytes = 0, total_packets = 0;
 742
 743         i = tx_ring->next_to_clean;
 744         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 745         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 746
 747         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 748                (count < tx_ring->work_limit)) {
 749                 bool cleaned = false;
 750                 rmb(); /* read buffer_info after eop_desc */
 751                 for ( ; !cleaned; count++) {
 752                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 753                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 754
 755                         tx_desc->wb.status = 0;
 756                         cleaned = (i == eop);
 757
 758                         i++;
 759                         if (i == tx_ring->count)
 760                                 i = 0;
 761
 762                         if (cleaned && tx_buffer_info->skb) {
 763                                 total_bytes += tx_buffer_info->bytecount;
 764                                 total_packets += tx_buffer_info->gso_segs;
 765                         }
 766
 767                         ixgbe_unmap_and_free_tx_resource(adapter,
 768                                                          tx_buffer_info);
 769                 }
 770
 771                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 772                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 773         }
 774
 775         tx_ring->next_to_clean = i;
 776
 777 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 778         if (unlikely(count && netif_carrier_ok(netdev) &&
 779                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 780                 /* Make sure that anybody stopping the queue after this
 781                  * sees the new next_to_clean.
 782                  */
 783                 smp_mb();
 784                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 785                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 786                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 787                         ++tx_ring->restart_queue;
 788                 }
 789         }
 790
 791         if (adapter->detect_tx_hung) {
 792                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 793                         /* schedule immediate reset if we believe we hung */
 794                         e_info(probe, "tx hang %d detected, resetting "
 795                                "adapter\n", adapter->tx_timeout_count + 1);
 796                         ixgbe_tx_timeout(adapter->netdev);
 797                 }
 798         }
 799
 800         /* re-arm the interrupt */
 801         if (count >= tx_ring->work_limit)
 802                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 803
 804         tx_ring->total_bytes += total_bytes;
 805         tx_ring->total_packets += total_packets;
 806         u64_stats_update_begin(&tx_ring->syncp);
 807         tx_ring->stats.packets += total_packets;
 808         tx_ring->stats.bytes += total_bytes;
 809         u64_stats_update_end(&tx_ring->syncp);
 810         return count < tx_ring->work_limit;
 811 }
 812
 813 #ifdef CONFIG_IXGBE_DCA
 814 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 815                                 struct ixgbe_ring *rx_ring)
 816 {
 817         u32 rxctrl;
 818         int cpu = get_cpu();
 819         int q = rx_ring->reg_idx;
 820
 821         if (rx_ring->cpu != cpu) {
 822                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 823                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 824                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 825                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 826                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 827                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 828                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 829                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 830                 }
 831                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 832                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 833                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 834                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 835                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 836                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 837                 rx_ring->cpu = cpu;
 838         }
 839         put_cpu();
 840 }
 841
 842 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 843                                 struct ixgbe_ring *tx_ring)
 844 {
 845         u32 txctrl;
 846         int cpu = get_cpu();
 847         int q = tx_ring->reg_idx;
 848         struct ixgbe_hw *hw = &adapter->hw;
 849
 850         if (tx_ring->cpu != cpu) {
 851                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 852                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 853                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 854                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 855                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 856                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 857                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 858                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 859                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 860                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 861                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 862                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 863                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 864                 }
 865                 tx_ring->cpu = cpu;
 866         }
 867         put_cpu();
 868 }
 869
 870 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 871 {
 872         int i;
 873
 874         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 875                 return;
 876
 877         /* always use CB2 mode, difference is masked in the CB driver */
 878         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 879
 880         for (i = 0; i < adapter->num_tx_queues; i++) {
 881                 adapter->tx_ring[i]->cpu = -1;
 882                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 883         }
 884         for (i = 0; i < adapter->num_rx_queues; i++) {
 885                 adapter->rx_ring[i]->cpu = -1;
 886                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 887         }
 888 }
 889
 890 static int __ixgbe_notify_dca(struct device *dev, void *data)
 891 {
 892         struct net_device *netdev = dev_get_drvdata(dev);
 893         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 894         unsigned long event = *(unsigned long *)data;
 895
 896         switch (event) {
 897         case DCA_PROVIDER_ADD:
 898                 /* if we're already enabled, don't do it again */
 899                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 900                         break;
 901                 if (dca_add_requester(dev) == 0) {
 902                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 903                         ixgbe_setup_dca(adapter);
 904                         break;
 905                 }
 906                 /* Fall Through since DCA is disabled. */
 907         case DCA_PROVIDER_REMOVE:
 908                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 909                         dca_remove_requester(dev);
 910                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 911                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 912                 }
 913                 break;
 914         }
 915
 916         return 0;
 917 }
 918
 919 #endif /* CONFIG_IXGBE_DCA */
 920 /**
 921  * ixgbe_receive_skb - Send a completed packet up the stack
 922  * @adapter: board private structure
 923  * @skb: packet to send up
 924  * @status: hardware indication of status of receive
 925  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 926  * @rx_desc: rx descriptor
 927  **/
 928 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 929                               struct sk_buff *skb, u8 status,
 930                               struct ixgbe_ring *ring,
 931                               union ixgbe_adv_rx_desc *rx_desc)
 932 {
 933         struct ixgbe_adapter *adapter = q_vector->adapter;
 934         struct napi_struct *napi = &q_vector->napi;
 935         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 936         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 937
 938         if (is_vlan && (tag & VLAN_VID_MASK))
 939                 __vlan_hwaccel_put_tag(skb, tag);
 940
 941         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 942                 napi_gro_receive(napi, skb);
 943         else
 944                 netif_rx(skb);
 945 }
 946
 947 /**
 948  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 949  * @adapter: address of board private structure
 950  * @status_err: hardware indication of status of receive
 951  * @skb: skb currently being received and modified
 952  **/
 953 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 954                                      union ixgbe_adv_rx_desc *rx_desc,
 955                                      struct sk_buff *skb)
 956 {
 957         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 958
 959         skb_checksum_none_assert(skb);
 960
 961         /* Rx csum disabled */
 962         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 963                 return;
 964
 965         /* if IP and error */
 966         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 967             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 968                 adapter->hw_csum_rx_error++;
 969                 return;
 970         }
 971
 972         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 973                 return;
 974
 975         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 976                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 977
 978                 /*
 979                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 980                  * checksum errors.
 981                  */
 982                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 983                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 984                         return;
 985
 986                 adapter->hw_csum_rx_error++;
 987                 return;
 988         }
 989
 990         /* It must be a TCP or UDP packet with a valid checksum */
 991         skb->ip_summed = CHECKSUM_UNNECESSARY;
 992 }
 993
 994 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 995                                          struct ixgbe_ring *rx_ring, u32 val)
 996 {
 997         /*
 998          * Force memory writes to complete before letting h/w
 999          * know there are new descriptors to fetch.  (Only
1000          * applicable for weak-ordered memory model archs,
1001          * such as IA-64).
1002          */
1003         wmb();
1004         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1005 }
1006
1007 /**
1008  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1009  * @adapter: address of board private structure
1010  **/
1011 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1012                             struct ixgbe_ring *rx_ring,
1013                             u16 cleaned_count)
1014 {
1015         struct pci_dev *pdev = adapter->pdev;
1016         union ixgbe_adv_rx_desc *rx_desc;
1017         struct ixgbe_rx_buffer *bi;
1018         struct sk_buff *skb;
1019         u16 i = rx_ring->next_to_use;
1020
1021         while (cleaned_count--) {
1022                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1023                 bi = &rx_ring->rx_buffer_info[i];
1024                 skb = bi->skb;
1025
1026                 if (!skb) {
1027                         skb = netdev_alloc_skb_ip_align(adapter->netdev,
1028                                                         rx_ring->rx_buf_len);
1029                         if (!skb) {
1030                                 adapter->alloc_rx_buff_failed++;
1031                                 goto no_buffers;
1032                         }
1033                         /* initialize queue mapping */
1034                         skb_record_rx_queue(skb, rx_ring->queue_index);
1035                         bi->skb = skb;
1036                 }
1037
1038                 if (!bi->dma) {
1039                         bi->dma = dma_map_single(&pdev->dev,
1040                                                  skb->data,
1041                                                  rx_ring->rx_buf_len,
1042                                                  DMA_FROM_DEVICE);
1043                         if (dma_mapping_error(&pdev->dev, bi->dma)) {
1044                                 adapter->alloc_rx_buff_failed++;
1045                                 bi->dma = 0;
1046                                 goto no_buffers;
1047                         }
1048                 }
1049
1050                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1051                         if (!bi->page) {
1052                                 bi->page = netdev_alloc_page(adapter->netdev);
1053                                 if (!bi->page) {
1054                                         adapter->alloc_rx_page_failed++;
1055                                         goto no_buffers;
1056                                 }
1057                         }
1058
1059                         if (!bi->page_dma) {
1060                                 /* use a half page if we're re-using */
1061                                 bi->page_offset ^= PAGE_SIZE / 2;
1062                                 bi->page_dma = dma_map_page(&pdev->dev,
1063                                                             bi->page,
1064                                                             bi->page_offset,
1065                                                             PAGE_SIZE / 2,
1066                                                             DMA_FROM_DEVICE);
1067                                 if (dma_mapping_error(&pdev->dev,
1068                                                       bi->page_dma)) {
1069                                         adapter->alloc_rx_page_failed++;
1070                                         bi->page_dma = 0;
1071                                         goto no_buffers;
1072                                 }
1073                         }
1074
1075                         /* Refresh the desc even if buffer_addrs didn't change
1076                          * because each write-back erases this info. */
1077                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1078                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1079                 } else {
1080                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1081                         rx_desc->read.hdr_addr = 0;
1082                 }
1083
1084                 i++;
1085                 if (i == rx_ring->count)
1086                         i = 0;
1087         }
1088
1089 no_buffers:
1090         if (rx_ring->next_to_use != i) {
1091                 rx_ring->next_to_use = i;
1092                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1093         }
1094 }
1095
1096 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1097 {
1098         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1099 }
1100
1101 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1102 {
1103         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1104 }
1105
1106 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1107 {
1108         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1109                 IXGBE_RXDADV_RSCCNT_MASK) >>
1110                 IXGBE_RXDADV_RSCCNT_SHIFT;
1111 }
1112
1113 /**
1114  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1115  * @skb: pointer to the last skb in the rsc queue
1116  * @count: pointer to number of packets coalesced in this context
1117  *
1118  * This function changes a queue full of hw rsc buffers into a completed
1119  * packet.  It uses the ->prev pointers to find the first packet and then
1120  * turns it into the frag list owner.
1121  **/
1122 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1123                                                         u64 *count)
1124 {
1125         unsigned int frag_list_size = 0;
1126
1127         while (skb->prev) {
1128                 struct sk_buff *prev = skb->prev;
1129                 frag_list_size += skb->len;
1130                 skb->prev = NULL;
1131                 skb = prev;
1132                 *count += 1;
1133         }
1134
1135         skb_shinfo(skb)->frag_list = skb->next;
1136         skb->next = NULL;
1137         skb->len += frag_list_size;
1138         skb->data_len += frag_list_size;
1139         skb->truesize += frag_list_size;
1140         return skb;
1141 }
1142
1143 struct ixgbe_rsc_cb {
1144         dma_addr_t dma;
1145         bool delay_unmap;
1146 };
1147
1148 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1149
1150 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1151                                struct ixgbe_ring *rx_ring,
1152                                int *work_done, int work_to_do)
1153 {
1154         struct ixgbe_adapter *adapter = q_vector->adapter;
1155         struct pci_dev *pdev = adapter->pdev;
1156         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1157         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1158         struct sk_buff *skb;
1159         unsigned int i, rsc_count = 0;
1160         u32 len, staterr;
1161         u16 hdr_info;
1162         bool cleaned = false;
1163         int cleaned_count = 0;
1164         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1165 #ifdef IXGBE_FCOE
1166         int ddp_bytes = 0;
1167 #endif /* IXGBE_FCOE */
1168
1169         i = rx_ring->next_to_clean;
1170         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1171         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1172         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1173
1174         while (staterr & IXGBE_RXD_STAT_DD) {
1175                 u32 upper_len = 0;
1176                 if (*work_done >= work_to_do)
1177                         break;
1178                 (*work_done)++;
1179
1180                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1181                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1182                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1183                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1184                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1185                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1186                         if ((len > IXGBE_RX_HDR_SIZE) ||
1187                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1188                                 len = IXGBE_RX_HDR_SIZE;
1189                 } else {
1190                         len = le16_to_cpu(rx_desc->wb.upper.length);
1191                 }
1192
1193                 cleaned = true;
1194                 skb = rx_buffer_info->skb;
1195                 prefetch(skb->data);
1196                 rx_buffer_info->skb = NULL;
1197
1198                 if (rx_buffer_info->dma) {
1199                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1200                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1201                                  (!(skb->prev))) {
1202                                 /*
1203                                  * When HWRSC is enabled, delay unmapping
1204                                  * of the first packet. It carries the
1205                                  * header information, HW may still
1206                                  * access the header after the writeback.
1207                                  * Only unmap it when EOP is reached
1208                                  */
1209                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1210                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1211                         } else {
1212                                 dma_unmap_single(&pdev->dev,
1213                                                  rx_buffer_info->dma,
1214                                                  rx_ring->rx_buf_len,
1215                                                  DMA_FROM_DEVICE);
1216                         }
1217                         rx_buffer_info->dma = 0;
1218                         skb_put(skb, len);
1219                 }
1220
1221                 if (upper_len) {
1222                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1223                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
1224                         rx_buffer_info->page_dma = 0;
1225                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1226                                            rx_buffer_info->page,
1227                                            rx_buffer_info->page_offset,
1228                                            upper_len);
1229
1230                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1231                             (page_count(rx_buffer_info->page) != 1))
1232                                 rx_buffer_info->page = NULL;
1233                         else
1234                                 get_page(rx_buffer_info->page);
1235
1236                         skb->len += upper_len;
1237                         skb->data_len += upper_len;
1238                         skb->truesize += upper_len;
1239                 }
1240
1241                 i++;
1242                 if (i == rx_ring->count)
1243                         i = 0;
1244
1245                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1246                 prefetch(next_rxd);
1247                 cleaned_count++;
1248
1249                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1250                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1251
1252                 if (rsc_count) {
1253                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1254                                      IXGBE_RXDADV_NEXTP_SHIFT;
1255                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1256                 } else {
1257                         next_buffer = &rx_ring->rx_buffer_info[i];
1258                 }
1259
1260                 if (staterr & IXGBE_RXD_STAT_EOP) {
1261                         if (skb->prev)
1262                                 skb = ixgbe_transform_rsc_queue(skb,
1263                                                                 &(rx_ring->rsc_count));
1264                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1265                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1266                                         dma_unmap_single(&pdev->dev,
1267                                                          IXGBE_RSC_CB(skb)->dma,
1268                                                          rx_ring->rx_buf_len,
1269                                                          DMA_FROM_DEVICE);
1270                                         IXGBE_RSC_CB(skb)->dma = 0;
1271                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1272                                 }
1273                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1274                                         rx_ring->rsc_count +=
1275                                                 skb_shinfo(skb)->nr_frags;
1276                                 else
1277                                         rx_ring->rsc_count++;
1278                                 rx_ring->rsc_flush++;
1279                         }
1280                         u64_stats_update_begin(&rx_ring->syncp);
1281                         rx_ring->stats.packets++;
1282                         rx_ring->stats.bytes += skb->len;
1283                         u64_stats_update_end(&rx_ring->syncp);
1284                 } else {
1285                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1286                                 rx_buffer_info->skb = next_buffer->skb;
1287                                 rx_buffer_info->dma = next_buffer->dma;
1288                                 next_buffer->skb = skb;
1289                                 next_buffer->dma = 0;
1290                         } else {
1291                                 skb->next = next_buffer->skb;
1292                                 skb->next->prev = skb;
1293                         }
1294                         rx_ring->non_eop_descs++;
1295                         goto next_desc;
1296                 }
1297
1298                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1299                         dev_kfree_skb_irq(skb);
1300                         goto next_desc;
1301                 }
1302
1303                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1304
1305                 /* probably a little skewed due to removing CRC */
1306                 total_rx_bytes += skb->len;
1307                 total_rx_packets++;
1308
1309                 skb->protocol = eth_type_trans(skb, adapter->netdev);
1310 #ifdef IXGBE_FCOE
1311                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1312                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1313                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1314                         if (!ddp_bytes)
1315                                 goto next_desc;
1316                 }
1317 #endif /* IXGBE_FCOE */
1318                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1319
1320 next_desc:
1321                 rx_desc->wb.upper.status_error = 0;
1322
1323                 /* return some buffers to hardware, one at a time is too slow */
1324                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1325                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1326                         cleaned_count = 0;
1327                 }
1328
1329                 /* use prefetched values */
1330                 rx_desc = next_rxd;
1331                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1332
1333                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1334         }
1335
1336         rx_ring->next_to_clean = i;
1337         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1338
1339         if (cleaned_count)
1340                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1341
1342 #ifdef IXGBE_FCOE
1343         /* include DDPed FCoE data */
1344         if (ddp_bytes > 0) {
1345                 unsigned int mss;
1346
1347                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1348                         sizeof(struct fc_frame_header) -
1349                         sizeof(struct fcoe_crc_eof);
1350                 if (mss > 512)
1351                         mss &= ~511;
1352                 total_rx_bytes += ddp_bytes;
1353                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1354         }
1355 #endif /* IXGBE_FCOE */
1356
1357         rx_ring->total_packets += total_rx_packets;
1358         rx_ring->total_bytes += total_rx_bytes;
1359
1360         return cleaned;
1361 }
1362
1363 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1364 /**
1365  * ixgbe_configure_msix - Configure MSI-X hardware
1366  * @adapter: board private structure
1367  *
1368  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1369  * interrupts.
1370  **/
1371 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1372 {
1373         struct ixgbe_q_vector *q_vector;
1374         int i, j, q_vectors, v_idx, r_idx;
1375         u32 mask;
1376
1377         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1378
1379         /*
1380          * Populate the IVAR table and set the ITR values to the
1381          * corresponding register.
1382          */
1383         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1384                 q_vector = adapter->q_vector[v_idx];
1385                 /* XXX for_each_set_bit(...) */
1386                 r_idx = find_first_bit(q_vector->rxr_idx,
1387                                        adapter->num_rx_queues);
1388
1389                 for (i = 0; i < q_vector->rxr_count; i++) {
1390                         j = adapter->rx_ring[r_idx]->reg_idx;
1391                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1392                         r_idx = find_next_bit(q_vector->rxr_idx,
1393                                               adapter->num_rx_queues,
1394                                               r_idx + 1);
1395                 }
1396                 r_idx = find_first_bit(q_vector->txr_idx,
1397                                        adapter->num_tx_queues);
1398
1399                 for (i = 0; i < q_vector->txr_count; i++) {
1400                         j = adapter->tx_ring[r_idx]->reg_idx;
1401                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1402                         r_idx = find_next_bit(q_vector->txr_idx,
1403                                               adapter->num_tx_queues,
1404                                               r_idx + 1);
1405                 }
1406
1407                 if (q_vector->txr_count && !q_vector->rxr_count)
1408                         /* tx only */
1409                         q_vector->eitr = adapter->tx_eitr_param;
1410                 else if (q_vector->rxr_count)
1411                         /* rx or mixed */
1412                         q_vector->eitr = adapter->rx_eitr_param;
1413
1414                 ixgbe_write_eitr(q_vector);
1415                 /* If Flow Director is enabled, set interrupt affinity */
1416                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1417                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1418                         /*
1419                          * Allocate the affinity_hint cpumask, assign the mask
1420                          * for this vector, and set our affinity_hint for
1421                          * this irq.
1422                          */
1423                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1424                                                GFP_KERNEL))
1425                                 return;
1426                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1427                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1428                                               q_vector->affinity_mask);
1429                 }
1430         }
1431
1432         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1433                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1434                                v_idx);
1435         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1436                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1438
1439         /* set up to autoclear timer, and the vectors */
1440         mask = IXGBE_EIMS_ENABLE_MASK;
1441         if (adapter->num_vfs)
1442                 mask &= ~(IXGBE_EIMS_OTHER |
1443                           IXGBE_EIMS_MAILBOX |
1444                           IXGBE_EIMS_LSC);
1445         else
1446                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1447         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1448 }
1449
1450 enum latency_range {
1451         lowest_latency = 0,
1452         low_latency = 1,
1453         bulk_latency = 2,
1454         latency_invalid = 255
1455 };
1456
1457 /**
1458  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1459  * @adapter: pointer to adapter
1460  * @eitr: eitr setting (ints per sec) to give last timeslice
1461  * @itr_setting: current throttle rate in ints/second
1462  * @packets: the number of packets during this measurement interval
1463  * @bytes: the number of bytes during this measurement interval
1464  *
1465  *      Stores a new ITR value based on packets and byte
1466  *      counts during the last interrupt.  The advantage of per interrupt
1467  *      computation is faster updates and more accurate ITR for the current
1468  *      traffic pattern.  Constants in this function were computed
1469  *      based on theoretical maximum wire speed and thresholds were set based
1470  *      on testing data as well as attempting to minimize response time
1471  *      while increasing bulk throughput.
1472  *      this functionality is controlled by the InterruptThrottleRate module
1473  *      parameter (see ixgbe_param.c)
1474  **/
1475 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1476                            u32 eitr, u8 itr_setting,
1477                            int packets, int bytes)
1478 {
1479         unsigned int retval = itr_setting;
1480         u32 timepassed_us;
1481         u64 bytes_perint;
1482
1483         if (packets == 0)
1484                 goto update_itr_done;
1485
1486
1487         /* simple throttlerate management
1488          *    0-20MB/s lowest (100000 ints/s)
1489          *   20-100MB/s low   (20000 ints/s)
1490          *  100-1249MB/s bulk (8000 ints/s)
1491          */
1492         /* what was last interrupt timeslice? */
1493         timepassed_us = 1000000/eitr;
1494         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1495
1496         switch (itr_setting) {
1497         case lowest_latency:
1498                 if (bytes_perint > adapter->eitr_low)
1499                         retval = low_latency;
1500                 break;
1501         case low_latency:
1502                 if (bytes_perint > adapter->eitr_high)
1503                         retval = bulk_latency;
1504                 else if (bytes_perint <= adapter->eitr_low)
1505                         retval = lowest_latency;
1506                 break;
1507         case bulk_latency:
1508                 if (bytes_perint <= adapter->eitr_high)
1509                         retval = low_latency;
1510                 break;
1511         }
1512
1513 update_itr_done:
1514         return retval;
1515 }
1516
1517 /**
1518  * ixgbe_write_eitr - write EITR register in hardware specific way
1519  * @q_vector: structure containing interrupt and ring information
1520  *
1521  * This function is made to be called by ethtool and by the driver
1522  * when it needs to update EITR registers at runtime.  Hardware
1523  * specific quirks/differences are taken care of here.
1524  */
1525 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1526 {
1527         struct ixgbe_adapter *adapter = q_vector->adapter;
1528         struct ixgbe_hw *hw = &adapter->hw;
1529         int v_idx = q_vector->v_idx;
1530         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1531
1532         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1533                 /* must write high and low 16 bits to reset counter */
1534                 itr_reg |= (itr_reg << 16);
1535         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1536                 /*
1537                  * 82599 can support a value of zero, so allow it for
1538                  * max interrupt rate, but there is an errata where it can
1539                  * not be zero with RSC
1540                  */
1541                 if (itr_reg == 8 &&
1542                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1543                         itr_reg = 0;
1544
1545                 /*
1546                  * set the WDIS bit to not clear the timer bits and cause an
1547                  * immediate assertion of the interrupt
1548                  */
1549                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1550         }
1551         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1552 }
1553
1554 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1555 {
1556         struct ixgbe_adapter *adapter = q_vector->adapter;
1557         u32 new_itr;
1558         u8 current_itr, ret_itr;
1559         int i, r_idx;
1560         struct ixgbe_ring *rx_ring, *tx_ring;
1561
1562         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1563         for (i = 0; i < q_vector->txr_count; i++) {
1564                 tx_ring = adapter->tx_ring[r_idx];
1565                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1566                                            q_vector->tx_itr,
1567                                            tx_ring->total_packets,
1568                                            tx_ring->total_bytes);
1569                 /* if the result for this queue would decrease interrupt
1570                  * rate for this vector then use that result */
1571                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1572                                     q_vector->tx_itr - 1 : ret_itr);
1573                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1574                                       r_idx + 1);
1575         }
1576
1577         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1578         for (i = 0; i < q_vector->rxr_count; i++) {
1579                 rx_ring = adapter->rx_ring[r_idx];
1580                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1581                                            q_vector->rx_itr,
1582                                            rx_ring->total_packets,
1583                                            rx_ring->total_bytes);
1584                 /* if the result for this queue would decrease interrupt
1585                  * rate for this vector then use that result */
1586                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1587                                     q_vector->rx_itr - 1 : ret_itr);
1588                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1589                                       r_idx + 1);
1590         }
1591
1592         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1593
1594         switch (current_itr) {
1595         /* counts and packets in update_itr are dependent on these numbers */
1596         case lowest_latency:
1597                 new_itr = 100000;
1598                 break;
1599         case low_latency:
1600                 new_itr = 20000; /* aka hwitr = ~200 */
1601                 break;
1602         case bulk_latency:
1603         default:
1604                 new_itr = 8000;
1605                 break;
1606         }
1607
1608         if (new_itr != q_vector->eitr) {
1609                 /* do an exponential smoothing */
1610                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1611
1612                 /* save the algorithm value here, not the smoothed one */
1613                 q_vector->eitr = new_itr;
1614
1615                 ixgbe_write_eitr(q_vector);
1616         }
1617 }
1618
1619 /**
1620  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1621  * @work: pointer to work_struct containing our data
1622  **/
1623 static void ixgbe_check_overtemp_task(struct work_struct *work)
1624 {
1625         struct ixgbe_adapter *adapter = container_of(work,
1626                                                      struct ixgbe_adapter,
1627                                                      check_overtemp_task);
1628         struct ixgbe_hw *hw = &adapter->hw;
1629         u32 eicr = adapter->interrupt_event;
1630
1631         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1632                 return;
1633
1634         switch (hw->device_id) {
1635         case IXGBE_DEV_ID_82599_T3_LOM: {
1636                 u32 autoneg;
1637                 bool link_up = false;
1638
1639                 if (hw->mac.ops.check_link)
1640                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1641
1642                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1643                     (eicr & IXGBE_EICR_LSC))
1644                         /* Check if this is due to overtemp */
1645                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1646                                 break;
1647                 return;
1648         }
1649         default:
1650                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1651                         return;
1652                 break;
1653         }
1654         e_crit(drv,
1655                "Network adapter has been stopped because it has over heated. "
1656                "Restart the computer. If the problem persists, "
1657                "power off the system and replace the adapter\n");
1658         /* write to clear the interrupt */
1659         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1660 }
1661
1662 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1663 {
1664         struct ixgbe_hw *hw = &adapter->hw;
1665
1666         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1667             (eicr & IXGBE_EICR_GPI_SDP1)) {
1668                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1669                 /* write to clear the interrupt */
1670                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1671         }
1672 }
1673
1674 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1675 {
1676         struct ixgbe_hw *hw = &adapter->hw;
1677
1678         if (eicr & IXGBE_EICR_GPI_SDP1) {
1679                 /* Clear the interrupt */
1680                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1681                 schedule_work(&adapter->multispeed_fiber_task);
1682         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1683                 /* Clear the interrupt */
1684                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1685                 schedule_work(&adapter->sfp_config_module_task);
1686         } else {
1687                 /* Interrupt isn't for us... */
1688                 return;
1689         }
1690 }
1691
1692 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1693 {
1694         struct ixgbe_hw *hw = &adapter->hw;
1695
1696         adapter->lsc_int++;
1697         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1698         adapter->link_check_timeout = jiffies;
1699         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1700                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1701                 IXGBE_WRITE_FLUSH(hw);
1702                 schedule_work(&adapter->watchdog_task);
1703         }
1704 }
1705
1706 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1707 {
1708         struct net_device *netdev = data;
1709         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1710         struct ixgbe_hw *hw = &adapter->hw;
1711         u32 eicr;
1712
1713         /*
1714          * Workaround for Silicon errata.  Use clear-by-write instead
1715          * of clear-by-read.  Reading with EICS will return the
1716          * interrupt causes without clearing, which later be done
1717          * with the write to EICR.
1718          */
1719         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1720         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1721
1722         if (eicr & IXGBE_EICR_LSC)
1723                 ixgbe_check_lsc(adapter);
1724
1725         if (eicr & IXGBE_EICR_MAILBOX)
1726                 ixgbe_msg_task(adapter);
1727
1728         if (hw->mac.type == ixgbe_mac_82598EB)
1729                 ixgbe_check_fan_failure(adapter, eicr);
1730
1731         if (hw->mac.type == ixgbe_mac_82599EB) {
1732                 ixgbe_check_sfp_event(adapter, eicr);
1733                 adapter->interrupt_event = eicr;
1734                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1735                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1736                         schedule_work(&adapter->check_overtemp_task);
1737
1738                 /* Handle Flow Director Full threshold interrupt */
1739                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1740                         int i;
1741                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1742                         /* Disable transmits before FDIR Re-initialization */
1743                         netif_tx_stop_all_queues(netdev);
1744                         for (i = 0; i < adapter->num_tx_queues; i++) {
1745                                 struct ixgbe_ring *tx_ring =
1746                                                             adapter->tx_ring[i];
1747                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1748                                                        &tx_ring->reinit_state))
1749                                         schedule_work(&adapter->fdir_reinit_task);
1750                         }
1751                 }
1752         }
1753         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1754                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1755
1756         return IRQ_HANDLED;
1757 }
1758
1759 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1760                                            u64 qmask)
1761 {
1762         u32 mask;
1763
1764         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1765                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1766                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1767         } else {
1768                 mask = (qmask & 0xFFFFFFFF);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1770                 mask = (qmask >> 32);
1771                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1772         }
1773         /* skip the flush */
1774 }
1775
1776 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1777                                             u64 qmask)
1778 {
1779         u32 mask;
1780
1781         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1782                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1783                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1784         } else {
1785                 mask = (qmask & 0xFFFFFFFF);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1787                 mask = (qmask >> 32);
1788                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1789         }
1790         /* skip the flush */
1791 }
1792
1793 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1794 {
1795         struct ixgbe_q_vector *q_vector = data;
1796         struct ixgbe_adapter  *adapter = q_vector->adapter;
1797         struct ixgbe_ring     *tx_ring;
1798         int i, r_idx;
1799
1800         if (!q_vector->txr_count)
1801                 return IRQ_HANDLED;
1802
1803         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1804         for (i = 0; i < q_vector->txr_count; i++) {
1805                 tx_ring = adapter->tx_ring[r_idx];
1806                 tx_ring->total_bytes = 0;
1807                 tx_ring->total_packets = 0;
1808                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1809                                       r_idx + 1);
1810         }
1811
1812         /* EIAM disabled interrupts (on this vector) for us */
1813         napi_schedule(&q_vector->napi);
1814
1815         return IRQ_HANDLED;
1816 }
1817
1818 /**
1819  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1820  * @irq: unused
1821  * @data: pointer to our q_vector struct for this interrupt vector
1822  **/
1823 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1824 {
1825         struct ixgbe_q_vector *q_vector = data;
1826         struct ixgbe_adapter  *adapter = q_vector->adapter;
1827         struct ixgbe_ring  *rx_ring;
1828         int r_idx;
1829         int i;
1830
1831         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1832         for (i = 0;  i < q_vector->rxr_count; i++) {
1833                 rx_ring = adapter->rx_ring[r_idx];
1834                 rx_ring->total_bytes = 0;
1835                 rx_ring->total_packets = 0;
1836                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1837                                       r_idx + 1);
1838         }
1839
1840         if (!q_vector->rxr_count)
1841                 return IRQ_HANDLED;
1842
1843         /* disable interrupts on this vector only */
1844         /* EIAM disabled interrupts (on this vector) for us */
1845         napi_schedule(&q_vector->napi);
1846
1847         return IRQ_HANDLED;
1848 }
1849
1850 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1851 {
1852         struct ixgbe_q_vector *q_vector = data;
1853         struct ixgbe_adapter  *adapter = q_vector->adapter;
1854         struct ixgbe_ring  *ring;
1855         int r_idx;
1856         int i;
1857
1858         if (!q_vector->txr_count && !q_vector->rxr_count)
1859                 return IRQ_HANDLED;
1860
1861         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1862         for (i = 0; i < q_vector->txr_count; i++) {
1863                 ring = adapter->tx_ring[r_idx];
1864                 ring->total_bytes = 0;
1865                 ring->total_packets = 0;
1866                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1867                                       r_idx + 1);
1868         }
1869
1870         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1871         for (i = 0; i < q_vector->rxr_count; i++) {
1872                 ring = adapter->rx_ring[r_idx];
1873                 ring->total_bytes = 0;
1874                 ring->total_packets = 0;
1875                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1876                                       r_idx + 1);
1877         }
1878
1879         /* EIAM disabled interrupts (on this vector) for us */
1880         napi_schedule(&q_vector->napi);
1881
1882         return IRQ_HANDLED;
1883 }
1884
1885 /**
1886  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1887  * @napi: napi struct with our devices info in it
1888  * @budget: amount of work driver is allowed to do this pass, in packets
1889  *
1890  * This function is optimized for cleaning one queue only on a single
1891  * q_vector!!!
1892  **/
1893 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1894 {
1895         struct ixgbe_q_vector *q_vector =
1896                                container_of(napi, struct ixgbe_q_vector, napi);
1897         struct ixgbe_adapter *adapter = q_vector->adapter;
1898         struct ixgbe_ring *rx_ring = NULL;
1899         int work_done = 0;
1900         long r_idx;
1901
1902         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1903         rx_ring = adapter->rx_ring[r_idx];
1904 #ifdef CONFIG_IXGBE_DCA
1905         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1906                 ixgbe_update_rx_dca(adapter, rx_ring);
1907 #endif
1908
1909         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1910
1911         /* If all Rx work done, exit the polling mode */
1912         if (work_done < budget) {
1913                 napi_complete(napi);
1914                 if (adapter->rx_itr_setting & 1)
1915                         ixgbe_set_itr_msix(q_vector);
1916                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1917                         ixgbe_irq_enable_queues(adapter,
1918                                                 ((u64)1 << q_vector->v_idx));
1919         }
1920
1921         return work_done;
1922 }
1923
1924 /**
1925  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1926  * @napi: napi struct with our devices info in it
1927  * @budget: amount of work driver is allowed to do this pass, in packets
1928  *
1929  * This function will clean more than one rx queue associated with a
1930  * q_vector.
1931  **/
1932 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1933 {
1934         struct ixgbe_q_vector *q_vector =
1935                                container_of(napi, struct ixgbe_q_vector, napi);
1936         struct ixgbe_adapter *adapter = q_vector->adapter;
1937         struct ixgbe_ring *ring = NULL;
1938         int work_done = 0, i;
1939         long r_idx;
1940         bool tx_clean_complete = true;
1941
1942         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1943         for (i = 0; i < q_vector->txr_count; i++) {
1944                 ring = adapter->tx_ring[r_idx];
1945 #ifdef CONFIG_IXGBE_DCA
1946                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1947                         ixgbe_update_tx_dca(adapter, ring);
1948 #endif
1949                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1950                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1951                                       r_idx + 1);
1952         }
1953
1954         /* attempt to distribute budget to each queue fairly, but don't allow
1955          * the budget to go below 1 because we'll exit polling */
1956         budget /= (q_vector->rxr_count ?: 1);
1957         budget = max(budget, 1);
1958         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1959         for (i = 0; i < q_vector->rxr_count; i++) {
1960                 ring = adapter->rx_ring[r_idx];
1961 #ifdef CONFIG_IXGBE_DCA
1962                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1963                         ixgbe_update_rx_dca(adapter, ring);
1964 #endif
1965                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1966                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1967                                       r_idx + 1);
1968         }
1969
1970         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1971         ring = adapter->rx_ring[r_idx];
1972         /* If all Rx work done, exit the polling mode */
1973         if (work_done < budget) {
1974                 napi_complete(napi);
1975                 if (adapter->rx_itr_setting & 1)
1976                         ixgbe_set_itr_msix(q_vector);
1977                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1978                         ixgbe_irq_enable_queues(adapter,
1979                                                 ((u64)1 << q_vector->v_idx));
1980                 return 0;
1981         }
1982
1983         return work_done;
1984 }
1985
1986 /**
1987  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1988  * @napi: napi struct with our devices info in it
1989  * @budget: amount of work driver is allowed to do this pass, in packets
1990  *
1991  * This function is optimized for cleaning one queue only on a single
1992  * q_vector!!!
1993  **/
1994 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1995 {
1996         struct ixgbe_q_vector *q_vector =
1997                                container_of(napi, struct ixgbe_q_vector, napi);
1998         struct ixgbe_adapter *adapter = q_vector->adapter;
1999         struct ixgbe_ring *tx_ring = NULL;
2000         int work_done = 0;
2001         long r_idx;
2002
2003         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2004         tx_ring = adapter->tx_ring[r_idx];
2005 #ifdef CONFIG_IXGBE_DCA
2006         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2007                 ixgbe_update_tx_dca(adapter, tx_ring);
2008 #endif
2009
2010         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2011                 work_done = budget;
2012
2013         /* If all Tx work done, exit the polling mode */
2014         if (work_done < budget) {
2015                 napi_complete(napi);
2016                 if (adapter->tx_itr_setting & 1)
2017                         ixgbe_set_itr_msix(q_vector);
2018                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2019                         ixgbe_irq_enable_queues(adapter,
2020                                                 ((u64)1 << q_vector->v_idx));
2021         }
2022
2023         return work_done;
2024 }
2025
2026 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2027                                      int r_idx)
2028 {
2029         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2030
2031         set_bit(r_idx, q_vector->rxr_idx);
2032         q_vector->rxr_count++;
2033 }
2034
2035 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2036                                      int t_idx)
2037 {
2038         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2039
2040         set_bit(t_idx, q_vector->txr_idx);
2041         q_vector->txr_count++;
2042 }
2043
2044 /**
2045  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2046  * @adapter: board private structure to initialize
2047  * @vectors: allotted vector count for descriptor rings
2048  *
2049  * This function maps descriptor rings to the queue-specific vectors
2050  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2051  * one vector per ring/queue, but on a constrained vector budget, we
2052  * group the rings as "efficiently" as possible.  You would add new
2053  * mapping configurations in here.
2054  **/
2055 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2056                                       int vectors)
2057 {
2058         int v_start = 0;
2059         int rxr_idx = 0, txr_idx = 0;
2060         int rxr_remaining = adapter->num_rx_queues;
2061         int txr_remaining = adapter->num_tx_queues;
2062         int i, j;
2063         int rqpv, tqpv;
2064         int err = 0;
2065
2066         /* No mapping required if MSI-X is disabled. */
2067         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2068                 goto out;
2069
2070         /*
2071          * The ideal configuration...
2072          * We have enough vectors to map one per queue.
2073          */
2074         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2075                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2076                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2077
2078                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2079                         map_vector_to_txq(adapter, v_start, txr_idx);
2080
2081                 goto out;
2082         }
2083
2084         /*
2085          * If we don't have enough vectors for a 1-to-1
2086          * mapping, we'll have to group them so there are
2087          * multiple queues per vector.
2088          */
2089         /* Re-adjusting *qpv takes care of the remainder. */
2090         for (i = v_start; i < vectors; i++) {
2091                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2092                 for (j = 0; j < rqpv; j++) {
2093                         map_vector_to_rxq(adapter, i, rxr_idx);
2094                         rxr_idx++;
2095                         rxr_remaining--;
2096                 }
2097         }
2098         for (i = v_start; i < vectors; i++) {
2099                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2100                 for (j = 0; j < tqpv; j++) {
2101                         map_vector_to_txq(adapter, i, txr_idx);
2102                         txr_idx++;
2103                         txr_remaining--;
2104                 }
2105         }
2106
2107 out:
2108         return err;
2109 }
2110
2111 /**
2112  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2113  * @adapter: board private structure
2114  *
2115  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2116  * interrupts from the kernel.
2117  **/
2118 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2119 {
2120         struct net_device *netdev = adapter->netdev;
2121         irqreturn_t (*handler)(int, void *);
2122         int i, vector, q_vectors, err;
2123         int ri = 0, ti = 0;
2124
2125         /* Decrement for Other and TCP Timer vectors */
2126         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2127
2128         /* Map the Tx/Rx rings to the vectors we were allotted. */
2129         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2130         if (err)
2131                 goto out;
2132
2133 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2134                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2135                          &ixgbe_msix_clean_many)
2136         for (vector = 0; vector < q_vectors; vector++) {
2137                 handler = SET_HANDLER(adapter->q_vector[vector]);
2138
2139                 if (handler == &ixgbe_msix_clean_rx) {
2140                         sprintf(adapter->name[vector], "%s-%s-%d",
2141                                 netdev->name, "rx", ri++);
2142                 } else if (handler == &ixgbe_msix_clean_tx) {
2143                         sprintf(adapter->name[vector], "%s-%s-%d",
2144                                 netdev->name, "tx", ti++);
2145                 } else
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "TxRx", vector);
2148
2149                 err = request_irq(adapter->msix_entries[vector].vector,
2150                                   handler, 0, adapter->name[vector],
2151                                   adapter->q_vector[vector]);
2152                 if (err) {
2153                         e_err(probe, "request_irq failed for MSIX interrupt "
2154                               "Error: %d\n", err);
2155                         goto free_queue_irqs;
2156                 }
2157         }
2158
2159         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2160         err = request_irq(adapter->msix_entries[vector].vector,
2161                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2162         if (err) {
2163                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2164                 goto free_queue_irqs;
2165         }
2166
2167         return 0;
2168
2169 free_queue_irqs:
2170         for (i = vector - 1; i >= 0; i--)
2171                 free_irq(adapter->msix_entries[--vector].vector,
2172                          adapter->q_vector[i]);
2173         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2174         pci_disable_msix(adapter->pdev);
2175         kfree(adapter->msix_entries);
2176         adapter->msix_entries = NULL;
2177 out:
2178         return err;
2179 }
2180
2181 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2182 {
2183         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2184         u8 current_itr;
2185         u32 new_itr = q_vector->eitr;
2186         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2187         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2188
2189         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2190                                             q_vector->tx_itr,
2191                                             tx_ring->total_packets,
2192                                             tx_ring->total_bytes);
2193         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->rx_itr,
2195                                             rx_ring->total_packets,
2196                                             rx_ring->total_bytes);
2197
2198         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2199
2200         switch (current_itr) {
2201         /* counts and packets in update_itr are dependent on these numbers */
2202         case lowest_latency:
2203                 new_itr = 100000;
2204                 break;
2205         case low_latency:
2206                 new_itr = 20000; /* aka hwitr = ~200 */
2207                 break;
2208         case bulk_latency:
2209                 new_itr = 8000;
2210                 break;
2211         default:
2212                 break;
2213         }
2214
2215         if (new_itr != q_vector->eitr) {
2216                 /* do an exponential smoothing */
2217                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2218
2219                 /* save the algorithm value here, not the smoothed one */
2220                 q_vector->eitr = new_itr;
2221
2222                 ixgbe_write_eitr(q_vector);
2223         }
2224 }
2225
2226 /**
2227  * ixgbe_irq_enable - Enable default interrupt generation settings
2228  * @adapter: board private structure
2229  **/
2230 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2231                                     bool flush)
2232 {
2233         u32 mask;
2234
2235         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2236         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2237                 mask |= IXGBE_EIMS_GPI_SDP0;
2238         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2239                 mask |= IXGBE_EIMS_GPI_SDP1;
2240         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2241                 mask |= IXGBE_EIMS_ECC;
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243                 mask |= IXGBE_EIMS_GPI_SDP2;
2244                 if (adapter->num_vfs)
2245                         mask |= IXGBE_EIMS_MAILBOX;
2246         }
2247         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2248             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2249                 mask |= IXGBE_EIMS_FLOW_DIR;
2250
2251         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2252         if (queues)
2253                 ixgbe_irq_enable_queues(adapter, ~0);
2254         if (flush)
2255                 IXGBE_WRITE_FLUSH(&adapter->hw);
2256
2257         if (adapter->num_vfs > 32) {
2258                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2259                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2260         }
2261 }
2262
2263 /**
2264  * ixgbe_intr - legacy mode Interrupt Handler
2265  * @irq: interrupt number
2266  * @data: pointer to a network interface device structure
2267  **/
2268 static irqreturn_t ixgbe_intr(int irq, void *data)
2269 {
2270         struct net_device *netdev = data;
2271         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2272         struct ixgbe_hw *hw = &adapter->hw;
2273         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2274         u32 eicr;
2275
2276         /*
2277          * Workaround for silicon errata on 82598.  Mask the interrupts
2278          * before the read of EICR.
2279          */
2280         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2281
2282         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2283          * therefore no explict interrupt disable is necessary */
2284         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2285         if (!eicr) {
2286                 /*
2287                  * shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM
2290                  * finish the workaround of silicon errata on 82598.  Unmask
2291                  * the interrupt that we masked before the EICR read.
2292                  */
2293                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2294                         ixgbe_irq_enable(adapter, true, true);
2295                 return IRQ_NONE;        /* Not our interrupt */
2296         }
2297
2298         if (eicr & IXGBE_EICR_LSC)
2299                 ixgbe_check_lsc(adapter);
2300
2301         if (hw->mac.type == ixgbe_mac_82599EB)
2302                 ixgbe_check_sfp_event(adapter, eicr);
2303
2304         ixgbe_check_fan_failure(adapter, eicr);
2305         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2306             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2307                 schedule_work(&adapter->check_overtemp_task);
2308
2309         if (napi_schedule_prep(&(q_vector->napi))) {
2310                 adapter->tx_ring[0]->total_packets = 0;
2311                 adapter->tx_ring[0]->total_bytes = 0;
2312                 adapter->rx_ring[0]->total_packets = 0;
2313                 adapter->rx_ring[0]->total_bytes = 0;
2314                 /* would disable interrupts here but EIAM disabled it */
2315                 __napi_schedule(&(q_vector->napi));
2316         }
2317
2318         /*
2319          * re-enable link(maybe) and non-queue interrupts, no flush.
2320          * ixgbe_poll will re-enable the queue interrupts
2321          */
2322
2323         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2324                 ixgbe_irq_enable(adapter, false, false);
2325
2326         return IRQ_HANDLED;
2327 }
2328
2329 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2330 {
2331         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2332
2333         for (i = 0; i < q_vectors; i++) {
2334                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2335                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2336                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2337                 q_vector->rxr_count = 0;
2338                 q_vector->txr_count = 0;
2339         }
2340 }
2341
2342 /**
2343  * ixgbe_request_irq - initialize interrupts
2344  * @adapter: board private structure
2345  *
2346  * Attempts to configure interrupts using the best available
2347  * capabilities of the hardware and kernel.
2348  **/
2349 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2350 {
2351         struct net_device *netdev = adapter->netdev;
2352         int err;
2353
2354         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2355                 err = ixgbe_request_msix_irqs(adapter);
2356         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2357                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2358                                   netdev->name, netdev);
2359         } else {
2360                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2361                                   netdev->name, netdev);
2362         }
2363
2364         if (err)
2365                 e_err(probe, "request_irq failed, Error %d\n", err);
2366
2367         return err;
2368 }
2369
2370 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2371 {
2372         struct net_device *netdev = adapter->netdev;
2373
2374         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2375                 int i, q_vectors;
2376
2377                 q_vectors = adapter->num_msix_vectors;
2378
2379                 i = q_vectors - 1;
2380                 free_irq(adapter->msix_entries[i].vector, netdev);
2381
2382                 i--;
2383                 for (; i >= 0; i--) {
2384                         free_irq(adapter->msix_entries[i].vector,
2385                                  adapter->q_vector[i]);
2386                 }
2387
2388                 ixgbe_reset_q_vectors(adapter);
2389         } else {
2390                 free_irq(adapter->pdev->irq, netdev);
2391         }
2392 }
2393
2394 /**
2395  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2396  * @adapter: board private structure
2397  **/
2398 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2399 {
2400         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2401                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2402         } else {
2403                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2404                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2405                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2406                 if (adapter->num_vfs > 32)
2407                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2408         }
2409         IXGBE_WRITE_FLUSH(&adapter->hw);
2410         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2411                 int i;
2412                 for (i = 0; i < adapter->num_msix_vectors; i++)
2413                         synchronize_irq(adapter->msix_entries[i].vector);
2414         } else {
2415                 synchronize_irq(adapter->pdev->irq);
2416         }
2417 }
2418
2419 /**
2420  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2421  *
2422  **/
2423 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2424 {
2425         struct ixgbe_hw *hw = &adapter->hw;
2426
2427         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2428                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2429
2430         ixgbe_set_ivar(adapter, 0, 0, 0);
2431         ixgbe_set_ivar(adapter, 1, 0, 0);
2432
2433         map_vector_to_rxq(adapter, 0, 0);
2434         map_vector_to_txq(adapter, 0, 0);
2435
2436         e_info(hw, "Legacy interrupt IVAR setup done\n");
2437 }
2438
2439 /**
2440  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2441  * @adapter: board private structure
2442  * @ring: structure containing ring specific data
2443  *
2444  * Configure the Tx descriptor ring after a reset.
2445  **/
2446 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2447                              struct ixgbe_ring *ring)
2448 {
2449         struct ixgbe_hw *hw = &adapter->hw;
2450         u64 tdba = ring->dma;
2451         int wait_loop = 10;
2452         u32 txdctl;
2453         u16 reg_idx = ring->reg_idx;
2454
2455         /* disable queue to avoid issues while updating state */
2456         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2457         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2458                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2459         IXGBE_WRITE_FLUSH(hw);
2460
2461         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2462                         (tdba & DMA_BIT_MASK(32)));
2463         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2464         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2465                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2466         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2467         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2468         ring->head = IXGBE_TDH(reg_idx);
2469         ring->tail = IXGBE_TDT(reg_idx);
2470
2471         /* configure fetching thresholds */
2472         if (adapter->rx_itr_setting == 0) {
2473                 /* cannot set wthresh when itr==0 */
2474                 txdctl &= ~0x007F0000;
2475         } else {
2476                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2477                 txdctl |= (8 << 16);
2478         }
2479         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2480                 /* PThresh workaround for Tx hang with DFP enabled. */
2481                 txdctl |= 32;
2482         }
2483
2484         /* reinitialize flowdirector state */
2485         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2486
2487         /* enable queue */
2488         txdctl |= IXGBE_TXDCTL_ENABLE;
2489         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2490
2491         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2492         if (hw->mac.type == ixgbe_mac_82598EB &&
2493             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2494                 return;
2495
2496         /* poll to verify queue is enabled */
2497         do {
2498                 msleep(1);
2499                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2500         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2501         if (!wait_loop)
2502                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2503 }
2504
2505 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2506 {
2507         struct ixgbe_hw *hw = &adapter->hw;
2508         u32 rttdcs;
2509         u32 mask;
2510
2511         if (hw->mac.type == ixgbe_mac_82598EB)
2512                 return;
2513
2514         /* disable the arbiter while setting MTQC */
2515         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2516         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2517         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2518
2519         /* set transmit pool layout */
2520         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2521         switch (adapter->flags & mask) {
2522
2523         case (IXGBE_FLAG_SRIOV_ENABLED):
2524                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2525                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2526                 break;
2527
2528         case (IXGBE_FLAG_DCB_ENABLED):
2529                 /* We enable 8 traffic classes, DCB only */
2530                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2531                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2532                 break;
2533
2534         default:
2535                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2536                 break;
2537         }
2538
2539         /* re-enable the arbiter */
2540         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2541         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2542 }
2543
2544 /**
2545  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2546  * @adapter: board private structure
2547  *
2548  * Configure the Tx unit of the MAC after a reset.
2549  **/
2550 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2551 {
2552         struct ixgbe_hw *hw = &adapter->hw;
2553         u32 dmatxctl;
2554         u32 i;
2555
2556         ixgbe_setup_mtqc(adapter);
2557
2558         if (hw->mac.type != ixgbe_mac_82598EB) {
2559                 /* DMATXCTL.EN must be before Tx queues are enabled */
2560                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2561                 dmatxctl |= IXGBE_DMATXCTL_TE;
2562                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2563         }
2564
2565         /* Setup the HW Tx Head and Tail descriptor pointers */
2566         for (i = 0; i < adapter->num_tx_queues; i++)
2567                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2568 }
2569
2570 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2571
2572 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2573                                    struct ixgbe_ring *rx_ring)
2574 {
2575         u32 srrctl;
2576         int index;
2577         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2578
2579         index = rx_ring->reg_idx;
2580         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2581                 unsigned long mask;
2582                 mask = (unsigned long) feature[RING_F_RSS].mask;
2583                 index = index & mask;
2584         }
2585         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2586
2587         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2588         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2589         if (adapter->num_vfs)
2590                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2591
2592         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2593                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2594
2595         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2596 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2597                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2598 #else
2599                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2600 #endif
2601                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2602         } else {
2603                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2604                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2605                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2606         }
2607
2608         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2609 }
2610
2611 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2612 {
2613         struct ixgbe_hw *hw = &adapter->hw;
2614         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2615                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2616                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2617         u32 mrqc = 0, reta = 0;
2618         u32 rxcsum;
2619         int i, j;
2620         int mask;
2621
2622         /* Fill out hash function seeds */
2623         for (i = 0; i < 10; i++)
2624                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2625
2626         /* Fill out redirection table */
2627         for (i = 0, j = 0; i < 128; i++, j++) {
2628                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2629                         j = 0;
2630                 /* reta = 4-byte sliding window of
2631                  * 0x00..(indices-1)(indices-1)00..etc. */
2632                 reta = (reta << 8) | (j * 0x11);
2633                 if ((i & 3) == 3)
2634                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2635         }
2636
2637         /* Disable indicating checksum in descriptor, enables RSS hash */
2638         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2639         rxcsum |= IXGBE_RXCSUM_PCSD;
2640         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2641
2642         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2643                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2644         else
2645                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2646 #ifdef CONFIG_IXGBE_DCB
2647                                          | IXGBE_FLAG_DCB_ENABLED
2648 #endif
2649                                          | IXGBE_FLAG_SRIOV_ENABLED
2650                                         );
2651
2652         switch (mask) {
2653         case (IXGBE_FLAG_RSS_ENABLED):
2654                 mrqc = IXGBE_MRQC_RSSEN;
2655                 break;
2656         case (IXGBE_FLAG_SRIOV_ENABLED):
2657                 mrqc = IXGBE_MRQC_VMDQEN;
2658                 break;
2659 #ifdef CONFIG_IXGBE_DCB
2660         case (IXGBE_FLAG_DCB_ENABLED):
2661                 mrqc = IXGBE_MRQC_RT8TCEN;
2662                 break;
2663 #endif /* CONFIG_IXGBE_DCB */
2664         default:
2665                 break;
2666         }
2667
2668         /* Perform hash on these packet types */
2669         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2670               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2671               | IXGBE_MRQC_RSS_FIELD_IPV6
2672               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2673
2674         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2675 }
2676
2677 /**
2678  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2679  * @adapter:    address of board private structure
2680  * @index:      index of ring to set
2681  **/
2682 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2683                                    struct ixgbe_ring *ring)
2684 {
2685         struct ixgbe_hw *hw = &adapter->hw;
2686         u32 rscctrl;
2687         int rx_buf_len;
2688         u16 reg_idx = ring->reg_idx;
2689
2690         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2691                 return;
2692
2693         rx_buf_len = ring->rx_buf_len;
2694         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2695         rscctrl |= IXGBE_RSCCTL_RSCEN;
2696         /*
2697          * we must limit the number of descriptors so that the
2698          * total size of max desc * buf_len is not greater
2699          * than 65535
2700          */
2701         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2702 #if (MAX_SKB_FRAGS > 16)
2703                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2704 #elif (MAX_SKB_FRAGS > 8)
2705                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2706 #elif (MAX_SKB_FRAGS > 4)
2707                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2708 #else
2709                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2710 #endif
2711         } else {
2712                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2713                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2714                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2715                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2716                 else
2717                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2718         }
2719         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2720 }
2721
2722 /**
2723  *  ixgbe_set_uta - Set unicast filter table address
2724  *  @adapter: board private structure
2725  *
2726  *  The unicast table address is a register array of 32-bit registers.
2727  *  The table is meant to be used in a way similar to how the MTA is used
2728  *  however due to certain limitations in the hardware it is necessary to
2729  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2730  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2731  **/
2732 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2733 {
2734         struct ixgbe_hw *hw = &adapter->hw;
2735         int i;
2736
2737         /* The UTA table only exists on 82599 hardware and newer */
2738         if (hw->mac.type < ixgbe_mac_82599EB)
2739                 return;
2740
2741         /* we only need to do this if VMDq is enabled */
2742         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2743                 return;
2744
2745         for (i = 0; i < 128; i++)
2746                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2747 }
2748
2749 #define IXGBE_MAX_RX_DESC_POLL 10
2750 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2751                                        struct ixgbe_ring *ring)
2752 {
2753         struct ixgbe_hw *hw = &adapter->hw;
2754         int reg_idx = ring->reg_idx;
2755         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2756         u32 rxdctl;
2757
2758         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2759         if (hw->mac.type == ixgbe_mac_82598EB &&
2760             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2761                 return;
2762
2763         do {
2764                 msleep(1);
2765                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2766         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2767
2768         if (!wait_loop) {
2769                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2770                       "the polling period\n", reg_idx);
2771         }
2772 }
2773
2774 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2775                              struct ixgbe_ring *ring)
2776 {
2777         struct ixgbe_hw *hw = &adapter->hw;
2778         u64 rdba = ring->dma;
2779         u32 rxdctl;
2780         u16 reg_idx = ring->reg_idx;
2781
2782         /* disable queue to avoid issues while updating state */
2783         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2784         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2785                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2786         IXGBE_WRITE_FLUSH(hw);
2787
2788         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2789         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2790         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2791                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2792         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2793         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2794         ring->head = IXGBE_RDH(reg_idx);
2795         ring->tail = IXGBE_RDT(reg_idx);
2796
2797         ixgbe_configure_srrctl(adapter, ring);
2798         ixgbe_configure_rscctl(adapter, ring);
2799
2800         if (hw->mac.type == ixgbe_mac_82598EB) {
2801                 /*
2802                  * enable cache line friendly hardware writes:
2803                  * PTHRESH=32 descriptors (half the internal cache),
2804                  * this also removes ugly rx_no_buffer_count increment
2805                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2806                  * WTHRESH=8 burst writeback up to two cache lines
2807                  */
2808                 rxdctl &= ~0x3FFFFF;
2809                 rxdctl |=  0x080420;
2810         }
2811
2812         /* enable receive descriptor ring */
2813         rxdctl |= IXGBE_RXDCTL_ENABLE;
2814         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2815
2816         ixgbe_rx_desc_queue_enable(adapter, ring);
2817         ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2818 }
2819
2820 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2821 {
2822         struct ixgbe_hw *hw = &adapter->hw;
2823         int p;
2824
2825         /* PSRTYPE must be initialized in non 82598 adapters */
2826         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2827                       IXGBE_PSRTYPE_UDPHDR |
2828                       IXGBE_PSRTYPE_IPV4HDR |
2829                       IXGBE_PSRTYPE_L2HDR |
2830                       IXGBE_PSRTYPE_IPV6HDR;
2831
2832         if (hw->mac.type == ixgbe_mac_82598EB)
2833                 return;
2834
2835         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2836                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2837
2838         for (p = 0; p < adapter->num_rx_pools; p++)
2839                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2840                                 psrtype);
2841 }
2842
2843 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2844 {
2845         struct ixgbe_hw *hw = &adapter->hw;
2846         u32 gcr_ext;
2847         u32 vt_reg_bits;
2848         u32 reg_offset, vf_shift;
2849         u32 vmdctl;
2850
2851         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2852                 return;
2853
2854         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2855         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2856         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2857         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2858
2859         vf_shift = adapter->num_vfs % 32;
2860         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2861
2862         /* Enable only the PF's pool for Tx/Rx */
2863         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2864         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2865         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2866         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2867         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2868
2869         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2870         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2871
2872         /*
2873          * Set up VF register offsets for selected VT Mode,
2874          * i.e. 32 or 64 VFs for SR-IOV
2875          */
2876         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2877         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2878         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2879         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2880
2881         /* enable Tx loopback for VF/PF communication */
2882         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2883 }
2884
2885 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2886 {
2887         struct ixgbe_hw *hw = &adapter->hw;
2888         struct net_device *netdev = adapter->netdev;
2889         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2890         int rx_buf_len;
2891         struct ixgbe_ring *rx_ring;
2892         int i;
2893         u32 mhadd, hlreg0;
2894
2895         /* Decide whether to use packet split mode or not */
2896         /* Do not use packet split if we're in SR-IOV Mode */
2897         if (!adapter->num_vfs)
2898                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2899
2900         /* Set the RX buffer length according to the mode */
2901         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2902                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2903         } else {
2904                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2905                     (netdev->mtu <= ETH_DATA_LEN))
2906                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2907                 else
2908                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2909         }
2910
2911 #ifdef IXGBE_FCOE
2912         /* adjust max frame to be able to do baby jumbo for FCoE */
2913         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2914             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2915                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2916
2917 #endif /* IXGBE_FCOE */
2918         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2919         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2920                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2921                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2922
2923                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2924         }
2925
2926         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2927         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2928         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2929         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2930
2931         /*
2932          * Setup the HW Rx Head and Tail Descriptor Pointers and
2933          * the Base and Length of the Rx Descriptor Ring
2934          */
2935         for (i = 0; i < adapter->num_rx_queues; i++) {
2936                 rx_ring = adapter->rx_ring[i];
2937                 rx_ring->rx_buf_len = rx_buf_len;
2938
2939                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2940                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2941                 else
2942                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2943
2944 #ifdef IXGBE_FCOE
2945                 if (netdev->features & NETIF_F_FCOE_MTU) {
2946                         struct ixgbe_ring_feature *f;
2947                         f = &adapter->ring_feature[RING_F_FCOE];
2948                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2949                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2950                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2951                                         rx_ring->rx_buf_len =
2952                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2953                         }
2954                 }
2955 #endif /* IXGBE_FCOE */
2956         }
2957
2958 }
2959
2960 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2961 {
2962         struct ixgbe_hw *hw = &adapter->hw;
2963         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2964
2965         switch (hw->mac.type) {
2966         case ixgbe_mac_82598EB:
2967                 /*
2968                  * For VMDq support of different descriptor types or
2969                  * buffer sizes through the use of multiple SRRCTL
2970                  * registers, RDRXCTL.MVMEN must be set to 1
2971                  *
2972                  * also, the manual doesn't mention it clearly but DCA hints
2973                  * will only use queue 0's tags unless this bit is set.  Side
2974                  * effects of setting this bit are only that SRRCTL must be
2975                  * fully programmed [0..15]
2976                  */
2977                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2978                 break;
2979         case ixgbe_mac_82599EB:
2980                 /* Disable RSC for ACK packets */
2981                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2982                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2983                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2984                 /* hardware requires some bits to be set by default */
2985                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2986                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2987                 break;
2988         default:
2989                 /* We should do nothing since we don't know this hardware */
2990                 return;
2991         }
2992
2993         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2994 }
2995
2996 /**
2997  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2998  * @adapter: board private structure
2999  *
3000  * Configure the Rx unit of the MAC after a reset.
3001  **/
3002 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3003 {
3004         struct ixgbe_hw *hw = &adapter->hw;
3005         int i;
3006         u32 rxctrl;
3007
3008         /* disable receives while setting up the descriptors */
3009         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3010         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3011
3012         ixgbe_setup_psrtype(adapter);
3013         ixgbe_setup_rdrxctl(adapter);
3014
3015         /* Program registers for the distribution of queues */
3016         ixgbe_setup_mrqc(adapter);
3017
3018         ixgbe_set_uta(adapter);
3019
3020         /* set_rx_buffer_len must be called before ring initialization */
3021         ixgbe_set_rx_buffer_len(adapter);
3022
3023         /*
3024          * Setup the HW Rx Head and Tail Descriptor Pointers and
3025          * the Base and Length of the Rx Descriptor Ring
3026          */
3027         for (i = 0; i < adapter->num_rx_queues; i++)
3028                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3029
3030         /* disable drop enable for 82598 parts */
3031         if (hw->mac.type == ixgbe_mac_82598EB)
3032                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3033
3034         /* enable all receives */
3035         rxctrl |= IXGBE_RXCTRL_RXEN;
3036         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3037 }
3038
3039 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3040 {
3041         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3042         struct ixgbe_hw *hw = &adapter->hw;
3043         int pool_ndx = adapter->num_vfs;
3044
3045         /* add VID to filter table */
3046         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3047         set_bit(vid, adapter->active_vlans);
3048 }
3049
3050 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3051 {
3052         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3053         struct ixgbe_hw *hw = &adapter->hw;
3054         int pool_ndx = adapter->num_vfs;
3055
3056         /* remove VID from filter table */
3057         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3058         clear_bit(vid, adapter->active_vlans);
3059 }
3060
3061 /**
3062  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3063  * @adapter: driver data
3064  */
3065 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3066 {
3067         struct ixgbe_hw *hw = &adapter->hw;
3068         u32 vlnctrl;
3069
3070         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3071         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3072         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3073 }
3074
3075 /**
3076  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3077  * @adapter: driver data
3078  */
3079 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3080 {
3081         struct ixgbe_hw *hw = &adapter->hw;
3082         u32 vlnctrl;
3083
3084         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3085         vlnctrl |= IXGBE_VLNCTRL_VFE;
3086         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3087         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3088 }
3089
3090 /**
3091  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3092  * @adapter: driver data
3093  */
3094 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3095 {
3096         struct ixgbe_hw *hw = &adapter->hw;
3097         u32 vlnctrl;
3098         int i, j;
3099
3100         switch (hw->mac.type) {
3101         case ixgbe_mac_82598EB:
3102                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3103                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3104                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3105                 break;
3106         case ixgbe_mac_82599EB:
3107                 for (i = 0; i < adapter->num_rx_queues; i++) {
3108                         j = adapter->rx_ring[i]->reg_idx;
3109                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3110                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3111                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3112                 }
3113                 break;
3114         default:
3115                 break;
3116         }
3117 }
3118
3119 /**
3120  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3121  * @adapter: driver data
3122  */
3123 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3124 {
3125         struct ixgbe_hw *hw = &adapter->hw;
3126         u32 vlnctrl;
3127         int i, j;
3128
3129         switch (hw->mac.type) {
3130         case ixgbe_mac_82598EB:
3131                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3132                 vlnctrl |= IXGBE_VLNCTRL_VME;
3133                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3134                 break;
3135         case ixgbe_mac_82599EB:
3136                 for (i = 0; i < adapter->num_rx_queues; i++) {
3137                         j = adapter->rx_ring[i]->reg_idx;
3138                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3139                         vlnctrl |= IXGBE_RXDCTL_VME;
3140                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3141                 }
3142                 break;
3143         default:
3144                 break;
3145         }
3146 }
3147
3148 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3149 {
3150         u16 vid;
3151
3152         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3153
3154         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3155                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3156 }
3157
3158 /**
3159  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3160  * @netdev: network interface device structure
3161  *
3162  * Writes unicast address list to the RAR table.
3163  * Returns: -ENOMEM on failure/insufficient address space
3164  *                0 on no addresses written
3165  *                X on writing X addresses to the RAR table
3166  **/
3167 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3168 {
3169         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3170         struct ixgbe_hw *hw = &adapter->hw;
3171         unsigned int vfn = adapter->num_vfs;
3172         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3173         int count = 0;
3174
3175         /* return ENOMEM indicating insufficient memory for addresses */
3176         if (netdev_uc_count(netdev) > rar_entries)
3177                 return -ENOMEM;
3178
3179         if (!netdev_uc_empty(netdev) && rar_entries) {
3180                 struct netdev_hw_addr *ha;
3181                 /* return error if we do not support writing to RAR table */
3182                 if (!hw->mac.ops.set_rar)
3183                         return -ENOMEM;
3184
3185                 netdev_for_each_uc_addr(ha, netdev) {
3186                         if (!rar_entries)
3187                                 break;
3188                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3189                                             vfn, IXGBE_RAH_AV);
3190                         count++;
3191                 }
3192         }
3193         /* write the addresses in reverse order to avoid write combining */
3194         for (; rar_entries > 0 ; rar_entries--)
3195                 hw->mac.ops.clear_rar(hw, rar_entries);
3196
3197         return count;
3198 }
3199
3200 /**
3201  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3202  * @netdev: network interface device structure
3203  *
3204  * The set_rx_method entry point is called whenever the unicast/multicast
3205  * address list or the network interface flags are updated.  This routine is
3206  * responsible for configuring the hardware for proper unicast, multicast and
3207  * promiscuous mode.
3208  **/
3209 void ixgbe_set_rx_mode(struct net_device *netdev)
3210 {
3211         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3212         struct ixgbe_hw *hw = &adapter->hw;
3213         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3214         int count;
3215
3216         /* Check for Promiscuous and All Multicast modes */
3217
3218         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3219
3220         /* set all bits that we expect to always be set */
3221         fctrl |= IXGBE_FCTRL_BAM;
3222         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3223         fctrl |= IXGBE_FCTRL_PMCF;
3224
3225         /* clear the bits we are changing the status of */
3226         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3227
3228         if (netdev->flags & IFF_PROMISC) {
3229                 hw->addr_ctrl.user_set_promisc = true;
3230                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3231                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3232                 /* don't hardware filter vlans in promisc mode */
3233                 ixgbe_vlan_filter_disable(adapter);
3234         } else {
3235                 if (netdev->flags & IFF_ALLMULTI) {
3236                         fctrl |= IXGBE_FCTRL_MPE;
3237                         vmolr |= IXGBE_VMOLR_MPE;
3238                 } else {
3239                         /*
3240                          * Write addresses to the MTA, if the attempt fails
3241                          * then we should just turn on promiscous mode so
3242                          * that we can at least receive multicast traffic
3243                          */
3244                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3245                         vmolr |= IXGBE_VMOLR_ROMPE;
3246                 }
3247                 ixgbe_vlan_filter_enable(adapter);
3248                 hw->addr_ctrl.user_set_promisc = false;
3249                 /*
3250                  * Write addresses to available RAR registers, if there is not
3251                  * sufficient space to store all the addresses then enable
3252                  * unicast promiscous mode
3253                  */
3254                 count = ixgbe_write_uc_addr_list(netdev);
3255                 if (count < 0) {
3256                         fctrl |= IXGBE_FCTRL_UPE;
3257                         vmolr |= IXGBE_VMOLR_ROPE;
3258                 }
3259         }
3260
3261         if (adapter->num_vfs) {
3262                 ixgbe_restore_vf_multicasts(adapter);
3263                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3264                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3265                            IXGBE_VMOLR_ROPE);
3266                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3267         }
3268
3269         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3270
3271         if (netdev->features & NETIF_F_HW_VLAN_RX)
3272                 ixgbe_vlan_strip_enable(adapter);
3273         else
3274                 ixgbe_vlan_strip_disable(adapter);
3275 }
3276
3277 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3278 {
3279         int q_idx;
3280         struct ixgbe_q_vector *q_vector;
3281         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3282
3283         /* legacy and MSI only use one vector */
3284         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3285                 q_vectors = 1;
3286
3287         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3288                 struct napi_struct *napi;
3289                 q_vector = adapter->q_vector[q_idx];
3290                 napi = &q_vector->napi;
3291                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3292                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3293                                 if (q_vector->txr_count == 1)
3294                                         napi->poll = &ixgbe_clean_txonly;
3295                                 else if (q_vector->rxr_count == 1)
3296                                         napi->poll = &ixgbe_clean_rxonly;
3297                         }
3298                 }
3299
3300                 napi_enable(napi);
3301         }
3302 }
3303
3304 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3305 {
3306         int q_idx;
3307         struct ixgbe_q_vector *q_vector;
3308         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3309
3310         /* legacy and MSI only use one vector */
3311         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3312                 q_vectors = 1;
3313
3314         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3315                 q_vector = adapter->q_vector[q_idx];
3316                 napi_disable(&q_vector->napi);
3317         }
3318 }
3319
3320 #ifdef CONFIG_IXGBE_DCB
3321 /*
3322  * ixgbe_configure_dcb - Configure DCB hardware
3323  * @adapter: ixgbe adapter struct
3324  *
3325  * This is called by the driver on open to configure the DCB hardware.
3326  * This is also called by the gennetlink interface when reconfiguring
3327  * the DCB state.
3328  */
3329 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3330 {
3331         struct ixgbe_hw *hw = &adapter->hw;
3332         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3333         u32 txdctl;
3334         int i, j;
3335
3336         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3337                 if (hw->mac.type == ixgbe_mac_82598EB)
3338                         netif_set_gso_max_size(adapter->netdev, 65536);
3339                 return;
3340         }
3341
3342         if (hw->mac.type == ixgbe_mac_82598EB)
3343                 netif_set_gso_max_size(adapter->netdev, 32768);
3344
3345 #ifdef CONFIG_FCOE
3346         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3347                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3348 #endif
3349
3350         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3351                                         DCB_TX_CONFIG);
3352         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3353                                         DCB_RX_CONFIG);
3354
3355         /* reconfigure the hardware */
3356         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3357
3358         for (i = 0; i < adapter->num_tx_queues; i++) {
3359                 j = adapter->tx_ring[i]->reg_idx;
3360                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3361                 /* PThresh workaround for Tx hang with DFP enabled. */
3362                 txdctl |= 32;
3363                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3364         }
3365         /* Enable VLAN tag insert/strip */
3366         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3367
3368         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3369 }
3370
3371 #endif
3372 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3373 {
3374         struct net_device *netdev = adapter->netdev;
3375         struct ixgbe_hw *hw = &adapter->hw;
3376         int i;
3377
3378 #ifdef CONFIG_IXGBE_DCB
3379         ixgbe_configure_dcb(adapter);
3380 #endif
3381
3382         ixgbe_set_rx_mode(netdev);
3383         ixgbe_restore_vlan(adapter);
3384
3385 #ifdef IXGBE_FCOE
3386         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3387                 ixgbe_configure_fcoe(adapter);
3388
3389 #endif /* IXGBE_FCOE */
3390         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3391                 for (i = 0; i < adapter->num_tx_queues; i++)
3392                         adapter->tx_ring[i]->atr_sample_rate =
3393                                                        adapter->atr_sample_rate;
3394                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3395         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3396                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3397         }
3398         ixgbe_configure_virtualization(adapter);
3399
3400         ixgbe_configure_tx(adapter);
3401         ixgbe_configure_rx(adapter);
3402 }
3403
3404 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3405 {
3406         switch (hw->phy.type) {
3407         case ixgbe_phy_sfp_avago:
3408         case ixgbe_phy_sfp_ftl:
3409         case ixgbe_phy_sfp_intel:
3410         case ixgbe_phy_sfp_unknown:
3411         case ixgbe_phy_sfp_passive_tyco:
3412         case ixgbe_phy_sfp_passive_unknown:
3413         case ixgbe_phy_sfp_active_unknown:
3414         case ixgbe_phy_sfp_ftl_active:
3415                 return true;
3416         default:
3417                 return false;
3418         }
3419 }
3420
3421 /**
3422  * ixgbe_sfp_link_config - set up SFP+ link
3423  * @adapter: pointer to private adapter struct
3424  **/
3425 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3426 {
3427         struct ixgbe_hw *hw = &adapter->hw;
3428
3429                 if (hw->phy.multispeed_fiber) {
3430                         /*
3431                          * In multispeed fiber setups, the device may not have
3432                          * had a physical connection when the driver loaded.
3433                          * If that's the case, the initial link configuration
3434                          * couldn't get the MAC into 10G or 1G mode, so we'll
3435                          * never have a link status change interrupt fire.
3436                          * We need to try and force an autonegotiation
3437                          * session, then bring up link.
3438                          */
3439                         hw->mac.ops.setup_sfp(hw);
3440                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3441                                 schedule_work(&adapter->multispeed_fiber_task);
3442                 } else {
3443                         /*
3444                          * Direct Attach Cu and non-multispeed fiber modules
3445                          * still need to be configured properly prior to
3446                          * attempting link.
3447                          */
3448                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3449                                 schedule_work(&adapter->sfp_config_module_task);
3450                 }
3451 }
3452
3453 /**
3454  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3455  * @hw: pointer to private hardware struct
3456  *
3457  * Returns 0 on success, negative on failure
3458  **/
3459 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3460 {
3461         u32 autoneg;
3462         bool negotiation, link_up = false;
3463         u32 ret = IXGBE_ERR_LINK_SETUP;
3464
3465         if (hw->mac.ops.check_link)
3466                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3467
3468         if (ret)
3469                 goto link_cfg_out;
3470
3471         if (hw->mac.ops.get_link_capabilities)
3472                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3473                                                         &negotiation);
3474         if (ret)
3475                 goto link_cfg_out;
3476
3477         if (hw->mac.ops.setup_link)
3478                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3479 link_cfg_out:
3480         return ret;
3481 }
3482
3483 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3484 {
3485         struct ixgbe_hw *hw = &adapter->hw;
3486         u32 gpie = 0;
3487
3488         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3489                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3490                        IXGBE_GPIE_OCD;
3491                 gpie |= IXGBE_GPIE_EIAME;
3492                 /*
3493                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3494                  * this saves a register write for every interrupt
3495                  */
3496                 switch (hw->mac.type) {
3497                 case ixgbe_mac_82598EB:
3498                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3499                         break;
3500                 default:
3501                 case ixgbe_mac_82599EB:
3502                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3503                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3504                         break;
3505                 }
3506         } else {
3507                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3508                  * specifically only auto mask tx and rx interrupts */
3509                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3510         }
3511
3512         /* XXX: to interrupt immediately for EICS writes, enable this */
3513         /* gpie |= IXGBE_GPIE_EIMEN; */
3514
3515         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3516                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3517                 gpie |= IXGBE_GPIE_VTMODE_64;
3518         }
3519
3520         /* Enable fan failure interrupt */
3521         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3522                 gpie |= IXGBE_SDP1_GPIEN;
3523
3524         if (hw->mac.type == ixgbe_mac_82599EB)
3525                 gpie |= IXGBE_SDP1_GPIEN;
3526                 gpie |= IXGBE_SDP2_GPIEN;
3527
3528         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3529 }
3530
3531 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3532 {
3533         struct ixgbe_hw *hw = &adapter->hw;
3534         int err;
3535         u32 ctrl_ext;
3536
3537         ixgbe_get_hw_control(adapter);
3538         ixgbe_setup_gpie(adapter);
3539
3540         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3541                 ixgbe_configure_msix(adapter);
3542         else
3543                 ixgbe_configure_msi_and_legacy(adapter);
3544
3545         /* enable the optics */
3546         if (hw->phy.multispeed_fiber)
3547                 hw->mac.ops.enable_tx_laser(hw);
3548
3549         clear_bit(__IXGBE_DOWN, &adapter->state);
3550         ixgbe_napi_enable_all(adapter);
3551
3552         /* clear any pending interrupts, may auto mask */
3553         IXGBE_READ_REG(hw, IXGBE_EICR);
3554         ixgbe_irq_enable(adapter, true, true);
3555
3556         /*
3557          * If this adapter has a fan, check to see if we had a failure
3558          * before we enabled the interrupt.
3559          */
3560         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3561                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3562                 if (esdp & IXGBE_ESDP_SDP1)
3563                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3564         }
3565
3566         /*
3567          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3568          * arrived before interrupts were enabled but after probe.  Such
3569          * devices wouldn't have their type identified yet. We need to
3570          * kick off the SFP+ module setup first, then try to bring up link.
3571          * If we're not hot-pluggable SFP+, we just need to configure link
3572          * and bring it up.
3573          */
3574         if (hw->phy.type == ixgbe_phy_unknown) {
3575                 err = hw->phy.ops.identify(hw);
3576                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3577                         /*
3578                          * Take the device down and schedule the sfp tasklet
3579                          * which will unregister_netdev and log it.
3580                          */
3581                         ixgbe_down(adapter);
3582                         schedule_work(&adapter->sfp_config_module_task);
3583                         return err;
3584                 }
3585         }
3586
3587         if (ixgbe_is_sfp(hw)) {
3588                 ixgbe_sfp_link_config(adapter);
3589         } else {
3590                 err = ixgbe_non_sfp_link_config(hw);
3591                 if (err)
3592                         e_err(probe, "link_config FAILED %d\n", err);
3593         }
3594
3595         /* enable transmits */
3596         netif_tx_start_all_queues(adapter->netdev);
3597
3598         /* bring the link up in the watchdog, this could race with our first
3599          * link up interrupt but shouldn't be a problem */
3600         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3601         adapter->link_check_timeout = jiffies;
3602         mod_timer(&adapter->watchdog_timer, jiffies);
3603
3604         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3605         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3606         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3607         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3608
3609         return 0;
3610 }
3611
3612 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3613 {
3614         WARN_ON(in_interrupt());
3615         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3616                 msleep(1);
3617         ixgbe_down(adapter);
3618         /*
3619          * If SR-IOV enabled then wait a bit before bringing the adapter
3620          * back up to give the VFs time to respond to the reset.  The
3621          * two second wait is based upon the watchdog timer cycle in
3622          * the VF driver.
3623          */
3624         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3625                 msleep(2000);
3626         ixgbe_up(adapter);
3627         clear_bit(__IXGBE_RESETTING, &adapter->state);
3628 }
3629
3630 int ixgbe_up(struct ixgbe_adapter *adapter)
3631 {
3632         /* hardware has been reset, we need to reload some things */
3633         ixgbe_configure(adapter);
3634
3635         return ixgbe_up_complete(adapter);
3636 }
3637
3638 void ixgbe_reset(struct ixgbe_adapter *adapter)
3639 {
3640         struct ixgbe_hw *hw = &adapter->hw;
3641         int err;
3642
3643         err = hw->mac.ops.init_hw(hw);
3644         switch (err) {
3645         case 0:
3646         case IXGBE_ERR_SFP_NOT_PRESENT:
3647                 break;
3648         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3649                 e_dev_err("master disable timed out\n");
3650                 break;
3651         case IXGBE_ERR_EEPROM_VERSION:
3652                 /* We are running on a pre-production device, log a warning */
3653                 e_dev_warn("This device is a pre-production adapter/LOM. "
3654                            "Please be aware there may be issuesassociated with "
3655                            "your hardware.  If you are experiencing problems "
3656                            "please contact your Intel or hardware "
3657                            "representative who provided you with this "
3658                            "hardware.\n");
3659                 break;
3660         default:
3661                 e_dev_err("Hardware Error: %d\n", err);
3662         }
3663
3664         /* reprogram the RAR[0] in case user changed it. */
3665         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3666                             IXGBE_RAH_AV);
3667 }
3668
3669 /**
3670  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3671  * @adapter: board private structure
3672  * @rx_ring: ring to free buffers from
3673  **/
3674 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3675                                 struct ixgbe_ring *rx_ring)
3676 {
3677         struct pci_dev *pdev = adapter->pdev;
3678         unsigned long size;
3679         unsigned int i;
3680
3681         /* ring already cleared, nothing to do */
3682         if (!rx_ring->rx_buffer_info)
3683                 return;
3684
3685         /* Free all the Rx ring sk_buffs */
3686         for (i = 0; i < rx_ring->count; i++) {
3687                 struct ixgbe_rx_buffer *rx_buffer_info;
3688
3689                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3690                 if (rx_buffer_info->dma) {
3691                         dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3692                                          rx_ring->rx_buf_len,
3693                                          DMA_FROM_DEVICE);
3694                         rx_buffer_info->dma = 0;
3695                 }
3696                 if (rx_buffer_info->skb) {
3697                         struct sk_buff *skb = rx_buffer_info->skb;
3698                         rx_buffer_info->skb = NULL;
3699                         do {
3700                                 struct sk_buff *this = skb;
3701                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3702                                         dma_unmap_single(&pdev->dev,
3703                                                          IXGBE_RSC_CB(this)->dma,
3704                                                          rx_ring->rx_buf_len,
3705                                                          DMA_FROM_DEVICE);
3706                                         IXGBE_RSC_CB(this)->dma = 0;
3707                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3708                                 }
3709                                 skb = skb->prev;
3710                                 dev_kfree_skb(this);
3711                         } while (skb);
3712                 }
3713                 if (!rx_buffer_info->page)
3714                         continue;
3715                 if (rx_buffer_info->page_dma) {
3716                         dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3717                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3718                         rx_buffer_info->page_dma = 0;
3719                 }
3720                 put_page(rx_buffer_info->page);
3721                 rx_buffer_info->page = NULL;
3722                 rx_buffer_info->page_offset = 0;
3723         }
3724
3725         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3726         memset(rx_ring->rx_buffer_info, 0, size);
3727
3728         /* Zero out the descriptor ring */
3729         memset(rx_ring->desc, 0, rx_ring->size);
3730
3731         rx_ring->next_to_clean = 0;
3732         rx_ring->next_to_use = 0;
3733
3734         if (rx_ring->head)
3735                 writel(0, adapter->hw.hw_addr + rx_ring->head);
3736         if (rx_ring->tail)
3737                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3738 }
3739
3740 /**
3741  * ixgbe_clean_tx_ring - Free Tx Buffers
3742  * @adapter: board private structure
3743  * @tx_ring: ring to be cleaned
3744  **/
3745 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3746                                 struct ixgbe_ring *tx_ring)
3747 {
3748         struct ixgbe_tx_buffer *tx_buffer_info;
3749         unsigned long size;
3750         unsigned int i;
3751
3752         /* ring already cleared, nothing to do */
3753         if (!tx_ring->tx_buffer_info)
3754                 return;
3755
3756         /* Free all the Tx ring sk_buffs */
3757         for (i = 0; i < tx_ring->count; i++) {
3758                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3759                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3760         }
3761
3762         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3763         memset(tx_ring->tx_buffer_info, 0, size);
3764
3765         /* Zero out the descriptor ring */
3766         memset(tx_ring->desc, 0, tx_ring->size);
3767
3768         tx_ring->next_to_use = 0;
3769         tx_ring->next_to_clean = 0;
3770
3771         if (tx_ring->head)
3772                 writel(0, adapter->hw.hw_addr + tx_ring->head);
3773         if (tx_ring->tail)
3774                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3775 }
3776
3777 /**
3778  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3779  * @adapter: board private structure
3780  **/
3781 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3782 {
3783         int i;
3784
3785         for (i = 0; i < adapter->num_rx_queues; i++)
3786                 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3787 }
3788
3789 /**
3790  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3791  * @adapter: board private structure
3792  **/
3793 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3794 {
3795         int i;
3796
3797         for (i = 0; i < adapter->num_tx_queues; i++)
3798                 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3799 }
3800
3801 void ixgbe_down(struct ixgbe_adapter *adapter)
3802 {
3803         struct net_device *netdev = adapter->netdev;
3804         struct ixgbe_hw *hw = &adapter->hw;
3805         u32 rxctrl;
3806         u32 txdctl;
3807         int i, j;
3808         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3809
3810         /* signal that we are down to the interrupt handler */
3811         set_bit(__IXGBE_DOWN, &adapter->state);
3812
3813         /* disable receive for all VFs and wait one second */
3814         if (adapter->num_vfs) {
3815                 /* ping all the active vfs to let them know we are going down */
3816                 ixgbe_ping_all_vfs(adapter);
3817
3818                 /* Disable all VFTE/VFRE TX/RX */
3819                 ixgbe_disable_tx_rx(adapter);
3820
3821                 /* Mark all the VFs as inactive */
3822                 for (i = 0 ; i < adapter->num_vfs; i++)
3823                         adapter->vfinfo[i].clear_to_send = 0;
3824         }
3825
3826         /* disable receives */
3827         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3828         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3829
3830         IXGBE_WRITE_FLUSH(hw);
3831         msleep(10);
3832
3833         netif_tx_stop_all_queues(netdev);
3834
3835         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3836         del_timer_sync(&adapter->sfp_timer);
3837         del_timer_sync(&adapter->watchdog_timer);
3838         cancel_work_sync(&adapter->watchdog_task);
3839
3840         netif_carrier_off(netdev);
3841         netif_tx_disable(netdev);
3842
3843         ixgbe_irq_disable(adapter);
3844
3845         ixgbe_napi_disable_all(adapter);
3846
3847         /* Cleanup the affinity_hint CPU mask memory and callback */
3848         for (i = 0; i < num_q_vectors; i++) {
3849                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3850                 /* clear the affinity_mask in the IRQ descriptor */
3851                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3852                 /* release the CPU mask memory */
3853                 free_cpumask_var(q_vector->affinity_mask);
3854         }
3855
3856         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3857             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3858                 cancel_work_sync(&adapter->fdir_reinit_task);
3859
3860         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3861                 cancel_work_sync(&adapter->check_overtemp_task);
3862
3863         /* disable transmits in the hardware now that interrupts are off */
3864         for (i = 0; i < adapter->num_tx_queues; i++) {
3865                 j = adapter->tx_ring[i]->reg_idx;
3866                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3867                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3868                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3869         }
3870         /* Disable the Tx DMA engine on 82599 */
3871         if (hw->mac.type == ixgbe_mac_82599EB)
3872                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3873                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3874                                  ~IXGBE_DMATXCTL_TE));
3875
3876         /* power down the optics */
3877         if (hw->phy.multispeed_fiber)
3878                 hw->mac.ops.disable_tx_laser(hw);
3879
3880         /* clear n-tuple filters that are cached */
3881         ethtool_ntuple_flush(netdev);
3882
3883         if (!pci_channel_offline(adapter->pdev))
3884                 ixgbe_reset(adapter);
3885         ixgbe_clean_all_tx_rings(adapter);
3886         ixgbe_clean_all_rx_rings(adapter);
3887
3888 #ifdef CONFIG_IXGBE_DCA
3889         /* since we reset the hardware DCA settings were cleared */
3890         ixgbe_setup_dca(adapter);
3891 #endif
3892 }
3893
3894 /**
3895  * ixgbe_poll - NAPI Rx polling callback
3896  * @napi: structure for representing this polling device
3897  * @budget: how many packets driver is allowed to clean
3898  *
3899  * This function is used for legacy and MSI, NAPI mode
3900  **/
3901 static int ixgbe_poll(struct napi_struct *napi, int budget)
3902 {
3903         struct ixgbe_q_vector *q_vector =
3904                                 container_of(napi, struct ixgbe_q_vector, napi);
3905         struct ixgbe_adapter *adapter = q_vector->adapter;
3906         int tx_clean_complete, work_done = 0;
3907
3908 #ifdef CONFIG_IXGBE_DCA
3909         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3910                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3911                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3912         }
3913 #endif
3914
3915         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3916         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3917
3918         if (!tx_clean_complete)
3919                 work_done = budget;
3920
3921         /* If budget not fully consumed, exit the polling mode */
3922         if (work_done < budget) {
3923                 napi_complete(napi);
3924                 if (adapter->rx_itr_setting & 1)
3925                         ixgbe_set_itr(adapter);
3926                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3927                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3928         }
3929         return work_done;
3930 }
3931
3932 /**
3933  * ixgbe_tx_timeout - Respond to a Tx Hang
3934  * @netdev: network interface device structure
3935  **/
3936 static void ixgbe_tx_timeout(struct net_device *netdev)
3937 {
3938         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3939
3940         /* Do the reset outside of interrupt context */
3941         schedule_work(&adapter->reset_task);
3942 }
3943
3944 static void ixgbe_reset_task(struct work_struct *work)
3945 {
3946         struct ixgbe_adapter *adapter;
3947         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3948
3949         /* If we're already down or resetting, just bail */
3950         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3951             test_bit(__IXGBE_RESETTING, &adapter->state))
3952                 return;
3953
3954         adapter->tx_timeout_count++;
3955
3956         ixgbe_dump(adapter);
3957         netdev_err(adapter->netdev, "Reset adapter\n");
3958         ixgbe_reinit_locked(adapter);
3959 }
3960
3961 #ifdef CONFIG_IXGBE_DCB
3962 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3963 {
3964         bool ret = false;
3965         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3966
3967         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3968                 return ret;
3969
3970         f->mask = 0x7 << 3;
3971         adapter->num_rx_queues = f->indices;
3972         adapter->num_tx_queues = f->indices;
3973         ret = true;
3974
3975         return ret;
3976 }
3977 #endif
3978
3979 /**
3980  * ixgbe_set_rss_queues: Allocate queues for RSS
3981  * @adapter: board private structure to initialize
3982  *
3983  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3984  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3985  *
3986  **/
3987 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3988 {
3989         bool ret = false;
3990         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3991
3992         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3993                 f->mask = 0xF;
3994                 adapter->num_rx_queues = f->indices;
3995                 adapter->num_tx_queues = f->indices;
3996                 ret = true;
3997         } else {
3998                 ret = false;
3999         }
4000
4001         return ret;
4002 }
4003
4004 /**
4005  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4006  * @adapter: board private structure to initialize
4007  *
4008  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4009  * to the original CPU that initiated the Tx session.  This runs in addition
4010  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4011  * Rx load across CPUs using RSS.
4012  *
4013  **/
4014 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4015 {
4016         bool ret = false;
4017         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4018
4019         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4020         f_fdir->mask = 0;
4021
4022         /* Flow Director must have RSS enabled */
4023         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4024             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4025              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4026                 adapter->num_tx_queues = f_fdir->indices;
4027                 adapter->num_rx_queues = f_fdir->indices;
4028                 ret = true;
4029         } else {
4030                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4031                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4032         }
4033         return ret;
4034 }
4035
4036 #ifdef IXGBE_FCOE
4037 /**
4038  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4039  * @adapter: board private structure to initialize
4040  *
4041  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4042  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4043  * rx queues out of the max number of rx queues, instead, it is used as the
4044  * index of the first rx queue used by FCoE.
4045  *
4046  **/
4047 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4048 {
4049         bool ret = false;
4050         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4051
4052         f->indices = min((int)num_online_cpus(), f->indices);
4053         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4054                 adapter->num_rx_queues = 1;
4055                 adapter->num_tx_queues = 1;
4056 #ifdef CONFIG_IXGBE_DCB
4057                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4058                         e_info(probe, "FCoE enabled with DCB\n");
4059                         ixgbe_set_dcb_queues(adapter);
4060                 }
4061 #endif
4062                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4063                         e_info(probe, "FCoE enabled with RSS\n");
4064                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4065                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4066                                 ixgbe_set_fdir_queues(adapter);
4067                         else
4068                                 ixgbe_set_rss_queues(adapter);
4069                 }
4070                 /* adding FCoE rx rings to the end */
4071                 f->mask = adapter->num_rx_queues;
4072                 adapter->num_rx_queues += f->indices;
4073                 adapter->num_tx_queues += f->indices;
4074
4075                 ret = true;
4076         }
4077
4078         return ret;
4079 }
4080
4081 #endif /* IXGBE_FCOE */
4082 /**
4083  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4084  * @adapter: board private structure to initialize
4085  *
4086  * IOV doesn't actually use anything, so just NAK the
4087  * request for now and let the other queue routines
4088  * figure out what to do.
4089  */
4090 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4091 {
4092         return false;
4093 }
4094
4095 /*
4096  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4097  * @adapter: board private structure to initialize
4098  *
4099  * This is the top level queue allocation routine.  The order here is very
4100  * important, starting with the "most" number of features turned on at once,
4101  * and ending with the smallest set of features.  This way large combinations
4102  * can be allocated if they're turned on, and smaller combinations are the
4103  * fallthrough conditions.
4104  *
4105  **/
4106 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4107 {
4108         /* Start with base case */
4109         adapter->num_rx_queues = 1;
4110         adapter->num_tx_queues = 1;
4111         adapter->num_rx_pools = adapter->num_rx_queues;
4112         adapter->num_rx_queues_per_pool = 1;
4113
4114         if (ixgbe_set_sriov_queues(adapter))
4115                 goto done;
4116
4117 #ifdef IXGBE_FCOE
4118         if (ixgbe_set_fcoe_queues(adapter))
4119                 goto done;
4120
4121 #endif /* IXGBE_FCOE */
4122 #ifdef CONFIG_IXGBE_DCB
4123         if (ixgbe_set_dcb_queues(adapter))
4124                 goto done;
4125
4126 #endif
4127         if (ixgbe_set_fdir_queues(adapter))
4128                 goto done;
4129
4130         if (ixgbe_set_rss_queues(adapter))
4131                 goto done;
4132
4133         /* fallback to base case */
4134         adapter->num_rx_queues = 1;
4135         adapter->num_tx_queues = 1;
4136
4137 done:
4138         /* Notify the stack of the (possibly) reduced queue counts. */
4139         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4140         return netif_set_real_num_rx_queues(adapter->netdev,
4141                                             adapter->num_rx_queues);
4142 }
4143
4144 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4145                                        int vectors)
4146 {
4147         int err, vector_threshold;
4148
4149         /* We'll want at least 3 (vector_threshold):
4150          * 1) TxQ[0] Cleanup
4151          * 2) RxQ[0] Cleanup
4152          * 3) Other (Link Status Change, etc.)
4153          * 4) TCP Timer (optional)
4154          */
4155         vector_threshold = MIN_MSIX_COUNT;
4156
4157         /* The more we get, the more we will assign to Tx/Rx Cleanup
4158          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4159          * Right now, we simply care about how many we'll get; we'll
4160          * set them up later while requesting irq's.
4161          */
4162         while (vectors >= vector_threshold) {
4163                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4164                                       vectors);
4165                 if (!err) /* Success in acquiring all requested vectors. */
4166                         break;
4167                 else if (err < 0)
4168                         vectors = 0; /* Nasty failure, quit now */
4169                 else /* err == number of vectors we should try again with */
4170                         vectors = err;
4171         }
4172
4173         if (vectors < vector_threshold) {
4174                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4175                  * This just means we'll go with either a single MSI
4176                  * vector or fall back to legacy interrupts.
4177                  */
4178                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4179                              "Unable to allocate MSI-X interrupts\n");
4180                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4181                 kfree(adapter->msix_entries);
4182                 adapter->msix_entries = NULL;
4183         } else {
4184                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4185                 /*
4186                  * Adjust for only the vectors we'll use, which is minimum
4187                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4188                  * vectors we were allocated.
4189                  */
4190                 adapter->num_msix_vectors = min(vectors,
4191                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4192         }
4193 }
4194
4195 /**
4196  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4197  * @adapter: board private structure to initialize
4198  *
4199  * Cache the descriptor ring offsets for RSS to the assigned rings.
4200  *
4201  **/
4202 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4203 {
4204         int i;
4205         bool ret = false;
4206
4207         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4208                 for (i = 0; i < adapter->num_rx_queues; i++)
4209                         adapter->rx_ring[i]->reg_idx = i;
4210                 for (i = 0; i < adapter->num_tx_queues; i++)
4211                         adapter->tx_ring[i]->reg_idx = i;
4212                 ret = true;
4213         } else {
4214                 ret = false;
4215         }
4216
4217         return ret;
4218 }
4219
4220 #ifdef CONFIG_IXGBE_DCB
4221 /**
4222  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4223  * @adapter: board private structure to initialize
4224  *
4225  * Cache the descriptor ring offsets for DCB to the assigned rings.
4226  *
4227  **/
4228 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4229 {
4230         int i;
4231         bool ret = false;
4232         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4233
4234         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4235                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4236                         /* the number of queues is assumed to be symmetric */
4237                         for (i = 0; i < dcb_i; i++) {
4238                                 adapter->rx_ring[i]->reg_idx = i << 3;
4239                                 adapter->tx_ring[i]->reg_idx = i << 2;
4240                         }
4241                         ret = true;
4242                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4243                         if (dcb_i == 8) {
4244                                 /*
4245                                  * Tx TC0 starts at: descriptor queue 0
4246                                  * Tx TC1 starts at: descriptor queue 32
4247                                  * Tx TC2 starts at: descriptor queue 64
4248                                  * Tx TC3 starts at: descriptor queue 80
4249                                  * Tx TC4 starts at: descriptor queue 96
4250                                  * Tx TC5 starts at: descriptor queue 104
4251                                  * Tx TC6 starts at: descriptor queue 112
4252                                  * Tx TC7 starts at: descriptor queue 120
4253                                  *
4254                                  * Rx TC0-TC7 are offset by 16 queues each
4255                                  */
4256                                 for (i = 0; i < 3; i++) {
4257                                         adapter->tx_ring[i]->reg_idx = i << 5;
4258                                         adapter->rx_ring[i]->reg_idx = i << 4;
4259                                 }
4260                                 for ( ; i < 5; i++) {
4261                                         adapter->tx_ring[i]->reg_idx =
4262                                                                  ((i + 2) << 4);
4263                                         adapter->rx_ring[i]->reg_idx = i << 4;
4264                                 }
4265                                 for ( ; i < dcb_i; i++) {
4266                                         adapter->tx_ring[i]->reg_idx =
4267                                                                  ((i + 8) << 3);
4268                                         adapter->rx_ring[i]->reg_idx = i << 4;
4269                                 }
4270
4271                                 ret = true;
4272                         } else if (dcb_i == 4) {
4273                                 /*
4274                                  * Tx TC0 starts at: descriptor queue 0
4275                                  * Tx TC1 starts at: descriptor queue 64
4276                                  * Tx TC2 starts at: descriptor queue 96
4277                                  * Tx TC3 starts at: descriptor queue 112
4278                                  *
4279                                  * Rx TC0-TC3 are offset by 32 queues each
4280                                  */
4281                                 adapter->tx_ring[0]->reg_idx = 0;
4282                                 adapter->tx_ring[1]->reg_idx = 64;
4283                                 adapter->tx_ring[2]->reg_idx = 96;
4284                                 adapter->tx_ring[3]->reg_idx = 112;
4285                                 for (i = 0 ; i < dcb_i; i++)
4286                                         adapter->rx_ring[i]->reg_idx = i << 5;
4287
4288                                 ret = true;
4289                         } else {
4290                                 ret = false;
4291                         }
4292                 } else {
4293                         ret = false;
4294                 }
4295         } else {
4296                 ret = false;
4297         }
4298
4299         return ret;
4300 }
4301 #endif
4302
4303 /**
4304  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4305  * @adapter: board private structure to initialize
4306  *
4307  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4308  *
4309  **/
4310 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4311 {
4312         int i;
4313         bool ret = false;
4314
4315         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4316             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4317              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4318                 for (i = 0; i < adapter->num_rx_queues; i++)
4319                         adapter->rx_ring[i]->reg_idx = i;
4320                 for (i = 0; i < adapter->num_tx_queues; i++)
4321                         adapter->tx_ring[i]->reg_idx = i;
4322                 ret = true;
4323         }
4324
4325         return ret;
4326 }
4327
4328 #ifdef IXGBE_FCOE
4329 /**
4330  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4331  * @adapter: board private structure to initialize
4332  *
4333  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4334  *
4335  */
4336 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4337 {
4338         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4339         bool ret = false;
4340         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4341
4342         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4343 #ifdef CONFIG_IXGBE_DCB
4344                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4345                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4346
4347                         ixgbe_cache_ring_dcb(adapter);
4348                         /* find out queues in TC for FCoE */
4349                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4350                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4351                         /*
4352                          * In 82599, the number of Tx queues for each traffic
4353                          * class for both 8-TC and 4-TC modes are:
4354                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4355                          * 8 TCs:  32  32  16  16   8   8   8   8
4356                          * 4 TCs:  64  64  32  32
4357                          * We have max 8 queues for FCoE, where 8 the is
4358                          * FCoE redirection table size. If TC for FCoE is
4359                          * less than or equal to TC3, we have enough queues
4360                          * to add max of 8 queues for FCoE, so we start FCoE
4361                          * tx descriptor from the next one, i.e., reg_idx + 1.
4362                          * If TC for FCoE is above TC3, implying 8 TC mode,
4363                          * and we need 8 for FCoE, we have to take all queues
4364                          * in that traffic class for FCoE.
4365                          */
4366                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4367                                 fcoe_tx_i--;
4368                 }
4369 #endif /* CONFIG_IXGBE_DCB */
4370                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4371                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4372                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4373                                 ixgbe_cache_ring_fdir(adapter);
4374                         else
4375                                 ixgbe_cache_ring_rss(adapter);
4376
4377                         fcoe_rx_i = f->mask;
4378                         fcoe_tx_i = f->mask;
4379                 }
4380                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4381                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4382                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4383                 }
4384                 ret = true;
4385         }
4386         return ret;
4387 }
4388
4389 #endif /* IXGBE_FCOE */
4390 /**
4391  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4392  * @adapter: board private structure to initialize
4393  *
4394  * SR-IOV doesn't use any descriptor rings but changes the default if
4395  * no other mapping is used.
4396  *
4397  */
4398 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4399 {
4400         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4401         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4402         if (adapter->num_vfs)
4403                 return true;
4404         else
4405                 return false;
4406 }
4407
4408 /**
4409  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4410  * @adapter: board private structure to initialize
4411  *
4412  * Once we know the feature-set enabled for the device, we'll cache
4413  * the register offset the descriptor ring is assigned to.
4414  *
4415  * Note, the order the various feature calls is important.  It must start with
4416  * the "most" features enabled at the same time, then trickle down to the
4417  * least amount of features turned on at once.
4418  **/
4419 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4420 {
4421         /* start with default case */
4422         adapter->rx_ring[0]->reg_idx = 0;
4423         adapter->tx_ring[0]->reg_idx = 0;
4424
4425         if (ixgbe_cache_ring_sriov(adapter))
4426                 return;
4427
4428 #ifdef IXGBE_FCOE
4429         if (ixgbe_cache_ring_fcoe(adapter))
4430                 return;
4431
4432 #endif /* IXGBE_FCOE */
4433 #ifdef CONFIG_IXGBE_DCB
4434         if (ixgbe_cache_ring_dcb(adapter))
4435                 return;
4436
4437 #endif
4438         if (ixgbe_cache_ring_fdir(adapter))
4439                 return;
4440
4441         if (ixgbe_cache_ring_rss(adapter))
4442                 return;
4443 }
4444
4445 /**
4446  * ixgbe_alloc_queues - Allocate memory for all rings
4447  * @adapter: board private structure to initialize
4448  *
4449  * We allocate one ring per queue at run-time since we don't know the
4450  * number of queues at compile-time.  The polling_netdev array is
4451  * intended for Multiqueue, but should work fine with a single queue.
4452  **/
4453 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4454 {
4455         int i;
4456         int orig_node = adapter->node;
4457
4458         for (i = 0; i < adapter->num_tx_queues; i++) {
4459                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4460                 if (orig_node == -1) {
4461                         int cur_node = next_online_node(adapter->node);
4462                         if (cur_node == MAX_NUMNODES)
4463                                 cur_node = first_online_node;
4464                         adapter->node = cur_node;
4465                 }
4466                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4467                                     adapter->node);
4468                 if (!ring)
4469                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4470                 if (!ring)
4471                         goto err_tx_ring_allocation;
4472                 ring->count = adapter->tx_ring_count;
4473                 ring->queue_index = i;
4474                 ring->numa_node = adapter->node;
4475
4476                 adapter->tx_ring[i] = ring;
4477         }
4478
4479         /* Restore the adapter's original node */
4480         adapter->node = orig_node;
4481
4482         for (i = 0; i < adapter->num_rx_queues; i++) {
4483                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4484                 if (orig_node == -1) {
4485                         int cur_node = next_online_node(adapter->node);
4486                         if (cur_node == MAX_NUMNODES)
4487                                 cur_node = first_online_node;
4488                         adapter->node = cur_node;
4489                 }
4490                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4491                                     adapter->node);
4492                 if (!ring)
4493                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4494                 if (!ring)
4495                         goto err_rx_ring_allocation;
4496                 ring->count = adapter->rx_ring_count;
4497                 ring->queue_index = i;
4498                 ring->numa_node = adapter->node;
4499
4500                 adapter->rx_ring[i] = ring;
4501         }
4502
4503         /* Restore the adapter's original node */
4504         adapter->node = orig_node;
4505
4506         ixgbe_cache_ring_register(adapter);
4507
4508         return 0;
4509
4510 err_rx_ring_allocation:
4511         for (i = 0; i < adapter->num_tx_queues; i++)
4512                 kfree(adapter->tx_ring[i]);
4513 err_tx_ring_allocation:
4514         return -ENOMEM;
4515 }
4516
4517 /**
4518  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4519  * @adapter: board private structure to initialize
4520  *
4521  * Attempt to configure the interrupts using the best available
4522  * capabilities of the hardware and the kernel.
4523  **/
4524 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4525 {
4526         struct ixgbe_hw *hw = &adapter->hw;
4527         int err = 0;
4528         int vector, v_budget;
4529
4530         /*
4531          * It's easy to be greedy for MSI-X vectors, but it really
4532          * doesn't do us much good if we have a lot more vectors
4533          * than CPU's.  So let's be conservative and only ask for
4534          * (roughly) the same number of vectors as there are CPU's.
4535          */
4536         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4537                        (int)num_online_cpus()) + NON_Q_VECTORS;
4538
4539         /*
4540          * At the same time, hardware can only support a maximum of
4541          * hw.mac->max_msix_vectors vectors.  With features
4542          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4543          * descriptor queues supported by our device.  Thus, we cap it off in
4544          * those rare cases where the cpu count also exceeds our vector limit.
4545          */
4546         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4547
4548         /* A failure in MSI-X entry allocation isn't fatal, but it does
4549          * mean we disable MSI-X capabilities of the adapter. */
4550         adapter->msix_entries = kcalloc(v_budget,
4551                                         sizeof(struct msix_entry), GFP_KERNEL);
4552         if (adapter->msix_entries) {
4553                 for (vector = 0; vector < v_budget; vector++)
4554                         adapter->msix_entries[vector].entry = vector;
4555
4556                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4557
4558                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4559                         goto out;
4560         }
4561
4562         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4563         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4564         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4565         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4566         adapter->atr_sample_rate = 0;
4567         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4568                 ixgbe_disable_sriov(adapter);
4569
4570         err = ixgbe_set_num_queues(adapter);
4571         if (err)
4572                 return err;
4573
4574         err = pci_enable_msi(adapter->pdev);
4575         if (!err) {
4576                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4577         } else {
4578                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4579                              "Unable to allocate MSI interrupt, "
4580                              "falling back to legacy.  Error: %d\n", err);
4581                 /* reset err */
4582                 err = 0;
4583         }
4584
4585 out:
4586         return err;
4587 }
4588
4589 /**
4590  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4591  * @adapter: board private structure to initialize
4592  *
4593  * We allocate one q_vector per queue interrupt.  If allocation fails we
4594  * return -ENOMEM.
4595  **/
4596 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4597 {
4598         int q_idx, num_q_vectors;
4599         struct ixgbe_q_vector *q_vector;
4600         int napi_vectors;
4601         int (*poll)(struct napi_struct *, int);
4602
4603         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4604                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4605                 napi_vectors = adapter->num_rx_queues;
4606                 poll = &ixgbe_clean_rxtx_many;
4607         } else {
4608                 num_q_vectors = 1;
4609                 napi_vectors = 1;
4610                 poll = &ixgbe_poll;
4611         }
4612
4613         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4614                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4615                                         GFP_KERNEL, adapter->node);
4616                 if (!q_vector)
4617                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4618                                            GFP_KERNEL);
4619                 if (!q_vector)
4620                         goto err_out;
4621                 q_vector->adapter = adapter;
4622                 if (q_vector->txr_count && !q_vector->rxr_count)
4623                         q_vector->eitr = adapter->tx_eitr_param;
4624                 else
4625                         q_vector->eitr = adapter->rx_eitr_param;
4626                 q_vector->v_idx = q_idx;
4627                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4628                 adapter->q_vector[q_idx] = q_vector;
4629         }
4630
4631         return 0;
4632
4633 err_out:
4634         while (q_idx) {
4635                 q_idx--;
4636                 q_vector = adapter->q_vector[q_idx];
4637                 netif_napi_del(&q_vector->napi);
4638                 kfree(q_vector);
4639                 adapter->q_vector[q_idx] = NULL;
4640         }
4641         return -ENOMEM;
4642 }
4643
4644 /**
4645  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4646  * @adapter: board private structure to initialize
4647  *
4648  * This function frees the memory allocated to the q_vectors.  In addition if
4649  * NAPI is enabled it will delete any references to the NAPI struct prior
4650  * to freeing the q_vector.
4651  **/
4652 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4653 {
4654         int q_idx, num_q_vectors;
4655
4656         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4657                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4658         else
4659                 num_q_vectors = 1;
4660
4661         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4662                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4663                 adapter->q_vector[q_idx] = NULL;
4664                 netif_napi_del(&q_vector->napi);
4665                 kfree(q_vector);
4666         }
4667 }
4668
4669 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4670 {
4671         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4672                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4673                 pci_disable_msix(adapter->pdev);
4674                 kfree(adapter->msix_entries);
4675                 adapter->msix_entries = NULL;
4676         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4677                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4678                 pci_disable_msi(adapter->pdev);
4679         }
4680 }
4681
4682 /**
4683  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4684  * @adapter: board private structure to initialize
4685  *
4686  * We determine which interrupt scheme to use based on...
4687  * - Kernel support (MSI, MSI-X)
4688  *   - which can be user-defined (via MODULE_PARAM)
4689  * - Hardware queue count (num_*_queues)
4690  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4691  **/
4692 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4693 {
4694         int err;
4695
4696         /* Number of supported queues */
4697         err = ixgbe_set_num_queues(adapter);
4698         if (err)
4699                 return err;
4700
4701         err = ixgbe_set_interrupt_capability(adapter);
4702         if (err) {
4703                 e_dev_err("Unable to setup interrupt capabilities\n");
4704                 goto err_set_interrupt;
4705         }
4706
4707         err = ixgbe_alloc_q_vectors(adapter);
4708         if (err) {
4709                 e_dev_err("Unable to allocate memory for queue vectors\n");
4710                 goto err_alloc_q_vectors;
4711         }
4712
4713         err = ixgbe_alloc_queues(adapter);
4714         if (err) {
4715                 e_dev_err("Unable to allocate memory for queues\n");
4716                 goto err_alloc_queues;
4717         }
4718
4719         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4720                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4721                    adapter->num_rx_queues, adapter->num_tx_queues);
4722
4723         set_bit(__IXGBE_DOWN, &adapter->state);
4724
4725         return 0;
4726
4727 err_alloc_queues:
4728         ixgbe_free_q_vectors(adapter);
4729 err_alloc_q_vectors:
4730         ixgbe_reset_interrupt_capability(adapter);
4731 err_set_interrupt:
4732         return err;
4733 }
4734
4735 static void ring_free_rcu(struct rcu_head *head)
4736 {
4737         kfree(container_of(head, struct ixgbe_ring, rcu));
4738 }
4739
4740 /**
4741  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4742  * @adapter: board private structure to clear interrupt scheme on
4743  *
4744  * We go through and clear interrupt specific resources and reset the structure
4745  * to pre-load conditions
4746  **/
4747 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4748 {
4749         int i;
4750
4751         for (i = 0; i < adapter->num_tx_queues; i++) {
4752                 kfree(adapter->tx_ring[i]);
4753                 adapter->tx_ring[i] = NULL;
4754         }
4755         for (i = 0; i < adapter->num_rx_queues; i++) {
4756                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4757
4758                 /* ixgbe_get_stats64() might access this ring, we must wait
4759                  * a grace period before freeing it.
4760                  */
4761                 call_rcu(&ring->rcu, ring_free_rcu);
4762                 adapter->rx_ring[i] = NULL;
4763         }
4764
4765         ixgbe_free_q_vectors(adapter);
4766         ixgbe_reset_interrupt_capability(adapter);
4767 }
4768
4769 /**
4770  * ixgbe_sfp_timer - worker thread to find a missing module
4771  * @data: pointer to our adapter struct
4772  **/
4773 static void ixgbe_sfp_timer(unsigned long data)
4774 {
4775         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4776
4777         /*
4778          * Do the sfp_timer outside of interrupt context due to the
4779          * delays that sfp+ detection requires
4780          */
4781         schedule_work(&adapter->sfp_task);
4782 }
4783
4784 /**
4785  * ixgbe_sfp_task - worker thread to find a missing module
4786  * @work: pointer to work_struct containing our data
4787  **/
4788 static void ixgbe_sfp_task(struct work_struct *work)
4789 {
4790         struct ixgbe_adapter *adapter = container_of(work,
4791                                                      struct ixgbe_adapter,
4792                                                      sfp_task);
4793         struct ixgbe_hw *hw = &adapter->hw;
4794
4795         if ((hw->phy.type == ixgbe_phy_nl) &&
4796             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4797                 s32 ret = hw->phy.ops.identify_sfp(hw);
4798                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4799                         goto reschedule;
4800                 ret = hw->phy.ops.reset(hw);
4801                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4802                         e_dev_err("failed to initialize because an unsupported "
4803                                   "SFP+ module type was detected.\n");
4804                         e_dev_err("Reload the driver after installing a "
4805                                   "supported module.\n");
4806                         unregister_netdev(adapter->netdev);
4807                 } else {
4808                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4809                 }
4810                 /* don't need this routine any more */
4811                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4812         }
4813         return;
4814 reschedule:
4815         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4816                 mod_timer(&adapter->sfp_timer,
4817                           round_jiffies(jiffies + (2 * HZ)));
4818 }
4819
4820 /**
4821  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4822  * @adapter: board private structure to initialize
4823  *
4824  * ixgbe_sw_init initializes the Adapter private data structure.
4825  * Fields are initialized based on PCI device information and
4826  * OS network device settings (MTU size).
4827  **/
4828 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4829 {
4830         struct ixgbe_hw *hw = &adapter->hw;
4831         struct pci_dev *pdev = adapter->pdev;
4832         struct net_device *dev = adapter->netdev;
4833         unsigned int rss;
4834 #ifdef CONFIG_IXGBE_DCB
4835         int j;
4836         struct tc_configuration *tc;
4837 #endif
4838         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4839
4840         /* PCI config space info */
4841
4842         hw->vendor_id = pdev->vendor;
4843         hw->device_id = pdev->device;
4844         hw->revision_id = pdev->revision;
4845         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4846         hw->subsystem_device_id = pdev->subsystem_device;
4847
4848         /* Set capability flags */
4849         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4850         adapter->ring_feature[RING_F_RSS].indices = rss;
4851         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4852         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4853         if (hw->mac.type == ixgbe_mac_82598EB) {
4854                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4855                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4856                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4857         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4858                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4859                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4860                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4861                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4862                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4863                 if (dev->features & NETIF_F_NTUPLE) {
4864                         /* Flow Director perfect filter enabled */
4865                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4866                         adapter->atr_sample_rate = 0;
4867                         spin_lock_init(&adapter->fdir_perfect_lock);
4868                 } else {
4869                         /* Flow Director hash filters enabled */
4870                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4871                         adapter->atr_sample_rate = 20;
4872                 }
4873                 adapter->ring_feature[RING_F_FDIR].indices =
4874                                                          IXGBE_MAX_FDIR_INDICES;
4875                 adapter->fdir_pballoc = 0;
4876 #ifdef IXGBE_FCOE
4877                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4878                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4879                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4880 #ifdef CONFIG_IXGBE_DCB
4881                 /* Default traffic class to use for FCoE */
4882                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4883                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4884 #endif
4885 #endif /* IXGBE_FCOE */
4886         }
4887
4888 #ifdef CONFIG_IXGBE_DCB
4889         /* Configure DCB traffic classes */
4890         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4891                 tc = &adapter->dcb_cfg.tc_config[j];
4892                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4893                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4894                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4895                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4896                 tc->dcb_pfc = pfc_disabled;
4897         }
4898         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4899         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4900         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4901         adapter->dcb_cfg.pfc_mode_enable = false;
4902         adapter->dcb_cfg.round_robin_enable = false;
4903         adapter->dcb_set_bitmap = 0x00;
4904         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4905                            adapter->ring_feature[RING_F_DCB].indices);
4906
4907 #endif
4908
4909         /* default flow control settings */
4910         hw->fc.requested_mode = ixgbe_fc_full;
4911         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4912 #ifdef CONFIG_DCB
4913         adapter->last_lfc_mode = hw->fc.current_mode;
4914 #endif
4915         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4916         hw->fc.low_water = FC_LOW_WATER(max_frame);
4917         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4918         hw->fc.send_xon = true;
4919         hw->fc.disable_fc_autoneg = false;
4920
4921         /* enable itr by default in dynamic mode */
4922         adapter->rx_itr_setting = 1;
4923         adapter->rx_eitr_param = 20000;
4924         adapter->tx_itr_setting = 1;
4925         adapter->tx_eitr_param = 10000;
4926
4927         /* set defaults for eitr in MegaBytes */
4928         adapter->eitr_low = 10;
4929         adapter->eitr_high = 20;
4930
4931         /* set default ring sizes */
4932         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4933         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4934
4935         /* initialize eeprom parameters */
4936         if (ixgbe_init_eeprom_params_generic(hw)) {
4937                 e_dev_err("EEPROM initialization failed\n");
4938                 return -EIO;
4939         }
4940
4941         /* enable rx csum by default */
4942         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4943
4944         /* get assigned NUMA node */
4945         adapter->node = dev_to_node(&pdev->dev);
4946
4947         set_bit(__IXGBE_DOWN, &adapter->state);
4948
4949         return 0;
4950 }
4951
4952 /**
4953  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4954  * @adapter: board private structure
4955  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4956  *
4957  * Return 0 on success, negative on failure
4958  **/
4959 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4960                              struct ixgbe_ring *tx_ring)
4961 {
4962         struct pci_dev *pdev = adapter->pdev;
4963         int size;
4964
4965         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4966         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4967         if (!tx_ring->tx_buffer_info)
4968                 tx_ring->tx_buffer_info = vmalloc(size);
4969         if (!tx_ring->tx_buffer_info)
4970                 goto err;
4971         memset(tx_ring->tx_buffer_info, 0, size);
4972
4973         /* round up to nearest 4K */
4974         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4975         tx_ring->size = ALIGN(tx_ring->size, 4096);
4976
4977         tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4978                                            &tx_ring->dma, GFP_KERNEL);
4979         if (!tx_ring->desc)
4980                 goto err;
4981
4982         tx_ring->next_to_use = 0;
4983         tx_ring->next_to_clean = 0;
4984         tx_ring->work_limit = tx_ring->count;
4985         return 0;
4986
4987 err:
4988         vfree(tx_ring->tx_buffer_info);
4989         tx_ring->tx_buffer_info = NULL;
4990         e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4991         return -ENOMEM;
4992 }
4993
4994 /**
4995  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4996  * @adapter: board private structure
4997  *
4998  * If this function returns with an error, then it's possible one or
4999  * more of the rings is populated (while the rest are not).  It is the
5000  * callers duty to clean those orphaned rings.
5001  *
5002  * Return 0 on success, negative on failure
5003  **/
5004 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5005 {
5006         int i, err = 0;
5007
5008         for (i = 0; i < adapter->num_tx_queues; i++) {
5009                 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
5010                 if (!err)
5011                         continue;
5012                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5013                 break;
5014         }
5015
5016         return err;
5017 }
5018
5019 /**
5020  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5021  * @adapter: board private structure
5022  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5023  *
5024  * Returns 0 on success, negative on failure
5025  **/
5026 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
5027                              struct ixgbe_ring *rx_ring)
5028 {
5029         struct pci_dev *pdev = adapter->pdev;
5030         int size;
5031
5032         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5033         rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5034         if (!rx_ring->rx_buffer_info)
5035                 rx_ring->rx_buffer_info = vmalloc(size);
5036         if (!rx_ring->rx_buffer_info) {
5037                 e_err(probe, "vmalloc allocation failed for the Rx "
5038                       "descriptor ring\n");
5039                 goto alloc_failed;
5040         }
5041         memset(rx_ring->rx_buffer_info, 0, size);
5042
5043         /* Round up to nearest 4K */
5044         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5045         rx_ring->size = ALIGN(rx_ring->size, 4096);
5046
5047         rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5048                                            &rx_ring->dma, GFP_KERNEL);
5049
5050         if (!rx_ring->desc) {
5051                 e_err(probe, "Memory allocation failed for the Rx "
5052                       "descriptor ring\n");
5053                 vfree(rx_ring->rx_buffer_info);
5054                 goto alloc_failed;
5055         }
5056
5057         rx_ring->next_to_clean = 0;
5058         rx_ring->next_to_use = 0;
5059
5060         return 0;
5061
5062 alloc_failed:
5063         return -ENOMEM;
5064 }
5065
5066 /**
5067  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5068  * @adapter: board private structure
5069  *
5070  * If this function returns with an error, then it's possible one or
5071  * more of the rings is populated (while the rest are not).  It is the
5072  * callers duty to clean those orphaned rings.
5073  *
5074  * Return 0 on success, negative on failure
5075  **/
5076
5077 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5078 {
5079         int i, err = 0;
5080
5081         for (i = 0; i < adapter->num_rx_queues; i++) {
5082                 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5083                 if (!err)
5084                         continue;
5085                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5086                 break;
5087         }
5088
5089         return err;
5090 }
5091
5092 /**
5093  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5094  * @adapter: board private structure
5095  * @tx_ring: Tx descriptor ring for a specific queue
5096  *
5097  * Free all transmit software resources
5098  **/
5099 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5100                              struct ixgbe_ring *tx_ring)
5101 {
5102         struct pci_dev *pdev = adapter->pdev;
5103
5104         ixgbe_clean_tx_ring(adapter, tx_ring);
5105
5106         vfree(tx_ring->tx_buffer_info);
5107         tx_ring->tx_buffer_info = NULL;
5108
5109         dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5110                           tx_ring->dma);
5111
5112         tx_ring->desc = NULL;
5113 }
5114
5115 /**
5116  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5117  * @adapter: board private structure
5118  *
5119  * Free all transmit software resources
5120  **/
5121 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5122 {
5123         int i;
5124
5125         for (i = 0; i < adapter->num_tx_queues; i++)
5126                 if (adapter->tx_ring[i]->desc)
5127                         ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5128 }
5129
5130 /**
5131  * ixgbe_free_rx_resources - Free Rx Resources
5132  * @adapter: board private structure
5133  * @rx_ring: ring to clean the resources from
5134  *
5135  * Free all receive software resources
5136  **/
5137 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5138                              struct ixgbe_ring *rx_ring)
5139 {
5140         struct pci_dev *pdev = adapter->pdev;
5141
5142         ixgbe_clean_rx_ring(adapter, rx_ring);
5143
5144         vfree(rx_ring->rx_buffer_info);
5145         rx_ring->rx_buffer_info = NULL;
5146
5147         dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5148                           rx_ring->dma);
5149
5150         rx_ring->desc = NULL;
5151 }
5152
5153 /**
5154  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5155  * @adapter: board private structure
5156  *
5157  * Free all receive software resources
5158  **/
5159 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5160 {
5161         int i;
5162
5163         for (i = 0; i < adapter->num_rx_queues; i++)
5164                 if (adapter->rx_ring[i]->desc)
5165                         ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5166 }
5167
5168 /**
5169  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5170  * @netdev: network interface device structure
5171  * @new_mtu: new value for maximum frame size
5172  *
5173  * Returns 0 on success, negative on failure
5174  **/
5175 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5176 {
5177         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5178         struct ixgbe_hw *hw = &adapter->hw;
5179         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5180
5181         /* MTU < 68 is an error and causes problems on some kernels */
5182         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5183                 return -EINVAL;
5184
5185         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5186         /* must set new MTU before calling down or up */
5187         netdev->mtu = new_mtu;
5188
5189         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5190         hw->fc.low_water = FC_LOW_WATER(max_frame);
5191
5192         if (netif_running(netdev))
5193                 ixgbe_reinit_locked(adapter);
5194
5195         return 0;
5196 }
5197
5198 /**
5199  * ixgbe_open - Called when a network interface is made active
5200  * @netdev: network interface device structure
5201  *
5202  * Returns 0 on success, negative value on failure
5203  *
5204  * The open entry point is called when a network interface is made
5205  * active by the system (IFF_UP).  At this point all resources needed
5206  * for transmit and receive operations are allocated, the interrupt
5207  * handler is registered with the OS, the watchdog timer is started,
5208  * and the stack is notified that the interface is ready.
5209  **/
5210 static int ixgbe_open(struct net_device *netdev)
5211 {
5212         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5213         int err;
5214
5215         /* disallow open during test */
5216         if (test_bit(__IXGBE_TESTING, &adapter->state))
5217                 return -EBUSY;
5218
5219         netif_carrier_off(netdev);
5220
5221         /* allocate transmit descriptors */
5222         err = ixgbe_setup_all_tx_resources(adapter);
5223         if (err)
5224                 goto err_setup_tx;
5225
5226         /* allocate receive descriptors */
5227         err = ixgbe_setup_all_rx_resources(adapter);
5228         if (err)
5229                 goto err_setup_rx;
5230
5231         ixgbe_configure(adapter);
5232
5233         err = ixgbe_request_irq(adapter);
5234         if (err)
5235                 goto err_req_irq;
5236
5237         err = ixgbe_up_complete(adapter);
5238         if (err)
5239                 goto err_up;
5240
5241         netif_tx_start_all_queues(netdev);
5242
5243         return 0;
5244
5245 err_up:
5246         ixgbe_release_hw_control(adapter);
5247         ixgbe_free_irq(adapter);
5248 err_req_irq:
5249 err_setup_rx:
5250         ixgbe_free_all_rx_resources(adapter);
5251 err_setup_tx:
5252         ixgbe_free_all_tx_resources(adapter);
5253         ixgbe_reset(adapter);
5254
5255         return err;
5256 }
5257
5258 /**
5259  * ixgbe_close - Disables a network interface
5260  * @netdev: network interface device structure
5261  *
5262  * Returns 0, this is not allowed to fail
5263  *
5264  * The close entry point is called when an interface is de-activated
5265  * by the OS.  The hardware is still under the drivers control, but
5266  * needs to be disabled.  A global MAC reset is issued to stop the
5267  * hardware, and all transmit and receive resources are freed.
5268  **/
5269 static int ixgbe_close(struct net_device *netdev)
5270 {
5271         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5272
5273         ixgbe_down(adapter);
5274         ixgbe_free_irq(adapter);
5275
5276         ixgbe_free_all_tx_resources(adapter);
5277         ixgbe_free_all_rx_resources(adapter);
5278
5279         ixgbe_release_hw_control(adapter);
5280
5281         return 0;
5282 }
5283
5284 #ifdef CONFIG_PM
5285 static int ixgbe_resume(struct pci_dev *pdev)
5286 {
5287         struct net_device *netdev = pci_get_drvdata(pdev);
5288         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5289         u32 err;
5290
5291         pci_set_power_state(pdev, PCI_D0);
5292         pci_restore_state(pdev);
5293         /*
5294          * pci_restore_state clears dev->state_saved so call
5295          * pci_save_state to restore it.
5296          */
5297         pci_save_state(pdev);
5298
5299         err = pci_enable_device_mem(pdev);
5300         if (err) {
5301                 e_dev_err("Cannot enable PCI device from suspend\n");
5302                 return err;
5303         }
5304         pci_set_master(pdev);
5305
5306         pci_wake_from_d3(pdev, false);
5307
5308         err = ixgbe_init_interrupt_scheme(adapter);
5309         if (err) {
5310                 e_dev_err("Cannot initialize interrupts for device\n");
5311                 return err;
5312         }
5313
5314         ixgbe_reset(adapter);
5315
5316         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5317
5318         if (netif_running(netdev)) {
5319                 err = ixgbe_open(adapter->netdev);
5320                 if (err)
5321                         return err;
5322         }
5323
5324         netif_device_attach(netdev);
5325
5326         return 0;
5327 }
5328 #endif /* CONFIG_PM */
5329
5330 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5331 {
5332         struct net_device *netdev = pci_get_drvdata(pdev);
5333         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5334         struct ixgbe_hw *hw = &adapter->hw;
5335         u32 ctrl, fctrl;
5336         u32 wufc = adapter->wol;
5337 #ifdef CONFIG_PM
5338         int retval = 0;
5339 #endif
5340
5341         netif_device_detach(netdev);
5342
5343         if (netif_running(netdev)) {
5344                 ixgbe_down(adapter);
5345                 ixgbe_free_irq(adapter);
5346                 ixgbe_free_all_tx_resources(adapter);
5347                 ixgbe_free_all_rx_resources(adapter);
5348         }
5349
5350 #ifdef CONFIG_PM
5351         retval = pci_save_state(pdev);
5352         if (retval)
5353                 return retval;
5354
5355 #endif
5356         if (wufc) {
5357                 ixgbe_set_rx_mode(netdev);
5358
5359                 /* turn on all-multi mode if wake on multicast is enabled */
5360                 if (wufc & IXGBE_WUFC_MC) {
5361                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5362                         fctrl |= IXGBE_FCTRL_MPE;
5363                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5364                 }
5365
5366                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5367                 ctrl |= IXGBE_CTRL_GIO_DIS;
5368                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5369
5370                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5371         } else {
5372                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5373                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5374         }
5375
5376         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5377                 pci_wake_from_d3(pdev, true);
5378         else
5379                 pci_wake_from_d3(pdev, false);
5380
5381         *enable_wake = !!wufc;
5382
5383         ixgbe_clear_interrupt_scheme(adapter);
5384
5385         ixgbe_release_hw_control(adapter);
5386
5387         pci_disable_device(pdev);
5388
5389         return 0;
5390 }
5391
5392 #ifdef CONFIG_PM
5393 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5394 {
5395         int retval;
5396         bool wake;
5397
5398         retval = __ixgbe_shutdown(pdev, &wake);
5399         if (retval)
5400                 return retval;
5401
5402         if (wake) {
5403                 pci_prepare_to_sleep(pdev);
5404         } else {
5405                 pci_wake_from_d3(pdev, false);
5406                 pci_set_power_state(pdev, PCI_D3hot);
5407         }
5408
5409         return 0;
5410 }
5411 #endif /* CONFIG_PM */
5412
5413 static void ixgbe_shutdown(struct pci_dev *pdev)
5414 {
5415         bool wake;
5416
5417         __ixgbe_shutdown(pdev, &wake);
5418
5419         if (system_state == SYSTEM_POWER_OFF) {
5420                 pci_wake_from_d3(pdev, wake);
5421                 pci_set_power_state(pdev, PCI_D3hot);
5422         }
5423 }
5424
5425 /**
5426  * ixgbe_update_stats - Update the board statistics counters.
5427  * @adapter: board private structure
5428  **/
5429 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5430 {
5431         struct net_device *netdev = adapter->netdev;
5432         struct ixgbe_hw *hw = &adapter->hw;
5433         u64 total_mpc = 0;
5434         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5435         u64 non_eop_descs = 0, restart_queue = 0;
5436         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5437
5438         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5439             test_bit(__IXGBE_RESETTING, &adapter->state))
5440                 return;
5441
5442         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5443                 u64 rsc_count = 0;
5444                 u64 rsc_flush = 0;
5445                 for (i = 0; i < 16; i++)
5446                         adapter->hw_rx_no_dma_resources +=
5447                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5448                 for (i = 0; i < adapter->num_rx_queues; i++) {
5449                         rsc_count += adapter->rx_ring[i]->rsc_count;
5450                         rsc_flush += adapter->rx_ring[i]->rsc_flush;
5451                 }
5452                 adapter->rsc_total_count = rsc_count;
5453                 adapter->rsc_total_flush = rsc_flush;
5454         }
5455
5456         /* gather some stats to the adapter struct that are per queue */
5457         for (i = 0; i < adapter->num_tx_queues; i++)
5458                 restart_queue += adapter->tx_ring[i]->restart_queue;
5459         adapter->restart_queue = restart_queue;
5460
5461         for (i = 0; i < adapter->num_rx_queues; i++)
5462                 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5463         adapter->non_eop_descs = non_eop_descs;
5464
5465         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5466         for (i = 0; i < 8; i++) {
5467                 /* for packet buffers not used, the register should read 0 */
5468                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5469                 missed_rx += mpc;
5470                 hwstats->mpc[i] += mpc;
5471                 total_mpc += hwstats->mpc[i];
5472                 if (hw->mac.type == ixgbe_mac_82598EB)
5473                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5474                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5475                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5476                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5477                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5478                 if (hw->mac.type == ixgbe_mac_82599EB) {
5479                         hwstats->pxonrxc[i] +=
5480                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5481                         hwstats->pxoffrxc[i] +=
5482                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5483                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5484                 } else {
5485                         hwstats->pxonrxc[i] +=
5486                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5487                         hwstats->pxoffrxc[i] +=
5488                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5489                 }
5490                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5491                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5492         }
5493         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5494         /* work around hardware counting issue */
5495         hwstats->gprc -= missed_rx;
5496
5497         /* 82598 hardware only has a 32 bit counter in the high register */
5498         if (hw->mac.type == ixgbe_mac_82599EB) {
5499                 u64 tmp;
5500                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5501                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5502                                                 /* 4 high bits of GORC */
5503                 hwstats->gorc += (tmp << 32);
5504                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5505                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5506                                                 /* 4 high bits of GOTC */
5507                 hwstats->gotc += (tmp << 32);
5508                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5509                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5510                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5511                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5512                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5513                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5514 #ifdef IXGBE_FCOE
5515                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5516                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5517                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5518                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5519                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5520                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5521 #endif /* IXGBE_FCOE */
5522         } else {
5523                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5524                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5525                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5526                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5527                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5528         }
5529         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5530         hwstats->bprc += bprc;
5531         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5532         if (hw->mac.type == ixgbe_mac_82598EB)
5533                 hwstats->mprc -= bprc;
5534         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5535         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5536         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5537         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5538         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5539         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5540         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5541         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5542         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5543         hwstats->lxontxc += lxon;
5544         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5545         hwstats->lxofftxc += lxoff;
5546         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5547         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5548         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5549         /*
5550          * 82598 errata - tx of flow control packets is included in tx counters
5551          */
5552         xon_off_tot = lxon + lxoff;
5553         hwstats->gptc -= xon_off_tot;
5554         hwstats->mptc -= xon_off_tot;
5555         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5556         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5557         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5558         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5559         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5560         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5561         hwstats->ptc64 -= xon_off_tot;
5562         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5563         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5564         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5565         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5566         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5567         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5568
5569         /* Fill out the OS statistics structure */
5570         netdev->stats.multicast = hwstats->mprc;
5571
5572         /* Rx Errors */
5573         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5574         netdev->stats.rx_dropped = 0;
5575         netdev->stats.rx_length_errors = hwstats->rlec;
5576         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5577         netdev->stats.rx_missed_errors = total_mpc;
5578 }
5579
5580 /**
5581  * ixgbe_watchdog - Timer Call-back
5582  * @data: pointer to adapter cast into an unsigned long
5583  **/
5584 static void ixgbe_watchdog(unsigned long data)
5585 {
5586         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5587         struct ixgbe_hw *hw = &adapter->hw;
5588         u64 eics = 0;
5589         int i;
5590
5591         /*
5592          *  Do the watchdog outside of interrupt context due to the lovely
5593          * delays that some of the newer hardware requires
5594          */
5595
5596         if (test_bit(__IXGBE_DOWN, &adapter->state))
5597                 goto watchdog_short_circuit;
5598
5599         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5600                 /*
5601                  * for legacy and MSI interrupts don't set any bits
5602                  * that are enabled for EIAM, because this operation
5603                  * would set *both* EIMS and EICS for any bit in EIAM
5604                  */
5605                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5606                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5607                 goto watchdog_reschedule;
5608         }
5609
5610         /* get one bit for every active tx/rx interrupt vector */
5611         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5612                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5613                 if (qv->rxr_count || qv->txr_count)
5614                         eics |= ((u64)1 << i);
5615         }
5616
5617         /* Cause software interrupt to ensure rx rings are cleaned */
5618         ixgbe_irq_rearm_queues(adapter, eics);
5619
5620 watchdog_reschedule:
5621         /* Reset the timer */
5622         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5623
5624 watchdog_short_circuit:
5625         schedule_work(&adapter->watchdog_task);
5626 }
5627
5628 /**
5629  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5630  * @work: pointer to work_struct containing our data
5631  **/
5632 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5633 {
5634         struct ixgbe_adapter *adapter = container_of(work,
5635                                                      struct ixgbe_adapter,
5636                                                      multispeed_fiber_task);
5637         struct ixgbe_hw *hw = &adapter->hw;
5638         u32 autoneg;
5639         bool negotiation;
5640
5641         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5642         autoneg = hw->phy.autoneg_advertised;
5643         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5644                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5645         hw->mac.autotry_restart = false;
5646         if (hw->mac.ops.setup_link)
5647                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5648         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5649         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5650 }
5651
5652 /**
5653  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5654  * @work: pointer to work_struct containing our data
5655  **/
5656 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5657 {
5658         struct ixgbe_adapter *adapter = container_of(work,
5659                                                      struct ixgbe_adapter,
5660                                                      sfp_config_module_task);
5661         struct ixgbe_hw *hw = &adapter->hw;
5662         u32 err;
5663
5664         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5665
5666         /* Time for electrical oscillations to settle down */
5667         msleep(100);
5668         err = hw->phy.ops.identify_sfp(hw);
5669
5670         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5671                 e_dev_err("failed to initialize because an unsupported SFP+ "
5672                           "module type was detected.\n");
5673                 e_dev_err("Reload the driver after installing a supported "
5674                           "module.\n");
5675                 unregister_netdev(adapter->netdev);
5676                 return;
5677         }
5678         hw->mac.ops.setup_sfp(hw);
5679
5680         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5681                 /* This will also work for DA Twinax connections */
5682                 schedule_work(&adapter->multispeed_fiber_task);
5683         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5684 }
5685
5686 /**
5687  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5688  * @work: pointer to work_struct containing our data
5689  **/
5690 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5691 {
5692         struct ixgbe_adapter *adapter = container_of(work,
5693                                                      struct ixgbe_adapter,
5694                                                      fdir_reinit_task);
5695         struct ixgbe_hw *hw = &adapter->hw;
5696         int i;
5697
5698         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5699                 for (i = 0; i < adapter->num_tx_queues; i++)
5700                         set_bit(__IXGBE_FDIR_INIT_DONE,
5701                                 &(adapter->tx_ring[i]->reinit_state));
5702         } else {
5703                 e_err(probe, "failed to finish FDIR re-initialization, "
5704                       "ignored adding FDIR ATR filters\n");
5705         }
5706         /* Done FDIR Re-initialization, enable transmits */
5707         netif_tx_start_all_queues(adapter->netdev);
5708 }
5709
5710 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5711
5712 /**
5713  * ixgbe_watchdog_task - worker thread to bring link up
5714  * @work: pointer to work_struct containing our data
5715  **/
5716 static void ixgbe_watchdog_task(struct work_struct *work)
5717 {
5718         struct ixgbe_adapter *adapter = container_of(work,
5719                                                      struct ixgbe_adapter,
5720                                                      watchdog_task);
5721         struct net_device *netdev = adapter->netdev;
5722         struct ixgbe_hw *hw = &adapter->hw;
5723         u32 link_speed;
5724         bool link_up;
5725         int i;
5726         struct ixgbe_ring *tx_ring;
5727         int some_tx_pending = 0;
5728
5729         mutex_lock(&ixgbe_watchdog_lock);
5730
5731         link_up = adapter->link_up;
5732         link_speed = adapter->link_speed;
5733
5734         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5735                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5736                 if (link_up) {
5737 #ifdef CONFIG_DCB
5738                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5739                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5740                                         hw->mac.ops.fc_enable(hw, i);
5741                         } else {
5742                                 hw->mac.ops.fc_enable(hw, 0);
5743                         }
5744 #else
5745                         hw->mac.ops.fc_enable(hw, 0);
5746 #endif
5747                 }
5748
5749                 if (link_up ||
5750                     time_after(jiffies, (adapter->link_check_timeout +
5751                                          IXGBE_TRY_LINK_TIMEOUT))) {
5752                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5753                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5754                 }
5755                 adapter->link_up = link_up;
5756                 adapter->link_speed = link_speed;
5757         }
5758
5759         if (link_up) {
5760                 if (!netif_carrier_ok(netdev)) {
5761                         bool flow_rx, flow_tx;
5762
5763                         if (hw->mac.type == ixgbe_mac_82599EB) {
5764                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5765                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5766                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5767                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5768                         } else {
5769                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5770                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5771                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5772                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5773                         }
5774
5775                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5776                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5777                                "10 Gbps" :
5778                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5779                                "1 Gbps" : "unknown speed")),
5780                                ((flow_rx && flow_tx) ? "RX/TX" :
5781                                (flow_rx ? "RX" :
5782                                (flow_tx ? "TX" : "None"))));
5783
5784                         netif_carrier_on(netdev);
5785                 } else {
5786                         /* Force detection of hung controller */
5787                         adapter->detect_tx_hung = true;
5788                 }
5789         } else {
5790                 adapter->link_up = false;
5791                 adapter->link_speed = 0;
5792                 if (netif_carrier_ok(netdev)) {
5793                         e_info(drv, "NIC Link is Down\n");
5794                         netif_carrier_off(netdev);
5795                 }
5796         }
5797
5798         if (!netif_carrier_ok(netdev)) {
5799                 for (i = 0; i < adapter->num_tx_queues; i++) {
5800                         tx_ring = adapter->tx_ring[i];
5801                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5802                                 some_tx_pending = 1;
5803                                 break;
5804                         }
5805                 }
5806
5807                 if (some_tx_pending) {
5808                         /* We've lost link, so the controller stops DMA,
5809                          * but we've got queued Tx work that's never going
5810                          * to get done, so reset controller to flush Tx.
5811                          * (Do the reset outside of interrupt context).
5812                          */
5813                          schedule_work(&adapter->reset_task);
5814                 }
5815         }
5816
5817         ixgbe_update_stats(adapter);
5818         mutex_unlock(&ixgbe_watchdog_lock);
5819 }
5820
5821 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5822                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5823                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5824 {
5825         struct ixgbe_adv_tx_context_desc *context_desc;
5826         unsigned int i;
5827         int err;
5828         struct ixgbe_tx_buffer *tx_buffer_info;
5829         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5830         u32 mss_l4len_idx, l4len;
5831
5832         if (skb_is_gso(skb)) {
5833                 if (skb_header_cloned(skb)) {
5834                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5835                         if (err)
5836                                 return err;
5837                 }
5838                 l4len = tcp_hdrlen(skb);
5839                 *hdr_len += l4len;
5840
5841                 if (protocol == htons(ETH_P_IP)) {
5842                         struct iphdr *iph = ip_hdr(skb);
5843                         iph->tot_len = 0;
5844                         iph->check = 0;
5845                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5846                                                                  iph->daddr, 0,
5847                                                                  IPPROTO_TCP,
5848                                                                  0);
5849                 } else if (skb_is_gso_v6(skb)) {
5850                         ipv6_hdr(skb)->payload_len = 0;
5851                         tcp_hdr(skb)->check =
5852                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5853                                              &ipv6_hdr(skb)->daddr,
5854                                              0, IPPROTO_TCP, 0);
5855                 }
5856
5857                 i = tx_ring->next_to_use;
5858
5859                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5860                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5861
5862                 /* VLAN MACLEN IPLEN */
5863                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5864                         vlan_macip_lens |=
5865                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5866                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5867                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5868                 *hdr_len += skb_network_offset(skb);
5869                 vlan_macip_lens |=
5870                     (skb_transport_header(skb) - skb_network_header(skb));
5871                 *hdr_len +=
5872                     (skb_transport_header(skb) - skb_network_header(skb));
5873                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5874                 context_desc->seqnum_seed = 0;
5875
5876                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5877                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5878                                    IXGBE_ADVTXD_DTYP_CTXT);
5879
5880                 if (protocol == htons(ETH_P_IP))
5881                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5882                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5883                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5884
5885                 /* MSS L4LEN IDX */
5886                 mss_l4len_idx =
5887                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5888                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5889                 /* use index 1 for TSO */
5890                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5891                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5892
5893                 tx_buffer_info->time_stamp = jiffies;
5894                 tx_buffer_info->next_to_watch = i;
5895
5896                 i++;
5897                 if (i == tx_ring->count)
5898                         i = 0;
5899                 tx_ring->next_to_use = i;
5900
5901                 return true;
5902         }
5903         return false;
5904 }
5905
5906 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5907                       __be16 protocol)
5908 {
5909         u32 rtn = 0;
5910
5911         switch (protocol) {
5912         case cpu_to_be16(ETH_P_IP):
5913                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5914                 switch (ip_hdr(skb)->protocol) {
5915                 case IPPROTO_TCP:
5916                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5917                         break;
5918                 case IPPROTO_SCTP:
5919                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5920                         break;
5921                 }
5922                 break;
5923         case cpu_to_be16(ETH_P_IPV6):
5924                 /* XXX what about other V6 headers?? */
5925                 switch (ipv6_hdr(skb)->nexthdr) {
5926                 case IPPROTO_TCP:
5927                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5928                         break;
5929                 case IPPROTO_SCTP:
5930                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5931                         break;
5932                 }
5933                 break;
5934         default:
5935                 if (unlikely(net_ratelimit()))
5936                         e_warn(probe, "partial checksum but proto=%x!\n",
5937                                protocol);
5938                 break;
5939         }
5940
5941         return rtn;
5942 }
5943
5944 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5945                           struct ixgbe_ring *tx_ring,
5946                           struct sk_buff *skb, u32 tx_flags,
5947                           __be16 protocol)
5948 {
5949         struct ixgbe_adv_tx_context_desc *context_desc;
5950         unsigned int i;
5951         struct ixgbe_tx_buffer *tx_buffer_info;
5952         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5953
5954         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5955             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5956                 i = tx_ring->next_to_use;
5957                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5958                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5959
5960                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5961                         vlan_macip_lens |=
5962                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5963                 vlan_macip_lens |= (skb_network_offset(skb) <<
5964                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5965                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5966                         vlan_macip_lens |= (skb_transport_header(skb) -
5967                                             skb_network_header(skb));
5968
5969                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5970                 context_desc->seqnum_seed = 0;
5971
5972                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5973                                     IXGBE_ADVTXD_DTYP_CTXT);
5974
5975                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5976                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
5977
5978                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5979                 /* use index zero for tx checksum offload */
5980                 context_desc->mss_l4len_idx = 0;
5981
5982                 tx_buffer_info->time_stamp = jiffies;
5983                 tx_buffer_info->next_to_watch = i;
5984
5985                 i++;
5986                 if (i == tx_ring->count)
5987                         i = 0;
5988                 tx_ring->next_to_use = i;
5989
5990                 return true;
5991         }
5992
5993         return false;
5994 }
5995
5996 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5997                         struct ixgbe_ring *tx_ring,
5998                         struct sk_buff *skb, u32 tx_flags,
5999                         unsigned int first, const u8 hdr_len)
6000 {
6001         struct pci_dev *pdev = adapter->pdev;
6002         struct ixgbe_tx_buffer *tx_buffer_info;
6003         unsigned int len;
6004         unsigned int total = skb->len;
6005         unsigned int offset = 0, size, count = 0, i;
6006         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6007         unsigned int f;
6008         unsigned int bytecount = skb->len;
6009         u16 gso_segs = 1;
6010
6011         i = tx_ring->next_to_use;
6012
6013         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6014                 /* excluding fcoe_crc_eof for FCoE */
6015                 total -= sizeof(struct fcoe_crc_eof);
6016
6017         len = min(skb_headlen(skb), total);
6018         while (len) {
6019                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6020                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6021
6022                 tx_buffer_info->length = size;
6023                 tx_buffer_info->mapped_as_page = false;
6024                 tx_buffer_info->dma = dma_map_single(&pdev->dev,
6025                                                      skb->data + offset,
6026                                                      size, DMA_TO_DEVICE);
6027                 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6028                         goto dma_error;
6029                 tx_buffer_info->time_stamp = jiffies;
6030                 tx_buffer_info->next_to_watch = i;
6031
6032                 len -= size;
6033                 total -= size;
6034                 offset += size;
6035                 count++;
6036
6037                 if (len) {
6038                         i++;
6039                         if (i == tx_ring->count)
6040                                 i = 0;
6041                 }
6042         }
6043
6044         for (f = 0; f < nr_frags; f++) {
6045                 struct skb_frag_struct *frag;
6046
6047                 frag = &skb_shinfo(skb)->frags[f];
6048                 len = min((unsigned int)frag->size, total);
6049                 offset = frag->page_offset;
6050
6051                 while (len) {
6052                         i++;
6053                         if (i == tx_ring->count)
6054                                 i = 0;
6055
6056                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6057                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6058
6059                         tx_buffer_info->length = size;
6060                         tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
6061                                                            frag->page,
6062                                                            offset, size,
6063                                                            DMA_TO_DEVICE);
6064                         tx_buffer_info->mapped_as_page = true;
6065                         if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6066                                 goto dma_error;
6067                         tx_buffer_info->time_stamp = jiffies;
6068                         tx_buffer_info->next_to_watch = i;
6069
6070                         len -= size;
6071                         total -= size;
6072                         offset += size;
6073                         count++;
6074                 }
6075                 if (total == 0)
6076                         break;
6077         }
6078
6079         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6080                 gso_segs = skb_shinfo(skb)->gso_segs;
6081 #ifdef IXGBE_FCOE
6082         /* adjust for FCoE Sequence Offload */
6083         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6084                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6085                                         skb_shinfo(skb)->gso_size);
6086 #endif /* IXGBE_FCOE */
6087         bytecount += (gso_segs - 1) * hdr_len;
6088
6089         /* multiply data chunks by size of headers */
6090         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6091         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6092         tx_ring->tx_buffer_info[i].skb = skb;
6093         tx_ring->tx_buffer_info[first].next_to_watch = i;
6094
6095         return count;
6096
6097 dma_error:
6098         e_dev_err("TX DMA map failed\n");
6099
6100         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6101         tx_buffer_info->dma = 0;
6102         tx_buffer_info->time_stamp = 0;
6103         tx_buffer_info->next_to_watch = 0;
6104         if (count)
6105                 count--;
6106
6107         /* clear timestamp and dma mappings for remaining portion of packet */
6108         while (count--) {
6109                 if (i == 0)
6110                         i += tx_ring->count;
6111                 i--;
6112                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6113                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6114         }
6115
6116         return 0;
6117 }
6118
6119 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6120                            struct ixgbe_ring *tx_ring,
6121                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6122 {
6123         union ixgbe_adv_tx_desc *tx_desc = NULL;
6124         struct ixgbe_tx_buffer *tx_buffer_info;
6125         u32 olinfo_status = 0, cmd_type_len = 0;
6126         unsigned int i;
6127         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6128
6129         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6130
6131         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6132
6133         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6134                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6135
6136         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6137                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6138
6139                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6140                                  IXGBE_ADVTXD_POPTS_SHIFT;
6141
6142                 /* use index 1 context for tso */
6143                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6144                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6145                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6146                                          IXGBE_ADVTXD_POPTS_SHIFT;
6147
6148         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6149                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6150                                  IXGBE_ADVTXD_POPTS_SHIFT;
6151
6152         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6153                 olinfo_status |= IXGBE_ADVTXD_CC;
6154                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6155                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6156                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6157         }
6158
6159         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6160
6161         i = tx_ring->next_to_use;
6162         while (count--) {
6163                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6164                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6165                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6166                 tx_desc->read.cmd_type_len =
6167                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6168                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6169                 i++;
6170                 if (i == tx_ring->count)
6171                         i = 0;
6172         }
6173
6174         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6175
6176         /*
6177          * Force memory writes to complete before letting h/w
6178          * know there are new descriptors to fetch.  (Only
6179          * applicable for weak-ordered memory model archs,
6180          * such as IA-64).
6181          */
6182         wmb();
6183
6184         tx_ring->next_to_use = i;
6185         writel(i, adapter->hw.hw_addr + tx_ring->tail);
6186 }
6187
6188 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6189                       int queue, u32 tx_flags, __be16 protocol)
6190 {
6191         struct ixgbe_atr_input atr_input;
6192         struct tcphdr *th;
6193         struct iphdr *iph = ip_hdr(skb);
6194         struct ethhdr *eth = (struct ethhdr *)skb->data;
6195         u16 vlan_id, src_port, dst_port, flex_bytes;
6196         u32 src_ipv4_addr, dst_ipv4_addr;
6197         u8 l4type = 0;
6198
6199         /* Right now, we support IPv4 only */
6200         if (protocol != htons(ETH_P_IP))
6201                 return;
6202         /* check if we're UDP or TCP */
6203         if (iph->protocol == IPPROTO_TCP) {
6204                 th = tcp_hdr(skb);
6205                 src_port = th->source;
6206                 dst_port = th->dest;
6207                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6208                 /* l4type IPv4 type is 0, no need to assign */
6209         } else {
6210                 /* Unsupported L4 header, just bail here */
6211                 return;
6212         }
6213
6214         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6215
6216         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6217                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6218         src_ipv4_addr = iph->saddr;
6219         dst_ipv4_addr = iph->daddr;
6220         flex_bytes = eth->h_proto;
6221
6222         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6223         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6224         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6225         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6226         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6227         /* src and dst are inverted, think how the receiver sees them */
6228         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6229         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6230
6231         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6232         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6233 }
6234
6235 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6236                                  struct ixgbe_ring *tx_ring, int size)
6237 {
6238         netif_stop_subqueue(netdev, tx_ring->queue_index);
6239         /* Herbert's original patch had:
6240          *  smp_mb__after_netif_stop_queue();
6241          * but since that doesn't exist yet, just open code it. */
6242         smp_mb();
6243
6244         /* We need to check again in a case another CPU has just
6245          * made room available. */
6246         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6247                 return -EBUSY;
6248
6249         /* A reprieve! - use start_queue because it doesn't call schedule */
6250         netif_start_subqueue(netdev, tx_ring->queue_index);
6251         ++tx_ring->restart_queue;
6252         return 0;
6253 }
6254
6255 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6256                               struct ixgbe_ring *tx_ring, int size)
6257 {
6258         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6259                 return 0;
6260         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6261 }
6262
6263 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6264 {
6265         struct ixgbe_adapter *adapter = netdev_priv(dev);
6266         int txq = smp_processor_id();
6267 #ifdef IXGBE_FCOE
6268         __be16 protocol;
6269
6270         protocol = vlan_get_protocol(skb);
6271
6272         if ((protocol == htons(ETH_P_FCOE)) ||
6273             (protocol == htons(ETH_P_FIP))) {
6274                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6275                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6276                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6277                         return txq;
6278 #ifdef CONFIG_IXGBE_DCB
6279                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6280                         txq = adapter->fcoe.up;
6281                         return txq;
6282 #endif
6283                 }
6284         }
6285 #endif
6286
6287         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6288                 while (unlikely(txq >= dev->real_num_tx_queues))
6289                         txq -= dev->real_num_tx_queues;
6290                 return txq;
6291         }
6292
6293         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6294                 if (skb->priority == TC_PRIO_CONTROL)
6295                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6296                 else
6297                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6298                                >> 13;
6299                 return txq;
6300         }
6301
6302         return skb_tx_hash(dev, skb);
6303 }
6304
6305 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6306                           struct ixgbe_adapter *adapter,
6307                           struct ixgbe_ring *tx_ring)
6308 {
6309         struct netdev_queue *txq;
6310         unsigned int first;
6311         unsigned int tx_flags = 0;
6312         u8 hdr_len = 0;
6313         int tso;
6314         int count = 0;
6315         unsigned int f;
6316         __be16 protocol;
6317
6318         protocol = vlan_get_protocol(skb);
6319
6320         if (vlan_tx_tag_present(skb)) {
6321                 tx_flags |= vlan_tx_tag_get(skb);
6322                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6323                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6324                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6325                 }
6326                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6327                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6328         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6329                    skb->priority != TC_PRIO_CONTROL) {
6330                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6331                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6332                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6333         }
6334
6335 #ifdef IXGBE_FCOE
6336         /* for FCoE with DCB, we force the priority to what
6337          * was specified by the switch */
6338         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6339             (protocol == htons(ETH_P_FCOE) ||
6340              protocol == htons(ETH_P_FIP))) {
6341 #ifdef CONFIG_IXGBE_DCB
6342                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6343                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6344                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6345                         tx_flags |= ((adapter->fcoe.up << 13)
6346                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6347                 }
6348 #endif
6349                 /* flag for FCoE offloads */
6350                 if (protocol == htons(ETH_P_FCOE))
6351                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6352         }
6353 #endif
6354
6355         /* four things can cause us to need a context descriptor */
6356         if (skb_is_gso(skb) ||
6357             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6358             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6359             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6360                 count++;
6361
6362         count += TXD_USE_COUNT(skb_headlen(skb));
6363         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6364                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6365
6366         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6367                 adapter->tx_busy++;
6368                 return NETDEV_TX_BUSY;
6369         }
6370
6371         first = tx_ring->next_to_use;
6372         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6373 #ifdef IXGBE_FCOE
6374                 /* setup tx offload for FCoE */
6375                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6376                 if (tso < 0) {
6377                         dev_kfree_skb_any(skb);
6378                         return NETDEV_TX_OK;
6379                 }
6380                 if (tso)
6381                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6382 #endif /* IXGBE_FCOE */
6383         } else {
6384                 if (protocol == htons(ETH_P_IP))
6385                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6386                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6387                                 protocol);
6388                 if (tso < 0) {
6389                         dev_kfree_skb_any(skb);
6390                         return NETDEV_TX_OK;
6391                 }
6392
6393                 if (tso)
6394                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6395                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6396                                        protocol) &&
6397                          (skb->ip_summed == CHECKSUM_PARTIAL))
6398                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6399         }
6400
6401         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6402         if (count) {
6403                 /* add the ATR filter if ATR is on */
6404                 if (tx_ring->atr_sample_rate) {
6405                         ++tx_ring->atr_count;
6406                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6407                              test_bit(__IXGBE_FDIR_INIT_DONE,
6408                                       &tx_ring->reinit_state)) {
6409                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6410                                           tx_flags, protocol);
6411                                 tx_ring->atr_count = 0;
6412                         }
6413                 }
6414                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6415                 txq->tx_bytes += skb->len;
6416                 txq->tx_packets++;
6417                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6418                                hdr_len);
6419                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6420
6421         } else {
6422                 dev_kfree_skb_any(skb);
6423                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6424                 tx_ring->next_to_use = first;
6425         }
6426
6427         return NETDEV_TX_OK;
6428 }
6429
6430 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6431 {
6432         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6433         struct ixgbe_ring *tx_ring;
6434
6435         tx_ring = adapter->tx_ring[skb->queue_mapping];
6436         return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6437 }
6438
6439 /**
6440  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6441  * @netdev: network interface device structure
6442  * @p: pointer to an address structure
6443  *
6444  * Returns 0 on success, negative on failure
6445  **/
6446 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6447 {
6448         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6449         struct ixgbe_hw *hw = &adapter->hw;
6450         struct sockaddr *addr = p;
6451
6452         if (!is_valid_ether_addr(addr->sa_data))
6453                 return -EADDRNOTAVAIL;
6454
6455         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6456         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6457
6458         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6459                             IXGBE_RAH_AV);
6460
6461         return 0;
6462 }
6463
6464 static int
6465 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6466 {
6467         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6468         struct ixgbe_hw *hw = &adapter->hw;
6469         u16 value;
6470         int rc;
6471
6472         if (prtad != hw->phy.mdio.prtad)
6473                 return -EINVAL;
6474         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6475         if (!rc)
6476                 rc = value;
6477         return rc;
6478 }
6479
6480 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6481                             u16 addr, u16 value)
6482 {
6483         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6484         struct ixgbe_hw *hw = &adapter->hw;
6485
6486         if (prtad != hw->phy.mdio.prtad)
6487                 return -EINVAL;
6488         return hw->phy.ops.write_reg(hw, addr, devad, value);
6489 }
6490
6491 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6492 {
6493         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6494
6495         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6496 }
6497
6498 /**
6499  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6500  * netdev->dev_addrs
6501  * @netdev: network interface device structure
6502  *
6503  * Returns non-zero on failure
6504  **/
6505 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6506 {
6507         int err = 0;
6508         struct ixgbe_adapter *adapter = netdev_priv(dev);
6509         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6510
6511         if (is_valid_ether_addr(mac->san_addr)) {
6512                 rtnl_lock();
6513                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6514                 rtnl_unlock();
6515         }
6516         return err;
6517 }
6518
6519 /**
6520  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6521  * netdev->dev_addrs
6522  * @netdev: network interface device structure
6523  *
6524  * Returns non-zero on failure
6525  **/
6526 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6527 {
6528         int err = 0;
6529         struct ixgbe_adapter *adapter = netdev_priv(dev);
6530         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6531
6532         if (is_valid_ether_addr(mac->san_addr)) {
6533                 rtnl_lock();
6534                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6535                 rtnl_unlock();
6536         }
6537         return err;
6538 }
6539
6540 #ifdef CONFIG_NET_POLL_CONTROLLER
6541 /*
6542  * Polling 'interrupt' - used by things like netconsole to send skbs
6543  * without having to re-enable interrupts. It's not called while
6544  * the interrupt routine is executing.
6545  */
6546 static void ixgbe_netpoll(struct net_device *netdev)
6547 {
6548         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6549         int i;
6550
6551         /* if interface is down do nothing */
6552         if (test_bit(__IXGBE_DOWN, &adapter->state))
6553                 return;
6554
6555         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6556         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6557                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6558                 for (i = 0; i < num_q_vectors; i++) {
6559                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6560                         ixgbe_msix_clean_many(0, q_vector);
6561                 }
6562         } else {
6563                 ixgbe_intr(adapter->pdev->irq, netdev);
6564         }
6565         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6566 }
6567 #endif
6568
6569 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6570                                                    struct rtnl_link_stats64 *stats)
6571 {
6572         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6573         int i;
6574
6575         /* accurate rx/tx bytes/packets stats */
6576         dev_txq_stats_fold(netdev, stats);
6577         rcu_read_lock();
6578         for (i = 0; i < adapter->num_rx_queues; i++) {
6579                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6580                 u64 bytes, packets;
6581                 unsigned int start;
6582
6583                 if (ring) {
6584                         do {
6585                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6586                                 packets = ring->stats.packets;
6587                                 bytes   = ring->stats.bytes;
6588                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6589                         stats->rx_packets += packets;
6590                         stats->rx_bytes   += bytes;
6591                 }
6592         }
6593         rcu_read_unlock();
6594         /* following stats updated by ixgbe_watchdog_task() */
6595         stats->multicast        = netdev->stats.multicast;
6596         stats->rx_errors        = netdev->stats.rx_errors;
6597         stats->rx_length_errors = netdev->stats.rx_length_errors;
6598         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6599         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6600         return stats;
6601 }
6602
6603
6604 static const struct net_device_ops ixgbe_netdev_ops = {
6605         .ndo_open               = ixgbe_open,
6606         .ndo_stop               = ixgbe_close,
6607         .ndo_start_xmit         = ixgbe_xmit_frame,
6608         .ndo_select_queue       = ixgbe_select_queue,
6609         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6610         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6611         .ndo_validate_addr      = eth_validate_addr,
6612         .ndo_set_mac_address    = ixgbe_set_mac,
6613         .ndo_change_mtu         = ixgbe_change_mtu,
6614         .ndo_tx_timeout         = ixgbe_tx_timeout,
6615         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6616         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6617         .ndo_do_ioctl           = ixgbe_ioctl,
6618         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6619         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6620         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6621         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6622         .ndo_get_stats64        = ixgbe_get_stats64,
6623 #ifdef CONFIG_NET_POLL_CONTROLLER
6624         .ndo_poll_controller    = ixgbe_netpoll,
6625 #endif
6626 #ifdef IXGBE_FCOE
6627         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6628         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6629         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6630         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6631         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6632 #endif /* IXGBE_FCOE */
6633 };
6634
6635 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6636                            const struct ixgbe_info *ii)
6637 {
6638 #ifdef CONFIG_PCI_IOV
6639         struct ixgbe_hw *hw = &adapter->hw;
6640         int err;
6641
6642         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6643                 return;
6644
6645         /* The 82599 supports up to 64 VFs per physical function
6646          * but this implementation limits allocation to 63 so that
6647          * basic networking resources are still available to the
6648          * physical function
6649          */
6650         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6651         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6652         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6653         if (err) {
6654                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6655                 goto err_novfs;
6656         }
6657         /* If call to enable VFs succeeded then allocate memory
6658          * for per VF control structures.
6659          */
6660         adapter->vfinfo =
6661                 kcalloc(adapter->num_vfs,
6662                         sizeof(struct vf_data_storage), GFP_KERNEL);
6663         if (adapter->vfinfo) {
6664                 /* Now that we're sure SR-IOV is enabled
6665                  * and memory allocated set up the mailbox parameters
6666                  */
6667                 ixgbe_init_mbx_params_pf(hw);
6668                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6669                        sizeof(hw->mbx.ops));
6670
6671                 /* Disable RSC when in SR-IOV mode */
6672                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6673                                      IXGBE_FLAG2_RSC_ENABLED);
6674                 return;
6675         }
6676
6677         /* Oh oh */
6678         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6679               "SRIOV disabled\n");
6680         pci_disable_sriov(adapter->pdev);
6681
6682 err_novfs:
6683         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6684         adapter->num_vfs = 0;
6685 #endif /* CONFIG_PCI_IOV */
6686 }
6687
6688 /**
6689  * ixgbe_probe - Device Initialization Routine
6690  * @pdev: PCI device information struct
6691  * @ent: entry in ixgbe_pci_tbl
6692  *
6693  * Returns 0 on success, negative on failure
6694  *
6695  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6696  * The OS initialization, configuring of the adapter private structure,
6697  * and a hardware reset occur.
6698  **/
6699 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6700                                  const struct pci_device_id *ent)
6701 {
6702         struct net_device *netdev;
6703         struct ixgbe_adapter *adapter = NULL;
6704         struct ixgbe_hw *hw;
6705         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6706         static int cards_found;
6707         int i, err, pci_using_dac;
6708         unsigned int indices = num_possible_cpus();
6709 #ifdef IXGBE_FCOE
6710         u16 device_caps;
6711 #endif
6712         u32 part_num, eec;
6713
6714         /* Catch broken hardware that put the wrong VF device ID in
6715          * the PCIe SR-IOV capability.
6716          */
6717         if (pdev->is_virtfn) {
6718                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6719                      pci_name(pdev), pdev->vendor, pdev->device);
6720                 return -EINVAL;
6721         }
6722
6723         err = pci_enable_device_mem(pdev);
6724         if (err)
6725                 return err;
6726
6727         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6728             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6729                 pci_using_dac = 1;
6730         } else {
6731                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6732                 if (err) {
6733                         err = dma_set_coherent_mask(&pdev->dev,
6734                                                     DMA_BIT_MASK(32));
6735                         if (err) {
6736                                 dev_err(&pdev->dev,
6737                                         "No usable DMA configuration, aborting\n");
6738                                 goto err_dma;
6739                         }
6740                 }
6741                 pci_using_dac = 0;
6742         }
6743
6744         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6745                                            IORESOURCE_MEM), ixgbe_driver_name);
6746         if (err) {
6747                 dev_err(&pdev->dev,
6748                         "pci_request_selected_regions failed 0x%x\n", err);
6749                 goto err_pci_reg;
6750         }
6751
6752         pci_enable_pcie_error_reporting(pdev);
6753
6754         pci_set_master(pdev);
6755         pci_save_state(pdev);
6756
6757         if (ii->mac == ixgbe_mac_82598EB)
6758                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6759         else
6760                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6761
6762         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6763 #ifdef IXGBE_FCOE
6764         indices += min_t(unsigned int, num_possible_cpus(),
6765                          IXGBE_MAX_FCOE_INDICES);
6766 #endif
6767         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6768         if (!netdev) {
6769                 err = -ENOMEM;
6770                 goto err_alloc_etherdev;
6771         }
6772
6773         SET_NETDEV_DEV(netdev, &pdev->dev);
6774
6775         pci_set_drvdata(pdev, netdev);
6776         adapter = netdev_priv(netdev);
6777
6778         adapter->netdev = netdev;
6779         adapter->pdev = pdev;
6780         hw = &adapter->hw;
6781         hw->back = adapter;
6782         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6783
6784         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6785                               pci_resource_len(pdev, 0));
6786         if (!hw->hw_addr) {
6787                 err = -EIO;
6788                 goto err_ioremap;
6789         }
6790
6791         for (i = 1; i <= 5; i++) {
6792                 if (pci_resource_len(pdev, i) == 0)
6793                         continue;
6794         }
6795
6796         netdev->netdev_ops = &ixgbe_netdev_ops;
6797         ixgbe_set_ethtool_ops(netdev);
6798         netdev->watchdog_timeo = 5 * HZ;
6799         strcpy(netdev->name, pci_name(pdev));
6800
6801         adapter->bd_number = cards_found;
6802
6803         /* Setup hw api */
6804         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6805         hw->mac.type  = ii->mac;
6806
6807         /* EEPROM */
6808         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6809         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6810         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6811         if (!(eec & (1 << 8)))
6812                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6813
6814         /* PHY */
6815         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6816         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6817         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6818         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6819         hw->phy.mdio.mmds = 0;
6820         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6821         hw->phy.mdio.dev = netdev;
6822         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6823         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6824
6825         /* set up this timer and work struct before calling get_invariants
6826          * which might start the timer
6827          */
6828         init_timer(&adapter->sfp_timer);
6829         adapter->sfp_timer.function = ixgbe_sfp_timer;
6830         adapter->sfp_timer.data = (unsigned long) adapter;
6831
6832         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6833
6834         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6835         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6836
6837         /* a new SFP+ module arrival, called from GPI SDP2 context */
6838         INIT_WORK(&adapter->sfp_config_module_task,
6839                   ixgbe_sfp_config_module_task);
6840
6841         ii->get_invariants(hw);
6842
6843         /* setup the private structure */
6844         err = ixgbe_sw_init(adapter);
6845         if (err)
6846                 goto err_sw_init;
6847
6848         /* Make it possible the adapter to be woken up via WOL */
6849         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6850                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6851
6852         /*
6853          * If there is a fan on this device and it has failed log the
6854          * failure.
6855          */
6856         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6857                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6858                 if (esdp & IXGBE_ESDP_SDP1)
6859                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6860         }
6861
6862         /* reset_hw fills in the perm_addr as well */
6863         hw->phy.reset_if_overtemp = true;
6864         err = hw->mac.ops.reset_hw(hw);
6865         hw->phy.reset_if_overtemp = false;
6866         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6867             hw->mac.type == ixgbe_mac_82598EB) {
6868                 /*
6869                  * Start a kernel thread to watch for a module to arrive.
6870                  * Only do this for 82598, since 82599 will generate
6871                  * interrupts on module arrival.
6872                  */
6873                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6874                 mod_timer(&adapter->sfp_timer,
6875                           round_jiffies(jiffies + (2 * HZ)));
6876                 err = 0;
6877         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6878                 e_dev_err("failed to initialize because an unsupported SFP+ "
6879                           "module type was detected.\n");
6880                 e_dev_err("Reload the driver after installing a supported "
6881                           "module.\n");
6882                 goto err_sw_init;
6883         } else if (err) {
6884                 e_dev_err("HW Init failed: %d\n", err);
6885                 goto err_sw_init;
6886         }
6887
6888         ixgbe_probe_vf(adapter, ii);
6889
6890         netdev->features = NETIF_F_SG |
6891                            NETIF_F_IP_CSUM |
6892                            NETIF_F_HW_VLAN_TX |
6893                            NETIF_F_HW_VLAN_RX |
6894                            NETIF_F_HW_VLAN_FILTER;
6895
6896         netdev->features |= NETIF_F_IPV6_CSUM;
6897         netdev->features |= NETIF_F_TSO;
6898         netdev->features |= NETIF_F_TSO6;
6899         netdev->features |= NETIF_F_GRO;
6900
6901         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6902                 netdev->features |= NETIF_F_SCTP_CSUM;
6903
6904         netdev->vlan_features |= NETIF_F_TSO;
6905         netdev->vlan_features |= NETIF_F_TSO6;
6906         netdev->vlan_features |= NETIF_F_IP_CSUM;
6907         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6908         netdev->vlan_features |= NETIF_F_SG;
6909
6910         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6911                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6912                                     IXGBE_FLAG_DCB_ENABLED);
6913         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6914                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6915
6916 #ifdef CONFIG_IXGBE_DCB
6917         netdev->dcbnl_ops = &dcbnl_ops;
6918 #endif
6919
6920 #ifdef IXGBE_FCOE
6921         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6922                 if (hw->mac.ops.get_device_caps) {
6923                         hw->mac.ops.get_device_caps(hw, &device_caps);
6924                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6925                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6926                 }
6927         }
6928         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6929                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6930                 netdev->vlan_features |= NETIF_F_FSO;
6931                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6932         }
6933 #endif /* IXGBE_FCOE */
6934         if (pci_using_dac) {
6935                 netdev->features |= NETIF_F_HIGHDMA;
6936                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6937         }
6938
6939         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6940                 netdev->features |= NETIF_F_LRO;
6941
6942         /* make sure the EEPROM is good */
6943         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6944                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6945                 err = -EIO;
6946                 goto err_eeprom;
6947         }
6948
6949         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6950         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6951
6952         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6953                 e_dev_err("invalid MAC address\n");
6954                 err = -EIO;
6955                 goto err_eeprom;
6956         }
6957
6958         /* power down the optics */
6959         if (hw->phy.multispeed_fiber)
6960                 hw->mac.ops.disable_tx_laser(hw);
6961
6962         init_timer(&adapter->watchdog_timer);
6963         adapter->watchdog_timer.function = ixgbe_watchdog;
6964         adapter->watchdog_timer.data = (unsigned long)adapter;
6965
6966         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6967         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6968
6969         err = ixgbe_init_interrupt_scheme(adapter);
6970         if (err)
6971                 goto err_sw_init;
6972
6973         switch (pdev->device) {
6974         case IXGBE_DEV_ID_82599_KX4:
6975                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6976                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6977                 break;
6978         default:
6979                 adapter->wol = 0;
6980                 break;
6981         }
6982         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6983
6984         /* pick up the PCI bus settings for reporting later */
6985         hw->mac.ops.get_bus_info(hw);
6986
6987         /* print bus type/speed/width info */
6988         e_dev_info("(PCI Express:%s:%s) %pM\n",
6989                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6990                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6991                     "Unknown"),
6992                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6993                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6994                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6995                     "Unknown"),
6996                    netdev->dev_addr);
6997         ixgbe_read_pba_num_generic(hw, &part_num);
6998         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6999                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7000                            "PBA No: %06x-%03x\n",
7001                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7002                            (part_num >> 8), (part_num & 0xff));
7003         else
7004                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7005                            hw->mac.type, hw->phy.type,
7006                            (part_num >> 8), (part_num & 0xff));
7007
7008         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7009                 e_dev_warn("PCI-Express bandwidth available for this card is "
7010                            "not sufficient for optimal performance.\n");
7011                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7012                            "is required.\n");
7013         }
7014
7015         /* save off EEPROM version number */
7016         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7017
7018         /* reset the hardware with the new settings */
7019         err = hw->mac.ops.start_hw(hw);
7020
7021         if (err == IXGBE_ERR_EEPROM_VERSION) {
7022                 /* We are running on a pre-production device, log a warning */
7023                 e_dev_warn("This device is a pre-production adapter/LOM. "
7024                            "Please be aware there may be issues associated "
7025                            "with your hardware.  If you are experiencing "
7026                            "problems please contact your Intel or hardware "
7027                            "representative who provided you with this "
7028                            "hardware.\n");
7029         }
7030         strcpy(netdev->name, "eth%d");
7031         err = register_netdev(netdev);
7032         if (err)
7033                 goto err_register;
7034
7035         /* carrier off reporting is important to ethtool even BEFORE open */
7036         netif_carrier_off(netdev);
7037
7038         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7039             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7040                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7041
7042         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7043                 INIT_WORK(&adapter->check_overtemp_task,
7044                           ixgbe_check_overtemp_task);
7045 #ifdef CONFIG_IXGBE_DCA
7046         if (dca_add_requester(&pdev->dev) == 0) {
7047                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7048                 ixgbe_setup_dca(adapter);
7049         }
7050 #endif
7051         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7052                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7053                 for (i = 0; i < adapter->num_vfs; i++)
7054                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7055         }
7056
7057         /* add san mac addr to netdev */
7058         ixgbe_add_sanmac_netdev(netdev);
7059
7060         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7061         cards_found++;
7062         return 0;
7063
7064 err_register:
7065         ixgbe_release_hw_control(adapter);
7066         ixgbe_clear_interrupt_scheme(adapter);
7067 err_sw_init:
7068 err_eeprom:
7069         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7070                 ixgbe_disable_sriov(adapter);
7071         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7072         del_timer_sync(&adapter->sfp_timer);
7073         cancel_work_sync(&adapter->sfp_task);
7074         cancel_work_sync(&adapter->multispeed_fiber_task);
7075         cancel_work_sync(&adapter->sfp_config_module_task);
7076         iounmap(hw->hw_addr);
7077 err_ioremap:
7078         free_netdev(netdev);
7079 err_alloc_etherdev:
7080         pci_release_selected_regions(pdev,
7081                                      pci_select_bars(pdev, IORESOURCE_MEM));
7082 err_pci_reg:
7083 err_dma:
7084         pci_disable_device(pdev);
7085         return err;
7086 }
7087
7088 /**
7089  * ixgbe_remove - Device Removal Routine
7090  * @pdev: PCI device information struct
7091  *
7092  * ixgbe_remove is called by the PCI subsystem to alert the driver
7093  * that it should release a PCI device.  The could be caused by a
7094  * Hot-Plug event, or because the driver is going to be removed from
7095  * memory.
7096  **/
7097 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7098 {
7099         struct net_device *netdev = pci_get_drvdata(pdev);
7100         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7101
7102         set_bit(__IXGBE_DOWN, &adapter->state);
7103         /* clear the module not found bit to make sure the worker won't
7104          * reschedule
7105          */
7106         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7107         del_timer_sync(&adapter->watchdog_timer);
7108
7109         del_timer_sync(&adapter->sfp_timer);
7110         cancel_work_sync(&adapter->watchdog_task);
7111         cancel_work_sync(&adapter->sfp_task);
7112         cancel_work_sync(&adapter->multispeed_fiber_task);
7113         cancel_work_sync(&adapter->sfp_config_module_task);
7114         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7115             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7116                 cancel_work_sync(&adapter->fdir_reinit_task);
7117         flush_scheduled_work();
7118
7119 #ifdef CONFIG_IXGBE_DCA
7120         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7121                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7122                 dca_remove_requester(&pdev->dev);
7123                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7124         }
7125
7126 #endif
7127 #ifdef IXGBE_FCOE
7128         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7129                 ixgbe_cleanup_fcoe(adapter);
7130
7131 #endif /* IXGBE_FCOE */
7132
7133         /* remove the added san mac */
7134         ixgbe_del_sanmac_netdev(netdev);
7135
7136         if (netdev->reg_state == NETREG_REGISTERED)
7137                 unregister_netdev(netdev);
7138
7139         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7140                 ixgbe_disable_sriov(adapter);
7141
7142         ixgbe_clear_interrupt_scheme(adapter);
7143
7144         ixgbe_release_hw_control(adapter);
7145
7146         iounmap(adapter->hw.hw_addr);
7147         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7148                                      IORESOURCE_MEM));
7149
7150         e_dev_info("complete\n");
7151
7152         free_netdev(netdev);
7153
7154         pci_disable_pcie_error_reporting(pdev);
7155
7156         pci_disable_device(pdev);
7157 }
7158
7159 /**
7160  * ixgbe_io_error_detected - called when PCI error is detected
7161  * @pdev: Pointer to PCI device
7162  * @state: The current pci connection state
7163  *
7164  * This function is called after a PCI bus error affecting
7165  * this device has been detected.
7166  */
7167 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7168                                                 pci_channel_state_t state)
7169 {
7170         struct net_device *netdev = pci_get_drvdata(pdev);
7171         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7172
7173         netif_device_detach(netdev);
7174
7175         if (state == pci_channel_io_perm_failure)
7176                 return PCI_ERS_RESULT_DISCONNECT;
7177
7178         if (netif_running(netdev))
7179                 ixgbe_down(adapter);
7180         pci_disable_device(pdev);
7181
7182         /* Request a slot reset. */
7183         return PCI_ERS_RESULT_NEED_RESET;
7184 }
7185
7186 /**
7187  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7188  * @pdev: Pointer to PCI device
7189  *
7190  * Restart the card from scratch, as if from a cold-boot.
7191  */
7192 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7193 {
7194         struct net_device *netdev = pci_get_drvdata(pdev);
7195         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7196         pci_ers_result_t result;
7197         int err;
7198
7199         if (pci_enable_device_mem(pdev)) {
7200                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7201                 result = PCI_ERS_RESULT_DISCONNECT;
7202         } else {
7203                 pci_set_master(pdev);
7204                 pci_restore_state(pdev);
7205                 pci_save_state(pdev);
7206
7207                 pci_wake_from_d3(pdev, false);
7208
7209                 ixgbe_reset(adapter);
7210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7211                 result = PCI_ERS_RESULT_RECOVERED;
7212         }
7213
7214         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7215         if (err) {
7216                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7217                           "failed 0x%0x\n", err);
7218                 /* non-fatal, continue */
7219         }
7220
7221         return result;
7222 }
7223
7224 /**
7225  * ixgbe_io_resume - called when traffic can start flowing again.
7226  * @pdev: Pointer to PCI device
7227  *
7228  * This callback is called when the error recovery driver tells us that
7229  * its OK to resume normal operation.
7230  */
7231 static void ixgbe_io_resume(struct pci_dev *pdev)
7232 {
7233         struct net_device *netdev = pci_get_drvdata(pdev);
7234         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7235
7236         if (netif_running(netdev)) {
7237                 if (ixgbe_up(adapter)) {
7238                         e_info(probe, "ixgbe_up failed after reset\n");
7239                         return;
7240                 }
7241         }
7242
7243         netif_device_attach(netdev);
7244 }
7245
7246 static struct pci_error_handlers ixgbe_err_handler = {
7247         .error_detected = ixgbe_io_error_detected,
7248         .slot_reset = ixgbe_io_slot_reset,
7249         .resume = ixgbe_io_resume,
7250 };
7251
7252 static struct pci_driver ixgbe_driver = {
7253         .name     = ixgbe_driver_name,
7254         .id_table = ixgbe_pci_tbl,
7255         .probe    = ixgbe_probe,
7256         .remove   = __devexit_p(ixgbe_remove),
7257 #ifdef CONFIG_PM
7258         .suspend  = ixgbe_suspend,
7259         .resume   = ixgbe_resume,
7260 #endif
7261         .shutdown = ixgbe_shutdown,
7262         .err_handler = &ixgbe_err_handler
7263 };
7264
7265 /**
7266  * ixgbe_init_module - Driver Registration Routine
7267  *
7268  * ixgbe_init_module is the first routine called when the driver is
7269  * loaded. All it does is register with the PCI subsystem.
7270  **/
7271 static int __init ixgbe_init_module(void)
7272 {
7273         int ret;
7274         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7275         pr_info("%s\n", ixgbe_copyright);
7276
7277 #ifdef CONFIG_IXGBE_DCA
7278         dca_register_notify(&dca_notifier);
7279 #endif
7280
7281         ret = pci_register_driver(&ixgbe_driver);
7282         return ret;
7283 }
7284
7285 module_init(ixgbe_init_module);
7286
7287 /**
7288  * ixgbe_exit_module - Driver Exit Cleanup Routine
7289  *
7290  * ixgbe_exit_module is called just before the driver is removed
7291  * from memory.
7292  **/
7293 static void __exit ixgbe_exit_module(void)
7294 {
7295 #ifdef CONFIG_IXGBE_DCA
7296         dca_unregister_notify(&dca_notifier);
7297 #endif
7298         pci_unregister_driver(&ixgbe_driver);
7299         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7300 }
7301
7302 #ifdef CONFIG_IXGBE_DCA
7303 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7304                             void *p)
7305 {
7306         int ret_val;
7307
7308         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7309                                          __ixgbe_notify_dca);
7310
7311         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7312 }
7313
7314 #endif /* CONFIG_IXGBE_DCA */
7315
7316 /**
7317  * ixgbe_get_hw_dev return device
7318  * used by hardware layer to print debugging information
7319  **/
7320 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7321 {
7322         struct ixgbe_adapter *adapter = hw->back;
7323         return adapter->netdev;
7324 }
7325
7326 module_exit(ixgbe_exit_module);
7327
7328 /* ixgbe_main.c */