drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         adapter->detect_tx_hung = false;
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int i, eop, count = 0;
 739         unsigned int total_bytes = 0, total_packets = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774
 775 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 776         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 777                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 778                 /* Make sure that anybody stopping the queue after this
 779                  * sees the new next_to_clean.
 780                  */
 781                 smp_mb();
 782                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 783                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 784                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 785                         ++tx_ring->tx_stats.restart_queue;
 786                 }
 787         }
 788
 789         if (adapter->detect_tx_hung) {
 790                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 791                         /* schedule immediate reset if we believe we hung */
 792                         e_info(probe, "tx hang %d detected, resetting "
 793                                "adapter\n", adapter->tx_timeout_count + 1);
 794                         ixgbe_tx_timeout(adapter->netdev);
 795                 }
 796         }
 797
 798         /* re-arm the interrupt */
 799         if (count >= tx_ring->work_limit)
 800                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 801
 802         tx_ring->total_bytes += total_bytes;
 803         tx_ring->total_packets += total_packets;
 804         u64_stats_update_begin(&tx_ring->syncp);
 805         tx_ring->stats.packets += total_packets;
 806         tx_ring->stats.bytes += total_bytes;
 807         u64_stats_update_end(&tx_ring->syncp);
 808         return count < tx_ring->work_limit;
 809 }
 810
 811 #ifdef CONFIG_IXGBE_DCA
 812 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 813                                 struct ixgbe_ring *rx_ring)
 814 {
 815         u32 rxctrl;
 816         int cpu = get_cpu();
 817         int q = rx_ring->reg_idx;
 818
 819         if (rx_ring->cpu != cpu) {
 820                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 821                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 822                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 823                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 824                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 825                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 826                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 827                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 828                 }
 829                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 830                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 831                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 832                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 833                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 834                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 835                 rx_ring->cpu = cpu;
 836         }
 837         put_cpu();
 838 }
 839
 840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 841                                 struct ixgbe_ring *tx_ring)
 842 {
 843         u32 txctrl;
 844         int cpu = get_cpu();
 845         int q = tx_ring->reg_idx;
 846         struct ixgbe_hw *hw = &adapter->hw;
 847
 848         if (tx_ring->cpu != cpu) {
 849                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 850                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
 851                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 852                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 853                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 854                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
 855                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 856                         txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
 857                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 858                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 859                                   IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 860                         txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 861                         IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
 862                 }
 863                 tx_ring->cpu = cpu;
 864         }
 865         put_cpu();
 866 }
 867
 868 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 869 {
 870         int i;
 871
 872         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 873                 return;
 874
 875         /* always use CB2 mode, difference is masked in the CB driver */
 876         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 877
 878         for (i = 0; i < adapter->num_tx_queues; i++) {
 879                 adapter->tx_ring[i]->cpu = -1;
 880                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
 881         }
 882         for (i = 0; i < adapter->num_rx_queues; i++) {
 883                 adapter->rx_ring[i]->cpu = -1;
 884                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
 885         }
 886 }
 887
 888 static int __ixgbe_notify_dca(struct device *dev, void *data)
 889 {
 890         struct net_device *netdev = dev_get_drvdata(dev);
 891         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 892         unsigned long event = *(unsigned long *)data;
 893
 894         switch (event) {
 895         case DCA_PROVIDER_ADD:
 896                 /* if we're already enabled, don't do it again */
 897                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 898                         break;
 899                 if (dca_add_requester(dev) == 0) {
 900                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 901                         ixgbe_setup_dca(adapter);
 902                         break;
 903                 }
 904                 /* Fall Through since DCA is disabled. */
 905         case DCA_PROVIDER_REMOVE:
 906                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 907                         dca_remove_requester(dev);
 908                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 909                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 910                 }
 911                 break;
 912         }
 913
 914         return 0;
 915 }
 916
 917 #endif /* CONFIG_IXGBE_DCA */
 918 /**
 919  * ixgbe_receive_skb - Send a completed packet up the stack
 920  * @adapter: board private structure
 921  * @skb: packet to send up
 922  * @status: hardware indication of status of receive
 923  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 924  * @rx_desc: rx descriptor
 925  **/
 926 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 927                               struct sk_buff *skb, u8 status,
 928                               struct ixgbe_ring *ring,
 929                               union ixgbe_adv_rx_desc *rx_desc)
 930 {
 931         struct ixgbe_adapter *adapter = q_vector->adapter;
 932         struct napi_struct *napi = &q_vector->napi;
 933         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 934         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 935
 936         if (is_vlan && (tag & VLAN_VID_MASK))
 937                 __vlan_hwaccel_put_tag(skb, tag);
 938
 939         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 940                 napi_gro_receive(napi, skb);
 941         else
 942                 netif_rx(skb);
 943 }
 944
 945 /**
 946  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 947  * @adapter: address of board private structure
 948  * @status_err: hardware indication of status of receive
 949  * @skb: skb currently being received and modified
 950  **/
 951 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 952                                      union ixgbe_adv_rx_desc *rx_desc,
 953                                      struct sk_buff *skb)
 954 {
 955         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 956
 957         skb_checksum_none_assert(skb);
 958
 959         /* Rx csum disabled */
 960         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 961                 return;
 962
 963         /* if IP and error */
 964         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 965             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 966                 adapter->hw_csum_rx_error++;
 967                 return;
 968         }
 969
 970         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 971                 return;
 972
 973         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 974                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 975
 976                 /*
 977                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 978                  * checksum errors.
 979                  */
 980                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 981                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 982                         return;
 983
 984                 adapter->hw_csum_rx_error++;
 985                 return;
 986         }
 987
 988         /* It must be a TCP or UDP packet with a valid checksum */
 989         skb->ip_summed = CHECKSUM_UNNECESSARY;
 990 }
 991
 992 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
 993 {
 994         /*
 995          * Force memory writes to complete before letting h/w
 996          * know there are new descriptors to fetch.  (Only
 997          * applicable for weak-ordered memory model archs,
 998          * such as IA-64).
 999          */
1000         wmb();
1001         writel(val, rx_ring->tail);
1002 }
1003
1004 /**
1005  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1006  * @rx_ring: ring to place buffers on
1007  * @cleaned_count: number of buffers to replace
1008  **/
1009 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1010 {
1011         union ixgbe_adv_rx_desc *rx_desc;
1012         struct ixgbe_rx_buffer *bi;
1013         struct sk_buff *skb;
1014         u16 i = rx_ring->next_to_use;
1015
1016         /* do nothing if no valid netdev defined */
1017         if (!rx_ring->netdev)
1018                 return;
1019
1020         while (cleaned_count--) {
1021                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1022                 bi = &rx_ring->rx_buffer_info[i];
1023                 skb = bi->skb;
1024
1025                 if (!skb) {
1026                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1027                                                         rx_ring->rx_buf_len);
1028                         if (!skb) {
1029                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1030                                 goto no_buffers;
1031                         }
1032                         /* initialize queue mapping */
1033                         skb_record_rx_queue(skb, rx_ring->queue_index);
1034                         bi->skb = skb;
1035                 }
1036
1037                 if (!bi->dma) {
1038                         bi->dma = dma_map_single(rx_ring->dev,
1039                                                  skb->data,
1040                                                  rx_ring->rx_buf_len,
1041                                                  DMA_FROM_DEVICE);
1042                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1043                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1044                                 bi->dma = 0;
1045                                 goto no_buffers;
1046                         }
1047                 }
1048
1049                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1050                         if (!bi->page) {
1051                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1052                                 if (!bi->page) {
1053                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1054                                         goto no_buffers;
1055                                 }
1056                         }
1057
1058                         if (!bi->page_dma) {
1059                                 /* use a half page if we're re-using */
1060                                 bi->page_offset ^= PAGE_SIZE / 2;
1061                                 bi->page_dma = dma_map_page(rx_ring->dev,
1062                                                             bi->page,
1063                                                             bi->page_offset,
1064                                                             PAGE_SIZE / 2,
1065                                                             DMA_FROM_DEVICE);
1066                                 if (dma_mapping_error(rx_ring->dev,
1067                                                       bi->page_dma)) {
1068                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1069                                         bi->page_dma = 0;
1070                                         goto no_buffers;
1071                                 }
1072                         }
1073
1074                         /* Refresh the desc even if buffer_addrs didn't change
1075                          * because each write-back erases this info. */
1076                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1077                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1078                 } else {
1079                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1080                         rx_desc->read.hdr_addr = 0;
1081                 }
1082
1083                 i++;
1084                 if (i == rx_ring->count)
1085                         i = 0;
1086         }
1087
1088 no_buffers:
1089         if (rx_ring->next_to_use != i) {
1090                 rx_ring->next_to_use = i;
1091                 ixgbe_release_rx_desc(rx_ring, i);
1092         }
1093 }
1094
1095 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1096 {
1097         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1098 }
1099
1100 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1101 {
1102         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1103 }
1104
1105 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1106 {
1107         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1108                 IXGBE_RXDADV_RSCCNT_MASK) >>
1109                 IXGBE_RXDADV_RSCCNT_SHIFT;
1110 }
1111
1112 /**
1113  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1114  * @skb: pointer to the last skb in the rsc queue
1115  * @count: pointer to number of packets coalesced in this context
1116  *
1117  * This function changes a queue full of hw rsc buffers into a completed
1118  * packet.  It uses the ->prev pointers to find the first packet and then
1119  * turns it into the frag list owner.
1120  **/
1121 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1122                                                         u64 *count)
1123 {
1124         unsigned int frag_list_size = 0;
1125
1126         while (skb->prev) {
1127                 struct sk_buff *prev = skb->prev;
1128                 frag_list_size += skb->len;
1129                 skb->prev = NULL;
1130                 skb = prev;
1131                 *count += 1;
1132         }
1133
1134         skb_shinfo(skb)->frag_list = skb->next;
1135         skb->next = NULL;
1136         skb->len += frag_list_size;
1137         skb->data_len += frag_list_size;
1138         skb->truesize += frag_list_size;
1139         return skb;
1140 }
1141
1142 struct ixgbe_rsc_cb {
1143         dma_addr_t dma;
1144         bool delay_unmap;
1145 };
1146
1147 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1148
1149 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1150                                struct ixgbe_ring *rx_ring,
1151                                int *work_done, int work_to_do)
1152 {
1153         struct ixgbe_adapter *adapter = q_vector->adapter;
1154         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1155         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1156         struct sk_buff *skb;
1157         unsigned int i, rsc_count = 0;
1158         u32 len, staterr;
1159         u16 hdr_info;
1160         bool cleaned = false;
1161         int cleaned_count = 0;
1162         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1163 #ifdef IXGBE_FCOE
1164         int ddp_bytes = 0;
1165 #endif /* IXGBE_FCOE */
1166
1167         i = rx_ring->next_to_clean;
1168         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1169         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1170         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1171
1172         while (staterr & IXGBE_RXD_STAT_DD) {
1173                 u32 upper_len = 0;
1174                 if (*work_done >= work_to_do)
1175                         break;
1176                 (*work_done)++;
1177
1178                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1179                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1180                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1181                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1182                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1183                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1184                         if ((len > IXGBE_RX_HDR_SIZE) ||
1185                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1186                                 len = IXGBE_RX_HDR_SIZE;
1187                 } else {
1188                         len = le16_to_cpu(rx_desc->wb.upper.length);
1189                 }
1190
1191                 cleaned = true;
1192                 skb = rx_buffer_info->skb;
1193                 prefetch(skb->data);
1194                 rx_buffer_info->skb = NULL;
1195
1196                 if (rx_buffer_info->dma) {
1197                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1198                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1199                                  (!(skb->prev))) {
1200                                 /*
1201                                  * When HWRSC is enabled, delay unmapping
1202                                  * of the first packet. It carries the
1203                                  * header information, HW may still
1204                                  * access the header after the writeback.
1205                                  * Only unmap it when EOP is reached
1206                                  */
1207                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1208                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1209                         } else {
1210                                 dma_unmap_single(rx_ring->dev,
1211                                                  rx_buffer_info->dma,
1212                                                  rx_ring->rx_buf_len,
1213                                                  DMA_FROM_DEVICE);
1214                         }
1215                         rx_buffer_info->dma = 0;
1216                         skb_put(skb, len);
1217                 }
1218
1219                 if (upper_len) {
1220                         dma_unmap_page(rx_ring->dev,
1221                                        rx_buffer_info->page_dma,
1222                                        PAGE_SIZE / 2,
1223                                        DMA_FROM_DEVICE);
1224                         rx_buffer_info->page_dma = 0;
1225                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1226                                            rx_buffer_info->page,
1227                                            rx_buffer_info->page_offset,
1228                                            upper_len);
1229
1230                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1231                             (page_count(rx_buffer_info->page) != 1))
1232                                 rx_buffer_info->page = NULL;
1233                         else
1234                                 get_page(rx_buffer_info->page);
1235
1236                         skb->len += upper_len;
1237                         skb->data_len += upper_len;
1238                         skb->truesize += upper_len;
1239                 }
1240
1241                 i++;
1242                 if (i == rx_ring->count)
1243                         i = 0;
1244
1245                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1246                 prefetch(next_rxd);
1247                 cleaned_count++;
1248
1249                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1250                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1251
1252                 if (rsc_count) {
1253                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1254                                      IXGBE_RXDADV_NEXTP_SHIFT;
1255                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1256                 } else {
1257                         next_buffer = &rx_ring->rx_buffer_info[i];
1258                 }
1259
1260                 if (staterr & IXGBE_RXD_STAT_EOP) {
1261                         if (skb->prev)
1262                                 skb = ixgbe_transform_rsc_queue(skb,
1263                                                 &(rx_ring->rx_stats.rsc_count));
1264                         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1265                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1266                                         dma_unmap_single(rx_ring->dev,
1267                                                          IXGBE_RSC_CB(skb)->dma,
1268                                                          rx_ring->rx_buf_len,
1269                                                          DMA_FROM_DEVICE);
1270                                         IXGBE_RSC_CB(skb)->dma = 0;
1271                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1272                                 }
1273                                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1274                                         rx_ring->rx_stats.rsc_count +=
1275                                                  skb_shinfo(skb)->nr_frags;
1276                                 else
1277                                         rx_ring->rx_stats.rsc_count++;
1278                                 rx_ring->rx_stats.rsc_flush++;
1279                         }
1280                         u64_stats_update_begin(&rx_ring->syncp);
1281                         rx_ring->stats.packets++;
1282                         rx_ring->stats.bytes += skb->len;
1283                         u64_stats_update_end(&rx_ring->syncp);
1284                 } else {
1285                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1286                                 rx_buffer_info->skb = next_buffer->skb;
1287                                 rx_buffer_info->dma = next_buffer->dma;
1288                                 next_buffer->skb = skb;
1289                                 next_buffer->dma = 0;
1290                         } else {
1291                                 skb->next = next_buffer->skb;
1292                                 skb->next->prev = skb;
1293                         }
1294                         rx_ring->rx_stats.non_eop_descs++;
1295                         goto next_desc;
1296                 }
1297
1298                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1299                         dev_kfree_skb_irq(skb);
1300                         goto next_desc;
1301                 }
1302
1303                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1304
1305                 /* probably a little skewed due to removing CRC */
1306                 total_rx_bytes += skb->len;
1307                 total_rx_packets++;
1308
1309                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1310 #ifdef IXGBE_FCOE
1311                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1312                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1313                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1314                         if (!ddp_bytes)
1315                                 goto next_desc;
1316                 }
1317 #endif /* IXGBE_FCOE */
1318                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1319
1320 next_desc:
1321                 rx_desc->wb.upper.status_error = 0;
1322
1323                 /* return some buffers to hardware, one at a time is too slow */
1324                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1325                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1326                         cleaned_count = 0;
1327                 }
1328
1329                 /* use prefetched values */
1330                 rx_desc = next_rxd;
1331                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1332
1333                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1334         }
1335
1336         rx_ring->next_to_clean = i;
1337         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1338
1339         if (cleaned_count)
1340                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1341
1342 #ifdef IXGBE_FCOE
1343         /* include DDPed FCoE data */
1344         if (ddp_bytes > 0) {
1345                 unsigned int mss;
1346
1347                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1348                         sizeof(struct fc_frame_header) -
1349                         sizeof(struct fcoe_crc_eof);
1350                 if (mss > 512)
1351                         mss &= ~511;
1352                 total_rx_bytes += ddp_bytes;
1353                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1354         }
1355 #endif /* IXGBE_FCOE */
1356
1357         rx_ring->total_packets += total_rx_packets;
1358         rx_ring->total_bytes += total_rx_bytes;
1359
1360         return cleaned;
1361 }
1362
1363 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1364 /**
1365  * ixgbe_configure_msix - Configure MSI-X hardware
1366  * @adapter: board private structure
1367  *
1368  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1369  * interrupts.
1370  **/
1371 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1372 {
1373         struct ixgbe_q_vector *q_vector;
1374         int i, j, q_vectors, v_idx, r_idx;
1375         u32 mask;
1376
1377         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1378
1379         /*
1380          * Populate the IVAR table and set the ITR values to the
1381          * corresponding register.
1382          */
1383         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1384                 q_vector = adapter->q_vector[v_idx];
1385                 /* XXX for_each_set_bit(...) */
1386                 r_idx = find_first_bit(q_vector->rxr_idx,
1387                                        adapter->num_rx_queues);
1388
1389                 for (i = 0; i < q_vector->rxr_count; i++) {
1390                         j = adapter->rx_ring[r_idx]->reg_idx;
1391                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1392                         r_idx = find_next_bit(q_vector->rxr_idx,
1393                                               adapter->num_rx_queues,
1394                                               r_idx + 1);
1395                 }
1396                 r_idx = find_first_bit(q_vector->txr_idx,
1397                                        adapter->num_tx_queues);
1398
1399                 for (i = 0; i < q_vector->txr_count; i++) {
1400                         j = adapter->tx_ring[r_idx]->reg_idx;
1401                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1402                         r_idx = find_next_bit(q_vector->txr_idx,
1403                                               adapter->num_tx_queues,
1404                                               r_idx + 1);
1405                 }
1406
1407                 if (q_vector->txr_count && !q_vector->rxr_count)
1408                         /* tx only */
1409                         q_vector->eitr = adapter->tx_eitr_param;
1410                 else if (q_vector->rxr_count)
1411                         /* rx or mixed */
1412                         q_vector->eitr = adapter->rx_eitr_param;
1413
1414                 ixgbe_write_eitr(q_vector);
1415                 /* If Flow Director is enabled, set interrupt affinity */
1416                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1417                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1418                         /*
1419                          * Allocate the affinity_hint cpumask, assign the mask
1420                          * for this vector, and set our affinity_hint for
1421                          * this irq.
1422                          */
1423                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1424                                                GFP_KERNEL))
1425                                 return;
1426                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1427                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1428                                               q_vector->affinity_mask);
1429                 }
1430         }
1431
1432         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1433                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1434                                v_idx);
1435         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1436                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1438
1439         /* set up to autoclear timer, and the vectors */
1440         mask = IXGBE_EIMS_ENABLE_MASK;
1441         if (adapter->num_vfs)
1442                 mask &= ~(IXGBE_EIMS_OTHER |
1443                           IXGBE_EIMS_MAILBOX |
1444                           IXGBE_EIMS_LSC);
1445         else
1446                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1447         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1448 }
1449
1450 enum latency_range {
1451         lowest_latency = 0,
1452         low_latency = 1,
1453         bulk_latency = 2,
1454         latency_invalid = 255
1455 };
1456
1457 /**
1458  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1459  * @adapter: pointer to adapter
1460  * @eitr: eitr setting (ints per sec) to give last timeslice
1461  * @itr_setting: current throttle rate in ints/second
1462  * @packets: the number of packets during this measurement interval
1463  * @bytes: the number of bytes during this measurement interval
1464  *
1465  *      Stores a new ITR value based on packets and byte
1466  *      counts during the last interrupt.  The advantage of per interrupt
1467  *      computation is faster updates and more accurate ITR for the current
1468  *      traffic pattern.  Constants in this function were computed
1469  *      based on theoretical maximum wire speed and thresholds were set based
1470  *      on testing data as well as attempting to minimize response time
1471  *      while increasing bulk throughput.
1472  *      this functionality is controlled by the InterruptThrottleRate module
1473  *      parameter (see ixgbe_param.c)
1474  **/
1475 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1476                            u32 eitr, u8 itr_setting,
1477                            int packets, int bytes)
1478 {
1479         unsigned int retval = itr_setting;
1480         u32 timepassed_us;
1481         u64 bytes_perint;
1482
1483         if (packets == 0)
1484                 goto update_itr_done;
1485
1486
1487         /* simple throttlerate management
1488          *    0-20MB/s lowest (100000 ints/s)
1489          *   20-100MB/s low   (20000 ints/s)
1490          *  100-1249MB/s bulk (8000 ints/s)
1491          */
1492         /* what was last interrupt timeslice? */
1493         timepassed_us = 1000000/eitr;
1494         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1495
1496         switch (itr_setting) {
1497         case lowest_latency:
1498                 if (bytes_perint > adapter->eitr_low)
1499                         retval = low_latency;
1500                 break;
1501         case low_latency:
1502                 if (bytes_perint > adapter->eitr_high)
1503                         retval = bulk_latency;
1504                 else if (bytes_perint <= adapter->eitr_low)
1505                         retval = lowest_latency;
1506                 break;
1507         case bulk_latency:
1508                 if (bytes_perint <= adapter->eitr_high)
1509                         retval = low_latency;
1510                 break;
1511         }
1512
1513 update_itr_done:
1514         return retval;
1515 }
1516
1517 /**
1518  * ixgbe_write_eitr - write EITR register in hardware specific way
1519  * @q_vector: structure containing interrupt and ring information
1520  *
1521  * This function is made to be called by ethtool and by the driver
1522  * when it needs to update EITR registers at runtime.  Hardware
1523  * specific quirks/differences are taken care of here.
1524  */
1525 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1526 {
1527         struct ixgbe_adapter *adapter = q_vector->adapter;
1528         struct ixgbe_hw *hw = &adapter->hw;
1529         int v_idx = q_vector->v_idx;
1530         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1531
1532         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1533                 /* must write high and low 16 bits to reset counter */
1534                 itr_reg |= (itr_reg << 16);
1535         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1536                 /*
1537                  * 82599 can support a value of zero, so allow it for
1538                  * max interrupt rate, but there is an errata where it can
1539                  * not be zero with RSC
1540                  */
1541                 if (itr_reg == 8 &&
1542                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1543                         itr_reg = 0;
1544
1545                 /*
1546                  * set the WDIS bit to not clear the timer bits and cause an
1547                  * immediate assertion of the interrupt
1548                  */
1549                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1550         }
1551         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1552 }
1553
1554 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1555 {
1556         struct ixgbe_adapter *adapter = q_vector->adapter;
1557         u32 new_itr;
1558         u8 current_itr, ret_itr;
1559         int i, r_idx;
1560         struct ixgbe_ring *rx_ring, *tx_ring;
1561
1562         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1563         for (i = 0; i < q_vector->txr_count; i++) {
1564                 tx_ring = adapter->tx_ring[r_idx];
1565                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1566                                            q_vector->tx_itr,
1567                                            tx_ring->total_packets,
1568                                            tx_ring->total_bytes);
1569                 /* if the result for this queue would decrease interrupt
1570                  * rate for this vector then use that result */
1571                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1572                                     q_vector->tx_itr - 1 : ret_itr);
1573                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1574                                       r_idx + 1);
1575         }
1576
1577         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1578         for (i = 0; i < q_vector->rxr_count; i++) {
1579                 rx_ring = adapter->rx_ring[r_idx];
1580                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1581                                            q_vector->rx_itr,
1582                                            rx_ring->total_packets,
1583                                            rx_ring->total_bytes);
1584                 /* if the result for this queue would decrease interrupt
1585                  * rate for this vector then use that result */
1586                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1587                                     q_vector->rx_itr - 1 : ret_itr);
1588                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1589                                       r_idx + 1);
1590         }
1591
1592         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1593
1594         switch (current_itr) {
1595         /* counts and packets in update_itr are dependent on these numbers */
1596         case lowest_latency:
1597                 new_itr = 100000;
1598                 break;
1599         case low_latency:
1600                 new_itr = 20000; /* aka hwitr = ~200 */
1601                 break;
1602         case bulk_latency:
1603         default:
1604                 new_itr = 8000;
1605                 break;
1606         }
1607
1608         if (new_itr != q_vector->eitr) {
1609                 /* do an exponential smoothing */
1610                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1611
1612                 /* save the algorithm value here, not the smoothed one */
1613                 q_vector->eitr = new_itr;
1614
1615                 ixgbe_write_eitr(q_vector);
1616         }
1617 }
1618
1619 /**
1620  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1621  * @work: pointer to work_struct containing our data
1622  **/
1623 static void ixgbe_check_overtemp_task(struct work_struct *work)
1624 {
1625         struct ixgbe_adapter *adapter = container_of(work,
1626                                                      struct ixgbe_adapter,
1627                                                      check_overtemp_task);
1628         struct ixgbe_hw *hw = &adapter->hw;
1629         u32 eicr = adapter->interrupt_event;
1630
1631         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1632                 return;
1633
1634         switch (hw->device_id) {
1635         case IXGBE_DEV_ID_82599_T3_LOM: {
1636                 u32 autoneg;
1637                 bool link_up = false;
1638
1639                 if (hw->mac.ops.check_link)
1640                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1641
1642                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1643                     (eicr & IXGBE_EICR_LSC))
1644                         /* Check if this is due to overtemp */
1645                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1646                                 break;
1647                 return;
1648         }
1649         default:
1650                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1651                         return;
1652                 break;
1653         }
1654         e_crit(drv,
1655                "Network adapter has been stopped because it has over heated. "
1656                "Restart the computer. If the problem persists, "
1657                "power off the system and replace the adapter\n");
1658         /* write to clear the interrupt */
1659         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1660 }
1661
1662 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1663 {
1664         struct ixgbe_hw *hw = &adapter->hw;
1665
1666         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1667             (eicr & IXGBE_EICR_GPI_SDP1)) {
1668                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1669                 /* write to clear the interrupt */
1670                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1671         }
1672 }
1673
1674 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1675 {
1676         struct ixgbe_hw *hw = &adapter->hw;
1677
1678         if (eicr & IXGBE_EICR_GPI_SDP1) {
1679                 /* Clear the interrupt */
1680                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1681                 schedule_work(&adapter->multispeed_fiber_task);
1682         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1683                 /* Clear the interrupt */
1684                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1685                 schedule_work(&adapter->sfp_config_module_task);
1686         } else {
1687                 /* Interrupt isn't for us... */
1688                 return;
1689         }
1690 }
1691
1692 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1693 {
1694         struct ixgbe_hw *hw = &adapter->hw;
1695
1696         adapter->lsc_int++;
1697         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1698         adapter->link_check_timeout = jiffies;
1699         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1700                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1701                 IXGBE_WRITE_FLUSH(hw);
1702                 schedule_work(&adapter->watchdog_task);
1703         }
1704 }
1705
1706 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1707 {
1708         struct net_device *netdev = data;
1709         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1710         struct ixgbe_hw *hw = &adapter->hw;
1711         u32 eicr;
1712
1713         /*
1714          * Workaround for Silicon errata.  Use clear-by-write instead
1715          * of clear-by-read.  Reading with EICS will return the
1716          * interrupt causes without clearing, which later be done
1717          * with the write to EICR.
1718          */
1719         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1720         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1721
1722         if (eicr & IXGBE_EICR_LSC)
1723                 ixgbe_check_lsc(adapter);
1724
1725         if (eicr & IXGBE_EICR_MAILBOX)
1726                 ixgbe_msg_task(adapter);
1727
1728         if (hw->mac.type == ixgbe_mac_82598EB)
1729                 ixgbe_check_fan_failure(adapter, eicr);
1730
1731         if (hw->mac.type == ixgbe_mac_82599EB) {
1732                 ixgbe_check_sfp_event(adapter, eicr);
1733                 adapter->interrupt_event = eicr;
1734                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1735                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1736                         schedule_work(&adapter->check_overtemp_task);
1737
1738                 /* Handle Flow Director Full threshold interrupt */
1739                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1740                         int i;
1741                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1742                         /* Disable transmits before FDIR Re-initialization */
1743                         netif_tx_stop_all_queues(netdev);
1744                         for (i = 0; i < adapter->num_tx_queues; i++) {
1745                                 struct ixgbe_ring *tx_ring =
1746                                                             adapter->tx_ring[i];
1747                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1748                                                        &tx_ring->reinit_state))
1749                                         schedule_work(&adapter->fdir_reinit_task);
1750                         }
1751                 }
1752         }
1753         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1754                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1755
1756         return IRQ_HANDLED;
1757 }
1758
1759 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1760                                            u64 qmask)
1761 {
1762         u32 mask;
1763
1764         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1765                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1766                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1767         } else {
1768                 mask = (qmask & 0xFFFFFFFF);
1769                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1770                 mask = (qmask >> 32);
1771                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1772         }
1773         /* skip the flush */
1774 }
1775
1776 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1777                                             u64 qmask)
1778 {
1779         u32 mask;
1780
1781         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1782                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1783                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1784         } else {
1785                 mask = (qmask & 0xFFFFFFFF);
1786                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1787                 mask = (qmask >> 32);
1788                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1789         }
1790         /* skip the flush */
1791 }
1792
1793 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1794 {
1795         struct ixgbe_q_vector *q_vector = data;
1796         struct ixgbe_adapter  *adapter = q_vector->adapter;
1797         struct ixgbe_ring     *tx_ring;
1798         int i, r_idx;
1799
1800         if (!q_vector->txr_count)
1801                 return IRQ_HANDLED;
1802
1803         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1804         for (i = 0; i < q_vector->txr_count; i++) {
1805                 tx_ring = adapter->tx_ring[r_idx];
1806                 tx_ring->total_bytes = 0;
1807                 tx_ring->total_packets = 0;
1808                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1809                                       r_idx + 1);
1810         }
1811
1812         /* EIAM disabled interrupts (on this vector) for us */
1813         napi_schedule(&q_vector->napi);
1814
1815         return IRQ_HANDLED;
1816 }
1817
1818 /**
1819  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1820  * @irq: unused
1821  * @data: pointer to our q_vector struct for this interrupt vector
1822  **/
1823 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1824 {
1825         struct ixgbe_q_vector *q_vector = data;
1826         struct ixgbe_adapter  *adapter = q_vector->adapter;
1827         struct ixgbe_ring  *rx_ring;
1828         int r_idx;
1829         int i;
1830
1831         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1832         for (i = 0;  i < q_vector->rxr_count; i++) {
1833                 rx_ring = adapter->rx_ring[r_idx];
1834                 rx_ring->total_bytes = 0;
1835                 rx_ring->total_packets = 0;
1836                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1837                                       r_idx + 1);
1838         }
1839
1840         if (!q_vector->rxr_count)
1841                 return IRQ_HANDLED;
1842
1843         /* disable interrupts on this vector only */
1844         /* EIAM disabled interrupts (on this vector) for us */
1845         napi_schedule(&q_vector->napi);
1846
1847         return IRQ_HANDLED;
1848 }
1849
1850 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1851 {
1852         struct ixgbe_q_vector *q_vector = data;
1853         struct ixgbe_adapter  *adapter = q_vector->adapter;
1854         struct ixgbe_ring  *ring;
1855         int r_idx;
1856         int i;
1857
1858         if (!q_vector->txr_count && !q_vector->rxr_count)
1859                 return IRQ_HANDLED;
1860
1861         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1862         for (i = 0; i < q_vector->txr_count; i++) {
1863                 ring = adapter->tx_ring[r_idx];
1864                 ring->total_bytes = 0;
1865                 ring->total_packets = 0;
1866                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1867                                       r_idx + 1);
1868         }
1869
1870         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1871         for (i = 0; i < q_vector->rxr_count; i++) {
1872                 ring = adapter->rx_ring[r_idx];
1873                 ring->total_bytes = 0;
1874                 ring->total_packets = 0;
1875                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1876                                       r_idx + 1);
1877         }
1878
1879         /* EIAM disabled interrupts (on this vector) for us */
1880         napi_schedule(&q_vector->napi);
1881
1882         return IRQ_HANDLED;
1883 }
1884
1885 /**
1886  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1887  * @napi: napi struct with our devices info in it
1888  * @budget: amount of work driver is allowed to do this pass, in packets
1889  *
1890  * This function is optimized for cleaning one queue only on a single
1891  * q_vector!!!
1892  **/
1893 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1894 {
1895         struct ixgbe_q_vector *q_vector =
1896                                container_of(napi, struct ixgbe_q_vector, napi);
1897         struct ixgbe_adapter *adapter = q_vector->adapter;
1898         struct ixgbe_ring *rx_ring = NULL;
1899         int work_done = 0;
1900         long r_idx;
1901
1902         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1903         rx_ring = adapter->rx_ring[r_idx];
1904 #ifdef CONFIG_IXGBE_DCA
1905         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1906                 ixgbe_update_rx_dca(adapter, rx_ring);
1907 #endif
1908
1909         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1910
1911         /* If all Rx work done, exit the polling mode */
1912         if (work_done < budget) {
1913                 napi_complete(napi);
1914                 if (adapter->rx_itr_setting & 1)
1915                         ixgbe_set_itr_msix(q_vector);
1916                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1917                         ixgbe_irq_enable_queues(adapter,
1918                                                 ((u64)1 << q_vector->v_idx));
1919         }
1920
1921         return work_done;
1922 }
1923
1924 /**
1925  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1926  * @napi: napi struct with our devices info in it
1927  * @budget: amount of work driver is allowed to do this pass, in packets
1928  *
1929  * This function will clean more than one rx queue associated with a
1930  * q_vector.
1931  **/
1932 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1933 {
1934         struct ixgbe_q_vector *q_vector =
1935                                container_of(napi, struct ixgbe_q_vector, napi);
1936         struct ixgbe_adapter *adapter = q_vector->adapter;
1937         struct ixgbe_ring *ring = NULL;
1938         int work_done = 0, i;
1939         long r_idx;
1940         bool tx_clean_complete = true;
1941
1942         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1943         for (i = 0; i < q_vector->txr_count; i++) {
1944                 ring = adapter->tx_ring[r_idx];
1945 #ifdef CONFIG_IXGBE_DCA
1946                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1947                         ixgbe_update_tx_dca(adapter, ring);
1948 #endif
1949                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1950                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1951                                       r_idx + 1);
1952         }
1953
1954         /* attempt to distribute budget to each queue fairly, but don't allow
1955          * the budget to go below 1 because we'll exit polling */
1956         budget /= (q_vector->rxr_count ?: 1);
1957         budget = max(budget, 1);
1958         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1959         for (i = 0; i < q_vector->rxr_count; i++) {
1960                 ring = adapter->rx_ring[r_idx];
1961 #ifdef CONFIG_IXGBE_DCA
1962                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1963                         ixgbe_update_rx_dca(adapter, ring);
1964 #endif
1965                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1966                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1967                                       r_idx + 1);
1968         }
1969
1970         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1971         ring = adapter->rx_ring[r_idx];
1972         /* If all Rx work done, exit the polling mode */
1973         if (work_done < budget) {
1974                 napi_complete(napi);
1975                 if (adapter->rx_itr_setting & 1)
1976                         ixgbe_set_itr_msix(q_vector);
1977                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1978                         ixgbe_irq_enable_queues(adapter,
1979                                                 ((u64)1 << q_vector->v_idx));
1980                 return 0;
1981         }
1982
1983         return work_done;
1984 }
1985
1986 /**
1987  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1988  * @napi: napi struct with our devices info in it
1989  * @budget: amount of work driver is allowed to do this pass, in packets
1990  *
1991  * This function is optimized for cleaning one queue only on a single
1992  * q_vector!!!
1993  **/
1994 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1995 {
1996         struct ixgbe_q_vector *q_vector =
1997                                container_of(napi, struct ixgbe_q_vector, napi);
1998         struct ixgbe_adapter *adapter = q_vector->adapter;
1999         struct ixgbe_ring *tx_ring = NULL;
2000         int work_done = 0;
2001         long r_idx;
2002
2003         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2004         tx_ring = adapter->tx_ring[r_idx];
2005 #ifdef CONFIG_IXGBE_DCA
2006         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2007                 ixgbe_update_tx_dca(adapter, tx_ring);
2008 #endif
2009
2010         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2011                 work_done = budget;
2012
2013         /* If all Tx work done, exit the polling mode */
2014         if (work_done < budget) {
2015                 napi_complete(napi);
2016                 if (adapter->tx_itr_setting & 1)
2017                         ixgbe_set_itr_msix(q_vector);
2018                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2019                         ixgbe_irq_enable_queues(adapter,
2020                                                 ((u64)1 << q_vector->v_idx));
2021         }
2022
2023         return work_done;
2024 }
2025
2026 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2027                                      int r_idx)
2028 {
2029         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2030
2031         set_bit(r_idx, q_vector->rxr_idx);
2032         q_vector->rxr_count++;
2033 }
2034
2035 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2036                                      int t_idx)
2037 {
2038         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2039
2040         set_bit(t_idx, q_vector->txr_idx);
2041         q_vector->txr_count++;
2042 }
2043
2044 /**
2045  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2046  * @adapter: board private structure to initialize
2047  * @vectors: allotted vector count for descriptor rings
2048  *
2049  * This function maps descriptor rings to the queue-specific vectors
2050  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2051  * one vector per ring/queue, but on a constrained vector budget, we
2052  * group the rings as "efficiently" as possible.  You would add new
2053  * mapping configurations in here.
2054  **/
2055 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2056                                       int vectors)
2057 {
2058         int v_start = 0;
2059         int rxr_idx = 0, txr_idx = 0;
2060         int rxr_remaining = adapter->num_rx_queues;
2061         int txr_remaining = adapter->num_tx_queues;
2062         int i, j;
2063         int rqpv, tqpv;
2064         int err = 0;
2065
2066         /* No mapping required if MSI-X is disabled. */
2067         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2068                 goto out;
2069
2070         /*
2071          * The ideal configuration...
2072          * We have enough vectors to map one per queue.
2073          */
2074         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2075                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2076                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2077
2078                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2079                         map_vector_to_txq(adapter, v_start, txr_idx);
2080
2081                 goto out;
2082         }
2083
2084         /*
2085          * If we don't have enough vectors for a 1-to-1
2086          * mapping, we'll have to group them so there are
2087          * multiple queues per vector.
2088          */
2089         /* Re-adjusting *qpv takes care of the remainder. */
2090         for (i = v_start; i < vectors; i++) {
2091                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2092                 for (j = 0; j < rqpv; j++) {
2093                         map_vector_to_rxq(adapter, i, rxr_idx);
2094                         rxr_idx++;
2095                         rxr_remaining--;
2096                 }
2097         }
2098         for (i = v_start; i < vectors; i++) {
2099                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2100                 for (j = 0; j < tqpv; j++) {
2101                         map_vector_to_txq(adapter, i, txr_idx);
2102                         txr_idx++;
2103                         txr_remaining--;
2104                 }
2105         }
2106
2107 out:
2108         return err;
2109 }
2110
2111 /**
2112  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2113  * @adapter: board private structure
2114  *
2115  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2116  * interrupts from the kernel.
2117  **/
2118 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2119 {
2120         struct net_device *netdev = adapter->netdev;
2121         irqreturn_t (*handler)(int, void *);
2122         int i, vector, q_vectors, err;
2123         int ri = 0, ti = 0;
2124
2125         /* Decrement for Other and TCP Timer vectors */
2126         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2127
2128         /* Map the Tx/Rx rings to the vectors we were allotted. */
2129         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2130         if (err)
2131                 goto out;
2132
2133 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2134                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2135                          &ixgbe_msix_clean_many)
2136         for (vector = 0; vector < q_vectors; vector++) {
2137                 handler = SET_HANDLER(adapter->q_vector[vector]);
2138
2139                 if (handler == &ixgbe_msix_clean_rx) {
2140                         sprintf(adapter->name[vector], "%s-%s-%d",
2141                                 netdev->name, "rx", ri++);
2142                 } else if (handler == &ixgbe_msix_clean_tx) {
2143                         sprintf(adapter->name[vector], "%s-%s-%d",
2144                                 netdev->name, "tx", ti++);
2145                 } else
2146                         sprintf(adapter->name[vector], "%s-%s-%d",
2147                                 netdev->name, "TxRx", vector);
2148
2149                 err = request_irq(adapter->msix_entries[vector].vector,
2150                                   handler, 0, adapter->name[vector],
2151                                   adapter->q_vector[vector]);
2152                 if (err) {
2153                         e_err(probe, "request_irq failed for MSIX interrupt "
2154                               "Error: %d\n", err);
2155                         goto free_queue_irqs;
2156                 }
2157         }
2158
2159         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2160         err = request_irq(adapter->msix_entries[vector].vector,
2161                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2162         if (err) {
2163                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2164                 goto free_queue_irqs;
2165         }
2166
2167         return 0;
2168
2169 free_queue_irqs:
2170         for (i = vector - 1; i >= 0; i--)
2171                 free_irq(adapter->msix_entries[--vector].vector,
2172                          adapter->q_vector[i]);
2173         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2174         pci_disable_msix(adapter->pdev);
2175         kfree(adapter->msix_entries);
2176         adapter->msix_entries = NULL;
2177 out:
2178         return err;
2179 }
2180
2181 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2182 {
2183         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2184         u8 current_itr;
2185         u32 new_itr = q_vector->eitr;
2186         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2187         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2188
2189         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2190                                             q_vector->tx_itr,
2191                                             tx_ring->total_packets,
2192                                             tx_ring->total_bytes);
2193         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2194                                             q_vector->rx_itr,
2195                                             rx_ring->total_packets,
2196                                             rx_ring->total_bytes);
2197
2198         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2199
2200         switch (current_itr) {
2201         /* counts and packets in update_itr are dependent on these numbers */
2202         case lowest_latency:
2203                 new_itr = 100000;
2204                 break;
2205         case low_latency:
2206                 new_itr = 20000; /* aka hwitr = ~200 */
2207                 break;
2208         case bulk_latency:
2209                 new_itr = 8000;
2210                 break;
2211         default:
2212                 break;
2213         }
2214
2215         if (new_itr != q_vector->eitr) {
2216                 /* do an exponential smoothing */
2217                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2218
2219                 /* save the algorithm value here, not the smoothed one */
2220                 q_vector->eitr = new_itr;
2221
2222                 ixgbe_write_eitr(q_vector);
2223         }
2224 }
2225
2226 /**
2227  * ixgbe_irq_enable - Enable default interrupt generation settings
2228  * @adapter: board private structure
2229  **/
2230 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2231                                     bool flush)
2232 {
2233         u32 mask;
2234
2235         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2236         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2237                 mask |= IXGBE_EIMS_GPI_SDP0;
2238         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2239                 mask |= IXGBE_EIMS_GPI_SDP1;
2240         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2241                 mask |= IXGBE_EIMS_ECC;
2242                 mask |= IXGBE_EIMS_GPI_SDP1;
2243                 mask |= IXGBE_EIMS_GPI_SDP2;
2244                 if (adapter->num_vfs)
2245                         mask |= IXGBE_EIMS_MAILBOX;
2246         }
2247         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2248             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2249                 mask |= IXGBE_EIMS_FLOW_DIR;
2250
2251         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2252         if (queues)
2253                 ixgbe_irq_enable_queues(adapter, ~0);
2254         if (flush)
2255                 IXGBE_WRITE_FLUSH(&adapter->hw);
2256
2257         if (adapter->num_vfs > 32) {
2258                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2259                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2260         }
2261 }
2262
2263 /**
2264  * ixgbe_intr - legacy mode Interrupt Handler
2265  * @irq: interrupt number
2266  * @data: pointer to a network interface device structure
2267  **/
2268 static irqreturn_t ixgbe_intr(int irq, void *data)
2269 {
2270         struct net_device *netdev = data;
2271         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2272         struct ixgbe_hw *hw = &adapter->hw;
2273         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2274         u32 eicr;
2275
2276         /*
2277          * Workaround for silicon errata on 82598.  Mask the interrupts
2278          * before the read of EICR.
2279          */
2280         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2281
2282         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2283          * therefore no explict interrupt disable is necessary */
2284         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2285         if (!eicr) {
2286                 /*
2287                  * shared interrupt alert!
2288                  * make sure interrupts are enabled because the read will
2289                  * have disabled interrupts due to EIAM
2290                  * finish the workaround of silicon errata on 82598.  Unmask
2291                  * the interrupt that we masked before the EICR read.
2292                  */
2293                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2294                         ixgbe_irq_enable(adapter, true, true);
2295                 return IRQ_NONE;        /* Not our interrupt */
2296         }
2297
2298         if (eicr & IXGBE_EICR_LSC)
2299                 ixgbe_check_lsc(adapter);
2300
2301         if (hw->mac.type == ixgbe_mac_82599EB)
2302                 ixgbe_check_sfp_event(adapter, eicr);
2303
2304         ixgbe_check_fan_failure(adapter, eicr);
2305         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2306             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2307                 schedule_work(&adapter->check_overtemp_task);
2308
2309         if (napi_schedule_prep(&(q_vector->napi))) {
2310                 adapter->tx_ring[0]->total_packets = 0;
2311                 adapter->tx_ring[0]->total_bytes = 0;
2312                 adapter->rx_ring[0]->total_packets = 0;
2313                 adapter->rx_ring[0]->total_bytes = 0;
2314                 /* would disable interrupts here but EIAM disabled it */
2315                 __napi_schedule(&(q_vector->napi));
2316         }
2317
2318         /*
2319          * re-enable link(maybe) and non-queue interrupts, no flush.
2320          * ixgbe_poll will re-enable the queue interrupts
2321          */
2322
2323         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2324                 ixgbe_irq_enable(adapter, false, false);
2325
2326         return IRQ_HANDLED;
2327 }
2328
2329 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2330 {
2331         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2332
2333         for (i = 0; i < q_vectors; i++) {
2334                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2335                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2336                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2337                 q_vector->rxr_count = 0;
2338                 q_vector->txr_count = 0;
2339         }
2340 }
2341
2342 /**
2343  * ixgbe_request_irq - initialize interrupts
2344  * @adapter: board private structure
2345  *
2346  * Attempts to configure interrupts using the best available
2347  * capabilities of the hardware and kernel.
2348  **/
2349 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2350 {
2351         struct net_device *netdev = adapter->netdev;
2352         int err;
2353
2354         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2355                 err = ixgbe_request_msix_irqs(adapter);
2356         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2357                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2358                                   netdev->name, netdev);
2359         } else {
2360                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2361                                   netdev->name, netdev);
2362         }
2363
2364         if (err)
2365                 e_err(probe, "request_irq failed, Error %d\n", err);
2366
2367         return err;
2368 }
2369
2370 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2371 {
2372         struct net_device *netdev = adapter->netdev;
2373
2374         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2375                 int i, q_vectors;
2376
2377                 q_vectors = adapter->num_msix_vectors;
2378
2379                 i = q_vectors - 1;
2380                 free_irq(adapter->msix_entries[i].vector, netdev);
2381
2382                 i--;
2383                 for (; i >= 0; i--) {
2384                         free_irq(adapter->msix_entries[i].vector,
2385                                  adapter->q_vector[i]);
2386                 }
2387
2388                 ixgbe_reset_q_vectors(adapter);
2389         } else {
2390                 free_irq(adapter->pdev->irq, netdev);
2391         }
2392 }
2393
2394 /**
2395  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2396  * @adapter: board private structure
2397  **/
2398 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2399 {
2400         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2401                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2402         } else {
2403                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2404                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2405                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2406                 if (adapter->num_vfs > 32)
2407                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2408         }
2409         IXGBE_WRITE_FLUSH(&adapter->hw);
2410         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2411                 int i;
2412                 for (i = 0; i < adapter->num_msix_vectors; i++)
2413                         synchronize_irq(adapter->msix_entries[i].vector);
2414         } else {
2415                 synchronize_irq(adapter->pdev->irq);
2416         }
2417 }
2418
2419 /**
2420  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2421  *
2422  **/
2423 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2424 {
2425         struct ixgbe_hw *hw = &adapter->hw;
2426
2427         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2428                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2429
2430         ixgbe_set_ivar(adapter, 0, 0, 0);
2431         ixgbe_set_ivar(adapter, 1, 0, 0);
2432
2433         map_vector_to_rxq(adapter, 0, 0);
2434         map_vector_to_txq(adapter, 0, 0);
2435
2436         e_info(hw, "Legacy interrupt IVAR setup done\n");
2437 }
2438
2439 /**
2440  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2441  * @adapter: board private structure
2442  * @ring: structure containing ring specific data
2443  *
2444  * Configure the Tx descriptor ring after a reset.
2445  **/
2446 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2447                              struct ixgbe_ring *ring)
2448 {
2449         struct ixgbe_hw *hw = &adapter->hw;
2450         u64 tdba = ring->dma;
2451         int wait_loop = 10;
2452         u32 txdctl;
2453         u16 reg_idx = ring->reg_idx;
2454
2455         /* disable queue to avoid issues while updating state */
2456         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2457         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2458                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2459         IXGBE_WRITE_FLUSH(hw);
2460
2461         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2462                         (tdba & DMA_BIT_MASK(32)));
2463         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2464         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2465                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2466         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2467         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2468         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2469
2470         /* configure fetching thresholds */
2471         if (adapter->rx_itr_setting == 0) {
2472                 /* cannot set wthresh when itr==0 */
2473                 txdctl &= ~0x007F0000;
2474         } else {
2475                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2476                 txdctl |= (8 << 16);
2477         }
2478         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2479                 /* PThresh workaround for Tx hang with DFP enabled. */
2480                 txdctl |= 32;
2481         }
2482
2483         /* reinitialize flowdirector state */
2484         set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2485
2486         /* enable queue */
2487         txdctl |= IXGBE_TXDCTL_ENABLE;
2488         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2489
2490         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2491         if (hw->mac.type == ixgbe_mac_82598EB &&
2492             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2493                 return;
2494
2495         /* poll to verify queue is enabled */
2496         do {
2497                 msleep(1);
2498                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2499         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2500         if (!wait_loop)
2501                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2502 }
2503
2504 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2505 {
2506         struct ixgbe_hw *hw = &adapter->hw;
2507         u32 rttdcs;
2508         u32 mask;
2509
2510         if (hw->mac.type == ixgbe_mac_82598EB)
2511                 return;
2512
2513         /* disable the arbiter while setting MTQC */
2514         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2515         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2516         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2517
2518         /* set transmit pool layout */
2519         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2520         switch (adapter->flags & mask) {
2521
2522         case (IXGBE_FLAG_SRIOV_ENABLED):
2523                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2524                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2525                 break;
2526
2527         case (IXGBE_FLAG_DCB_ENABLED):
2528                 /* We enable 8 traffic classes, DCB only */
2529                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2530                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2531                 break;
2532
2533         default:
2534                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2535                 break;
2536         }
2537
2538         /* re-enable the arbiter */
2539         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2540         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2541 }
2542
2543 /**
2544  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2545  * @adapter: board private structure
2546  *
2547  * Configure the Tx unit of the MAC after a reset.
2548  **/
2549 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2550 {
2551         struct ixgbe_hw *hw = &adapter->hw;
2552         u32 dmatxctl;
2553         u32 i;
2554
2555         ixgbe_setup_mtqc(adapter);
2556
2557         if (hw->mac.type != ixgbe_mac_82598EB) {
2558                 /* DMATXCTL.EN must be before Tx queues are enabled */
2559                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2560                 dmatxctl |= IXGBE_DMATXCTL_TE;
2561                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2562         }
2563
2564         /* Setup the HW Tx Head and Tail descriptor pointers */
2565         for (i = 0; i < adapter->num_tx_queues; i++)
2566                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2567 }
2568
2569 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2570
2571 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2572                                    struct ixgbe_ring *rx_ring)
2573 {
2574         u32 srrctl;
2575         int index;
2576         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2577
2578         index = rx_ring->reg_idx;
2579         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2580                 unsigned long mask;
2581                 mask = (unsigned long) feature[RING_F_RSS].mask;
2582                 index = index & mask;
2583         }
2584         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2585
2586         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2587         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2588         if (adapter->num_vfs)
2589                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2590
2591         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2592                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2593
2594         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2595 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2596                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2597 #else
2598                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2599 #endif
2600                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2601         } else {
2602                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2603                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2604                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2605         }
2606
2607         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2608 }
2609
2610 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2611 {
2612         struct ixgbe_hw *hw = &adapter->hw;
2613         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2614                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2615                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2616         u32 mrqc = 0, reta = 0;
2617         u32 rxcsum;
2618         int i, j;
2619         int mask;
2620
2621         /* Fill out hash function seeds */
2622         for (i = 0; i < 10; i++)
2623                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2624
2625         /* Fill out redirection table */
2626         for (i = 0, j = 0; i < 128; i++, j++) {
2627                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2628                         j = 0;
2629                 /* reta = 4-byte sliding window of
2630                  * 0x00..(indices-1)(indices-1)00..etc. */
2631                 reta = (reta << 8) | (j * 0x11);
2632                 if ((i & 3) == 3)
2633                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2634         }
2635
2636         /* Disable indicating checksum in descriptor, enables RSS hash */
2637         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2638         rxcsum |= IXGBE_RXCSUM_PCSD;
2639         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2640
2641         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2642                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2643         else
2644                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2645 #ifdef CONFIG_IXGBE_DCB
2646                                          | IXGBE_FLAG_DCB_ENABLED
2647 #endif
2648                                          | IXGBE_FLAG_SRIOV_ENABLED
2649                                         );
2650
2651         switch (mask) {
2652         case (IXGBE_FLAG_RSS_ENABLED):
2653                 mrqc = IXGBE_MRQC_RSSEN;
2654                 break;
2655         case (IXGBE_FLAG_SRIOV_ENABLED):
2656                 mrqc = IXGBE_MRQC_VMDQEN;
2657                 break;
2658 #ifdef CONFIG_IXGBE_DCB
2659         case (IXGBE_FLAG_DCB_ENABLED):
2660                 mrqc = IXGBE_MRQC_RT8TCEN;
2661                 break;
2662 #endif /* CONFIG_IXGBE_DCB */
2663         default:
2664                 break;
2665         }
2666
2667         /* Perform hash on these packet types */
2668         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2669               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2670               | IXGBE_MRQC_RSS_FIELD_IPV6
2671               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2672
2673         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2674 }
2675
2676 /**
2677  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2678  * @adapter:    address of board private structure
2679  * @index:      index of ring to set
2680  **/
2681 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2682                                    struct ixgbe_ring *ring)
2683 {
2684         struct ixgbe_hw *hw = &adapter->hw;
2685         u32 rscctrl;
2686         int rx_buf_len;
2687         u16 reg_idx = ring->reg_idx;
2688
2689         if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2690                 return;
2691
2692         rx_buf_len = ring->rx_buf_len;
2693         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2694         rscctrl |= IXGBE_RSCCTL_RSCEN;
2695         /*
2696          * we must limit the number of descriptors so that the
2697          * total size of max desc * buf_len is not greater
2698          * than 65535
2699          */
2700         if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2701 #if (MAX_SKB_FRAGS > 16)
2702                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2703 #elif (MAX_SKB_FRAGS > 8)
2704                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2705 #elif (MAX_SKB_FRAGS > 4)
2706                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2707 #else
2708                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2709 #endif
2710         } else {
2711                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2712                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2713                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2714                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2715                 else
2716                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2717         }
2718         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2719 }
2720
2721 /**
2722  *  ixgbe_set_uta - Set unicast filter table address
2723  *  @adapter: board private structure
2724  *
2725  *  The unicast table address is a register array of 32-bit registers.
2726  *  The table is meant to be used in a way similar to how the MTA is used
2727  *  however due to certain limitations in the hardware it is necessary to
2728  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2729  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2730  **/
2731 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2732 {
2733         struct ixgbe_hw *hw = &adapter->hw;
2734         int i;
2735
2736         /* The UTA table only exists on 82599 hardware and newer */
2737         if (hw->mac.type < ixgbe_mac_82599EB)
2738                 return;
2739
2740         /* we only need to do this if VMDq is enabled */
2741         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2742                 return;
2743
2744         for (i = 0; i < 128; i++)
2745                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2746 }
2747
2748 #define IXGBE_MAX_RX_DESC_POLL 10
2749 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2750                                        struct ixgbe_ring *ring)
2751 {
2752         struct ixgbe_hw *hw = &adapter->hw;
2753         int reg_idx = ring->reg_idx;
2754         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2755         u32 rxdctl;
2756
2757         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2758         if (hw->mac.type == ixgbe_mac_82598EB &&
2759             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2760                 return;
2761
2762         do {
2763                 msleep(1);
2764                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2765         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2766
2767         if (!wait_loop) {
2768                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2769                       "the polling period\n", reg_idx);
2770         }
2771 }
2772
2773 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2774                              struct ixgbe_ring *ring)
2775 {
2776         struct ixgbe_hw *hw = &adapter->hw;
2777         u64 rdba = ring->dma;
2778         u32 rxdctl;
2779         u16 reg_idx = ring->reg_idx;
2780
2781         /* disable queue to avoid issues while updating state */
2782         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2783         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2784                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2785         IXGBE_WRITE_FLUSH(hw);
2786
2787         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2788         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2789         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2790                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2791         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2792         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2793         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2794
2795         ixgbe_configure_srrctl(adapter, ring);
2796         ixgbe_configure_rscctl(adapter, ring);
2797
2798         if (hw->mac.type == ixgbe_mac_82598EB) {
2799                 /*
2800                  * enable cache line friendly hardware writes:
2801                  * PTHRESH=32 descriptors (half the internal cache),
2802                  * this also removes ugly rx_no_buffer_count increment
2803                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2804                  * WTHRESH=8 burst writeback up to two cache lines
2805                  */
2806                 rxdctl &= ~0x3FFFFF;
2807                 rxdctl |=  0x080420;
2808         }
2809
2810         /* enable receive descriptor ring */
2811         rxdctl |= IXGBE_RXDCTL_ENABLE;
2812         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2813
2814         ixgbe_rx_desc_queue_enable(adapter, ring);
2815         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2816 }
2817
2818 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2819 {
2820         struct ixgbe_hw *hw = &adapter->hw;
2821         int p;
2822
2823         /* PSRTYPE must be initialized in non 82598 adapters */
2824         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2825                       IXGBE_PSRTYPE_UDPHDR |
2826                       IXGBE_PSRTYPE_IPV4HDR |
2827                       IXGBE_PSRTYPE_L2HDR |
2828                       IXGBE_PSRTYPE_IPV6HDR;
2829
2830         if (hw->mac.type == ixgbe_mac_82598EB)
2831                 return;
2832
2833         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2834                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2835
2836         for (p = 0; p < adapter->num_rx_pools; p++)
2837                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2838                                 psrtype);
2839 }
2840
2841 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2842 {
2843         struct ixgbe_hw *hw = &adapter->hw;
2844         u32 gcr_ext;
2845         u32 vt_reg_bits;
2846         u32 reg_offset, vf_shift;
2847         u32 vmdctl;
2848
2849         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2850                 return;
2851
2852         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2853         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2854         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2855         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2856
2857         vf_shift = adapter->num_vfs % 32;
2858         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2859
2860         /* Enable only the PF's pool for Tx/Rx */
2861         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2862         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2863         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2864         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2865         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2866
2867         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2868         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2869
2870         /*
2871          * Set up VF register offsets for selected VT Mode,
2872          * i.e. 32 or 64 VFs for SR-IOV
2873          */
2874         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2875         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2876         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2877         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2878
2879         /* enable Tx loopback for VF/PF communication */
2880         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2881 }
2882
2883 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2884 {
2885         struct ixgbe_hw *hw = &adapter->hw;
2886         struct net_device *netdev = adapter->netdev;
2887         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2888         int rx_buf_len;
2889         struct ixgbe_ring *rx_ring;
2890         int i;
2891         u32 mhadd, hlreg0;
2892
2893         /* Decide whether to use packet split mode or not */
2894         /* Do not use packet split if we're in SR-IOV Mode */
2895         if (!adapter->num_vfs)
2896                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2897
2898         /* Set the RX buffer length according to the mode */
2899         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2900                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2901         } else {
2902                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2903                     (netdev->mtu <= ETH_DATA_LEN))
2904                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2905                 else
2906                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2907         }
2908
2909 #ifdef IXGBE_FCOE
2910         /* adjust max frame to be able to do baby jumbo for FCoE */
2911         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2912             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2913                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2914
2915 #endif /* IXGBE_FCOE */
2916         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2917         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2918                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2919                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2920
2921                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2922         }
2923
2924         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2925         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2926         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2927         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2928
2929         /*
2930          * Setup the HW Rx Head and Tail Descriptor Pointers and
2931          * the Base and Length of the Rx Descriptor Ring
2932          */
2933         for (i = 0; i < adapter->num_rx_queues; i++) {
2934                 rx_ring = adapter->rx_ring[i];
2935                 rx_ring->rx_buf_len = rx_buf_len;
2936
2937                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2938                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2939                 else
2940                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2941
2942 #ifdef IXGBE_FCOE
2943                 if (netdev->features & NETIF_F_FCOE_MTU) {
2944                         struct ixgbe_ring_feature *f;
2945                         f = &adapter->ring_feature[RING_F_FCOE];
2946                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2947                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2948                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2949                                         rx_ring->rx_buf_len =
2950                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2951                         }
2952                 }
2953 #endif /* IXGBE_FCOE */
2954         }
2955
2956 }
2957
2958 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2959 {
2960         struct ixgbe_hw *hw = &adapter->hw;
2961         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2962
2963         switch (hw->mac.type) {
2964         case ixgbe_mac_82598EB:
2965                 /*
2966                  * For VMDq support of different descriptor types or
2967                  * buffer sizes through the use of multiple SRRCTL
2968                  * registers, RDRXCTL.MVMEN must be set to 1
2969                  *
2970                  * also, the manual doesn't mention it clearly but DCA hints
2971                  * will only use queue 0's tags unless this bit is set.  Side
2972                  * effects of setting this bit are only that SRRCTL must be
2973                  * fully programmed [0..15]
2974                  */
2975                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2976                 break;
2977         case ixgbe_mac_82599EB:
2978                 /* Disable RSC for ACK packets */
2979                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2980                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2981                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2982                 /* hardware requires some bits to be set by default */
2983                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2984                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2985                 break;
2986         default:
2987                 /* We should do nothing since we don't know this hardware */
2988                 return;
2989         }
2990
2991         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2992 }
2993
2994 /**
2995  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2996  * @adapter: board private structure
2997  *
2998  * Configure the Rx unit of the MAC after a reset.
2999  **/
3000 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3001 {
3002         struct ixgbe_hw *hw = &adapter->hw;
3003         int i;
3004         u32 rxctrl;
3005
3006         /* disable receives while setting up the descriptors */
3007         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3008         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3009
3010         ixgbe_setup_psrtype(adapter);
3011         ixgbe_setup_rdrxctl(adapter);
3012
3013         /* Program registers for the distribution of queues */
3014         ixgbe_setup_mrqc(adapter);
3015
3016         ixgbe_set_uta(adapter);
3017
3018         /* set_rx_buffer_len must be called before ring initialization */
3019         ixgbe_set_rx_buffer_len(adapter);
3020
3021         /*
3022          * Setup the HW Rx Head and Tail Descriptor Pointers and
3023          * the Base and Length of the Rx Descriptor Ring
3024          */
3025         for (i = 0; i < adapter->num_rx_queues; i++)
3026                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3027
3028         /* disable drop enable for 82598 parts */
3029         if (hw->mac.type == ixgbe_mac_82598EB)
3030                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3031
3032         /* enable all receives */
3033         rxctrl |= IXGBE_RXCTRL_RXEN;
3034         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3035 }
3036
3037 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3038 {
3039         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3040         struct ixgbe_hw *hw = &adapter->hw;
3041         int pool_ndx = adapter->num_vfs;
3042
3043         /* add VID to filter table */
3044         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3045         set_bit(vid, adapter->active_vlans);
3046 }
3047
3048 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3049 {
3050         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3051         struct ixgbe_hw *hw = &adapter->hw;
3052         int pool_ndx = adapter->num_vfs;
3053
3054         /* remove VID from filter table */
3055         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3056         clear_bit(vid, adapter->active_vlans);
3057 }
3058
3059 /**
3060  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3061  * @adapter: driver data
3062  */
3063 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3064 {
3065         struct ixgbe_hw *hw = &adapter->hw;
3066         u32 vlnctrl;
3067
3068         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3069         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3070         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3071 }
3072
3073 /**
3074  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3075  * @adapter: driver data
3076  */
3077 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3078 {
3079         struct ixgbe_hw *hw = &adapter->hw;
3080         u32 vlnctrl;
3081
3082         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3083         vlnctrl |= IXGBE_VLNCTRL_VFE;
3084         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3085         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3086 }
3087
3088 /**
3089  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3090  * @adapter: driver data
3091  */
3092 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3093 {
3094         struct ixgbe_hw *hw = &adapter->hw;
3095         u32 vlnctrl;
3096         int i, j;
3097
3098         switch (hw->mac.type) {
3099         case ixgbe_mac_82598EB:
3100                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3101                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3102                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3103                 break;
3104         case ixgbe_mac_82599EB:
3105                 for (i = 0; i < adapter->num_rx_queues; i++) {
3106                         j = adapter->rx_ring[i]->reg_idx;
3107                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3108                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3109                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3110                 }
3111                 break;
3112         default:
3113                 break;
3114         }
3115 }
3116
3117 /**
3118  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3119  * @adapter: driver data
3120  */
3121 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3122 {
3123         struct ixgbe_hw *hw = &adapter->hw;
3124         u32 vlnctrl;
3125         int i, j;
3126
3127         switch (hw->mac.type) {
3128         case ixgbe_mac_82598EB:
3129                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3130                 vlnctrl |= IXGBE_VLNCTRL_VME;
3131                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3132                 break;
3133         case ixgbe_mac_82599EB:
3134                 for (i = 0; i < adapter->num_rx_queues; i++) {
3135                         j = adapter->rx_ring[i]->reg_idx;
3136                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3137                         vlnctrl |= IXGBE_RXDCTL_VME;
3138                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3139                 }
3140                 break;
3141         default:
3142                 break;
3143         }
3144 }
3145
3146 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3147 {
3148         u16 vid;
3149
3150         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3151
3152         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3153                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3154 }
3155
3156 /**
3157  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3158  * @netdev: network interface device structure
3159  *
3160  * Writes unicast address list to the RAR table.
3161  * Returns: -ENOMEM on failure/insufficient address space
3162  *                0 on no addresses written
3163  *                X on writing X addresses to the RAR table
3164  **/
3165 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3166 {
3167         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3168         struct ixgbe_hw *hw = &adapter->hw;
3169         unsigned int vfn = adapter->num_vfs;
3170         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3171         int count = 0;
3172
3173         /* return ENOMEM indicating insufficient memory for addresses */
3174         if (netdev_uc_count(netdev) > rar_entries)
3175                 return -ENOMEM;
3176
3177         if (!netdev_uc_empty(netdev) && rar_entries) {
3178                 struct netdev_hw_addr *ha;
3179                 /* return error if we do not support writing to RAR table */
3180                 if (!hw->mac.ops.set_rar)
3181                         return -ENOMEM;
3182
3183                 netdev_for_each_uc_addr(ha, netdev) {
3184                         if (!rar_entries)
3185                                 break;
3186                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3187                                             vfn, IXGBE_RAH_AV);
3188                         count++;
3189                 }
3190         }
3191         /* write the addresses in reverse order to avoid write combining */
3192         for (; rar_entries > 0 ; rar_entries--)
3193                 hw->mac.ops.clear_rar(hw, rar_entries);
3194
3195         return count;
3196 }
3197
3198 /**
3199  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3200  * @netdev: network interface device structure
3201  *
3202  * The set_rx_method entry point is called whenever the unicast/multicast
3203  * address list or the network interface flags are updated.  This routine is
3204  * responsible for configuring the hardware for proper unicast, multicast and
3205  * promiscuous mode.
3206  **/
3207 void ixgbe_set_rx_mode(struct net_device *netdev)
3208 {
3209         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3210         struct ixgbe_hw *hw = &adapter->hw;
3211         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3212         int count;
3213
3214         /* Check for Promiscuous and All Multicast modes */
3215
3216         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3217
3218         /* set all bits that we expect to always be set */
3219         fctrl |= IXGBE_FCTRL_BAM;
3220         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3221         fctrl |= IXGBE_FCTRL_PMCF;
3222
3223         /* clear the bits we are changing the status of */
3224         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3225
3226         if (netdev->flags & IFF_PROMISC) {
3227                 hw->addr_ctrl.user_set_promisc = true;
3228                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3229                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3230                 /* don't hardware filter vlans in promisc mode */
3231                 ixgbe_vlan_filter_disable(adapter);
3232         } else {
3233                 if (netdev->flags & IFF_ALLMULTI) {
3234                         fctrl |= IXGBE_FCTRL_MPE;
3235                         vmolr |= IXGBE_VMOLR_MPE;
3236                 } else {
3237                         /*
3238                          * Write addresses to the MTA, if the attempt fails
3239                          * then we should just turn on promiscous mode so
3240                          * that we can at least receive multicast traffic
3241                          */
3242                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3243                         vmolr |= IXGBE_VMOLR_ROMPE;
3244                 }
3245                 ixgbe_vlan_filter_enable(adapter);
3246                 hw->addr_ctrl.user_set_promisc = false;
3247                 /*
3248                  * Write addresses to available RAR registers, if there is not
3249                  * sufficient space to store all the addresses then enable
3250                  * unicast promiscous mode
3251                  */
3252                 count = ixgbe_write_uc_addr_list(netdev);
3253                 if (count < 0) {
3254                         fctrl |= IXGBE_FCTRL_UPE;
3255                         vmolr |= IXGBE_VMOLR_ROPE;
3256                 }
3257         }
3258
3259         if (adapter->num_vfs) {
3260                 ixgbe_restore_vf_multicasts(adapter);
3261                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3262                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3263                            IXGBE_VMOLR_ROPE);
3264                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3265         }
3266
3267         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3268
3269         if (netdev->features & NETIF_F_HW_VLAN_RX)
3270                 ixgbe_vlan_strip_enable(adapter);
3271         else
3272                 ixgbe_vlan_strip_disable(adapter);
3273 }
3274
3275 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3276 {
3277         int q_idx;
3278         struct ixgbe_q_vector *q_vector;
3279         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3280
3281         /* legacy and MSI only use one vector */
3282         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3283                 q_vectors = 1;
3284
3285         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3286                 struct napi_struct *napi;
3287                 q_vector = adapter->q_vector[q_idx];
3288                 napi = &q_vector->napi;
3289                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3290                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3291                                 if (q_vector->txr_count == 1)
3292                                         napi->poll = &ixgbe_clean_txonly;
3293                                 else if (q_vector->rxr_count == 1)
3294                                         napi->poll = &ixgbe_clean_rxonly;
3295                         }
3296                 }
3297
3298                 napi_enable(napi);
3299         }
3300 }
3301
3302 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3303 {
3304         int q_idx;
3305         struct ixgbe_q_vector *q_vector;
3306         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3307
3308         /* legacy and MSI only use one vector */
3309         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3310                 q_vectors = 1;
3311
3312         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3313                 q_vector = adapter->q_vector[q_idx];
3314                 napi_disable(&q_vector->napi);
3315         }
3316 }
3317
3318 #ifdef CONFIG_IXGBE_DCB
3319 /*
3320  * ixgbe_configure_dcb - Configure DCB hardware
3321  * @adapter: ixgbe adapter struct
3322  *
3323  * This is called by the driver on open to configure the DCB hardware.
3324  * This is also called by the gennetlink interface when reconfiguring
3325  * the DCB state.
3326  */
3327 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3328 {
3329         struct ixgbe_hw *hw = &adapter->hw;
3330         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3331
3332         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3333                 if (hw->mac.type == ixgbe_mac_82598EB)
3334                         netif_set_gso_max_size(adapter->netdev, 65536);
3335                 return;
3336         }
3337
3338         if (hw->mac.type == ixgbe_mac_82598EB)
3339                 netif_set_gso_max_size(adapter->netdev, 32768);
3340
3341 #ifdef CONFIG_FCOE
3342         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3343                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3344 #endif
3345
3346         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3347                                         DCB_TX_CONFIG);
3348         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3349                                         DCB_RX_CONFIG);
3350
3351         /* Enable VLAN tag insert/strip */
3352         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3353
3354         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3355
3356         /* reconfigure the hardware */
3357         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3358 }
3359
3360 #endif
3361 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3362 {
3363         struct net_device *netdev = adapter->netdev;
3364         struct ixgbe_hw *hw = &adapter->hw;
3365         int i;
3366
3367 #ifdef CONFIG_IXGBE_DCB
3368         ixgbe_configure_dcb(adapter);
3369 #endif
3370
3371         ixgbe_set_rx_mode(netdev);
3372         ixgbe_restore_vlan(adapter);
3373
3374 #ifdef IXGBE_FCOE
3375         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3376                 ixgbe_configure_fcoe(adapter);
3377
3378 #endif /* IXGBE_FCOE */
3379         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3380                 for (i = 0; i < adapter->num_tx_queues; i++)
3381                         adapter->tx_ring[i]->atr_sample_rate =
3382                                                        adapter->atr_sample_rate;
3383                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3384         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3385                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3386         }
3387         ixgbe_configure_virtualization(adapter);
3388
3389         ixgbe_configure_tx(adapter);
3390         ixgbe_configure_rx(adapter);
3391 }
3392
3393 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3394 {
3395         switch (hw->phy.type) {
3396         case ixgbe_phy_sfp_avago:
3397         case ixgbe_phy_sfp_ftl:
3398         case ixgbe_phy_sfp_intel:
3399         case ixgbe_phy_sfp_unknown:
3400         case ixgbe_phy_sfp_passive_tyco:
3401         case ixgbe_phy_sfp_passive_unknown:
3402         case ixgbe_phy_sfp_active_unknown:
3403         case ixgbe_phy_sfp_ftl_active:
3404                 return true;
3405         default:
3406                 return false;
3407         }
3408 }
3409
3410 /**
3411  * ixgbe_sfp_link_config - set up SFP+ link
3412  * @adapter: pointer to private adapter struct
3413  **/
3414 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3415 {
3416         struct ixgbe_hw *hw = &adapter->hw;
3417
3418                 if (hw->phy.multispeed_fiber) {
3419                         /*
3420                          * In multispeed fiber setups, the device may not have
3421                          * had a physical connection when the driver loaded.
3422                          * If that's the case, the initial link configuration
3423                          * couldn't get the MAC into 10G or 1G mode, so we'll
3424                          * never have a link status change interrupt fire.
3425                          * We need to try and force an autonegotiation
3426                          * session, then bring up link.
3427                          */
3428                         hw->mac.ops.setup_sfp(hw);
3429                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3430                                 schedule_work(&adapter->multispeed_fiber_task);
3431                 } else {
3432                         /*
3433                          * Direct Attach Cu and non-multispeed fiber modules
3434                          * still need to be configured properly prior to
3435                          * attempting link.
3436                          */
3437                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3438                                 schedule_work(&adapter->sfp_config_module_task);
3439                 }
3440 }
3441
3442 /**
3443  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3444  * @hw: pointer to private hardware struct
3445  *
3446  * Returns 0 on success, negative on failure
3447  **/
3448 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3449 {
3450         u32 autoneg;
3451         bool negotiation, link_up = false;
3452         u32 ret = IXGBE_ERR_LINK_SETUP;
3453
3454         if (hw->mac.ops.check_link)
3455                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3456
3457         if (ret)
3458                 goto link_cfg_out;
3459
3460         if (hw->mac.ops.get_link_capabilities)
3461                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3462                                                         &negotiation);
3463         if (ret)
3464                 goto link_cfg_out;
3465
3466         if (hw->mac.ops.setup_link)
3467                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3468 link_cfg_out:
3469         return ret;
3470 }
3471
3472 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3473 {
3474         struct ixgbe_hw *hw = &adapter->hw;
3475         u32 gpie = 0;
3476
3477         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3478                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3479                        IXGBE_GPIE_OCD;
3480                 gpie |= IXGBE_GPIE_EIAME;
3481                 /*
3482                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3483                  * this saves a register write for every interrupt
3484                  */
3485                 switch (hw->mac.type) {
3486                 case ixgbe_mac_82598EB:
3487                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3488                         break;
3489                 default:
3490                 case ixgbe_mac_82599EB:
3491                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3492                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3493                         break;
3494                 }
3495         } else {
3496                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3497                  * specifically only auto mask tx and rx interrupts */
3498                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3499         }
3500
3501         /* XXX: to interrupt immediately for EICS writes, enable this */
3502         /* gpie |= IXGBE_GPIE_EIMEN; */
3503
3504         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3505                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3506                 gpie |= IXGBE_GPIE_VTMODE_64;
3507         }
3508
3509         /* Enable fan failure interrupt */
3510         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3511                 gpie |= IXGBE_SDP1_GPIEN;
3512
3513         if (hw->mac.type == ixgbe_mac_82599EB)
3514                 gpie |= IXGBE_SDP1_GPIEN;
3515                 gpie |= IXGBE_SDP2_GPIEN;
3516
3517         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3518 }
3519
3520 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3521 {
3522         struct ixgbe_hw *hw = &adapter->hw;
3523         int err;
3524         u32 ctrl_ext;
3525
3526         ixgbe_get_hw_control(adapter);
3527         ixgbe_setup_gpie(adapter);
3528
3529         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3530                 ixgbe_configure_msix(adapter);
3531         else
3532                 ixgbe_configure_msi_and_legacy(adapter);
3533
3534         /* enable the optics */
3535         if (hw->phy.multispeed_fiber)
3536                 hw->mac.ops.enable_tx_laser(hw);
3537
3538         clear_bit(__IXGBE_DOWN, &adapter->state);
3539         ixgbe_napi_enable_all(adapter);
3540
3541         /* clear any pending interrupts, may auto mask */
3542         IXGBE_READ_REG(hw, IXGBE_EICR);
3543         ixgbe_irq_enable(adapter, true, true);
3544
3545         /*
3546          * If this adapter has a fan, check to see if we had a failure
3547          * before we enabled the interrupt.
3548          */
3549         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3550                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3551                 if (esdp & IXGBE_ESDP_SDP1)
3552                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3553         }
3554
3555         /*
3556          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3557          * arrived before interrupts were enabled but after probe.  Such
3558          * devices wouldn't have their type identified yet. We need to
3559          * kick off the SFP+ module setup first, then try to bring up link.
3560          * If we're not hot-pluggable SFP+, we just need to configure link
3561          * and bring it up.
3562          */
3563         if (hw->phy.type == ixgbe_phy_unknown) {
3564                 err = hw->phy.ops.identify(hw);
3565                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3566                         /*
3567                          * Take the device down and schedule the sfp tasklet
3568                          * which will unregister_netdev and log it.
3569                          */
3570                         ixgbe_down(adapter);
3571                         schedule_work(&adapter->sfp_config_module_task);
3572                         return err;
3573                 }
3574         }
3575
3576         if (ixgbe_is_sfp(hw)) {
3577                 ixgbe_sfp_link_config(adapter);
3578         } else {
3579                 err = ixgbe_non_sfp_link_config(hw);
3580                 if (err)
3581                         e_err(probe, "link_config FAILED %d\n", err);
3582         }
3583
3584         /* enable transmits */
3585         netif_tx_start_all_queues(adapter->netdev);
3586
3587         /* bring the link up in the watchdog, this could race with our first
3588          * link up interrupt but shouldn't be a problem */
3589         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3590         adapter->link_check_timeout = jiffies;
3591         mod_timer(&adapter->watchdog_timer, jiffies);
3592
3593         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3594         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3595         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3596         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3597
3598         return 0;
3599 }
3600
3601 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3602 {
3603         WARN_ON(in_interrupt());
3604         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3605                 msleep(1);
3606         ixgbe_down(adapter);
3607         /*
3608          * If SR-IOV enabled then wait a bit before bringing the adapter
3609          * back up to give the VFs time to respond to the reset.  The
3610          * two second wait is based upon the watchdog timer cycle in
3611          * the VF driver.
3612          */
3613         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3614                 msleep(2000);
3615         ixgbe_up(adapter);
3616         clear_bit(__IXGBE_RESETTING, &adapter->state);
3617 }
3618
3619 int ixgbe_up(struct ixgbe_adapter *adapter)
3620 {
3621         /* hardware has been reset, we need to reload some things */
3622         ixgbe_configure(adapter);
3623
3624         return ixgbe_up_complete(adapter);
3625 }
3626
3627 void ixgbe_reset(struct ixgbe_adapter *adapter)
3628 {
3629         struct ixgbe_hw *hw = &adapter->hw;
3630         int err;
3631
3632         err = hw->mac.ops.init_hw(hw);
3633         switch (err) {
3634         case 0:
3635         case IXGBE_ERR_SFP_NOT_PRESENT:
3636                 break;
3637         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3638                 e_dev_err("master disable timed out\n");
3639                 break;
3640         case IXGBE_ERR_EEPROM_VERSION:
3641                 /* We are running on a pre-production device, log a warning */
3642                 e_dev_warn("This device is a pre-production adapter/LOM. "
3643                            "Please be aware there may be issuesassociated with "
3644                            "your hardware.  If you are experiencing problems "
3645                            "please contact your Intel or hardware "
3646                            "representative who provided you with this "
3647                            "hardware.\n");
3648                 break;
3649         default:
3650                 e_dev_err("Hardware Error: %d\n", err);
3651         }
3652
3653         /* reprogram the RAR[0] in case user changed it. */
3654         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3655                             IXGBE_RAH_AV);
3656 }
3657
3658 /**
3659  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3660  * @rx_ring: ring to free buffers from
3661  **/
3662 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3663 {
3664         struct device *dev = rx_ring->dev;
3665         unsigned long size;
3666         u16 i;
3667
3668         /* ring already cleared, nothing to do */
3669         if (!rx_ring->rx_buffer_info)
3670                 return;
3671
3672         /* Free all the Rx ring sk_buffs */
3673         for (i = 0; i < rx_ring->count; i++) {
3674                 struct ixgbe_rx_buffer *rx_buffer_info;
3675
3676                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3677                 if (rx_buffer_info->dma) {
3678                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3679                                          rx_ring->rx_buf_len,
3680                                          DMA_FROM_DEVICE);
3681                         rx_buffer_info->dma = 0;
3682                 }
3683                 if (rx_buffer_info->skb) {
3684                         struct sk_buff *skb = rx_buffer_info->skb;
3685                         rx_buffer_info->skb = NULL;
3686                         do {
3687                                 struct sk_buff *this = skb;
3688                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3689                                         dma_unmap_single(dev,
3690                                                          IXGBE_RSC_CB(this)->dma,
3691                                                          rx_ring->rx_buf_len,
3692                                                          DMA_FROM_DEVICE);
3693                                         IXGBE_RSC_CB(this)->dma = 0;
3694                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3695                                 }
3696                                 skb = skb->prev;
3697                                 dev_kfree_skb(this);
3698                         } while (skb);
3699                 }
3700                 if (!rx_buffer_info->page)
3701                         continue;
3702                 if (rx_buffer_info->page_dma) {
3703                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3704                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3705                         rx_buffer_info->page_dma = 0;
3706                 }
3707                 put_page(rx_buffer_info->page);
3708                 rx_buffer_info->page = NULL;
3709                 rx_buffer_info->page_offset = 0;
3710         }
3711
3712         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3713         memset(rx_ring->rx_buffer_info, 0, size);
3714
3715         /* Zero out the descriptor ring */
3716         memset(rx_ring->desc, 0, rx_ring->size);
3717
3718         rx_ring->next_to_clean = 0;
3719         rx_ring->next_to_use = 0;
3720 }
3721
3722 /**
3723  * ixgbe_clean_tx_ring - Free Tx Buffers
3724  * @tx_ring: ring to be cleaned
3725  **/
3726 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3727 {
3728         struct ixgbe_tx_buffer *tx_buffer_info;
3729         unsigned long size;
3730         u16 i;
3731
3732         /* ring already cleared, nothing to do */
3733         if (!tx_ring->tx_buffer_info)
3734                 return;
3735
3736         /* Free all the Tx ring sk_buffs */
3737         for (i = 0; i < tx_ring->count; i++) {
3738                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3739                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3740         }
3741
3742         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3743         memset(tx_ring->tx_buffer_info, 0, size);
3744
3745         /* Zero out the descriptor ring */
3746         memset(tx_ring->desc, 0, tx_ring->size);
3747
3748         tx_ring->next_to_use = 0;
3749         tx_ring->next_to_clean = 0;
3750 }
3751
3752 /**
3753  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3754  * @adapter: board private structure
3755  **/
3756 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3757 {
3758         int i;
3759
3760         for (i = 0; i < adapter->num_rx_queues; i++)
3761                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3762 }
3763
3764 /**
3765  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3766  * @adapter: board private structure
3767  **/
3768 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3769 {
3770         int i;
3771
3772         for (i = 0; i < adapter->num_tx_queues; i++)
3773                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3774 }
3775
3776 void ixgbe_down(struct ixgbe_adapter *adapter)
3777 {
3778         struct net_device *netdev = adapter->netdev;
3779         struct ixgbe_hw *hw = &adapter->hw;
3780         u32 rxctrl;
3781         u32 txdctl;
3782         int i, j;
3783         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3784
3785         /* signal that we are down to the interrupt handler */
3786         set_bit(__IXGBE_DOWN, &adapter->state);
3787
3788         /* disable receive for all VFs and wait one second */
3789         if (adapter->num_vfs) {
3790                 /* ping all the active vfs to let them know we are going down */
3791                 ixgbe_ping_all_vfs(adapter);
3792
3793                 /* Disable all VFTE/VFRE TX/RX */
3794                 ixgbe_disable_tx_rx(adapter);
3795
3796                 /* Mark all the VFs as inactive */
3797                 for (i = 0 ; i < adapter->num_vfs; i++)
3798                         adapter->vfinfo[i].clear_to_send = 0;
3799         }
3800
3801         /* disable receives */
3802         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3803         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3804
3805         IXGBE_WRITE_FLUSH(hw);
3806         msleep(10);
3807
3808         netif_tx_stop_all_queues(netdev);
3809
3810         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3811         del_timer_sync(&adapter->sfp_timer);
3812         del_timer_sync(&adapter->watchdog_timer);
3813         cancel_work_sync(&adapter->watchdog_task);
3814
3815         netif_carrier_off(netdev);
3816         netif_tx_disable(netdev);
3817
3818         ixgbe_irq_disable(adapter);
3819
3820         ixgbe_napi_disable_all(adapter);
3821
3822         /* Cleanup the affinity_hint CPU mask memory and callback */
3823         for (i = 0; i < num_q_vectors; i++) {
3824                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3825                 /* clear the affinity_mask in the IRQ descriptor */
3826                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3827                 /* release the CPU mask memory */
3828                 free_cpumask_var(q_vector->affinity_mask);
3829         }
3830
3831         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3832             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3833                 cancel_work_sync(&adapter->fdir_reinit_task);
3834
3835         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3836                 cancel_work_sync(&adapter->check_overtemp_task);
3837
3838         /* disable transmits in the hardware now that interrupts are off */
3839         for (i = 0; i < adapter->num_tx_queues; i++) {
3840                 j = adapter->tx_ring[i]->reg_idx;
3841                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3842                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3843                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3844         }
3845         /* Disable the Tx DMA engine on 82599 */
3846         if (hw->mac.type == ixgbe_mac_82599EB)
3847                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3848                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3849                                  ~IXGBE_DMATXCTL_TE));
3850
3851         /* power down the optics */
3852         if (hw->phy.multispeed_fiber)
3853                 hw->mac.ops.disable_tx_laser(hw);
3854
3855         /* clear n-tuple filters that are cached */
3856         ethtool_ntuple_flush(netdev);
3857
3858         if (!pci_channel_offline(adapter->pdev))
3859                 ixgbe_reset(adapter);
3860         ixgbe_clean_all_tx_rings(adapter);
3861         ixgbe_clean_all_rx_rings(adapter);
3862
3863 #ifdef CONFIG_IXGBE_DCA
3864         /* since we reset the hardware DCA settings were cleared */
3865         ixgbe_setup_dca(adapter);
3866 #endif
3867 }
3868
3869 /**
3870  * ixgbe_poll - NAPI Rx polling callback
3871  * @napi: structure for representing this polling device
3872  * @budget: how many packets driver is allowed to clean
3873  *
3874  * This function is used for legacy and MSI, NAPI mode
3875  **/
3876 static int ixgbe_poll(struct napi_struct *napi, int budget)
3877 {
3878         struct ixgbe_q_vector *q_vector =
3879                                 container_of(napi, struct ixgbe_q_vector, napi);
3880         struct ixgbe_adapter *adapter = q_vector->adapter;
3881         int tx_clean_complete, work_done = 0;
3882
3883 #ifdef CONFIG_IXGBE_DCA
3884         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3885                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3886                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3887         }
3888 #endif
3889
3890         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3891         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3892
3893         if (!tx_clean_complete)
3894                 work_done = budget;
3895
3896         /* If budget not fully consumed, exit the polling mode */
3897         if (work_done < budget) {
3898                 napi_complete(napi);
3899                 if (adapter->rx_itr_setting & 1)
3900                         ixgbe_set_itr(adapter);
3901                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3902                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3903         }
3904         return work_done;
3905 }
3906
3907 /**
3908  * ixgbe_tx_timeout - Respond to a Tx Hang
3909  * @netdev: network interface device structure
3910  **/
3911 static void ixgbe_tx_timeout(struct net_device *netdev)
3912 {
3913         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3914
3915         /* Do the reset outside of interrupt context */
3916         schedule_work(&adapter->reset_task);
3917 }
3918
3919 static void ixgbe_reset_task(struct work_struct *work)
3920 {
3921         struct ixgbe_adapter *adapter;
3922         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3923
3924         /* If we're already down or resetting, just bail */
3925         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3926             test_bit(__IXGBE_RESETTING, &adapter->state))
3927                 return;
3928
3929         adapter->tx_timeout_count++;
3930
3931         ixgbe_dump(adapter);
3932         netdev_err(adapter->netdev, "Reset adapter\n");
3933         ixgbe_reinit_locked(adapter);
3934 }
3935
3936 #ifdef CONFIG_IXGBE_DCB
3937 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3938 {
3939         bool ret = false;
3940         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3941
3942         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3943                 return ret;
3944
3945         f->mask = 0x7 << 3;
3946         adapter->num_rx_queues = f->indices;
3947         adapter->num_tx_queues = f->indices;
3948         ret = true;
3949
3950         return ret;
3951 }
3952 #endif
3953
3954 /**
3955  * ixgbe_set_rss_queues: Allocate queues for RSS
3956  * @adapter: board private structure to initialize
3957  *
3958  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3959  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3960  *
3961  **/
3962 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3963 {
3964         bool ret = false;
3965         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3966
3967         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3968                 f->mask = 0xF;
3969                 adapter->num_rx_queues = f->indices;
3970                 adapter->num_tx_queues = f->indices;
3971                 ret = true;
3972         } else {
3973                 ret = false;
3974         }
3975
3976         return ret;
3977 }
3978
3979 /**
3980  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3981  * @adapter: board private structure to initialize
3982  *
3983  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3984  * to the original CPU that initiated the Tx session.  This runs in addition
3985  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3986  * Rx load across CPUs using RSS.
3987  *
3988  **/
3989 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3990 {
3991         bool ret = false;
3992         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3993
3994         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3995         f_fdir->mask = 0;
3996
3997         /* Flow Director must have RSS enabled */
3998         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3999             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4000              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4001                 adapter->num_tx_queues = f_fdir->indices;
4002                 adapter->num_rx_queues = f_fdir->indices;
4003                 ret = true;
4004         } else {
4005                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4006                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4007         }
4008         return ret;
4009 }
4010
4011 #ifdef IXGBE_FCOE
4012 /**
4013  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4014  * @adapter: board private structure to initialize
4015  *
4016  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4017  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4018  * rx queues out of the max number of rx queues, instead, it is used as the
4019  * index of the first rx queue used by FCoE.
4020  *
4021  **/
4022 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4023 {
4024         bool ret = false;
4025         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4026
4027         f->indices = min((int)num_online_cpus(), f->indices);
4028         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4029                 adapter->num_rx_queues = 1;
4030                 adapter->num_tx_queues = 1;
4031 #ifdef CONFIG_IXGBE_DCB
4032                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4033                         e_info(probe, "FCoE enabled with DCB\n");
4034                         ixgbe_set_dcb_queues(adapter);
4035                 }
4036 #endif
4037                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4038                         e_info(probe, "FCoE enabled with RSS\n");
4039                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4040                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4041                                 ixgbe_set_fdir_queues(adapter);
4042                         else
4043                                 ixgbe_set_rss_queues(adapter);
4044                 }
4045                 /* adding FCoE rx rings to the end */
4046                 f->mask = adapter->num_rx_queues;
4047                 adapter->num_rx_queues += f->indices;
4048                 adapter->num_tx_queues += f->indices;
4049
4050                 ret = true;
4051         }
4052
4053         return ret;
4054 }
4055
4056 #endif /* IXGBE_FCOE */
4057 /**
4058  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4059  * @adapter: board private structure to initialize
4060  *
4061  * IOV doesn't actually use anything, so just NAK the
4062  * request for now and let the other queue routines
4063  * figure out what to do.
4064  */
4065 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4066 {
4067         return false;
4068 }
4069
4070 /*
4071  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4072  * @adapter: board private structure to initialize
4073  *
4074  * This is the top level queue allocation routine.  The order here is very
4075  * important, starting with the "most" number of features turned on at once,
4076  * and ending with the smallest set of features.  This way large combinations
4077  * can be allocated if they're turned on, and smaller combinations are the
4078  * fallthrough conditions.
4079  *
4080  **/
4081 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4082 {
4083         /* Start with base case */
4084         adapter->num_rx_queues = 1;
4085         adapter->num_tx_queues = 1;
4086         adapter->num_rx_pools = adapter->num_rx_queues;
4087         adapter->num_rx_queues_per_pool = 1;
4088
4089         if (ixgbe_set_sriov_queues(adapter))
4090                 goto done;
4091
4092 #ifdef IXGBE_FCOE
4093         if (ixgbe_set_fcoe_queues(adapter))
4094                 goto done;
4095
4096 #endif /* IXGBE_FCOE */
4097 #ifdef CONFIG_IXGBE_DCB
4098         if (ixgbe_set_dcb_queues(adapter))
4099                 goto done;
4100
4101 #endif
4102         if (ixgbe_set_fdir_queues(adapter))
4103                 goto done;
4104
4105         if (ixgbe_set_rss_queues(adapter))
4106                 goto done;
4107
4108         /* fallback to base case */
4109         adapter->num_rx_queues = 1;
4110         adapter->num_tx_queues = 1;
4111
4112 done:
4113         /* Notify the stack of the (possibly) reduced queue counts. */
4114         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4115         return netif_set_real_num_rx_queues(adapter->netdev,
4116                                             adapter->num_rx_queues);
4117 }
4118
4119 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4120                                        int vectors)
4121 {
4122         int err, vector_threshold;
4123
4124         /* We'll want at least 3 (vector_threshold):
4125          * 1) TxQ[0] Cleanup
4126          * 2) RxQ[0] Cleanup
4127          * 3) Other (Link Status Change, etc.)
4128          * 4) TCP Timer (optional)
4129          */
4130         vector_threshold = MIN_MSIX_COUNT;
4131
4132         /* The more we get, the more we will assign to Tx/Rx Cleanup
4133          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4134          * Right now, we simply care about how many we'll get; we'll
4135          * set them up later while requesting irq's.
4136          */
4137         while (vectors >= vector_threshold) {
4138                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4139                                       vectors);
4140                 if (!err) /* Success in acquiring all requested vectors. */
4141                         break;
4142                 else if (err < 0)
4143                         vectors = 0; /* Nasty failure, quit now */
4144                 else /* err == number of vectors we should try again with */
4145                         vectors = err;
4146         }
4147
4148         if (vectors < vector_threshold) {
4149                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4150                  * This just means we'll go with either a single MSI
4151                  * vector or fall back to legacy interrupts.
4152                  */
4153                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4154                              "Unable to allocate MSI-X interrupts\n");
4155                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4156                 kfree(adapter->msix_entries);
4157                 adapter->msix_entries = NULL;
4158         } else {
4159                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4160                 /*
4161                  * Adjust for only the vectors we'll use, which is minimum
4162                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4163                  * vectors we were allocated.
4164                  */
4165                 adapter->num_msix_vectors = min(vectors,
4166                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4167         }
4168 }
4169
4170 /**
4171  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4172  * @adapter: board private structure to initialize
4173  *
4174  * Cache the descriptor ring offsets for RSS to the assigned rings.
4175  *
4176  **/
4177 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4178 {
4179         int i;
4180         bool ret = false;
4181
4182         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4183                 for (i = 0; i < adapter->num_rx_queues; i++)
4184                         adapter->rx_ring[i]->reg_idx = i;
4185                 for (i = 0; i < adapter->num_tx_queues; i++)
4186                         adapter->tx_ring[i]->reg_idx = i;
4187                 ret = true;
4188         } else {
4189                 ret = false;
4190         }
4191
4192         return ret;
4193 }
4194
4195 #ifdef CONFIG_IXGBE_DCB
4196 /**
4197  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4198  * @adapter: board private structure to initialize
4199  *
4200  * Cache the descriptor ring offsets for DCB to the assigned rings.
4201  *
4202  **/
4203 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4204 {
4205         int i;
4206         bool ret = false;
4207         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4208
4209         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4210                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4211                         /* the number of queues is assumed to be symmetric */
4212                         for (i = 0; i < dcb_i; i++) {
4213                                 adapter->rx_ring[i]->reg_idx = i << 3;
4214                                 adapter->tx_ring[i]->reg_idx = i << 2;
4215                         }
4216                         ret = true;
4217                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4218                         if (dcb_i == 8) {
4219                                 /*
4220                                  * Tx TC0 starts at: descriptor queue 0
4221                                  * Tx TC1 starts at: descriptor queue 32
4222                                  * Tx TC2 starts at: descriptor queue 64
4223                                  * Tx TC3 starts at: descriptor queue 80
4224                                  * Tx TC4 starts at: descriptor queue 96
4225                                  * Tx TC5 starts at: descriptor queue 104
4226                                  * Tx TC6 starts at: descriptor queue 112
4227                                  * Tx TC7 starts at: descriptor queue 120
4228                                  *
4229                                  * Rx TC0-TC7 are offset by 16 queues each
4230                                  */
4231                                 for (i = 0; i < 3; i++) {
4232                                         adapter->tx_ring[i]->reg_idx = i << 5;
4233                                         adapter->rx_ring[i]->reg_idx = i << 4;
4234                                 }
4235                                 for ( ; i < 5; i++) {
4236                                         adapter->tx_ring[i]->reg_idx =
4237                                                                  ((i + 2) << 4);
4238                                         adapter->rx_ring[i]->reg_idx = i << 4;
4239                                 }
4240                                 for ( ; i < dcb_i; i++) {
4241                                         adapter->tx_ring[i]->reg_idx =
4242                                                                  ((i + 8) << 3);
4243                                         adapter->rx_ring[i]->reg_idx = i << 4;
4244                                 }
4245
4246                                 ret = true;
4247                         } else if (dcb_i == 4) {
4248                                 /*
4249                                  * Tx TC0 starts at: descriptor queue 0
4250                                  * Tx TC1 starts at: descriptor queue 64
4251                                  * Tx TC2 starts at: descriptor queue 96
4252                                  * Tx TC3 starts at: descriptor queue 112
4253                                  *
4254                                  * Rx TC0-TC3 are offset by 32 queues each
4255                                  */
4256                                 adapter->tx_ring[0]->reg_idx = 0;
4257                                 adapter->tx_ring[1]->reg_idx = 64;
4258                                 adapter->tx_ring[2]->reg_idx = 96;
4259                                 adapter->tx_ring[3]->reg_idx = 112;
4260                                 for (i = 0 ; i < dcb_i; i++)
4261                                         adapter->rx_ring[i]->reg_idx = i << 5;
4262
4263                                 ret = true;
4264                         } else {
4265                                 ret = false;
4266                         }
4267                 } else {
4268                         ret = false;
4269                 }
4270         } else {
4271                 ret = false;
4272         }
4273
4274         return ret;
4275 }
4276 #endif
4277
4278 /**
4279  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4280  * @adapter: board private structure to initialize
4281  *
4282  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4283  *
4284  **/
4285 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4286 {
4287         int i;
4288         bool ret = false;
4289
4290         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4291             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4292              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4293                 for (i = 0; i < adapter->num_rx_queues; i++)
4294                         adapter->rx_ring[i]->reg_idx = i;
4295                 for (i = 0; i < adapter->num_tx_queues; i++)
4296                         adapter->tx_ring[i]->reg_idx = i;
4297                 ret = true;
4298         }
4299
4300         return ret;
4301 }
4302
4303 #ifdef IXGBE_FCOE
4304 /**
4305  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4306  * @adapter: board private structure to initialize
4307  *
4308  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4309  *
4310  */
4311 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4312 {
4313         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4314         bool ret = false;
4315         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4316
4317         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4318 #ifdef CONFIG_IXGBE_DCB
4319                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4320                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4321
4322                         ixgbe_cache_ring_dcb(adapter);
4323                         /* find out queues in TC for FCoE */
4324                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4325                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4326                         /*
4327                          * In 82599, the number of Tx queues for each traffic
4328                          * class for both 8-TC and 4-TC modes are:
4329                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4330                          * 8 TCs:  32  32  16  16   8   8   8   8
4331                          * 4 TCs:  64  64  32  32
4332                          * We have max 8 queues for FCoE, where 8 the is
4333                          * FCoE redirection table size. If TC for FCoE is
4334                          * less than or equal to TC3, we have enough queues
4335                          * to add max of 8 queues for FCoE, so we start FCoE
4336                          * tx descriptor from the next one, i.e., reg_idx + 1.
4337                          * If TC for FCoE is above TC3, implying 8 TC mode,
4338                          * and we need 8 for FCoE, we have to take all queues
4339                          * in that traffic class for FCoE.
4340                          */
4341                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4342                                 fcoe_tx_i--;
4343                 }
4344 #endif /* CONFIG_IXGBE_DCB */
4345                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4346                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4347                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4348                                 ixgbe_cache_ring_fdir(adapter);
4349                         else
4350                                 ixgbe_cache_ring_rss(adapter);
4351
4352                         fcoe_rx_i = f->mask;
4353                         fcoe_tx_i = f->mask;
4354                 }
4355                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4356                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4357                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4358                 }
4359                 ret = true;
4360         }
4361         return ret;
4362 }
4363
4364 #endif /* IXGBE_FCOE */
4365 /**
4366  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4367  * @adapter: board private structure to initialize
4368  *
4369  * SR-IOV doesn't use any descriptor rings but changes the default if
4370  * no other mapping is used.
4371  *
4372  */
4373 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4374 {
4375         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4376         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4377         if (adapter->num_vfs)
4378                 return true;
4379         else
4380                 return false;
4381 }
4382
4383 /**
4384  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4385  * @adapter: board private structure to initialize
4386  *
4387  * Once we know the feature-set enabled for the device, we'll cache
4388  * the register offset the descriptor ring is assigned to.
4389  *
4390  * Note, the order the various feature calls is important.  It must start with
4391  * the "most" features enabled at the same time, then trickle down to the
4392  * least amount of features turned on at once.
4393  **/
4394 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4395 {
4396         /* start with default case */
4397         adapter->rx_ring[0]->reg_idx = 0;
4398         adapter->tx_ring[0]->reg_idx = 0;
4399
4400         if (ixgbe_cache_ring_sriov(adapter))
4401                 return;
4402
4403 #ifdef IXGBE_FCOE
4404         if (ixgbe_cache_ring_fcoe(adapter))
4405                 return;
4406
4407 #endif /* IXGBE_FCOE */
4408 #ifdef CONFIG_IXGBE_DCB
4409         if (ixgbe_cache_ring_dcb(adapter))
4410                 return;
4411
4412 #endif
4413         if (ixgbe_cache_ring_fdir(adapter))
4414                 return;
4415
4416         if (ixgbe_cache_ring_rss(adapter))
4417                 return;
4418 }
4419
4420 /**
4421  * ixgbe_alloc_queues - Allocate memory for all rings
4422  * @adapter: board private structure to initialize
4423  *
4424  * We allocate one ring per queue at run-time since we don't know the
4425  * number of queues at compile-time.  The polling_netdev array is
4426  * intended for Multiqueue, but should work fine with a single queue.
4427  **/
4428 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4429 {
4430         int i;
4431         int rx_count;
4432         int orig_node = adapter->node;
4433
4434         for (i = 0; i < adapter->num_tx_queues; i++) {
4435                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4436                 if (orig_node == -1) {
4437                         int cur_node = next_online_node(adapter->node);
4438                         if (cur_node == MAX_NUMNODES)
4439                                 cur_node = first_online_node;
4440                         adapter->node = cur_node;
4441                 }
4442                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4443                                     adapter->node);
4444                 if (!ring)
4445                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4446                 if (!ring)
4447                         goto err_tx_ring_allocation;
4448                 ring->count = adapter->tx_ring_count;
4449                 ring->queue_index = i;
4450                 ring->dev = &adapter->pdev->dev;
4451                 ring->netdev = adapter->netdev;
4452                 ring->numa_node = adapter->node;
4453
4454                 adapter->tx_ring[i] = ring;
4455         }
4456
4457         /* Restore the adapter's original node */
4458         adapter->node = orig_node;
4459
4460         rx_count = adapter->rx_ring_count;
4461         for (i = 0; i < adapter->num_rx_queues; i++) {
4462                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4463                 if (orig_node == -1) {
4464                         int cur_node = next_online_node(adapter->node);
4465                         if (cur_node == MAX_NUMNODES)
4466                                 cur_node = first_online_node;
4467                         adapter->node = cur_node;
4468                 }
4469                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4470                                     adapter->node);
4471                 if (!ring)
4472                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4473                 if (!ring)
4474                         goto err_rx_ring_allocation;
4475                 ring->count = rx_count;
4476                 ring->queue_index = i;
4477                 ring->dev = &adapter->pdev->dev;
4478                 ring->netdev = adapter->netdev;
4479                 ring->numa_node = adapter->node;
4480
4481                 adapter->rx_ring[i] = ring;
4482         }
4483
4484         /* Restore the adapter's original node */
4485         adapter->node = orig_node;
4486
4487         ixgbe_cache_ring_register(adapter);
4488
4489         return 0;
4490
4491 err_rx_ring_allocation:
4492         for (i = 0; i < adapter->num_tx_queues; i++)
4493                 kfree(adapter->tx_ring[i]);
4494 err_tx_ring_allocation:
4495         return -ENOMEM;
4496 }
4497
4498 /**
4499  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4500  * @adapter: board private structure to initialize
4501  *
4502  * Attempt to configure the interrupts using the best available
4503  * capabilities of the hardware and the kernel.
4504  **/
4505 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4506 {
4507         struct ixgbe_hw *hw = &adapter->hw;
4508         int err = 0;
4509         int vector, v_budget;
4510
4511         /*
4512          * It's easy to be greedy for MSI-X vectors, but it really
4513          * doesn't do us much good if we have a lot more vectors
4514          * than CPU's.  So let's be conservative and only ask for
4515          * (roughly) the same number of vectors as there are CPU's.
4516          */
4517         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4518                        (int)num_online_cpus()) + NON_Q_VECTORS;
4519
4520         /*
4521          * At the same time, hardware can only support a maximum of
4522          * hw.mac->max_msix_vectors vectors.  With features
4523          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4524          * descriptor queues supported by our device.  Thus, we cap it off in
4525          * those rare cases where the cpu count also exceeds our vector limit.
4526          */
4527         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4528
4529         /* A failure in MSI-X entry allocation isn't fatal, but it does
4530          * mean we disable MSI-X capabilities of the adapter. */
4531         adapter->msix_entries = kcalloc(v_budget,
4532                                         sizeof(struct msix_entry), GFP_KERNEL);
4533         if (adapter->msix_entries) {
4534                 for (vector = 0; vector < v_budget; vector++)
4535                         adapter->msix_entries[vector].entry = vector;
4536
4537                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4538
4539                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4540                         goto out;
4541         }
4542
4543         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4544         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4545         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4546         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4547         adapter->atr_sample_rate = 0;
4548         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4549                 ixgbe_disable_sriov(adapter);
4550
4551         err = ixgbe_set_num_queues(adapter);
4552         if (err)
4553                 return err;
4554
4555         err = pci_enable_msi(adapter->pdev);
4556         if (!err) {
4557                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4558         } else {
4559                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4560                              "Unable to allocate MSI interrupt, "
4561                              "falling back to legacy.  Error: %d\n", err);
4562                 /* reset err */
4563                 err = 0;
4564         }
4565
4566 out:
4567         return err;
4568 }
4569
4570 /**
4571  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4572  * @adapter: board private structure to initialize
4573  *
4574  * We allocate one q_vector per queue interrupt.  If allocation fails we
4575  * return -ENOMEM.
4576  **/
4577 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4578 {
4579         int q_idx, num_q_vectors;
4580         struct ixgbe_q_vector *q_vector;
4581         int napi_vectors;
4582         int (*poll)(struct napi_struct *, int);
4583
4584         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4585                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4586                 napi_vectors = adapter->num_rx_queues;
4587                 poll = &ixgbe_clean_rxtx_many;
4588         } else {
4589                 num_q_vectors = 1;
4590                 napi_vectors = 1;
4591                 poll = &ixgbe_poll;
4592         }
4593
4594         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4595                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4596                                         GFP_KERNEL, adapter->node);
4597                 if (!q_vector)
4598                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4599                                            GFP_KERNEL);
4600                 if (!q_vector)
4601                         goto err_out;
4602                 q_vector->adapter = adapter;
4603                 if (q_vector->txr_count && !q_vector->rxr_count)
4604                         q_vector->eitr = adapter->tx_eitr_param;
4605                 else
4606                         q_vector->eitr = adapter->rx_eitr_param;
4607                 q_vector->v_idx = q_idx;
4608                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4609                 adapter->q_vector[q_idx] = q_vector;
4610         }
4611
4612         return 0;
4613
4614 err_out:
4615         while (q_idx) {
4616                 q_idx--;
4617                 q_vector = adapter->q_vector[q_idx];
4618                 netif_napi_del(&q_vector->napi);
4619                 kfree(q_vector);
4620                 adapter->q_vector[q_idx] = NULL;
4621         }
4622         return -ENOMEM;
4623 }
4624
4625 /**
4626  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4627  * @adapter: board private structure to initialize
4628  *
4629  * This function frees the memory allocated to the q_vectors.  In addition if
4630  * NAPI is enabled it will delete any references to the NAPI struct prior
4631  * to freeing the q_vector.
4632  **/
4633 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4634 {
4635         int q_idx, num_q_vectors;
4636
4637         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4638                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4639         else
4640                 num_q_vectors = 1;
4641
4642         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4643                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4644                 adapter->q_vector[q_idx] = NULL;
4645                 netif_napi_del(&q_vector->napi);
4646                 kfree(q_vector);
4647         }
4648 }
4649
4650 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4651 {
4652         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4653                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4654                 pci_disable_msix(adapter->pdev);
4655                 kfree(adapter->msix_entries);
4656                 adapter->msix_entries = NULL;
4657         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4658                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4659                 pci_disable_msi(adapter->pdev);
4660         }
4661 }
4662
4663 /**
4664  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4665  * @adapter: board private structure to initialize
4666  *
4667  * We determine which interrupt scheme to use based on...
4668  * - Kernel support (MSI, MSI-X)
4669  *   - which can be user-defined (via MODULE_PARAM)
4670  * - Hardware queue count (num_*_queues)
4671  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4672  **/
4673 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4674 {
4675         int err;
4676
4677         /* Number of supported queues */
4678         err = ixgbe_set_num_queues(adapter);
4679         if (err)
4680                 return err;
4681
4682         err = ixgbe_set_interrupt_capability(adapter);
4683         if (err) {
4684                 e_dev_err("Unable to setup interrupt capabilities\n");
4685                 goto err_set_interrupt;
4686         }
4687
4688         err = ixgbe_alloc_q_vectors(adapter);
4689         if (err) {
4690                 e_dev_err("Unable to allocate memory for queue vectors\n");
4691                 goto err_alloc_q_vectors;
4692         }
4693
4694         err = ixgbe_alloc_queues(adapter);
4695         if (err) {
4696                 e_dev_err("Unable to allocate memory for queues\n");
4697                 goto err_alloc_queues;
4698         }
4699
4700         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4701                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4702                    adapter->num_rx_queues, adapter->num_tx_queues);
4703
4704         set_bit(__IXGBE_DOWN, &adapter->state);
4705
4706         return 0;
4707
4708 err_alloc_queues:
4709         ixgbe_free_q_vectors(adapter);
4710 err_alloc_q_vectors:
4711         ixgbe_reset_interrupt_capability(adapter);
4712 err_set_interrupt:
4713         return err;
4714 }
4715
4716 static void ring_free_rcu(struct rcu_head *head)
4717 {
4718         kfree(container_of(head, struct ixgbe_ring, rcu));
4719 }
4720
4721 /**
4722  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4723  * @adapter: board private structure to clear interrupt scheme on
4724  *
4725  * We go through and clear interrupt specific resources and reset the structure
4726  * to pre-load conditions
4727  **/
4728 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4729 {
4730         int i;
4731
4732         for (i = 0; i < adapter->num_tx_queues; i++) {
4733                 kfree(adapter->tx_ring[i]);
4734                 adapter->tx_ring[i] = NULL;
4735         }
4736         for (i = 0; i < adapter->num_rx_queues; i++) {
4737                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4738
4739                 /* ixgbe_get_stats64() might access this ring, we must wait
4740                  * a grace period before freeing it.
4741                  */
4742                 call_rcu(&ring->rcu, ring_free_rcu);
4743                 adapter->rx_ring[i] = NULL;
4744         }
4745
4746         ixgbe_free_q_vectors(adapter);
4747         ixgbe_reset_interrupt_capability(adapter);
4748 }
4749
4750 /**
4751  * ixgbe_sfp_timer - worker thread to find a missing module
4752  * @data: pointer to our adapter struct
4753  **/
4754 static void ixgbe_sfp_timer(unsigned long data)
4755 {
4756         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4757
4758         /*
4759          * Do the sfp_timer outside of interrupt context due to the
4760          * delays that sfp+ detection requires
4761          */
4762         schedule_work(&adapter->sfp_task);
4763 }
4764
4765 /**
4766  * ixgbe_sfp_task - worker thread to find a missing module
4767  * @work: pointer to work_struct containing our data
4768  **/
4769 static void ixgbe_sfp_task(struct work_struct *work)
4770 {
4771         struct ixgbe_adapter *adapter = container_of(work,
4772                                                      struct ixgbe_adapter,
4773                                                      sfp_task);
4774         struct ixgbe_hw *hw = &adapter->hw;
4775
4776         if ((hw->phy.type == ixgbe_phy_nl) &&
4777             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4778                 s32 ret = hw->phy.ops.identify_sfp(hw);
4779                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4780                         goto reschedule;
4781                 ret = hw->phy.ops.reset(hw);
4782                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4783                         e_dev_err("failed to initialize because an unsupported "
4784                                   "SFP+ module type was detected.\n");
4785                         e_dev_err("Reload the driver after installing a "
4786                                   "supported module.\n");
4787                         unregister_netdev(adapter->netdev);
4788                 } else {
4789                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4790                 }
4791                 /* don't need this routine any more */
4792                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4793         }
4794         return;
4795 reschedule:
4796         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4797                 mod_timer(&adapter->sfp_timer,
4798                           round_jiffies(jiffies + (2 * HZ)));
4799 }
4800
4801 /**
4802  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4803  * @adapter: board private structure to initialize
4804  *
4805  * ixgbe_sw_init initializes the Adapter private data structure.
4806  * Fields are initialized based on PCI device information and
4807  * OS network device settings (MTU size).
4808  **/
4809 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4810 {
4811         struct ixgbe_hw *hw = &adapter->hw;
4812         struct pci_dev *pdev = adapter->pdev;
4813         struct net_device *dev = adapter->netdev;
4814         unsigned int rss;
4815 #ifdef CONFIG_IXGBE_DCB
4816         int j;
4817         struct tc_configuration *tc;
4818 #endif
4819         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4820
4821         /* PCI config space info */
4822
4823         hw->vendor_id = pdev->vendor;
4824         hw->device_id = pdev->device;
4825         hw->revision_id = pdev->revision;
4826         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4827         hw->subsystem_device_id = pdev->subsystem_device;
4828
4829         /* Set capability flags */
4830         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4831         adapter->ring_feature[RING_F_RSS].indices = rss;
4832         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4833         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4834         if (hw->mac.type == ixgbe_mac_82598EB) {
4835                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4836                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4837                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4838         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4839                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4840                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4841                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4842                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4843                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4844                 if (dev->features & NETIF_F_NTUPLE) {
4845                         /* Flow Director perfect filter enabled */
4846                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4847                         adapter->atr_sample_rate = 0;
4848                         spin_lock_init(&adapter->fdir_perfect_lock);
4849                 } else {
4850                         /* Flow Director hash filters enabled */
4851                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4852                         adapter->atr_sample_rate = 20;
4853                 }
4854                 adapter->ring_feature[RING_F_FDIR].indices =
4855                                                          IXGBE_MAX_FDIR_INDICES;
4856                 adapter->fdir_pballoc = 0;
4857 #ifdef IXGBE_FCOE
4858                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4859                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4860                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4861 #ifdef CONFIG_IXGBE_DCB
4862                 /* Default traffic class to use for FCoE */
4863                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4864                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4865 #endif
4866 #endif /* IXGBE_FCOE */
4867         }
4868
4869 #ifdef CONFIG_IXGBE_DCB
4870         /* Configure DCB traffic classes */
4871         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4872                 tc = &adapter->dcb_cfg.tc_config[j];
4873                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4874                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4875                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4876                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4877                 tc->dcb_pfc = pfc_disabled;
4878         }
4879         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4880         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4881         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4882         adapter->dcb_cfg.pfc_mode_enable = false;
4883         adapter->dcb_cfg.round_robin_enable = false;
4884         adapter->dcb_set_bitmap = 0x00;
4885         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4886                            adapter->ring_feature[RING_F_DCB].indices);
4887
4888 #endif
4889
4890         /* default flow control settings */
4891         hw->fc.requested_mode = ixgbe_fc_full;
4892         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4893 #ifdef CONFIG_DCB
4894         adapter->last_lfc_mode = hw->fc.current_mode;
4895 #endif
4896         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4897         hw->fc.low_water = FC_LOW_WATER(max_frame);
4898         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4899         hw->fc.send_xon = true;
4900         hw->fc.disable_fc_autoneg = false;
4901
4902         /* enable itr by default in dynamic mode */
4903         adapter->rx_itr_setting = 1;
4904         adapter->rx_eitr_param = 20000;
4905         adapter->tx_itr_setting = 1;
4906         adapter->tx_eitr_param = 10000;
4907
4908         /* set defaults for eitr in MegaBytes */
4909         adapter->eitr_low = 10;
4910         adapter->eitr_high = 20;
4911
4912         /* set default ring sizes */
4913         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4914         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4915
4916         /* initialize eeprom parameters */
4917         if (ixgbe_init_eeprom_params_generic(hw)) {
4918                 e_dev_err("EEPROM initialization failed\n");
4919                 return -EIO;
4920         }
4921
4922         /* enable rx csum by default */
4923         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4924
4925         /* get assigned NUMA node */
4926         adapter->node = dev_to_node(&pdev->dev);
4927
4928         set_bit(__IXGBE_DOWN, &adapter->state);
4929
4930         return 0;
4931 }
4932
4933 /**
4934  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4935  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4936  *
4937  * Return 0 on success, negative on failure
4938  **/
4939 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4940 {
4941         struct device *dev = tx_ring->dev;
4942         int size;
4943
4944         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4945         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4946         if (!tx_ring->tx_buffer_info)
4947                 tx_ring->tx_buffer_info = vmalloc(size);
4948         if (!tx_ring->tx_buffer_info)
4949                 goto err;
4950         memset(tx_ring->tx_buffer_info, 0, size);
4951
4952         /* round up to nearest 4K */
4953         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4954         tx_ring->size = ALIGN(tx_ring->size, 4096);
4955
4956         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4957                                            &tx_ring->dma, GFP_KERNEL);
4958         if (!tx_ring->desc)
4959                 goto err;
4960
4961         tx_ring->next_to_use = 0;
4962         tx_ring->next_to_clean = 0;
4963         tx_ring->work_limit = tx_ring->count;
4964         return 0;
4965
4966 err:
4967         vfree(tx_ring->tx_buffer_info);
4968         tx_ring->tx_buffer_info = NULL;
4969         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
4970         return -ENOMEM;
4971 }
4972
4973 /**
4974  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4975  * @adapter: board private structure
4976  *
4977  * If this function returns with an error, then it's possible one or
4978  * more of the rings is populated (while the rest are not).  It is the
4979  * callers duty to clean those orphaned rings.
4980  *
4981  * Return 0 on success, negative on failure
4982  **/
4983 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4984 {
4985         int i, err = 0;
4986
4987         for (i = 0; i < adapter->num_tx_queues; i++) {
4988                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
4989                 if (!err)
4990                         continue;
4991                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
4992                 break;
4993         }
4994
4995         return err;
4996 }
4997
4998 /**
4999  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5000  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5001  *
5002  * Returns 0 on success, negative on failure
5003  **/
5004 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5005 {
5006         struct device *dev = rx_ring->dev;
5007         int size;
5008
5009         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5010         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5011         if (!rx_ring->rx_buffer_info)
5012                 rx_ring->rx_buffer_info = vmalloc(size);
5013         if (!rx_ring->rx_buffer_info)
5014                 goto err;
5015         memset(rx_ring->rx_buffer_info, 0, size);
5016
5017         /* Round up to nearest 4K */
5018         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5019         rx_ring->size = ALIGN(rx_ring->size, 4096);
5020
5021         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5022                                            &rx_ring->dma, GFP_KERNEL);
5023
5024         if (!rx_ring->desc)
5025                 goto err;
5026
5027         rx_ring->next_to_clean = 0;
5028         rx_ring->next_to_use = 0;
5029
5030         return 0;
5031 err:
5032         vfree(rx_ring->rx_buffer_info);
5033         rx_ring->rx_buffer_info = NULL;
5034         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5035         return -ENOMEM;
5036 }
5037
5038 /**
5039  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5040  * @adapter: board private structure
5041  *
5042  * If this function returns with an error, then it's possible one or
5043  * more of the rings is populated (while the rest are not).  It is the
5044  * callers duty to clean those orphaned rings.
5045  *
5046  * Return 0 on success, negative on failure
5047  **/
5048 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5049 {
5050         int i, err = 0;
5051
5052         for (i = 0; i < adapter->num_rx_queues; i++) {
5053                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5054                 if (!err)
5055                         continue;
5056                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5057                 break;
5058         }
5059
5060         return err;
5061 }
5062
5063 /**
5064  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5065  * @tx_ring: Tx descriptor ring for a specific queue
5066  *
5067  * Free all transmit software resources
5068  **/
5069 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5070 {
5071         ixgbe_clean_tx_ring(tx_ring);
5072
5073         vfree(tx_ring->tx_buffer_info);
5074         tx_ring->tx_buffer_info = NULL;
5075
5076         /* if not set, then don't free */
5077         if (!tx_ring->desc)
5078                 return;
5079
5080         dma_free_coherent(tx_ring->dev, tx_ring->size,
5081                           tx_ring->desc, tx_ring->dma);
5082
5083         tx_ring->desc = NULL;
5084 }
5085
5086 /**
5087  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5088  * @adapter: board private structure
5089  *
5090  * Free all transmit software resources
5091  **/
5092 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5093 {
5094         int i;
5095
5096         for (i = 0; i < adapter->num_tx_queues; i++)
5097                 if (adapter->tx_ring[i]->desc)
5098                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5099 }
5100
5101 /**
5102  * ixgbe_free_rx_resources - Free Rx Resources
5103  * @rx_ring: ring to clean the resources from
5104  *
5105  * Free all receive software resources
5106  **/
5107 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5108 {
5109         ixgbe_clean_rx_ring(rx_ring);
5110
5111         vfree(rx_ring->rx_buffer_info);
5112         rx_ring->rx_buffer_info = NULL;
5113
5114         /* if not set, then don't free */
5115         if (!rx_ring->desc)
5116                 return;
5117
5118         dma_free_coherent(rx_ring->dev, rx_ring->size,
5119                           rx_ring->desc, rx_ring->dma);
5120
5121         rx_ring->desc = NULL;
5122 }
5123
5124 /**
5125  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5126  * @adapter: board private structure
5127  *
5128  * Free all receive software resources
5129  **/
5130 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5131 {
5132         int i;
5133
5134         for (i = 0; i < adapter->num_rx_queues; i++)
5135                 if (adapter->rx_ring[i]->desc)
5136                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5137 }
5138
5139 /**
5140  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5141  * @netdev: network interface device structure
5142  * @new_mtu: new value for maximum frame size
5143  *
5144  * Returns 0 on success, negative on failure
5145  **/
5146 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5147 {
5148         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5149         struct ixgbe_hw *hw = &adapter->hw;
5150         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5151
5152         /* MTU < 68 is an error and causes problems on some kernels */
5153         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5154                 return -EINVAL;
5155
5156         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5157         /* must set new MTU before calling down or up */
5158         netdev->mtu = new_mtu;
5159
5160         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5161         hw->fc.low_water = FC_LOW_WATER(max_frame);
5162
5163         if (netif_running(netdev))
5164                 ixgbe_reinit_locked(adapter);
5165
5166         return 0;
5167 }
5168
5169 /**
5170  * ixgbe_open - Called when a network interface is made active
5171  * @netdev: network interface device structure
5172  *
5173  * Returns 0 on success, negative value on failure
5174  *
5175  * The open entry point is called when a network interface is made
5176  * active by the system (IFF_UP).  At this point all resources needed
5177  * for transmit and receive operations are allocated, the interrupt
5178  * handler is registered with the OS, the watchdog timer is started,
5179  * and the stack is notified that the interface is ready.
5180  **/
5181 static int ixgbe_open(struct net_device *netdev)
5182 {
5183         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5184         int err;
5185
5186         /* disallow open during test */
5187         if (test_bit(__IXGBE_TESTING, &adapter->state))
5188                 return -EBUSY;
5189
5190         netif_carrier_off(netdev);
5191
5192         /* allocate transmit descriptors */
5193         err = ixgbe_setup_all_tx_resources(adapter);
5194         if (err)
5195                 goto err_setup_tx;
5196
5197         /* allocate receive descriptors */
5198         err = ixgbe_setup_all_rx_resources(adapter);
5199         if (err)
5200                 goto err_setup_rx;
5201
5202         ixgbe_configure(adapter);
5203
5204         err = ixgbe_request_irq(adapter);
5205         if (err)
5206                 goto err_req_irq;
5207
5208         err = ixgbe_up_complete(adapter);
5209         if (err)
5210                 goto err_up;
5211
5212         netif_tx_start_all_queues(netdev);
5213
5214         return 0;
5215
5216 err_up:
5217         ixgbe_release_hw_control(adapter);
5218         ixgbe_free_irq(adapter);
5219 err_req_irq:
5220 err_setup_rx:
5221         ixgbe_free_all_rx_resources(adapter);
5222 err_setup_tx:
5223         ixgbe_free_all_tx_resources(adapter);
5224         ixgbe_reset(adapter);
5225
5226         return err;
5227 }
5228
5229 /**
5230  * ixgbe_close - Disables a network interface
5231  * @netdev: network interface device structure
5232  *
5233  * Returns 0, this is not allowed to fail
5234  *
5235  * The close entry point is called when an interface is de-activated
5236  * by the OS.  The hardware is still under the drivers control, but
5237  * needs to be disabled.  A global MAC reset is issued to stop the
5238  * hardware, and all transmit and receive resources are freed.
5239  **/
5240 static int ixgbe_close(struct net_device *netdev)
5241 {
5242         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5243
5244         ixgbe_down(adapter);
5245         ixgbe_free_irq(adapter);
5246
5247         ixgbe_free_all_tx_resources(adapter);
5248         ixgbe_free_all_rx_resources(adapter);
5249
5250         ixgbe_release_hw_control(adapter);
5251
5252         return 0;
5253 }
5254
5255 #ifdef CONFIG_PM
5256 static int ixgbe_resume(struct pci_dev *pdev)
5257 {
5258         struct net_device *netdev = pci_get_drvdata(pdev);
5259         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5260         u32 err;
5261
5262         pci_set_power_state(pdev, PCI_D0);
5263         pci_restore_state(pdev);
5264         /*
5265          * pci_restore_state clears dev->state_saved so call
5266          * pci_save_state to restore it.
5267          */
5268         pci_save_state(pdev);
5269
5270         err = pci_enable_device_mem(pdev);
5271         if (err) {
5272                 e_dev_err("Cannot enable PCI device from suspend\n");
5273                 return err;
5274         }
5275         pci_set_master(pdev);
5276
5277         pci_wake_from_d3(pdev, false);
5278
5279         err = ixgbe_init_interrupt_scheme(adapter);
5280         if (err) {
5281                 e_dev_err("Cannot initialize interrupts for device\n");
5282                 return err;
5283         }
5284
5285         ixgbe_reset(adapter);
5286
5287         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5288
5289         if (netif_running(netdev)) {
5290                 err = ixgbe_open(adapter->netdev);
5291                 if (err)
5292                         return err;
5293         }
5294
5295         netif_device_attach(netdev);
5296
5297         return 0;
5298 }
5299 #endif /* CONFIG_PM */
5300
5301 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5302 {
5303         struct net_device *netdev = pci_get_drvdata(pdev);
5304         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5305         struct ixgbe_hw *hw = &adapter->hw;
5306         u32 ctrl, fctrl;
5307         u32 wufc = adapter->wol;
5308 #ifdef CONFIG_PM
5309         int retval = 0;
5310 #endif
5311
5312         netif_device_detach(netdev);
5313
5314         if (netif_running(netdev)) {
5315                 ixgbe_down(adapter);
5316                 ixgbe_free_irq(adapter);
5317                 ixgbe_free_all_tx_resources(adapter);
5318                 ixgbe_free_all_rx_resources(adapter);
5319         }
5320
5321         ixgbe_clear_interrupt_scheme(adapter);
5322
5323 #ifdef CONFIG_PM
5324         retval = pci_save_state(pdev);
5325         if (retval)
5326                 return retval;
5327
5328 #endif
5329         if (wufc) {
5330                 ixgbe_set_rx_mode(netdev);
5331
5332                 /* turn on all-multi mode if wake on multicast is enabled */
5333                 if (wufc & IXGBE_WUFC_MC) {
5334                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5335                         fctrl |= IXGBE_FCTRL_MPE;
5336                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5337                 }
5338
5339                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5340                 ctrl |= IXGBE_CTRL_GIO_DIS;
5341                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5342
5343                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5344         } else {
5345                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5346                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5347         }
5348
5349         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5350                 pci_wake_from_d3(pdev, true);
5351         else
5352                 pci_wake_from_d3(pdev, false);
5353
5354         *enable_wake = !!wufc;
5355
5356         ixgbe_release_hw_control(adapter);
5357
5358         pci_disable_device(pdev);
5359
5360         return 0;
5361 }
5362
5363 #ifdef CONFIG_PM
5364 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5365 {
5366         int retval;
5367         bool wake;
5368
5369         retval = __ixgbe_shutdown(pdev, &wake);
5370         if (retval)
5371                 return retval;
5372
5373         if (wake) {
5374                 pci_prepare_to_sleep(pdev);
5375         } else {
5376                 pci_wake_from_d3(pdev, false);
5377                 pci_set_power_state(pdev, PCI_D3hot);
5378         }
5379
5380         return 0;
5381 }
5382 #endif /* CONFIG_PM */
5383
5384 static void ixgbe_shutdown(struct pci_dev *pdev)
5385 {
5386         bool wake;
5387
5388         __ixgbe_shutdown(pdev, &wake);
5389
5390         if (system_state == SYSTEM_POWER_OFF) {
5391                 pci_wake_from_d3(pdev, wake);
5392                 pci_set_power_state(pdev, PCI_D3hot);
5393         }
5394 }
5395
5396 /**
5397  * ixgbe_update_stats - Update the board statistics counters.
5398  * @adapter: board private structure
5399  **/
5400 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5401 {
5402         struct net_device *netdev = adapter->netdev;
5403         struct ixgbe_hw *hw = &adapter->hw;
5404         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5405         u64 total_mpc = 0;
5406         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5407         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5408         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5409         u64 bytes = 0, packets = 0;
5410
5411         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5412             test_bit(__IXGBE_RESETTING, &adapter->state))
5413                 return;
5414
5415         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5416                 u64 rsc_count = 0;
5417                 u64 rsc_flush = 0;
5418                 for (i = 0; i < 16; i++)
5419                         adapter->hw_rx_no_dma_resources +=
5420                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5421                 for (i = 0; i < adapter->num_rx_queues; i++) {
5422                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5423                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5424                 }
5425                 adapter->rsc_total_count = rsc_count;
5426                 adapter->rsc_total_flush = rsc_flush;
5427         }
5428
5429         for (i = 0; i < adapter->num_rx_queues; i++) {
5430                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5431                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5432                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5433                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5434                 bytes += rx_ring->stats.bytes;
5435                 packets += rx_ring->stats.packets;
5436         }
5437         adapter->non_eop_descs = non_eop_descs;
5438         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5439         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5440         netdev->stats.rx_bytes = bytes;
5441         netdev->stats.rx_packets = packets;
5442
5443         bytes = 0;
5444         packets = 0;
5445         /* gather some stats to the adapter struct that are per queue */
5446         for (i = 0; i < adapter->num_tx_queues; i++) {
5447                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5448                 restart_queue += tx_ring->tx_stats.restart_queue;
5449                 tx_busy += tx_ring->tx_stats.tx_busy;
5450                 bytes += tx_ring->stats.bytes;
5451                 packets += tx_ring->stats.packets;
5452         }
5453         adapter->restart_queue = restart_queue;
5454         adapter->tx_busy = tx_busy;
5455         netdev->stats.tx_bytes = bytes;
5456         netdev->stats.tx_packets = packets;
5457
5458         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5459         for (i = 0; i < 8; i++) {
5460                 /* for packet buffers not used, the register should read 0 */
5461                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5462                 missed_rx += mpc;
5463                 hwstats->mpc[i] += mpc;
5464                 total_mpc += hwstats->mpc[i];
5465                 if (hw->mac.type == ixgbe_mac_82598EB)
5466                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5467                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5468                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5469                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5470                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5471                 if (hw->mac.type == ixgbe_mac_82599EB) {
5472                         hwstats->pxonrxc[i] +=
5473                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5474                         hwstats->pxoffrxc[i] +=
5475                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5476                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5477                 } else {
5478                         hwstats->pxonrxc[i] +=
5479                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5480                         hwstats->pxoffrxc[i] +=
5481                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5482                 }
5483                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5484                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5485         }
5486         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5487         /* work around hardware counting issue */
5488         hwstats->gprc -= missed_rx;
5489
5490         /* 82598 hardware only has a 32 bit counter in the high register */
5491         if (hw->mac.type == ixgbe_mac_82599EB) {
5492                 u64 tmp;
5493                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5494                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5495                                                 /* 4 high bits of GORC */
5496                 hwstats->gorc += (tmp << 32);
5497                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5498                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5499                                                 /* 4 high bits of GOTC */
5500                 hwstats->gotc += (tmp << 32);
5501                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5502                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5503                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5504                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5505                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5506                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5507 #ifdef IXGBE_FCOE
5508                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5509                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5510                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5511                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5512                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5513                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5514 #endif /* IXGBE_FCOE */
5515         } else {
5516                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5517                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5518                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5519                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5520                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5521         }
5522         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5523         hwstats->bprc += bprc;
5524         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5525         if (hw->mac.type == ixgbe_mac_82598EB)
5526                 hwstats->mprc -= bprc;
5527         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5528         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5529         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5530         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5531         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5532         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5533         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5534         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5535         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5536         hwstats->lxontxc += lxon;
5537         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5538         hwstats->lxofftxc += lxoff;
5539         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5540         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5541         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5542         /*
5543          * 82598 errata - tx of flow control packets is included in tx counters
5544          */
5545         xon_off_tot = lxon + lxoff;
5546         hwstats->gptc -= xon_off_tot;
5547         hwstats->mptc -= xon_off_tot;
5548         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5549         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5550         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5551         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5552         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5553         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5554         hwstats->ptc64 -= xon_off_tot;
5555         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5556         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5557         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5558         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5559         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5560         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5561
5562         /* Fill out the OS statistics structure */
5563         netdev->stats.multicast = hwstats->mprc;
5564
5565         /* Rx Errors */
5566         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5567         netdev->stats.rx_dropped = 0;
5568         netdev->stats.rx_length_errors = hwstats->rlec;
5569         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5570         netdev->stats.rx_missed_errors = total_mpc;
5571 }
5572
5573 /**
5574  * ixgbe_watchdog - Timer Call-back
5575  * @data: pointer to adapter cast into an unsigned long
5576  **/
5577 static void ixgbe_watchdog(unsigned long data)
5578 {
5579         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5580         struct ixgbe_hw *hw = &adapter->hw;
5581         u64 eics = 0;
5582         int i;
5583
5584         /*
5585          *  Do the watchdog outside of interrupt context due to the lovely
5586          * delays that some of the newer hardware requires
5587          */
5588
5589         if (test_bit(__IXGBE_DOWN, &adapter->state))
5590                 goto watchdog_short_circuit;
5591
5592         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5593                 /*
5594                  * for legacy and MSI interrupts don't set any bits
5595                  * that are enabled for EIAM, because this operation
5596                  * would set *both* EIMS and EICS for any bit in EIAM
5597                  */
5598                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5599                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5600                 goto watchdog_reschedule;
5601         }
5602
5603         /* get one bit for every active tx/rx interrupt vector */
5604         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5605                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5606                 if (qv->rxr_count || qv->txr_count)
5607                         eics |= ((u64)1 << i);
5608         }
5609
5610         /* Cause software interrupt to ensure rx rings are cleaned */
5611         ixgbe_irq_rearm_queues(adapter, eics);
5612
5613 watchdog_reschedule:
5614         /* Reset the timer */
5615         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5616
5617 watchdog_short_circuit:
5618         schedule_work(&adapter->watchdog_task);
5619 }
5620
5621 /**
5622  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5623  * @work: pointer to work_struct containing our data
5624  **/
5625 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5626 {
5627         struct ixgbe_adapter *adapter = container_of(work,
5628                                                      struct ixgbe_adapter,
5629                                                      multispeed_fiber_task);
5630         struct ixgbe_hw *hw = &adapter->hw;
5631         u32 autoneg;
5632         bool negotiation;
5633
5634         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5635         autoneg = hw->phy.autoneg_advertised;
5636         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5637                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5638         hw->mac.autotry_restart = false;
5639         if (hw->mac.ops.setup_link)
5640                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5641         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5642         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5643 }
5644
5645 /**
5646  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5647  * @work: pointer to work_struct containing our data
5648  **/
5649 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5650 {
5651         struct ixgbe_adapter *adapter = container_of(work,
5652                                                      struct ixgbe_adapter,
5653                                                      sfp_config_module_task);
5654         struct ixgbe_hw *hw = &adapter->hw;
5655         u32 err;
5656
5657         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5658
5659         /* Time for electrical oscillations to settle down */
5660         msleep(100);
5661         err = hw->phy.ops.identify_sfp(hw);
5662
5663         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5664                 e_dev_err("failed to initialize because an unsupported SFP+ "
5665                           "module type was detected.\n");
5666                 e_dev_err("Reload the driver after installing a supported "
5667                           "module.\n");
5668                 unregister_netdev(adapter->netdev);
5669                 return;
5670         }
5671         hw->mac.ops.setup_sfp(hw);
5672
5673         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5674                 /* This will also work for DA Twinax connections */
5675                 schedule_work(&adapter->multispeed_fiber_task);
5676         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5677 }
5678
5679 /**
5680  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5681  * @work: pointer to work_struct containing our data
5682  **/
5683 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5684 {
5685         struct ixgbe_adapter *adapter = container_of(work,
5686                                                      struct ixgbe_adapter,
5687                                                      fdir_reinit_task);
5688         struct ixgbe_hw *hw = &adapter->hw;
5689         int i;
5690
5691         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5692                 for (i = 0; i < adapter->num_tx_queues; i++)
5693                         set_bit(__IXGBE_FDIR_INIT_DONE,
5694                                 &(adapter->tx_ring[i]->reinit_state));
5695         } else {
5696                 e_err(probe, "failed to finish FDIR re-initialization, "
5697                       "ignored adding FDIR ATR filters\n");
5698         }
5699         /* Done FDIR Re-initialization, enable transmits */
5700         netif_tx_start_all_queues(adapter->netdev);
5701 }
5702
5703 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5704
5705 /**
5706  * ixgbe_watchdog_task - worker thread to bring link up
5707  * @work: pointer to work_struct containing our data
5708  **/
5709 static void ixgbe_watchdog_task(struct work_struct *work)
5710 {
5711         struct ixgbe_adapter *adapter = container_of(work,
5712                                                      struct ixgbe_adapter,
5713                                                      watchdog_task);
5714         struct net_device *netdev = adapter->netdev;
5715         struct ixgbe_hw *hw = &adapter->hw;
5716         u32 link_speed;
5717         bool link_up;
5718         int i;
5719         struct ixgbe_ring *tx_ring;
5720         int some_tx_pending = 0;
5721
5722         mutex_lock(&ixgbe_watchdog_lock);
5723
5724         link_up = adapter->link_up;
5725         link_speed = adapter->link_speed;
5726
5727         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5728                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5729                 if (link_up) {
5730 #ifdef CONFIG_DCB
5731                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5732                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5733                                         hw->mac.ops.fc_enable(hw, i);
5734                         } else {
5735                                 hw->mac.ops.fc_enable(hw, 0);
5736                         }
5737 #else
5738                         hw->mac.ops.fc_enable(hw, 0);
5739 #endif
5740                 }
5741
5742                 if (link_up ||
5743                     time_after(jiffies, (adapter->link_check_timeout +
5744                                          IXGBE_TRY_LINK_TIMEOUT))) {
5745                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5746                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5747                 }
5748                 adapter->link_up = link_up;
5749                 adapter->link_speed = link_speed;
5750         }
5751
5752         if (link_up) {
5753                 if (!netif_carrier_ok(netdev)) {
5754                         bool flow_rx, flow_tx;
5755
5756                         if (hw->mac.type == ixgbe_mac_82599EB) {
5757                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5758                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5759                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5760                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5761                         } else {
5762                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5763                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5764                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5765                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5766                         }
5767
5768                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5769                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5770                                "10 Gbps" :
5771                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5772                                "1 Gbps" : "unknown speed")),
5773                                ((flow_rx && flow_tx) ? "RX/TX" :
5774                                (flow_rx ? "RX" :
5775                                (flow_tx ? "TX" : "None"))));
5776
5777                         netif_carrier_on(netdev);
5778                 } else {
5779                         /* Force detection of hung controller */
5780                         adapter->detect_tx_hung = true;
5781                 }
5782         } else {
5783                 adapter->link_up = false;
5784                 adapter->link_speed = 0;
5785                 if (netif_carrier_ok(netdev)) {
5786                         e_info(drv, "NIC Link is Down\n");
5787                         netif_carrier_off(netdev);
5788                 }
5789         }
5790
5791         if (!netif_carrier_ok(netdev)) {
5792                 for (i = 0; i < adapter->num_tx_queues; i++) {
5793                         tx_ring = adapter->tx_ring[i];
5794                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5795                                 some_tx_pending = 1;
5796                                 break;
5797                         }
5798                 }
5799
5800                 if (some_tx_pending) {
5801                         /* We've lost link, so the controller stops DMA,
5802                          * but we've got queued Tx work that's never going
5803                          * to get done, so reset controller to flush Tx.
5804                          * (Do the reset outside of interrupt context).
5805                          */
5806                          schedule_work(&adapter->reset_task);
5807                 }
5808         }
5809
5810         ixgbe_update_stats(adapter);
5811         mutex_unlock(&ixgbe_watchdog_lock);
5812 }
5813
5814 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5815                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5816                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5817 {
5818         struct ixgbe_adv_tx_context_desc *context_desc;
5819         unsigned int i;
5820         int err;
5821         struct ixgbe_tx_buffer *tx_buffer_info;
5822         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5823         u32 mss_l4len_idx, l4len;
5824
5825         if (skb_is_gso(skb)) {
5826                 if (skb_header_cloned(skb)) {
5827                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5828                         if (err)
5829                                 return err;
5830                 }
5831                 l4len = tcp_hdrlen(skb);
5832                 *hdr_len += l4len;
5833
5834                 if (protocol == htons(ETH_P_IP)) {
5835                         struct iphdr *iph = ip_hdr(skb);
5836                         iph->tot_len = 0;
5837                         iph->check = 0;
5838                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5839                                                                  iph->daddr, 0,
5840                                                                  IPPROTO_TCP,
5841                                                                  0);
5842                 } else if (skb_is_gso_v6(skb)) {
5843                         ipv6_hdr(skb)->payload_len = 0;
5844                         tcp_hdr(skb)->check =
5845                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5846                                              &ipv6_hdr(skb)->daddr,
5847                                              0, IPPROTO_TCP, 0);
5848                 }
5849
5850                 i = tx_ring->next_to_use;
5851
5852                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5853                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5854
5855                 /* VLAN MACLEN IPLEN */
5856                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5857                         vlan_macip_lens |=
5858                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5859                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5860                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5861                 *hdr_len += skb_network_offset(skb);
5862                 vlan_macip_lens |=
5863                     (skb_transport_header(skb) - skb_network_header(skb));
5864                 *hdr_len +=
5865                     (skb_transport_header(skb) - skb_network_header(skb));
5866                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5867                 context_desc->seqnum_seed = 0;
5868
5869                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5870                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5871                                    IXGBE_ADVTXD_DTYP_CTXT);
5872
5873                 if (protocol == htons(ETH_P_IP))
5874                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5875                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5876                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5877
5878                 /* MSS L4LEN IDX */
5879                 mss_l4len_idx =
5880                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5881                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5882                 /* use index 1 for TSO */
5883                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5884                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5885
5886                 tx_buffer_info->time_stamp = jiffies;
5887                 tx_buffer_info->next_to_watch = i;
5888
5889                 i++;
5890                 if (i == tx_ring->count)
5891                         i = 0;
5892                 tx_ring->next_to_use = i;
5893
5894                 return true;
5895         }
5896         return false;
5897 }
5898
5899 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5900                       __be16 protocol)
5901 {
5902         u32 rtn = 0;
5903
5904         switch (protocol) {
5905         case cpu_to_be16(ETH_P_IP):
5906                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5907                 switch (ip_hdr(skb)->protocol) {
5908                 case IPPROTO_TCP:
5909                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5910                         break;
5911                 case IPPROTO_SCTP:
5912                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5913                         break;
5914                 }
5915                 break;
5916         case cpu_to_be16(ETH_P_IPV6):
5917                 /* XXX what about other V6 headers?? */
5918                 switch (ipv6_hdr(skb)->nexthdr) {
5919                 case IPPROTO_TCP:
5920                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5921                         break;
5922                 case IPPROTO_SCTP:
5923                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5924                         break;
5925                 }
5926                 break;
5927         default:
5928                 if (unlikely(net_ratelimit()))
5929                         e_warn(probe, "partial checksum but proto=%x!\n",
5930                                protocol);
5931                 break;
5932         }
5933
5934         return rtn;
5935 }
5936
5937 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5938                           struct ixgbe_ring *tx_ring,
5939                           struct sk_buff *skb, u32 tx_flags,
5940                           __be16 protocol)
5941 {
5942         struct ixgbe_adv_tx_context_desc *context_desc;
5943         unsigned int i;
5944         struct ixgbe_tx_buffer *tx_buffer_info;
5945         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5946
5947         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5948             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5949                 i = tx_ring->next_to_use;
5950                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5951                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5952
5953                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5954                         vlan_macip_lens |=
5955                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5956                 vlan_macip_lens |= (skb_network_offset(skb) <<
5957                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5958                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5959                         vlan_macip_lens |= (skb_transport_header(skb) -
5960                                             skb_network_header(skb));
5961
5962                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5963                 context_desc->seqnum_seed = 0;
5964
5965                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5966                                     IXGBE_ADVTXD_DTYP_CTXT);
5967
5968                 if (skb->ip_summed == CHECKSUM_PARTIAL)
5969                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
5970
5971                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5972                 /* use index zero for tx checksum offload */
5973                 context_desc->mss_l4len_idx = 0;
5974
5975                 tx_buffer_info->time_stamp = jiffies;
5976                 tx_buffer_info->next_to_watch = i;
5977
5978                 i++;
5979                 if (i == tx_ring->count)
5980                         i = 0;
5981                 tx_ring->next_to_use = i;
5982
5983                 return true;
5984         }
5985
5986         return false;
5987 }
5988
5989 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
5990                         struct ixgbe_ring *tx_ring,
5991                         struct sk_buff *skb, u32 tx_flags,
5992                         unsigned int first, const u8 hdr_len)
5993 {
5994         struct device *dev = tx_ring->dev;
5995         struct ixgbe_tx_buffer *tx_buffer_info;
5996         unsigned int len;
5997         unsigned int total = skb->len;
5998         unsigned int offset = 0, size, count = 0, i;
5999         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6000         unsigned int f;
6001         unsigned int bytecount = skb->len;
6002         u16 gso_segs = 1;
6003
6004         i = tx_ring->next_to_use;
6005
6006         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6007                 /* excluding fcoe_crc_eof for FCoE */
6008                 total -= sizeof(struct fcoe_crc_eof);
6009
6010         len = min(skb_headlen(skb), total);
6011         while (len) {
6012                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6013                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6014
6015                 tx_buffer_info->length = size;
6016                 tx_buffer_info->mapped_as_page = false;
6017                 tx_buffer_info->dma = dma_map_single(dev,
6018                                                      skb->data + offset,
6019                                                      size, DMA_TO_DEVICE);
6020                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6021                         goto dma_error;
6022                 tx_buffer_info->time_stamp = jiffies;
6023                 tx_buffer_info->next_to_watch = i;
6024
6025                 len -= size;
6026                 total -= size;
6027                 offset += size;
6028                 count++;
6029
6030                 if (len) {
6031                         i++;
6032                         if (i == tx_ring->count)
6033                                 i = 0;
6034                 }
6035         }
6036
6037         for (f = 0; f < nr_frags; f++) {
6038                 struct skb_frag_struct *frag;
6039
6040                 frag = &skb_shinfo(skb)->frags[f];
6041                 len = min((unsigned int)frag->size, total);
6042                 offset = frag->page_offset;
6043
6044                 while (len) {
6045                         i++;
6046                         if (i == tx_ring->count)
6047                                 i = 0;
6048
6049                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6050                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6051
6052                         tx_buffer_info->length = size;
6053                         tx_buffer_info->dma = dma_map_page(dev,
6054                                                            frag->page,
6055                                                            offset, size,
6056                                                            DMA_TO_DEVICE);
6057                         tx_buffer_info->mapped_as_page = true;
6058                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6059                                 goto dma_error;
6060                         tx_buffer_info->time_stamp = jiffies;
6061                         tx_buffer_info->next_to_watch = i;
6062
6063                         len -= size;
6064                         total -= size;
6065                         offset += size;
6066                         count++;
6067                 }
6068                 if (total == 0)
6069                         break;
6070         }
6071
6072         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6073                 gso_segs = skb_shinfo(skb)->gso_segs;
6074 #ifdef IXGBE_FCOE
6075         /* adjust for FCoE Sequence Offload */
6076         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6077                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6078                                         skb_shinfo(skb)->gso_size);
6079 #endif /* IXGBE_FCOE */
6080         bytecount += (gso_segs - 1) * hdr_len;
6081
6082         /* multiply data chunks by size of headers */
6083         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6084         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6085         tx_ring->tx_buffer_info[i].skb = skb;
6086         tx_ring->tx_buffer_info[first].next_to_watch = i;
6087
6088         return count;
6089
6090 dma_error:
6091         e_dev_err("TX DMA map failed\n");
6092
6093         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6094         tx_buffer_info->dma = 0;
6095         tx_buffer_info->time_stamp = 0;
6096         tx_buffer_info->next_to_watch = 0;
6097         if (count)
6098                 count--;
6099
6100         /* clear timestamp and dma mappings for remaining portion of packet */
6101         while (count--) {
6102                 if (i == 0)
6103                         i += tx_ring->count;
6104                 i--;
6105                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6106                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6107         }
6108
6109         return 0;
6110 }
6111
6112 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6113                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6114 {
6115         union ixgbe_adv_tx_desc *tx_desc = NULL;
6116         struct ixgbe_tx_buffer *tx_buffer_info;
6117         u32 olinfo_status = 0, cmd_type_len = 0;
6118         unsigned int i;
6119         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6120
6121         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6122
6123         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6124
6125         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6126                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6127
6128         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6129                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6130
6131                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6132                                  IXGBE_ADVTXD_POPTS_SHIFT;
6133
6134                 /* use index 1 context for tso */
6135                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6136                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6137                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6138                                          IXGBE_ADVTXD_POPTS_SHIFT;
6139
6140         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6141                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6142                                  IXGBE_ADVTXD_POPTS_SHIFT;
6143
6144         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6145                 olinfo_status |= IXGBE_ADVTXD_CC;
6146                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6147                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6148                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6149         }
6150
6151         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6152
6153         i = tx_ring->next_to_use;
6154         while (count--) {
6155                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6156                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6157                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6158                 tx_desc->read.cmd_type_len =
6159                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6160                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6161                 i++;
6162                 if (i == tx_ring->count)
6163                         i = 0;
6164         }
6165
6166         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6167
6168         /*
6169          * Force memory writes to complete before letting h/w
6170          * know there are new descriptors to fetch.  (Only
6171          * applicable for weak-ordered memory model archs,
6172          * such as IA-64).
6173          */
6174         wmb();
6175
6176         tx_ring->next_to_use = i;
6177         writel(i, tx_ring->tail);
6178 }
6179
6180 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6181                       int queue, u32 tx_flags, __be16 protocol)
6182 {
6183         struct ixgbe_atr_input atr_input;
6184         struct tcphdr *th;
6185         struct iphdr *iph = ip_hdr(skb);
6186         struct ethhdr *eth = (struct ethhdr *)skb->data;
6187         u16 vlan_id, src_port, dst_port, flex_bytes;
6188         u32 src_ipv4_addr, dst_ipv4_addr;
6189         u8 l4type = 0;
6190
6191         /* Right now, we support IPv4 only */
6192         if (protocol != htons(ETH_P_IP))
6193                 return;
6194         /* check if we're UDP or TCP */
6195         if (iph->protocol == IPPROTO_TCP) {
6196                 th = tcp_hdr(skb);
6197                 src_port = th->source;
6198                 dst_port = th->dest;
6199                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6200                 /* l4type IPv4 type is 0, no need to assign */
6201         } else {
6202                 /* Unsupported L4 header, just bail here */
6203                 return;
6204         }
6205
6206         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6207
6208         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6209                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6210         src_ipv4_addr = iph->saddr;
6211         dst_ipv4_addr = iph->daddr;
6212         flex_bytes = eth->h_proto;
6213
6214         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6215         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6216         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6217         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6218         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6219         /* src and dst are inverted, think how the receiver sees them */
6220         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6221         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6222
6223         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6224         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6225 }
6226
6227 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6228 {
6229         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6230         /* Herbert's original patch had:
6231          *  smp_mb__after_netif_stop_queue();
6232          * but since that doesn't exist yet, just open code it. */
6233         smp_mb();
6234
6235         /* We need to check again in a case another CPU has just
6236          * made room available. */
6237         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6238                 return -EBUSY;
6239
6240         /* A reprieve! - use start_queue because it doesn't call schedule */
6241         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6242         ++tx_ring->tx_stats.restart_queue;
6243         return 0;
6244 }
6245
6246 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6247 {
6248         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6249                 return 0;
6250         return __ixgbe_maybe_stop_tx(tx_ring, size);
6251 }
6252
6253 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6254 {
6255         struct ixgbe_adapter *adapter = netdev_priv(dev);
6256         int txq = smp_processor_id();
6257 #ifdef IXGBE_FCOE
6258         __be16 protocol;
6259
6260         protocol = vlan_get_protocol(skb);
6261
6262         if ((protocol == htons(ETH_P_FCOE)) ||
6263             (protocol == htons(ETH_P_FIP))) {
6264                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6265                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6266                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6267                         return txq;
6268 #ifdef CONFIG_IXGBE_DCB
6269                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6270                         txq = adapter->fcoe.up;
6271                         return txq;
6272 #endif
6273                 }
6274         }
6275 #endif
6276
6277         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6278                 while (unlikely(txq >= dev->real_num_tx_queues))
6279                         txq -= dev->real_num_tx_queues;
6280                 return txq;
6281         }
6282
6283         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6284                 if (skb->priority == TC_PRIO_CONTROL)
6285                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6286                 else
6287                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6288                                >> 13;
6289                 return txq;
6290         }
6291
6292         return skb_tx_hash(dev, skb);
6293 }
6294
6295 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6296                           struct ixgbe_adapter *adapter,
6297                           struct ixgbe_ring *tx_ring)
6298 {
6299         struct net_device *netdev = tx_ring->netdev;
6300         struct netdev_queue *txq;
6301         unsigned int first;
6302         unsigned int tx_flags = 0;
6303         u8 hdr_len = 0;
6304         int tso;
6305         int count = 0;
6306         unsigned int f;
6307         __be16 protocol;
6308
6309         protocol = vlan_get_protocol(skb);
6310
6311         if (vlan_tx_tag_present(skb)) {
6312                 tx_flags |= vlan_tx_tag_get(skb);
6313                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6314                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6315                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6316                 }
6317                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6318                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6319         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6320                    skb->priority != TC_PRIO_CONTROL) {
6321                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6322                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6323                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6324         }
6325
6326 #ifdef IXGBE_FCOE
6327         /* for FCoE with DCB, we force the priority to what
6328          * was specified by the switch */
6329         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6330             (protocol == htons(ETH_P_FCOE) ||
6331              protocol == htons(ETH_P_FIP))) {
6332 #ifdef CONFIG_IXGBE_DCB
6333                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6334                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6335                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6336                         tx_flags |= ((adapter->fcoe.up << 13)
6337                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6338                 }
6339 #endif
6340                 /* flag for FCoE offloads */
6341                 if (protocol == htons(ETH_P_FCOE))
6342                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6343         }
6344 #endif
6345
6346         /* four things can cause us to need a context descriptor */
6347         if (skb_is_gso(skb) ||
6348             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6349             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6350             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6351                 count++;
6352
6353         count += TXD_USE_COUNT(skb_headlen(skb));
6354         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6355                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6356
6357         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6358                 tx_ring->tx_stats.tx_busy++;
6359                 return NETDEV_TX_BUSY;
6360         }
6361
6362         first = tx_ring->next_to_use;
6363         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6364 #ifdef IXGBE_FCOE
6365                 /* setup tx offload for FCoE */
6366                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6367                 if (tso < 0) {
6368                         dev_kfree_skb_any(skb);
6369                         return NETDEV_TX_OK;
6370                 }
6371                 if (tso)
6372                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6373 #endif /* IXGBE_FCOE */
6374         } else {
6375                 if (protocol == htons(ETH_P_IP))
6376                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6377                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6378                                 protocol);
6379                 if (tso < 0) {
6380                         dev_kfree_skb_any(skb);
6381                         return NETDEV_TX_OK;
6382                 }
6383
6384                 if (tso)
6385                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6386                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6387                                        protocol) &&
6388                          (skb->ip_summed == CHECKSUM_PARTIAL))
6389                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6390         }
6391
6392         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6393         if (count) {
6394                 /* add the ATR filter if ATR is on */
6395                 if (tx_ring->atr_sample_rate) {
6396                         ++tx_ring->atr_count;
6397                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6398                              test_bit(__IXGBE_FDIR_INIT_DONE,
6399                                       &tx_ring->reinit_state)) {
6400                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6401                                           tx_flags, protocol);
6402                                 tx_ring->atr_count = 0;
6403                         }
6404                 }
6405                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6406                 txq->tx_bytes += skb->len;
6407                 txq->tx_packets++;
6408                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6409                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6410
6411         } else {
6412                 dev_kfree_skb_any(skb);
6413                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6414                 tx_ring->next_to_use = first;
6415         }
6416
6417         return NETDEV_TX_OK;
6418 }
6419
6420 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6421 {
6422         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6423         struct ixgbe_ring *tx_ring;
6424
6425         tx_ring = adapter->tx_ring[skb->queue_mapping];
6426         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6427 }
6428
6429 /**
6430  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6431  * @netdev: network interface device structure
6432  * @p: pointer to an address structure
6433  *
6434  * Returns 0 on success, negative on failure
6435  **/
6436 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6437 {
6438         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6439         struct ixgbe_hw *hw = &adapter->hw;
6440         struct sockaddr *addr = p;
6441
6442         if (!is_valid_ether_addr(addr->sa_data))
6443                 return -EADDRNOTAVAIL;
6444
6445         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6446         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6447
6448         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6449                             IXGBE_RAH_AV);
6450
6451         return 0;
6452 }
6453
6454 static int
6455 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6456 {
6457         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6458         struct ixgbe_hw *hw = &adapter->hw;
6459         u16 value;
6460         int rc;
6461
6462         if (prtad != hw->phy.mdio.prtad)
6463                 return -EINVAL;
6464         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6465         if (!rc)
6466                 rc = value;
6467         return rc;
6468 }
6469
6470 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6471                             u16 addr, u16 value)
6472 {
6473         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6474         struct ixgbe_hw *hw = &adapter->hw;
6475
6476         if (prtad != hw->phy.mdio.prtad)
6477                 return -EINVAL;
6478         return hw->phy.ops.write_reg(hw, addr, devad, value);
6479 }
6480
6481 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6482 {
6483         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6484
6485         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6486 }
6487
6488 /**
6489  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6490  * netdev->dev_addrs
6491  * @netdev: network interface device structure
6492  *
6493  * Returns non-zero on failure
6494  **/
6495 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6496 {
6497         int err = 0;
6498         struct ixgbe_adapter *adapter = netdev_priv(dev);
6499         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6500
6501         if (is_valid_ether_addr(mac->san_addr)) {
6502                 rtnl_lock();
6503                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6504                 rtnl_unlock();
6505         }
6506         return err;
6507 }
6508
6509 /**
6510  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6511  * netdev->dev_addrs
6512  * @netdev: network interface device structure
6513  *
6514  * Returns non-zero on failure
6515  **/
6516 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6517 {
6518         int err = 0;
6519         struct ixgbe_adapter *adapter = netdev_priv(dev);
6520         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6521
6522         if (is_valid_ether_addr(mac->san_addr)) {
6523                 rtnl_lock();
6524                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6525                 rtnl_unlock();
6526         }
6527         return err;
6528 }
6529
6530 #ifdef CONFIG_NET_POLL_CONTROLLER
6531 /*
6532  * Polling 'interrupt' - used by things like netconsole to send skbs
6533  * without having to re-enable interrupts. It's not called while
6534  * the interrupt routine is executing.
6535  */
6536 static void ixgbe_netpoll(struct net_device *netdev)
6537 {
6538         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6539         int i;
6540
6541         /* if interface is down do nothing */
6542         if (test_bit(__IXGBE_DOWN, &adapter->state))
6543                 return;
6544
6545         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6546         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6547                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6548                 for (i = 0; i < num_q_vectors; i++) {
6549                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6550                         ixgbe_msix_clean_many(0, q_vector);
6551                 }
6552         } else {
6553                 ixgbe_intr(adapter->pdev->irq, netdev);
6554         }
6555         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6556 }
6557 #endif
6558
6559 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6560                                                    struct rtnl_link_stats64 *stats)
6561 {
6562         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6563         int i;
6564
6565         /* accurate rx/tx bytes/packets stats */
6566         dev_txq_stats_fold(netdev, stats);
6567         rcu_read_lock();
6568         for (i = 0; i < adapter->num_rx_queues; i++) {
6569                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6570                 u64 bytes, packets;
6571                 unsigned int start;
6572
6573                 if (ring) {
6574                         do {
6575                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6576                                 packets = ring->stats.packets;
6577                                 bytes   = ring->stats.bytes;
6578                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6579                         stats->rx_packets += packets;
6580                         stats->rx_bytes   += bytes;
6581                 }
6582         }
6583         rcu_read_unlock();
6584         /* following stats updated by ixgbe_watchdog_task() */
6585         stats->multicast        = netdev->stats.multicast;
6586         stats->rx_errors        = netdev->stats.rx_errors;
6587         stats->rx_length_errors = netdev->stats.rx_length_errors;
6588         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6589         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6590         return stats;
6591 }
6592
6593
6594 static const struct net_device_ops ixgbe_netdev_ops = {
6595         .ndo_open               = ixgbe_open,
6596         .ndo_stop               = ixgbe_close,
6597         .ndo_start_xmit         = ixgbe_xmit_frame,
6598         .ndo_select_queue       = ixgbe_select_queue,
6599         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6600         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6601         .ndo_validate_addr      = eth_validate_addr,
6602         .ndo_set_mac_address    = ixgbe_set_mac,
6603         .ndo_change_mtu         = ixgbe_change_mtu,
6604         .ndo_tx_timeout         = ixgbe_tx_timeout,
6605         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6606         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6607         .ndo_do_ioctl           = ixgbe_ioctl,
6608         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6609         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6610         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6611         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6612         .ndo_get_stats64        = ixgbe_get_stats64,
6613 #ifdef CONFIG_NET_POLL_CONTROLLER
6614         .ndo_poll_controller    = ixgbe_netpoll,
6615 #endif
6616 #ifdef IXGBE_FCOE
6617         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6618         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6619         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6620         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6621         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6622 #endif /* IXGBE_FCOE */
6623 };
6624
6625 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6626                            const struct ixgbe_info *ii)
6627 {
6628 #ifdef CONFIG_PCI_IOV
6629         struct ixgbe_hw *hw = &adapter->hw;
6630         int err;
6631
6632         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6633                 return;
6634
6635         /* The 82599 supports up to 64 VFs per physical function
6636          * but this implementation limits allocation to 63 so that
6637          * basic networking resources are still available to the
6638          * physical function
6639          */
6640         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6641         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6642         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6643         if (err) {
6644                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6645                 goto err_novfs;
6646         }
6647         /* If call to enable VFs succeeded then allocate memory
6648          * for per VF control structures.
6649          */
6650         adapter->vfinfo =
6651                 kcalloc(adapter->num_vfs,
6652                         sizeof(struct vf_data_storage), GFP_KERNEL);
6653         if (adapter->vfinfo) {
6654                 /* Now that we're sure SR-IOV is enabled
6655                  * and memory allocated set up the mailbox parameters
6656                  */
6657                 ixgbe_init_mbx_params_pf(hw);
6658                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6659                        sizeof(hw->mbx.ops));
6660
6661                 /* Disable RSC when in SR-IOV mode */
6662                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6663                                      IXGBE_FLAG2_RSC_ENABLED);
6664                 return;
6665         }
6666
6667         /* Oh oh */
6668         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6669               "SRIOV disabled\n");
6670         pci_disable_sriov(adapter->pdev);
6671
6672 err_novfs:
6673         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6674         adapter->num_vfs = 0;
6675 #endif /* CONFIG_PCI_IOV */
6676 }
6677
6678 /**
6679  * ixgbe_probe - Device Initialization Routine
6680  * @pdev: PCI device information struct
6681  * @ent: entry in ixgbe_pci_tbl
6682  *
6683  * Returns 0 on success, negative on failure
6684  *
6685  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6686  * The OS initialization, configuring of the adapter private structure,
6687  * and a hardware reset occur.
6688  **/
6689 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6690                                  const struct pci_device_id *ent)
6691 {
6692         struct net_device *netdev;
6693         struct ixgbe_adapter *adapter = NULL;
6694         struct ixgbe_hw *hw;
6695         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6696         static int cards_found;
6697         int i, err, pci_using_dac;
6698         unsigned int indices = num_possible_cpus();
6699 #ifdef IXGBE_FCOE
6700         u16 device_caps;
6701 #endif
6702         u32 part_num, eec;
6703
6704         /* Catch broken hardware that put the wrong VF device ID in
6705          * the PCIe SR-IOV capability.
6706          */
6707         if (pdev->is_virtfn) {
6708                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6709                      pci_name(pdev), pdev->vendor, pdev->device);
6710                 return -EINVAL;
6711         }
6712
6713         err = pci_enable_device_mem(pdev);
6714         if (err)
6715                 return err;
6716
6717         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6718             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6719                 pci_using_dac = 1;
6720         } else {
6721                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6722                 if (err) {
6723                         err = dma_set_coherent_mask(&pdev->dev,
6724                                                     DMA_BIT_MASK(32));
6725                         if (err) {
6726                                 dev_err(&pdev->dev,
6727                                         "No usable DMA configuration, aborting\n");
6728                                 goto err_dma;
6729                         }
6730                 }
6731                 pci_using_dac = 0;
6732         }
6733
6734         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6735                                            IORESOURCE_MEM), ixgbe_driver_name);
6736         if (err) {
6737                 dev_err(&pdev->dev,
6738                         "pci_request_selected_regions failed 0x%x\n", err);
6739                 goto err_pci_reg;
6740         }
6741
6742         pci_enable_pcie_error_reporting(pdev);
6743
6744         pci_set_master(pdev);
6745         pci_save_state(pdev);
6746
6747         if (ii->mac == ixgbe_mac_82598EB)
6748                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6749         else
6750                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6751
6752         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6753 #ifdef IXGBE_FCOE
6754         indices += min_t(unsigned int, num_possible_cpus(),
6755                          IXGBE_MAX_FCOE_INDICES);
6756 #endif
6757         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6758         if (!netdev) {
6759                 err = -ENOMEM;
6760                 goto err_alloc_etherdev;
6761         }
6762
6763         SET_NETDEV_DEV(netdev, &pdev->dev);
6764
6765         pci_set_drvdata(pdev, netdev);
6766         adapter = netdev_priv(netdev);
6767
6768         adapter->netdev = netdev;
6769         adapter->pdev = pdev;
6770         hw = &adapter->hw;
6771         hw->back = adapter;
6772         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6773
6774         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6775                               pci_resource_len(pdev, 0));
6776         if (!hw->hw_addr) {
6777                 err = -EIO;
6778                 goto err_ioremap;
6779         }
6780
6781         for (i = 1; i <= 5; i++) {
6782                 if (pci_resource_len(pdev, i) == 0)
6783                         continue;
6784         }
6785
6786         netdev->netdev_ops = &ixgbe_netdev_ops;
6787         ixgbe_set_ethtool_ops(netdev);
6788         netdev->watchdog_timeo = 5 * HZ;
6789         strcpy(netdev->name, pci_name(pdev));
6790
6791         adapter->bd_number = cards_found;
6792
6793         /* Setup hw api */
6794         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6795         hw->mac.type  = ii->mac;
6796
6797         /* EEPROM */
6798         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6799         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6800         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6801         if (!(eec & (1 << 8)))
6802                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6803
6804         /* PHY */
6805         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6806         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6807         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6808         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6809         hw->phy.mdio.mmds = 0;
6810         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6811         hw->phy.mdio.dev = netdev;
6812         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6813         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6814
6815         /* set up this timer and work struct before calling get_invariants
6816          * which might start the timer
6817          */
6818         init_timer(&adapter->sfp_timer);
6819         adapter->sfp_timer.function = ixgbe_sfp_timer;
6820         adapter->sfp_timer.data = (unsigned long) adapter;
6821
6822         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6823
6824         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6825         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6826
6827         /* a new SFP+ module arrival, called from GPI SDP2 context */
6828         INIT_WORK(&adapter->sfp_config_module_task,
6829                   ixgbe_sfp_config_module_task);
6830
6831         ii->get_invariants(hw);
6832
6833         /* setup the private structure */
6834         err = ixgbe_sw_init(adapter);
6835         if (err)
6836                 goto err_sw_init;
6837
6838         /* Make it possible the adapter to be woken up via WOL */
6839         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6840                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6841
6842         /*
6843          * If there is a fan on this device and it has failed log the
6844          * failure.
6845          */
6846         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6847                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6848                 if (esdp & IXGBE_ESDP_SDP1)
6849                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6850         }
6851
6852         /* reset_hw fills in the perm_addr as well */
6853         hw->phy.reset_if_overtemp = true;
6854         err = hw->mac.ops.reset_hw(hw);
6855         hw->phy.reset_if_overtemp = false;
6856         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6857             hw->mac.type == ixgbe_mac_82598EB) {
6858                 /*
6859                  * Start a kernel thread to watch for a module to arrive.
6860                  * Only do this for 82598, since 82599 will generate
6861                  * interrupts on module arrival.
6862                  */
6863                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6864                 mod_timer(&adapter->sfp_timer,
6865                           round_jiffies(jiffies + (2 * HZ)));
6866                 err = 0;
6867         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6868                 e_dev_err("failed to initialize because an unsupported SFP+ "
6869                           "module type was detected.\n");
6870                 e_dev_err("Reload the driver after installing a supported "
6871                           "module.\n");
6872                 goto err_sw_init;
6873         } else if (err) {
6874                 e_dev_err("HW Init failed: %d\n", err);
6875                 goto err_sw_init;
6876         }
6877
6878         ixgbe_probe_vf(adapter, ii);
6879
6880         netdev->features = NETIF_F_SG |
6881                            NETIF_F_IP_CSUM |
6882                            NETIF_F_HW_VLAN_TX |
6883                            NETIF_F_HW_VLAN_RX |
6884                            NETIF_F_HW_VLAN_FILTER;
6885
6886         netdev->features |= NETIF_F_IPV6_CSUM;
6887         netdev->features |= NETIF_F_TSO;
6888         netdev->features |= NETIF_F_TSO6;
6889         netdev->features |= NETIF_F_GRO;
6890
6891         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6892                 netdev->features |= NETIF_F_SCTP_CSUM;
6893
6894         netdev->vlan_features |= NETIF_F_TSO;
6895         netdev->vlan_features |= NETIF_F_TSO6;
6896         netdev->vlan_features |= NETIF_F_IP_CSUM;
6897         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6898         netdev->vlan_features |= NETIF_F_SG;
6899
6900         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6901                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6902                                     IXGBE_FLAG_DCB_ENABLED);
6903         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6904                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6905
6906 #ifdef CONFIG_IXGBE_DCB
6907         netdev->dcbnl_ops = &dcbnl_ops;
6908 #endif
6909
6910 #ifdef IXGBE_FCOE
6911         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6912                 if (hw->mac.ops.get_device_caps) {
6913                         hw->mac.ops.get_device_caps(hw, &device_caps);
6914                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6915                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6916                 }
6917         }
6918         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6919                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6920                 netdev->vlan_features |= NETIF_F_FSO;
6921                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6922         }
6923 #endif /* IXGBE_FCOE */
6924         if (pci_using_dac) {
6925                 netdev->features |= NETIF_F_HIGHDMA;
6926                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6927         }
6928
6929         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6930                 netdev->features |= NETIF_F_LRO;
6931
6932         /* make sure the EEPROM is good */
6933         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6934                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6935                 err = -EIO;
6936                 goto err_eeprom;
6937         }
6938
6939         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6940         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6941
6942         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6943                 e_dev_err("invalid MAC address\n");
6944                 err = -EIO;
6945                 goto err_eeprom;
6946         }
6947
6948         /* power down the optics */
6949         if (hw->phy.multispeed_fiber)
6950                 hw->mac.ops.disable_tx_laser(hw);
6951
6952         init_timer(&adapter->watchdog_timer);
6953         adapter->watchdog_timer.function = ixgbe_watchdog;
6954         adapter->watchdog_timer.data = (unsigned long)adapter;
6955
6956         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6957         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6958
6959         err = ixgbe_init_interrupt_scheme(adapter);
6960         if (err)
6961                 goto err_sw_init;
6962
6963         switch (pdev->device) {
6964         case IXGBE_DEV_ID_82599_KX4:
6965                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6966                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6967                 break;
6968         default:
6969                 adapter->wol = 0;
6970                 break;
6971         }
6972         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6973
6974         /* pick up the PCI bus settings for reporting later */
6975         hw->mac.ops.get_bus_info(hw);
6976
6977         /* print bus type/speed/width info */
6978         e_dev_info("(PCI Express:%s:%s) %pM\n",
6979                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6980                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6981                     "Unknown"),
6982                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6983                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6984                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6985                     "Unknown"),
6986                    netdev->dev_addr);
6987         ixgbe_read_pba_num_generic(hw, &part_num);
6988         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6989                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6990                            "PBA No: %06x-%03x\n",
6991                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6992                            (part_num >> 8), (part_num & 0xff));
6993         else
6994                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6995                            hw->mac.type, hw->phy.type,
6996                            (part_num >> 8), (part_num & 0xff));
6997
6998         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6999                 e_dev_warn("PCI-Express bandwidth available for this card is "
7000                            "not sufficient for optimal performance.\n");
7001                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7002                            "is required.\n");
7003         }
7004
7005         /* save off EEPROM version number */
7006         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7007
7008         /* reset the hardware with the new settings */
7009         err = hw->mac.ops.start_hw(hw);
7010
7011         if (err == IXGBE_ERR_EEPROM_VERSION) {
7012                 /* We are running on a pre-production device, log a warning */
7013                 e_dev_warn("This device is a pre-production adapter/LOM. "
7014                            "Please be aware there may be issues associated "
7015                            "with your hardware.  If you are experiencing "
7016                            "problems please contact your Intel or hardware "
7017                            "representative who provided you with this "
7018                            "hardware.\n");
7019         }
7020         strcpy(netdev->name, "eth%d");
7021         err = register_netdev(netdev);
7022         if (err)
7023                 goto err_register;
7024
7025         /* carrier off reporting is important to ethtool even BEFORE open */
7026         netif_carrier_off(netdev);
7027
7028         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7029             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7030                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7031
7032         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7033                 INIT_WORK(&adapter->check_overtemp_task,
7034                           ixgbe_check_overtemp_task);
7035 #ifdef CONFIG_IXGBE_DCA
7036         if (dca_add_requester(&pdev->dev) == 0) {
7037                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7038                 ixgbe_setup_dca(adapter);
7039         }
7040 #endif
7041         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7042                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7043                 for (i = 0; i < adapter->num_vfs; i++)
7044                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7045         }
7046
7047         /* add san mac addr to netdev */
7048         ixgbe_add_sanmac_netdev(netdev);
7049
7050         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7051         cards_found++;
7052         return 0;
7053
7054 err_register:
7055         ixgbe_release_hw_control(adapter);
7056         ixgbe_clear_interrupt_scheme(adapter);
7057 err_sw_init:
7058 err_eeprom:
7059         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7060                 ixgbe_disable_sriov(adapter);
7061         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7062         del_timer_sync(&adapter->sfp_timer);
7063         cancel_work_sync(&adapter->sfp_task);
7064         cancel_work_sync(&adapter->multispeed_fiber_task);
7065         cancel_work_sync(&adapter->sfp_config_module_task);
7066         iounmap(hw->hw_addr);
7067 err_ioremap:
7068         free_netdev(netdev);
7069 err_alloc_etherdev:
7070         pci_release_selected_regions(pdev,
7071                                      pci_select_bars(pdev, IORESOURCE_MEM));
7072 err_pci_reg:
7073 err_dma:
7074         pci_disable_device(pdev);
7075         return err;
7076 }
7077
7078 /**
7079  * ixgbe_remove - Device Removal Routine
7080  * @pdev: PCI device information struct
7081  *
7082  * ixgbe_remove is called by the PCI subsystem to alert the driver
7083  * that it should release a PCI device.  The could be caused by a
7084  * Hot-Plug event, or because the driver is going to be removed from
7085  * memory.
7086  **/
7087 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7088 {
7089         struct net_device *netdev = pci_get_drvdata(pdev);
7090         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7091
7092         set_bit(__IXGBE_DOWN, &adapter->state);
7093         /* clear the module not found bit to make sure the worker won't
7094          * reschedule
7095          */
7096         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7097         del_timer_sync(&adapter->watchdog_timer);
7098
7099         del_timer_sync(&adapter->sfp_timer);
7100         cancel_work_sync(&adapter->watchdog_task);
7101         cancel_work_sync(&adapter->sfp_task);
7102         cancel_work_sync(&adapter->multispeed_fiber_task);
7103         cancel_work_sync(&adapter->sfp_config_module_task);
7104         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7105             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7106                 cancel_work_sync(&adapter->fdir_reinit_task);
7107         flush_scheduled_work();
7108
7109 #ifdef CONFIG_IXGBE_DCA
7110         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7111                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7112                 dca_remove_requester(&pdev->dev);
7113                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7114         }
7115
7116 #endif
7117 #ifdef IXGBE_FCOE
7118         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7119                 ixgbe_cleanup_fcoe(adapter);
7120
7121 #endif /* IXGBE_FCOE */
7122
7123         /* remove the added san mac */
7124         ixgbe_del_sanmac_netdev(netdev);
7125
7126         if (netdev->reg_state == NETREG_REGISTERED)
7127                 unregister_netdev(netdev);
7128
7129         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7130                 ixgbe_disable_sriov(adapter);
7131
7132         ixgbe_clear_interrupt_scheme(adapter);
7133
7134         ixgbe_release_hw_control(adapter);
7135
7136         iounmap(adapter->hw.hw_addr);
7137         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7138                                      IORESOURCE_MEM));
7139
7140         e_dev_info("complete\n");
7141
7142         free_netdev(netdev);
7143
7144         pci_disable_pcie_error_reporting(pdev);
7145
7146         pci_disable_device(pdev);
7147 }
7148
7149 /**
7150  * ixgbe_io_error_detected - called when PCI error is detected
7151  * @pdev: Pointer to PCI device
7152  * @state: The current pci connection state
7153  *
7154  * This function is called after a PCI bus error affecting
7155  * this device has been detected.
7156  */
7157 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7158                                                 pci_channel_state_t state)
7159 {
7160         struct net_device *netdev = pci_get_drvdata(pdev);
7161         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7162
7163         netif_device_detach(netdev);
7164
7165         if (state == pci_channel_io_perm_failure)
7166                 return PCI_ERS_RESULT_DISCONNECT;
7167
7168         if (netif_running(netdev))
7169                 ixgbe_down(adapter);
7170         pci_disable_device(pdev);
7171
7172         /* Request a slot reset. */
7173         return PCI_ERS_RESULT_NEED_RESET;
7174 }
7175
7176 /**
7177  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7178  * @pdev: Pointer to PCI device
7179  *
7180  * Restart the card from scratch, as if from a cold-boot.
7181  */
7182 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7183 {
7184         struct net_device *netdev = pci_get_drvdata(pdev);
7185         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7186         pci_ers_result_t result;
7187         int err;
7188
7189         if (pci_enable_device_mem(pdev)) {
7190                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7191                 result = PCI_ERS_RESULT_DISCONNECT;
7192         } else {
7193                 pci_set_master(pdev);
7194                 pci_restore_state(pdev);
7195                 pci_save_state(pdev);
7196
7197                 pci_wake_from_d3(pdev, false);
7198
7199                 ixgbe_reset(adapter);
7200                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7201                 result = PCI_ERS_RESULT_RECOVERED;
7202         }
7203
7204         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7205         if (err) {
7206                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7207                           "failed 0x%0x\n", err);
7208                 /* non-fatal, continue */
7209         }
7210
7211         return result;
7212 }
7213
7214 /**
7215  * ixgbe_io_resume - called when traffic can start flowing again.
7216  * @pdev: Pointer to PCI device
7217  *
7218  * This callback is called when the error recovery driver tells us that
7219  * its OK to resume normal operation.
7220  */
7221 static void ixgbe_io_resume(struct pci_dev *pdev)
7222 {
7223         struct net_device *netdev = pci_get_drvdata(pdev);
7224         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7225
7226         if (netif_running(netdev)) {
7227                 if (ixgbe_up(adapter)) {
7228                         e_info(probe, "ixgbe_up failed after reset\n");
7229                         return;
7230                 }
7231         }
7232
7233         netif_device_attach(netdev);
7234 }
7235
7236 static struct pci_error_handlers ixgbe_err_handler = {
7237         .error_detected = ixgbe_io_error_detected,
7238         .slot_reset = ixgbe_io_slot_reset,
7239         .resume = ixgbe_io_resume,
7240 };
7241
7242 static struct pci_driver ixgbe_driver = {
7243         .name     = ixgbe_driver_name,
7244         .id_table = ixgbe_pci_tbl,
7245         .probe    = ixgbe_probe,
7246         .remove   = __devexit_p(ixgbe_remove),
7247 #ifdef CONFIG_PM
7248         .suspend  = ixgbe_suspend,
7249         .resume   = ixgbe_resume,
7250 #endif
7251         .shutdown = ixgbe_shutdown,
7252         .err_handler = &ixgbe_err_handler
7253 };
7254
7255 /**
7256  * ixgbe_init_module - Driver Registration Routine
7257  *
7258  * ixgbe_init_module is the first routine called when the driver is
7259  * loaded. All it does is register with the PCI subsystem.
7260  **/
7261 static int __init ixgbe_init_module(void)
7262 {
7263         int ret;
7264         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7265         pr_info("%s\n", ixgbe_copyright);
7266
7267 #ifdef CONFIG_IXGBE_DCA
7268         dca_register_notify(&dca_notifier);
7269 #endif
7270
7271         ret = pci_register_driver(&ixgbe_driver);
7272         return ret;
7273 }
7274
7275 module_init(ixgbe_init_module);
7276
7277 /**
7278  * ixgbe_exit_module - Driver Exit Cleanup Routine
7279  *
7280  * ixgbe_exit_module is called just before the driver is removed
7281  * from memory.
7282  **/
7283 static void __exit ixgbe_exit_module(void)
7284 {
7285 #ifdef CONFIG_IXGBE_DCA
7286         dca_unregister_notify(&dca_notifier);
7287 #endif
7288         pci_unregister_driver(&ixgbe_driver);
7289         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7290 }
7291
7292 #ifdef CONFIG_IXGBE_DCA
7293 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7294                             void *p)
7295 {
7296         int ret_val;
7297
7298         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7299                                          __ixgbe_notify_dca);
7300
7301         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7302 }
7303
7304 #endif /* CONFIG_IXGBE_DCA */
7305
7306 /**
7307  * ixgbe_get_hw_dev return device
7308  * used by hardware layer to print debugging information
7309  **/
7310 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7311 {
7312         struct ixgbe_adapter *adapter = hw->back;
7313         return adapter->netdev;
7314 }
7315
7316 module_exit(ixgbe_exit_module);
7317
7318 /* ixgbe_main.c */