drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         clear_check_for_tx_hang(tx_ring);
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int total_bytes = 0, total_packets = 0;
 739         u16 i, eop, count = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774         tx_ring->total_bytes += total_bytes;
 775         tx_ring->total_packets += total_packets;
 776         u64_stats_update_begin(&tx_ring->syncp);
 777         tx_ring->stats.packets += total_packets;
 778         tx_ring->stats.bytes += total_bytes;
 779         u64_stats_update_end(&tx_ring->syncp);
 780
 781         if (check_for_tx_hang(tx_ring) &&
 782             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 783                 /* schedule immediate reset if we believe we hung */
 784                 e_info(probe, "tx hang %d detected, resetting "
 785                        "adapter\n", adapter->tx_timeout_count + 1);
 786                 ixgbe_tx_timeout(adapter->netdev);
 787
 788                 /* the adapter is about to reset, no point in enabling stuff */
 789                 return true;
 790         }
 791
 792 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 793         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 794                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 795                 /* Make sure that anybody stopping the queue after this
 796                  * sees the new next_to_clean.
 797                  */
 798                 smp_mb();
 799                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 800                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 801                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 802                         ++tx_ring->tx_stats.restart_queue;
 803                 }
 804         }
 805
 806         return count < tx_ring->work_limit;
 807 }
 808
 809 #ifdef CONFIG_IXGBE_DCA
 810 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 811                                 struct ixgbe_ring *rx_ring,
 812                                 int cpu)
 813 {
 814         struct ixgbe_hw *hw = &adapter->hw;
 815         u32 rxctrl;
 816         u8 reg_idx = rx_ring->reg_idx;
 817
 818         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 819         switch (hw->mac.type) {
 820         case ixgbe_mac_82598EB:
 821                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 822                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 823                 break;
 824         case ixgbe_mac_82599EB:
 825                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 826                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 827                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 828                 break;
 829         default:
 830                 break;
 831         }
 832         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 833         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 834         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 835         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 836                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 837         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 838 }
 839
 840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 841                                 struct ixgbe_ring *tx_ring,
 842                                 int cpu)
 843 {
 844         struct ixgbe_hw *hw = &adapter->hw;
 845         u32 txctrl;
 846         u8 reg_idx = tx_ring->reg_idx;
 847
 848         switch (hw->mac.type) {
 849         case ixgbe_mac_82598EB:
 850                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 851                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 852                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 853                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 854                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 855                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 856                 break;
 857         case ixgbe_mac_82599EB:
 858                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 859                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 860                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 861                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 862                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 863                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 864                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 865                 break;
 866         default:
 867                 break;
 868         }
 869 }
 870
 871 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 872 {
 873         struct ixgbe_adapter *adapter = q_vector->adapter;
 874         int cpu = get_cpu();
 875         long r_idx;
 876         int i;
 877
 878         if (q_vector->cpu == cpu)
 879                 goto out_no_update;
 880
 881         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 882         for (i = 0; i < q_vector->txr_count; i++) {
 883                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 884                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 885                                       r_idx + 1);
 886         }
 887
 888         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 889         for (i = 0; i < q_vector->rxr_count; i++) {
 890                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 891                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 892                                       r_idx + 1);
 893         }
 894
 895         q_vector->cpu = cpu;
 896 out_no_update:
 897         put_cpu();
 898 }
 899
 900 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 901 {
 902         int num_q_vectors;
 903         int i;
 904
 905         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 906                 return;
 907
 908         /* always use CB2 mode, difference is masked in the CB driver */
 909         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 910
 911         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 912                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 913         else
 914                 num_q_vectors = 1;
 915
 916         for (i = 0; i < num_q_vectors; i++) {
 917                 adapter->q_vector[i]->cpu = -1;
 918                 ixgbe_update_dca(adapter->q_vector[i]);
 919         }
 920 }
 921
 922 static int __ixgbe_notify_dca(struct device *dev, void *data)
 923 {
 924         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 925         unsigned long event = *(unsigned long *)data;
 926
 927         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 928                 return 0;
 929
 930         switch (event) {
 931         case DCA_PROVIDER_ADD:
 932                 /* if we're already enabled, don't do it again */
 933                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 934                         break;
 935                 if (dca_add_requester(dev) == 0) {
 936                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 937                         ixgbe_setup_dca(adapter);
 938                         break;
 939                 }
 940                 /* Fall Through since DCA is disabled. */
 941         case DCA_PROVIDER_REMOVE:
 942                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 943                         dca_remove_requester(dev);
 944                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 945                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 946                 }
 947                 break;
 948         }
 949
 950         return 0;
 951 }
 952
 953 #endif /* CONFIG_IXGBE_DCA */
 954 /**
 955  * ixgbe_receive_skb - Send a completed packet up the stack
 956  * @adapter: board private structure
 957  * @skb: packet to send up
 958  * @status: hardware indication of status of receive
 959  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 960  * @rx_desc: rx descriptor
 961  **/
 962 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 963                               struct sk_buff *skb, u8 status,
 964                               struct ixgbe_ring *ring,
 965                               union ixgbe_adv_rx_desc *rx_desc)
 966 {
 967         struct ixgbe_adapter *adapter = q_vector->adapter;
 968         struct napi_struct *napi = &q_vector->napi;
 969         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 970         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 971
 972         if (is_vlan && (tag & VLAN_VID_MASK))
 973                 __vlan_hwaccel_put_tag(skb, tag);
 974
 975         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 976                 napi_gro_receive(napi, skb);
 977         else
 978                 netif_rx(skb);
 979 }
 980
 981 /**
 982  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 983  * @adapter: address of board private structure
 984  * @status_err: hardware indication of status of receive
 985  * @skb: skb currently being received and modified
 986  **/
 987 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 988                                      union ixgbe_adv_rx_desc *rx_desc,
 989                                      struct sk_buff *skb)
 990 {
 991         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 992
 993         skb_checksum_none_assert(skb);
 994
 995         /* Rx csum disabled */
 996         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 997                 return;
 998
 999         /* if IP and error */
1000         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1001             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1002                 adapter->hw_csum_rx_error++;
1003                 return;
1004         }
1005
1006         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1007                 return;
1008
1009         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1010                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012                 /*
1013                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1014                  * checksum errors.
1015                  */
1016                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1017                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1018                         return;
1019
1020                 adapter->hw_csum_rx_error++;
1021                 return;
1022         }
1023
1024         /* It must be a TCP or UDP packet with a valid checksum */
1025         skb->ip_summed = CHECKSUM_UNNECESSARY;
1026 }
1027
1028 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1029 {
1030         /*
1031          * Force memory writes to complete before letting h/w
1032          * know there are new descriptors to fetch.  (Only
1033          * applicable for weak-ordered memory model archs,
1034          * such as IA-64).
1035          */
1036         wmb();
1037         writel(val, rx_ring->tail);
1038 }
1039
1040 /**
1041  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1042  * @rx_ring: ring to place buffers on
1043  * @cleaned_count: number of buffers to replace
1044  **/
1045 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1046 {
1047         union ixgbe_adv_rx_desc *rx_desc;
1048         struct ixgbe_rx_buffer *bi;
1049         struct sk_buff *skb;
1050         u16 i = rx_ring->next_to_use;
1051
1052         /* do nothing if no valid netdev defined */
1053         if (!rx_ring->netdev)
1054                 return;
1055
1056         while (cleaned_count--) {
1057                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1058                 bi = &rx_ring->rx_buffer_info[i];
1059                 skb = bi->skb;
1060
1061                 if (!skb) {
1062                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1063                                                         rx_ring->rx_buf_len);
1064                         if (!skb) {
1065                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1066                                 goto no_buffers;
1067                         }
1068                         /* initialize queue mapping */
1069                         skb_record_rx_queue(skb, rx_ring->queue_index);
1070                         bi->skb = skb;
1071                 }
1072
1073                 if (!bi->dma) {
1074                         bi->dma = dma_map_single(rx_ring->dev,
1075                                                  skb->data,
1076                                                  rx_ring->rx_buf_len,
1077                                                  DMA_FROM_DEVICE);
1078                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1079                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1080                                 bi->dma = 0;
1081                                 goto no_buffers;
1082                         }
1083                 }
1084
1085                 if (ring_is_ps_enabled(rx_ring)) {
1086                         if (!bi->page) {
1087                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1088                                 if (!bi->page) {
1089                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1090                                         goto no_buffers;
1091                                 }
1092                         }
1093
1094                         if (!bi->page_dma) {
1095                                 /* use a half page if we're re-using */
1096                                 bi->page_offset ^= PAGE_SIZE / 2;
1097                                 bi->page_dma = dma_map_page(rx_ring->dev,
1098                                                             bi->page,
1099                                                             bi->page_offset,
1100                                                             PAGE_SIZE / 2,
1101                                                             DMA_FROM_DEVICE);
1102                                 if (dma_mapping_error(rx_ring->dev,
1103                                                       bi->page_dma)) {
1104                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1105                                         bi->page_dma = 0;
1106                                         goto no_buffers;
1107                                 }
1108                         }
1109
1110                         /* Refresh the desc even if buffer_addrs didn't change
1111                          * because each write-back erases this info. */
1112                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1113                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1114                 } else {
1115                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1116                         rx_desc->read.hdr_addr = 0;
1117                 }
1118
1119                 i++;
1120                 if (i == rx_ring->count)
1121                         i = 0;
1122         }
1123
1124 no_buffers:
1125         if (rx_ring->next_to_use != i) {
1126                 rx_ring->next_to_use = i;
1127                 ixgbe_release_rx_desc(rx_ring, i);
1128         }
1129 }
1130
1131 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1132 {
1133         /* HW will not DMA in data larger than the given buffer, even if it
1134          * parses the (NFS, of course) header to be larger.  In that case, it
1135          * fills the header buffer and spills the rest into the page.
1136          */
1137         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1138         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1139                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1140         if (hlen > IXGBE_RX_HDR_SIZE)
1141                 hlen = IXGBE_RX_HDR_SIZE;
1142         return hlen;
1143 }
1144
1145 /**
1146  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1147  * @skb: pointer to the last skb in the rsc queue
1148  *
1149  * This function changes a queue full of hw rsc buffers into a completed
1150  * packet.  It uses the ->prev pointers to find the first packet and then
1151  * turns it into the frag list owner.
1152  **/
1153 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1154 {
1155         unsigned int frag_list_size = 0;
1156         unsigned int skb_cnt = 1;
1157
1158         while (skb->prev) {
1159                 struct sk_buff *prev = skb->prev;
1160                 frag_list_size += skb->len;
1161                 skb->prev = NULL;
1162                 skb = prev;
1163                 skb_cnt++;
1164         }
1165
1166         skb_shinfo(skb)->frag_list = skb->next;
1167         skb->next = NULL;
1168         skb->len += frag_list_size;
1169         skb->data_len += frag_list_size;
1170         skb->truesize += frag_list_size;
1171         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1172
1173         return skb;
1174 }
1175
1176 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1177 {
1178         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1179                 IXGBE_RXDADV_RSCCNT_MASK);
1180 }
1181
1182 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1183                                struct ixgbe_ring *rx_ring,
1184                                int *work_done, int work_to_do)
1185 {
1186         struct ixgbe_adapter *adapter = q_vector->adapter;
1187         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1188         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1189         struct sk_buff *skb;
1190         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1191         const int current_node = numa_node_id();
1192 #ifdef IXGBE_FCOE
1193         int ddp_bytes = 0;
1194 #endif /* IXGBE_FCOE */
1195         u32 staterr;
1196         u16 i;
1197         u16 cleaned_count = 0;
1198         bool pkt_is_rsc = false;
1199
1200         i = rx_ring->next_to_clean;
1201         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1202         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1203
1204         while (staterr & IXGBE_RXD_STAT_DD) {
1205                 u32 upper_len = 0;
1206
1207                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1208
1209                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1210
1211                 skb = rx_buffer_info->skb;
1212                 rx_buffer_info->skb = NULL;
1213                 prefetch(skb->data);
1214
1215                 if (ring_is_rsc_enabled(rx_ring))
1216                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1217
1218                 /* if this is a skb from previous receive DMA will be 0 */
1219                 if (rx_buffer_info->dma) {
1220                         u16 hlen;
1221                         if (pkt_is_rsc &&
1222                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1223                             !skb->prev) {
1224                                 /*
1225                                  * When HWRSC is enabled, delay unmapping
1226                                  * of the first packet. It carries the
1227                                  * header information, HW may still
1228                                  * access the header after the writeback.
1229                                  * Only unmap it when EOP is reached
1230                                  */
1231                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1232                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1233                         } else {
1234                                 dma_unmap_single(rx_ring->dev,
1235                                                  rx_buffer_info->dma,
1236                                                  rx_ring->rx_buf_len,
1237                                                  DMA_FROM_DEVICE);
1238                         }
1239                         rx_buffer_info->dma = 0;
1240
1241                         if (ring_is_ps_enabled(rx_ring)) {
1242                                 hlen = ixgbe_get_hlen(rx_desc);
1243                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1244                         } else {
1245                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1246                         }
1247
1248                         skb_put(skb, hlen);
1249                 } else {
1250                         /* assume packet split since header is unmapped */
1251                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1252                 }
1253
1254                 if (upper_len) {
1255                         dma_unmap_page(rx_ring->dev,
1256                                        rx_buffer_info->page_dma,
1257                                        PAGE_SIZE / 2,
1258                                        DMA_FROM_DEVICE);
1259                         rx_buffer_info->page_dma = 0;
1260                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1261                                            rx_buffer_info->page,
1262                                            rx_buffer_info->page_offset,
1263                                            upper_len);
1264
1265                         if ((page_count(rx_buffer_info->page) == 1) &&
1266                             (page_to_nid(rx_buffer_info->page) == current_node))
1267                                 get_page(rx_buffer_info->page);
1268                         else
1269                                 rx_buffer_info->page = NULL;
1270
1271                         skb->len += upper_len;
1272                         skb->data_len += upper_len;
1273                         skb->truesize += upper_len;
1274                 }
1275
1276                 i++;
1277                 if (i == rx_ring->count)
1278                         i = 0;
1279
1280                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1281                 prefetch(next_rxd);
1282                 cleaned_count++;
1283
1284                 if (pkt_is_rsc) {
1285                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1286                                      IXGBE_RXDADV_NEXTP_SHIFT;
1287                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1288                 } else {
1289                         next_buffer = &rx_ring->rx_buffer_info[i];
1290                 }
1291
1292                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1293                         if (ring_is_ps_enabled(rx_ring)) {
1294                                 rx_buffer_info->skb = next_buffer->skb;
1295                                 rx_buffer_info->dma = next_buffer->dma;
1296                                 next_buffer->skb = skb;
1297                                 next_buffer->dma = 0;
1298                         } else {
1299                                 skb->next = next_buffer->skb;
1300                                 skb->next->prev = skb;
1301                         }
1302                         rx_ring->rx_stats.non_eop_descs++;
1303                         goto next_desc;
1304                 }
1305
1306                 if (skb->prev) {
1307                         skb = ixgbe_transform_rsc_queue(skb);
1308                         /* if we got here without RSC the packet is invalid */
1309                         if (!pkt_is_rsc) {
1310                                 __pskb_trim(skb, 0);
1311                                 rx_buffer_info->skb = skb;
1312                                 goto next_desc;
1313                         }
1314                 }
1315
1316                 if (ring_is_rsc_enabled(rx_ring)) {
1317                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1318                                 dma_unmap_single(rx_ring->dev,
1319                                                  IXGBE_RSC_CB(skb)->dma,
1320                                                  rx_ring->rx_buf_len,
1321                                                  DMA_FROM_DEVICE);
1322                                 IXGBE_RSC_CB(skb)->dma = 0;
1323                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1324                         }
1325                 }
1326                 if (pkt_is_rsc) {
1327                         if (ring_is_ps_enabled(rx_ring))
1328                                 rx_ring->rx_stats.rsc_count +=
1329                                         skb_shinfo(skb)->nr_frags;
1330                         else
1331                                 rx_ring->rx_stats.rsc_count +=
1332                                         IXGBE_RSC_CB(skb)->skb_cnt;
1333                         rx_ring->rx_stats.rsc_flush++;
1334                 }
1335
1336                 /* ERR_MASK will only have valid bits if EOP set */
1337                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1338                         /* trim packet back to size 0 and recycle it */
1339                         __pskb_trim(skb, 0);
1340                         rx_buffer_info->skb = skb;
1341                         goto next_desc;
1342                 }
1343
1344                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1345
1346                 /* probably a little skewed due to removing CRC */
1347                 total_rx_bytes += skb->len;
1348                 total_rx_packets++;
1349
1350                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1351 #ifdef IXGBE_FCOE
1352                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1353                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1354                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1355                         if (!ddp_bytes)
1356                                 goto next_desc;
1357                 }
1358 #endif /* IXGBE_FCOE */
1359                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1360
1361 next_desc:
1362                 rx_desc->wb.upper.status_error = 0;
1363
1364                 (*work_done)++;
1365                 if (*work_done >= work_to_do)
1366                         break;
1367
1368                 /* return some buffers to hardware, one at a time is too slow */
1369                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1370                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1371                         cleaned_count = 0;
1372                 }
1373
1374                 /* use prefetched values */
1375                 rx_desc = next_rxd;
1376                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1377         }
1378
1379         rx_ring->next_to_clean = i;
1380         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1381
1382         if (cleaned_count)
1383                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1384
1385 #ifdef IXGBE_FCOE
1386         /* include DDPed FCoE data */
1387         if (ddp_bytes > 0) {
1388                 unsigned int mss;
1389
1390                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1391                         sizeof(struct fc_frame_header) -
1392                         sizeof(struct fcoe_crc_eof);
1393                 if (mss > 512)
1394                         mss &= ~511;
1395                 total_rx_bytes += ddp_bytes;
1396                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1397         }
1398 #endif /* IXGBE_FCOE */
1399
1400         rx_ring->total_packets += total_rx_packets;
1401         rx_ring->total_bytes += total_rx_bytes;
1402         u64_stats_update_begin(&rx_ring->syncp);
1403         rx_ring->stats.packets += total_rx_packets;
1404         rx_ring->stats.bytes += total_rx_bytes;
1405         u64_stats_update_end(&rx_ring->syncp);
1406 }
1407
1408 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1409 /**
1410  * ixgbe_configure_msix - Configure MSI-X hardware
1411  * @adapter: board private structure
1412  *
1413  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1414  * interrupts.
1415  **/
1416 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1417 {
1418         struct ixgbe_q_vector *q_vector;
1419         int i, j, q_vectors, v_idx, r_idx;
1420         u32 mask;
1421
1422         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1423
1424         /*
1425          * Populate the IVAR table and set the ITR values to the
1426          * corresponding register.
1427          */
1428         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1429                 q_vector = adapter->q_vector[v_idx];
1430                 /* XXX for_each_set_bit(...) */
1431                 r_idx = find_first_bit(q_vector->rxr_idx,
1432                                        adapter->num_rx_queues);
1433
1434                 for (i = 0; i < q_vector->rxr_count; i++) {
1435                         j = adapter->rx_ring[r_idx]->reg_idx;
1436                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1437                         r_idx = find_next_bit(q_vector->rxr_idx,
1438                                               adapter->num_rx_queues,
1439                                               r_idx + 1);
1440                 }
1441                 r_idx = find_first_bit(q_vector->txr_idx,
1442                                        adapter->num_tx_queues);
1443
1444                 for (i = 0; i < q_vector->txr_count; i++) {
1445                         j = adapter->tx_ring[r_idx]->reg_idx;
1446                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1447                         r_idx = find_next_bit(q_vector->txr_idx,
1448                                               adapter->num_tx_queues,
1449                                               r_idx + 1);
1450                 }
1451
1452                 if (q_vector->txr_count && !q_vector->rxr_count)
1453                         /* tx only */
1454                         q_vector->eitr = adapter->tx_eitr_param;
1455                 else if (q_vector->rxr_count)
1456                         /* rx or mixed */
1457                         q_vector->eitr = adapter->rx_eitr_param;
1458
1459                 ixgbe_write_eitr(q_vector);
1460                 /* If Flow Director is enabled, set interrupt affinity */
1461                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1462                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1463                         /*
1464                          * Allocate the affinity_hint cpumask, assign the mask
1465                          * for this vector, and set our affinity_hint for
1466                          * this irq.
1467                          */
1468                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1469                                                GFP_KERNEL))
1470                                 return;
1471                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1472                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1473                                               q_vector->affinity_mask);
1474                 }
1475         }
1476
1477         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1478                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1479                                v_idx);
1480         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1481                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1482         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1483
1484         /* set up to autoclear timer, and the vectors */
1485         mask = IXGBE_EIMS_ENABLE_MASK;
1486         if (adapter->num_vfs)
1487                 mask &= ~(IXGBE_EIMS_OTHER |
1488                           IXGBE_EIMS_MAILBOX |
1489                           IXGBE_EIMS_LSC);
1490         else
1491                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1492         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1493 }
1494
1495 enum latency_range {
1496         lowest_latency = 0,
1497         low_latency = 1,
1498         bulk_latency = 2,
1499         latency_invalid = 255
1500 };
1501
1502 /**
1503  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1504  * @adapter: pointer to adapter
1505  * @eitr: eitr setting (ints per sec) to give last timeslice
1506  * @itr_setting: current throttle rate in ints/second
1507  * @packets: the number of packets during this measurement interval
1508  * @bytes: the number of bytes during this measurement interval
1509  *
1510  *      Stores a new ITR value based on packets and byte
1511  *      counts during the last interrupt.  The advantage of per interrupt
1512  *      computation is faster updates and more accurate ITR for the current
1513  *      traffic pattern.  Constants in this function were computed
1514  *      based on theoretical maximum wire speed and thresholds were set based
1515  *      on testing data as well as attempting to minimize response time
1516  *      while increasing bulk throughput.
1517  *      this functionality is controlled by the InterruptThrottleRate module
1518  *      parameter (see ixgbe_param.c)
1519  **/
1520 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1521                            u32 eitr, u8 itr_setting,
1522                            int packets, int bytes)
1523 {
1524         unsigned int retval = itr_setting;
1525         u32 timepassed_us;
1526         u64 bytes_perint;
1527
1528         if (packets == 0)
1529                 goto update_itr_done;
1530
1531
1532         /* simple throttlerate management
1533          *    0-20MB/s lowest (100000 ints/s)
1534          *   20-100MB/s low   (20000 ints/s)
1535          *  100-1249MB/s bulk (8000 ints/s)
1536          */
1537         /* what was last interrupt timeslice? */
1538         timepassed_us = 1000000/eitr;
1539         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1540
1541         switch (itr_setting) {
1542         case lowest_latency:
1543                 if (bytes_perint > adapter->eitr_low)
1544                         retval = low_latency;
1545                 break;
1546         case low_latency:
1547                 if (bytes_perint > adapter->eitr_high)
1548                         retval = bulk_latency;
1549                 else if (bytes_perint <= adapter->eitr_low)
1550                         retval = lowest_latency;
1551                 break;
1552         case bulk_latency:
1553                 if (bytes_perint <= adapter->eitr_high)
1554                         retval = low_latency;
1555                 break;
1556         }
1557
1558 update_itr_done:
1559         return retval;
1560 }
1561
1562 /**
1563  * ixgbe_write_eitr - write EITR register in hardware specific way
1564  * @q_vector: structure containing interrupt and ring information
1565  *
1566  * This function is made to be called by ethtool and by the driver
1567  * when it needs to update EITR registers at runtime.  Hardware
1568  * specific quirks/differences are taken care of here.
1569  */
1570 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1571 {
1572         struct ixgbe_adapter *adapter = q_vector->adapter;
1573         struct ixgbe_hw *hw = &adapter->hw;
1574         int v_idx = q_vector->v_idx;
1575         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1576
1577         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1578                 /* must write high and low 16 bits to reset counter */
1579                 itr_reg |= (itr_reg << 16);
1580         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1581                 /*
1582                  * 82599 can support a value of zero, so allow it for
1583                  * max interrupt rate, but there is an errata where it can
1584                  * not be zero with RSC
1585                  */
1586                 if (itr_reg == 8 &&
1587                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1588                         itr_reg = 0;
1589
1590                 /*
1591                  * set the WDIS bit to not clear the timer bits and cause an
1592                  * immediate assertion of the interrupt
1593                  */
1594                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1595         }
1596         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1597 }
1598
1599 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1600 {
1601         struct ixgbe_adapter *adapter = q_vector->adapter;
1602         u32 new_itr;
1603         u8 current_itr, ret_itr;
1604         int i, r_idx;
1605         struct ixgbe_ring *rx_ring, *tx_ring;
1606
1607         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1608         for (i = 0; i < q_vector->txr_count; i++) {
1609                 tx_ring = adapter->tx_ring[r_idx];
1610                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1611                                            q_vector->tx_itr,
1612                                            tx_ring->total_packets,
1613                                            tx_ring->total_bytes);
1614                 /* if the result for this queue would decrease interrupt
1615                  * rate for this vector then use that result */
1616                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1617                                     q_vector->tx_itr - 1 : ret_itr);
1618                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1619                                       r_idx + 1);
1620         }
1621
1622         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1623         for (i = 0; i < q_vector->rxr_count; i++) {
1624                 rx_ring = adapter->rx_ring[r_idx];
1625                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1626                                            q_vector->rx_itr,
1627                                            rx_ring->total_packets,
1628                                            rx_ring->total_bytes);
1629                 /* if the result for this queue would decrease interrupt
1630                  * rate for this vector then use that result */
1631                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1632                                     q_vector->rx_itr - 1 : ret_itr);
1633                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1634                                       r_idx + 1);
1635         }
1636
1637         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1638
1639         switch (current_itr) {
1640         /* counts and packets in update_itr are dependent on these numbers */
1641         case lowest_latency:
1642                 new_itr = 100000;
1643                 break;
1644         case low_latency:
1645                 new_itr = 20000; /* aka hwitr = ~200 */
1646                 break;
1647         case bulk_latency:
1648         default:
1649                 new_itr = 8000;
1650                 break;
1651         }
1652
1653         if (new_itr != q_vector->eitr) {
1654                 /* do an exponential smoothing */
1655                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1656
1657                 /* save the algorithm value here, not the smoothed one */
1658                 q_vector->eitr = new_itr;
1659
1660                 ixgbe_write_eitr(q_vector);
1661         }
1662 }
1663
1664 /**
1665  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1666  * @work: pointer to work_struct containing our data
1667  **/
1668 static void ixgbe_check_overtemp_task(struct work_struct *work)
1669 {
1670         struct ixgbe_adapter *adapter = container_of(work,
1671                                                      struct ixgbe_adapter,
1672                                                      check_overtemp_task);
1673         struct ixgbe_hw *hw = &adapter->hw;
1674         u32 eicr = adapter->interrupt_event;
1675
1676         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1677                 return;
1678
1679         switch (hw->device_id) {
1680         case IXGBE_DEV_ID_82599_T3_LOM: {
1681                 u32 autoneg;
1682                 bool link_up = false;
1683
1684                 if (hw->mac.ops.check_link)
1685                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1686
1687                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1688                     (eicr & IXGBE_EICR_LSC))
1689                         /* Check if this is due to overtemp */
1690                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1691                                 break;
1692                 return;
1693         }
1694         default:
1695                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1696                         return;
1697                 break;
1698         }
1699         e_crit(drv,
1700                "Network adapter has been stopped because it has over heated. "
1701                "Restart the computer. If the problem persists, "
1702                "power off the system and replace the adapter\n");
1703         /* write to clear the interrupt */
1704         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1705 }
1706
1707 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1708 {
1709         struct ixgbe_hw *hw = &adapter->hw;
1710
1711         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1712             (eicr & IXGBE_EICR_GPI_SDP1)) {
1713                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1714                 /* write to clear the interrupt */
1715                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1716         }
1717 }
1718
1719 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1720 {
1721         struct ixgbe_hw *hw = &adapter->hw;
1722
1723         if (eicr & IXGBE_EICR_GPI_SDP2) {
1724                 /* Clear the interrupt */
1725                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1726                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1727                         schedule_work(&adapter->sfp_config_module_task);
1728         }
1729
1730         if (eicr & IXGBE_EICR_GPI_SDP1) {
1731                 /* Clear the interrupt */
1732                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1733                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1734                         schedule_work(&adapter->multispeed_fiber_task);
1735         }
1736 }
1737
1738 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1739 {
1740         struct ixgbe_hw *hw = &adapter->hw;
1741
1742         adapter->lsc_int++;
1743         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1744         adapter->link_check_timeout = jiffies;
1745         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1746                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1747                 IXGBE_WRITE_FLUSH(hw);
1748                 schedule_work(&adapter->watchdog_task);
1749         }
1750 }
1751
1752 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1753 {
1754         struct net_device *netdev = data;
1755         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1756         struct ixgbe_hw *hw = &adapter->hw;
1757         u32 eicr;
1758
1759         /*
1760          * Workaround for Silicon errata.  Use clear-by-write instead
1761          * of clear-by-read.  Reading with EICS will return the
1762          * interrupt causes without clearing, which later be done
1763          * with the write to EICR.
1764          */
1765         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1766         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1767
1768         if (eicr & IXGBE_EICR_LSC)
1769                 ixgbe_check_lsc(adapter);
1770
1771         if (eicr & IXGBE_EICR_MAILBOX)
1772                 ixgbe_msg_task(adapter);
1773
1774         if (hw->mac.type == ixgbe_mac_82598EB)
1775                 ixgbe_check_fan_failure(adapter, eicr);
1776
1777         if (hw->mac.type == ixgbe_mac_82599EB) {
1778                 ixgbe_check_sfp_event(adapter, eicr);
1779                 adapter->interrupt_event = eicr;
1780                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1781                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1782                         schedule_work(&adapter->check_overtemp_task);
1783
1784                 /* Handle Flow Director Full threshold interrupt */
1785                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1786                         int i;
1787                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1788                         /* Disable transmits before FDIR Re-initialization */
1789                         netif_tx_stop_all_queues(netdev);
1790                         for (i = 0; i < adapter->num_tx_queues; i++) {
1791                                 struct ixgbe_ring *tx_ring =
1792                                                             adapter->tx_ring[i];
1793                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1794                                                        &tx_ring->state))
1795                                         schedule_work(&adapter->fdir_reinit_task);
1796                         }
1797                 }
1798         }
1799         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1800                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1801
1802         return IRQ_HANDLED;
1803 }
1804
1805 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1806                                            u64 qmask)
1807 {
1808         u32 mask;
1809
1810         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1811                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1812                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1813         } else {
1814                 mask = (qmask & 0xFFFFFFFF);
1815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1816                 mask = (qmask >> 32);
1817                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1818         }
1819         /* skip the flush */
1820 }
1821
1822 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1823                                             u64 qmask)
1824 {
1825         u32 mask;
1826
1827         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1828                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1829                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1830         } else {
1831                 mask = (qmask & 0xFFFFFFFF);
1832                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1833                 mask = (qmask >> 32);
1834                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1835         }
1836         /* skip the flush */
1837 }
1838
1839 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1840 {
1841         struct ixgbe_q_vector *q_vector = data;
1842         struct ixgbe_adapter  *adapter = q_vector->adapter;
1843         struct ixgbe_ring     *tx_ring;
1844         int i, r_idx;
1845
1846         if (!q_vector->txr_count)
1847                 return IRQ_HANDLED;
1848
1849         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1850         for (i = 0; i < q_vector->txr_count; i++) {
1851                 tx_ring = adapter->tx_ring[r_idx];
1852                 tx_ring->total_bytes = 0;
1853                 tx_ring->total_packets = 0;
1854                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1855                                       r_idx + 1);
1856         }
1857
1858         /* EIAM disabled interrupts (on this vector) for us */
1859         napi_schedule(&q_vector->napi);
1860
1861         return IRQ_HANDLED;
1862 }
1863
1864 /**
1865  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1866  * @irq: unused
1867  * @data: pointer to our q_vector struct for this interrupt vector
1868  **/
1869 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1870 {
1871         struct ixgbe_q_vector *q_vector = data;
1872         struct ixgbe_adapter  *adapter = q_vector->adapter;
1873         struct ixgbe_ring  *rx_ring;
1874         int r_idx;
1875         int i;
1876
1877 #ifdef CONFIG_IXGBE_DCA
1878         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1879                 ixgbe_update_dca(q_vector);
1880 #endif
1881
1882         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1883         for (i = 0; i < q_vector->rxr_count; i++) {
1884                 rx_ring = adapter->rx_ring[r_idx];
1885                 rx_ring->total_bytes = 0;
1886                 rx_ring->total_packets = 0;
1887                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1888                                       r_idx + 1);
1889         }
1890
1891         if (!q_vector->rxr_count)
1892                 return IRQ_HANDLED;
1893
1894         /* EIAM disabled interrupts (on this vector) for us */
1895         napi_schedule(&q_vector->napi);
1896
1897         return IRQ_HANDLED;
1898 }
1899
1900 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1901 {
1902         struct ixgbe_q_vector *q_vector = data;
1903         struct ixgbe_adapter  *adapter = q_vector->adapter;
1904         struct ixgbe_ring  *ring;
1905         int r_idx;
1906         int i;
1907
1908         if (!q_vector->txr_count && !q_vector->rxr_count)
1909                 return IRQ_HANDLED;
1910
1911         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1912         for (i = 0; i < q_vector->txr_count; i++) {
1913                 ring = adapter->tx_ring[r_idx];
1914                 ring->total_bytes = 0;
1915                 ring->total_packets = 0;
1916                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1917                                       r_idx + 1);
1918         }
1919
1920         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1921         for (i = 0; i < q_vector->rxr_count; i++) {
1922                 ring = adapter->rx_ring[r_idx];
1923                 ring->total_bytes = 0;
1924                 ring->total_packets = 0;
1925                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1926                                       r_idx + 1);
1927         }
1928
1929         /* EIAM disabled interrupts (on this vector) for us */
1930         napi_schedule(&q_vector->napi);
1931
1932         return IRQ_HANDLED;
1933 }
1934
1935 /**
1936  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1937  * @napi: napi struct with our devices info in it
1938  * @budget: amount of work driver is allowed to do this pass, in packets
1939  *
1940  * This function is optimized for cleaning one queue only on a single
1941  * q_vector!!!
1942  **/
1943 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1944 {
1945         struct ixgbe_q_vector *q_vector =
1946                                container_of(napi, struct ixgbe_q_vector, napi);
1947         struct ixgbe_adapter *adapter = q_vector->adapter;
1948         struct ixgbe_ring *rx_ring = NULL;
1949         int work_done = 0;
1950         long r_idx;
1951
1952 #ifdef CONFIG_IXGBE_DCA
1953         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1954                 ixgbe_update_dca(q_vector);
1955 #endif
1956
1957         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1958         rx_ring = adapter->rx_ring[r_idx];
1959
1960         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1961
1962         /* If all Rx work done, exit the polling mode */
1963         if (work_done < budget) {
1964                 napi_complete(napi);
1965                 if (adapter->rx_itr_setting & 1)
1966                         ixgbe_set_itr_msix(q_vector);
1967                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1968                         ixgbe_irq_enable_queues(adapter,
1969                                                 ((u64)1 << q_vector->v_idx));
1970         }
1971
1972         return work_done;
1973 }
1974
1975 /**
1976  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1977  * @napi: napi struct with our devices info in it
1978  * @budget: amount of work driver is allowed to do this pass, in packets
1979  *
1980  * This function will clean more than one rx queue associated with a
1981  * q_vector.
1982  **/
1983 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1984 {
1985         struct ixgbe_q_vector *q_vector =
1986                                container_of(napi, struct ixgbe_q_vector, napi);
1987         struct ixgbe_adapter *adapter = q_vector->adapter;
1988         struct ixgbe_ring *ring = NULL;
1989         int work_done = 0, i;
1990         long r_idx;
1991         bool tx_clean_complete = true;
1992
1993 #ifdef CONFIG_IXGBE_DCA
1994         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1995                 ixgbe_update_dca(q_vector);
1996 #endif
1997
1998         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1999         for (i = 0; i < q_vector->txr_count; i++) {
2000                 ring = adapter->tx_ring[r_idx];
2001                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2002                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2003                                       r_idx + 1);
2004         }
2005
2006         /* attempt to distribute budget to each queue fairly, but don't allow
2007          * the budget to go below 1 because we'll exit polling */
2008         budget /= (q_vector->rxr_count ?: 1);
2009         budget = max(budget, 1);
2010         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2011         for (i = 0; i < q_vector->rxr_count; i++) {
2012                 ring = adapter->rx_ring[r_idx];
2013                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2014                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2015                                       r_idx + 1);
2016         }
2017
2018         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2019         ring = adapter->rx_ring[r_idx];
2020         /* If all Rx work done, exit the polling mode */
2021         if (work_done < budget) {
2022                 napi_complete(napi);
2023                 if (adapter->rx_itr_setting & 1)
2024                         ixgbe_set_itr_msix(q_vector);
2025                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2026                         ixgbe_irq_enable_queues(adapter,
2027                                                 ((u64)1 << q_vector->v_idx));
2028                 return 0;
2029         }
2030
2031         return work_done;
2032 }
2033
2034 /**
2035  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2036  * @napi: napi struct with our devices info in it
2037  * @budget: amount of work driver is allowed to do this pass, in packets
2038  *
2039  * This function is optimized for cleaning one queue only on a single
2040  * q_vector!!!
2041  **/
2042 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2043 {
2044         struct ixgbe_q_vector *q_vector =
2045                                container_of(napi, struct ixgbe_q_vector, napi);
2046         struct ixgbe_adapter *adapter = q_vector->adapter;
2047         struct ixgbe_ring *tx_ring = NULL;
2048         int work_done = 0;
2049         long r_idx;
2050
2051 #ifdef CONFIG_IXGBE_DCA
2052         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2053                 ixgbe_update_dca(q_vector);
2054 #endif
2055
2056         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2057         tx_ring = adapter->tx_ring[r_idx];
2058
2059         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2060                 work_done = budget;
2061
2062         /* If all Tx work done, exit the polling mode */
2063         if (work_done < budget) {
2064                 napi_complete(napi);
2065                 if (adapter->tx_itr_setting & 1)
2066                         ixgbe_set_itr_msix(q_vector);
2067                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2068                         ixgbe_irq_enable_queues(adapter,
2069                                                 ((u64)1 << q_vector->v_idx));
2070         }
2071
2072         return work_done;
2073 }
2074
2075 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2076                                      int r_idx)
2077 {
2078         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2079
2080         set_bit(r_idx, q_vector->rxr_idx);
2081         q_vector->rxr_count++;
2082 }
2083
2084 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2085                                      int t_idx)
2086 {
2087         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2088
2089         set_bit(t_idx, q_vector->txr_idx);
2090         q_vector->txr_count++;
2091 }
2092
2093 /**
2094  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2095  * @adapter: board private structure to initialize
2096  * @vectors: allotted vector count for descriptor rings
2097  *
2098  * This function maps descriptor rings to the queue-specific vectors
2099  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2100  * one vector per ring/queue, but on a constrained vector budget, we
2101  * group the rings as "efficiently" as possible.  You would add new
2102  * mapping configurations in here.
2103  **/
2104 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2105                                       int vectors)
2106 {
2107         int v_start = 0;
2108         int rxr_idx = 0, txr_idx = 0;
2109         int rxr_remaining = adapter->num_rx_queues;
2110         int txr_remaining = adapter->num_tx_queues;
2111         int i, j;
2112         int rqpv, tqpv;
2113         int err = 0;
2114
2115         /* No mapping required if MSI-X is disabled. */
2116         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2117                 goto out;
2118
2119         /*
2120          * The ideal configuration...
2121          * We have enough vectors to map one per queue.
2122          */
2123         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2124                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2125                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2126
2127                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2128                         map_vector_to_txq(adapter, v_start, txr_idx);
2129
2130                 goto out;
2131         }
2132
2133         /*
2134          * If we don't have enough vectors for a 1-to-1
2135          * mapping, we'll have to group them so there are
2136          * multiple queues per vector.
2137          */
2138         /* Re-adjusting *qpv takes care of the remainder. */
2139         for (i = v_start; i < vectors; i++) {
2140                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2141                 for (j = 0; j < rqpv; j++) {
2142                         map_vector_to_rxq(adapter, i, rxr_idx);
2143                         rxr_idx++;
2144                         rxr_remaining--;
2145                 }
2146         }
2147         for (i = v_start; i < vectors; i++) {
2148                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2149                 for (j = 0; j < tqpv; j++) {
2150                         map_vector_to_txq(adapter, i, txr_idx);
2151                         txr_idx++;
2152                         txr_remaining--;
2153                 }
2154         }
2155
2156 out:
2157         return err;
2158 }
2159
2160 /**
2161  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2162  * @adapter: board private structure
2163  *
2164  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2165  * interrupts from the kernel.
2166  **/
2167 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2168 {
2169         struct net_device *netdev = adapter->netdev;
2170         irqreturn_t (*handler)(int, void *);
2171         int i, vector, q_vectors, err;
2172         int ri = 0, ti = 0;
2173
2174         /* Decrement for Other and TCP Timer vectors */
2175         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2176
2177         /* Map the Tx/Rx rings to the vectors we were allotted. */
2178         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2179         if (err)
2180                 goto out;
2181
2182 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2183                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2184                          &ixgbe_msix_clean_many)
2185         for (vector = 0; vector < q_vectors; vector++) {
2186                 handler = SET_HANDLER(adapter->q_vector[vector]);
2187
2188                 if (handler == &ixgbe_msix_clean_rx) {
2189                         sprintf(adapter->name[vector], "%s-%s-%d",
2190                                 netdev->name, "rx", ri++);
2191                 } else if (handler == &ixgbe_msix_clean_tx) {
2192                         sprintf(adapter->name[vector], "%s-%s-%d",
2193                                 netdev->name, "tx", ti++);
2194                 } else {
2195                         sprintf(adapter->name[vector], "%s-%s-%d",
2196                                 netdev->name, "TxRx", ri++);
2197                         ti++;
2198                 }
2199
2200                 err = request_irq(adapter->msix_entries[vector].vector,
2201                                   handler, 0, adapter->name[vector],
2202                                   adapter->q_vector[vector]);
2203                 if (err) {
2204                         e_err(probe, "request_irq failed for MSIX interrupt "
2205                               "Error: %d\n", err);
2206                         goto free_queue_irqs;
2207                 }
2208         }
2209
2210         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2211         err = request_irq(adapter->msix_entries[vector].vector,
2212                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2213         if (err) {
2214                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2215                 goto free_queue_irqs;
2216         }
2217
2218         return 0;
2219
2220 free_queue_irqs:
2221         for (i = vector - 1; i >= 0; i--)
2222                 free_irq(adapter->msix_entries[--vector].vector,
2223                          adapter->q_vector[i]);
2224         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2225         pci_disable_msix(adapter->pdev);
2226         kfree(adapter->msix_entries);
2227         adapter->msix_entries = NULL;
2228 out:
2229         return err;
2230 }
2231
2232 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2233 {
2234         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2235         u8 current_itr;
2236         u32 new_itr = q_vector->eitr;
2237         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2238         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2239
2240         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2241                                             q_vector->tx_itr,
2242                                             tx_ring->total_packets,
2243                                             tx_ring->total_bytes);
2244         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2245                                             q_vector->rx_itr,
2246                                             rx_ring->total_packets,
2247                                             rx_ring->total_bytes);
2248
2249         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2250
2251         switch (current_itr) {
2252         /* counts and packets in update_itr are dependent on these numbers */
2253         case lowest_latency:
2254                 new_itr = 100000;
2255                 break;
2256         case low_latency:
2257                 new_itr = 20000; /* aka hwitr = ~200 */
2258                 break;
2259         case bulk_latency:
2260                 new_itr = 8000;
2261                 break;
2262         default:
2263                 break;
2264         }
2265
2266         if (new_itr != q_vector->eitr) {
2267                 /* do an exponential smoothing */
2268                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2269
2270                 /* save the algorithm value here, not the smoothed one */
2271                 q_vector->eitr = new_itr;
2272
2273                 ixgbe_write_eitr(q_vector);
2274         }
2275 }
2276
2277 /**
2278  * ixgbe_irq_enable - Enable default interrupt generation settings
2279  * @adapter: board private structure
2280  **/
2281 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2282                                     bool flush)
2283 {
2284         u32 mask;
2285
2286         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2287         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2288                 mask |= IXGBE_EIMS_GPI_SDP0;
2289         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2290                 mask |= IXGBE_EIMS_GPI_SDP1;
2291         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2292                 mask |= IXGBE_EIMS_ECC;
2293                 mask |= IXGBE_EIMS_GPI_SDP1;
2294                 mask |= IXGBE_EIMS_GPI_SDP2;
2295                 if (adapter->num_vfs)
2296                         mask |= IXGBE_EIMS_MAILBOX;
2297         }
2298         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2299             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2300                 mask |= IXGBE_EIMS_FLOW_DIR;
2301
2302         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2303         if (queues)
2304                 ixgbe_irq_enable_queues(adapter, ~0);
2305         if (flush)
2306                 IXGBE_WRITE_FLUSH(&adapter->hw);
2307
2308         if (adapter->num_vfs > 32) {
2309                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2310                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2311         }
2312 }
2313
2314 /**
2315  * ixgbe_intr - legacy mode Interrupt Handler
2316  * @irq: interrupt number
2317  * @data: pointer to a network interface device structure
2318  **/
2319 static irqreturn_t ixgbe_intr(int irq, void *data)
2320 {
2321         struct net_device *netdev = data;
2322         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2323         struct ixgbe_hw *hw = &adapter->hw;
2324         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2325         u32 eicr;
2326
2327         /*
2328          * Workaround for silicon errata on 82598.  Mask the interrupts
2329          * before the read of EICR.
2330          */
2331         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2332
2333         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2334          * therefore no explict interrupt disable is necessary */
2335         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2336         if (!eicr) {
2337                 /*
2338                  * shared interrupt alert!
2339                  * make sure interrupts are enabled because the read will
2340                  * have disabled interrupts due to EIAM
2341                  * finish the workaround of silicon errata on 82598.  Unmask
2342                  * the interrupt that we masked before the EICR read.
2343                  */
2344                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2345                         ixgbe_irq_enable(adapter, true, true);
2346                 return IRQ_NONE;        /* Not our interrupt */
2347         }
2348
2349         if (eicr & IXGBE_EICR_LSC)
2350                 ixgbe_check_lsc(adapter);
2351
2352         if (hw->mac.type == ixgbe_mac_82599EB)
2353                 ixgbe_check_sfp_event(adapter, eicr);
2354
2355         ixgbe_check_fan_failure(adapter, eicr);
2356         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2357             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2358                 schedule_work(&adapter->check_overtemp_task);
2359
2360         if (napi_schedule_prep(&(q_vector->napi))) {
2361                 adapter->tx_ring[0]->total_packets = 0;
2362                 adapter->tx_ring[0]->total_bytes = 0;
2363                 adapter->rx_ring[0]->total_packets = 0;
2364                 adapter->rx_ring[0]->total_bytes = 0;
2365                 /* would disable interrupts here but EIAM disabled it */
2366                 __napi_schedule(&(q_vector->napi));
2367         }
2368
2369         /*
2370          * re-enable link(maybe) and non-queue interrupts, no flush.
2371          * ixgbe_poll will re-enable the queue interrupts
2372          */
2373
2374         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2375                 ixgbe_irq_enable(adapter, false, false);
2376
2377         return IRQ_HANDLED;
2378 }
2379
2380 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2381 {
2382         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2383
2384         for (i = 0; i < q_vectors; i++) {
2385                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2386                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2387                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2388                 q_vector->rxr_count = 0;
2389                 q_vector->txr_count = 0;
2390         }
2391 }
2392
2393 /**
2394  * ixgbe_request_irq - initialize interrupts
2395  * @adapter: board private structure
2396  *
2397  * Attempts to configure interrupts using the best available
2398  * capabilities of the hardware and kernel.
2399  **/
2400 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2401 {
2402         struct net_device *netdev = adapter->netdev;
2403         int err;
2404
2405         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2406                 err = ixgbe_request_msix_irqs(adapter);
2407         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2408                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2409                                   netdev->name, netdev);
2410         } else {
2411                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2412                                   netdev->name, netdev);
2413         }
2414
2415         if (err)
2416                 e_err(probe, "request_irq failed, Error %d\n", err);
2417
2418         return err;
2419 }
2420
2421 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2422 {
2423         struct net_device *netdev = adapter->netdev;
2424
2425         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2426                 int i, q_vectors;
2427
2428                 q_vectors = adapter->num_msix_vectors;
2429
2430                 i = q_vectors - 1;
2431                 free_irq(adapter->msix_entries[i].vector, netdev);
2432
2433                 i--;
2434                 for (; i >= 0; i--) {
2435                         free_irq(adapter->msix_entries[i].vector,
2436                                  adapter->q_vector[i]);
2437                 }
2438
2439                 ixgbe_reset_q_vectors(adapter);
2440         } else {
2441                 free_irq(adapter->pdev->irq, netdev);
2442         }
2443 }
2444
2445 /**
2446  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2447  * @adapter: board private structure
2448  **/
2449 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2450 {
2451         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2452                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2453         } else {
2454                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2455                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2456                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2457                 if (adapter->num_vfs > 32)
2458                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2459         }
2460         IXGBE_WRITE_FLUSH(&adapter->hw);
2461         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2462                 int i;
2463                 for (i = 0; i < adapter->num_msix_vectors; i++)
2464                         synchronize_irq(adapter->msix_entries[i].vector);
2465         } else {
2466                 synchronize_irq(adapter->pdev->irq);
2467         }
2468 }
2469
2470 /**
2471  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2472  *
2473  **/
2474 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2475 {
2476         struct ixgbe_hw *hw = &adapter->hw;
2477
2478         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2479                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2480
2481         ixgbe_set_ivar(adapter, 0, 0, 0);
2482         ixgbe_set_ivar(adapter, 1, 0, 0);
2483
2484         map_vector_to_rxq(adapter, 0, 0);
2485         map_vector_to_txq(adapter, 0, 0);
2486
2487         e_info(hw, "Legacy interrupt IVAR setup done\n");
2488 }
2489
2490 /**
2491  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2492  * @adapter: board private structure
2493  * @ring: structure containing ring specific data
2494  *
2495  * Configure the Tx descriptor ring after a reset.
2496  **/
2497 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2498                              struct ixgbe_ring *ring)
2499 {
2500         struct ixgbe_hw *hw = &adapter->hw;
2501         u64 tdba = ring->dma;
2502         int wait_loop = 10;
2503         u32 txdctl;
2504         u16 reg_idx = ring->reg_idx;
2505
2506         /* disable queue to avoid issues while updating state */
2507         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2508         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2509                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2510         IXGBE_WRITE_FLUSH(hw);
2511
2512         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2513                         (tdba & DMA_BIT_MASK(32)));
2514         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2515         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2516                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2517         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2518         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2519         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2520
2521         /* configure fetching thresholds */
2522         if (adapter->rx_itr_setting == 0) {
2523                 /* cannot set wthresh when itr==0 */
2524                 txdctl &= ~0x007F0000;
2525         } else {
2526                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2527                 txdctl |= (8 << 16);
2528         }
2529         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2530                 /* PThresh workaround for Tx hang with DFP enabled. */
2531                 txdctl |= 32;
2532         }
2533
2534         /* reinitialize flowdirector state */
2535         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2536             adapter->atr_sample_rate) {
2537                 ring->atr_sample_rate = adapter->atr_sample_rate;
2538                 ring->atr_count = 0;
2539                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2540         } else {
2541                 ring->atr_sample_rate = 0;
2542         }
2543
2544         /* enable queue */
2545         txdctl |= IXGBE_TXDCTL_ENABLE;
2546         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2547
2548         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2549         if (hw->mac.type == ixgbe_mac_82598EB &&
2550             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2551                 return;
2552
2553         /* poll to verify queue is enabled */
2554         do {
2555                 msleep(1);
2556                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2557         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2558         if (!wait_loop)
2559                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2560 }
2561
2562 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2563 {
2564         struct ixgbe_hw *hw = &adapter->hw;
2565         u32 rttdcs;
2566         u32 mask;
2567
2568         if (hw->mac.type == ixgbe_mac_82598EB)
2569                 return;
2570
2571         /* disable the arbiter while setting MTQC */
2572         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2573         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2574         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2575
2576         /* set transmit pool layout */
2577         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2578         switch (adapter->flags & mask) {
2579
2580         case (IXGBE_FLAG_SRIOV_ENABLED):
2581                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2582                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2583                 break;
2584
2585         case (IXGBE_FLAG_DCB_ENABLED):
2586                 /* We enable 8 traffic classes, DCB only */
2587                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2588                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2589                 break;
2590
2591         default:
2592                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2593                 break;
2594         }
2595
2596         /* re-enable the arbiter */
2597         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2598         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2599 }
2600
2601 /**
2602  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2603  * @adapter: board private structure
2604  *
2605  * Configure the Tx unit of the MAC after a reset.
2606  **/
2607 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2608 {
2609         struct ixgbe_hw *hw = &adapter->hw;
2610         u32 dmatxctl;
2611         u32 i;
2612
2613         ixgbe_setup_mtqc(adapter);
2614
2615         if (hw->mac.type != ixgbe_mac_82598EB) {
2616                 /* DMATXCTL.EN must be before Tx queues are enabled */
2617                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2618                 dmatxctl |= IXGBE_DMATXCTL_TE;
2619                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2620         }
2621
2622         /* Setup the HW Tx Head and Tail descriptor pointers */
2623         for (i = 0; i < adapter->num_tx_queues; i++)
2624                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2625 }
2626
2627 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2628
2629 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2630                                    struct ixgbe_ring *rx_ring)
2631 {
2632         u32 srrctl;
2633         int index;
2634         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2635
2636         index = rx_ring->reg_idx;
2637         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2638                 unsigned long mask;
2639                 mask = (unsigned long) feature[RING_F_RSS].mask;
2640                 index = index & mask;
2641         }
2642         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2643
2644         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2645         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2646         if (adapter->num_vfs)
2647                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2648
2649         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2650                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2651
2652         if (ring_is_ps_enabled(rx_ring)) {
2653 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2654                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2655 #else
2656                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2657 #endif
2658                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2659         } else {
2660                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2661                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2662                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2663         }
2664
2665         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2666 }
2667
2668 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2669 {
2670         struct ixgbe_hw *hw = &adapter->hw;
2671         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2672                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2673                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2674         u32 mrqc = 0, reta = 0;
2675         u32 rxcsum;
2676         int i, j;
2677         int mask;
2678
2679         /* Fill out hash function seeds */
2680         for (i = 0; i < 10; i++)
2681                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2682
2683         /* Fill out redirection table */
2684         for (i = 0, j = 0; i < 128; i++, j++) {
2685                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2686                         j = 0;
2687                 /* reta = 4-byte sliding window of
2688                  * 0x00..(indices-1)(indices-1)00..etc. */
2689                 reta = (reta << 8) | (j * 0x11);
2690                 if ((i & 3) == 3)
2691                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2692         }
2693
2694         /* Disable indicating checksum in descriptor, enables RSS hash */
2695         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2696         rxcsum |= IXGBE_RXCSUM_PCSD;
2697         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2698
2699         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2700                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2701         else
2702                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2703 #ifdef CONFIG_IXGBE_DCB
2704                                          | IXGBE_FLAG_DCB_ENABLED
2705 #endif
2706                                          | IXGBE_FLAG_SRIOV_ENABLED
2707                                         );
2708
2709         switch (mask) {
2710         case (IXGBE_FLAG_RSS_ENABLED):
2711                 mrqc = IXGBE_MRQC_RSSEN;
2712                 break;
2713         case (IXGBE_FLAG_SRIOV_ENABLED):
2714                 mrqc = IXGBE_MRQC_VMDQEN;
2715                 break;
2716 #ifdef CONFIG_IXGBE_DCB
2717         case (IXGBE_FLAG_DCB_ENABLED):
2718                 mrqc = IXGBE_MRQC_RT8TCEN;
2719                 break;
2720 #endif /* CONFIG_IXGBE_DCB */
2721         default:
2722                 break;
2723         }
2724
2725         /* Perform hash on these packet types */
2726         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2727               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2728               | IXGBE_MRQC_RSS_FIELD_IPV6
2729               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2730
2731         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2732 }
2733
2734 /**
2735  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2736  * @adapter:    address of board private structure
2737  * @index:      index of ring to set
2738  **/
2739 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2740                                    struct ixgbe_ring *ring)
2741 {
2742         struct ixgbe_hw *hw = &adapter->hw;
2743         u32 rscctrl;
2744         int rx_buf_len;
2745         u16 reg_idx = ring->reg_idx;
2746
2747         if (!ring_is_rsc_enabled(ring))
2748                 return;
2749
2750         rx_buf_len = ring->rx_buf_len;
2751         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2752         rscctrl |= IXGBE_RSCCTL_RSCEN;
2753         /*
2754          * we must limit the number of descriptors so that the
2755          * total size of max desc * buf_len is not greater
2756          * than 65535
2757          */
2758         if (ring_is_ps_enabled(ring)) {
2759 #if (MAX_SKB_FRAGS > 16)
2760                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2761 #elif (MAX_SKB_FRAGS > 8)
2762                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2763 #elif (MAX_SKB_FRAGS > 4)
2764                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2765 #else
2766                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2767 #endif
2768         } else {
2769                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2770                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2771                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2772                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2773                 else
2774                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2775         }
2776         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2777 }
2778
2779 /**
2780  *  ixgbe_set_uta - Set unicast filter table address
2781  *  @adapter: board private structure
2782  *
2783  *  The unicast table address is a register array of 32-bit registers.
2784  *  The table is meant to be used in a way similar to how the MTA is used
2785  *  however due to certain limitations in the hardware it is necessary to
2786  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2787  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2788  **/
2789 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2790 {
2791         struct ixgbe_hw *hw = &adapter->hw;
2792         int i;
2793
2794         /* The UTA table only exists on 82599 hardware and newer */
2795         if (hw->mac.type < ixgbe_mac_82599EB)
2796                 return;
2797
2798         /* we only need to do this if VMDq is enabled */
2799         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2800                 return;
2801
2802         for (i = 0; i < 128; i++)
2803                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2804 }
2805
2806 #define IXGBE_MAX_RX_DESC_POLL 10
2807 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2808                                        struct ixgbe_ring *ring)
2809 {
2810         struct ixgbe_hw *hw = &adapter->hw;
2811         int reg_idx = ring->reg_idx;
2812         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2813         u32 rxdctl;
2814
2815         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2816         if (hw->mac.type == ixgbe_mac_82598EB &&
2817             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2818                 return;
2819
2820         do {
2821                 msleep(1);
2822                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2823         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2824
2825         if (!wait_loop) {
2826                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2827                       "the polling period\n", reg_idx);
2828         }
2829 }
2830
2831 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2832                              struct ixgbe_ring *ring)
2833 {
2834         struct ixgbe_hw *hw = &adapter->hw;
2835         u64 rdba = ring->dma;
2836         u32 rxdctl;
2837         u16 reg_idx = ring->reg_idx;
2838
2839         /* disable queue to avoid issues while updating state */
2840         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2841         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2842                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2843         IXGBE_WRITE_FLUSH(hw);
2844
2845         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2846         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2847         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2848                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2849         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2850         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2851         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2852
2853         ixgbe_configure_srrctl(adapter, ring);
2854         ixgbe_configure_rscctl(adapter, ring);
2855
2856         if (hw->mac.type == ixgbe_mac_82598EB) {
2857                 /*
2858                  * enable cache line friendly hardware writes:
2859                  * PTHRESH=32 descriptors (half the internal cache),
2860                  * this also removes ugly rx_no_buffer_count increment
2861                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2862                  * WTHRESH=8 burst writeback up to two cache lines
2863                  */
2864                 rxdctl &= ~0x3FFFFF;
2865                 rxdctl |=  0x080420;
2866         }
2867
2868         /* enable receive descriptor ring */
2869         rxdctl |= IXGBE_RXDCTL_ENABLE;
2870         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2871
2872         ixgbe_rx_desc_queue_enable(adapter, ring);
2873         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2874 }
2875
2876 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2877 {
2878         struct ixgbe_hw *hw = &adapter->hw;
2879         int p;
2880
2881         /* PSRTYPE must be initialized in non 82598 adapters */
2882         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2883                       IXGBE_PSRTYPE_UDPHDR |
2884                       IXGBE_PSRTYPE_IPV4HDR |
2885                       IXGBE_PSRTYPE_L2HDR |
2886                       IXGBE_PSRTYPE_IPV6HDR;
2887
2888         if (hw->mac.type == ixgbe_mac_82598EB)
2889                 return;
2890
2891         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2892                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2893
2894         for (p = 0; p < adapter->num_rx_pools; p++)
2895                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2896                                 psrtype);
2897 }
2898
2899 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2900 {
2901         struct ixgbe_hw *hw = &adapter->hw;
2902         u32 gcr_ext;
2903         u32 vt_reg_bits;
2904         u32 reg_offset, vf_shift;
2905         u32 vmdctl;
2906
2907         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2908                 return;
2909
2910         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2911         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2912         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2913         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2914
2915         vf_shift = adapter->num_vfs % 32;
2916         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2917
2918         /* Enable only the PF's pool for Tx/Rx */
2919         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2920         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2921         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2922         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2923         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2924
2925         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2926         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2927
2928         /*
2929          * Set up VF register offsets for selected VT Mode,
2930          * i.e. 32 or 64 VFs for SR-IOV
2931          */
2932         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2933         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2934         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2935         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2936
2937         /* enable Tx loopback for VF/PF communication */
2938         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2939 }
2940
2941 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2942 {
2943         struct ixgbe_hw *hw = &adapter->hw;
2944         struct net_device *netdev = adapter->netdev;
2945         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2946         int rx_buf_len;
2947         struct ixgbe_ring *rx_ring;
2948         int i;
2949         u32 mhadd, hlreg0;
2950
2951         /* Decide whether to use packet split mode or not */
2952         /* Do not use packet split if we're in SR-IOV Mode */
2953         if (!adapter->num_vfs)
2954                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2955
2956         /* Set the RX buffer length according to the mode */
2957         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2958                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2959         } else {
2960                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2961                     (netdev->mtu <= ETH_DATA_LEN))
2962                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2963                 else
2964                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2965         }
2966
2967 #ifdef IXGBE_FCOE
2968         /* adjust max frame to be able to do baby jumbo for FCoE */
2969         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2970             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2971                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2972
2973 #endif /* IXGBE_FCOE */
2974         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2975         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2976                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2977                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2978
2979                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2980         }
2981
2982         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2983         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2984         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2985         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2986
2987         /*
2988          * Setup the HW Rx Head and Tail Descriptor Pointers and
2989          * the Base and Length of the Rx Descriptor Ring
2990          */
2991         for (i = 0; i < adapter->num_rx_queues; i++) {
2992                 rx_ring = adapter->rx_ring[i];
2993                 rx_ring->rx_buf_len = rx_buf_len;
2994
2995                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2996                         set_ring_ps_enabled(rx_ring);
2997                 else
2998                         clear_ring_ps_enabled(rx_ring);
2999
3000                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3001                         set_ring_rsc_enabled(rx_ring);
3002                 else
3003                         clear_ring_rsc_enabled(rx_ring);
3004
3005 #ifdef IXGBE_FCOE
3006                 if (netdev->features & NETIF_F_FCOE_MTU) {
3007                         struct ixgbe_ring_feature *f;
3008                         f = &adapter->ring_feature[RING_F_FCOE];
3009                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3010                                 clear_ring_ps_enabled(rx_ring);
3011                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3012                                         rx_ring->rx_buf_len =
3013                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3014                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3015                                    !ring_is_ps_enabled(rx_ring)) {
3016                                 rx_ring->rx_buf_len =
3017                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3018                         }
3019                 }
3020 #endif /* IXGBE_FCOE */
3021         }
3022 }
3023
3024 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3025 {
3026         struct ixgbe_hw *hw = &adapter->hw;
3027         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3028
3029         switch (hw->mac.type) {
3030         case ixgbe_mac_82598EB:
3031                 /*
3032                  * For VMDq support of different descriptor types or
3033                  * buffer sizes through the use of multiple SRRCTL
3034                  * registers, RDRXCTL.MVMEN must be set to 1
3035                  *
3036                  * also, the manual doesn't mention it clearly but DCA hints
3037                  * will only use queue 0's tags unless this bit is set.  Side
3038                  * effects of setting this bit are only that SRRCTL must be
3039                  * fully programmed [0..15]
3040                  */
3041                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3042                 break;
3043         case ixgbe_mac_82599EB:
3044                 /* Disable RSC for ACK packets */
3045                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3046                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3047                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3048                 /* hardware requires some bits to be set by default */
3049                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3050                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3051                 break;
3052         default:
3053                 /* We should do nothing since we don't know this hardware */
3054                 return;
3055         }
3056
3057         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3058 }
3059
3060 /**
3061  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3062  * @adapter: board private structure
3063  *
3064  * Configure the Rx unit of the MAC after a reset.
3065  **/
3066 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3067 {
3068         struct ixgbe_hw *hw = &adapter->hw;
3069         int i;
3070         u32 rxctrl;
3071
3072         /* disable receives while setting up the descriptors */
3073         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3074         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3075
3076         ixgbe_setup_psrtype(adapter);
3077         ixgbe_setup_rdrxctl(adapter);
3078
3079         /* Program registers for the distribution of queues */
3080         ixgbe_setup_mrqc(adapter);
3081
3082         ixgbe_set_uta(adapter);
3083
3084         /* set_rx_buffer_len must be called before ring initialization */
3085         ixgbe_set_rx_buffer_len(adapter);
3086
3087         /*
3088          * Setup the HW Rx Head and Tail Descriptor Pointers and
3089          * the Base and Length of the Rx Descriptor Ring
3090          */
3091         for (i = 0; i < adapter->num_rx_queues; i++)
3092                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3093
3094         /* disable drop enable for 82598 parts */
3095         if (hw->mac.type == ixgbe_mac_82598EB)
3096                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3097
3098         /* enable all receives */
3099         rxctrl |= IXGBE_RXCTRL_RXEN;
3100         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3101 }
3102
3103 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3104 {
3105         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3106         struct ixgbe_hw *hw = &adapter->hw;
3107         int pool_ndx = adapter->num_vfs;
3108
3109         /* add VID to filter table */
3110         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3111         set_bit(vid, adapter->active_vlans);
3112 }
3113
3114 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3115 {
3116         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3117         struct ixgbe_hw *hw = &adapter->hw;
3118         int pool_ndx = adapter->num_vfs;
3119
3120         /* remove VID from filter table */
3121         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3122         clear_bit(vid, adapter->active_vlans);
3123 }
3124
3125 /**
3126  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3127  * @adapter: driver data
3128  */
3129 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3130 {
3131         struct ixgbe_hw *hw = &adapter->hw;
3132         u32 vlnctrl;
3133
3134         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3135         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3136         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3137 }
3138
3139 /**
3140  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3141  * @adapter: driver data
3142  */
3143 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3144 {
3145         struct ixgbe_hw *hw = &adapter->hw;
3146         u32 vlnctrl;
3147
3148         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3149         vlnctrl |= IXGBE_VLNCTRL_VFE;
3150         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3151         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3152 }
3153
3154 /**
3155  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3156  * @adapter: driver data
3157  */
3158 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3159 {
3160         struct ixgbe_hw *hw = &adapter->hw;
3161         u32 vlnctrl;
3162         int i, j;
3163
3164         switch (hw->mac.type) {
3165         case ixgbe_mac_82598EB:
3166                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3167                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3168                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3169                 break;
3170         case ixgbe_mac_82599EB:
3171                 for (i = 0; i < adapter->num_rx_queues; i++) {
3172                         j = adapter->rx_ring[i]->reg_idx;
3173                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3174                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3175                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3176                 }
3177                 break;
3178         default:
3179                 break;
3180         }
3181 }
3182
3183 /**
3184  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3185  * @adapter: driver data
3186  */
3187 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3188 {
3189         struct ixgbe_hw *hw = &adapter->hw;
3190         u32 vlnctrl;
3191         int i, j;
3192
3193         switch (hw->mac.type) {
3194         case ixgbe_mac_82598EB:
3195                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3196                 vlnctrl |= IXGBE_VLNCTRL_VME;
3197                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3198                 break;
3199         case ixgbe_mac_82599EB:
3200                 for (i = 0; i < adapter->num_rx_queues; i++) {
3201                         j = adapter->rx_ring[i]->reg_idx;
3202                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3203                         vlnctrl |= IXGBE_RXDCTL_VME;
3204                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3205                 }
3206                 break;
3207         default:
3208                 break;
3209         }
3210 }
3211
3212 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3213 {
3214         u16 vid;
3215
3216         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3217
3218         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3219                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3220 }
3221
3222 /**
3223  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3224  * @netdev: network interface device structure
3225  *
3226  * Writes unicast address list to the RAR table.
3227  * Returns: -ENOMEM on failure/insufficient address space
3228  *                0 on no addresses written
3229  *                X on writing X addresses to the RAR table
3230  **/
3231 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3232 {
3233         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3234         struct ixgbe_hw *hw = &adapter->hw;
3235         unsigned int vfn = adapter->num_vfs;
3236         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3237         int count = 0;
3238
3239         /* return ENOMEM indicating insufficient memory for addresses */
3240         if (netdev_uc_count(netdev) > rar_entries)
3241                 return -ENOMEM;
3242
3243         if (!netdev_uc_empty(netdev) && rar_entries) {
3244                 struct netdev_hw_addr *ha;
3245                 /* return error if we do not support writing to RAR table */
3246                 if (!hw->mac.ops.set_rar)
3247                         return -ENOMEM;
3248
3249                 netdev_for_each_uc_addr(ha, netdev) {
3250                         if (!rar_entries)
3251                                 break;
3252                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3253                                             vfn, IXGBE_RAH_AV);
3254                         count++;
3255                 }
3256         }
3257         /* write the addresses in reverse order to avoid write combining */
3258         for (; rar_entries > 0 ; rar_entries--)
3259                 hw->mac.ops.clear_rar(hw, rar_entries);
3260
3261         return count;
3262 }
3263
3264 /**
3265  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3266  * @netdev: network interface device structure
3267  *
3268  * The set_rx_method entry point is called whenever the unicast/multicast
3269  * address list or the network interface flags are updated.  This routine is
3270  * responsible for configuring the hardware for proper unicast, multicast and
3271  * promiscuous mode.
3272  **/
3273 void ixgbe_set_rx_mode(struct net_device *netdev)
3274 {
3275         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3276         struct ixgbe_hw *hw = &adapter->hw;
3277         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3278         int count;
3279
3280         /* Check for Promiscuous and All Multicast modes */
3281
3282         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3283
3284         /* set all bits that we expect to always be set */
3285         fctrl |= IXGBE_FCTRL_BAM;
3286         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3287         fctrl |= IXGBE_FCTRL_PMCF;
3288
3289         /* clear the bits we are changing the status of */
3290         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3291
3292         if (netdev->flags & IFF_PROMISC) {
3293                 hw->addr_ctrl.user_set_promisc = true;
3294                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3295                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3296                 /* don't hardware filter vlans in promisc mode */
3297                 ixgbe_vlan_filter_disable(adapter);
3298         } else {
3299                 if (netdev->flags & IFF_ALLMULTI) {
3300                         fctrl |= IXGBE_FCTRL_MPE;
3301                         vmolr |= IXGBE_VMOLR_MPE;
3302                 } else {
3303                         /*
3304                          * Write addresses to the MTA, if the attempt fails
3305                          * then we should just turn on promiscous mode so
3306                          * that we can at least receive multicast traffic
3307                          */
3308                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3309                         vmolr |= IXGBE_VMOLR_ROMPE;
3310                 }
3311                 ixgbe_vlan_filter_enable(adapter);
3312                 hw->addr_ctrl.user_set_promisc = false;
3313                 /*
3314                  * Write addresses to available RAR registers, if there is not
3315                  * sufficient space to store all the addresses then enable
3316                  * unicast promiscous mode
3317                  */
3318                 count = ixgbe_write_uc_addr_list(netdev);
3319                 if (count < 0) {
3320                         fctrl |= IXGBE_FCTRL_UPE;
3321                         vmolr |= IXGBE_VMOLR_ROPE;
3322                 }
3323         }
3324
3325         if (adapter->num_vfs) {
3326                 ixgbe_restore_vf_multicasts(adapter);
3327                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3328                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3329                            IXGBE_VMOLR_ROPE);
3330                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3331         }
3332
3333         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3334
3335         if (netdev->features & NETIF_F_HW_VLAN_RX)
3336                 ixgbe_vlan_strip_enable(adapter);
3337         else
3338                 ixgbe_vlan_strip_disable(adapter);
3339 }
3340
3341 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3342 {
3343         int q_idx;
3344         struct ixgbe_q_vector *q_vector;
3345         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3346
3347         /* legacy and MSI only use one vector */
3348         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3349                 q_vectors = 1;
3350
3351         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3352                 struct napi_struct *napi;
3353                 q_vector = adapter->q_vector[q_idx];
3354                 napi = &q_vector->napi;
3355                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3356                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3357                                 if (q_vector->txr_count == 1)
3358                                         napi->poll = &ixgbe_clean_txonly;
3359                                 else if (q_vector->rxr_count == 1)
3360                                         napi->poll = &ixgbe_clean_rxonly;
3361                         }
3362                 }
3363
3364                 napi_enable(napi);
3365         }
3366 }
3367
3368 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3369 {
3370         int q_idx;
3371         struct ixgbe_q_vector *q_vector;
3372         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3373
3374         /* legacy and MSI only use one vector */
3375         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3376                 q_vectors = 1;
3377
3378         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3379                 q_vector = adapter->q_vector[q_idx];
3380                 napi_disable(&q_vector->napi);
3381         }
3382 }
3383
3384 #ifdef CONFIG_IXGBE_DCB
3385 /*
3386  * ixgbe_configure_dcb - Configure DCB hardware
3387  * @adapter: ixgbe adapter struct
3388  *
3389  * This is called by the driver on open to configure the DCB hardware.
3390  * This is also called by the gennetlink interface when reconfiguring
3391  * the DCB state.
3392  */
3393 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3394 {
3395         struct ixgbe_hw *hw = &adapter->hw;
3396         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3397
3398         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3399                 if (hw->mac.type == ixgbe_mac_82598EB)
3400                         netif_set_gso_max_size(adapter->netdev, 65536);
3401                 return;
3402         }
3403
3404         if (hw->mac.type == ixgbe_mac_82598EB)
3405                 netif_set_gso_max_size(adapter->netdev, 32768);
3406
3407 #ifdef CONFIG_FCOE
3408         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3409                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3410 #endif
3411
3412         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3413                                         DCB_TX_CONFIG);
3414         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3415                                         DCB_RX_CONFIG);
3416
3417         /* Enable VLAN tag insert/strip */
3418         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3419
3420         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3421
3422         /* reconfigure the hardware */
3423         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3424 }
3425
3426 #endif
3427 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3428 {
3429         struct net_device *netdev = adapter->netdev;
3430         struct ixgbe_hw *hw = &adapter->hw;
3431         int i;
3432
3433 #ifdef CONFIG_IXGBE_DCB
3434         ixgbe_configure_dcb(adapter);
3435 #endif
3436
3437         ixgbe_set_rx_mode(netdev);
3438         ixgbe_restore_vlan(adapter);
3439
3440 #ifdef IXGBE_FCOE
3441         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3442                 ixgbe_configure_fcoe(adapter);
3443
3444 #endif /* IXGBE_FCOE */
3445         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3446                 for (i = 0; i < adapter->num_tx_queues; i++)
3447                         adapter->tx_ring[i]->atr_sample_rate =
3448                                                        adapter->atr_sample_rate;
3449                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3450         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3451                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3452         }
3453         ixgbe_configure_virtualization(adapter);
3454
3455         ixgbe_configure_tx(adapter);
3456         ixgbe_configure_rx(adapter);
3457 }
3458
3459 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3460 {
3461         switch (hw->phy.type) {
3462         case ixgbe_phy_sfp_avago:
3463         case ixgbe_phy_sfp_ftl:
3464         case ixgbe_phy_sfp_intel:
3465         case ixgbe_phy_sfp_unknown:
3466         case ixgbe_phy_sfp_passive_tyco:
3467         case ixgbe_phy_sfp_passive_unknown:
3468         case ixgbe_phy_sfp_active_unknown:
3469         case ixgbe_phy_sfp_ftl_active:
3470                 return true;
3471         default:
3472                 return false;
3473         }
3474 }
3475
3476 /**
3477  * ixgbe_sfp_link_config - set up SFP+ link
3478  * @adapter: pointer to private adapter struct
3479  **/
3480 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3481 {
3482         struct ixgbe_hw *hw = &adapter->hw;
3483
3484                 if (hw->phy.multispeed_fiber) {
3485                         /*
3486                          * In multispeed fiber setups, the device may not have
3487                          * had a physical connection when the driver loaded.
3488                          * If that's the case, the initial link configuration
3489                          * couldn't get the MAC into 10G or 1G mode, so we'll
3490                          * never have a link status change interrupt fire.
3491                          * We need to try and force an autonegotiation
3492                          * session, then bring up link.
3493                          */
3494                         hw->mac.ops.setup_sfp(hw);
3495                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3496                                 schedule_work(&adapter->multispeed_fiber_task);
3497                 } else {
3498                         /*
3499                          * Direct Attach Cu and non-multispeed fiber modules
3500                          * still need to be configured properly prior to
3501                          * attempting link.
3502                          */
3503                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3504                                 schedule_work(&adapter->sfp_config_module_task);
3505                 }
3506 }
3507
3508 /**
3509  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3510  * @hw: pointer to private hardware struct
3511  *
3512  * Returns 0 on success, negative on failure
3513  **/
3514 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3515 {
3516         u32 autoneg;
3517         bool negotiation, link_up = false;
3518         u32 ret = IXGBE_ERR_LINK_SETUP;
3519
3520         if (hw->mac.ops.check_link)
3521                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3522
3523         if (ret)
3524                 goto link_cfg_out;
3525
3526         if (hw->mac.ops.get_link_capabilities)
3527                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3528                                                         &negotiation);
3529         if (ret)
3530                 goto link_cfg_out;
3531
3532         if (hw->mac.ops.setup_link)
3533                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3534 link_cfg_out:
3535         return ret;
3536 }
3537
3538 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3539 {
3540         struct ixgbe_hw *hw = &adapter->hw;
3541         u32 gpie = 0;
3542
3543         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3544                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3545                        IXGBE_GPIE_OCD;
3546                 gpie |= IXGBE_GPIE_EIAME;
3547                 /*
3548                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3549                  * this saves a register write for every interrupt
3550                  */
3551                 switch (hw->mac.type) {
3552                 case ixgbe_mac_82598EB:
3553                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3554                         break;
3555                 default:
3556                 case ixgbe_mac_82599EB:
3557                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3558                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3559                         break;
3560                 }
3561         } else {
3562                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3563                  * specifically only auto mask tx and rx interrupts */
3564                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3565         }
3566
3567         /* XXX: to interrupt immediately for EICS writes, enable this */
3568         /* gpie |= IXGBE_GPIE_EIMEN; */
3569
3570         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3571                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3572                 gpie |= IXGBE_GPIE_VTMODE_64;
3573         }
3574
3575         /* Enable fan failure interrupt */
3576         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3577                 gpie |= IXGBE_SDP1_GPIEN;
3578
3579         if (hw->mac.type == ixgbe_mac_82599EB)
3580                 gpie |= IXGBE_SDP1_GPIEN;
3581                 gpie |= IXGBE_SDP2_GPIEN;
3582
3583         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3584 }
3585
3586 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3587 {
3588         struct ixgbe_hw *hw = &adapter->hw;
3589         int err;
3590         u32 ctrl_ext;
3591
3592         ixgbe_get_hw_control(adapter);
3593         ixgbe_setup_gpie(adapter);
3594
3595         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3596                 ixgbe_configure_msix(adapter);
3597         else
3598                 ixgbe_configure_msi_and_legacy(adapter);
3599
3600         /* enable the optics */
3601         if (hw->phy.multispeed_fiber)
3602                 hw->mac.ops.enable_tx_laser(hw);
3603
3604         clear_bit(__IXGBE_DOWN, &adapter->state);
3605         ixgbe_napi_enable_all(adapter);
3606
3607         if (ixgbe_is_sfp(hw)) {
3608                 ixgbe_sfp_link_config(adapter);
3609         } else {
3610                 err = ixgbe_non_sfp_link_config(hw);
3611                 if (err)
3612                         e_err(probe, "link_config FAILED %d\n", err);
3613         }
3614
3615         /* clear any pending interrupts, may auto mask */
3616         IXGBE_READ_REG(hw, IXGBE_EICR);
3617         ixgbe_irq_enable(adapter, true, true);
3618
3619         /*
3620          * If this adapter has a fan, check to see if we had a failure
3621          * before we enabled the interrupt.
3622          */
3623         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3624                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3625                 if (esdp & IXGBE_ESDP_SDP1)
3626                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3627         }
3628
3629         /*
3630          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3631          * arrived before interrupts were enabled but after probe.  Such
3632          * devices wouldn't have their type identified yet. We need to
3633          * kick off the SFP+ module setup first, then try to bring up link.
3634          * If we're not hot-pluggable SFP+, we just need to configure link
3635          * and bring it up.
3636          */
3637         if (hw->phy.type == ixgbe_phy_unknown)
3638                 schedule_work(&adapter->sfp_config_module_task);
3639
3640         /* enable transmits */
3641         netif_tx_start_all_queues(adapter->netdev);
3642
3643         /* bring the link up in the watchdog, this could race with our first
3644          * link up interrupt but shouldn't be a problem */
3645         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3646         adapter->link_check_timeout = jiffies;
3647         mod_timer(&adapter->watchdog_timer, jiffies);
3648
3649         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3650         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3651         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3652         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3653
3654         return 0;
3655 }
3656
3657 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3658 {
3659         WARN_ON(in_interrupt());
3660         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3661                 msleep(1);
3662         ixgbe_down(adapter);
3663         /*
3664          * If SR-IOV enabled then wait a bit before bringing the adapter
3665          * back up to give the VFs time to respond to the reset.  The
3666          * two second wait is based upon the watchdog timer cycle in
3667          * the VF driver.
3668          */
3669         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3670                 msleep(2000);
3671         ixgbe_up(adapter);
3672         clear_bit(__IXGBE_RESETTING, &adapter->state);
3673 }
3674
3675 int ixgbe_up(struct ixgbe_adapter *adapter)
3676 {
3677         /* hardware has been reset, we need to reload some things */
3678         ixgbe_configure(adapter);
3679
3680         return ixgbe_up_complete(adapter);
3681 }
3682
3683 void ixgbe_reset(struct ixgbe_adapter *adapter)
3684 {
3685         struct ixgbe_hw *hw = &adapter->hw;
3686         int err;
3687
3688         err = hw->mac.ops.init_hw(hw);
3689         switch (err) {
3690         case 0:
3691         case IXGBE_ERR_SFP_NOT_PRESENT:
3692                 break;
3693         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3694                 e_dev_err("master disable timed out\n");
3695                 break;
3696         case IXGBE_ERR_EEPROM_VERSION:
3697                 /* We are running on a pre-production device, log a warning */
3698                 e_dev_warn("This device is a pre-production adapter/LOM. "
3699                            "Please be aware there may be issuesassociated with "
3700                            "your hardware.  If you are experiencing problems "
3701                            "please contact your Intel or hardware "
3702                            "representative who provided you with this "
3703                            "hardware.\n");
3704                 break;
3705         default:
3706                 e_dev_err("Hardware Error: %d\n", err);
3707         }
3708
3709         /* reprogram the RAR[0] in case user changed it. */
3710         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3711                             IXGBE_RAH_AV);
3712 }
3713
3714 /**
3715  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3716  * @rx_ring: ring to free buffers from
3717  **/
3718 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3719 {
3720         struct device *dev = rx_ring->dev;
3721         unsigned long size;
3722         u16 i;
3723
3724         /* ring already cleared, nothing to do */
3725         if (!rx_ring->rx_buffer_info)
3726                 return;
3727
3728         /* Free all the Rx ring sk_buffs */
3729         for (i = 0; i < rx_ring->count; i++) {
3730                 struct ixgbe_rx_buffer *rx_buffer_info;
3731
3732                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3733                 if (rx_buffer_info->dma) {
3734                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3735                                          rx_ring->rx_buf_len,
3736                                          DMA_FROM_DEVICE);
3737                         rx_buffer_info->dma = 0;
3738                 }
3739                 if (rx_buffer_info->skb) {
3740                         struct sk_buff *skb = rx_buffer_info->skb;
3741                         rx_buffer_info->skb = NULL;
3742                         do {
3743                                 struct sk_buff *this = skb;
3744                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3745                                         dma_unmap_single(dev,
3746                                                          IXGBE_RSC_CB(this)->dma,
3747                                                          rx_ring->rx_buf_len,
3748                                                          DMA_FROM_DEVICE);
3749                                         IXGBE_RSC_CB(this)->dma = 0;
3750                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3751                                 }
3752                                 skb = skb->prev;
3753                                 dev_kfree_skb(this);
3754                         } while (skb);
3755                 }
3756                 if (!rx_buffer_info->page)
3757                         continue;
3758                 if (rx_buffer_info->page_dma) {
3759                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3760                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3761                         rx_buffer_info->page_dma = 0;
3762                 }
3763                 put_page(rx_buffer_info->page);
3764                 rx_buffer_info->page = NULL;
3765                 rx_buffer_info->page_offset = 0;
3766         }
3767
3768         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3769         memset(rx_ring->rx_buffer_info, 0, size);
3770
3771         /* Zero out the descriptor ring */
3772         memset(rx_ring->desc, 0, rx_ring->size);
3773
3774         rx_ring->next_to_clean = 0;
3775         rx_ring->next_to_use = 0;
3776 }
3777
3778 /**
3779  * ixgbe_clean_tx_ring - Free Tx Buffers
3780  * @tx_ring: ring to be cleaned
3781  **/
3782 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3783 {
3784         struct ixgbe_tx_buffer *tx_buffer_info;
3785         unsigned long size;
3786         u16 i;
3787
3788         /* ring already cleared, nothing to do */
3789         if (!tx_ring->tx_buffer_info)
3790                 return;
3791
3792         /* Free all the Tx ring sk_buffs */
3793         for (i = 0; i < tx_ring->count; i++) {
3794                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3795                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3796         }
3797
3798         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3799         memset(tx_ring->tx_buffer_info, 0, size);
3800
3801         /* Zero out the descriptor ring */
3802         memset(tx_ring->desc, 0, tx_ring->size);
3803
3804         tx_ring->next_to_use = 0;
3805         tx_ring->next_to_clean = 0;
3806 }
3807
3808 /**
3809  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3810  * @adapter: board private structure
3811  **/
3812 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3813 {
3814         int i;
3815
3816         for (i = 0; i < adapter->num_rx_queues; i++)
3817                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3818 }
3819
3820 /**
3821  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3822  * @adapter: board private structure
3823  **/
3824 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3825 {
3826         int i;
3827
3828         for (i = 0; i < adapter->num_tx_queues; i++)
3829                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3830 }
3831
3832 void ixgbe_down(struct ixgbe_adapter *adapter)
3833 {
3834         struct net_device *netdev = adapter->netdev;
3835         struct ixgbe_hw *hw = &adapter->hw;
3836         u32 rxctrl;
3837         u32 txdctl;
3838         int i, j;
3839         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3840
3841         /* signal that we are down to the interrupt handler */
3842         set_bit(__IXGBE_DOWN, &adapter->state);
3843
3844         /* disable receive for all VFs and wait one second */
3845         if (adapter->num_vfs) {
3846                 /* ping all the active vfs to let them know we are going down */
3847                 ixgbe_ping_all_vfs(adapter);
3848
3849                 /* Disable all VFTE/VFRE TX/RX */
3850                 ixgbe_disable_tx_rx(adapter);
3851
3852                 /* Mark all the VFs as inactive */
3853                 for (i = 0 ; i < adapter->num_vfs; i++)
3854                         adapter->vfinfo[i].clear_to_send = 0;
3855         }
3856
3857         /* disable receives */
3858         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3859         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3860
3861         IXGBE_WRITE_FLUSH(hw);
3862         msleep(10);
3863
3864         netif_tx_stop_all_queues(netdev);
3865
3866         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3867         del_timer_sync(&adapter->sfp_timer);
3868         del_timer_sync(&adapter->watchdog_timer);
3869         cancel_work_sync(&adapter->watchdog_task);
3870
3871         netif_carrier_off(netdev);
3872         netif_tx_disable(netdev);
3873
3874         ixgbe_irq_disable(adapter);
3875
3876         ixgbe_napi_disable_all(adapter);
3877
3878         /* Cleanup the affinity_hint CPU mask memory and callback */
3879         for (i = 0; i < num_q_vectors; i++) {
3880                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3881                 /* clear the affinity_mask in the IRQ descriptor */
3882                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3883                 /* release the CPU mask memory */
3884                 free_cpumask_var(q_vector->affinity_mask);
3885         }
3886
3887         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3888             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3889                 cancel_work_sync(&adapter->fdir_reinit_task);
3890
3891         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3892                 cancel_work_sync(&adapter->check_overtemp_task);
3893
3894         /* disable transmits in the hardware now that interrupts are off */
3895         for (i = 0; i < adapter->num_tx_queues; i++) {
3896                 j = adapter->tx_ring[i]->reg_idx;
3897                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3898                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3899                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3900         }
3901         /* Disable the Tx DMA engine on 82599 */
3902         if (hw->mac.type == ixgbe_mac_82599EB)
3903                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3904                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3905                                  ~IXGBE_DMATXCTL_TE));
3906
3907         /* power down the optics */
3908         if (hw->phy.multispeed_fiber)
3909                 hw->mac.ops.disable_tx_laser(hw);
3910
3911         /* clear n-tuple filters that are cached */
3912         ethtool_ntuple_flush(netdev);
3913
3914         if (!pci_channel_offline(adapter->pdev))
3915                 ixgbe_reset(adapter);
3916         ixgbe_clean_all_tx_rings(adapter);
3917         ixgbe_clean_all_rx_rings(adapter);
3918
3919 #ifdef CONFIG_IXGBE_DCA
3920         /* since we reset the hardware DCA settings were cleared */
3921         ixgbe_setup_dca(adapter);
3922 #endif
3923 }
3924
3925 /**
3926  * ixgbe_poll - NAPI Rx polling callback
3927  * @napi: structure for representing this polling device
3928  * @budget: how many packets driver is allowed to clean
3929  *
3930  * This function is used for legacy and MSI, NAPI mode
3931  **/
3932 static int ixgbe_poll(struct napi_struct *napi, int budget)
3933 {
3934         struct ixgbe_q_vector *q_vector =
3935                                 container_of(napi, struct ixgbe_q_vector, napi);
3936         struct ixgbe_adapter *adapter = q_vector->adapter;
3937         int tx_clean_complete, work_done = 0;
3938
3939 #ifdef CONFIG_IXGBE_DCA
3940         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3941                 ixgbe_update_dca(q_vector);
3942 #endif
3943
3944         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3945         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3946
3947         if (!tx_clean_complete)
3948                 work_done = budget;
3949
3950         /* If budget not fully consumed, exit the polling mode */
3951         if (work_done < budget) {
3952                 napi_complete(napi);
3953                 if (adapter->rx_itr_setting & 1)
3954                         ixgbe_set_itr(adapter);
3955                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3956                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3957         }
3958         return work_done;
3959 }
3960
3961 /**
3962  * ixgbe_tx_timeout - Respond to a Tx Hang
3963  * @netdev: network interface device structure
3964  **/
3965 static void ixgbe_tx_timeout(struct net_device *netdev)
3966 {
3967         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3968
3969         /* Do the reset outside of interrupt context */
3970         schedule_work(&adapter->reset_task);
3971 }
3972
3973 static void ixgbe_reset_task(struct work_struct *work)
3974 {
3975         struct ixgbe_adapter *adapter;
3976         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3977
3978         /* If we're already down or resetting, just bail */
3979         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3980             test_bit(__IXGBE_RESETTING, &adapter->state))
3981                 return;
3982
3983         adapter->tx_timeout_count++;
3984
3985         ixgbe_dump(adapter);
3986         netdev_err(adapter->netdev, "Reset adapter\n");
3987         ixgbe_reinit_locked(adapter);
3988 }
3989
3990 #ifdef CONFIG_IXGBE_DCB
3991 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3992 {
3993         bool ret = false;
3994         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3995
3996         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3997                 return ret;
3998
3999         f->mask = 0x7 << 3;
4000         adapter->num_rx_queues = f->indices;
4001         adapter->num_tx_queues = f->indices;
4002         ret = true;
4003
4004         return ret;
4005 }
4006 #endif
4007
4008 /**
4009  * ixgbe_set_rss_queues: Allocate queues for RSS
4010  * @adapter: board private structure to initialize
4011  *
4012  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4013  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4014  *
4015  **/
4016 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4017 {
4018         bool ret = false;
4019         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4020
4021         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4022                 f->mask = 0xF;
4023                 adapter->num_rx_queues = f->indices;
4024                 adapter->num_tx_queues = f->indices;
4025                 ret = true;
4026         } else {
4027                 ret = false;
4028         }
4029
4030         return ret;
4031 }
4032
4033 /**
4034  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4035  * @adapter: board private structure to initialize
4036  *
4037  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4038  * to the original CPU that initiated the Tx session.  This runs in addition
4039  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4040  * Rx load across CPUs using RSS.
4041  *
4042  **/
4043 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4044 {
4045         bool ret = false;
4046         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4047
4048         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4049         f_fdir->mask = 0;
4050
4051         /* Flow Director must have RSS enabled */
4052         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4053             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4054              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4055                 adapter->num_tx_queues = f_fdir->indices;
4056                 adapter->num_rx_queues = f_fdir->indices;
4057                 ret = true;
4058         } else {
4059                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4060                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4061         }
4062         return ret;
4063 }
4064
4065 #ifdef IXGBE_FCOE
4066 /**
4067  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4068  * @adapter: board private structure to initialize
4069  *
4070  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4071  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4072  * rx queues out of the max number of rx queues, instead, it is used as the
4073  * index of the first rx queue used by FCoE.
4074  *
4075  **/
4076 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4077 {
4078         bool ret = false;
4079         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4080
4081         f->indices = min((int)num_online_cpus(), f->indices);
4082         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4083                 adapter->num_rx_queues = 1;
4084                 adapter->num_tx_queues = 1;
4085 #ifdef CONFIG_IXGBE_DCB
4086                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4087                         e_info(probe, "FCoE enabled with DCB\n");
4088                         ixgbe_set_dcb_queues(adapter);
4089                 }
4090 #endif
4091                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4092                         e_info(probe, "FCoE enabled with RSS\n");
4093                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4094                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4095                                 ixgbe_set_fdir_queues(adapter);
4096                         else
4097                                 ixgbe_set_rss_queues(adapter);
4098                 }
4099                 /* adding FCoE rx rings to the end */
4100                 f->mask = adapter->num_rx_queues;
4101                 adapter->num_rx_queues += f->indices;
4102                 adapter->num_tx_queues += f->indices;
4103
4104                 ret = true;
4105         }
4106
4107         return ret;
4108 }
4109
4110 #endif /* IXGBE_FCOE */
4111 /**
4112  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4113  * @adapter: board private structure to initialize
4114  *
4115  * IOV doesn't actually use anything, so just NAK the
4116  * request for now and let the other queue routines
4117  * figure out what to do.
4118  */
4119 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4120 {
4121         return false;
4122 }
4123
4124 /*
4125  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4126  * @adapter: board private structure to initialize
4127  *
4128  * This is the top level queue allocation routine.  The order here is very
4129  * important, starting with the "most" number of features turned on at once,
4130  * and ending with the smallest set of features.  This way large combinations
4131  * can be allocated if they're turned on, and smaller combinations are the
4132  * fallthrough conditions.
4133  *
4134  **/
4135 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4136 {
4137         /* Start with base case */
4138         adapter->num_rx_queues = 1;
4139         adapter->num_tx_queues = 1;
4140         adapter->num_rx_pools = adapter->num_rx_queues;
4141         adapter->num_rx_queues_per_pool = 1;
4142
4143         if (ixgbe_set_sriov_queues(adapter))
4144                 goto done;
4145
4146 #ifdef IXGBE_FCOE
4147         if (ixgbe_set_fcoe_queues(adapter))
4148                 goto done;
4149
4150 #endif /* IXGBE_FCOE */
4151 #ifdef CONFIG_IXGBE_DCB
4152         if (ixgbe_set_dcb_queues(adapter))
4153                 goto done;
4154
4155 #endif
4156         if (ixgbe_set_fdir_queues(adapter))
4157                 goto done;
4158
4159         if (ixgbe_set_rss_queues(adapter))
4160                 goto done;
4161
4162         /* fallback to base case */
4163         adapter->num_rx_queues = 1;
4164         adapter->num_tx_queues = 1;
4165
4166 done:
4167         /* Notify the stack of the (possibly) reduced queue counts. */
4168         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4169         return netif_set_real_num_rx_queues(adapter->netdev,
4170                                             adapter->num_rx_queues);
4171 }
4172
4173 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4174                                        int vectors)
4175 {
4176         int err, vector_threshold;
4177
4178         /* We'll want at least 3 (vector_threshold):
4179          * 1) TxQ[0] Cleanup
4180          * 2) RxQ[0] Cleanup
4181          * 3) Other (Link Status Change, etc.)
4182          * 4) TCP Timer (optional)
4183          */
4184         vector_threshold = MIN_MSIX_COUNT;
4185
4186         /* The more we get, the more we will assign to Tx/Rx Cleanup
4187          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4188          * Right now, we simply care about how many we'll get; we'll
4189          * set them up later while requesting irq's.
4190          */
4191         while (vectors >= vector_threshold) {
4192                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4193                                       vectors);
4194                 if (!err) /* Success in acquiring all requested vectors. */
4195                         break;
4196                 else if (err < 0)
4197                         vectors = 0; /* Nasty failure, quit now */
4198                 else /* err == number of vectors we should try again with */
4199                         vectors = err;
4200         }
4201
4202         if (vectors < vector_threshold) {
4203                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4204                  * This just means we'll go with either a single MSI
4205                  * vector or fall back to legacy interrupts.
4206                  */
4207                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4208                              "Unable to allocate MSI-X interrupts\n");
4209                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4210                 kfree(adapter->msix_entries);
4211                 adapter->msix_entries = NULL;
4212         } else {
4213                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4214                 /*
4215                  * Adjust for only the vectors we'll use, which is minimum
4216                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4217                  * vectors we were allocated.
4218                  */
4219                 adapter->num_msix_vectors = min(vectors,
4220                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4221         }
4222 }
4223
4224 /**
4225  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4226  * @adapter: board private structure to initialize
4227  *
4228  * Cache the descriptor ring offsets for RSS to the assigned rings.
4229  *
4230  **/
4231 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4232 {
4233         int i;
4234         bool ret = false;
4235
4236         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4237                 for (i = 0; i < adapter->num_rx_queues; i++)
4238                         adapter->rx_ring[i]->reg_idx = i;
4239                 for (i = 0; i < adapter->num_tx_queues; i++)
4240                         adapter->tx_ring[i]->reg_idx = i;
4241                 ret = true;
4242         } else {
4243                 ret = false;
4244         }
4245
4246         return ret;
4247 }
4248
4249 #ifdef CONFIG_IXGBE_DCB
4250 /**
4251  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4252  * @adapter: board private structure to initialize
4253  *
4254  * Cache the descriptor ring offsets for DCB to the assigned rings.
4255  *
4256  **/
4257 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4258 {
4259         int i;
4260         bool ret = false;
4261         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4262
4263         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4264                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4265                         /* the number of queues is assumed to be symmetric */
4266                         for (i = 0; i < dcb_i; i++) {
4267                                 adapter->rx_ring[i]->reg_idx = i << 3;
4268                                 adapter->tx_ring[i]->reg_idx = i << 2;
4269                         }
4270                         ret = true;
4271                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4272                         if (dcb_i == 8) {
4273                                 /*
4274                                  * Tx TC0 starts at: descriptor queue 0
4275                                  * Tx TC1 starts at: descriptor queue 32
4276                                  * Tx TC2 starts at: descriptor queue 64
4277                                  * Tx TC3 starts at: descriptor queue 80
4278                                  * Tx TC4 starts at: descriptor queue 96
4279                                  * Tx TC5 starts at: descriptor queue 104
4280                                  * Tx TC6 starts at: descriptor queue 112
4281                                  * Tx TC7 starts at: descriptor queue 120
4282                                  *
4283                                  * Rx TC0-TC7 are offset by 16 queues each
4284                                  */
4285                                 for (i = 0; i < 3; i++) {
4286                                         adapter->tx_ring[i]->reg_idx = i << 5;
4287                                         adapter->rx_ring[i]->reg_idx = i << 4;
4288                                 }
4289                                 for ( ; i < 5; i++) {
4290                                         adapter->tx_ring[i]->reg_idx =
4291                                                                  ((i + 2) << 4);
4292                                         adapter->rx_ring[i]->reg_idx = i << 4;
4293                                 }
4294                                 for ( ; i < dcb_i; i++) {
4295                                         adapter->tx_ring[i]->reg_idx =
4296                                                                  ((i + 8) << 3);
4297                                         adapter->rx_ring[i]->reg_idx = i << 4;
4298                                 }
4299
4300                                 ret = true;
4301                         } else if (dcb_i == 4) {
4302                                 /*
4303                                  * Tx TC0 starts at: descriptor queue 0
4304                                  * Tx TC1 starts at: descriptor queue 64
4305                                  * Tx TC2 starts at: descriptor queue 96
4306                                  * Tx TC3 starts at: descriptor queue 112
4307                                  *
4308                                  * Rx TC0-TC3 are offset by 32 queues each
4309                                  */
4310                                 adapter->tx_ring[0]->reg_idx = 0;
4311                                 adapter->tx_ring[1]->reg_idx = 64;
4312                                 adapter->tx_ring[2]->reg_idx = 96;
4313                                 adapter->tx_ring[3]->reg_idx = 112;
4314                                 for (i = 0 ; i < dcb_i; i++)
4315                                         adapter->rx_ring[i]->reg_idx = i << 5;
4316
4317                                 ret = true;
4318                         } else {
4319                                 ret = false;
4320                         }
4321                 } else {
4322                         ret = false;
4323                 }
4324         } else {
4325                 ret = false;
4326         }
4327
4328         return ret;
4329 }
4330 #endif
4331
4332 /**
4333  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4334  * @adapter: board private structure to initialize
4335  *
4336  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4337  *
4338  **/
4339 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4340 {
4341         int i;
4342         bool ret = false;
4343
4344         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4345             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4346              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4347                 for (i = 0; i < adapter->num_rx_queues; i++)
4348                         adapter->rx_ring[i]->reg_idx = i;
4349                 for (i = 0; i < adapter->num_tx_queues; i++)
4350                         adapter->tx_ring[i]->reg_idx = i;
4351                 ret = true;
4352         }
4353
4354         return ret;
4355 }
4356
4357 #ifdef IXGBE_FCOE
4358 /**
4359  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4360  * @adapter: board private structure to initialize
4361  *
4362  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4363  *
4364  */
4365 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4366 {
4367         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4368         bool ret = false;
4369         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4370
4371         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4372 #ifdef CONFIG_IXGBE_DCB
4373                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4374                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4375
4376                         ixgbe_cache_ring_dcb(adapter);
4377                         /* find out queues in TC for FCoE */
4378                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4379                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4380                         /*
4381                          * In 82599, the number of Tx queues for each traffic
4382                          * class for both 8-TC and 4-TC modes are:
4383                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4384                          * 8 TCs:  32  32  16  16   8   8   8   8
4385                          * 4 TCs:  64  64  32  32
4386                          * We have max 8 queues for FCoE, where 8 the is
4387                          * FCoE redirection table size. If TC for FCoE is
4388                          * less than or equal to TC3, we have enough queues
4389                          * to add max of 8 queues for FCoE, so we start FCoE
4390                          * tx descriptor from the next one, i.e., reg_idx + 1.
4391                          * If TC for FCoE is above TC3, implying 8 TC mode,
4392                          * and we need 8 for FCoE, we have to take all queues
4393                          * in that traffic class for FCoE.
4394                          */
4395                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4396                                 fcoe_tx_i--;
4397                 }
4398 #endif /* CONFIG_IXGBE_DCB */
4399                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4400                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4401                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4402                                 ixgbe_cache_ring_fdir(adapter);
4403                         else
4404                                 ixgbe_cache_ring_rss(adapter);
4405
4406                         fcoe_rx_i = f->mask;
4407                         fcoe_tx_i = f->mask;
4408                 }
4409                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4410                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4411                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4412                 }
4413                 ret = true;
4414         }
4415         return ret;
4416 }
4417
4418 #endif /* IXGBE_FCOE */
4419 /**
4420  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4421  * @adapter: board private structure to initialize
4422  *
4423  * SR-IOV doesn't use any descriptor rings but changes the default if
4424  * no other mapping is used.
4425  *
4426  */
4427 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4428 {
4429         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4430         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4431         if (adapter->num_vfs)
4432                 return true;
4433         else
4434                 return false;
4435 }
4436
4437 /**
4438  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4439  * @adapter: board private structure to initialize
4440  *
4441  * Once we know the feature-set enabled for the device, we'll cache
4442  * the register offset the descriptor ring is assigned to.
4443  *
4444  * Note, the order the various feature calls is important.  It must start with
4445  * the "most" features enabled at the same time, then trickle down to the
4446  * least amount of features turned on at once.
4447  **/
4448 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4449 {
4450         /* start with default case */
4451         adapter->rx_ring[0]->reg_idx = 0;
4452         adapter->tx_ring[0]->reg_idx = 0;
4453
4454         if (ixgbe_cache_ring_sriov(adapter))
4455                 return;
4456
4457 #ifdef IXGBE_FCOE
4458         if (ixgbe_cache_ring_fcoe(adapter))
4459                 return;
4460
4461 #endif /* IXGBE_FCOE */
4462 #ifdef CONFIG_IXGBE_DCB
4463         if (ixgbe_cache_ring_dcb(adapter))
4464                 return;
4465
4466 #endif
4467         if (ixgbe_cache_ring_fdir(adapter))
4468                 return;
4469
4470         if (ixgbe_cache_ring_rss(adapter))
4471                 return;
4472 }
4473
4474 /**
4475  * ixgbe_alloc_queues - Allocate memory for all rings
4476  * @adapter: board private structure to initialize
4477  *
4478  * We allocate one ring per queue at run-time since we don't know the
4479  * number of queues at compile-time.  The polling_netdev array is
4480  * intended for Multiqueue, but should work fine with a single queue.
4481  **/
4482 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4483 {
4484         int i;
4485         int rx_count;
4486         int orig_node = adapter->node;
4487
4488         for (i = 0; i < adapter->num_tx_queues; i++) {
4489                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4490                 if (orig_node == -1) {
4491                         int cur_node = next_online_node(adapter->node);
4492                         if (cur_node == MAX_NUMNODES)
4493                                 cur_node = first_online_node;
4494                         adapter->node = cur_node;
4495                 }
4496                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4497                                     adapter->node);
4498                 if (!ring)
4499                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4500                 if (!ring)
4501                         goto err_tx_ring_allocation;
4502                 ring->count = adapter->tx_ring_count;
4503                 ring->queue_index = i;
4504                 ring->dev = &adapter->pdev->dev;
4505                 ring->netdev = adapter->netdev;
4506                 ring->numa_node = adapter->node;
4507
4508                 adapter->tx_ring[i] = ring;
4509         }
4510
4511         /* Restore the adapter's original node */
4512         adapter->node = orig_node;
4513
4514         rx_count = adapter->rx_ring_count;
4515         for (i = 0; i < adapter->num_rx_queues; i++) {
4516                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4517                 if (orig_node == -1) {
4518                         int cur_node = next_online_node(adapter->node);
4519                         if (cur_node == MAX_NUMNODES)
4520                                 cur_node = first_online_node;
4521                         adapter->node = cur_node;
4522                 }
4523                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4524                                     adapter->node);
4525                 if (!ring)
4526                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4527                 if (!ring)
4528                         goto err_rx_ring_allocation;
4529                 ring->count = rx_count;
4530                 ring->queue_index = i;
4531                 ring->dev = &adapter->pdev->dev;
4532                 ring->netdev = adapter->netdev;
4533                 ring->numa_node = adapter->node;
4534
4535                 adapter->rx_ring[i] = ring;
4536         }
4537
4538         /* Restore the adapter's original node */
4539         adapter->node = orig_node;
4540
4541         ixgbe_cache_ring_register(adapter);
4542
4543         return 0;
4544
4545 err_rx_ring_allocation:
4546         for (i = 0; i < adapter->num_tx_queues; i++)
4547                 kfree(adapter->tx_ring[i]);
4548 err_tx_ring_allocation:
4549         return -ENOMEM;
4550 }
4551
4552 /**
4553  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4554  * @adapter: board private structure to initialize
4555  *
4556  * Attempt to configure the interrupts using the best available
4557  * capabilities of the hardware and the kernel.
4558  **/
4559 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4560 {
4561         struct ixgbe_hw *hw = &adapter->hw;
4562         int err = 0;
4563         int vector, v_budget;
4564
4565         /*
4566          * It's easy to be greedy for MSI-X vectors, but it really
4567          * doesn't do us much good if we have a lot more vectors
4568          * than CPU's.  So let's be conservative and only ask for
4569          * (roughly) the same number of vectors as there are CPU's.
4570          */
4571         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4572                        (int)num_online_cpus()) + NON_Q_VECTORS;
4573
4574         /*
4575          * At the same time, hardware can only support a maximum of
4576          * hw.mac->max_msix_vectors vectors.  With features
4577          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4578          * descriptor queues supported by our device.  Thus, we cap it off in
4579          * those rare cases where the cpu count also exceeds our vector limit.
4580          */
4581         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4582
4583         /* A failure in MSI-X entry allocation isn't fatal, but it does
4584          * mean we disable MSI-X capabilities of the adapter. */
4585         adapter->msix_entries = kcalloc(v_budget,
4586                                         sizeof(struct msix_entry), GFP_KERNEL);
4587         if (adapter->msix_entries) {
4588                 for (vector = 0; vector < v_budget; vector++)
4589                         adapter->msix_entries[vector].entry = vector;
4590
4591                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4592
4593                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4594                         goto out;
4595         }
4596
4597         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4598         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4599         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4600         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4601         adapter->atr_sample_rate = 0;
4602         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4603                 ixgbe_disable_sriov(adapter);
4604
4605         err = ixgbe_set_num_queues(adapter);
4606         if (err)
4607                 return err;
4608
4609         err = pci_enable_msi(adapter->pdev);
4610         if (!err) {
4611                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4612         } else {
4613                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4614                              "Unable to allocate MSI interrupt, "
4615                              "falling back to legacy.  Error: %d\n", err);
4616                 /* reset err */
4617                 err = 0;
4618         }
4619
4620 out:
4621         return err;
4622 }
4623
4624 /**
4625  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4626  * @adapter: board private structure to initialize
4627  *
4628  * We allocate one q_vector per queue interrupt.  If allocation fails we
4629  * return -ENOMEM.
4630  **/
4631 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4632 {
4633         int q_idx, num_q_vectors;
4634         struct ixgbe_q_vector *q_vector;
4635         int napi_vectors;
4636         int (*poll)(struct napi_struct *, int);
4637
4638         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4639                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4640                 napi_vectors = adapter->num_rx_queues;
4641                 poll = &ixgbe_clean_rxtx_many;
4642         } else {
4643                 num_q_vectors = 1;
4644                 napi_vectors = 1;
4645                 poll = &ixgbe_poll;
4646         }
4647
4648         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4649                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4650                                         GFP_KERNEL, adapter->node);
4651                 if (!q_vector)
4652                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4653                                            GFP_KERNEL);
4654                 if (!q_vector)
4655                         goto err_out;
4656                 q_vector->adapter = adapter;
4657                 if (q_vector->txr_count && !q_vector->rxr_count)
4658                         q_vector->eitr = adapter->tx_eitr_param;
4659                 else
4660                         q_vector->eitr = adapter->rx_eitr_param;
4661                 q_vector->v_idx = q_idx;
4662                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4663                 adapter->q_vector[q_idx] = q_vector;
4664         }
4665
4666         return 0;
4667
4668 err_out:
4669         while (q_idx) {
4670                 q_idx--;
4671                 q_vector = adapter->q_vector[q_idx];
4672                 netif_napi_del(&q_vector->napi);
4673                 kfree(q_vector);
4674                 adapter->q_vector[q_idx] = NULL;
4675         }
4676         return -ENOMEM;
4677 }
4678
4679 /**
4680  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4681  * @adapter: board private structure to initialize
4682  *
4683  * This function frees the memory allocated to the q_vectors.  In addition if
4684  * NAPI is enabled it will delete any references to the NAPI struct prior
4685  * to freeing the q_vector.
4686  **/
4687 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4688 {
4689         int q_idx, num_q_vectors;
4690
4691         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4692                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4693         else
4694                 num_q_vectors = 1;
4695
4696         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4697                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4698                 adapter->q_vector[q_idx] = NULL;
4699                 netif_napi_del(&q_vector->napi);
4700                 kfree(q_vector);
4701         }
4702 }
4703
4704 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4705 {
4706         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4707                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4708                 pci_disable_msix(adapter->pdev);
4709                 kfree(adapter->msix_entries);
4710                 adapter->msix_entries = NULL;
4711         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4712                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4713                 pci_disable_msi(adapter->pdev);
4714         }
4715 }
4716
4717 /**
4718  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4719  * @adapter: board private structure to initialize
4720  *
4721  * We determine which interrupt scheme to use based on...
4722  * - Kernel support (MSI, MSI-X)
4723  *   - which can be user-defined (via MODULE_PARAM)
4724  * - Hardware queue count (num_*_queues)
4725  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4726  **/
4727 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4728 {
4729         int err;
4730
4731         /* Number of supported queues */
4732         err = ixgbe_set_num_queues(adapter);
4733         if (err)
4734                 return err;
4735
4736         err = ixgbe_set_interrupt_capability(adapter);
4737         if (err) {
4738                 e_dev_err("Unable to setup interrupt capabilities\n");
4739                 goto err_set_interrupt;
4740         }
4741
4742         err = ixgbe_alloc_q_vectors(adapter);
4743         if (err) {
4744                 e_dev_err("Unable to allocate memory for queue vectors\n");
4745                 goto err_alloc_q_vectors;
4746         }
4747
4748         err = ixgbe_alloc_queues(adapter);
4749         if (err) {
4750                 e_dev_err("Unable to allocate memory for queues\n");
4751                 goto err_alloc_queues;
4752         }
4753
4754         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4755                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4756                    adapter->num_rx_queues, adapter->num_tx_queues);
4757
4758         set_bit(__IXGBE_DOWN, &adapter->state);
4759
4760         return 0;
4761
4762 err_alloc_queues:
4763         ixgbe_free_q_vectors(adapter);
4764 err_alloc_q_vectors:
4765         ixgbe_reset_interrupt_capability(adapter);
4766 err_set_interrupt:
4767         return err;
4768 }
4769
4770 static void ring_free_rcu(struct rcu_head *head)
4771 {
4772         kfree(container_of(head, struct ixgbe_ring, rcu));
4773 }
4774
4775 /**
4776  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4777  * @adapter: board private structure to clear interrupt scheme on
4778  *
4779  * We go through and clear interrupt specific resources and reset the structure
4780  * to pre-load conditions
4781  **/
4782 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4783 {
4784         int i;
4785
4786         for (i = 0; i < adapter->num_tx_queues; i++) {
4787                 kfree(adapter->tx_ring[i]);
4788                 adapter->tx_ring[i] = NULL;
4789         }
4790         for (i = 0; i < adapter->num_rx_queues; i++) {
4791                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4792
4793                 /* ixgbe_get_stats64() might access this ring, we must wait
4794                  * a grace period before freeing it.
4795                  */
4796                 call_rcu(&ring->rcu, ring_free_rcu);
4797                 adapter->rx_ring[i] = NULL;
4798         }
4799
4800         ixgbe_free_q_vectors(adapter);
4801         ixgbe_reset_interrupt_capability(adapter);
4802 }
4803
4804 /**
4805  * ixgbe_sfp_timer - worker thread to find a missing module
4806  * @data: pointer to our adapter struct
4807  **/
4808 static void ixgbe_sfp_timer(unsigned long data)
4809 {
4810         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4811
4812         /*
4813          * Do the sfp_timer outside of interrupt context due to the
4814          * delays that sfp+ detection requires
4815          */
4816         schedule_work(&adapter->sfp_task);
4817 }
4818
4819 /**
4820  * ixgbe_sfp_task - worker thread to find a missing module
4821  * @work: pointer to work_struct containing our data
4822  **/
4823 static void ixgbe_sfp_task(struct work_struct *work)
4824 {
4825         struct ixgbe_adapter *adapter = container_of(work,
4826                                                      struct ixgbe_adapter,
4827                                                      sfp_task);
4828         struct ixgbe_hw *hw = &adapter->hw;
4829
4830         if ((hw->phy.type == ixgbe_phy_nl) &&
4831             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4832                 s32 ret = hw->phy.ops.identify_sfp(hw);
4833                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4834                         goto reschedule;
4835                 ret = hw->phy.ops.reset(hw);
4836                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4837                         e_dev_err("failed to initialize because an unsupported "
4838                                   "SFP+ module type was detected.\n");
4839                         e_dev_err("Reload the driver after installing a "
4840                                   "supported module.\n");
4841                         unregister_netdev(adapter->netdev);
4842                 } else {
4843                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4844                 }
4845                 /* don't need this routine any more */
4846                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4847         }
4848         return;
4849 reschedule:
4850         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4851                 mod_timer(&adapter->sfp_timer,
4852                           round_jiffies(jiffies + (2 * HZ)));
4853 }
4854
4855 /**
4856  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4857  * @adapter: board private structure to initialize
4858  *
4859  * ixgbe_sw_init initializes the Adapter private data structure.
4860  * Fields are initialized based on PCI device information and
4861  * OS network device settings (MTU size).
4862  **/
4863 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4864 {
4865         struct ixgbe_hw *hw = &adapter->hw;
4866         struct pci_dev *pdev = adapter->pdev;
4867         struct net_device *dev = adapter->netdev;
4868         unsigned int rss;
4869 #ifdef CONFIG_IXGBE_DCB
4870         int j;
4871         struct tc_configuration *tc;
4872 #endif
4873         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4874
4875         /* PCI config space info */
4876
4877         hw->vendor_id = pdev->vendor;
4878         hw->device_id = pdev->device;
4879         hw->revision_id = pdev->revision;
4880         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4881         hw->subsystem_device_id = pdev->subsystem_device;
4882
4883         /* Set capability flags */
4884         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4885         adapter->ring_feature[RING_F_RSS].indices = rss;
4886         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4887         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4888         if (hw->mac.type == ixgbe_mac_82598EB) {
4889                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4890                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4891                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4892         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4893                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4894                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4895                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4896                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4897                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4898                 if (dev->features & NETIF_F_NTUPLE) {
4899                         /* Flow Director perfect filter enabled */
4900                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4901                         adapter->atr_sample_rate = 0;
4902                         spin_lock_init(&adapter->fdir_perfect_lock);
4903                 } else {
4904                         /* Flow Director hash filters enabled */
4905                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4906                         adapter->atr_sample_rate = 20;
4907                 }
4908                 adapter->ring_feature[RING_F_FDIR].indices =
4909                                                          IXGBE_MAX_FDIR_INDICES;
4910                 adapter->fdir_pballoc = 0;
4911 #ifdef IXGBE_FCOE
4912                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4913                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4914                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4915 #ifdef CONFIG_IXGBE_DCB
4916                 /* Default traffic class to use for FCoE */
4917                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4918                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4919 #endif
4920 #endif /* IXGBE_FCOE */
4921         }
4922
4923 #ifdef CONFIG_IXGBE_DCB
4924         /* Configure DCB traffic classes */
4925         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4926                 tc = &adapter->dcb_cfg.tc_config[j];
4927                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4928                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4929                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4930                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4931                 tc->dcb_pfc = pfc_disabled;
4932         }
4933         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4934         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4935         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4936         adapter->dcb_cfg.pfc_mode_enable = false;
4937         adapter->dcb_cfg.round_robin_enable = false;
4938         adapter->dcb_set_bitmap = 0x00;
4939         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4940                            adapter->ring_feature[RING_F_DCB].indices);
4941
4942 #endif
4943
4944         /* default flow control settings */
4945         hw->fc.requested_mode = ixgbe_fc_full;
4946         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4947 #ifdef CONFIG_DCB
4948         adapter->last_lfc_mode = hw->fc.current_mode;
4949 #endif
4950         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4951         hw->fc.low_water = FC_LOW_WATER(max_frame);
4952         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4953         hw->fc.send_xon = true;
4954         hw->fc.disable_fc_autoneg = false;
4955
4956         /* enable itr by default in dynamic mode */
4957         adapter->rx_itr_setting = 1;
4958         adapter->rx_eitr_param = 20000;
4959         adapter->tx_itr_setting = 1;
4960         adapter->tx_eitr_param = 10000;
4961
4962         /* set defaults for eitr in MegaBytes */
4963         adapter->eitr_low = 10;
4964         adapter->eitr_high = 20;
4965
4966         /* set default ring sizes */
4967         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4968         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4969
4970         /* initialize eeprom parameters */
4971         if (ixgbe_init_eeprom_params_generic(hw)) {
4972                 e_dev_err("EEPROM initialization failed\n");
4973                 return -EIO;
4974         }
4975
4976         /* enable rx csum by default */
4977         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4978
4979         /* get assigned NUMA node */
4980         adapter->node = dev_to_node(&pdev->dev);
4981
4982         set_bit(__IXGBE_DOWN, &adapter->state);
4983
4984         return 0;
4985 }
4986
4987 /**
4988  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4989  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4990  *
4991  * Return 0 on success, negative on failure
4992  **/
4993 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4994 {
4995         struct device *dev = tx_ring->dev;
4996         int size;
4997
4998         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4999         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
5000         if (!tx_ring->tx_buffer_info)
5001                 tx_ring->tx_buffer_info = vmalloc(size);
5002         if (!tx_ring->tx_buffer_info)
5003                 goto err;
5004         memset(tx_ring->tx_buffer_info, 0, size);
5005
5006         /* round up to nearest 4K */
5007         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5008         tx_ring->size = ALIGN(tx_ring->size, 4096);
5009
5010         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5011                                            &tx_ring->dma, GFP_KERNEL);
5012         if (!tx_ring->desc)
5013                 goto err;
5014
5015         tx_ring->next_to_use = 0;
5016         tx_ring->next_to_clean = 0;
5017         tx_ring->work_limit = tx_ring->count;
5018         return 0;
5019
5020 err:
5021         vfree(tx_ring->tx_buffer_info);
5022         tx_ring->tx_buffer_info = NULL;
5023         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5024         return -ENOMEM;
5025 }
5026
5027 /**
5028  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5029  * @adapter: board private structure
5030  *
5031  * If this function returns with an error, then it's possible one or
5032  * more of the rings is populated (while the rest are not).  It is the
5033  * callers duty to clean those orphaned rings.
5034  *
5035  * Return 0 on success, negative on failure
5036  **/
5037 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5038 {
5039         int i, err = 0;
5040
5041         for (i = 0; i < adapter->num_tx_queues; i++) {
5042                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5043                 if (!err)
5044                         continue;
5045                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5046                 break;
5047         }
5048
5049         return err;
5050 }
5051
5052 /**
5053  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5054  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5055  *
5056  * Returns 0 on success, negative on failure
5057  **/
5058 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5059 {
5060         struct device *dev = rx_ring->dev;
5061         int size;
5062
5063         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5064         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5065         if (!rx_ring->rx_buffer_info)
5066                 rx_ring->rx_buffer_info = vmalloc(size);
5067         if (!rx_ring->rx_buffer_info)
5068                 goto err;
5069         memset(rx_ring->rx_buffer_info, 0, size);
5070
5071         /* Round up to nearest 4K */
5072         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5073         rx_ring->size = ALIGN(rx_ring->size, 4096);
5074
5075         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5076                                            &rx_ring->dma, GFP_KERNEL);
5077
5078         if (!rx_ring->desc)
5079                 goto err;
5080
5081         rx_ring->next_to_clean = 0;
5082         rx_ring->next_to_use = 0;
5083
5084         return 0;
5085 err:
5086         vfree(rx_ring->rx_buffer_info);
5087         rx_ring->rx_buffer_info = NULL;
5088         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5089         return -ENOMEM;
5090 }
5091
5092 /**
5093  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5094  * @adapter: board private structure
5095  *
5096  * If this function returns with an error, then it's possible one or
5097  * more of the rings is populated (while the rest are not).  It is the
5098  * callers duty to clean those orphaned rings.
5099  *
5100  * Return 0 on success, negative on failure
5101  **/
5102 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5103 {
5104         int i, err = 0;
5105
5106         for (i = 0; i < adapter->num_rx_queues; i++) {
5107                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5108                 if (!err)
5109                         continue;
5110                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5111                 break;
5112         }
5113
5114         return err;
5115 }
5116
5117 /**
5118  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5119  * @tx_ring: Tx descriptor ring for a specific queue
5120  *
5121  * Free all transmit software resources
5122  **/
5123 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5124 {
5125         ixgbe_clean_tx_ring(tx_ring);
5126
5127         vfree(tx_ring->tx_buffer_info);
5128         tx_ring->tx_buffer_info = NULL;
5129
5130         /* if not set, then don't free */
5131         if (!tx_ring->desc)
5132                 return;
5133
5134         dma_free_coherent(tx_ring->dev, tx_ring->size,
5135                           tx_ring->desc, tx_ring->dma);
5136
5137         tx_ring->desc = NULL;
5138 }
5139
5140 /**
5141  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5142  * @adapter: board private structure
5143  *
5144  * Free all transmit software resources
5145  **/
5146 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5147 {
5148         int i;
5149
5150         for (i = 0; i < adapter->num_tx_queues; i++)
5151                 if (adapter->tx_ring[i]->desc)
5152                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5153 }
5154
5155 /**
5156  * ixgbe_free_rx_resources - Free Rx Resources
5157  * @rx_ring: ring to clean the resources from
5158  *
5159  * Free all receive software resources
5160  **/
5161 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5162 {
5163         ixgbe_clean_rx_ring(rx_ring);
5164
5165         vfree(rx_ring->rx_buffer_info);
5166         rx_ring->rx_buffer_info = NULL;
5167
5168         /* if not set, then don't free */
5169         if (!rx_ring->desc)
5170                 return;
5171
5172         dma_free_coherent(rx_ring->dev, rx_ring->size,
5173                           rx_ring->desc, rx_ring->dma);
5174
5175         rx_ring->desc = NULL;
5176 }
5177
5178 /**
5179  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5180  * @adapter: board private structure
5181  *
5182  * Free all receive software resources
5183  **/
5184 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5185 {
5186         int i;
5187
5188         for (i = 0; i < adapter->num_rx_queues; i++)
5189                 if (adapter->rx_ring[i]->desc)
5190                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5191 }
5192
5193 /**
5194  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5195  * @netdev: network interface device structure
5196  * @new_mtu: new value for maximum frame size
5197  *
5198  * Returns 0 on success, negative on failure
5199  **/
5200 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5201 {
5202         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5203         struct ixgbe_hw *hw = &adapter->hw;
5204         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5205
5206         /* MTU < 68 is an error and causes problems on some kernels */
5207         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5208                 return -EINVAL;
5209
5210         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5211         /* must set new MTU before calling down or up */
5212         netdev->mtu = new_mtu;
5213
5214         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5215         hw->fc.low_water = FC_LOW_WATER(max_frame);
5216
5217         if (netif_running(netdev))
5218                 ixgbe_reinit_locked(adapter);
5219
5220         return 0;
5221 }
5222
5223 /**
5224  * ixgbe_open - Called when a network interface is made active
5225  * @netdev: network interface device structure
5226  *
5227  * Returns 0 on success, negative value on failure
5228  *
5229  * The open entry point is called when a network interface is made
5230  * active by the system (IFF_UP).  At this point all resources needed
5231  * for transmit and receive operations are allocated, the interrupt
5232  * handler is registered with the OS, the watchdog timer is started,
5233  * and the stack is notified that the interface is ready.
5234  **/
5235 static int ixgbe_open(struct net_device *netdev)
5236 {
5237         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5238         int err;
5239
5240         /* disallow open during test */
5241         if (test_bit(__IXGBE_TESTING, &adapter->state))
5242                 return -EBUSY;
5243
5244         netif_carrier_off(netdev);
5245
5246         /* allocate transmit descriptors */
5247         err = ixgbe_setup_all_tx_resources(adapter);
5248         if (err)
5249                 goto err_setup_tx;
5250
5251         /* allocate receive descriptors */
5252         err = ixgbe_setup_all_rx_resources(adapter);
5253         if (err)
5254                 goto err_setup_rx;
5255
5256         ixgbe_configure(adapter);
5257
5258         err = ixgbe_request_irq(adapter);
5259         if (err)
5260                 goto err_req_irq;
5261
5262         err = ixgbe_up_complete(adapter);
5263         if (err)
5264                 goto err_up;
5265
5266         netif_tx_start_all_queues(netdev);
5267
5268         return 0;
5269
5270 err_up:
5271         ixgbe_release_hw_control(adapter);
5272         ixgbe_free_irq(adapter);
5273 err_req_irq:
5274 err_setup_rx:
5275         ixgbe_free_all_rx_resources(adapter);
5276 err_setup_tx:
5277         ixgbe_free_all_tx_resources(adapter);
5278         ixgbe_reset(adapter);
5279
5280         return err;
5281 }
5282
5283 /**
5284  * ixgbe_close - Disables a network interface
5285  * @netdev: network interface device structure
5286  *
5287  * Returns 0, this is not allowed to fail
5288  *
5289  * The close entry point is called when an interface is de-activated
5290  * by the OS.  The hardware is still under the drivers control, but
5291  * needs to be disabled.  A global MAC reset is issued to stop the
5292  * hardware, and all transmit and receive resources are freed.
5293  **/
5294 static int ixgbe_close(struct net_device *netdev)
5295 {
5296         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5297
5298         ixgbe_down(adapter);
5299         ixgbe_free_irq(adapter);
5300
5301         ixgbe_free_all_tx_resources(adapter);
5302         ixgbe_free_all_rx_resources(adapter);
5303
5304         ixgbe_release_hw_control(adapter);
5305
5306         return 0;
5307 }
5308
5309 #ifdef CONFIG_PM
5310 static int ixgbe_resume(struct pci_dev *pdev)
5311 {
5312         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5313         struct net_device *netdev = adapter->netdev;
5314         u32 err;
5315
5316         pci_set_power_state(pdev, PCI_D0);
5317         pci_restore_state(pdev);
5318         /*
5319          * pci_restore_state clears dev->state_saved so call
5320          * pci_save_state to restore it.
5321          */
5322         pci_save_state(pdev);
5323
5324         err = pci_enable_device_mem(pdev);
5325         if (err) {
5326                 e_dev_err("Cannot enable PCI device from suspend\n");
5327                 return err;
5328         }
5329         pci_set_master(pdev);
5330
5331         pci_wake_from_d3(pdev, false);
5332
5333         err = ixgbe_init_interrupt_scheme(adapter);
5334         if (err) {
5335                 e_dev_err("Cannot initialize interrupts for device\n");
5336                 return err;
5337         }
5338
5339         ixgbe_reset(adapter);
5340
5341         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5342
5343         if (netif_running(netdev)) {
5344                 err = ixgbe_open(netdev);
5345                 if (err)
5346                         return err;
5347         }
5348
5349         netif_device_attach(netdev);
5350
5351         return 0;
5352 }
5353 #endif /* CONFIG_PM */
5354
5355 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5356 {
5357         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5358         struct net_device *netdev = adapter->netdev;
5359         struct ixgbe_hw *hw = &adapter->hw;
5360         u32 ctrl, fctrl;
5361         u32 wufc = adapter->wol;
5362 #ifdef CONFIG_PM
5363         int retval = 0;
5364 #endif
5365
5366         netif_device_detach(netdev);
5367
5368         if (netif_running(netdev)) {
5369                 ixgbe_down(adapter);
5370                 ixgbe_free_irq(adapter);
5371                 ixgbe_free_all_tx_resources(adapter);
5372                 ixgbe_free_all_rx_resources(adapter);
5373         }
5374
5375         ixgbe_clear_interrupt_scheme(adapter);
5376
5377 #ifdef CONFIG_PM
5378         retval = pci_save_state(pdev);
5379         if (retval)
5380                 return retval;
5381
5382 #endif
5383         if (wufc) {
5384                 ixgbe_set_rx_mode(netdev);
5385
5386                 /* turn on all-multi mode if wake on multicast is enabled */
5387                 if (wufc & IXGBE_WUFC_MC) {
5388                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5389                         fctrl |= IXGBE_FCTRL_MPE;
5390                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5391                 }
5392
5393                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5394                 ctrl |= IXGBE_CTRL_GIO_DIS;
5395                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5396
5397                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5398         } else {
5399                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5400                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5401         }
5402
5403         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5404                 pci_wake_from_d3(pdev, true);
5405         else
5406                 pci_wake_from_d3(pdev, false);
5407
5408         *enable_wake = !!wufc;
5409
5410         ixgbe_release_hw_control(adapter);
5411
5412         pci_disable_device(pdev);
5413
5414         return 0;
5415 }
5416
5417 #ifdef CONFIG_PM
5418 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5419 {
5420         int retval;
5421         bool wake;
5422
5423         retval = __ixgbe_shutdown(pdev, &wake);
5424         if (retval)
5425                 return retval;
5426
5427         if (wake) {
5428                 pci_prepare_to_sleep(pdev);
5429         } else {
5430                 pci_wake_from_d3(pdev, false);
5431                 pci_set_power_state(pdev, PCI_D3hot);
5432         }
5433
5434         return 0;
5435 }
5436 #endif /* CONFIG_PM */
5437
5438 static void ixgbe_shutdown(struct pci_dev *pdev)
5439 {
5440         bool wake;
5441
5442         __ixgbe_shutdown(pdev, &wake);
5443
5444         if (system_state == SYSTEM_POWER_OFF) {
5445                 pci_wake_from_d3(pdev, wake);
5446                 pci_set_power_state(pdev, PCI_D3hot);
5447         }
5448 }
5449
5450 /**
5451  * ixgbe_update_stats - Update the board statistics counters.
5452  * @adapter: board private structure
5453  **/
5454 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5455 {
5456         struct net_device *netdev = adapter->netdev;
5457         struct ixgbe_hw *hw = &adapter->hw;
5458         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5459         u64 total_mpc = 0;
5460         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5461         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5462         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5463         u64 bytes = 0, packets = 0;
5464
5465         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5466             test_bit(__IXGBE_RESETTING, &adapter->state))
5467                 return;
5468
5469         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5470                 u64 rsc_count = 0;
5471                 u64 rsc_flush = 0;
5472                 for (i = 0; i < 16; i++)
5473                         adapter->hw_rx_no_dma_resources +=
5474                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5475                 for (i = 0; i < adapter->num_rx_queues; i++) {
5476                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5477                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5478                 }
5479                 adapter->rsc_total_count = rsc_count;
5480                 adapter->rsc_total_flush = rsc_flush;
5481         }
5482
5483         for (i = 0; i < adapter->num_rx_queues; i++) {
5484                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5485                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5486                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5487                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5488                 bytes += rx_ring->stats.bytes;
5489                 packets += rx_ring->stats.packets;
5490         }
5491         adapter->non_eop_descs = non_eop_descs;
5492         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5493         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5494         netdev->stats.rx_bytes = bytes;
5495         netdev->stats.rx_packets = packets;
5496
5497         bytes = 0;
5498         packets = 0;
5499         /* gather some stats to the adapter struct that are per queue */
5500         for (i = 0; i < adapter->num_tx_queues; i++) {
5501                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5502                 restart_queue += tx_ring->tx_stats.restart_queue;
5503                 tx_busy += tx_ring->tx_stats.tx_busy;
5504                 bytes += tx_ring->stats.bytes;
5505                 packets += tx_ring->stats.packets;
5506         }
5507         adapter->restart_queue = restart_queue;
5508         adapter->tx_busy = tx_busy;
5509         netdev->stats.tx_bytes = bytes;
5510         netdev->stats.tx_packets = packets;
5511
5512         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5513         for (i = 0; i < 8; i++) {
5514                 /* for packet buffers not used, the register should read 0 */
5515                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5516                 missed_rx += mpc;
5517                 hwstats->mpc[i] += mpc;
5518                 total_mpc += hwstats->mpc[i];
5519                 if (hw->mac.type == ixgbe_mac_82598EB)
5520                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5521                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5522                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5523                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5524                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5525                 if (hw->mac.type == ixgbe_mac_82599EB) {
5526                         hwstats->pxonrxc[i] +=
5527                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5528                         hwstats->pxoffrxc[i] +=
5529                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5530                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5531                 } else {
5532                         hwstats->pxonrxc[i] +=
5533                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5534                         hwstats->pxoffrxc[i] +=
5535                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5536                 }
5537                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5538                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5539         }
5540         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5541         /* work around hardware counting issue */
5542         hwstats->gprc -= missed_rx;
5543
5544         /* 82598 hardware only has a 32 bit counter in the high register */
5545         if (hw->mac.type == ixgbe_mac_82599EB) {
5546                 u64 tmp;
5547                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5548                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5549                                                 /* 4 high bits of GORC */
5550                 hwstats->gorc += (tmp << 32);
5551                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5552                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5553                                                 /* 4 high bits of GOTC */
5554                 hwstats->gotc += (tmp << 32);
5555                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5556                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5557                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5558                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5559                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5560                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5561 #ifdef IXGBE_FCOE
5562                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5563                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5564                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5565                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5566                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5567                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5568 #endif /* IXGBE_FCOE */
5569         } else {
5570                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5571                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5572                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5573                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5574                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5575         }
5576         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5577         hwstats->bprc += bprc;
5578         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5579         if (hw->mac.type == ixgbe_mac_82598EB)
5580                 hwstats->mprc -= bprc;
5581         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5582         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5583         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5584         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5585         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5586         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5587         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5588         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5589         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5590         hwstats->lxontxc += lxon;
5591         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5592         hwstats->lxofftxc += lxoff;
5593         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5594         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5595         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5596         /*
5597          * 82598 errata - tx of flow control packets is included in tx counters
5598          */
5599         xon_off_tot = lxon + lxoff;
5600         hwstats->gptc -= xon_off_tot;
5601         hwstats->mptc -= xon_off_tot;
5602         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5603         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5604         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5605         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5606         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5607         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5608         hwstats->ptc64 -= xon_off_tot;
5609         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5610         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5611         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5612         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5613         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5614         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5615
5616         /* Fill out the OS statistics structure */
5617         netdev->stats.multicast = hwstats->mprc;
5618
5619         /* Rx Errors */
5620         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5621         netdev->stats.rx_dropped = 0;
5622         netdev->stats.rx_length_errors = hwstats->rlec;
5623         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5624         netdev->stats.rx_missed_errors = total_mpc;
5625 }
5626
5627 /**
5628  * ixgbe_watchdog - Timer Call-back
5629  * @data: pointer to adapter cast into an unsigned long
5630  **/
5631 static void ixgbe_watchdog(unsigned long data)
5632 {
5633         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5634         struct ixgbe_hw *hw = &adapter->hw;
5635         u64 eics = 0;
5636         int i;
5637
5638         /*
5639          *  Do the watchdog outside of interrupt context due to the lovely
5640          * delays that some of the newer hardware requires
5641          */
5642
5643         if (test_bit(__IXGBE_DOWN, &adapter->state))
5644                 goto watchdog_short_circuit;
5645
5646         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5647                 /*
5648                  * for legacy and MSI interrupts don't set any bits
5649                  * that are enabled for EIAM, because this operation
5650                  * would set *both* EIMS and EICS for any bit in EIAM
5651                  */
5652                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5653                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5654                 goto watchdog_reschedule;
5655         }
5656
5657         /* get one bit for every active tx/rx interrupt vector */
5658         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5659                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5660                 if (qv->rxr_count || qv->txr_count)
5661                         eics |= ((u64)1 << i);
5662         }
5663
5664         /* Cause software interrupt to ensure rx rings are cleaned */
5665         ixgbe_irq_rearm_queues(adapter, eics);
5666
5667 watchdog_reschedule:
5668         /* Reset the timer */
5669         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5670
5671 watchdog_short_circuit:
5672         schedule_work(&adapter->watchdog_task);
5673 }
5674
5675 /**
5676  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5677  * @work: pointer to work_struct containing our data
5678  **/
5679 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5680 {
5681         struct ixgbe_adapter *adapter = container_of(work,
5682                                                      struct ixgbe_adapter,
5683                                                      multispeed_fiber_task);
5684         struct ixgbe_hw *hw = &adapter->hw;
5685         u32 autoneg;
5686         bool negotiation;
5687
5688         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5689         autoneg = hw->phy.autoneg_advertised;
5690         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5691                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5692         hw->mac.autotry_restart = false;
5693         if (hw->mac.ops.setup_link)
5694                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5695         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5696         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5697 }
5698
5699 /**
5700  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5701  * @work: pointer to work_struct containing our data
5702  **/
5703 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5704 {
5705         struct ixgbe_adapter *adapter = container_of(work,
5706                                                      struct ixgbe_adapter,
5707                                                      sfp_config_module_task);
5708         struct ixgbe_hw *hw = &adapter->hw;
5709         u32 err;
5710
5711         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5712
5713         /* Time for electrical oscillations to settle down */
5714         msleep(100);
5715         err = hw->phy.ops.identify_sfp(hw);
5716
5717         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5718                 e_dev_err("failed to initialize because an unsupported SFP+ "
5719                           "module type was detected.\n");
5720                 e_dev_err("Reload the driver after installing a supported "
5721                           "module.\n");
5722                 unregister_netdev(adapter->netdev);
5723                 return;
5724         }
5725         hw->mac.ops.setup_sfp(hw);
5726
5727         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5728                 /* This will also work for DA Twinax connections */
5729                 schedule_work(&adapter->multispeed_fiber_task);
5730         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5731 }
5732
5733 /**
5734  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5735  * @work: pointer to work_struct containing our data
5736  **/
5737 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5738 {
5739         struct ixgbe_adapter *adapter = container_of(work,
5740                                                      struct ixgbe_adapter,
5741                                                      fdir_reinit_task);
5742         struct ixgbe_hw *hw = &adapter->hw;
5743         int i;
5744
5745         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5746                 for (i = 0; i < adapter->num_tx_queues; i++)
5747                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5748                                 &(adapter->tx_ring[i]->state));
5749         } else {
5750                 e_err(probe, "failed to finish FDIR re-initialization, "
5751                       "ignored adding FDIR ATR filters\n");
5752         }
5753         /* Done FDIR Re-initialization, enable transmits */
5754         netif_tx_start_all_queues(adapter->netdev);
5755 }
5756
5757 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5758
5759 /**
5760  * ixgbe_watchdog_task - worker thread to bring link up
5761  * @work: pointer to work_struct containing our data
5762  **/
5763 static void ixgbe_watchdog_task(struct work_struct *work)
5764 {
5765         struct ixgbe_adapter *adapter = container_of(work,
5766                                                      struct ixgbe_adapter,
5767                                                      watchdog_task);
5768         struct net_device *netdev = adapter->netdev;
5769         struct ixgbe_hw *hw = &adapter->hw;
5770         u32 link_speed;
5771         bool link_up;
5772         int i;
5773         struct ixgbe_ring *tx_ring;
5774         int some_tx_pending = 0;
5775
5776         mutex_lock(&ixgbe_watchdog_lock);
5777
5778         link_up = adapter->link_up;
5779         link_speed = adapter->link_speed;
5780
5781         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5782                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5783                 if (link_up) {
5784 #ifdef CONFIG_DCB
5785                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5786                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5787                                         hw->mac.ops.fc_enable(hw, i);
5788                         } else {
5789                                 hw->mac.ops.fc_enable(hw, 0);
5790                         }
5791 #else
5792                         hw->mac.ops.fc_enable(hw, 0);
5793 #endif
5794                 }
5795
5796                 if (link_up ||
5797                     time_after(jiffies, (adapter->link_check_timeout +
5798                                          IXGBE_TRY_LINK_TIMEOUT))) {
5799                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5800                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5801                 }
5802                 adapter->link_up = link_up;
5803                 adapter->link_speed = link_speed;
5804         }
5805
5806         if (link_up) {
5807                 if (!netif_carrier_ok(netdev)) {
5808                         bool flow_rx, flow_tx;
5809
5810                         if (hw->mac.type == ixgbe_mac_82599EB) {
5811                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5812                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5813                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5814                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5815                         } else {
5816                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5817                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5818                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5819                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5820                         }
5821
5822                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5823                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5824                                "10 Gbps" :
5825                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5826                                "1 Gbps" : "unknown speed")),
5827                                ((flow_rx && flow_tx) ? "RX/TX" :
5828                                (flow_rx ? "RX" :
5829                                (flow_tx ? "TX" : "None"))));
5830
5831                         netif_carrier_on(netdev);
5832                 } else {
5833                         /* Force detection of hung controller */
5834                         for (i = 0; i < adapter->num_tx_queues; i++) {
5835                                 tx_ring = adapter->tx_ring[i];
5836                                 set_check_for_tx_hang(tx_ring);
5837                         }
5838                 }
5839         } else {
5840                 adapter->link_up = false;
5841                 adapter->link_speed = 0;
5842                 if (netif_carrier_ok(netdev)) {
5843                         e_info(drv, "NIC Link is Down\n");
5844                         netif_carrier_off(netdev);
5845                 }
5846         }
5847
5848         if (!netif_carrier_ok(netdev)) {
5849                 for (i = 0; i < adapter->num_tx_queues; i++) {
5850                         tx_ring = adapter->tx_ring[i];
5851                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5852                                 some_tx_pending = 1;
5853                                 break;
5854                         }
5855                 }
5856
5857                 if (some_tx_pending) {
5858                         /* We've lost link, so the controller stops DMA,
5859                          * but we've got queued Tx work that's never going
5860                          * to get done, so reset controller to flush Tx.
5861                          * (Do the reset outside of interrupt context).
5862                          */
5863                          schedule_work(&adapter->reset_task);
5864                 }
5865         }
5866
5867         ixgbe_update_stats(adapter);
5868         mutex_unlock(&ixgbe_watchdog_lock);
5869 }
5870
5871 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5872                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5873                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5874 {
5875         struct ixgbe_adv_tx_context_desc *context_desc;
5876         unsigned int i;
5877         int err;
5878         struct ixgbe_tx_buffer *tx_buffer_info;
5879         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5880         u32 mss_l4len_idx, l4len;
5881
5882         if (skb_is_gso(skb)) {
5883                 if (skb_header_cloned(skb)) {
5884                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5885                         if (err)
5886                                 return err;
5887                 }
5888                 l4len = tcp_hdrlen(skb);
5889                 *hdr_len += l4len;
5890
5891                 if (protocol == htons(ETH_P_IP)) {
5892                         struct iphdr *iph = ip_hdr(skb);
5893                         iph->tot_len = 0;
5894                         iph->check = 0;
5895                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5896                                                                  iph->daddr, 0,
5897                                                                  IPPROTO_TCP,
5898                                                                  0);
5899                 } else if (skb_is_gso_v6(skb)) {
5900                         ipv6_hdr(skb)->payload_len = 0;
5901                         tcp_hdr(skb)->check =
5902                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5903                                              &ipv6_hdr(skb)->daddr,
5904                                              0, IPPROTO_TCP, 0);
5905                 }
5906
5907                 i = tx_ring->next_to_use;
5908
5909                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5910                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5911
5912                 /* VLAN MACLEN IPLEN */
5913                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5914                         vlan_macip_lens |=
5915                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5916                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5917                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5918                 *hdr_len += skb_network_offset(skb);
5919                 vlan_macip_lens |=
5920                     (skb_transport_header(skb) - skb_network_header(skb));
5921                 *hdr_len +=
5922                     (skb_transport_header(skb) - skb_network_header(skb));
5923                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5924                 context_desc->seqnum_seed = 0;
5925
5926                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5927                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5928                                    IXGBE_ADVTXD_DTYP_CTXT);
5929
5930                 if (protocol == htons(ETH_P_IP))
5931                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5932                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5933                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5934
5935                 /* MSS L4LEN IDX */
5936                 mss_l4len_idx =
5937                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5938                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5939                 /* use index 1 for TSO */
5940                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5941                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5942
5943                 tx_buffer_info->time_stamp = jiffies;
5944                 tx_buffer_info->next_to_watch = i;
5945
5946                 i++;
5947                 if (i == tx_ring->count)
5948                         i = 0;
5949                 tx_ring->next_to_use = i;
5950
5951                 return true;
5952         }
5953         return false;
5954 }
5955
5956 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5957                       __be16 protocol)
5958 {
5959         u32 rtn = 0;
5960
5961         switch (protocol) {
5962         case cpu_to_be16(ETH_P_IP):
5963                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5964                 switch (ip_hdr(skb)->protocol) {
5965                 case IPPROTO_TCP:
5966                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5967                         break;
5968                 case IPPROTO_SCTP:
5969                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5970                         break;
5971                 }
5972                 break;
5973         case cpu_to_be16(ETH_P_IPV6):
5974                 /* XXX what about other V6 headers?? */
5975                 switch (ipv6_hdr(skb)->nexthdr) {
5976                 case IPPROTO_TCP:
5977                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5978                         break;
5979                 case IPPROTO_SCTP:
5980                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5981                         break;
5982                 }
5983                 break;
5984         default:
5985                 if (unlikely(net_ratelimit()))
5986                         e_warn(probe, "partial checksum but proto=%x!\n",
5987                                protocol);
5988                 break;
5989         }
5990
5991         return rtn;
5992 }
5993
5994 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5995                           struct ixgbe_ring *tx_ring,
5996                           struct sk_buff *skb, u32 tx_flags,
5997                           __be16 protocol)
5998 {
5999         struct ixgbe_adv_tx_context_desc *context_desc;
6000         unsigned int i;
6001         struct ixgbe_tx_buffer *tx_buffer_info;
6002         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6003
6004         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6005             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6006                 i = tx_ring->next_to_use;
6007                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6008                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6009
6010                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6011                         vlan_macip_lens |=
6012                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6013                 vlan_macip_lens |= (skb_network_offset(skb) <<
6014                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6015                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6016                         vlan_macip_lens |= (skb_transport_header(skb) -
6017                                             skb_network_header(skb));
6018
6019                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6020                 context_desc->seqnum_seed = 0;
6021
6022                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6023                                     IXGBE_ADVTXD_DTYP_CTXT);
6024
6025                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6026                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6027
6028                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6029                 /* use index zero for tx checksum offload */
6030                 context_desc->mss_l4len_idx = 0;
6031
6032                 tx_buffer_info->time_stamp = jiffies;
6033                 tx_buffer_info->next_to_watch = i;
6034
6035                 i++;
6036                 if (i == tx_ring->count)
6037                         i = 0;
6038                 tx_ring->next_to_use = i;
6039
6040                 return true;
6041         }
6042
6043         return false;
6044 }
6045
6046 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6047                         struct ixgbe_ring *tx_ring,
6048                         struct sk_buff *skb, u32 tx_flags,
6049                         unsigned int first, const u8 hdr_len)
6050 {
6051         struct device *dev = tx_ring->dev;
6052         struct ixgbe_tx_buffer *tx_buffer_info;
6053         unsigned int len;
6054         unsigned int total = skb->len;
6055         unsigned int offset = 0, size, count = 0, i;
6056         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6057         unsigned int f;
6058         unsigned int bytecount = skb->len;
6059         u16 gso_segs = 1;
6060
6061         i = tx_ring->next_to_use;
6062
6063         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6064                 /* excluding fcoe_crc_eof for FCoE */
6065                 total -= sizeof(struct fcoe_crc_eof);
6066
6067         len = min(skb_headlen(skb), total);
6068         while (len) {
6069                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6070                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6071
6072                 tx_buffer_info->length = size;
6073                 tx_buffer_info->mapped_as_page = false;
6074                 tx_buffer_info->dma = dma_map_single(dev,
6075                                                      skb->data + offset,
6076                                                      size, DMA_TO_DEVICE);
6077                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6078                         goto dma_error;
6079                 tx_buffer_info->time_stamp = jiffies;
6080                 tx_buffer_info->next_to_watch = i;
6081
6082                 len -= size;
6083                 total -= size;
6084                 offset += size;
6085                 count++;
6086
6087                 if (len) {
6088                         i++;
6089                         if (i == tx_ring->count)
6090                                 i = 0;
6091                 }
6092         }
6093
6094         for (f = 0; f < nr_frags; f++) {
6095                 struct skb_frag_struct *frag;
6096
6097                 frag = &skb_shinfo(skb)->frags[f];
6098                 len = min((unsigned int)frag->size, total);
6099                 offset = frag->page_offset;
6100
6101                 while (len) {
6102                         i++;
6103                         if (i == tx_ring->count)
6104                                 i = 0;
6105
6106                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6107                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6108
6109                         tx_buffer_info->length = size;
6110                         tx_buffer_info->dma = dma_map_page(dev,
6111                                                            frag->page,
6112                                                            offset, size,
6113                                                            DMA_TO_DEVICE);
6114                         tx_buffer_info->mapped_as_page = true;
6115                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6116                                 goto dma_error;
6117                         tx_buffer_info->time_stamp = jiffies;
6118                         tx_buffer_info->next_to_watch = i;
6119
6120                         len -= size;
6121                         total -= size;
6122                         offset += size;
6123                         count++;
6124                 }
6125                 if (total == 0)
6126                         break;
6127         }
6128
6129         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6130                 gso_segs = skb_shinfo(skb)->gso_segs;
6131 #ifdef IXGBE_FCOE
6132         /* adjust for FCoE Sequence Offload */
6133         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6134                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6135                                         skb_shinfo(skb)->gso_size);
6136 #endif /* IXGBE_FCOE */
6137         bytecount += (gso_segs - 1) * hdr_len;
6138
6139         /* multiply data chunks by size of headers */
6140         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6141         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6142         tx_ring->tx_buffer_info[i].skb = skb;
6143         tx_ring->tx_buffer_info[first].next_to_watch = i;
6144
6145         return count;
6146
6147 dma_error:
6148         e_dev_err("TX DMA map failed\n");
6149
6150         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6151         tx_buffer_info->dma = 0;
6152         tx_buffer_info->time_stamp = 0;
6153         tx_buffer_info->next_to_watch = 0;
6154         if (count)
6155                 count--;
6156
6157         /* clear timestamp and dma mappings for remaining portion of packet */
6158         while (count--) {
6159                 if (i == 0)
6160                         i += tx_ring->count;
6161                 i--;
6162                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6163                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6164         }
6165
6166         return 0;
6167 }
6168
6169 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6170                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6171 {
6172         union ixgbe_adv_tx_desc *tx_desc = NULL;
6173         struct ixgbe_tx_buffer *tx_buffer_info;
6174         u32 olinfo_status = 0, cmd_type_len = 0;
6175         unsigned int i;
6176         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6177
6178         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6179
6180         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6181
6182         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6183                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6184
6185         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6186                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6187
6188                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6189                                  IXGBE_ADVTXD_POPTS_SHIFT;
6190
6191                 /* use index 1 context for tso */
6192                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6193                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6194                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6195                                          IXGBE_ADVTXD_POPTS_SHIFT;
6196
6197         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6198                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6199                                  IXGBE_ADVTXD_POPTS_SHIFT;
6200
6201         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6202                 olinfo_status |= IXGBE_ADVTXD_CC;
6203                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6204                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6205                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6206         }
6207
6208         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6209
6210         i = tx_ring->next_to_use;
6211         while (count--) {
6212                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6213                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6214                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6215                 tx_desc->read.cmd_type_len =
6216                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6217                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6218                 i++;
6219                 if (i == tx_ring->count)
6220                         i = 0;
6221         }
6222
6223         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6224
6225         /*
6226          * Force memory writes to complete before letting h/w
6227          * know there are new descriptors to fetch.  (Only
6228          * applicable for weak-ordered memory model archs,
6229          * such as IA-64).
6230          */
6231         wmb();
6232
6233         tx_ring->next_to_use = i;
6234         writel(i, tx_ring->tail);
6235 }
6236
6237 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6238                       u8 queue, u32 tx_flags, __be16 protocol)
6239 {
6240         struct ixgbe_atr_input atr_input;
6241         struct iphdr *iph = ip_hdr(skb);
6242         struct ethhdr *eth = (struct ethhdr *)skb->data;
6243         struct tcphdr *th;
6244         u16 vlan_id;
6245
6246         /* Right now, we support IPv4 w/ TCP only */
6247         if (protocol != htons(ETH_P_IP) ||
6248             iph->protocol != IPPROTO_TCP)
6249                 return;
6250
6251         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6252
6253         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6254                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6255
6256         th = tcp_hdr(skb);
6257
6258         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6259         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6260         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6261         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6262         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6263         /* src and dst are inverted, think how the receiver sees them */
6264         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6265         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6266
6267         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6268         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6269 }
6270
6271 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6272 {
6273         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6274         /* Herbert's original patch had:
6275          *  smp_mb__after_netif_stop_queue();
6276          * but since that doesn't exist yet, just open code it. */
6277         smp_mb();
6278
6279         /* We need to check again in a case another CPU has just
6280          * made room available. */
6281         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6282                 return -EBUSY;
6283
6284         /* A reprieve! - use start_queue because it doesn't call schedule */
6285         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6286         ++tx_ring->tx_stats.restart_queue;
6287         return 0;
6288 }
6289
6290 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6291 {
6292         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6293                 return 0;
6294         return __ixgbe_maybe_stop_tx(tx_ring, size);
6295 }
6296
6297 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6298 {
6299         struct ixgbe_adapter *adapter = netdev_priv(dev);
6300         int txq = smp_processor_id();
6301 #ifdef IXGBE_FCOE
6302         __be16 protocol;
6303
6304         protocol = vlan_get_protocol(skb);
6305
6306         if ((protocol == htons(ETH_P_FCOE)) ||
6307             (protocol == htons(ETH_P_FIP))) {
6308                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6309                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6310                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6311                         return txq;
6312 #ifdef CONFIG_IXGBE_DCB
6313                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6314                         txq = adapter->fcoe.up;
6315                         return txq;
6316 #endif
6317                 }
6318         }
6319 #endif
6320
6321         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6322                 while (unlikely(txq >= dev->real_num_tx_queues))
6323                         txq -= dev->real_num_tx_queues;
6324                 return txq;
6325         }
6326
6327         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6328                 if (skb->priority == TC_PRIO_CONTROL)
6329                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6330                 else
6331                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6332                                >> 13;
6333                 return txq;
6334         }
6335
6336         return skb_tx_hash(dev, skb);
6337 }
6338
6339 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6340                           struct ixgbe_adapter *adapter,
6341                           struct ixgbe_ring *tx_ring)
6342 {
6343         struct net_device *netdev = tx_ring->netdev;
6344         struct netdev_queue *txq;
6345         unsigned int first;
6346         unsigned int tx_flags = 0;
6347         u8 hdr_len = 0;
6348         int tso;
6349         int count = 0;
6350         unsigned int f;
6351         __be16 protocol;
6352
6353         protocol = vlan_get_protocol(skb);
6354
6355         if (vlan_tx_tag_present(skb)) {
6356                 tx_flags |= vlan_tx_tag_get(skb);
6357                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6358                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6359                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6360                 }
6361                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6362                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6363         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6364                    skb->priority != TC_PRIO_CONTROL) {
6365                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6366                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6367                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6368         }
6369
6370 #ifdef IXGBE_FCOE
6371         /* for FCoE with DCB, we force the priority to what
6372          * was specified by the switch */
6373         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6374             (protocol == htons(ETH_P_FCOE) ||
6375              protocol == htons(ETH_P_FIP))) {
6376 #ifdef CONFIG_IXGBE_DCB
6377                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6378                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6379                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6380                         tx_flags |= ((adapter->fcoe.up << 13)
6381                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6382                 }
6383 #endif
6384                 /* flag for FCoE offloads */
6385                 if (protocol == htons(ETH_P_FCOE))
6386                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6387         }
6388 #endif
6389
6390         /* four things can cause us to need a context descriptor */
6391         if (skb_is_gso(skb) ||
6392             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6393             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6394             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6395                 count++;
6396
6397         count += TXD_USE_COUNT(skb_headlen(skb));
6398         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6399                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6400
6401         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6402                 tx_ring->tx_stats.tx_busy++;
6403                 return NETDEV_TX_BUSY;
6404         }
6405
6406         first = tx_ring->next_to_use;
6407         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6408 #ifdef IXGBE_FCOE
6409                 /* setup tx offload for FCoE */
6410                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6411                 if (tso < 0) {
6412                         dev_kfree_skb_any(skb);
6413                         return NETDEV_TX_OK;
6414                 }
6415                 if (tso)
6416                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6417 #endif /* IXGBE_FCOE */
6418         } else {
6419                 if (protocol == htons(ETH_P_IP))
6420                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6421                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6422                                 protocol);
6423                 if (tso < 0) {
6424                         dev_kfree_skb_any(skb);
6425                         return NETDEV_TX_OK;
6426                 }
6427
6428                 if (tso)
6429                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6430                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6431                                        protocol) &&
6432                          (skb->ip_summed == CHECKSUM_PARTIAL))
6433                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6434         }
6435
6436         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6437         if (count) {
6438                 /* add the ATR filter if ATR is on */
6439                 if (tx_ring->atr_sample_rate) {
6440                         ++tx_ring->atr_count;
6441                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6442                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6443                                       &tx_ring->state)) {
6444                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6445                                           tx_flags, protocol);
6446                                 tx_ring->atr_count = 0;
6447                         }
6448                 }
6449                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6450                 txq->tx_bytes += skb->len;
6451                 txq->tx_packets++;
6452                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6453                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6454
6455         } else {
6456                 dev_kfree_skb_any(skb);
6457                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6458                 tx_ring->next_to_use = first;
6459         }
6460
6461         return NETDEV_TX_OK;
6462 }
6463
6464 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6465 {
6466         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6467         struct ixgbe_ring *tx_ring;
6468
6469         tx_ring = adapter->tx_ring[skb->queue_mapping];
6470         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6471 }
6472
6473 /**
6474  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6475  * @netdev: network interface device structure
6476  * @p: pointer to an address structure
6477  *
6478  * Returns 0 on success, negative on failure
6479  **/
6480 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6481 {
6482         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6483         struct ixgbe_hw *hw = &adapter->hw;
6484         struct sockaddr *addr = p;
6485
6486         if (!is_valid_ether_addr(addr->sa_data))
6487                 return -EADDRNOTAVAIL;
6488
6489         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6490         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6491
6492         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6493                             IXGBE_RAH_AV);
6494
6495         return 0;
6496 }
6497
6498 static int
6499 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6500 {
6501         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6502         struct ixgbe_hw *hw = &adapter->hw;
6503         u16 value;
6504         int rc;
6505
6506         if (prtad != hw->phy.mdio.prtad)
6507                 return -EINVAL;
6508         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6509         if (!rc)
6510                 rc = value;
6511         return rc;
6512 }
6513
6514 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6515                             u16 addr, u16 value)
6516 {
6517         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6518         struct ixgbe_hw *hw = &adapter->hw;
6519
6520         if (prtad != hw->phy.mdio.prtad)
6521                 return -EINVAL;
6522         return hw->phy.ops.write_reg(hw, addr, devad, value);
6523 }
6524
6525 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6526 {
6527         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6528
6529         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6530 }
6531
6532 /**
6533  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6534  * netdev->dev_addrs
6535  * @netdev: network interface device structure
6536  *
6537  * Returns non-zero on failure
6538  **/
6539 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6540 {
6541         int err = 0;
6542         struct ixgbe_adapter *adapter = netdev_priv(dev);
6543         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6544
6545         if (is_valid_ether_addr(mac->san_addr)) {
6546                 rtnl_lock();
6547                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6548                 rtnl_unlock();
6549         }
6550         return err;
6551 }
6552
6553 /**
6554  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6555  * netdev->dev_addrs
6556  * @netdev: network interface device structure
6557  *
6558  * Returns non-zero on failure
6559  **/
6560 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6561 {
6562         int err = 0;
6563         struct ixgbe_adapter *adapter = netdev_priv(dev);
6564         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6565
6566         if (is_valid_ether_addr(mac->san_addr)) {
6567                 rtnl_lock();
6568                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6569                 rtnl_unlock();
6570         }
6571         return err;
6572 }
6573
6574 #ifdef CONFIG_NET_POLL_CONTROLLER
6575 /*
6576  * Polling 'interrupt' - used by things like netconsole to send skbs
6577  * without having to re-enable interrupts. It's not called while
6578  * the interrupt routine is executing.
6579  */
6580 static void ixgbe_netpoll(struct net_device *netdev)
6581 {
6582         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6583         int i;
6584
6585         /* if interface is down do nothing */
6586         if (test_bit(__IXGBE_DOWN, &adapter->state))
6587                 return;
6588
6589         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6590         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6591                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6592                 for (i = 0; i < num_q_vectors; i++) {
6593                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6594                         ixgbe_msix_clean_many(0, q_vector);
6595                 }
6596         } else {
6597                 ixgbe_intr(adapter->pdev->irq, netdev);
6598         }
6599         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6600 }
6601 #endif
6602
6603 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6604                                                    struct rtnl_link_stats64 *stats)
6605 {
6606         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6607         int i;
6608
6609         /* accurate rx/tx bytes/packets stats */
6610         dev_txq_stats_fold(netdev, stats);
6611         rcu_read_lock();
6612         for (i = 0; i < adapter->num_rx_queues; i++) {
6613                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6614                 u64 bytes, packets;
6615                 unsigned int start;
6616
6617                 if (ring) {
6618                         do {
6619                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6620                                 packets = ring->stats.packets;
6621                                 bytes   = ring->stats.bytes;
6622                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6623                         stats->rx_packets += packets;
6624                         stats->rx_bytes   += bytes;
6625                 }
6626         }
6627         rcu_read_unlock();
6628         /* following stats updated by ixgbe_watchdog_task() */
6629         stats->multicast        = netdev->stats.multicast;
6630         stats->rx_errors        = netdev->stats.rx_errors;
6631         stats->rx_length_errors = netdev->stats.rx_length_errors;
6632         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6633         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6634         return stats;
6635 }
6636
6637
6638 static const struct net_device_ops ixgbe_netdev_ops = {
6639         .ndo_open               = ixgbe_open,
6640         .ndo_stop               = ixgbe_close,
6641         .ndo_start_xmit         = ixgbe_xmit_frame,
6642         .ndo_select_queue       = ixgbe_select_queue,
6643         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6644         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6645         .ndo_validate_addr      = eth_validate_addr,
6646         .ndo_set_mac_address    = ixgbe_set_mac,
6647         .ndo_change_mtu         = ixgbe_change_mtu,
6648         .ndo_tx_timeout         = ixgbe_tx_timeout,
6649         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6650         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6651         .ndo_do_ioctl           = ixgbe_ioctl,
6652         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6653         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6654         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6655         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6656         .ndo_get_stats64        = ixgbe_get_stats64,
6657 #ifdef CONFIG_NET_POLL_CONTROLLER
6658         .ndo_poll_controller    = ixgbe_netpoll,
6659 #endif
6660 #ifdef IXGBE_FCOE
6661         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6662         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6663         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6664         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6665         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6666 #endif /* IXGBE_FCOE */
6667 };
6668
6669 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6670                            const struct ixgbe_info *ii)
6671 {
6672 #ifdef CONFIG_PCI_IOV
6673         struct ixgbe_hw *hw = &adapter->hw;
6674         int err;
6675
6676         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6677                 return;
6678
6679         /* The 82599 supports up to 64 VFs per physical function
6680          * but this implementation limits allocation to 63 so that
6681          * basic networking resources are still available to the
6682          * physical function
6683          */
6684         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6685         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6686         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6687         if (err) {
6688                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6689                 goto err_novfs;
6690         }
6691         /* If call to enable VFs succeeded then allocate memory
6692          * for per VF control structures.
6693          */
6694         adapter->vfinfo =
6695                 kcalloc(adapter->num_vfs,
6696                         sizeof(struct vf_data_storage), GFP_KERNEL);
6697         if (adapter->vfinfo) {
6698                 /* Now that we're sure SR-IOV is enabled
6699                  * and memory allocated set up the mailbox parameters
6700                  */
6701                 ixgbe_init_mbx_params_pf(hw);
6702                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6703                        sizeof(hw->mbx.ops));
6704
6705                 /* Disable RSC when in SR-IOV mode */
6706                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6707                                      IXGBE_FLAG2_RSC_ENABLED);
6708                 return;
6709         }
6710
6711         /* Oh oh */
6712         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6713               "SRIOV disabled\n");
6714         pci_disable_sriov(adapter->pdev);
6715
6716 err_novfs:
6717         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6718         adapter->num_vfs = 0;
6719 #endif /* CONFIG_PCI_IOV */
6720 }
6721
6722 /**
6723  * ixgbe_probe - Device Initialization Routine
6724  * @pdev: PCI device information struct
6725  * @ent: entry in ixgbe_pci_tbl
6726  *
6727  * Returns 0 on success, negative on failure
6728  *
6729  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6730  * The OS initialization, configuring of the adapter private structure,
6731  * and a hardware reset occur.
6732  **/
6733 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6734                                  const struct pci_device_id *ent)
6735 {
6736         struct net_device *netdev;
6737         struct ixgbe_adapter *adapter = NULL;
6738         struct ixgbe_hw *hw;
6739         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6740         static int cards_found;
6741         int i, err, pci_using_dac;
6742         unsigned int indices = num_possible_cpus();
6743 #ifdef IXGBE_FCOE
6744         u16 device_caps;
6745 #endif
6746         u32 part_num, eec;
6747
6748         /* Catch broken hardware that put the wrong VF device ID in
6749          * the PCIe SR-IOV capability.
6750          */
6751         if (pdev->is_virtfn) {
6752                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6753                      pci_name(pdev), pdev->vendor, pdev->device);
6754                 return -EINVAL;
6755         }
6756
6757         err = pci_enable_device_mem(pdev);
6758         if (err)
6759                 return err;
6760
6761         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6762             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6763                 pci_using_dac = 1;
6764         } else {
6765                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6766                 if (err) {
6767                         err = dma_set_coherent_mask(&pdev->dev,
6768                                                     DMA_BIT_MASK(32));
6769                         if (err) {
6770                                 dev_err(&pdev->dev,
6771                                         "No usable DMA configuration, aborting\n");
6772                                 goto err_dma;
6773                         }
6774                 }
6775                 pci_using_dac = 0;
6776         }
6777
6778         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6779                                            IORESOURCE_MEM), ixgbe_driver_name);
6780         if (err) {
6781                 dev_err(&pdev->dev,
6782                         "pci_request_selected_regions failed 0x%x\n", err);
6783                 goto err_pci_reg;
6784         }
6785
6786         pci_enable_pcie_error_reporting(pdev);
6787
6788         pci_set_master(pdev);
6789         pci_save_state(pdev);
6790
6791         if (ii->mac == ixgbe_mac_82598EB)
6792                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6793         else
6794                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6795
6796         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6797 #ifdef IXGBE_FCOE
6798         indices += min_t(unsigned int, num_possible_cpus(),
6799                          IXGBE_MAX_FCOE_INDICES);
6800 #endif
6801         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6802         if (!netdev) {
6803                 err = -ENOMEM;
6804                 goto err_alloc_etherdev;
6805         }
6806
6807         SET_NETDEV_DEV(netdev, &pdev->dev);
6808
6809         adapter = netdev_priv(netdev);
6810         pci_set_drvdata(pdev, adapter);
6811
6812         adapter->netdev = netdev;
6813         adapter->pdev = pdev;
6814         hw = &adapter->hw;
6815         hw->back = adapter;
6816         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6817
6818         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6819                               pci_resource_len(pdev, 0));
6820         if (!hw->hw_addr) {
6821                 err = -EIO;
6822                 goto err_ioremap;
6823         }
6824
6825         for (i = 1; i <= 5; i++) {
6826                 if (pci_resource_len(pdev, i) == 0)
6827                         continue;
6828         }
6829
6830         netdev->netdev_ops = &ixgbe_netdev_ops;
6831         ixgbe_set_ethtool_ops(netdev);
6832         netdev->watchdog_timeo = 5 * HZ;
6833         strcpy(netdev->name, pci_name(pdev));
6834
6835         adapter->bd_number = cards_found;
6836
6837         /* Setup hw api */
6838         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6839         hw->mac.type  = ii->mac;
6840
6841         /* EEPROM */
6842         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6843         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6844         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6845         if (!(eec & (1 << 8)))
6846                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6847
6848         /* PHY */
6849         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6850         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6851         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6852         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6853         hw->phy.mdio.mmds = 0;
6854         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6855         hw->phy.mdio.dev = netdev;
6856         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6857         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6858
6859         /* set up this timer and work struct before calling get_invariants
6860          * which might start the timer
6861          */
6862         init_timer(&adapter->sfp_timer);
6863         adapter->sfp_timer.function = ixgbe_sfp_timer;
6864         adapter->sfp_timer.data = (unsigned long) adapter;
6865
6866         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6867
6868         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6869         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6870
6871         /* a new SFP+ module arrival, called from GPI SDP2 context */
6872         INIT_WORK(&adapter->sfp_config_module_task,
6873                   ixgbe_sfp_config_module_task);
6874
6875         ii->get_invariants(hw);
6876
6877         /* setup the private structure */
6878         err = ixgbe_sw_init(adapter);
6879         if (err)
6880                 goto err_sw_init;
6881
6882         /* Make it possible the adapter to be woken up via WOL */
6883         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6884                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6885
6886         /*
6887          * If there is a fan on this device and it has failed log the
6888          * failure.
6889          */
6890         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6891                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6892                 if (esdp & IXGBE_ESDP_SDP1)
6893                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6894         }
6895
6896         /* reset_hw fills in the perm_addr as well */
6897         hw->phy.reset_if_overtemp = true;
6898         err = hw->mac.ops.reset_hw(hw);
6899         hw->phy.reset_if_overtemp = false;
6900         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6901             hw->mac.type == ixgbe_mac_82598EB) {
6902                 /*
6903                  * Start a kernel thread to watch for a module to arrive.
6904                  * Only do this for 82598, since 82599 will generate
6905                  * interrupts on module arrival.
6906                  */
6907                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6908                 mod_timer(&adapter->sfp_timer,
6909                           round_jiffies(jiffies + (2 * HZ)));
6910                 err = 0;
6911         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6912                 e_dev_err("failed to initialize because an unsupported SFP+ "
6913                           "module type was detected.\n");
6914                 e_dev_err("Reload the driver after installing a supported "
6915                           "module.\n");
6916                 goto err_sw_init;
6917         } else if (err) {
6918                 e_dev_err("HW Init failed: %d\n", err);
6919                 goto err_sw_init;
6920         }
6921
6922         ixgbe_probe_vf(adapter, ii);
6923
6924         netdev->features = NETIF_F_SG |
6925                            NETIF_F_IP_CSUM |
6926                            NETIF_F_HW_VLAN_TX |
6927                            NETIF_F_HW_VLAN_RX |
6928                            NETIF_F_HW_VLAN_FILTER;
6929
6930         netdev->features |= NETIF_F_IPV6_CSUM;
6931         netdev->features |= NETIF_F_TSO;
6932         netdev->features |= NETIF_F_TSO6;
6933         netdev->features |= NETIF_F_GRO;
6934
6935         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6936                 netdev->features |= NETIF_F_SCTP_CSUM;
6937
6938         netdev->vlan_features |= NETIF_F_TSO;
6939         netdev->vlan_features |= NETIF_F_TSO6;
6940         netdev->vlan_features |= NETIF_F_IP_CSUM;
6941         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6942         netdev->vlan_features |= NETIF_F_SG;
6943
6944         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6945                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6946                                     IXGBE_FLAG_DCB_ENABLED);
6947         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6948                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6949
6950 #ifdef CONFIG_IXGBE_DCB
6951         netdev->dcbnl_ops = &dcbnl_ops;
6952 #endif
6953
6954 #ifdef IXGBE_FCOE
6955         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6956                 if (hw->mac.ops.get_device_caps) {
6957                         hw->mac.ops.get_device_caps(hw, &device_caps);
6958                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6959                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6960                 }
6961         }
6962         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6963                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6964                 netdev->vlan_features |= NETIF_F_FSO;
6965                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6966         }
6967 #endif /* IXGBE_FCOE */
6968         if (pci_using_dac) {
6969                 netdev->features |= NETIF_F_HIGHDMA;
6970                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6971         }
6972
6973         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6974                 netdev->features |= NETIF_F_LRO;
6975
6976         /* make sure the EEPROM is good */
6977         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6978                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6979                 err = -EIO;
6980                 goto err_eeprom;
6981         }
6982
6983         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6984         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6985
6986         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6987                 e_dev_err("invalid MAC address\n");
6988                 err = -EIO;
6989                 goto err_eeprom;
6990         }
6991
6992         /* power down the optics */
6993         if (hw->phy.multispeed_fiber)
6994                 hw->mac.ops.disable_tx_laser(hw);
6995
6996         init_timer(&adapter->watchdog_timer);
6997         adapter->watchdog_timer.function = ixgbe_watchdog;
6998         adapter->watchdog_timer.data = (unsigned long)adapter;
6999
7000         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7001         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7002
7003         err = ixgbe_init_interrupt_scheme(adapter);
7004         if (err)
7005                 goto err_sw_init;
7006
7007         switch (pdev->device) {
7008         case IXGBE_DEV_ID_82599_KX4:
7009                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7010                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7011                 break;
7012         default:
7013                 adapter->wol = 0;
7014                 break;
7015         }
7016         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7017
7018         /* pick up the PCI bus settings for reporting later */
7019         hw->mac.ops.get_bus_info(hw);
7020
7021         /* print bus type/speed/width info */
7022         e_dev_info("(PCI Express:%s:%s) %pM\n",
7023                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7024                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7025                     "Unknown"),
7026                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7027                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7028                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7029                     "Unknown"),
7030                    netdev->dev_addr);
7031         ixgbe_read_pba_num_generic(hw, &part_num);
7032         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7033                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7034                            "PBA No: %06x-%03x\n",
7035                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7036                            (part_num >> 8), (part_num & 0xff));
7037         else
7038                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7039                            hw->mac.type, hw->phy.type,
7040                            (part_num >> 8), (part_num & 0xff));
7041
7042         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7043                 e_dev_warn("PCI-Express bandwidth available for this card is "
7044                            "not sufficient for optimal performance.\n");
7045                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7046                            "is required.\n");
7047         }
7048
7049         /* save off EEPROM version number */
7050         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7051
7052         /* reset the hardware with the new settings */
7053         err = hw->mac.ops.start_hw(hw);
7054
7055         if (err == IXGBE_ERR_EEPROM_VERSION) {
7056                 /* We are running on a pre-production device, log a warning */
7057                 e_dev_warn("This device is a pre-production adapter/LOM. "
7058                            "Please be aware there may be issues associated "
7059                            "with your hardware.  If you are experiencing "
7060                            "problems please contact your Intel or hardware "
7061                            "representative who provided you with this "
7062                            "hardware.\n");
7063         }
7064         strcpy(netdev->name, "eth%d");
7065         err = register_netdev(netdev);
7066         if (err)
7067                 goto err_register;
7068
7069         /* carrier off reporting is important to ethtool even BEFORE open */
7070         netif_carrier_off(netdev);
7071
7072         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7073             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7074                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7075
7076         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7077                 INIT_WORK(&adapter->check_overtemp_task,
7078                           ixgbe_check_overtemp_task);
7079 #ifdef CONFIG_IXGBE_DCA
7080         if (dca_add_requester(&pdev->dev) == 0) {
7081                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7082                 ixgbe_setup_dca(adapter);
7083         }
7084 #endif
7085         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7086                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7087                 for (i = 0; i < adapter->num_vfs; i++)
7088                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7089         }
7090
7091         /* add san mac addr to netdev */
7092         ixgbe_add_sanmac_netdev(netdev);
7093
7094         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7095         cards_found++;
7096         return 0;
7097
7098 err_register:
7099         ixgbe_release_hw_control(adapter);
7100         ixgbe_clear_interrupt_scheme(adapter);
7101 err_sw_init:
7102 err_eeprom:
7103         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7104                 ixgbe_disable_sriov(adapter);
7105         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7106         del_timer_sync(&adapter->sfp_timer);
7107         cancel_work_sync(&adapter->sfp_task);
7108         cancel_work_sync(&adapter->multispeed_fiber_task);
7109         cancel_work_sync(&adapter->sfp_config_module_task);
7110         iounmap(hw->hw_addr);
7111 err_ioremap:
7112         free_netdev(netdev);
7113 err_alloc_etherdev:
7114         pci_release_selected_regions(pdev,
7115                                      pci_select_bars(pdev, IORESOURCE_MEM));
7116 err_pci_reg:
7117 err_dma:
7118         pci_disable_device(pdev);
7119         return err;
7120 }
7121
7122 /**
7123  * ixgbe_remove - Device Removal Routine
7124  * @pdev: PCI device information struct
7125  *
7126  * ixgbe_remove is called by the PCI subsystem to alert the driver
7127  * that it should release a PCI device.  The could be caused by a
7128  * Hot-Plug event, or because the driver is going to be removed from
7129  * memory.
7130  **/
7131 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7132 {
7133         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7134         struct net_device *netdev = adapter->netdev;
7135
7136         set_bit(__IXGBE_DOWN, &adapter->state);
7137         /* clear the module not found bit to make sure the worker won't
7138          * reschedule
7139          */
7140         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7141         del_timer_sync(&adapter->watchdog_timer);
7142
7143         del_timer_sync(&adapter->sfp_timer);
7144         cancel_work_sync(&adapter->watchdog_task);
7145         cancel_work_sync(&adapter->sfp_task);
7146         cancel_work_sync(&adapter->multispeed_fiber_task);
7147         cancel_work_sync(&adapter->sfp_config_module_task);
7148         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7149             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7150                 cancel_work_sync(&adapter->fdir_reinit_task);
7151         flush_scheduled_work();
7152
7153 #ifdef CONFIG_IXGBE_DCA
7154         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7155                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7156                 dca_remove_requester(&pdev->dev);
7157                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7158         }
7159
7160 #endif
7161 #ifdef IXGBE_FCOE
7162         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7163                 ixgbe_cleanup_fcoe(adapter);
7164
7165 #endif /* IXGBE_FCOE */
7166
7167         /* remove the added san mac */
7168         ixgbe_del_sanmac_netdev(netdev);
7169
7170         if (netdev->reg_state == NETREG_REGISTERED)
7171                 unregister_netdev(netdev);
7172
7173         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7174                 ixgbe_disable_sriov(adapter);
7175
7176         ixgbe_clear_interrupt_scheme(adapter);
7177
7178         ixgbe_release_hw_control(adapter);
7179
7180         iounmap(adapter->hw.hw_addr);
7181         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7182                                      IORESOURCE_MEM));
7183
7184         e_dev_info("complete\n");
7185
7186         free_netdev(netdev);
7187
7188         pci_disable_pcie_error_reporting(pdev);
7189
7190         pci_disable_device(pdev);
7191 }
7192
7193 /**
7194  * ixgbe_io_error_detected - called when PCI error is detected
7195  * @pdev: Pointer to PCI device
7196  * @state: The current pci connection state
7197  *
7198  * This function is called after a PCI bus error affecting
7199  * this device has been detected.
7200  */
7201 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7202                                                 pci_channel_state_t state)
7203 {
7204         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7205         struct net_device *netdev = adapter->netdev;
7206
7207         netif_device_detach(netdev);
7208
7209         if (state == pci_channel_io_perm_failure)
7210                 return PCI_ERS_RESULT_DISCONNECT;
7211
7212         if (netif_running(netdev))
7213                 ixgbe_down(adapter);
7214         pci_disable_device(pdev);
7215
7216         /* Request a slot reset. */
7217         return PCI_ERS_RESULT_NEED_RESET;
7218 }
7219
7220 /**
7221  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7222  * @pdev: Pointer to PCI device
7223  *
7224  * Restart the card from scratch, as if from a cold-boot.
7225  */
7226 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7227 {
7228         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7229         pci_ers_result_t result;
7230         int err;
7231
7232         if (pci_enable_device_mem(pdev)) {
7233                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7234                 result = PCI_ERS_RESULT_DISCONNECT;
7235         } else {
7236                 pci_set_master(pdev);
7237                 pci_restore_state(pdev);
7238                 pci_save_state(pdev);
7239
7240                 pci_wake_from_d3(pdev, false);
7241
7242                 ixgbe_reset(adapter);
7243                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7244                 result = PCI_ERS_RESULT_RECOVERED;
7245         }
7246
7247         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7248         if (err) {
7249                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7250                           "failed 0x%0x\n", err);
7251                 /* non-fatal, continue */
7252         }
7253
7254         return result;
7255 }
7256
7257 /**
7258  * ixgbe_io_resume - called when traffic can start flowing again.
7259  * @pdev: Pointer to PCI device
7260  *
7261  * This callback is called when the error recovery driver tells us that
7262  * its OK to resume normal operation.
7263  */
7264 static void ixgbe_io_resume(struct pci_dev *pdev)
7265 {
7266         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7267         struct net_device *netdev = adapter->netdev;
7268
7269         if (netif_running(netdev)) {
7270                 if (ixgbe_up(adapter)) {
7271                         e_info(probe, "ixgbe_up failed after reset\n");
7272                         return;
7273                 }
7274         }
7275
7276         netif_device_attach(netdev);
7277 }
7278
7279 static struct pci_error_handlers ixgbe_err_handler = {
7280         .error_detected = ixgbe_io_error_detected,
7281         .slot_reset = ixgbe_io_slot_reset,
7282         .resume = ixgbe_io_resume,
7283 };
7284
7285 static struct pci_driver ixgbe_driver = {
7286         .name     = ixgbe_driver_name,
7287         .id_table = ixgbe_pci_tbl,
7288         .probe    = ixgbe_probe,
7289         .remove   = __devexit_p(ixgbe_remove),
7290 #ifdef CONFIG_PM
7291         .suspend  = ixgbe_suspend,
7292         .resume   = ixgbe_resume,
7293 #endif
7294         .shutdown = ixgbe_shutdown,
7295         .err_handler = &ixgbe_err_handler
7296 };
7297
7298 /**
7299  * ixgbe_init_module - Driver Registration Routine
7300  *
7301  * ixgbe_init_module is the first routine called when the driver is
7302  * loaded. All it does is register with the PCI subsystem.
7303  **/
7304 static int __init ixgbe_init_module(void)
7305 {
7306         int ret;
7307         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7308         pr_info("%s\n", ixgbe_copyright);
7309
7310 #ifdef CONFIG_IXGBE_DCA
7311         dca_register_notify(&dca_notifier);
7312 #endif
7313
7314         ret = pci_register_driver(&ixgbe_driver);
7315         return ret;
7316 }
7317
7318 module_init(ixgbe_init_module);
7319
7320 /**
7321  * ixgbe_exit_module - Driver Exit Cleanup Routine
7322  *
7323  * ixgbe_exit_module is called just before the driver is removed
7324  * from memory.
7325  **/
7326 static void __exit ixgbe_exit_module(void)
7327 {
7328 #ifdef CONFIG_IXGBE_DCA
7329         dca_unregister_notify(&dca_notifier);
7330 #endif
7331         pci_unregister_driver(&ixgbe_driver);
7332         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7333 }
7334
7335 #ifdef CONFIG_IXGBE_DCA
7336 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7337                             void *p)
7338 {
7339         int ret_val;
7340
7341         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7342                                          __ixgbe_notify_dca);
7343
7344         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7345 }
7346
7347 #endif /* CONFIG_IXGBE_DCA */
7348
7349 /**
7350  * ixgbe_get_hw_dev return device
7351  * used by hardware layer to print debugging information
7352  **/
7353 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7354 {
7355         struct ixgbe_adapter *adapter = hw->back;
7356         return adapter->netdev;
7357 }
7358
7359 module_exit(ixgbe_exit_module);
7360
7361 /* ixgbe_main.c */