drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         switch (adapter->hw.mac.type) {
 593         case ixgbe_mac_82598EB:
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596                 break;
 597         case ixgbe_mac_82599EB:
 598                 mask = (qmask & 0xFFFFFFFF);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 600                 mask = (qmask >> 32);
 601                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 602                 break;
 603         default:
 604                 break;
 605         }
 606 }
 607
 608 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 609                                       struct ixgbe_tx_buffer *tx_buffer_info)
 610 {
 611         if (tx_buffer_info->dma) {
 612                 if (tx_buffer_info->mapped_as_page)
 613                         dma_unmap_page(tx_ring->dev,
 614                                        tx_buffer_info->dma,
 615                                        tx_buffer_info->length,
 616                                        DMA_TO_DEVICE);
 617                 else
 618                         dma_unmap_single(tx_ring->dev,
 619                                          tx_buffer_info->dma,
 620                                          tx_buffer_info->length,
 621                                          DMA_TO_DEVICE);
 622                 tx_buffer_info->dma = 0;
 623         }
 624         if (tx_buffer_info->skb) {
 625                 dev_kfree_skb_any(tx_buffer_info->skb);
 626                 tx_buffer_info->skb = NULL;
 627         }
 628         tx_buffer_info->time_stamp = 0;
 629         /* tx_buffer_info must be completely set up in the transmit path */
 630 }
 631
 632 /**
 633  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 634  * @adapter: driver private struct
 635  * @index: reg idx of queue to query (0-127)
 636  *
 637  * Helper function to determine the traffic index for a paticular
 638  * register index.
 639  *
 640  * Returns : a tc index for use in range 0-7, or 0-3
 641  */
 642 u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 643 {
 644         int tc = -1;
 645         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 646
 647         /* if DCB is not enabled the queues have no TC */
 648         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 649                 return tc;
 650
 651         /* check valid range */
 652         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 653                 return tc;
 654
 655         switch (adapter->hw.mac.type) {
 656         case ixgbe_mac_82598EB:
 657                 tc = reg_idx >> 2;
 658                 break;
 659         default:
 660                 if (dcb_i != 4 && dcb_i != 8)
 661                         break;
 662
 663                 /* if VMDq is enabled the lowest order bits determine TC */
 664                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 665                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 666                         tc = reg_idx & (dcb_i - 1);
 667                         break;
 668                 }
 669
 670                 /*
 671                  * Convert the reg_idx into the correct TC. This bitmask
 672                  * targets the last full 32 ring traffic class and assigns
 673                  * it a value of 1. From there the rest of the rings are
 674                  * based on shifting the mask further up to include the
 675                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 676                  * will only ever be 8 or 4 and that reg_idx will never
 677                  * be greater then 128. The code without the power of 2
 678                  * optimizations would be:
 679                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 680                  */
 681                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 682                 tc >>= 9 - (reg_idx >> 5);
 683         }
 684
 685         return tc;
 686 }
 687
 688 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 689 {
 690         struct ixgbe_hw *hw = &adapter->hw;
 691         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 692         u32 data = 0;
 693         u32 xoff[8] = {0};
 694         int i;
 695
 696         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 697             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 698                 switch (hw->mac.type) {
 699                 case ixgbe_mac_82598EB:
 700                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 701                         break;
 702                 default:
 703                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 704                 }
 705                 hwstats->lxoffrxc += data;
 706
 707                 /* refill credits (no tx hang) if we received xoff */
 708                 if (!data)
 709                         return;
 710
 711                 for (i = 0; i < adapter->num_tx_queues; i++)
 712                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 713                                   &adapter->tx_ring[i]->state);
 714                 return;
 715         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 716                 return;
 717
 718         /* update stats for each tc, only valid with PFC enabled */
 719         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 720                 switch (hw->mac.type) {
 721                 case ixgbe_mac_82598EB:
 722                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 723                         break;
 724                 default:
 725                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 726                 }
 727                 hwstats->pxoffrxc[i] += xoff[i];
 728         }
 729
 730         /* disarm tx queues that have received xoff frames */
 731         for (i = 0; i < adapter->num_tx_queues; i++) {
 732                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 733                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 734
 735                 if (xoff[tc])
 736                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 737         }
 738 }
 739
 740 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 741 {
 742         return ring->tx_stats.completed;
 743 }
 744
 745 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 746 {
 747         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 748         struct ixgbe_hw *hw = &adapter->hw;
 749
 750         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 751         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 752
 753         if (head != tail)
 754                 return (head < tail) ?
 755                         tail - head : (tail + ring->count - head);
 756
 757         return 0;
 758 }
 759
 760 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 761 {
 762         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 763         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 764         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 765         bool ret = false;
 766
 767         clear_check_for_tx_hang(tx_ring);
 768
 769         /*
 770          * Check for a hung queue, but be thorough. This verifies
 771          * that a transmit has been completed since the previous
 772          * check AND there is at least one packet pending. The
 773          * ARMED bit is set to indicate a potential hang. The
 774          * bit is cleared if a pause frame is received to remove
 775          * false hang detection due to PFC or 802.3x frames. By
 776          * requiring this to fail twice we avoid races with
 777          * pfc clearing the ARMED bit and conditions where we
 778          * run the check_tx_hang logic with a transmit completion
 779          * pending but without time to complete it yet.
 780          */
 781         if ((tx_done_old == tx_done) && tx_pending) {
 782                 /* make sure it is true for two checks in a row */
 783                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 784                                        &tx_ring->state);
 785         } else {
 786                 /* update completed stats and continue */
 787                 tx_ring->tx_stats.tx_done_old = tx_done;
 788                 /* reset the countdown */
 789                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 790         }
 791
 792         return ret;
 793 }
 794
 795 #define IXGBE_MAX_TXD_PWR       14
 796 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 797
 798 /* Tx Descriptors needed, worst case */
 799 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 800                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 801 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 802         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 803
 804 static void ixgbe_tx_timeout(struct net_device *netdev);
 805
 806 /**
 807  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 808  * @q_vector: structure containing interrupt and ring information
 809  * @tx_ring: tx ring to clean
 810  **/
 811 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 812                                struct ixgbe_ring *tx_ring)
 813 {
 814         struct ixgbe_adapter *adapter = q_vector->adapter;
 815         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 816         struct ixgbe_tx_buffer *tx_buffer_info;
 817         unsigned int total_bytes = 0, total_packets = 0;
 818         u16 i, eop, count = 0;
 819
 820         i = tx_ring->next_to_clean;
 821         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 822         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 823
 824         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 825                (count < tx_ring->work_limit)) {
 826                 bool cleaned = false;
 827                 rmb(); /* read buffer_info after eop_desc */
 828                 for ( ; !cleaned; count++) {
 829                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 830                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 831
 832                         tx_desc->wb.status = 0;
 833                         cleaned = (i == eop);
 834
 835                         i++;
 836                         if (i == tx_ring->count)
 837                                 i = 0;
 838
 839                         if (cleaned && tx_buffer_info->skb) {
 840                                 total_bytes += tx_buffer_info->bytecount;
 841                                 total_packets += tx_buffer_info->gso_segs;
 842                         }
 843
 844                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 845                                                          tx_buffer_info);
 846                 }
 847
 848                 tx_ring->tx_stats.completed++;
 849                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 850                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 851         }
 852
 853         tx_ring->next_to_clean = i;
 854         tx_ring->total_bytes += total_bytes;
 855         tx_ring->total_packets += total_packets;
 856         u64_stats_update_begin(&tx_ring->syncp);
 857         tx_ring->stats.packets += total_packets;
 858         tx_ring->stats.bytes += total_bytes;
 859         u64_stats_update_end(&tx_ring->syncp);
 860
 861         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 862                 /* schedule immediate reset if we believe we hung */
 863                 struct ixgbe_hw *hw = &adapter->hw;
 864                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 865                 e_err(drv, "Detected Tx Unit Hang\n"
 866                         "  Tx Queue             <%d>\n"
 867                         "  TDH, TDT             <%x>, <%x>\n"
 868                         "  next_to_use          <%x>\n"
 869                         "  next_to_clean        <%x>\n"
 870                         "tx_buffer_info[next_to_clean]\n"
 871                         "  time_stamp           <%lx>\n"
 872                         "  jiffies              <%lx>\n",
 873                         tx_ring->queue_index,
 874                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 875                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 876                         tx_ring->next_to_use, eop,
 877                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 878
 879                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 880
 881                 e_info(probe,
 882                        "tx hang %d detected on queue %d, resetting adapter\n",
 883                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 884
 885                 /* schedule immediate reset if we believe we hung */
 886                 ixgbe_tx_timeout(adapter->netdev);
 887
 888                 /* the adapter is about to reset, no point in enabling stuff */
 889                 return true;
 890         }
 891
 892 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 893         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 894                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 895                 /* Make sure that anybody stopping the queue after this
 896                  * sees the new next_to_clean.
 897                  */
 898                 smp_mb();
 899                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 900                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 901                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 902                         ++tx_ring->tx_stats.restart_queue;
 903                 }
 904         }
 905
 906         return count < tx_ring->work_limit;
 907 }
 908
 909 #ifdef CONFIG_IXGBE_DCA
 910 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 911                                 struct ixgbe_ring *rx_ring,
 912                                 int cpu)
 913 {
 914         struct ixgbe_hw *hw = &adapter->hw;
 915         u32 rxctrl;
 916         u8 reg_idx = rx_ring->reg_idx;
 917
 918         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 919         switch (hw->mac.type) {
 920         case ixgbe_mac_82598EB:
 921                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 922                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 923                 break;
 924         case ixgbe_mac_82599EB:
 925                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 926                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 927                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 928                 break;
 929         default:
 930                 break;
 931         }
 932         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 933         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 934         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 935         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 936                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 937         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 938 }
 939
 940 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 941                                 struct ixgbe_ring *tx_ring,
 942                                 int cpu)
 943 {
 944         struct ixgbe_hw *hw = &adapter->hw;
 945         u32 txctrl;
 946         u8 reg_idx = tx_ring->reg_idx;
 947
 948         switch (hw->mac.type) {
 949         case ixgbe_mac_82598EB:
 950                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 951                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 952                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 953                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 954                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 955                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 956                 break;
 957         case ixgbe_mac_82599EB:
 958                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 959                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 960                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 961                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 962                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 963                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 964                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 965                 break;
 966         default:
 967                 break;
 968         }
 969 }
 970
 971 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 972 {
 973         struct ixgbe_adapter *adapter = q_vector->adapter;
 974         int cpu = get_cpu();
 975         long r_idx;
 976         int i;
 977
 978         if (q_vector->cpu == cpu)
 979                 goto out_no_update;
 980
 981         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 982         for (i = 0; i < q_vector->txr_count; i++) {
 983                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 984                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 985                                       r_idx + 1);
 986         }
 987
 988         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 989         for (i = 0; i < q_vector->rxr_count; i++) {
 990                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 991                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 992                                       r_idx + 1);
 993         }
 994
 995         q_vector->cpu = cpu;
 996 out_no_update:
 997         put_cpu();
 998 }
 999
1000 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1001 {
1002         int num_q_vectors;
1003         int i;
1004
1005         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1006                 return;
1007
1008         /* always use CB2 mode, difference is masked in the CB driver */
1009         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1010
1011         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1012                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1013         else
1014                 num_q_vectors = 1;
1015
1016         for (i = 0; i < num_q_vectors; i++) {
1017                 adapter->q_vector[i]->cpu = -1;
1018                 ixgbe_update_dca(adapter->q_vector[i]);
1019         }
1020 }
1021
1022 static int __ixgbe_notify_dca(struct device *dev, void *data)
1023 {
1024         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1025         unsigned long event = *(unsigned long *)data;
1026
1027         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1028                 return 0;
1029
1030         switch (event) {
1031         case DCA_PROVIDER_ADD:
1032                 /* if we're already enabled, don't do it again */
1033                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1034                         break;
1035                 if (dca_add_requester(dev) == 0) {
1036                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1037                         ixgbe_setup_dca(adapter);
1038                         break;
1039                 }
1040                 /* Fall Through since DCA is disabled. */
1041         case DCA_PROVIDER_REMOVE:
1042                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1043                         dca_remove_requester(dev);
1044                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1045                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1046                 }
1047                 break;
1048         }
1049
1050         return 0;
1051 }
1052
1053 #endif /* CONFIG_IXGBE_DCA */
1054 /**
1055  * ixgbe_receive_skb - Send a completed packet up the stack
1056  * @adapter: board private structure
1057  * @skb: packet to send up
1058  * @status: hardware indication of status of receive
1059  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1060  * @rx_desc: rx descriptor
1061  **/
1062 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1063                               struct sk_buff *skb, u8 status,
1064                               struct ixgbe_ring *ring,
1065                               union ixgbe_adv_rx_desc *rx_desc)
1066 {
1067         struct ixgbe_adapter *adapter = q_vector->adapter;
1068         struct napi_struct *napi = &q_vector->napi;
1069         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1070         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1071
1072         if (is_vlan && (tag & VLAN_VID_MASK))
1073                 __vlan_hwaccel_put_tag(skb, tag);
1074
1075         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1076                 napi_gro_receive(napi, skb);
1077         else
1078                 netif_rx(skb);
1079 }
1080
1081 /**
1082  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1083  * @adapter: address of board private structure
1084  * @status_err: hardware indication of status of receive
1085  * @skb: skb currently being received and modified
1086  **/
1087 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1088                                      union ixgbe_adv_rx_desc *rx_desc,
1089                                      struct sk_buff *skb)
1090 {
1091         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1092
1093         skb_checksum_none_assert(skb);
1094
1095         /* Rx csum disabled */
1096         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1097                 return;
1098
1099         /* if IP and error */
1100         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1101             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1102                 adapter->hw_csum_rx_error++;
1103                 return;
1104         }
1105
1106         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1107                 return;
1108
1109         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1110                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1111
1112                 /*
1113                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1114                  * checksum errors.
1115                  */
1116                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1117                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1118                         return;
1119
1120                 adapter->hw_csum_rx_error++;
1121                 return;
1122         }
1123
1124         /* It must be a TCP or UDP packet with a valid checksum */
1125         skb->ip_summed = CHECKSUM_UNNECESSARY;
1126 }
1127
1128 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1129 {
1130         /*
1131          * Force memory writes to complete before letting h/w
1132          * know there are new descriptors to fetch.  (Only
1133          * applicable for weak-ordered memory model archs,
1134          * such as IA-64).
1135          */
1136         wmb();
1137         writel(val, rx_ring->tail);
1138 }
1139
1140 /**
1141  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1142  * @rx_ring: ring to place buffers on
1143  * @cleaned_count: number of buffers to replace
1144  **/
1145 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1146 {
1147         union ixgbe_adv_rx_desc *rx_desc;
1148         struct ixgbe_rx_buffer *bi;
1149         struct sk_buff *skb;
1150         u16 i = rx_ring->next_to_use;
1151
1152         /* do nothing if no valid netdev defined */
1153         if (!rx_ring->netdev)
1154                 return;
1155
1156         while (cleaned_count--) {
1157                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1158                 bi = &rx_ring->rx_buffer_info[i];
1159                 skb = bi->skb;
1160
1161                 if (!skb) {
1162                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1163                                                         rx_ring->rx_buf_len);
1164                         if (!skb) {
1165                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1166                                 goto no_buffers;
1167                         }
1168                         /* initialize queue mapping */
1169                         skb_record_rx_queue(skb, rx_ring->queue_index);
1170                         bi->skb = skb;
1171                 }
1172
1173                 if (!bi->dma) {
1174                         bi->dma = dma_map_single(rx_ring->dev,
1175                                                  skb->data,
1176                                                  rx_ring->rx_buf_len,
1177                                                  DMA_FROM_DEVICE);
1178                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1179                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1180                                 bi->dma = 0;
1181                                 goto no_buffers;
1182                         }
1183                 }
1184
1185                 if (ring_is_ps_enabled(rx_ring)) {
1186                         if (!bi->page) {
1187                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1188                                 if (!bi->page) {
1189                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1190                                         goto no_buffers;
1191                                 }
1192                         }
1193
1194                         if (!bi->page_dma) {
1195                                 /* use a half page if we're re-using */
1196                                 bi->page_offset ^= PAGE_SIZE / 2;
1197                                 bi->page_dma = dma_map_page(rx_ring->dev,
1198                                                             bi->page,
1199                                                             bi->page_offset,
1200                                                             PAGE_SIZE / 2,
1201                                                             DMA_FROM_DEVICE);
1202                                 if (dma_mapping_error(rx_ring->dev,
1203                                                       bi->page_dma)) {
1204                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1205                                         bi->page_dma = 0;
1206                                         goto no_buffers;
1207                                 }
1208                         }
1209
1210                         /* Refresh the desc even if buffer_addrs didn't change
1211                          * because each write-back erases this info. */
1212                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1213                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1214                 } else {
1215                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1216                         rx_desc->read.hdr_addr = 0;
1217                 }
1218
1219                 i++;
1220                 if (i == rx_ring->count)
1221                         i = 0;
1222         }
1223
1224 no_buffers:
1225         if (rx_ring->next_to_use != i) {
1226                 rx_ring->next_to_use = i;
1227                 ixgbe_release_rx_desc(rx_ring, i);
1228         }
1229 }
1230
1231 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1232 {
1233         /* HW will not DMA in data larger than the given buffer, even if it
1234          * parses the (NFS, of course) header to be larger.  In that case, it
1235          * fills the header buffer and spills the rest into the page.
1236          */
1237         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1238         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1239                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1240         if (hlen > IXGBE_RX_HDR_SIZE)
1241                 hlen = IXGBE_RX_HDR_SIZE;
1242         return hlen;
1243 }
1244
1245 /**
1246  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1247  * @skb: pointer to the last skb in the rsc queue
1248  *
1249  * This function changes a queue full of hw rsc buffers into a completed
1250  * packet.  It uses the ->prev pointers to find the first packet and then
1251  * turns it into the frag list owner.
1252  **/
1253 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1254 {
1255         unsigned int frag_list_size = 0;
1256         unsigned int skb_cnt = 1;
1257
1258         while (skb->prev) {
1259                 struct sk_buff *prev = skb->prev;
1260                 frag_list_size += skb->len;
1261                 skb->prev = NULL;
1262                 skb = prev;
1263                 skb_cnt++;
1264         }
1265
1266         skb_shinfo(skb)->frag_list = skb->next;
1267         skb->next = NULL;
1268         skb->len += frag_list_size;
1269         skb->data_len += frag_list_size;
1270         skb->truesize += frag_list_size;
1271         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1272
1273         return skb;
1274 }
1275
1276 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1277 {
1278         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1279                 IXGBE_RXDADV_RSCCNT_MASK);
1280 }
1281
1282 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1283                                struct ixgbe_ring *rx_ring,
1284                                int *work_done, int work_to_do)
1285 {
1286         struct ixgbe_adapter *adapter = q_vector->adapter;
1287         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1288         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1289         struct sk_buff *skb;
1290         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1291         const int current_node = numa_node_id();
1292 #ifdef IXGBE_FCOE
1293         int ddp_bytes = 0;
1294 #endif /* IXGBE_FCOE */
1295         u32 staterr;
1296         u16 i;
1297         u16 cleaned_count = 0;
1298         bool pkt_is_rsc = false;
1299
1300         i = rx_ring->next_to_clean;
1301         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1302         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1303
1304         while (staterr & IXGBE_RXD_STAT_DD) {
1305                 u32 upper_len = 0;
1306
1307                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1308
1309                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1310
1311                 skb = rx_buffer_info->skb;
1312                 rx_buffer_info->skb = NULL;
1313                 prefetch(skb->data);
1314
1315                 if (ring_is_rsc_enabled(rx_ring))
1316                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1317
1318                 /* if this is a skb from previous receive DMA will be 0 */
1319                 if (rx_buffer_info->dma) {
1320                         u16 hlen;
1321                         if (pkt_is_rsc &&
1322                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1323                             !skb->prev) {
1324                                 /*
1325                                  * When HWRSC is enabled, delay unmapping
1326                                  * of the first packet. It carries the
1327                                  * header information, HW may still
1328                                  * access the header after the writeback.
1329                                  * Only unmap it when EOP is reached
1330                                  */
1331                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1332                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1333                         } else {
1334                                 dma_unmap_single(rx_ring->dev,
1335                                                  rx_buffer_info->dma,
1336                                                  rx_ring->rx_buf_len,
1337                                                  DMA_FROM_DEVICE);
1338                         }
1339                         rx_buffer_info->dma = 0;
1340
1341                         if (ring_is_ps_enabled(rx_ring)) {
1342                                 hlen = ixgbe_get_hlen(rx_desc);
1343                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1344                         } else {
1345                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1346                         }
1347
1348                         skb_put(skb, hlen);
1349                 } else {
1350                         /* assume packet split since header is unmapped */
1351                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1352                 }
1353
1354                 if (upper_len) {
1355                         dma_unmap_page(rx_ring->dev,
1356                                        rx_buffer_info->page_dma,
1357                                        PAGE_SIZE / 2,
1358                                        DMA_FROM_DEVICE);
1359                         rx_buffer_info->page_dma = 0;
1360                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1361                                            rx_buffer_info->page,
1362                                            rx_buffer_info->page_offset,
1363                                            upper_len);
1364
1365                         if ((page_count(rx_buffer_info->page) == 1) &&
1366                             (page_to_nid(rx_buffer_info->page) == current_node))
1367                                 get_page(rx_buffer_info->page);
1368                         else
1369                                 rx_buffer_info->page = NULL;
1370
1371                         skb->len += upper_len;
1372                         skb->data_len += upper_len;
1373                         skb->truesize += upper_len;
1374                 }
1375
1376                 i++;
1377                 if (i == rx_ring->count)
1378                         i = 0;
1379
1380                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1381                 prefetch(next_rxd);
1382                 cleaned_count++;
1383
1384                 if (pkt_is_rsc) {
1385                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1386                                      IXGBE_RXDADV_NEXTP_SHIFT;
1387                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1388                 } else {
1389                         next_buffer = &rx_ring->rx_buffer_info[i];
1390                 }
1391
1392                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1393                         if (ring_is_ps_enabled(rx_ring)) {
1394                                 rx_buffer_info->skb = next_buffer->skb;
1395                                 rx_buffer_info->dma = next_buffer->dma;
1396                                 next_buffer->skb = skb;
1397                                 next_buffer->dma = 0;
1398                         } else {
1399                                 skb->next = next_buffer->skb;
1400                                 skb->next->prev = skb;
1401                         }
1402                         rx_ring->rx_stats.non_eop_descs++;
1403                         goto next_desc;
1404                 }
1405
1406                 if (skb->prev) {
1407                         skb = ixgbe_transform_rsc_queue(skb);
1408                         /* if we got here without RSC the packet is invalid */
1409                         if (!pkt_is_rsc) {
1410                                 __pskb_trim(skb, 0);
1411                                 rx_buffer_info->skb = skb;
1412                                 goto next_desc;
1413                         }
1414                 }
1415
1416                 if (ring_is_rsc_enabled(rx_ring)) {
1417                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1418                                 dma_unmap_single(rx_ring->dev,
1419                                                  IXGBE_RSC_CB(skb)->dma,
1420                                                  rx_ring->rx_buf_len,
1421                                                  DMA_FROM_DEVICE);
1422                                 IXGBE_RSC_CB(skb)->dma = 0;
1423                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1424                         }
1425                 }
1426                 if (pkt_is_rsc) {
1427                         if (ring_is_ps_enabled(rx_ring))
1428                                 rx_ring->rx_stats.rsc_count +=
1429                                         skb_shinfo(skb)->nr_frags;
1430                         else
1431                                 rx_ring->rx_stats.rsc_count +=
1432                                         IXGBE_RSC_CB(skb)->skb_cnt;
1433                         rx_ring->rx_stats.rsc_flush++;
1434                 }
1435
1436                 /* ERR_MASK will only have valid bits if EOP set */
1437                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1438                         /* trim packet back to size 0 and recycle it */
1439                         __pskb_trim(skb, 0);
1440                         rx_buffer_info->skb = skb;
1441                         goto next_desc;
1442                 }
1443
1444                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1445
1446                 /* probably a little skewed due to removing CRC */
1447                 total_rx_bytes += skb->len;
1448                 total_rx_packets++;
1449
1450                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1451 #ifdef IXGBE_FCOE
1452                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1453                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1454                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1455                         if (!ddp_bytes)
1456                                 goto next_desc;
1457                 }
1458 #endif /* IXGBE_FCOE */
1459                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1460
1461 next_desc:
1462                 rx_desc->wb.upper.status_error = 0;
1463
1464                 (*work_done)++;
1465                 if (*work_done >= work_to_do)
1466                         break;
1467
1468                 /* return some buffers to hardware, one at a time is too slow */
1469                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1470                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1471                         cleaned_count = 0;
1472                 }
1473
1474                 /* use prefetched values */
1475                 rx_desc = next_rxd;
1476                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1477         }
1478
1479         rx_ring->next_to_clean = i;
1480         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1481
1482         if (cleaned_count)
1483                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1484
1485 #ifdef IXGBE_FCOE
1486         /* include DDPed FCoE data */
1487         if (ddp_bytes > 0) {
1488                 unsigned int mss;
1489
1490                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1491                         sizeof(struct fc_frame_header) -
1492                         sizeof(struct fcoe_crc_eof);
1493                 if (mss > 512)
1494                         mss &= ~511;
1495                 total_rx_bytes += ddp_bytes;
1496                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1497         }
1498 #endif /* IXGBE_FCOE */
1499
1500         rx_ring->total_packets += total_rx_packets;
1501         rx_ring->total_bytes += total_rx_bytes;
1502         u64_stats_update_begin(&rx_ring->syncp);
1503         rx_ring->stats.packets += total_rx_packets;
1504         rx_ring->stats.bytes += total_rx_bytes;
1505         u64_stats_update_end(&rx_ring->syncp);
1506 }
1507
1508 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1509 /**
1510  * ixgbe_configure_msix - Configure MSI-X hardware
1511  * @adapter: board private structure
1512  *
1513  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1514  * interrupts.
1515  **/
1516 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1517 {
1518         struct ixgbe_q_vector *q_vector;
1519         int i, q_vectors, v_idx, r_idx;
1520         u32 mask;
1521
1522         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1523
1524         /*
1525          * Populate the IVAR table and set the ITR values to the
1526          * corresponding register.
1527          */
1528         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1529                 q_vector = adapter->q_vector[v_idx];
1530                 /* XXX for_each_set_bit(...) */
1531                 r_idx = find_first_bit(q_vector->rxr_idx,
1532                                        adapter->num_rx_queues);
1533
1534                 for (i = 0; i < q_vector->rxr_count; i++) {
1535                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1536                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1537                         r_idx = find_next_bit(q_vector->rxr_idx,
1538                                               adapter->num_rx_queues,
1539                                               r_idx + 1);
1540                 }
1541                 r_idx = find_first_bit(q_vector->txr_idx,
1542                                        adapter->num_tx_queues);
1543
1544                 for (i = 0; i < q_vector->txr_count; i++) {
1545                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1546                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1547                         r_idx = find_next_bit(q_vector->txr_idx,
1548                                               adapter->num_tx_queues,
1549                                               r_idx + 1);
1550                 }
1551
1552                 if (q_vector->txr_count && !q_vector->rxr_count)
1553                         /* tx only */
1554                         q_vector->eitr = adapter->tx_eitr_param;
1555                 else if (q_vector->rxr_count)
1556                         /* rx or mixed */
1557                         q_vector->eitr = adapter->rx_eitr_param;
1558
1559                 ixgbe_write_eitr(q_vector);
1560                 /* If Flow Director is enabled, set interrupt affinity */
1561                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1562                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1563                         /*
1564                          * Allocate the affinity_hint cpumask, assign the mask
1565                          * for this vector, and set our affinity_hint for
1566                          * this irq.
1567                          */
1568                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1569                                                GFP_KERNEL))
1570                                 return;
1571                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1572                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1573                                               q_vector->affinity_mask);
1574                 }
1575         }
1576
1577         switch (adapter->hw.mac.type) {
1578         case ixgbe_mac_82598EB:
1579                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1580                                v_idx);
1581                 break;
1582         case ixgbe_mac_82599EB:
1583                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1584                 break;
1585
1586         default:
1587                 break;
1588         }
1589         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1590
1591         /* set up to autoclear timer, and the vectors */
1592         mask = IXGBE_EIMS_ENABLE_MASK;
1593         if (adapter->num_vfs)
1594                 mask &= ~(IXGBE_EIMS_OTHER |
1595                           IXGBE_EIMS_MAILBOX |
1596                           IXGBE_EIMS_LSC);
1597         else
1598                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1599         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1600 }
1601
1602 enum latency_range {
1603         lowest_latency = 0,
1604         low_latency = 1,
1605         bulk_latency = 2,
1606         latency_invalid = 255
1607 };
1608
1609 /**
1610  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1611  * @adapter: pointer to adapter
1612  * @eitr: eitr setting (ints per sec) to give last timeslice
1613  * @itr_setting: current throttle rate in ints/second
1614  * @packets: the number of packets during this measurement interval
1615  * @bytes: the number of bytes during this measurement interval
1616  *
1617  *      Stores a new ITR value based on packets and byte
1618  *      counts during the last interrupt.  The advantage of per interrupt
1619  *      computation is faster updates and more accurate ITR for the current
1620  *      traffic pattern.  Constants in this function were computed
1621  *      based on theoretical maximum wire speed and thresholds were set based
1622  *      on testing data as well as attempting to minimize response time
1623  *      while increasing bulk throughput.
1624  *      this functionality is controlled by the InterruptThrottleRate module
1625  *      parameter (see ixgbe_param.c)
1626  **/
1627 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1628                            u32 eitr, u8 itr_setting,
1629                            int packets, int bytes)
1630 {
1631         unsigned int retval = itr_setting;
1632         u32 timepassed_us;
1633         u64 bytes_perint;
1634
1635         if (packets == 0)
1636                 goto update_itr_done;
1637
1638
1639         /* simple throttlerate management
1640          *    0-20MB/s lowest (100000 ints/s)
1641          *   20-100MB/s low   (20000 ints/s)
1642          *  100-1249MB/s bulk (8000 ints/s)
1643          */
1644         /* what was last interrupt timeslice? */
1645         timepassed_us = 1000000/eitr;
1646         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1647
1648         switch (itr_setting) {
1649         case lowest_latency:
1650                 if (bytes_perint > adapter->eitr_low)
1651                         retval = low_latency;
1652                 break;
1653         case low_latency:
1654                 if (bytes_perint > adapter->eitr_high)
1655                         retval = bulk_latency;
1656                 else if (bytes_perint <= adapter->eitr_low)
1657                         retval = lowest_latency;
1658                 break;
1659         case bulk_latency:
1660                 if (bytes_perint <= adapter->eitr_high)
1661                         retval = low_latency;
1662                 break;
1663         }
1664
1665 update_itr_done:
1666         return retval;
1667 }
1668
1669 /**
1670  * ixgbe_write_eitr - write EITR register in hardware specific way
1671  * @q_vector: structure containing interrupt and ring information
1672  *
1673  * This function is made to be called by ethtool and by the driver
1674  * when it needs to update EITR registers at runtime.  Hardware
1675  * specific quirks/differences are taken care of here.
1676  */
1677 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1678 {
1679         struct ixgbe_adapter *adapter = q_vector->adapter;
1680         struct ixgbe_hw *hw = &adapter->hw;
1681         int v_idx = q_vector->v_idx;
1682         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1683
1684         switch (adapter->hw.mac.type) {
1685         case ixgbe_mac_82598EB:
1686                 /* must write high and low 16 bits to reset counter */
1687                 itr_reg |= (itr_reg << 16);
1688                 break;
1689         case ixgbe_mac_82599EB:
1690                 /*
1691                  * 82599 can support a value of zero, so allow it for
1692                  * max interrupt rate, but there is an errata where it can
1693                  * not be zero with RSC
1694                  */
1695                 if (itr_reg == 8 &&
1696                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1697                         itr_reg = 0;
1698
1699                 /*
1700                  * set the WDIS bit to not clear the timer bits and cause an
1701                  * immediate assertion of the interrupt
1702                  */
1703                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1704                 break;
1705         default:
1706                 break;
1707         }
1708         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1709 }
1710
1711 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1712 {
1713         struct ixgbe_adapter *adapter = q_vector->adapter;
1714         int i, r_idx;
1715         u32 new_itr;
1716         u8 current_itr, ret_itr;
1717
1718         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1719         for (i = 0; i < q_vector->txr_count; i++) {
1720                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1721                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1722                                            q_vector->tx_itr,
1723                                            tx_ring->total_packets,
1724                                            tx_ring->total_bytes);
1725                 /* if the result for this queue would decrease interrupt
1726                  * rate for this vector then use that result */
1727                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1728                                     q_vector->tx_itr - 1 : ret_itr);
1729                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1730                                       r_idx + 1);
1731         }
1732
1733         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1734         for (i = 0; i < q_vector->rxr_count; i++) {
1735                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1736                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1737                                            q_vector->rx_itr,
1738                                            rx_ring->total_packets,
1739                                            rx_ring->total_bytes);
1740                 /* if the result for this queue would decrease interrupt
1741                  * rate for this vector then use that result */
1742                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1743                                     q_vector->rx_itr - 1 : ret_itr);
1744                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1745                                       r_idx + 1);
1746         }
1747
1748         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1749
1750         switch (current_itr) {
1751         /* counts and packets in update_itr are dependent on these numbers */
1752         case lowest_latency:
1753                 new_itr = 100000;
1754                 break;
1755         case low_latency:
1756                 new_itr = 20000; /* aka hwitr = ~200 */
1757                 break;
1758         case bulk_latency:
1759         default:
1760                 new_itr = 8000;
1761                 break;
1762         }
1763
1764         if (new_itr != q_vector->eitr) {
1765                 /* do an exponential smoothing */
1766                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1767
1768                 /* save the algorithm value here, not the smoothed one */
1769                 q_vector->eitr = new_itr;
1770
1771                 ixgbe_write_eitr(q_vector);
1772         }
1773 }
1774
1775 /**
1776  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1777  * @work: pointer to work_struct containing our data
1778  **/
1779 static void ixgbe_check_overtemp_task(struct work_struct *work)
1780 {
1781         struct ixgbe_adapter *adapter = container_of(work,
1782                                                      struct ixgbe_adapter,
1783                                                      check_overtemp_task);
1784         struct ixgbe_hw *hw = &adapter->hw;
1785         u32 eicr = adapter->interrupt_event;
1786
1787         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1788                 return;
1789
1790         switch (hw->device_id) {
1791         case IXGBE_DEV_ID_82599_T3_LOM: {
1792                 u32 autoneg;
1793                 bool link_up = false;
1794
1795                 if (hw->mac.ops.check_link)
1796                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1797
1798                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1799                     (eicr & IXGBE_EICR_LSC))
1800                         /* Check if this is due to overtemp */
1801                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1802                                 break;
1803                 return;
1804         }
1805         default:
1806                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1807                         return;
1808                 break;
1809         }
1810         e_crit(drv,
1811                "Network adapter has been stopped because it has over heated. "
1812                "Restart the computer. If the problem persists, "
1813                "power off the system and replace the adapter\n");
1814         /* write to clear the interrupt */
1815         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1816 }
1817
1818 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1819 {
1820         struct ixgbe_hw *hw = &adapter->hw;
1821
1822         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1823             (eicr & IXGBE_EICR_GPI_SDP1)) {
1824                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1825                 /* write to clear the interrupt */
1826                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1827         }
1828 }
1829
1830 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1831 {
1832         struct ixgbe_hw *hw = &adapter->hw;
1833
1834         if (eicr & IXGBE_EICR_GPI_SDP2) {
1835                 /* Clear the interrupt */
1836                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1837                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1838                         schedule_work(&adapter->sfp_config_module_task);
1839         }
1840
1841         if (eicr & IXGBE_EICR_GPI_SDP1) {
1842                 /* Clear the interrupt */
1843                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1844                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1845                         schedule_work(&adapter->multispeed_fiber_task);
1846         }
1847 }
1848
1849 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1850 {
1851         struct ixgbe_hw *hw = &adapter->hw;
1852
1853         adapter->lsc_int++;
1854         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1855         adapter->link_check_timeout = jiffies;
1856         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1857                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1858                 IXGBE_WRITE_FLUSH(hw);
1859                 schedule_work(&adapter->watchdog_task);
1860         }
1861 }
1862
1863 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1864 {
1865         struct net_device *netdev = data;
1866         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1867         struct ixgbe_hw *hw = &adapter->hw;
1868         u32 eicr;
1869
1870         /*
1871          * Workaround for Silicon errata.  Use clear-by-write instead
1872          * of clear-by-read.  Reading with EICS will return the
1873          * interrupt causes without clearing, which later be done
1874          * with the write to EICR.
1875          */
1876         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1877         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1878
1879         if (eicr & IXGBE_EICR_LSC)
1880                 ixgbe_check_lsc(adapter);
1881
1882         if (eicr & IXGBE_EICR_MAILBOX)
1883                 ixgbe_msg_task(adapter);
1884
1885         switch (hw->mac.type) {
1886         case ixgbe_mac_82599EB:
1887                 /* Handle Flow Director Full threshold interrupt */
1888                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1889                         int i;
1890                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1891                         /* Disable transmits before FDIR Re-initialization */
1892                         netif_tx_stop_all_queues(netdev);
1893                         for (i = 0; i < adapter->num_tx_queues; i++) {
1894                                 struct ixgbe_ring *tx_ring =
1895                                                             adapter->tx_ring[i];
1896                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1897                                                        &tx_ring->state))
1898                                         schedule_work(&adapter->fdir_reinit_task);
1899                         }
1900                 }
1901                 ixgbe_check_sfp_event(adapter, eicr);
1902                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1903                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1904                         adapter->interrupt_event = eicr;
1905                         schedule_work(&adapter->check_overtemp_task);
1906                 }
1907                 break;
1908         default:
1909                 break;
1910         }
1911
1912         ixgbe_check_fan_failure(adapter, eicr);
1913
1914         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1915                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1916
1917         return IRQ_HANDLED;
1918 }
1919
1920 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1921                                            u64 qmask)
1922 {
1923         u32 mask;
1924         struct ixgbe_hw *hw = &adapter->hw;
1925
1926         switch (hw->mac.type) {
1927         case ixgbe_mac_82598EB:
1928                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1929                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1930                 break;
1931         case ixgbe_mac_82599EB:
1932                 mask = (qmask & 0xFFFFFFFF);
1933                 if (mask)
1934                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1935                 mask = (qmask >> 32);
1936                 if (mask)
1937                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1938                 break;
1939         default:
1940                 break;
1941         }
1942         /* skip the flush */
1943 }
1944
1945 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1946                                             u64 qmask)
1947 {
1948         u32 mask;
1949         struct ixgbe_hw *hw = &adapter->hw;
1950
1951         switch (hw->mac.type) {
1952         case ixgbe_mac_82598EB:
1953                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1954                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1955                 break;
1956         case ixgbe_mac_82599EB:
1957                 mask = (qmask & 0xFFFFFFFF);
1958                 if (mask)
1959                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1960                 mask = (qmask >> 32);
1961                 if (mask)
1962                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1963                 break;
1964         default:
1965                 break;
1966         }
1967         /* skip the flush */
1968 }
1969
1970 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1971 {
1972         struct ixgbe_q_vector *q_vector = data;
1973         struct ixgbe_adapter  *adapter = q_vector->adapter;
1974         struct ixgbe_ring     *tx_ring;
1975         int i, r_idx;
1976
1977         if (!q_vector->txr_count)
1978                 return IRQ_HANDLED;
1979
1980         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1981         for (i = 0; i < q_vector->txr_count; i++) {
1982                 tx_ring = adapter->tx_ring[r_idx];
1983                 tx_ring->total_bytes = 0;
1984                 tx_ring->total_packets = 0;
1985                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1986                                       r_idx + 1);
1987         }
1988
1989         /* EIAM disabled interrupts (on this vector) for us */
1990         napi_schedule(&q_vector->napi);
1991
1992         return IRQ_HANDLED;
1993 }
1994
1995 /**
1996  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1997  * @irq: unused
1998  * @data: pointer to our q_vector struct for this interrupt vector
1999  **/
2000 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2001 {
2002         struct ixgbe_q_vector *q_vector = data;
2003         struct ixgbe_adapter  *adapter = q_vector->adapter;
2004         struct ixgbe_ring  *rx_ring;
2005         int r_idx;
2006         int i;
2007
2008 #ifdef CONFIG_IXGBE_DCA
2009         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2010                 ixgbe_update_dca(q_vector);
2011 #endif
2012
2013         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2014         for (i = 0; i < q_vector->rxr_count; i++) {
2015                 rx_ring = adapter->rx_ring[r_idx];
2016                 rx_ring->total_bytes = 0;
2017                 rx_ring->total_packets = 0;
2018                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2019                                       r_idx + 1);
2020         }
2021
2022         if (!q_vector->rxr_count)
2023                 return IRQ_HANDLED;
2024
2025         /* EIAM disabled interrupts (on this vector) for us */
2026         napi_schedule(&q_vector->napi);
2027
2028         return IRQ_HANDLED;
2029 }
2030
2031 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2032 {
2033         struct ixgbe_q_vector *q_vector = data;
2034         struct ixgbe_adapter  *adapter = q_vector->adapter;
2035         struct ixgbe_ring  *ring;
2036         int r_idx;
2037         int i;
2038
2039         if (!q_vector->txr_count && !q_vector->rxr_count)
2040                 return IRQ_HANDLED;
2041
2042         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2043         for (i = 0; i < q_vector->txr_count; i++) {
2044                 ring = adapter->tx_ring[r_idx];
2045                 ring->total_bytes = 0;
2046                 ring->total_packets = 0;
2047                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2048                                       r_idx + 1);
2049         }
2050
2051         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2052         for (i = 0; i < q_vector->rxr_count; i++) {
2053                 ring = adapter->rx_ring[r_idx];
2054                 ring->total_bytes = 0;
2055                 ring->total_packets = 0;
2056                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2057                                       r_idx + 1);
2058         }
2059
2060         /* EIAM disabled interrupts (on this vector) for us */
2061         napi_schedule(&q_vector->napi);
2062
2063         return IRQ_HANDLED;
2064 }
2065
2066 /**
2067  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2068  * @napi: napi struct with our devices info in it
2069  * @budget: amount of work driver is allowed to do this pass, in packets
2070  *
2071  * This function is optimized for cleaning one queue only on a single
2072  * q_vector!!!
2073  **/
2074 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2075 {
2076         struct ixgbe_q_vector *q_vector =
2077                                container_of(napi, struct ixgbe_q_vector, napi);
2078         struct ixgbe_adapter *adapter = q_vector->adapter;
2079         struct ixgbe_ring *rx_ring = NULL;
2080         int work_done = 0;
2081         long r_idx;
2082
2083 #ifdef CONFIG_IXGBE_DCA
2084         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2085                 ixgbe_update_dca(q_vector);
2086 #endif
2087
2088         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2089         rx_ring = adapter->rx_ring[r_idx];
2090
2091         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2092
2093         /* If all Rx work done, exit the polling mode */
2094         if (work_done < budget) {
2095                 napi_complete(napi);
2096                 if (adapter->rx_itr_setting & 1)
2097                         ixgbe_set_itr_msix(q_vector);
2098                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2099                         ixgbe_irq_enable_queues(adapter,
2100                                                 ((u64)1 << q_vector->v_idx));
2101         }
2102
2103         return work_done;
2104 }
2105
2106 /**
2107  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2108  * @napi: napi struct with our devices info in it
2109  * @budget: amount of work driver is allowed to do this pass, in packets
2110  *
2111  * This function will clean more than one rx queue associated with a
2112  * q_vector.
2113  **/
2114 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2115 {
2116         struct ixgbe_q_vector *q_vector =
2117                                container_of(napi, struct ixgbe_q_vector, napi);
2118         struct ixgbe_adapter *adapter = q_vector->adapter;
2119         struct ixgbe_ring *ring = NULL;
2120         int work_done = 0, i;
2121         long r_idx;
2122         bool tx_clean_complete = true;
2123
2124 #ifdef CONFIG_IXGBE_DCA
2125         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2126                 ixgbe_update_dca(q_vector);
2127 #endif
2128
2129         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2130         for (i = 0; i < q_vector->txr_count; i++) {
2131                 ring = adapter->tx_ring[r_idx];
2132                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2133                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2134                                       r_idx + 1);
2135         }
2136
2137         /* attempt to distribute budget to each queue fairly, but don't allow
2138          * the budget to go below 1 because we'll exit polling */
2139         budget /= (q_vector->rxr_count ?: 1);
2140         budget = max(budget, 1);
2141         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2142         for (i = 0; i < q_vector->rxr_count; i++) {
2143                 ring = adapter->rx_ring[r_idx];
2144                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2145                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2146                                       r_idx + 1);
2147         }
2148
2149         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2150         ring = adapter->rx_ring[r_idx];
2151         /* If all Rx work done, exit the polling mode */
2152         if (work_done < budget) {
2153                 napi_complete(napi);
2154                 if (adapter->rx_itr_setting & 1)
2155                         ixgbe_set_itr_msix(q_vector);
2156                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2157                         ixgbe_irq_enable_queues(adapter,
2158                                                 ((u64)1 << q_vector->v_idx));
2159                 return 0;
2160         }
2161
2162         return work_done;
2163 }
2164
2165 /**
2166  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2167  * @napi: napi struct with our devices info in it
2168  * @budget: amount of work driver is allowed to do this pass, in packets
2169  *
2170  * This function is optimized for cleaning one queue only on a single
2171  * q_vector!!!
2172  **/
2173 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2174 {
2175         struct ixgbe_q_vector *q_vector =
2176                                container_of(napi, struct ixgbe_q_vector, napi);
2177         struct ixgbe_adapter *adapter = q_vector->adapter;
2178         struct ixgbe_ring *tx_ring = NULL;
2179         int work_done = 0;
2180         long r_idx;
2181
2182 #ifdef CONFIG_IXGBE_DCA
2183         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2184                 ixgbe_update_dca(q_vector);
2185 #endif
2186
2187         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2188         tx_ring = adapter->tx_ring[r_idx];
2189
2190         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2191                 work_done = budget;
2192
2193         /* If all Tx work done, exit the polling mode */
2194         if (work_done < budget) {
2195                 napi_complete(napi);
2196                 if (adapter->tx_itr_setting & 1)
2197                         ixgbe_set_itr_msix(q_vector);
2198                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2199                         ixgbe_irq_enable_queues(adapter,
2200                                                 ((u64)1 << q_vector->v_idx));
2201         }
2202
2203         return work_done;
2204 }
2205
2206 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2207                                      int r_idx)
2208 {
2209         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2210         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2211
2212         set_bit(r_idx, q_vector->rxr_idx);
2213         q_vector->rxr_count++;
2214         rx_ring->q_vector = q_vector;
2215 }
2216
2217 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2218                                      int t_idx)
2219 {
2220         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2221         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2222
2223         set_bit(t_idx, q_vector->txr_idx);
2224         q_vector->txr_count++;
2225         tx_ring->q_vector = q_vector;
2226 }
2227
2228 /**
2229  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2230  * @adapter: board private structure to initialize
2231  *
2232  * This function maps descriptor rings to the queue-specific vectors
2233  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2234  * one vector per ring/queue, but on a constrained vector budget, we
2235  * group the rings as "efficiently" as possible.  You would add new
2236  * mapping configurations in here.
2237  **/
2238 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2239 {
2240         int q_vectors;
2241         int v_start = 0;
2242         int rxr_idx = 0, txr_idx = 0;
2243         int rxr_remaining = adapter->num_rx_queues;
2244         int txr_remaining = adapter->num_tx_queues;
2245         int i, j;
2246         int rqpv, tqpv;
2247         int err = 0;
2248
2249         /* No mapping required if MSI-X is disabled. */
2250         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2251                 goto out;
2252
2253         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2254
2255         /*
2256          * The ideal configuration...
2257          * We have enough vectors to map one per queue.
2258          */
2259         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2260                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2261                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2262
2263                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2264                         map_vector_to_txq(adapter, v_start, txr_idx);
2265
2266                 goto out;
2267         }
2268
2269         /*
2270          * If we don't have enough vectors for a 1-to-1
2271          * mapping, we'll have to group them so there are
2272          * multiple queues per vector.
2273          */
2274         /* Re-adjusting *qpv takes care of the remainder. */
2275         for (i = v_start; i < q_vectors; i++) {
2276                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2277                 for (j = 0; j < rqpv; j++) {
2278                         map_vector_to_rxq(adapter, i, rxr_idx);
2279                         rxr_idx++;
2280                         rxr_remaining--;
2281                 }
2282                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2283                 for (j = 0; j < tqpv; j++) {
2284                         map_vector_to_txq(adapter, i, txr_idx);
2285                         txr_idx++;
2286                         txr_remaining--;
2287                 }
2288         }
2289 out:
2290         return err;
2291 }
2292
2293 /**
2294  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2295  * @adapter: board private structure
2296  *
2297  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2298  * interrupts from the kernel.
2299  **/
2300 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2301 {
2302         struct net_device *netdev = adapter->netdev;
2303         irqreturn_t (*handler)(int, void *);
2304         int i, vector, q_vectors, err;
2305         int ri = 0, ti = 0;
2306
2307         /* Decrement for Other and TCP Timer vectors */
2308         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2309
2310         err = ixgbe_map_rings_to_vectors(adapter);
2311         if (err)
2312                 return err;
2313
2314 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2315                                           ? &ixgbe_msix_clean_many : \
2316                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2317                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2318                           NULL)
2319         for (vector = 0; vector < q_vectors; vector++) {
2320                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2321                 handler = SET_HANDLER(q_vector);
2322
2323                 if (handler == &ixgbe_msix_clean_rx) {
2324                         sprintf(q_vector->name, "%s-%s-%d",
2325                                 netdev->name, "rx", ri++);
2326                 } else if (handler == &ixgbe_msix_clean_tx) {
2327                         sprintf(q_vector->name, "%s-%s-%d",
2328                                 netdev->name, "tx", ti++);
2329                 } else if (handler == &ixgbe_msix_clean_many) {
2330                         sprintf(q_vector->name, "%s-%s-%d",
2331                                 netdev->name, "TxRx", ri++);
2332                         ti++;
2333                 } else {
2334                         /* skip this unused q_vector */
2335                         continue;
2336                 }
2337                 err = request_irq(adapter->msix_entries[vector].vector,
2338                                   handler, 0, q_vector->name,
2339                                   q_vector);
2340                 if (err) {
2341                         e_err(probe, "request_irq failed for MSIX interrupt "
2342                               "Error: %d\n", err);
2343                         goto free_queue_irqs;
2344                 }
2345         }
2346
2347         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2348         err = request_irq(adapter->msix_entries[vector].vector,
2349                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2350         if (err) {
2351                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2352                 goto free_queue_irqs;
2353         }
2354
2355         return 0;
2356
2357 free_queue_irqs:
2358         for (i = vector - 1; i >= 0; i--)
2359                 free_irq(adapter->msix_entries[--vector].vector,
2360                          adapter->q_vector[i]);
2361         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2362         pci_disable_msix(adapter->pdev);
2363         kfree(adapter->msix_entries);
2364         adapter->msix_entries = NULL;
2365         return err;
2366 }
2367
2368 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2369 {
2370         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2371         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2372         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2373         u32 new_itr = q_vector->eitr;
2374         u8 current_itr;
2375
2376         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2377                                             q_vector->tx_itr,
2378                                             tx_ring->total_packets,
2379                                             tx_ring->total_bytes);
2380         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2381                                             q_vector->rx_itr,
2382                                             rx_ring->total_packets,
2383                                             rx_ring->total_bytes);
2384
2385         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2386
2387         switch (current_itr) {
2388         /* counts and packets in update_itr are dependent on these numbers */
2389         case lowest_latency:
2390                 new_itr = 100000;
2391                 break;
2392         case low_latency:
2393                 new_itr = 20000; /* aka hwitr = ~200 */
2394                 break;
2395         case bulk_latency:
2396                 new_itr = 8000;
2397                 break;
2398         default:
2399                 break;
2400         }
2401
2402         if (new_itr != q_vector->eitr) {
2403                 /* do an exponential smoothing */
2404                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2405
2406                 /* save the algorithm value here */
2407                 q_vector->eitr = new_itr;
2408
2409                 ixgbe_write_eitr(q_vector);
2410         }
2411 }
2412
2413 /**
2414  * ixgbe_irq_enable - Enable default interrupt generation settings
2415  * @adapter: board private structure
2416  **/
2417 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2418                                     bool flush)
2419 {
2420         u32 mask;
2421
2422         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2423         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2424                 mask |= IXGBE_EIMS_GPI_SDP0;
2425         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2426                 mask |= IXGBE_EIMS_GPI_SDP1;
2427         switch (adapter->hw.mac.type) {
2428         case ixgbe_mac_82599EB:
2429                 mask |= IXGBE_EIMS_ECC;
2430                 mask |= IXGBE_EIMS_GPI_SDP1;
2431                 mask |= IXGBE_EIMS_GPI_SDP2;
2432                 if (adapter->num_vfs)
2433                         mask |= IXGBE_EIMS_MAILBOX;
2434                 break;
2435         default:
2436                 break;
2437         }
2438         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2439             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2440                 mask |= IXGBE_EIMS_FLOW_DIR;
2441
2442         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2443         if (queues)
2444                 ixgbe_irq_enable_queues(adapter, ~0);
2445         if (flush)
2446                 IXGBE_WRITE_FLUSH(&adapter->hw);
2447
2448         if (adapter->num_vfs > 32) {
2449                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2450                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2451         }
2452 }
2453
2454 /**
2455  * ixgbe_intr - legacy mode Interrupt Handler
2456  * @irq: interrupt number
2457  * @data: pointer to a network interface device structure
2458  **/
2459 static irqreturn_t ixgbe_intr(int irq, void *data)
2460 {
2461         struct net_device *netdev = data;
2462         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2463         struct ixgbe_hw *hw = &adapter->hw;
2464         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2465         u32 eicr;
2466
2467         /*
2468          * Workaround for silicon errata on 82598.  Mask the interrupts
2469          * before the read of EICR.
2470          */
2471         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2472
2473         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2474          * therefore no explict interrupt disable is necessary */
2475         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2476         if (!eicr) {
2477                 /*
2478                  * shared interrupt alert!
2479                  * make sure interrupts are enabled because the read will
2480                  * have disabled interrupts due to EIAM
2481                  * finish the workaround of silicon errata on 82598.  Unmask
2482                  * the interrupt that we masked before the EICR read.
2483                  */
2484                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2485                         ixgbe_irq_enable(adapter, true, true);
2486                 return IRQ_NONE;        /* Not our interrupt */
2487         }
2488
2489         if (eicr & IXGBE_EICR_LSC)
2490                 ixgbe_check_lsc(adapter);
2491
2492         switch (hw->mac.type) {
2493         case ixgbe_mac_82599EB:
2494                 ixgbe_check_sfp_event(adapter, eicr);
2495                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2496                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2497                         adapter->interrupt_event = eicr;
2498                         schedule_work(&adapter->check_overtemp_task);
2499                 }
2500                 break;
2501         default:
2502                 break;
2503         }
2504
2505         ixgbe_check_fan_failure(adapter, eicr);
2506
2507         if (napi_schedule_prep(&(q_vector->napi))) {
2508                 adapter->tx_ring[0]->total_packets = 0;
2509                 adapter->tx_ring[0]->total_bytes = 0;
2510                 adapter->rx_ring[0]->total_packets = 0;
2511                 adapter->rx_ring[0]->total_bytes = 0;
2512                 /* would disable interrupts here but EIAM disabled it */
2513                 __napi_schedule(&(q_vector->napi));
2514         }
2515
2516         /*
2517          * re-enable link(maybe) and non-queue interrupts, no flush.
2518          * ixgbe_poll will re-enable the queue interrupts
2519          */
2520
2521         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2522                 ixgbe_irq_enable(adapter, false, false);
2523
2524         return IRQ_HANDLED;
2525 }
2526
2527 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2528 {
2529         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2530
2531         for (i = 0; i < q_vectors; i++) {
2532                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2533                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2534                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2535                 q_vector->rxr_count = 0;
2536                 q_vector->txr_count = 0;
2537         }
2538 }
2539
2540 /**
2541  * ixgbe_request_irq - initialize interrupts
2542  * @adapter: board private structure
2543  *
2544  * Attempts to configure interrupts using the best available
2545  * capabilities of the hardware and kernel.
2546  **/
2547 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2548 {
2549         struct net_device *netdev = adapter->netdev;
2550         int err;
2551
2552         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2553                 err = ixgbe_request_msix_irqs(adapter);
2554         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2555                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2556                                   netdev->name, netdev);
2557         } else {
2558                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2559                                   netdev->name, netdev);
2560         }
2561
2562         if (err)
2563                 e_err(probe, "request_irq failed, Error %d\n", err);
2564
2565         return err;
2566 }
2567
2568 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2569 {
2570         struct net_device *netdev = adapter->netdev;
2571
2572         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2573                 int i, q_vectors;
2574
2575                 q_vectors = adapter->num_msix_vectors;
2576
2577                 i = q_vectors - 1;
2578                 free_irq(adapter->msix_entries[i].vector, netdev);
2579
2580                 i--;
2581                 for (; i >= 0; i--) {
2582                         free_irq(adapter->msix_entries[i].vector,
2583                                  adapter->q_vector[i]);
2584                 }
2585
2586                 ixgbe_reset_q_vectors(adapter);
2587         } else {
2588                 free_irq(adapter->pdev->irq, netdev);
2589         }
2590 }
2591
2592 /**
2593  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2594  * @adapter: board private structure
2595  **/
2596 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2597 {
2598         switch (adapter->hw.mac.type) {
2599         case ixgbe_mac_82598EB:
2600                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2601                 break;
2602         case ixgbe_mac_82599EB:
2603                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2604                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2605                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2606                 if (adapter->num_vfs > 32)
2607                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2608                 break;
2609         default:
2610                 break;
2611         }
2612         IXGBE_WRITE_FLUSH(&adapter->hw);
2613         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2614                 int i;
2615                 for (i = 0; i < adapter->num_msix_vectors; i++)
2616                         synchronize_irq(adapter->msix_entries[i].vector);
2617         } else {
2618                 synchronize_irq(adapter->pdev->irq);
2619         }
2620 }
2621
2622 /**
2623  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2624  *
2625  **/
2626 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2627 {
2628         struct ixgbe_hw *hw = &adapter->hw;
2629
2630         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2631                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2632
2633         ixgbe_set_ivar(adapter, 0, 0, 0);
2634         ixgbe_set_ivar(adapter, 1, 0, 0);
2635
2636         map_vector_to_rxq(adapter, 0, 0);
2637         map_vector_to_txq(adapter, 0, 0);
2638
2639         e_info(hw, "Legacy interrupt IVAR setup done\n");
2640 }
2641
2642 /**
2643  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2644  * @adapter: board private structure
2645  * @ring: structure containing ring specific data
2646  *
2647  * Configure the Tx descriptor ring after a reset.
2648  **/
2649 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2650                              struct ixgbe_ring *ring)
2651 {
2652         struct ixgbe_hw *hw = &adapter->hw;
2653         u64 tdba = ring->dma;
2654         int wait_loop = 10;
2655         u32 txdctl;
2656         u8 reg_idx = ring->reg_idx;
2657
2658         /* disable queue to avoid issues while updating state */
2659         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2660         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2661                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2662         IXGBE_WRITE_FLUSH(hw);
2663
2664         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2665                         (tdba & DMA_BIT_MASK(32)));
2666         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2667         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2668                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2669         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2670         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2671         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2672
2673         /* configure fetching thresholds */
2674         if (adapter->rx_itr_setting == 0) {
2675                 /* cannot set wthresh when itr==0 */
2676                 txdctl &= ~0x007F0000;
2677         } else {
2678                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2679                 txdctl |= (8 << 16);
2680         }
2681         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2682                 /* PThresh workaround for Tx hang with DFP enabled. */
2683                 txdctl |= 32;
2684         }
2685
2686         /* reinitialize flowdirector state */
2687         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2688             adapter->atr_sample_rate) {
2689                 ring->atr_sample_rate = adapter->atr_sample_rate;
2690                 ring->atr_count = 0;
2691                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2692         } else {
2693                 ring->atr_sample_rate = 0;
2694         }
2695
2696         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2697
2698         /* enable queue */
2699         txdctl |= IXGBE_TXDCTL_ENABLE;
2700         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2701
2702         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2703         if (hw->mac.type == ixgbe_mac_82598EB &&
2704             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2705                 return;
2706
2707         /* poll to verify queue is enabled */
2708         do {
2709                 msleep(1);
2710                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2711         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2712         if (!wait_loop)
2713                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2714 }
2715
2716 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2717 {
2718         struct ixgbe_hw *hw = &adapter->hw;
2719         u32 rttdcs;
2720         u32 mask;
2721
2722         if (hw->mac.type == ixgbe_mac_82598EB)
2723                 return;
2724
2725         /* disable the arbiter while setting MTQC */
2726         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2727         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2728         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2729
2730         /* set transmit pool layout */
2731         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2732         switch (adapter->flags & mask) {
2733
2734         case (IXGBE_FLAG_SRIOV_ENABLED):
2735                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2736                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2737                 break;
2738
2739         case (IXGBE_FLAG_DCB_ENABLED):
2740                 /* We enable 8 traffic classes, DCB only */
2741                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2742                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2743                 break;
2744
2745         default:
2746                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2747                 break;
2748         }
2749
2750         /* re-enable the arbiter */
2751         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2752         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2753 }
2754
2755 /**
2756  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2757  * @adapter: board private structure
2758  *
2759  * Configure the Tx unit of the MAC after a reset.
2760  **/
2761 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2762 {
2763         struct ixgbe_hw *hw = &adapter->hw;
2764         u32 dmatxctl;
2765         u32 i;
2766
2767         ixgbe_setup_mtqc(adapter);
2768
2769         if (hw->mac.type != ixgbe_mac_82598EB) {
2770                 /* DMATXCTL.EN must be before Tx queues are enabled */
2771                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2772                 dmatxctl |= IXGBE_DMATXCTL_TE;
2773                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2774         }
2775
2776         /* Setup the HW Tx Head and Tail descriptor pointers */
2777         for (i = 0; i < adapter->num_tx_queues; i++)
2778                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2779 }
2780
2781 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2782
2783 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2784                                    struct ixgbe_ring *rx_ring)
2785 {
2786         u32 srrctl;
2787         u8 reg_idx = rx_ring->reg_idx;
2788
2789         switch (adapter->hw.mac.type) {
2790         case ixgbe_mac_82598EB: {
2791                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2792                 const int mask = feature[RING_F_RSS].mask;
2793                 reg_idx = reg_idx & mask;
2794         }
2795                 break;
2796         case ixgbe_mac_82599EB:
2797         default:
2798                 break;
2799         }
2800
2801         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2802
2803         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2804         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2805         if (adapter->num_vfs)
2806                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2807
2808         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2809                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2810
2811         if (ring_is_ps_enabled(rx_ring)) {
2812 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2813                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2814 #else
2815                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2816 #endif
2817                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2818         } else {
2819                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2820                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2821                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2822         }
2823
2824         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2825 }
2826
2827 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2828 {
2829         struct ixgbe_hw *hw = &adapter->hw;
2830         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2831                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2832                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2833         u32 mrqc = 0, reta = 0;
2834         u32 rxcsum;
2835         int i, j;
2836         int mask;
2837
2838         /* Fill out hash function seeds */
2839         for (i = 0; i < 10; i++)
2840                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2841
2842         /* Fill out redirection table */
2843         for (i = 0, j = 0; i < 128; i++, j++) {
2844                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2845                         j = 0;
2846                 /* reta = 4-byte sliding window of
2847                  * 0x00..(indices-1)(indices-1)00..etc. */
2848                 reta = (reta << 8) | (j * 0x11);
2849                 if ((i & 3) == 3)
2850                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2851         }
2852
2853         /* Disable indicating checksum in descriptor, enables RSS hash */
2854         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2855         rxcsum |= IXGBE_RXCSUM_PCSD;
2856         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2857
2858         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2859                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2860         else
2861                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2862 #ifdef CONFIG_IXGBE_DCB
2863                                          | IXGBE_FLAG_DCB_ENABLED
2864 #endif
2865                                          | IXGBE_FLAG_SRIOV_ENABLED
2866                                         );
2867
2868         switch (mask) {
2869         case (IXGBE_FLAG_RSS_ENABLED):
2870                 mrqc = IXGBE_MRQC_RSSEN;
2871                 break;
2872         case (IXGBE_FLAG_SRIOV_ENABLED):
2873                 mrqc = IXGBE_MRQC_VMDQEN;
2874                 break;
2875 #ifdef CONFIG_IXGBE_DCB
2876         case (IXGBE_FLAG_DCB_ENABLED):
2877                 mrqc = IXGBE_MRQC_RT8TCEN;
2878                 break;
2879 #endif /* CONFIG_IXGBE_DCB */
2880         default:
2881                 break;
2882         }
2883
2884         /* Perform hash on these packet types */
2885         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2886               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2887               | IXGBE_MRQC_RSS_FIELD_IPV6
2888               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2889
2890         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2891 }
2892
2893 /**
2894  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2895  * @adapter:    address of board private structure
2896  * @index:      index of ring to set
2897  **/
2898 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2899                                    struct ixgbe_ring *ring)
2900 {
2901         struct ixgbe_hw *hw = &adapter->hw;
2902         u32 rscctrl;
2903         int rx_buf_len;
2904         u8 reg_idx = ring->reg_idx;
2905
2906         if (!ring_is_rsc_enabled(ring))
2907                 return;
2908
2909         rx_buf_len = ring->rx_buf_len;
2910         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2911         rscctrl |= IXGBE_RSCCTL_RSCEN;
2912         /*
2913          * we must limit the number of descriptors so that the
2914          * total size of max desc * buf_len is not greater
2915          * than 65535
2916          */
2917         if (ring_is_ps_enabled(ring)) {
2918 #if (MAX_SKB_FRAGS > 16)
2919                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2920 #elif (MAX_SKB_FRAGS > 8)
2921                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2922 #elif (MAX_SKB_FRAGS > 4)
2923                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2924 #else
2925                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2926 #endif
2927         } else {
2928                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2929                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2930                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2931                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2932                 else
2933                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2934         }
2935         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2936 }
2937
2938 /**
2939  *  ixgbe_set_uta - Set unicast filter table address
2940  *  @adapter: board private structure
2941  *
2942  *  The unicast table address is a register array of 32-bit registers.
2943  *  The table is meant to be used in a way similar to how the MTA is used
2944  *  however due to certain limitations in the hardware it is necessary to
2945  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2946  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2947  **/
2948 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2949 {
2950         struct ixgbe_hw *hw = &adapter->hw;
2951         int i;
2952
2953         /* The UTA table only exists on 82599 hardware and newer */
2954         if (hw->mac.type < ixgbe_mac_82599EB)
2955                 return;
2956
2957         /* we only need to do this if VMDq is enabled */
2958         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2959                 return;
2960
2961         for (i = 0; i < 128; i++)
2962                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2963 }
2964
2965 #define IXGBE_MAX_RX_DESC_POLL 10
2966 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2967                                        struct ixgbe_ring *ring)
2968 {
2969         struct ixgbe_hw *hw = &adapter->hw;
2970         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2971         u32 rxdctl;
2972         u8 reg_idx = ring->reg_idx;
2973
2974         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2975         if (hw->mac.type == ixgbe_mac_82598EB &&
2976             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2977                 return;
2978
2979         do {
2980                 msleep(1);
2981                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2982         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2983
2984         if (!wait_loop) {
2985                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2986                       "the polling period\n", reg_idx);
2987         }
2988 }
2989
2990 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2991                              struct ixgbe_ring *ring)
2992 {
2993         struct ixgbe_hw *hw = &adapter->hw;
2994         u64 rdba = ring->dma;
2995         u32 rxdctl;
2996         u8 reg_idx = ring->reg_idx;
2997
2998         /* disable queue to avoid issues while updating state */
2999         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3000         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
3001                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
3002         IXGBE_WRITE_FLUSH(hw);
3003
3004         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3005         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3006         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3007                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3008         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3009         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3010         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3011
3012         ixgbe_configure_srrctl(adapter, ring);
3013         ixgbe_configure_rscctl(adapter, ring);
3014
3015         if (hw->mac.type == ixgbe_mac_82598EB) {
3016                 /*
3017                  * enable cache line friendly hardware writes:
3018                  * PTHRESH=32 descriptors (half the internal cache),
3019                  * this also removes ugly rx_no_buffer_count increment
3020                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3021                  * WTHRESH=8 burst writeback up to two cache lines
3022                  */
3023                 rxdctl &= ~0x3FFFFF;
3024                 rxdctl |=  0x080420;
3025         }
3026
3027         /* enable receive descriptor ring */
3028         rxdctl |= IXGBE_RXDCTL_ENABLE;
3029         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3030
3031         ixgbe_rx_desc_queue_enable(adapter, ring);
3032         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3033 }
3034
3035 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3036 {
3037         struct ixgbe_hw *hw = &adapter->hw;
3038         int p;
3039
3040         /* PSRTYPE must be initialized in non 82598 adapters */
3041         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3042                       IXGBE_PSRTYPE_UDPHDR |
3043                       IXGBE_PSRTYPE_IPV4HDR |
3044                       IXGBE_PSRTYPE_L2HDR |
3045                       IXGBE_PSRTYPE_IPV6HDR;
3046
3047         if (hw->mac.type == ixgbe_mac_82598EB)
3048                 return;
3049
3050         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3051                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3052
3053         for (p = 0; p < adapter->num_rx_pools; p++)
3054                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3055                                 psrtype);
3056 }
3057
3058 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3059 {
3060         struct ixgbe_hw *hw = &adapter->hw;
3061         u32 gcr_ext;
3062         u32 vt_reg_bits;
3063         u32 reg_offset, vf_shift;
3064         u32 vmdctl;
3065
3066         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3067                 return;
3068
3069         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3070         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3071         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3072         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3073
3074         vf_shift = adapter->num_vfs % 32;
3075         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3076
3077         /* Enable only the PF's pool for Tx/Rx */
3078         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3079         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3080         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3081         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3082         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3083
3084         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3085         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3086
3087         /*
3088          * Set up VF register offsets for selected VT Mode,
3089          * i.e. 32 or 64 VFs for SR-IOV
3090          */
3091         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3092         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3093         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3094         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3095
3096         /* enable Tx loopback for VF/PF communication */
3097         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3098 }
3099
3100 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3101 {
3102         struct ixgbe_hw *hw = &adapter->hw;
3103         struct net_device *netdev = adapter->netdev;
3104         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3105         int rx_buf_len;
3106         struct ixgbe_ring *rx_ring;
3107         int i;
3108         u32 mhadd, hlreg0;
3109
3110         /* Decide whether to use packet split mode or not */
3111         /* Do not use packet split if we're in SR-IOV Mode */
3112         if (!adapter->num_vfs)
3113                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3114
3115         /* Set the RX buffer length according to the mode */
3116         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3117                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3118         } else {
3119                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3120                     (netdev->mtu <= ETH_DATA_LEN))
3121                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3122                 else
3123                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3124         }
3125
3126 #ifdef IXGBE_FCOE
3127         /* adjust max frame to be able to do baby jumbo for FCoE */
3128         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3129             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3130                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3131
3132 #endif /* IXGBE_FCOE */
3133         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3134         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3135                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3136                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3137
3138                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3139         }
3140
3141         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3142         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3143         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3144         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3145
3146         /*
3147          * Setup the HW Rx Head and Tail Descriptor Pointers and
3148          * the Base and Length of the Rx Descriptor Ring
3149          */
3150         for (i = 0; i < adapter->num_rx_queues; i++) {
3151                 rx_ring = adapter->rx_ring[i];
3152                 rx_ring->rx_buf_len = rx_buf_len;
3153
3154                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3155                         set_ring_ps_enabled(rx_ring);
3156                 else
3157                         clear_ring_ps_enabled(rx_ring);
3158
3159                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3160                         set_ring_rsc_enabled(rx_ring);
3161                 else
3162                         clear_ring_rsc_enabled(rx_ring);
3163
3164 #ifdef IXGBE_FCOE
3165                 if (netdev->features & NETIF_F_FCOE_MTU) {
3166                         struct ixgbe_ring_feature *f;
3167                         f = &adapter->ring_feature[RING_F_FCOE];
3168                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3169                                 clear_ring_ps_enabled(rx_ring);
3170                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3171                                         rx_ring->rx_buf_len =
3172                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3173                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3174                                    !ring_is_ps_enabled(rx_ring)) {
3175                                 rx_ring->rx_buf_len =
3176                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3177                         }
3178                 }
3179 #endif /* IXGBE_FCOE */
3180         }
3181 }
3182
3183 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3184 {
3185         struct ixgbe_hw *hw = &adapter->hw;
3186         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3187
3188         switch (hw->mac.type) {
3189         case ixgbe_mac_82598EB:
3190                 /*
3191                  * For VMDq support of different descriptor types or
3192                  * buffer sizes through the use of multiple SRRCTL
3193                  * registers, RDRXCTL.MVMEN must be set to 1
3194                  *
3195                  * also, the manual doesn't mention it clearly but DCA hints
3196                  * will only use queue 0's tags unless this bit is set.  Side
3197                  * effects of setting this bit are only that SRRCTL must be
3198                  * fully programmed [0..15]
3199                  */
3200                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3201                 break;
3202         case ixgbe_mac_82599EB:
3203                 /* Disable RSC for ACK packets */
3204                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3205                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3206                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3207                 /* hardware requires some bits to be set by default */
3208                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3209                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3210                 break;
3211         default:
3212                 /* We should do nothing since we don't know this hardware */
3213                 return;
3214         }
3215
3216         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3217 }
3218
3219 /**
3220  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3221  * @adapter: board private structure
3222  *
3223  * Configure the Rx unit of the MAC after a reset.
3224  **/
3225 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3226 {
3227         struct ixgbe_hw *hw = &adapter->hw;
3228         int i;
3229         u32 rxctrl;
3230
3231         /* disable receives while setting up the descriptors */
3232         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3233         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3234
3235         ixgbe_setup_psrtype(adapter);
3236         ixgbe_setup_rdrxctl(adapter);
3237
3238         /* Program registers for the distribution of queues */
3239         ixgbe_setup_mrqc(adapter);
3240
3241         ixgbe_set_uta(adapter);
3242
3243         /* set_rx_buffer_len must be called before ring initialization */
3244         ixgbe_set_rx_buffer_len(adapter);
3245
3246         /*
3247          * Setup the HW Rx Head and Tail Descriptor Pointers and
3248          * the Base and Length of the Rx Descriptor Ring
3249          */
3250         for (i = 0; i < adapter->num_rx_queues; i++)
3251                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3252
3253         /* disable drop enable for 82598 parts */
3254         if (hw->mac.type == ixgbe_mac_82598EB)
3255                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3256
3257         /* enable all receives */
3258         rxctrl |= IXGBE_RXCTRL_RXEN;
3259         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3260 }
3261
3262 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3263 {
3264         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3265         struct ixgbe_hw *hw = &adapter->hw;
3266         int pool_ndx = adapter->num_vfs;
3267
3268         /* add VID to filter table */
3269         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3270         set_bit(vid, adapter->active_vlans);
3271 }
3272
3273 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3274 {
3275         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3276         struct ixgbe_hw *hw = &adapter->hw;
3277         int pool_ndx = adapter->num_vfs;
3278
3279         /* remove VID from filter table */
3280         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3281         clear_bit(vid, adapter->active_vlans);
3282 }
3283
3284 /**
3285  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3286  * @adapter: driver data
3287  */
3288 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3289 {
3290         struct ixgbe_hw *hw = &adapter->hw;
3291         u32 vlnctrl;
3292
3293         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3294         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3295         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3296 }
3297
3298 /**
3299  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3300  * @adapter: driver data
3301  */
3302 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3303 {
3304         struct ixgbe_hw *hw = &adapter->hw;
3305         u32 vlnctrl;
3306
3307         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3308         vlnctrl |= IXGBE_VLNCTRL_VFE;
3309         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3310         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3311 }
3312
3313 /**
3314  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3315  * @adapter: driver data
3316  */
3317 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3318 {
3319         struct ixgbe_hw *hw = &adapter->hw;
3320         u32 vlnctrl;
3321         int i, j;
3322
3323         switch (hw->mac.type) {
3324         case ixgbe_mac_82598EB:
3325                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3326                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3327                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3328                 break;
3329         case ixgbe_mac_82599EB:
3330                 for (i = 0; i < adapter->num_rx_queues; i++) {
3331                         j = adapter->rx_ring[i]->reg_idx;
3332                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3333                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3334                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3335                 }
3336                 break;
3337         default:
3338                 break;
3339         }
3340 }
3341
3342 /**
3343  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3344  * @adapter: driver data
3345  */
3346 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3347 {
3348         struct ixgbe_hw *hw = &adapter->hw;
3349         u32 vlnctrl;
3350         int i, j;
3351
3352         switch (hw->mac.type) {
3353         case ixgbe_mac_82598EB:
3354                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3355                 vlnctrl |= IXGBE_VLNCTRL_VME;
3356                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3357                 break;
3358         case ixgbe_mac_82599EB:
3359                 for (i = 0; i < adapter->num_rx_queues; i++) {
3360                         j = adapter->rx_ring[i]->reg_idx;
3361                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3362                         vlnctrl |= IXGBE_RXDCTL_VME;
3363                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3364                 }
3365                 break;
3366         default:
3367                 break;
3368         }
3369 }
3370
3371 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3372 {
3373         u16 vid;
3374
3375         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3376
3377         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3378                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3379 }
3380
3381 /**
3382  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3383  * @netdev: network interface device structure
3384  *
3385  * Writes unicast address list to the RAR table.
3386  * Returns: -ENOMEM on failure/insufficient address space
3387  *                0 on no addresses written
3388  *                X on writing X addresses to the RAR table
3389  **/
3390 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3391 {
3392         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393         struct ixgbe_hw *hw = &adapter->hw;
3394         unsigned int vfn = adapter->num_vfs;
3395         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3396         int count = 0;
3397
3398         /* return ENOMEM indicating insufficient memory for addresses */
3399         if (netdev_uc_count(netdev) > rar_entries)
3400                 return -ENOMEM;
3401
3402         if (!netdev_uc_empty(netdev) && rar_entries) {
3403                 struct netdev_hw_addr *ha;
3404                 /* return error if we do not support writing to RAR table */
3405                 if (!hw->mac.ops.set_rar)
3406                         return -ENOMEM;
3407
3408                 netdev_for_each_uc_addr(ha, netdev) {
3409                         if (!rar_entries)
3410                                 break;
3411                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3412                                             vfn, IXGBE_RAH_AV);
3413                         count++;
3414                 }
3415         }
3416         /* write the addresses in reverse order to avoid write combining */
3417         for (; rar_entries > 0 ; rar_entries--)
3418                 hw->mac.ops.clear_rar(hw, rar_entries);
3419
3420         return count;
3421 }
3422
3423 /**
3424  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3425  * @netdev: network interface device structure
3426  *
3427  * The set_rx_method entry point is called whenever the unicast/multicast
3428  * address list or the network interface flags are updated.  This routine is
3429  * responsible for configuring the hardware for proper unicast, multicast and
3430  * promiscuous mode.
3431  **/
3432 void ixgbe_set_rx_mode(struct net_device *netdev)
3433 {
3434         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3435         struct ixgbe_hw *hw = &adapter->hw;
3436         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3437         int count;
3438
3439         /* Check for Promiscuous and All Multicast modes */
3440
3441         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3442
3443         /* set all bits that we expect to always be set */
3444         fctrl |= IXGBE_FCTRL_BAM;
3445         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3446         fctrl |= IXGBE_FCTRL_PMCF;
3447
3448         /* clear the bits we are changing the status of */
3449         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3450
3451         if (netdev->flags & IFF_PROMISC) {
3452                 hw->addr_ctrl.user_set_promisc = true;
3453                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3454                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3455                 /* don't hardware filter vlans in promisc mode */
3456                 ixgbe_vlan_filter_disable(adapter);
3457         } else {
3458                 if (netdev->flags & IFF_ALLMULTI) {
3459                         fctrl |= IXGBE_FCTRL_MPE;
3460                         vmolr |= IXGBE_VMOLR_MPE;
3461                 } else {
3462                         /*
3463                          * Write addresses to the MTA, if the attempt fails
3464                          * then we should just turn on promiscous mode so
3465                          * that we can at least receive multicast traffic
3466                          */
3467                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3468                         vmolr |= IXGBE_VMOLR_ROMPE;
3469                 }
3470                 ixgbe_vlan_filter_enable(adapter);
3471                 hw->addr_ctrl.user_set_promisc = false;
3472                 /*
3473                  * Write addresses to available RAR registers, if there is not
3474                  * sufficient space to store all the addresses then enable
3475                  * unicast promiscous mode
3476                  */
3477                 count = ixgbe_write_uc_addr_list(netdev);
3478                 if (count < 0) {
3479                         fctrl |= IXGBE_FCTRL_UPE;
3480                         vmolr |= IXGBE_VMOLR_ROPE;
3481                 }
3482         }
3483
3484         if (adapter->num_vfs) {
3485                 ixgbe_restore_vf_multicasts(adapter);
3486                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3487                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3488                            IXGBE_VMOLR_ROPE);
3489                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3490         }
3491
3492         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3493
3494         if (netdev->features & NETIF_F_HW_VLAN_RX)
3495                 ixgbe_vlan_strip_enable(adapter);
3496         else
3497                 ixgbe_vlan_strip_disable(adapter);
3498 }
3499
3500 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3501 {
3502         int q_idx;
3503         struct ixgbe_q_vector *q_vector;
3504         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3505
3506         /* legacy and MSI only use one vector */
3507         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3508                 q_vectors = 1;
3509
3510         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3511                 struct napi_struct *napi;
3512                 q_vector = adapter->q_vector[q_idx];
3513                 napi = &q_vector->napi;
3514                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3515                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3516                                 if (q_vector->txr_count == 1)
3517                                         napi->poll = &ixgbe_clean_txonly;
3518                                 else if (q_vector->rxr_count == 1)
3519                                         napi->poll = &ixgbe_clean_rxonly;
3520                         }
3521                 }
3522
3523                 napi_enable(napi);
3524         }
3525 }
3526
3527 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3528 {
3529         int q_idx;
3530         struct ixgbe_q_vector *q_vector;
3531         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3532
3533         /* legacy and MSI only use one vector */
3534         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3535                 q_vectors = 1;
3536
3537         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3538                 q_vector = adapter->q_vector[q_idx];
3539                 napi_disable(&q_vector->napi);
3540         }
3541 }
3542
3543 #ifdef CONFIG_IXGBE_DCB
3544 /*
3545  * ixgbe_configure_dcb - Configure DCB hardware
3546  * @adapter: ixgbe adapter struct
3547  *
3548  * This is called by the driver on open to configure the DCB hardware.
3549  * This is also called by the gennetlink interface when reconfiguring
3550  * the DCB state.
3551  */
3552 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3553 {
3554         struct ixgbe_hw *hw = &adapter->hw;
3555         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3556
3557         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3558                 if (hw->mac.type == ixgbe_mac_82598EB)
3559                         netif_set_gso_max_size(adapter->netdev, 65536);
3560                 return;
3561         }
3562
3563         if (hw->mac.type == ixgbe_mac_82598EB)
3564                 netif_set_gso_max_size(adapter->netdev, 32768);
3565
3566 #ifdef CONFIG_FCOE
3567         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3568                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3569 #endif
3570
3571         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3572                                         DCB_TX_CONFIG);
3573         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3574                                         DCB_RX_CONFIG);
3575
3576         /* Enable VLAN tag insert/strip */
3577         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3578
3579         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3580
3581         /* reconfigure the hardware */
3582         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3583 }
3584
3585 #endif
3586 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3587 {
3588         struct net_device *netdev = adapter->netdev;
3589         struct ixgbe_hw *hw = &adapter->hw;
3590         int i;
3591
3592 #ifdef CONFIG_IXGBE_DCB
3593         ixgbe_configure_dcb(adapter);
3594 #endif
3595
3596         ixgbe_set_rx_mode(netdev);
3597         ixgbe_restore_vlan(adapter);
3598
3599 #ifdef IXGBE_FCOE
3600         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3601                 ixgbe_configure_fcoe(adapter);
3602
3603 #endif /* IXGBE_FCOE */
3604         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3605                 for (i = 0; i < adapter->num_tx_queues; i++)
3606                         adapter->tx_ring[i]->atr_sample_rate =
3607                                                        adapter->atr_sample_rate;
3608                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3609         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3610                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3611         }
3612         ixgbe_configure_virtualization(adapter);
3613
3614         ixgbe_configure_tx(adapter);
3615         ixgbe_configure_rx(adapter);
3616 }
3617
3618 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3619 {
3620         switch (hw->phy.type) {
3621         case ixgbe_phy_sfp_avago:
3622         case ixgbe_phy_sfp_ftl:
3623         case ixgbe_phy_sfp_intel:
3624         case ixgbe_phy_sfp_unknown:
3625         case ixgbe_phy_sfp_passive_tyco:
3626         case ixgbe_phy_sfp_passive_unknown:
3627         case ixgbe_phy_sfp_active_unknown:
3628         case ixgbe_phy_sfp_ftl_active:
3629                 return true;
3630         default:
3631                 return false;
3632         }
3633 }
3634
3635 /**
3636  * ixgbe_sfp_link_config - set up SFP+ link
3637  * @adapter: pointer to private adapter struct
3638  **/
3639 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3640 {
3641         struct ixgbe_hw *hw = &adapter->hw;
3642
3643                 if (hw->phy.multispeed_fiber) {
3644                         /*
3645                          * In multispeed fiber setups, the device may not have
3646                          * had a physical connection when the driver loaded.
3647                          * If that's the case, the initial link configuration
3648                          * couldn't get the MAC into 10G or 1G mode, so we'll
3649                          * never have a link status change interrupt fire.
3650                          * We need to try and force an autonegotiation
3651                          * session, then bring up link.
3652                          */
3653                         hw->mac.ops.setup_sfp(hw);
3654                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3655                                 schedule_work(&adapter->multispeed_fiber_task);
3656                 } else {
3657                         /*
3658                          * Direct Attach Cu and non-multispeed fiber modules
3659                          * still need to be configured properly prior to
3660                          * attempting link.
3661                          */
3662                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3663                                 schedule_work(&adapter->sfp_config_module_task);
3664                 }
3665 }
3666
3667 /**
3668  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3669  * @hw: pointer to private hardware struct
3670  *
3671  * Returns 0 on success, negative on failure
3672  **/
3673 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3674 {
3675         u32 autoneg;
3676         bool negotiation, link_up = false;
3677         u32 ret = IXGBE_ERR_LINK_SETUP;
3678
3679         if (hw->mac.ops.check_link)
3680                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3681
3682         if (ret)
3683                 goto link_cfg_out;
3684
3685         if (hw->mac.ops.get_link_capabilities)
3686                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3687                                                         &negotiation);
3688         if (ret)
3689                 goto link_cfg_out;
3690
3691         if (hw->mac.ops.setup_link)
3692                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3693 link_cfg_out:
3694         return ret;
3695 }
3696
3697 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3698 {
3699         struct ixgbe_hw *hw = &adapter->hw;
3700         u32 gpie = 0;
3701
3702         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3703                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3704                        IXGBE_GPIE_OCD;
3705                 gpie |= IXGBE_GPIE_EIAME;
3706                 /*
3707                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3708                  * this saves a register write for every interrupt
3709                  */
3710                 switch (hw->mac.type) {
3711                 case ixgbe_mac_82598EB:
3712                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3713                         break;
3714                 default:
3715                 case ixgbe_mac_82599EB:
3716                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3717                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3718                         break;
3719                 }
3720         } else {
3721                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3722                  * specifically only auto mask tx and rx interrupts */
3723                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3724         }
3725
3726         /* XXX: to interrupt immediately for EICS writes, enable this */
3727         /* gpie |= IXGBE_GPIE_EIMEN; */
3728
3729         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3730                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3731                 gpie |= IXGBE_GPIE_VTMODE_64;
3732         }
3733
3734         /* Enable fan failure interrupt */
3735         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3736                 gpie |= IXGBE_SDP1_GPIEN;
3737
3738         if (hw->mac.type == ixgbe_mac_82599EB)
3739                 gpie |= IXGBE_SDP1_GPIEN;
3740                 gpie |= IXGBE_SDP2_GPIEN;
3741
3742         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3743 }
3744
3745 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3746 {
3747         struct ixgbe_hw *hw = &adapter->hw;
3748         int err;
3749         u32 ctrl_ext;
3750
3751         ixgbe_get_hw_control(adapter);
3752         ixgbe_setup_gpie(adapter);
3753
3754         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3755                 ixgbe_configure_msix(adapter);
3756         else
3757                 ixgbe_configure_msi_and_legacy(adapter);
3758
3759         /* enable the optics */
3760         if (hw->phy.multispeed_fiber && hw->mac.ops.enable_tx_laser)
3761                 hw->mac.ops.enable_tx_laser(hw);
3762
3763         clear_bit(__IXGBE_DOWN, &adapter->state);
3764         ixgbe_napi_enable_all(adapter);
3765
3766         if (ixgbe_is_sfp(hw)) {
3767                 ixgbe_sfp_link_config(adapter);
3768         } else {
3769                 err = ixgbe_non_sfp_link_config(hw);
3770                 if (err)
3771                         e_err(probe, "link_config FAILED %d\n", err);
3772         }
3773
3774         /* clear any pending interrupts, may auto mask */
3775         IXGBE_READ_REG(hw, IXGBE_EICR);
3776         ixgbe_irq_enable(adapter, true, true);
3777
3778         /*
3779          * If this adapter has a fan, check to see if we had a failure
3780          * before we enabled the interrupt.
3781          */
3782         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3783                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3784                 if (esdp & IXGBE_ESDP_SDP1)
3785                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3786         }
3787
3788         /*
3789          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3790          * arrived before interrupts were enabled but after probe.  Such
3791          * devices wouldn't have their type identified yet. We need to
3792          * kick off the SFP+ module setup first, then try to bring up link.
3793          * If we're not hot-pluggable SFP+, we just need to configure link
3794          * and bring it up.
3795          */
3796         if (hw->phy.type == ixgbe_phy_unknown)
3797                 schedule_work(&adapter->sfp_config_module_task);
3798
3799         /* enable transmits */
3800         netif_tx_start_all_queues(adapter->netdev);
3801
3802         /* bring the link up in the watchdog, this could race with our first
3803          * link up interrupt but shouldn't be a problem */
3804         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3805         adapter->link_check_timeout = jiffies;
3806         mod_timer(&adapter->watchdog_timer, jiffies);
3807
3808         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3809         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3810         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3811         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3812
3813         return 0;
3814 }
3815
3816 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3817 {
3818         WARN_ON(in_interrupt());
3819         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3820                 msleep(1);
3821         ixgbe_down(adapter);
3822         /*
3823          * If SR-IOV enabled then wait a bit before bringing the adapter
3824          * back up to give the VFs time to respond to the reset.  The
3825          * two second wait is based upon the watchdog timer cycle in
3826          * the VF driver.
3827          */
3828         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3829                 msleep(2000);
3830         ixgbe_up(adapter);
3831         clear_bit(__IXGBE_RESETTING, &adapter->state);
3832 }
3833
3834 int ixgbe_up(struct ixgbe_adapter *adapter)
3835 {
3836         /* hardware has been reset, we need to reload some things */
3837         ixgbe_configure(adapter);
3838
3839         return ixgbe_up_complete(adapter);
3840 }
3841
3842 void ixgbe_reset(struct ixgbe_adapter *adapter)
3843 {
3844         struct ixgbe_hw *hw = &adapter->hw;
3845         int err;
3846
3847         err = hw->mac.ops.init_hw(hw);
3848         switch (err) {
3849         case 0:
3850         case IXGBE_ERR_SFP_NOT_PRESENT:
3851                 break;
3852         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3853                 e_dev_err("master disable timed out\n");
3854                 break;
3855         case IXGBE_ERR_EEPROM_VERSION:
3856                 /* We are running on a pre-production device, log a warning */
3857                 e_dev_warn("This device is a pre-production adapter/LOM. "
3858                            "Please be aware there may be issuesassociated with "
3859                            "your hardware.  If you are experiencing problems "
3860                            "please contact your Intel or hardware "
3861                            "representative who provided you with this "
3862                            "hardware.\n");
3863                 break;
3864         default:
3865                 e_dev_err("Hardware Error: %d\n", err);
3866         }
3867
3868         /* reprogram the RAR[0] in case user changed it. */
3869         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3870                             IXGBE_RAH_AV);
3871 }
3872
3873 /**
3874  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3875  * @rx_ring: ring to free buffers from
3876  **/
3877 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3878 {
3879         struct device *dev = rx_ring->dev;
3880         unsigned long size;
3881         u16 i;
3882
3883         /* ring already cleared, nothing to do */
3884         if (!rx_ring->rx_buffer_info)
3885                 return;
3886
3887         /* Free all the Rx ring sk_buffs */
3888         for (i = 0; i < rx_ring->count; i++) {
3889                 struct ixgbe_rx_buffer *rx_buffer_info;
3890
3891                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3892                 if (rx_buffer_info->dma) {
3893                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3894                                          rx_ring->rx_buf_len,
3895                                          DMA_FROM_DEVICE);
3896                         rx_buffer_info->dma = 0;
3897                 }
3898                 if (rx_buffer_info->skb) {
3899                         struct sk_buff *skb = rx_buffer_info->skb;
3900                         rx_buffer_info->skb = NULL;
3901                         do {
3902                                 struct sk_buff *this = skb;
3903                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3904                                         dma_unmap_single(dev,
3905                                                          IXGBE_RSC_CB(this)->dma,
3906                                                          rx_ring->rx_buf_len,
3907                                                          DMA_FROM_DEVICE);
3908                                         IXGBE_RSC_CB(this)->dma = 0;
3909                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3910                                 }
3911                                 skb = skb->prev;
3912                                 dev_kfree_skb(this);
3913                         } while (skb);
3914                 }
3915                 if (!rx_buffer_info->page)
3916                         continue;
3917                 if (rx_buffer_info->page_dma) {
3918                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3919                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3920                         rx_buffer_info->page_dma = 0;
3921                 }
3922                 put_page(rx_buffer_info->page);
3923                 rx_buffer_info->page = NULL;
3924                 rx_buffer_info->page_offset = 0;
3925         }
3926
3927         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3928         memset(rx_ring->rx_buffer_info, 0, size);
3929
3930         /* Zero out the descriptor ring */
3931         memset(rx_ring->desc, 0, rx_ring->size);
3932
3933         rx_ring->next_to_clean = 0;
3934         rx_ring->next_to_use = 0;
3935 }
3936
3937 /**
3938  * ixgbe_clean_tx_ring - Free Tx Buffers
3939  * @tx_ring: ring to be cleaned
3940  **/
3941 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3942 {
3943         struct ixgbe_tx_buffer *tx_buffer_info;
3944         unsigned long size;
3945         u16 i;
3946
3947         /* ring already cleared, nothing to do */
3948         if (!tx_ring->tx_buffer_info)
3949                 return;
3950
3951         /* Free all the Tx ring sk_buffs */
3952         for (i = 0; i < tx_ring->count; i++) {
3953                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3954                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3955         }
3956
3957         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3958         memset(tx_ring->tx_buffer_info, 0, size);
3959
3960         /* Zero out the descriptor ring */
3961         memset(tx_ring->desc, 0, tx_ring->size);
3962
3963         tx_ring->next_to_use = 0;
3964         tx_ring->next_to_clean = 0;
3965 }
3966
3967 /**
3968  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3969  * @adapter: board private structure
3970  **/
3971 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3972 {
3973         int i;
3974
3975         for (i = 0; i < adapter->num_rx_queues; i++)
3976                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3977 }
3978
3979 /**
3980  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3981  * @adapter: board private structure
3982  **/
3983 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3984 {
3985         int i;
3986
3987         for (i = 0; i < adapter->num_tx_queues; i++)
3988                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3989 }
3990
3991 void ixgbe_down(struct ixgbe_adapter *adapter)
3992 {
3993         struct net_device *netdev = adapter->netdev;
3994         struct ixgbe_hw *hw = &adapter->hw;
3995         u32 rxctrl;
3996         u32 txdctl;
3997         int i;
3998         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3999
4000         /* signal that we are down to the interrupt handler */
4001         set_bit(__IXGBE_DOWN, &adapter->state);
4002
4003         /* disable receive for all VFs and wait one second */
4004         if (adapter->num_vfs) {
4005                 /* ping all the active vfs to let them know we are going down */
4006                 ixgbe_ping_all_vfs(adapter);
4007
4008                 /* Disable all VFTE/VFRE TX/RX */
4009                 ixgbe_disable_tx_rx(adapter);
4010
4011                 /* Mark all the VFs as inactive */
4012                 for (i = 0 ; i < adapter->num_vfs; i++)
4013                         adapter->vfinfo[i].clear_to_send = 0;
4014         }
4015
4016         /* disable receives */
4017         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4018         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4019
4020         IXGBE_WRITE_FLUSH(hw);
4021         msleep(10);
4022
4023         netif_tx_stop_all_queues(netdev);
4024
4025         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4026         del_timer_sync(&adapter->sfp_timer);
4027         del_timer_sync(&adapter->watchdog_timer);
4028         cancel_work_sync(&adapter->watchdog_task);
4029
4030         netif_carrier_off(netdev);
4031         netif_tx_disable(netdev);
4032
4033         ixgbe_irq_disable(adapter);
4034
4035         ixgbe_napi_disable_all(adapter);
4036
4037         /* Cleanup the affinity_hint CPU mask memory and callback */
4038         for (i = 0; i < num_q_vectors; i++) {
4039                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4040                 /* clear the affinity_mask in the IRQ descriptor */
4041                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4042                 /* release the CPU mask memory */
4043                 free_cpumask_var(q_vector->affinity_mask);
4044         }
4045
4046         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4047             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
4048                 cancel_work_sync(&adapter->fdir_reinit_task);
4049
4050         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4051                 cancel_work_sync(&adapter->check_overtemp_task);
4052
4053         /* disable transmits in the hardware now that interrupts are off */
4054         for (i = 0; i < adapter->num_tx_queues; i++) {
4055                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4056                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
4057                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
4058                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
4059         }
4060         /* Disable the Tx DMA engine on 82599 */
4061         switch (hw->mac.type) {
4062         case ixgbe_mac_82599EB:
4063                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4064                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4065                                  ~IXGBE_DMATXCTL_TE));
4066                 break;
4067         default:
4068                 break;
4069         }
4070
4071         /* power down the optics */
4072         if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
4073                 hw->mac.ops.disable_tx_laser(hw);
4074
4075         /* clear n-tuple filters that are cached */
4076         ethtool_ntuple_flush(netdev);
4077
4078         if (!pci_channel_offline(adapter->pdev))
4079                 ixgbe_reset(adapter);
4080         ixgbe_clean_all_tx_rings(adapter);
4081         ixgbe_clean_all_rx_rings(adapter);
4082
4083 #ifdef CONFIG_IXGBE_DCA
4084         /* since we reset the hardware DCA settings were cleared */
4085         ixgbe_setup_dca(adapter);
4086 #endif
4087 }
4088
4089 /**
4090  * ixgbe_poll - NAPI Rx polling callback
4091  * @napi: structure for representing this polling device
4092  * @budget: how many packets driver is allowed to clean
4093  *
4094  * This function is used for legacy and MSI, NAPI mode
4095  **/
4096 static int ixgbe_poll(struct napi_struct *napi, int budget)
4097 {
4098         struct ixgbe_q_vector *q_vector =
4099                                 container_of(napi, struct ixgbe_q_vector, napi);
4100         struct ixgbe_adapter *adapter = q_vector->adapter;
4101         int tx_clean_complete, work_done = 0;
4102
4103 #ifdef CONFIG_IXGBE_DCA
4104         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4105                 ixgbe_update_dca(q_vector);
4106 #endif
4107
4108         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4109         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4110
4111         if (!tx_clean_complete)
4112                 work_done = budget;
4113
4114         /* If budget not fully consumed, exit the polling mode */
4115         if (work_done < budget) {
4116                 napi_complete(napi);
4117                 if (adapter->rx_itr_setting & 1)
4118                         ixgbe_set_itr(adapter);
4119                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4120                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4121         }
4122         return work_done;
4123 }
4124
4125 /**
4126  * ixgbe_tx_timeout - Respond to a Tx Hang
4127  * @netdev: network interface device structure
4128  **/
4129 static void ixgbe_tx_timeout(struct net_device *netdev)
4130 {
4131         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4132
4133         adapter->tx_timeout_count++;
4134
4135         /* Do the reset outside of interrupt context */
4136         schedule_work(&adapter->reset_task);
4137 }
4138
4139 static void ixgbe_reset_task(struct work_struct *work)
4140 {
4141         struct ixgbe_adapter *adapter;
4142         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4143
4144         /* If we're already down or resetting, just bail */
4145         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4146             test_bit(__IXGBE_RESETTING, &adapter->state))
4147                 return;
4148
4149         ixgbe_dump(adapter);
4150         netdev_err(adapter->netdev, "Reset adapter\n");
4151         ixgbe_reinit_locked(adapter);
4152 }
4153
4154 #ifdef CONFIG_IXGBE_DCB
4155 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4156 {
4157         bool ret = false;
4158         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4159
4160         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4161                 return ret;
4162
4163         f->mask = 0x7 << 3;
4164         adapter->num_rx_queues = f->indices;
4165         adapter->num_tx_queues = f->indices;
4166         ret = true;
4167
4168         return ret;
4169 }
4170 #endif
4171
4172 /**
4173  * ixgbe_set_rss_queues: Allocate queues for RSS
4174  * @adapter: board private structure to initialize
4175  *
4176  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4177  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4178  *
4179  **/
4180 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4181 {
4182         bool ret = false;
4183         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4184
4185         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4186                 f->mask = 0xF;
4187                 adapter->num_rx_queues = f->indices;
4188                 adapter->num_tx_queues = f->indices;
4189                 ret = true;
4190         } else {
4191                 ret = false;
4192         }
4193
4194         return ret;
4195 }
4196
4197 /**
4198  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4199  * @adapter: board private structure to initialize
4200  *
4201  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4202  * to the original CPU that initiated the Tx session.  This runs in addition
4203  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4204  * Rx load across CPUs using RSS.
4205  *
4206  **/
4207 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4208 {
4209         bool ret = false;
4210         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4211
4212         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4213         f_fdir->mask = 0;
4214
4215         /* Flow Director must have RSS enabled */
4216         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4217             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4218              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4219                 adapter->num_tx_queues = f_fdir->indices;
4220                 adapter->num_rx_queues = f_fdir->indices;
4221                 ret = true;
4222         } else {
4223                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4224                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4225         }
4226         return ret;
4227 }
4228
4229 #ifdef IXGBE_FCOE
4230 /**
4231  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4232  * @adapter: board private structure to initialize
4233  *
4234  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4235  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4236  * rx queues out of the max number of rx queues, instead, it is used as the
4237  * index of the first rx queue used by FCoE.
4238  *
4239  **/
4240 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4241 {
4242         bool ret = false;
4243         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4244
4245         f->indices = min((int)num_online_cpus(), f->indices);
4246         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4247                 adapter->num_rx_queues = 1;
4248                 adapter->num_tx_queues = 1;
4249 #ifdef CONFIG_IXGBE_DCB
4250                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4251                         e_info(probe, "FCoE enabled with DCB\n");
4252                         ixgbe_set_dcb_queues(adapter);
4253                 }
4254 #endif
4255                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4256                         e_info(probe, "FCoE enabled with RSS\n");
4257                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4258                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4259                                 ixgbe_set_fdir_queues(adapter);
4260                         else
4261                                 ixgbe_set_rss_queues(adapter);
4262                 }
4263                 /* adding FCoE rx rings to the end */
4264                 f->mask = adapter->num_rx_queues;
4265                 adapter->num_rx_queues += f->indices;
4266                 adapter->num_tx_queues += f->indices;
4267
4268                 ret = true;
4269         }
4270
4271         return ret;
4272 }
4273
4274 #endif /* IXGBE_FCOE */
4275 /**
4276  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4277  * @adapter: board private structure to initialize
4278  *
4279  * IOV doesn't actually use anything, so just NAK the
4280  * request for now and let the other queue routines
4281  * figure out what to do.
4282  */
4283 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4284 {
4285         return false;
4286 }
4287
4288 /*
4289  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4290  * @adapter: board private structure to initialize
4291  *
4292  * This is the top level queue allocation routine.  The order here is very
4293  * important, starting with the "most" number of features turned on at once,
4294  * and ending with the smallest set of features.  This way large combinations
4295  * can be allocated if they're turned on, and smaller combinations are the
4296  * fallthrough conditions.
4297  *
4298  **/
4299 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4300 {
4301         /* Start with base case */
4302         adapter->num_rx_queues = 1;
4303         adapter->num_tx_queues = 1;
4304         adapter->num_rx_pools = adapter->num_rx_queues;
4305         adapter->num_rx_queues_per_pool = 1;
4306
4307         if (ixgbe_set_sriov_queues(adapter))
4308                 goto done;
4309
4310 #ifdef IXGBE_FCOE
4311         if (ixgbe_set_fcoe_queues(adapter))
4312                 goto done;
4313
4314 #endif /* IXGBE_FCOE */
4315 #ifdef CONFIG_IXGBE_DCB
4316         if (ixgbe_set_dcb_queues(adapter))
4317                 goto done;
4318
4319 #endif
4320         if (ixgbe_set_fdir_queues(adapter))
4321                 goto done;
4322
4323         if (ixgbe_set_rss_queues(adapter))
4324                 goto done;
4325
4326         /* fallback to base case */
4327         adapter->num_rx_queues = 1;
4328         adapter->num_tx_queues = 1;
4329
4330 done:
4331         /* Notify the stack of the (possibly) reduced queue counts. */
4332         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4333         return netif_set_real_num_rx_queues(adapter->netdev,
4334                                             adapter->num_rx_queues);
4335 }
4336
4337 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4338                                        int vectors)
4339 {
4340         int err, vector_threshold;
4341
4342         /* We'll want at least 3 (vector_threshold):
4343          * 1) TxQ[0] Cleanup
4344          * 2) RxQ[0] Cleanup
4345          * 3) Other (Link Status Change, etc.)
4346          * 4) TCP Timer (optional)
4347          */
4348         vector_threshold = MIN_MSIX_COUNT;
4349
4350         /* The more we get, the more we will assign to Tx/Rx Cleanup
4351          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4352          * Right now, we simply care about how many we'll get; we'll
4353          * set them up later while requesting irq's.
4354          */
4355         while (vectors >= vector_threshold) {
4356                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4357                                       vectors);
4358                 if (!err) /* Success in acquiring all requested vectors. */
4359                         break;
4360                 else if (err < 0)
4361                         vectors = 0; /* Nasty failure, quit now */
4362                 else /* err == number of vectors we should try again with */
4363                         vectors = err;
4364         }
4365
4366         if (vectors < vector_threshold) {
4367                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4368                  * This just means we'll go with either a single MSI
4369                  * vector or fall back to legacy interrupts.
4370                  */
4371                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4372                              "Unable to allocate MSI-X interrupts\n");
4373                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4374                 kfree(adapter->msix_entries);
4375                 adapter->msix_entries = NULL;
4376         } else {
4377                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4378                 /*
4379                  * Adjust for only the vectors we'll use, which is minimum
4380                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4381                  * vectors we were allocated.
4382                  */
4383                 adapter->num_msix_vectors = min(vectors,
4384                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4385         }
4386 }
4387
4388 /**
4389  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4390  * @adapter: board private structure to initialize
4391  *
4392  * Cache the descriptor ring offsets for RSS to the assigned rings.
4393  *
4394  **/
4395 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4396 {
4397         int i;
4398
4399         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4400                 return false;
4401
4402         for (i = 0; i < adapter->num_rx_queues; i++)
4403                 adapter->rx_ring[i]->reg_idx = i;
4404         for (i = 0; i < adapter->num_tx_queues; i++)
4405                 adapter->tx_ring[i]->reg_idx = i;
4406
4407         return true;
4408 }
4409
4410 #ifdef CONFIG_IXGBE_DCB
4411 /**
4412  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4413  * @adapter: board private structure to initialize
4414  *
4415  * Cache the descriptor ring offsets for DCB to the assigned rings.
4416  *
4417  **/
4418 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4419 {
4420         int i;
4421         bool ret = false;
4422         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4423
4424         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4425                 return false;
4426
4427         /* the number of queues is assumed to be symmetric */
4428         switch (adapter->hw.mac.type) {
4429         case ixgbe_mac_82598EB:
4430                 for (i = 0; i < dcb_i; i++) {
4431                         adapter->rx_ring[i]->reg_idx = i << 3;
4432                         adapter->tx_ring[i]->reg_idx = i << 2;
4433                 }
4434                 ret = true;
4435                 break;
4436         case ixgbe_mac_82599EB:
4437                 if (dcb_i == 8) {
4438                         /*
4439                          * Tx TC0 starts at: descriptor queue 0
4440                          * Tx TC1 starts at: descriptor queue 32
4441                          * Tx TC2 starts at: descriptor queue 64
4442                          * Tx TC3 starts at: descriptor queue 80
4443                          * Tx TC4 starts at: descriptor queue 96
4444                          * Tx TC5 starts at: descriptor queue 104
4445                          * Tx TC6 starts at: descriptor queue 112
4446                          * Tx TC7 starts at: descriptor queue 120
4447                          *
4448                          * Rx TC0-TC7 are offset by 16 queues each
4449                          */
4450                         for (i = 0; i < 3; i++) {
4451                                 adapter->tx_ring[i]->reg_idx = i << 5;
4452                                 adapter->rx_ring[i]->reg_idx = i << 4;
4453                         }
4454                         for ( ; i < 5; i++) {
4455                                 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4456                                 adapter->rx_ring[i]->reg_idx = i << 4;
4457                         }
4458                         for ( ; i < dcb_i; i++) {
4459                                 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4460                                 adapter->rx_ring[i]->reg_idx = i << 4;
4461                         }
4462                         ret = true;
4463                 } else if (dcb_i == 4) {
4464                         /*
4465                          * Tx TC0 starts at: descriptor queue 0
4466                          * Tx TC1 starts at: descriptor queue 64
4467                          * Tx TC2 starts at: descriptor queue 96
4468                          * Tx TC3 starts at: descriptor queue 112
4469                          *
4470                          * Rx TC0-TC3 are offset by 32 queues each
4471                          */
4472                         adapter->tx_ring[0]->reg_idx = 0;
4473                         adapter->tx_ring[1]->reg_idx = 64;
4474                         adapter->tx_ring[2]->reg_idx = 96;
4475                         adapter->tx_ring[3]->reg_idx = 112;
4476                         for (i = 0 ; i < dcb_i; i++)
4477                                 adapter->rx_ring[i]->reg_idx = i << 5;
4478                         ret = true;
4479                 }
4480                 break;
4481         default:
4482                 break;
4483         }
4484         return ret;
4485 }
4486 #endif
4487
4488 /**
4489  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4490  * @adapter: board private structure to initialize
4491  *
4492  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4493  *
4494  **/
4495 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4496 {
4497         int i;
4498         bool ret = false;
4499
4500         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4501             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4502              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4503                 for (i = 0; i < adapter->num_rx_queues; i++)
4504                         adapter->rx_ring[i]->reg_idx = i;
4505                 for (i = 0; i < adapter->num_tx_queues; i++)
4506                         adapter->tx_ring[i]->reg_idx = i;
4507                 ret = true;
4508         }
4509
4510         return ret;
4511 }
4512
4513 #ifdef IXGBE_FCOE
4514 /**
4515  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4516  * @adapter: board private structure to initialize
4517  *
4518  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4519  *
4520  */
4521 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4522 {
4523         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4524         int i;
4525         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4526
4527         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4528                 return false;
4529
4530 #ifdef CONFIG_IXGBE_DCB
4531         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4532                 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4533
4534                 ixgbe_cache_ring_dcb(adapter);
4535                 /* find out queues in TC for FCoE */
4536                 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4537                 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4538                 /*
4539                  * In 82599, the number of Tx queues for each traffic
4540                  * class for both 8-TC and 4-TC modes are:
4541                  * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4542                  * 8 TCs:  32  32  16  16   8   8   8   8
4543                  * 4 TCs:  64  64  32  32
4544                  * We have max 8 queues for FCoE, where 8 the is
4545                  * FCoE redirection table size. If TC for FCoE is
4546                  * less than or equal to TC3, we have enough queues
4547                  * to add max of 8 queues for FCoE, so we start FCoE
4548                  * Tx queue from the next one, i.e., reg_idx + 1.
4549                  * If TC for FCoE is above TC3, implying 8 TC mode,
4550                  * and we need 8 for FCoE, we have to take all queues
4551                  * in that traffic class for FCoE.
4552                  */
4553                 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4554                         fcoe_tx_i--;
4555         }
4556 #endif /* CONFIG_IXGBE_DCB */
4557         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4558                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4559                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4560                         ixgbe_cache_ring_fdir(adapter);
4561                 else
4562                         ixgbe_cache_ring_rss(adapter);
4563
4564                 fcoe_rx_i = f->mask;
4565                 fcoe_tx_i = f->mask;
4566         }
4567         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4568                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4569                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4570         }
4571         return true;
4572 }
4573
4574 #endif /* IXGBE_FCOE */
4575 /**
4576  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4577  * @adapter: board private structure to initialize
4578  *
4579  * SR-IOV doesn't use any descriptor rings but changes the default if
4580  * no other mapping is used.
4581  *
4582  */
4583 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4584 {
4585         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4586         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4587         if (adapter->num_vfs)
4588                 return true;
4589         else
4590                 return false;
4591 }
4592
4593 /**
4594  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4595  * @adapter: board private structure to initialize
4596  *
4597  * Once we know the feature-set enabled for the device, we'll cache
4598  * the register offset the descriptor ring is assigned to.
4599  *
4600  * Note, the order the various feature calls is important.  It must start with
4601  * the "most" features enabled at the same time, then trickle down to the
4602  * least amount of features turned on at once.
4603  **/
4604 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4605 {
4606         /* start with default case */
4607         adapter->rx_ring[0]->reg_idx = 0;
4608         adapter->tx_ring[0]->reg_idx = 0;
4609
4610         if (ixgbe_cache_ring_sriov(adapter))
4611                 return;
4612
4613 #ifdef IXGBE_FCOE
4614         if (ixgbe_cache_ring_fcoe(adapter))
4615                 return;
4616
4617 #endif /* IXGBE_FCOE */
4618 #ifdef CONFIG_IXGBE_DCB
4619         if (ixgbe_cache_ring_dcb(adapter))
4620                 return;
4621
4622 #endif
4623         if (ixgbe_cache_ring_fdir(adapter))
4624                 return;
4625
4626         if (ixgbe_cache_ring_rss(adapter))
4627                 return;
4628 }
4629
4630 /**
4631  * ixgbe_alloc_queues - Allocate memory for all rings
4632  * @adapter: board private structure to initialize
4633  *
4634  * We allocate one ring per queue at run-time since we don't know the
4635  * number of queues at compile-time.  The polling_netdev array is
4636  * intended for Multiqueue, but should work fine with a single queue.
4637  **/
4638 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4639 {
4640         int i;
4641         int rx_count;
4642         int orig_node = adapter->node;
4643
4644         for (i = 0; i < adapter->num_tx_queues; i++) {
4645                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4646                 if (orig_node == -1) {
4647                         int cur_node = next_online_node(adapter->node);
4648                         if (cur_node == MAX_NUMNODES)
4649                                 cur_node = first_online_node;
4650                         adapter->node = cur_node;
4651                 }
4652                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4653                                     adapter->node);
4654                 if (!ring)
4655                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4656                 if (!ring)
4657                         goto err_tx_ring_allocation;
4658                 ring->count = adapter->tx_ring_count;
4659                 ring->queue_index = i;
4660                 ring->dev = &adapter->pdev->dev;
4661                 ring->netdev = adapter->netdev;
4662                 ring->numa_node = adapter->node;
4663
4664                 adapter->tx_ring[i] = ring;
4665         }
4666
4667         /* Restore the adapter's original node */
4668         adapter->node = orig_node;
4669
4670         rx_count = adapter->rx_ring_count;
4671         for (i = 0; i < adapter->num_rx_queues; i++) {
4672                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4673                 if (orig_node == -1) {
4674                         int cur_node = next_online_node(adapter->node);
4675                         if (cur_node == MAX_NUMNODES)
4676                                 cur_node = first_online_node;
4677                         adapter->node = cur_node;
4678                 }
4679                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4680                                     adapter->node);
4681                 if (!ring)
4682                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4683                 if (!ring)
4684                         goto err_rx_ring_allocation;
4685                 ring->count = rx_count;
4686                 ring->queue_index = i;
4687                 ring->dev = &adapter->pdev->dev;
4688                 ring->netdev = adapter->netdev;
4689                 ring->numa_node = adapter->node;
4690
4691                 adapter->rx_ring[i] = ring;
4692         }
4693
4694         /* Restore the adapter's original node */
4695         adapter->node = orig_node;
4696
4697         ixgbe_cache_ring_register(adapter);
4698
4699         return 0;
4700
4701 err_rx_ring_allocation:
4702         for (i = 0; i < adapter->num_tx_queues; i++)
4703                 kfree(adapter->tx_ring[i]);
4704 err_tx_ring_allocation:
4705         return -ENOMEM;
4706 }
4707
4708 /**
4709  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4710  * @adapter: board private structure to initialize
4711  *
4712  * Attempt to configure the interrupts using the best available
4713  * capabilities of the hardware and the kernel.
4714  **/
4715 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4716 {
4717         struct ixgbe_hw *hw = &adapter->hw;
4718         int err = 0;
4719         int vector, v_budget;
4720
4721         /*
4722          * It's easy to be greedy for MSI-X vectors, but it really
4723          * doesn't do us much good if we have a lot more vectors
4724          * than CPU's.  So let's be conservative and only ask for
4725          * (roughly) the same number of vectors as there are CPU's.
4726          */
4727         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4728                        (int)num_online_cpus()) + NON_Q_VECTORS;
4729
4730         /*
4731          * At the same time, hardware can only support a maximum of
4732          * hw.mac->max_msix_vectors vectors.  With features
4733          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4734          * descriptor queues supported by our device.  Thus, we cap it off in
4735          * those rare cases where the cpu count also exceeds our vector limit.
4736          */
4737         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4738
4739         /* A failure in MSI-X entry allocation isn't fatal, but it does
4740          * mean we disable MSI-X capabilities of the adapter. */
4741         adapter->msix_entries = kcalloc(v_budget,
4742                                         sizeof(struct msix_entry), GFP_KERNEL);
4743         if (adapter->msix_entries) {
4744                 for (vector = 0; vector < v_budget; vector++)
4745                         adapter->msix_entries[vector].entry = vector;
4746
4747                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4748
4749                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4750                         goto out;
4751         }
4752
4753         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4754         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4755         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4756         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4757         adapter->atr_sample_rate = 0;
4758         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4759                 ixgbe_disable_sriov(adapter);
4760
4761         err = ixgbe_set_num_queues(adapter);
4762         if (err)
4763                 return err;
4764
4765         err = pci_enable_msi(adapter->pdev);
4766         if (!err) {
4767                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4768         } else {
4769                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4770                              "Unable to allocate MSI interrupt, "
4771                              "falling back to legacy.  Error: %d\n", err);
4772                 /* reset err */
4773                 err = 0;
4774         }
4775
4776 out:
4777         return err;
4778 }
4779
4780 /**
4781  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4782  * @adapter: board private structure to initialize
4783  *
4784  * We allocate one q_vector per queue interrupt.  If allocation fails we
4785  * return -ENOMEM.
4786  **/
4787 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4788 {
4789         int q_idx, num_q_vectors;
4790         struct ixgbe_q_vector *q_vector;
4791         int napi_vectors;
4792         int (*poll)(struct napi_struct *, int);
4793
4794         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4795                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4796                 napi_vectors = adapter->num_rx_queues;
4797                 poll = &ixgbe_clean_rxtx_many;
4798         } else {
4799                 num_q_vectors = 1;
4800                 napi_vectors = 1;
4801                 poll = &ixgbe_poll;
4802         }
4803
4804         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4805                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4806                                         GFP_KERNEL, adapter->node);
4807                 if (!q_vector)
4808                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4809                                            GFP_KERNEL);
4810                 if (!q_vector)
4811                         goto err_out;
4812                 q_vector->adapter = adapter;
4813                 if (q_vector->txr_count && !q_vector->rxr_count)
4814                         q_vector->eitr = adapter->tx_eitr_param;
4815                 else
4816                         q_vector->eitr = adapter->rx_eitr_param;
4817                 q_vector->v_idx = q_idx;
4818                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4819                 adapter->q_vector[q_idx] = q_vector;
4820         }
4821
4822         return 0;
4823
4824 err_out:
4825         while (q_idx) {
4826                 q_idx--;
4827                 q_vector = adapter->q_vector[q_idx];
4828                 netif_napi_del(&q_vector->napi);
4829                 kfree(q_vector);
4830                 adapter->q_vector[q_idx] = NULL;
4831         }
4832         return -ENOMEM;
4833 }
4834
4835 /**
4836  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4837  * @adapter: board private structure to initialize
4838  *
4839  * This function frees the memory allocated to the q_vectors.  In addition if
4840  * NAPI is enabled it will delete any references to the NAPI struct prior
4841  * to freeing the q_vector.
4842  **/
4843 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4844 {
4845         int q_idx, num_q_vectors;
4846
4847         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4848                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4849         else
4850                 num_q_vectors = 1;
4851
4852         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4853                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4854                 adapter->q_vector[q_idx] = NULL;
4855                 netif_napi_del(&q_vector->napi);
4856                 kfree(q_vector);
4857         }
4858 }
4859
4860 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4861 {
4862         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4863                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4864                 pci_disable_msix(adapter->pdev);
4865                 kfree(adapter->msix_entries);
4866                 adapter->msix_entries = NULL;
4867         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4868                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4869                 pci_disable_msi(adapter->pdev);
4870         }
4871 }
4872
4873 /**
4874  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4875  * @adapter: board private structure to initialize
4876  *
4877  * We determine which interrupt scheme to use based on...
4878  * - Kernel support (MSI, MSI-X)
4879  *   - which can be user-defined (via MODULE_PARAM)
4880  * - Hardware queue count (num_*_queues)
4881  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4882  **/
4883 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4884 {
4885         int err;
4886
4887         /* Number of supported queues */
4888         err = ixgbe_set_num_queues(adapter);
4889         if (err)
4890                 return err;
4891
4892         err = ixgbe_set_interrupt_capability(adapter);
4893         if (err) {
4894                 e_dev_err("Unable to setup interrupt capabilities\n");
4895                 goto err_set_interrupt;
4896         }
4897
4898         err = ixgbe_alloc_q_vectors(adapter);
4899         if (err) {
4900                 e_dev_err("Unable to allocate memory for queue vectors\n");
4901                 goto err_alloc_q_vectors;
4902         }
4903
4904         err = ixgbe_alloc_queues(adapter);
4905         if (err) {
4906                 e_dev_err("Unable to allocate memory for queues\n");
4907                 goto err_alloc_queues;
4908         }
4909
4910         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4911                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4912                    adapter->num_rx_queues, adapter->num_tx_queues);
4913
4914         set_bit(__IXGBE_DOWN, &adapter->state);
4915
4916         return 0;
4917
4918 err_alloc_queues:
4919         ixgbe_free_q_vectors(adapter);
4920 err_alloc_q_vectors:
4921         ixgbe_reset_interrupt_capability(adapter);
4922 err_set_interrupt:
4923         return err;
4924 }
4925
4926 static void ring_free_rcu(struct rcu_head *head)
4927 {
4928         kfree(container_of(head, struct ixgbe_ring, rcu));
4929 }
4930
4931 /**
4932  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4933  * @adapter: board private structure to clear interrupt scheme on
4934  *
4935  * We go through and clear interrupt specific resources and reset the structure
4936  * to pre-load conditions
4937  **/
4938 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4939 {
4940         int i;
4941
4942         for (i = 0; i < adapter->num_tx_queues; i++) {
4943                 kfree(adapter->tx_ring[i]);
4944                 adapter->tx_ring[i] = NULL;
4945         }
4946         for (i = 0; i < adapter->num_rx_queues; i++) {
4947                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4948
4949                 /* ixgbe_get_stats64() might access this ring, we must wait
4950                  * a grace period before freeing it.
4951                  */
4952                 call_rcu(&ring->rcu, ring_free_rcu);
4953                 adapter->rx_ring[i] = NULL;
4954         }
4955
4956         ixgbe_free_q_vectors(adapter);
4957         ixgbe_reset_interrupt_capability(adapter);
4958 }
4959
4960 /**
4961  * ixgbe_sfp_timer - worker thread to find a missing module
4962  * @data: pointer to our adapter struct
4963  **/
4964 static void ixgbe_sfp_timer(unsigned long data)
4965 {
4966         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4967
4968         /*
4969          * Do the sfp_timer outside of interrupt context due to the
4970          * delays that sfp+ detection requires
4971          */
4972         schedule_work(&adapter->sfp_task);
4973 }
4974
4975 /**
4976  * ixgbe_sfp_task - worker thread to find a missing module
4977  * @work: pointer to work_struct containing our data
4978  **/
4979 static void ixgbe_sfp_task(struct work_struct *work)
4980 {
4981         struct ixgbe_adapter *adapter = container_of(work,
4982                                                      struct ixgbe_adapter,
4983                                                      sfp_task);
4984         struct ixgbe_hw *hw = &adapter->hw;
4985
4986         if ((hw->phy.type == ixgbe_phy_nl) &&
4987             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4988                 s32 ret = hw->phy.ops.identify_sfp(hw);
4989                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4990                         goto reschedule;
4991                 ret = hw->phy.ops.reset(hw);
4992                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4993                         e_dev_err("failed to initialize because an unsupported "
4994                                   "SFP+ module type was detected.\n");
4995                         e_dev_err("Reload the driver after installing a "
4996                                   "supported module.\n");
4997                         unregister_netdev(adapter->netdev);
4998                 } else {
4999                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5000                 }
5001                 /* don't need this routine any more */
5002                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5003         }
5004         return;
5005 reschedule:
5006         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
5007                 mod_timer(&adapter->sfp_timer,
5008                           round_jiffies(jiffies + (2 * HZ)));
5009 }
5010
5011 /**
5012  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5013  * @adapter: board private structure to initialize
5014  *
5015  * ixgbe_sw_init initializes the Adapter private data structure.
5016  * Fields are initialized based on PCI device information and
5017  * OS network device settings (MTU size).
5018  **/
5019 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5020 {
5021         struct ixgbe_hw *hw = &adapter->hw;
5022         struct pci_dev *pdev = adapter->pdev;
5023         struct net_device *dev = adapter->netdev;
5024         unsigned int rss;
5025 #ifdef CONFIG_IXGBE_DCB
5026         int j;
5027         struct tc_configuration *tc;
5028 #endif
5029         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5030
5031         /* PCI config space info */
5032
5033         hw->vendor_id = pdev->vendor;
5034         hw->device_id = pdev->device;
5035         hw->revision_id = pdev->revision;
5036         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5037         hw->subsystem_device_id = pdev->subsystem_device;
5038
5039         /* Set capability flags */
5040         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5041         adapter->ring_feature[RING_F_RSS].indices = rss;
5042         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5043         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5044         switch (hw->mac.type) {
5045         case ixgbe_mac_82598EB:
5046                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5047                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5048                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5049                 break;
5050         case ixgbe_mac_82599EB:
5051                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5052                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5053                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5054                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5055                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5056                 if (dev->features & NETIF_F_NTUPLE) {
5057                         /* Flow Director perfect filter enabled */
5058                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
5059                         adapter->atr_sample_rate = 0;
5060                         spin_lock_init(&adapter->fdir_perfect_lock);
5061                 } else {
5062                         /* Flow Director hash filters enabled */
5063                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5064                         adapter->atr_sample_rate = 20;
5065                 }
5066                 adapter->ring_feature[RING_F_FDIR].indices =
5067                                                          IXGBE_MAX_FDIR_INDICES;
5068                 adapter->fdir_pballoc = 0;
5069 #ifdef IXGBE_FCOE
5070                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5071                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5072                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5073 #ifdef CONFIG_IXGBE_DCB
5074                 /* Default traffic class to use for FCoE */
5075                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5076                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5077 #endif
5078 #endif /* IXGBE_FCOE */
5079                 break;
5080         default:
5081                 break;
5082         }
5083
5084 #ifdef CONFIG_IXGBE_DCB
5085         /* Configure DCB traffic classes */
5086         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5087                 tc = &adapter->dcb_cfg.tc_config[j];
5088                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5089                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5090                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5091                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5092                 tc->dcb_pfc = pfc_disabled;
5093         }
5094         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5095         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5096         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5097         adapter->dcb_cfg.pfc_mode_enable = false;
5098         adapter->dcb_cfg.round_robin_enable = false;
5099         adapter->dcb_set_bitmap = 0x00;
5100         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5101                            adapter->ring_feature[RING_F_DCB].indices);
5102
5103 #endif
5104
5105         /* default flow control settings */
5106         hw->fc.requested_mode = ixgbe_fc_full;
5107         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5108 #ifdef CONFIG_DCB
5109         adapter->last_lfc_mode = hw->fc.current_mode;
5110 #endif
5111         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5112         hw->fc.low_water = FC_LOW_WATER(max_frame);
5113         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5114         hw->fc.send_xon = true;
5115         hw->fc.disable_fc_autoneg = false;
5116
5117         /* enable itr by default in dynamic mode */
5118         adapter->rx_itr_setting = 1;
5119         adapter->rx_eitr_param = 20000;
5120         adapter->tx_itr_setting = 1;
5121         adapter->tx_eitr_param = 10000;
5122
5123         /* set defaults for eitr in MegaBytes */
5124         adapter->eitr_low = 10;
5125         adapter->eitr_high = 20;
5126
5127         /* set default ring sizes */
5128         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5129         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5130
5131         /* initialize eeprom parameters */
5132         if (ixgbe_init_eeprom_params_generic(hw)) {
5133                 e_dev_err("EEPROM initialization failed\n");
5134                 return -EIO;
5135         }
5136
5137         /* enable rx csum by default */
5138         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5139
5140         /* get assigned NUMA node */
5141         adapter->node = dev_to_node(&pdev->dev);
5142
5143         set_bit(__IXGBE_DOWN, &adapter->state);
5144
5145         return 0;
5146 }
5147
5148 /**
5149  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5150  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5151  *
5152  * Return 0 on success, negative on failure
5153  **/
5154 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5155 {
5156         struct device *dev = tx_ring->dev;
5157         int size;
5158
5159         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5160         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
5161         if (!tx_ring->tx_buffer_info)
5162                 tx_ring->tx_buffer_info = vmalloc(size);
5163         if (!tx_ring->tx_buffer_info)
5164                 goto err;
5165         memset(tx_ring->tx_buffer_info, 0, size);
5166
5167         /* round up to nearest 4K */
5168         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5169         tx_ring->size = ALIGN(tx_ring->size, 4096);
5170
5171         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5172                                            &tx_ring->dma, GFP_KERNEL);
5173         if (!tx_ring->desc)
5174                 goto err;
5175
5176         tx_ring->next_to_use = 0;
5177         tx_ring->next_to_clean = 0;
5178         tx_ring->work_limit = tx_ring->count;
5179         return 0;
5180
5181 err:
5182         vfree(tx_ring->tx_buffer_info);
5183         tx_ring->tx_buffer_info = NULL;
5184         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5185         return -ENOMEM;
5186 }
5187
5188 /**
5189  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5190  * @adapter: board private structure
5191  *
5192  * If this function returns with an error, then it's possible one or
5193  * more of the rings is populated (while the rest are not).  It is the
5194  * callers duty to clean those orphaned rings.
5195  *
5196  * Return 0 on success, negative on failure
5197  **/
5198 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5199 {
5200         int i, err = 0;
5201
5202         for (i = 0; i < adapter->num_tx_queues; i++) {
5203                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5204                 if (!err)
5205                         continue;
5206                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5207                 break;
5208         }
5209
5210         return err;
5211 }
5212
5213 /**
5214  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5215  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5216  *
5217  * Returns 0 on success, negative on failure
5218  **/
5219 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5220 {
5221         struct device *dev = rx_ring->dev;
5222         int size;
5223
5224         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5225         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5226         if (!rx_ring->rx_buffer_info)
5227                 rx_ring->rx_buffer_info = vmalloc(size);
5228         if (!rx_ring->rx_buffer_info)
5229                 goto err;
5230         memset(rx_ring->rx_buffer_info, 0, size);
5231
5232         /* Round up to nearest 4K */
5233         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5234         rx_ring->size = ALIGN(rx_ring->size, 4096);
5235
5236         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5237                                            &rx_ring->dma, GFP_KERNEL);
5238
5239         if (!rx_ring->desc)
5240                 goto err;
5241
5242         rx_ring->next_to_clean = 0;
5243         rx_ring->next_to_use = 0;
5244
5245         return 0;
5246 err:
5247         vfree(rx_ring->rx_buffer_info);
5248         rx_ring->rx_buffer_info = NULL;
5249         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5250         return -ENOMEM;
5251 }
5252
5253 /**
5254  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5255  * @adapter: board private structure
5256  *
5257  * If this function returns with an error, then it's possible one or
5258  * more of the rings is populated (while the rest are not).  It is the
5259  * callers duty to clean those orphaned rings.
5260  *
5261  * Return 0 on success, negative on failure
5262  **/
5263 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5264 {
5265         int i, err = 0;
5266
5267         for (i = 0; i < adapter->num_rx_queues; i++) {
5268                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5269                 if (!err)
5270                         continue;
5271                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5272                 break;
5273         }
5274
5275         return err;
5276 }
5277
5278 /**
5279  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5280  * @tx_ring: Tx descriptor ring for a specific queue
5281  *
5282  * Free all transmit software resources
5283  **/
5284 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5285 {
5286         ixgbe_clean_tx_ring(tx_ring);
5287
5288         vfree(tx_ring->tx_buffer_info);
5289         tx_ring->tx_buffer_info = NULL;
5290
5291         /* if not set, then don't free */
5292         if (!tx_ring->desc)
5293                 return;
5294
5295         dma_free_coherent(tx_ring->dev, tx_ring->size,
5296                           tx_ring->desc, tx_ring->dma);
5297
5298         tx_ring->desc = NULL;
5299 }
5300
5301 /**
5302  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5303  * @adapter: board private structure
5304  *
5305  * Free all transmit software resources
5306  **/
5307 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5308 {
5309         int i;
5310
5311         for (i = 0; i < adapter->num_tx_queues; i++)
5312                 if (adapter->tx_ring[i]->desc)
5313                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5314 }
5315
5316 /**
5317  * ixgbe_free_rx_resources - Free Rx Resources
5318  * @rx_ring: ring to clean the resources from
5319  *
5320  * Free all receive software resources
5321  **/
5322 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5323 {
5324         ixgbe_clean_rx_ring(rx_ring);
5325
5326         vfree(rx_ring->rx_buffer_info);
5327         rx_ring->rx_buffer_info = NULL;
5328
5329         /* if not set, then don't free */
5330         if (!rx_ring->desc)
5331                 return;
5332
5333         dma_free_coherent(rx_ring->dev, rx_ring->size,
5334                           rx_ring->desc, rx_ring->dma);
5335
5336         rx_ring->desc = NULL;
5337 }
5338
5339 /**
5340  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5341  * @adapter: board private structure
5342  *
5343  * Free all receive software resources
5344  **/
5345 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5346 {
5347         int i;
5348
5349         for (i = 0; i < adapter->num_rx_queues; i++)
5350                 if (adapter->rx_ring[i]->desc)
5351                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5352 }
5353
5354 /**
5355  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5356  * @netdev: network interface device structure
5357  * @new_mtu: new value for maximum frame size
5358  *
5359  * Returns 0 on success, negative on failure
5360  **/
5361 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5362 {
5363         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5364         struct ixgbe_hw *hw = &adapter->hw;
5365         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5366
5367         /* MTU < 68 is an error and causes problems on some kernels */
5368         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5369                 return -EINVAL;
5370
5371         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5372         /* must set new MTU before calling down or up */
5373         netdev->mtu = new_mtu;
5374
5375         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5376         hw->fc.low_water = FC_LOW_WATER(max_frame);
5377
5378         if (netif_running(netdev))
5379                 ixgbe_reinit_locked(adapter);
5380
5381         return 0;
5382 }
5383
5384 /**
5385  * ixgbe_open - Called when a network interface is made active
5386  * @netdev: network interface device structure
5387  *
5388  * Returns 0 on success, negative value on failure
5389  *
5390  * The open entry point is called when a network interface is made
5391  * active by the system (IFF_UP).  At this point all resources needed
5392  * for transmit and receive operations are allocated, the interrupt
5393  * handler is registered with the OS, the watchdog timer is started,
5394  * and the stack is notified that the interface is ready.
5395  **/
5396 static int ixgbe_open(struct net_device *netdev)
5397 {
5398         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5399         int err;
5400
5401         /* disallow open during test */
5402         if (test_bit(__IXGBE_TESTING, &adapter->state))
5403                 return -EBUSY;
5404
5405         netif_carrier_off(netdev);
5406
5407         /* allocate transmit descriptors */
5408         err = ixgbe_setup_all_tx_resources(adapter);
5409         if (err)
5410                 goto err_setup_tx;
5411
5412         /* allocate receive descriptors */
5413         err = ixgbe_setup_all_rx_resources(adapter);
5414         if (err)
5415                 goto err_setup_rx;
5416
5417         ixgbe_configure(adapter);
5418
5419         err = ixgbe_request_irq(adapter);
5420         if (err)
5421                 goto err_req_irq;
5422
5423         err = ixgbe_up_complete(adapter);
5424         if (err)
5425                 goto err_up;
5426
5427         netif_tx_start_all_queues(netdev);
5428
5429         return 0;
5430
5431 err_up:
5432         ixgbe_release_hw_control(adapter);
5433         ixgbe_free_irq(adapter);
5434 err_req_irq:
5435 err_setup_rx:
5436         ixgbe_free_all_rx_resources(adapter);
5437 err_setup_tx:
5438         ixgbe_free_all_tx_resources(adapter);
5439         ixgbe_reset(adapter);
5440
5441         return err;
5442 }
5443
5444 /**
5445  * ixgbe_close - Disables a network interface
5446  * @netdev: network interface device structure
5447  *
5448  * Returns 0, this is not allowed to fail
5449  *
5450  * The close entry point is called when an interface is de-activated
5451  * by the OS.  The hardware is still under the drivers control, but
5452  * needs to be disabled.  A global MAC reset is issued to stop the
5453  * hardware, and all transmit and receive resources are freed.
5454  **/
5455 static int ixgbe_close(struct net_device *netdev)
5456 {
5457         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5458
5459         ixgbe_down(adapter);
5460         ixgbe_free_irq(adapter);
5461
5462         ixgbe_free_all_tx_resources(adapter);
5463         ixgbe_free_all_rx_resources(adapter);
5464
5465         ixgbe_release_hw_control(adapter);
5466
5467         return 0;
5468 }
5469
5470 #ifdef CONFIG_PM
5471 static int ixgbe_resume(struct pci_dev *pdev)
5472 {
5473         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5474         struct net_device *netdev = adapter->netdev;
5475         u32 err;
5476
5477         pci_set_power_state(pdev, PCI_D0);
5478         pci_restore_state(pdev);
5479         /*
5480          * pci_restore_state clears dev->state_saved so call
5481          * pci_save_state to restore it.
5482          */
5483         pci_save_state(pdev);
5484
5485         err = pci_enable_device_mem(pdev);
5486         if (err) {
5487                 e_dev_err("Cannot enable PCI device from suspend\n");
5488                 return err;
5489         }
5490         pci_set_master(pdev);
5491
5492         pci_wake_from_d3(pdev, false);
5493
5494         err = ixgbe_init_interrupt_scheme(adapter);
5495         if (err) {
5496                 e_dev_err("Cannot initialize interrupts for device\n");
5497                 return err;
5498         }
5499
5500         ixgbe_reset(adapter);
5501
5502         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5503
5504         if (netif_running(netdev)) {
5505                 err = ixgbe_open(netdev);
5506                 if (err)
5507                         return err;
5508         }
5509
5510         netif_device_attach(netdev);
5511
5512         return 0;
5513 }
5514 #endif /* CONFIG_PM */
5515
5516 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5517 {
5518         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5519         struct net_device *netdev = adapter->netdev;
5520         struct ixgbe_hw *hw = &adapter->hw;
5521         u32 ctrl, fctrl;
5522         u32 wufc = adapter->wol;
5523 #ifdef CONFIG_PM
5524         int retval = 0;
5525 #endif
5526
5527         netif_device_detach(netdev);
5528
5529         if (netif_running(netdev)) {
5530                 ixgbe_down(adapter);
5531                 ixgbe_free_irq(adapter);
5532                 ixgbe_free_all_tx_resources(adapter);
5533                 ixgbe_free_all_rx_resources(adapter);
5534         }
5535
5536         ixgbe_clear_interrupt_scheme(adapter);
5537
5538 #ifdef CONFIG_PM
5539         retval = pci_save_state(pdev);
5540         if (retval)
5541                 return retval;
5542
5543 #endif
5544         if (wufc) {
5545                 ixgbe_set_rx_mode(netdev);
5546
5547                 /* turn on all-multi mode if wake on multicast is enabled */
5548                 if (wufc & IXGBE_WUFC_MC) {
5549                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5550                         fctrl |= IXGBE_FCTRL_MPE;
5551                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5552                 }
5553
5554                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5555                 ctrl |= IXGBE_CTRL_GIO_DIS;
5556                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5557
5558                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5559         } else {
5560                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5561                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5562         }
5563
5564         switch (hw->mac.type) {
5565         case ixgbe_mac_82598EB:
5566                 pci_wake_from_d3(pdev, false);
5567                 break;
5568         case ixgbe_mac_82599EB:
5569                 pci_wake_from_d3(pdev, !!wufc);
5570                 break;
5571         default:
5572                 break;
5573         }
5574
5575         *enable_wake = !!wufc;
5576
5577         ixgbe_release_hw_control(adapter);
5578
5579         pci_disable_device(pdev);
5580
5581         return 0;
5582 }
5583
5584 #ifdef CONFIG_PM
5585 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5586 {
5587         int retval;
5588         bool wake;
5589
5590         retval = __ixgbe_shutdown(pdev, &wake);
5591         if (retval)
5592                 return retval;
5593
5594         if (wake) {
5595                 pci_prepare_to_sleep(pdev);
5596         } else {
5597                 pci_wake_from_d3(pdev, false);
5598                 pci_set_power_state(pdev, PCI_D3hot);
5599         }
5600
5601         return 0;
5602 }
5603 #endif /* CONFIG_PM */
5604
5605 static void ixgbe_shutdown(struct pci_dev *pdev)
5606 {
5607         bool wake;
5608
5609         __ixgbe_shutdown(pdev, &wake);
5610
5611         if (system_state == SYSTEM_POWER_OFF) {
5612                 pci_wake_from_d3(pdev, wake);
5613                 pci_set_power_state(pdev, PCI_D3hot);
5614         }
5615 }
5616
5617 /**
5618  * ixgbe_update_stats - Update the board statistics counters.
5619  * @adapter: board private structure
5620  **/
5621 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5622 {
5623         struct net_device *netdev = adapter->netdev;
5624         struct ixgbe_hw *hw = &adapter->hw;
5625         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5626         u64 total_mpc = 0;
5627         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5628         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5629         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5630         u64 bytes = 0, packets = 0;
5631
5632         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5633             test_bit(__IXGBE_RESETTING, &adapter->state))
5634                 return;
5635
5636         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5637                 u64 rsc_count = 0;
5638                 u64 rsc_flush = 0;
5639                 for (i = 0; i < 16; i++)
5640                         adapter->hw_rx_no_dma_resources +=
5641                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5642                 for (i = 0; i < adapter->num_rx_queues; i++) {
5643                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5644                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5645                 }
5646                 adapter->rsc_total_count = rsc_count;
5647                 adapter->rsc_total_flush = rsc_flush;
5648         }
5649
5650         for (i = 0; i < adapter->num_rx_queues; i++) {
5651                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5652                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5653                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5654                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5655                 bytes += rx_ring->stats.bytes;
5656                 packets += rx_ring->stats.packets;
5657         }
5658         adapter->non_eop_descs = non_eop_descs;
5659         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5660         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5661         netdev->stats.rx_bytes = bytes;
5662         netdev->stats.rx_packets = packets;
5663
5664         bytes = 0;
5665         packets = 0;
5666         /* gather some stats to the adapter struct that are per queue */
5667         for (i = 0; i < adapter->num_tx_queues; i++) {
5668                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5669                 restart_queue += tx_ring->tx_stats.restart_queue;
5670                 tx_busy += tx_ring->tx_stats.tx_busy;
5671                 bytes += tx_ring->stats.bytes;
5672                 packets += tx_ring->stats.packets;
5673         }
5674         adapter->restart_queue = restart_queue;
5675         adapter->tx_busy = tx_busy;
5676         netdev->stats.tx_bytes = bytes;
5677         netdev->stats.tx_packets = packets;
5678
5679         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5680         for (i = 0; i < 8; i++) {
5681                 /* for packet buffers not used, the register should read 0 */
5682                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5683                 missed_rx += mpc;
5684                 hwstats->mpc[i] += mpc;
5685                 total_mpc += hwstats->mpc[i];
5686                 if (hw->mac.type == ixgbe_mac_82598EB)
5687                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5688                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5689                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5690                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5691                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5692                 switch (hw->mac.type) {
5693                 case ixgbe_mac_82598EB:
5694                         hwstats->pxonrxc[i] +=
5695                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5696                         break;
5697                 case ixgbe_mac_82599EB:
5698                         hwstats->pxonrxc[i] +=
5699                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5700                         break;
5701                 default:
5702                         break;
5703                 }
5704                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5705                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5706         }
5707         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5708         /* work around hardware counting issue */
5709         hwstats->gprc -= missed_rx;
5710
5711         ixgbe_update_xoff_received(adapter);
5712
5713         /* 82598 hardware only has a 32 bit counter in the high register */
5714         switch (hw->mac.type) {
5715         case ixgbe_mac_82598EB:
5716                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5717                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5718                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5719                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5720                 break;
5721         case ixgbe_mac_82599EB:
5722                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5723                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5724                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5725                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5726                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5727                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5728                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5729                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5730                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5731 #ifdef IXGBE_FCOE
5732                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5733                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5734                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5735                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5736                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5737                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5738 #endif /* IXGBE_FCOE */
5739                 break;
5740         default:
5741                 break;
5742         }
5743         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5744         hwstats->bprc += bprc;
5745         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5746         if (hw->mac.type == ixgbe_mac_82598EB)
5747                 hwstats->mprc -= bprc;
5748         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5749         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5750         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5751         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5752         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5753         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5754         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5755         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5756         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5757         hwstats->lxontxc += lxon;
5758         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5759         hwstats->lxofftxc += lxoff;
5760         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5761         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5762         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5763         /*
5764          * 82598 errata - tx of flow control packets is included in tx counters
5765          */
5766         xon_off_tot = lxon + lxoff;
5767         hwstats->gptc -= xon_off_tot;
5768         hwstats->mptc -= xon_off_tot;
5769         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5770         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5771         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5772         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5773         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5774         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5775         hwstats->ptc64 -= xon_off_tot;
5776         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5777         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5778         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5779         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5780         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5781         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5782
5783         /* Fill out the OS statistics structure */
5784         netdev->stats.multicast = hwstats->mprc;
5785
5786         /* Rx Errors */
5787         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5788         netdev->stats.rx_dropped = 0;
5789         netdev->stats.rx_length_errors = hwstats->rlec;
5790         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5791         netdev->stats.rx_missed_errors = total_mpc;
5792 }
5793
5794 /**
5795  * ixgbe_watchdog - Timer Call-back
5796  * @data: pointer to adapter cast into an unsigned long
5797  **/
5798 static void ixgbe_watchdog(unsigned long data)
5799 {
5800         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5801         struct ixgbe_hw *hw = &adapter->hw;
5802         u64 eics = 0;
5803         int i;
5804
5805         /*
5806          *  Do the watchdog outside of interrupt context due to the lovely
5807          * delays that some of the newer hardware requires
5808          */
5809
5810         if (test_bit(__IXGBE_DOWN, &adapter->state))
5811                 goto watchdog_short_circuit;
5812
5813         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5814                 /*
5815                  * for legacy and MSI interrupts don't set any bits
5816                  * that are enabled for EIAM, because this operation
5817                  * would set *both* EIMS and EICS for any bit in EIAM
5818                  */
5819                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5820                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5821                 goto watchdog_reschedule;
5822         }
5823
5824         /* get one bit for every active tx/rx interrupt vector */
5825         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5826                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5827                 if (qv->rxr_count || qv->txr_count)
5828                         eics |= ((u64)1 << i);
5829         }
5830
5831         /* Cause software interrupt to ensure rx rings are cleaned */
5832         ixgbe_irq_rearm_queues(adapter, eics);
5833
5834 watchdog_reschedule:
5835         /* Reset the timer */
5836         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5837
5838 watchdog_short_circuit:
5839         schedule_work(&adapter->watchdog_task);
5840 }
5841
5842 /**
5843  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5844  * @work: pointer to work_struct containing our data
5845  **/
5846 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5847 {
5848         struct ixgbe_adapter *adapter = container_of(work,
5849                                                      struct ixgbe_adapter,
5850                                                      multispeed_fiber_task);
5851         struct ixgbe_hw *hw = &adapter->hw;
5852         u32 autoneg;
5853         bool negotiation;
5854
5855         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5856         autoneg = hw->phy.autoneg_advertised;
5857         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5858                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5859         hw->mac.autotry_restart = false;
5860         if (hw->mac.ops.setup_link)
5861                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5862         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5863         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5864 }
5865
5866 /**
5867  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5868  * @work: pointer to work_struct containing our data
5869  **/
5870 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5871 {
5872         struct ixgbe_adapter *adapter = container_of(work,
5873                                                      struct ixgbe_adapter,
5874                                                      sfp_config_module_task);
5875         struct ixgbe_hw *hw = &adapter->hw;
5876         u32 err;
5877
5878         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5879
5880         /* Time for electrical oscillations to settle down */
5881         msleep(100);
5882         err = hw->phy.ops.identify_sfp(hw);
5883
5884         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5885                 e_dev_err("failed to initialize because an unsupported SFP+ "
5886                           "module type was detected.\n");
5887                 e_dev_err("Reload the driver after installing a supported "
5888                           "module.\n");
5889                 unregister_netdev(adapter->netdev);
5890                 return;
5891         }
5892         hw->mac.ops.setup_sfp(hw);
5893
5894         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5895                 /* This will also work for DA Twinax connections */
5896                 schedule_work(&adapter->multispeed_fiber_task);
5897         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5898 }
5899
5900 /**
5901  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5902  * @work: pointer to work_struct containing our data
5903  **/
5904 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5905 {
5906         struct ixgbe_adapter *adapter = container_of(work,
5907                                                      struct ixgbe_adapter,
5908                                                      fdir_reinit_task);
5909         struct ixgbe_hw *hw = &adapter->hw;
5910         int i;
5911
5912         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5913                 for (i = 0; i < adapter->num_tx_queues; i++)
5914                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5915                                 &(adapter->tx_ring[i]->state));
5916         } else {
5917                 e_err(probe, "failed to finish FDIR re-initialization, "
5918                       "ignored adding FDIR ATR filters\n");
5919         }
5920         /* Done FDIR Re-initialization, enable transmits */
5921         netif_tx_start_all_queues(adapter->netdev);
5922 }
5923
5924 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5925
5926 /**
5927  * ixgbe_watchdog_task - worker thread to bring link up
5928  * @work: pointer to work_struct containing our data
5929  **/
5930 static void ixgbe_watchdog_task(struct work_struct *work)
5931 {
5932         struct ixgbe_adapter *adapter = container_of(work,
5933                                                      struct ixgbe_adapter,
5934                                                      watchdog_task);
5935         struct net_device *netdev = adapter->netdev;
5936         struct ixgbe_hw *hw = &adapter->hw;
5937         u32 link_speed;
5938         bool link_up;
5939         int i;
5940         struct ixgbe_ring *tx_ring;
5941         int some_tx_pending = 0;
5942
5943         mutex_lock(&ixgbe_watchdog_lock);
5944
5945         link_up = adapter->link_up;
5946         link_speed = adapter->link_speed;
5947
5948         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5949                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5950                 if (link_up) {
5951 #ifdef CONFIG_DCB
5952                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5953                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5954                                         hw->mac.ops.fc_enable(hw, i);
5955                         } else {
5956                                 hw->mac.ops.fc_enable(hw, 0);
5957                         }
5958 #else
5959                         hw->mac.ops.fc_enable(hw, 0);
5960 #endif
5961                 }
5962
5963                 if (link_up ||
5964                     time_after(jiffies, (adapter->link_check_timeout +
5965                                          IXGBE_TRY_LINK_TIMEOUT))) {
5966                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5967                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5968                 }
5969                 adapter->link_up = link_up;
5970                 adapter->link_speed = link_speed;
5971         }
5972
5973         if (link_up) {
5974                 if (!netif_carrier_ok(netdev)) {
5975                         bool flow_rx, flow_tx;
5976
5977                         switch (hw->mac.type) {
5978                         case ixgbe_mac_82598EB: {
5979                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5980                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5981                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5982                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5983                         }
5984                                 break;
5985                         case ixgbe_mac_82599EB: {
5986                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5987                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5988                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5989                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5990                         }
5991                                 break;
5992                         default:
5993                                 flow_tx = false;
5994                                 flow_rx = false;
5995                                 break;
5996                         }
5997
5998                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5999                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6000                                "10 Gbps" :
6001                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6002                                "1 Gbps" : "unknown speed")),
6003                                ((flow_rx && flow_tx) ? "RX/TX" :
6004                                (flow_rx ? "RX" :
6005                                (flow_tx ? "TX" : "None"))));
6006
6007                         netif_carrier_on(netdev);
6008                 } else {
6009                         /* Force detection of hung controller */
6010                         for (i = 0; i < adapter->num_tx_queues; i++) {
6011                                 tx_ring = adapter->tx_ring[i];
6012                                 set_check_for_tx_hang(tx_ring);
6013                         }
6014                 }
6015         } else {
6016                 adapter->link_up = false;
6017                 adapter->link_speed = 0;
6018                 if (netif_carrier_ok(netdev)) {
6019                         e_info(drv, "NIC Link is Down\n");
6020                         netif_carrier_off(netdev);
6021                 }
6022         }
6023
6024         if (!netif_carrier_ok(netdev)) {
6025                 for (i = 0; i < adapter->num_tx_queues; i++) {
6026                         tx_ring = adapter->tx_ring[i];
6027                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6028                                 some_tx_pending = 1;
6029                                 break;
6030                         }
6031                 }
6032
6033                 if (some_tx_pending) {
6034                         /* We've lost link, so the controller stops DMA,
6035                          * but we've got queued Tx work that's never going
6036                          * to get done, so reset controller to flush Tx.
6037                          * (Do the reset outside of interrupt context).
6038                          */
6039                          schedule_work(&adapter->reset_task);
6040                 }
6041         }
6042
6043         ixgbe_update_stats(adapter);
6044         mutex_unlock(&ixgbe_watchdog_lock);
6045 }
6046
6047 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6048                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6049                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6050 {
6051         struct ixgbe_adv_tx_context_desc *context_desc;
6052         unsigned int i;
6053         int err;
6054         struct ixgbe_tx_buffer *tx_buffer_info;
6055         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6056         u32 mss_l4len_idx, l4len;
6057
6058         if (skb_is_gso(skb)) {
6059                 if (skb_header_cloned(skb)) {
6060                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6061                         if (err)
6062                                 return err;
6063                 }
6064                 l4len = tcp_hdrlen(skb);
6065                 *hdr_len += l4len;
6066
6067                 if (protocol == htons(ETH_P_IP)) {
6068                         struct iphdr *iph = ip_hdr(skb);
6069                         iph->tot_len = 0;
6070                         iph->check = 0;
6071                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6072                                                                  iph->daddr, 0,
6073                                                                  IPPROTO_TCP,
6074                                                                  0);
6075                 } else if (skb_is_gso_v6(skb)) {
6076                         ipv6_hdr(skb)->payload_len = 0;
6077                         tcp_hdr(skb)->check =
6078                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6079                                              &ipv6_hdr(skb)->daddr,
6080                                              0, IPPROTO_TCP, 0);
6081                 }
6082
6083                 i = tx_ring->next_to_use;
6084
6085                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6086                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6087
6088                 /* VLAN MACLEN IPLEN */
6089                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6090                         vlan_macip_lens |=
6091                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6092                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6093                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6094                 *hdr_len += skb_network_offset(skb);
6095                 vlan_macip_lens |=
6096                     (skb_transport_header(skb) - skb_network_header(skb));
6097                 *hdr_len +=
6098                     (skb_transport_header(skb) - skb_network_header(skb));
6099                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6100                 context_desc->seqnum_seed = 0;
6101
6102                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6103                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6104                                    IXGBE_ADVTXD_DTYP_CTXT);
6105
6106                 if (protocol == htons(ETH_P_IP))
6107                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6108                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6109                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6110
6111                 /* MSS L4LEN IDX */
6112                 mss_l4len_idx =
6113                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6114                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6115                 /* use index 1 for TSO */
6116                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6117                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6118
6119                 tx_buffer_info->time_stamp = jiffies;
6120                 tx_buffer_info->next_to_watch = i;
6121
6122                 i++;
6123                 if (i == tx_ring->count)
6124                         i = 0;
6125                 tx_ring->next_to_use = i;
6126
6127                 return true;
6128         }
6129         return false;
6130 }
6131
6132 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6133                       __be16 protocol)
6134 {
6135         u32 rtn = 0;
6136
6137         switch (protocol) {
6138         case cpu_to_be16(ETH_P_IP):
6139                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6140                 switch (ip_hdr(skb)->protocol) {
6141                 case IPPROTO_TCP:
6142                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6143                         break;
6144                 case IPPROTO_SCTP:
6145                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6146                         break;
6147                 }
6148                 break;
6149         case cpu_to_be16(ETH_P_IPV6):
6150                 /* XXX what about other V6 headers?? */
6151                 switch (ipv6_hdr(skb)->nexthdr) {
6152                 case IPPROTO_TCP:
6153                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6154                         break;
6155                 case IPPROTO_SCTP:
6156                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6157                         break;
6158                 }
6159                 break;
6160         default:
6161                 if (unlikely(net_ratelimit()))
6162                         e_warn(probe, "partial checksum but proto=%x!\n",
6163                                protocol);
6164                 break;
6165         }
6166
6167         return rtn;
6168 }
6169
6170 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6171                           struct ixgbe_ring *tx_ring,
6172                           struct sk_buff *skb, u32 tx_flags,
6173                           __be16 protocol)
6174 {
6175         struct ixgbe_adv_tx_context_desc *context_desc;
6176         unsigned int i;
6177         struct ixgbe_tx_buffer *tx_buffer_info;
6178         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6179
6180         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6181             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6182                 i = tx_ring->next_to_use;
6183                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6184                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6185
6186                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6187                         vlan_macip_lens |=
6188                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6189                 vlan_macip_lens |= (skb_network_offset(skb) <<
6190                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6191                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6192                         vlan_macip_lens |= (skb_transport_header(skb) -
6193                                             skb_network_header(skb));
6194
6195                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6196                 context_desc->seqnum_seed = 0;
6197
6198                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6199                                     IXGBE_ADVTXD_DTYP_CTXT);
6200
6201                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6202                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6203
6204                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6205                 /* use index zero for tx checksum offload */
6206                 context_desc->mss_l4len_idx = 0;
6207
6208                 tx_buffer_info->time_stamp = jiffies;
6209                 tx_buffer_info->next_to_watch = i;
6210
6211                 i++;
6212                 if (i == tx_ring->count)
6213                         i = 0;
6214                 tx_ring->next_to_use = i;
6215
6216                 return true;
6217         }
6218
6219         return false;
6220 }
6221
6222 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6223                         struct ixgbe_ring *tx_ring,
6224                         struct sk_buff *skb, u32 tx_flags,
6225                         unsigned int first, const u8 hdr_len)
6226 {
6227         struct device *dev = tx_ring->dev;
6228         struct ixgbe_tx_buffer *tx_buffer_info;
6229         unsigned int len;
6230         unsigned int total = skb->len;
6231         unsigned int offset = 0, size, count = 0, i;
6232         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6233         unsigned int f;
6234         unsigned int bytecount = skb->len;
6235         u16 gso_segs = 1;
6236
6237         i = tx_ring->next_to_use;
6238
6239         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6240                 /* excluding fcoe_crc_eof for FCoE */
6241                 total -= sizeof(struct fcoe_crc_eof);
6242
6243         len = min(skb_headlen(skb), total);
6244         while (len) {
6245                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6246                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6247
6248                 tx_buffer_info->length = size;
6249                 tx_buffer_info->mapped_as_page = false;
6250                 tx_buffer_info->dma = dma_map_single(dev,
6251                                                      skb->data + offset,
6252                                                      size, DMA_TO_DEVICE);
6253                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6254                         goto dma_error;
6255                 tx_buffer_info->time_stamp = jiffies;
6256                 tx_buffer_info->next_to_watch = i;
6257
6258                 len -= size;
6259                 total -= size;
6260                 offset += size;
6261                 count++;
6262
6263                 if (len) {
6264                         i++;
6265                         if (i == tx_ring->count)
6266                                 i = 0;
6267                 }
6268         }
6269
6270         for (f = 0; f < nr_frags; f++) {
6271                 struct skb_frag_struct *frag;
6272
6273                 frag = &skb_shinfo(skb)->frags[f];
6274                 len = min((unsigned int)frag->size, total);
6275                 offset = frag->page_offset;
6276
6277                 while (len) {
6278                         i++;
6279                         if (i == tx_ring->count)
6280                                 i = 0;
6281
6282                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6283                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6284
6285                         tx_buffer_info->length = size;
6286                         tx_buffer_info->dma = dma_map_page(dev,
6287                                                            frag->page,
6288                                                            offset, size,
6289                                                            DMA_TO_DEVICE);
6290                         tx_buffer_info->mapped_as_page = true;
6291                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6292                                 goto dma_error;
6293                         tx_buffer_info->time_stamp = jiffies;
6294                         tx_buffer_info->next_to_watch = i;
6295
6296                         len -= size;
6297                         total -= size;
6298                         offset += size;
6299                         count++;
6300                 }
6301                 if (total == 0)
6302                         break;
6303         }
6304
6305         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6306                 gso_segs = skb_shinfo(skb)->gso_segs;
6307 #ifdef IXGBE_FCOE
6308         /* adjust for FCoE Sequence Offload */
6309         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6310                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6311                                         skb_shinfo(skb)->gso_size);
6312 #endif /* IXGBE_FCOE */
6313         bytecount += (gso_segs - 1) * hdr_len;
6314
6315         /* multiply data chunks by size of headers */
6316         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6317         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6318         tx_ring->tx_buffer_info[i].skb = skb;
6319         tx_ring->tx_buffer_info[first].next_to_watch = i;
6320
6321         return count;
6322
6323 dma_error:
6324         e_dev_err("TX DMA map failed\n");
6325
6326         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6327         tx_buffer_info->dma = 0;
6328         tx_buffer_info->time_stamp = 0;
6329         tx_buffer_info->next_to_watch = 0;
6330         if (count)
6331                 count--;
6332
6333         /* clear timestamp and dma mappings for remaining portion of packet */
6334         while (count--) {
6335                 if (i == 0)
6336                         i += tx_ring->count;
6337                 i--;
6338                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6339                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6340         }
6341
6342         return 0;
6343 }
6344
6345 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6346                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6347 {
6348         union ixgbe_adv_tx_desc *tx_desc = NULL;
6349         struct ixgbe_tx_buffer *tx_buffer_info;
6350         u32 olinfo_status = 0, cmd_type_len = 0;
6351         unsigned int i;
6352         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6353
6354         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6355
6356         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6357
6358         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6359                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6360
6361         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6362                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6363
6364                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6365                                  IXGBE_ADVTXD_POPTS_SHIFT;
6366
6367                 /* use index 1 context for tso */
6368                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6369                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6370                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6371                                          IXGBE_ADVTXD_POPTS_SHIFT;
6372
6373         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6374                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6375                                  IXGBE_ADVTXD_POPTS_SHIFT;
6376
6377         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6378                 olinfo_status |= IXGBE_ADVTXD_CC;
6379                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6380                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6381                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6382         }
6383
6384         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6385
6386         i = tx_ring->next_to_use;
6387         while (count--) {
6388                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6389                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6390                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6391                 tx_desc->read.cmd_type_len =
6392                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6393                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6394                 i++;
6395                 if (i == tx_ring->count)
6396                         i = 0;
6397         }
6398
6399         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6400
6401         /*
6402          * Force memory writes to complete before letting h/w
6403          * know there are new descriptors to fetch.  (Only
6404          * applicable for weak-ordered memory model archs,
6405          * such as IA-64).
6406          */
6407         wmb();
6408
6409         tx_ring->next_to_use = i;
6410         writel(i, tx_ring->tail);
6411 }
6412
6413 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6414                       u8 queue, u32 tx_flags, __be16 protocol)
6415 {
6416         struct ixgbe_atr_input atr_input;
6417         struct iphdr *iph = ip_hdr(skb);
6418         struct ethhdr *eth = (struct ethhdr *)skb->data;
6419         struct tcphdr *th;
6420         u16 vlan_id;
6421
6422         /* Right now, we support IPv4 w/ TCP only */
6423         if (protocol != htons(ETH_P_IP) ||
6424             iph->protocol != IPPROTO_TCP)
6425                 return;
6426
6427         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6428
6429         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6430                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6431
6432         th = tcp_hdr(skb);
6433
6434         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6435         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6436         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6437         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6438         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6439         /* src and dst are inverted, think how the receiver sees them */
6440         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6441         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6442
6443         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6444         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6445 }
6446
6447 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6448 {
6449         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6450         /* Herbert's original patch had:
6451          *  smp_mb__after_netif_stop_queue();
6452          * but since that doesn't exist yet, just open code it. */
6453         smp_mb();
6454
6455         /* We need to check again in a case another CPU has just
6456          * made room available. */
6457         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6458                 return -EBUSY;
6459
6460         /* A reprieve! - use start_queue because it doesn't call schedule */
6461         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6462         ++tx_ring->tx_stats.restart_queue;
6463         return 0;
6464 }
6465
6466 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6467 {
6468         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6469                 return 0;
6470         return __ixgbe_maybe_stop_tx(tx_ring, size);
6471 }
6472
6473 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6474 {
6475         struct ixgbe_adapter *adapter = netdev_priv(dev);
6476         int txq = smp_processor_id();
6477 #ifdef IXGBE_FCOE
6478         __be16 protocol;
6479
6480         protocol = vlan_get_protocol(skb);
6481
6482         if ((protocol == htons(ETH_P_FCOE)) ||
6483             (protocol == htons(ETH_P_FIP))) {
6484                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6485                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6486                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6487                         return txq;
6488 #ifdef CONFIG_IXGBE_DCB
6489                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6490                         txq = adapter->fcoe.up;
6491                         return txq;
6492 #endif
6493                 }
6494         }
6495 #endif
6496
6497         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6498                 while (unlikely(txq >= dev->real_num_tx_queues))
6499                         txq -= dev->real_num_tx_queues;
6500                 return txq;
6501         }
6502
6503         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6504                 if (skb->priority == TC_PRIO_CONTROL)
6505                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6506                 else
6507                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6508                                >> 13;
6509                 return txq;
6510         }
6511
6512         return skb_tx_hash(dev, skb);
6513 }
6514
6515 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6516                           struct ixgbe_adapter *adapter,
6517                           struct ixgbe_ring *tx_ring)
6518 {
6519         struct net_device *netdev = tx_ring->netdev;
6520         struct netdev_queue *txq;
6521         unsigned int first;
6522         unsigned int tx_flags = 0;
6523         u8 hdr_len = 0;
6524         int tso;
6525         int count = 0;
6526         unsigned int f;
6527         __be16 protocol;
6528
6529         protocol = vlan_get_protocol(skb);
6530
6531         if (vlan_tx_tag_present(skb)) {
6532                 tx_flags |= vlan_tx_tag_get(skb);
6533                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6534                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6535                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6536                 }
6537                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6538                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6539         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6540                    skb->priority != TC_PRIO_CONTROL) {
6541                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6542                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6543                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6544         }
6545
6546 #ifdef IXGBE_FCOE
6547         /* for FCoE with DCB, we force the priority to what
6548          * was specified by the switch */
6549         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6550             (protocol == htons(ETH_P_FCOE) ||
6551              protocol == htons(ETH_P_FIP))) {
6552 #ifdef CONFIG_IXGBE_DCB
6553                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6554                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6555                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6556                         tx_flags |= ((adapter->fcoe.up << 13)
6557                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6558                 }
6559 #endif
6560                 /* flag for FCoE offloads */
6561                 if (protocol == htons(ETH_P_FCOE))
6562                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6563         }
6564 #endif
6565
6566         /* four things can cause us to need a context descriptor */
6567         if (skb_is_gso(skb) ||
6568             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6569             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6570             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6571                 count++;
6572
6573         count += TXD_USE_COUNT(skb_headlen(skb));
6574         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6575                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6576
6577         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6578                 tx_ring->tx_stats.tx_busy++;
6579                 return NETDEV_TX_BUSY;
6580         }
6581
6582         first = tx_ring->next_to_use;
6583         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6584 #ifdef IXGBE_FCOE
6585                 /* setup tx offload for FCoE */
6586                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6587                 if (tso < 0) {
6588                         dev_kfree_skb_any(skb);
6589                         return NETDEV_TX_OK;
6590                 }
6591                 if (tso)
6592                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6593 #endif /* IXGBE_FCOE */
6594         } else {
6595                 if (protocol == htons(ETH_P_IP))
6596                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6597                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6598                                 protocol);
6599                 if (tso < 0) {
6600                         dev_kfree_skb_any(skb);
6601                         return NETDEV_TX_OK;
6602                 }
6603
6604                 if (tso)
6605                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6606                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6607                                        protocol) &&
6608                          (skb->ip_summed == CHECKSUM_PARTIAL))
6609                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6610         }
6611
6612         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6613         if (count) {
6614                 /* add the ATR filter if ATR is on */
6615                 if (tx_ring->atr_sample_rate) {
6616                         ++tx_ring->atr_count;
6617                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6618                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6619                                       &tx_ring->state)) {
6620                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6621                                           tx_flags, protocol);
6622                                 tx_ring->atr_count = 0;
6623                         }
6624                 }
6625                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6626                 txq->tx_bytes += skb->len;
6627                 txq->tx_packets++;
6628                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6629                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6630
6631         } else {
6632                 dev_kfree_skb_any(skb);
6633                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6634                 tx_ring->next_to_use = first;
6635         }
6636
6637         return NETDEV_TX_OK;
6638 }
6639
6640 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6641 {
6642         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6643         struct ixgbe_ring *tx_ring;
6644
6645         tx_ring = adapter->tx_ring[skb->queue_mapping];
6646         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6647 }
6648
6649 /**
6650  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6651  * @netdev: network interface device structure
6652  * @p: pointer to an address structure
6653  *
6654  * Returns 0 on success, negative on failure
6655  **/
6656 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6657 {
6658         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6659         struct ixgbe_hw *hw = &adapter->hw;
6660         struct sockaddr *addr = p;
6661
6662         if (!is_valid_ether_addr(addr->sa_data))
6663                 return -EADDRNOTAVAIL;
6664
6665         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6666         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6667
6668         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6669                             IXGBE_RAH_AV);
6670
6671         return 0;
6672 }
6673
6674 static int
6675 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6676 {
6677         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6678         struct ixgbe_hw *hw = &adapter->hw;
6679         u16 value;
6680         int rc;
6681
6682         if (prtad != hw->phy.mdio.prtad)
6683                 return -EINVAL;
6684         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6685         if (!rc)
6686                 rc = value;
6687         return rc;
6688 }
6689
6690 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6691                             u16 addr, u16 value)
6692 {
6693         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6694         struct ixgbe_hw *hw = &adapter->hw;
6695
6696         if (prtad != hw->phy.mdio.prtad)
6697                 return -EINVAL;
6698         return hw->phy.ops.write_reg(hw, addr, devad, value);
6699 }
6700
6701 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6702 {
6703         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6704
6705         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6706 }
6707
6708 /**
6709  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6710  * netdev->dev_addrs
6711  * @netdev: network interface device structure
6712  *
6713  * Returns non-zero on failure
6714  **/
6715 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6716 {
6717         int err = 0;
6718         struct ixgbe_adapter *adapter = netdev_priv(dev);
6719         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6720
6721         if (is_valid_ether_addr(mac->san_addr)) {
6722                 rtnl_lock();
6723                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6724                 rtnl_unlock();
6725         }
6726         return err;
6727 }
6728
6729 /**
6730  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6731  * netdev->dev_addrs
6732  * @netdev: network interface device structure
6733  *
6734  * Returns non-zero on failure
6735  **/
6736 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6737 {
6738         int err = 0;
6739         struct ixgbe_adapter *adapter = netdev_priv(dev);
6740         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6741
6742         if (is_valid_ether_addr(mac->san_addr)) {
6743                 rtnl_lock();
6744                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6745                 rtnl_unlock();
6746         }
6747         return err;
6748 }
6749
6750 #ifdef CONFIG_NET_POLL_CONTROLLER
6751 /*
6752  * Polling 'interrupt' - used by things like netconsole to send skbs
6753  * without having to re-enable interrupts. It's not called while
6754  * the interrupt routine is executing.
6755  */
6756 static void ixgbe_netpoll(struct net_device *netdev)
6757 {
6758         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6759         int i;
6760
6761         /* if interface is down do nothing */
6762         if (test_bit(__IXGBE_DOWN, &adapter->state))
6763                 return;
6764
6765         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6766         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6767                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6768                 for (i = 0; i < num_q_vectors; i++) {
6769                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6770                         ixgbe_msix_clean_many(0, q_vector);
6771                 }
6772         } else {
6773                 ixgbe_intr(adapter->pdev->irq, netdev);
6774         }
6775         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6776 }
6777 #endif
6778
6779 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6780                                                    struct rtnl_link_stats64 *stats)
6781 {
6782         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6783         int i;
6784
6785         /* accurate rx/tx bytes/packets stats */
6786         dev_txq_stats_fold(netdev, stats);
6787         rcu_read_lock();
6788         for (i = 0; i < adapter->num_rx_queues; i++) {
6789                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6790                 u64 bytes, packets;
6791                 unsigned int start;
6792
6793                 if (ring) {
6794                         do {
6795                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6796                                 packets = ring->stats.packets;
6797                                 bytes   = ring->stats.bytes;
6798                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6799                         stats->rx_packets += packets;
6800                         stats->rx_bytes   += bytes;
6801                 }
6802         }
6803         rcu_read_unlock();
6804         /* following stats updated by ixgbe_watchdog_task() */
6805         stats->multicast        = netdev->stats.multicast;
6806         stats->rx_errors        = netdev->stats.rx_errors;
6807         stats->rx_length_errors = netdev->stats.rx_length_errors;
6808         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6809         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6810         return stats;
6811 }
6812
6813
6814 static const struct net_device_ops ixgbe_netdev_ops = {
6815         .ndo_open               = ixgbe_open,
6816         .ndo_stop               = ixgbe_close,
6817         .ndo_start_xmit         = ixgbe_xmit_frame,
6818         .ndo_select_queue       = ixgbe_select_queue,
6819         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6820         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6821         .ndo_validate_addr      = eth_validate_addr,
6822         .ndo_set_mac_address    = ixgbe_set_mac,
6823         .ndo_change_mtu         = ixgbe_change_mtu,
6824         .ndo_tx_timeout         = ixgbe_tx_timeout,
6825         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6826         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6827         .ndo_do_ioctl           = ixgbe_ioctl,
6828         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6829         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6830         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6831         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6832         .ndo_get_stats64        = ixgbe_get_stats64,
6833 #ifdef CONFIG_NET_POLL_CONTROLLER
6834         .ndo_poll_controller    = ixgbe_netpoll,
6835 #endif
6836 #ifdef IXGBE_FCOE
6837         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6838         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6839         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6840         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6841         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6842 #endif /* IXGBE_FCOE */
6843 };
6844
6845 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6846                            const struct ixgbe_info *ii)
6847 {
6848 #ifdef CONFIG_PCI_IOV
6849         struct ixgbe_hw *hw = &adapter->hw;
6850         int err;
6851
6852         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6853                 return;
6854
6855         /* The 82599 supports up to 64 VFs per physical function
6856          * but this implementation limits allocation to 63 so that
6857          * basic networking resources are still available to the
6858          * physical function
6859          */
6860         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6861         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6862         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6863         if (err) {
6864                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6865                 goto err_novfs;
6866         }
6867         /* If call to enable VFs succeeded then allocate memory
6868          * for per VF control structures.
6869          */
6870         adapter->vfinfo =
6871                 kcalloc(adapter->num_vfs,
6872                         sizeof(struct vf_data_storage), GFP_KERNEL);
6873         if (adapter->vfinfo) {
6874                 /* Now that we're sure SR-IOV is enabled
6875                  * and memory allocated set up the mailbox parameters
6876                  */
6877                 ixgbe_init_mbx_params_pf(hw);
6878                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6879                        sizeof(hw->mbx.ops));
6880
6881                 /* Disable RSC when in SR-IOV mode */
6882                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6883                                      IXGBE_FLAG2_RSC_ENABLED);
6884                 return;
6885         }
6886
6887         /* Oh oh */
6888         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6889               "SRIOV disabled\n");
6890         pci_disable_sriov(adapter->pdev);
6891
6892 err_novfs:
6893         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6894         adapter->num_vfs = 0;
6895 #endif /* CONFIG_PCI_IOV */
6896 }
6897
6898 /**
6899  * ixgbe_probe - Device Initialization Routine
6900  * @pdev: PCI device information struct
6901  * @ent: entry in ixgbe_pci_tbl
6902  *
6903  * Returns 0 on success, negative on failure
6904  *
6905  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6906  * The OS initialization, configuring of the adapter private structure,
6907  * and a hardware reset occur.
6908  **/
6909 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6910                                  const struct pci_device_id *ent)
6911 {
6912         struct net_device *netdev;
6913         struct ixgbe_adapter *adapter = NULL;
6914         struct ixgbe_hw *hw;
6915         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6916         static int cards_found;
6917         int i, err, pci_using_dac;
6918         unsigned int indices = num_possible_cpus();
6919 #ifdef IXGBE_FCOE
6920         u16 device_caps;
6921 #endif
6922         u32 part_num, eec;
6923
6924         /* Catch broken hardware that put the wrong VF device ID in
6925          * the PCIe SR-IOV capability.
6926          */
6927         if (pdev->is_virtfn) {
6928                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6929                      pci_name(pdev), pdev->vendor, pdev->device);
6930                 return -EINVAL;
6931         }
6932
6933         err = pci_enable_device_mem(pdev);
6934         if (err)
6935                 return err;
6936
6937         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6938             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6939                 pci_using_dac = 1;
6940         } else {
6941                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6942                 if (err) {
6943                         err = dma_set_coherent_mask(&pdev->dev,
6944                                                     DMA_BIT_MASK(32));
6945                         if (err) {
6946                                 dev_err(&pdev->dev,
6947                                         "No usable DMA configuration, aborting\n");
6948                                 goto err_dma;
6949                         }
6950                 }
6951                 pci_using_dac = 0;
6952         }
6953
6954         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6955                                            IORESOURCE_MEM), ixgbe_driver_name);
6956         if (err) {
6957                 dev_err(&pdev->dev,
6958                         "pci_request_selected_regions failed 0x%x\n", err);
6959                 goto err_pci_reg;
6960         }
6961
6962         pci_enable_pcie_error_reporting(pdev);
6963
6964         pci_set_master(pdev);
6965         pci_save_state(pdev);
6966
6967         if (ii->mac == ixgbe_mac_82598EB)
6968                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6969         else
6970                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6971
6972         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6973 #ifdef IXGBE_FCOE
6974         indices += min_t(unsigned int, num_possible_cpus(),
6975                          IXGBE_MAX_FCOE_INDICES);
6976 #endif
6977         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6978         if (!netdev) {
6979                 err = -ENOMEM;
6980                 goto err_alloc_etherdev;
6981         }
6982
6983         SET_NETDEV_DEV(netdev, &pdev->dev);
6984
6985         adapter = netdev_priv(netdev);
6986         pci_set_drvdata(pdev, adapter);
6987
6988         adapter->netdev = netdev;
6989         adapter->pdev = pdev;
6990         hw = &adapter->hw;
6991         hw->back = adapter;
6992         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6993
6994         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6995                               pci_resource_len(pdev, 0));
6996         if (!hw->hw_addr) {
6997                 err = -EIO;
6998                 goto err_ioremap;
6999         }
7000
7001         for (i = 1; i <= 5; i++) {
7002                 if (pci_resource_len(pdev, i) == 0)
7003                         continue;
7004         }
7005
7006         netdev->netdev_ops = &ixgbe_netdev_ops;
7007         ixgbe_set_ethtool_ops(netdev);
7008         netdev->watchdog_timeo = 5 * HZ;
7009         strcpy(netdev->name, pci_name(pdev));
7010
7011         adapter->bd_number = cards_found;
7012
7013         /* Setup hw api */
7014         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7015         hw->mac.type  = ii->mac;
7016
7017         /* EEPROM */
7018         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7019         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7020         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7021         if (!(eec & (1 << 8)))
7022                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7023
7024         /* PHY */
7025         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7026         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7027         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7028         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7029         hw->phy.mdio.mmds = 0;
7030         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7031         hw->phy.mdio.dev = netdev;
7032         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7033         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7034
7035         /* set up this timer and work struct before calling get_invariants
7036          * which might start the timer
7037          */
7038         init_timer(&adapter->sfp_timer);
7039         adapter->sfp_timer.function = ixgbe_sfp_timer;
7040         adapter->sfp_timer.data = (unsigned long) adapter;
7041
7042         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
7043
7044         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7045         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
7046
7047         /* a new SFP+ module arrival, called from GPI SDP2 context */
7048         INIT_WORK(&adapter->sfp_config_module_task,
7049                   ixgbe_sfp_config_module_task);
7050
7051         ii->get_invariants(hw);
7052
7053         /* setup the private structure */
7054         err = ixgbe_sw_init(adapter);
7055         if (err)
7056                 goto err_sw_init;
7057
7058         /* Make it possible the adapter to be woken up via WOL */
7059         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7060                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7061
7062         /*
7063          * If there is a fan on this device and it has failed log the
7064          * failure.
7065          */
7066         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7067                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7068                 if (esdp & IXGBE_ESDP_SDP1)
7069                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7070         }
7071
7072         /* reset_hw fills in the perm_addr as well */
7073         hw->phy.reset_if_overtemp = true;
7074         err = hw->mac.ops.reset_hw(hw);
7075         hw->phy.reset_if_overtemp = false;
7076         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7077             hw->mac.type == ixgbe_mac_82598EB) {
7078                 /*
7079                  * Start a kernel thread to watch for a module to arrive.
7080                  * Only do this for 82598, since 82599 will generate
7081                  * interrupts on module arrival.
7082                  */
7083                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7084                 mod_timer(&adapter->sfp_timer,
7085                           round_jiffies(jiffies + (2 * HZ)));
7086                 err = 0;
7087         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7088                 e_dev_err("failed to initialize because an unsupported SFP+ "
7089                           "module type was detected.\n");
7090                 e_dev_err("Reload the driver after installing a supported "
7091                           "module.\n");
7092                 goto err_sw_init;
7093         } else if (err) {
7094                 e_dev_err("HW Init failed: %d\n", err);
7095                 goto err_sw_init;
7096         }
7097
7098         ixgbe_probe_vf(adapter, ii);
7099
7100         netdev->features = NETIF_F_SG |
7101                            NETIF_F_IP_CSUM |
7102                            NETIF_F_HW_VLAN_TX |
7103                            NETIF_F_HW_VLAN_RX |
7104                            NETIF_F_HW_VLAN_FILTER;
7105
7106         netdev->features |= NETIF_F_IPV6_CSUM;
7107         netdev->features |= NETIF_F_TSO;
7108         netdev->features |= NETIF_F_TSO6;
7109         netdev->features |= NETIF_F_GRO;
7110
7111         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7112                 netdev->features |= NETIF_F_SCTP_CSUM;
7113
7114         netdev->vlan_features |= NETIF_F_TSO;
7115         netdev->vlan_features |= NETIF_F_TSO6;
7116         netdev->vlan_features |= NETIF_F_IP_CSUM;
7117         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7118         netdev->vlan_features |= NETIF_F_SG;
7119
7120         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7121                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7122                                     IXGBE_FLAG_DCB_ENABLED);
7123         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7124                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7125
7126 #ifdef CONFIG_IXGBE_DCB
7127         netdev->dcbnl_ops = &dcbnl_ops;
7128 #endif
7129
7130 #ifdef IXGBE_FCOE
7131         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7132                 if (hw->mac.ops.get_device_caps) {
7133                         hw->mac.ops.get_device_caps(hw, &device_caps);
7134                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7135                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7136                 }
7137         }
7138         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7139                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7140                 netdev->vlan_features |= NETIF_F_FSO;
7141                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7142         }
7143 #endif /* IXGBE_FCOE */
7144         if (pci_using_dac) {
7145                 netdev->features |= NETIF_F_HIGHDMA;
7146                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7147         }
7148
7149         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7150                 netdev->features |= NETIF_F_LRO;
7151
7152         /* make sure the EEPROM is good */
7153         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7154                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7155                 err = -EIO;
7156                 goto err_eeprom;
7157         }
7158
7159         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7160         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7161
7162         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7163                 e_dev_err("invalid MAC address\n");
7164                 err = -EIO;
7165                 goto err_eeprom;
7166         }
7167
7168         /* power down the optics */
7169         if (hw->phy.multispeed_fiber && hw->mac.ops.disable_tx_laser)
7170                 hw->mac.ops.disable_tx_laser(hw);
7171
7172         init_timer(&adapter->watchdog_timer);
7173         adapter->watchdog_timer.function = ixgbe_watchdog;
7174         adapter->watchdog_timer.data = (unsigned long)adapter;
7175
7176         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7177         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7178
7179         err = ixgbe_init_interrupt_scheme(adapter);
7180         if (err)
7181                 goto err_sw_init;
7182
7183         switch (pdev->device) {
7184         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7185                 /* All except this subdevice support WOL */
7186                 if (pdev->subsystem_device ==
7187                     IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7188                         adapter->wol = 0;
7189                         break;
7190                 }
7191         case IXGBE_DEV_ID_82599_KX4:
7192                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7193                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7194                 break;
7195         default:
7196                 adapter->wol = 0;
7197                 break;
7198         }
7199         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7200
7201         /* pick up the PCI bus settings for reporting later */
7202         hw->mac.ops.get_bus_info(hw);
7203
7204         /* print bus type/speed/width info */
7205         e_dev_info("(PCI Express:%s:%s) %pM\n",
7206                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7207                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7208                     "Unknown"),
7209                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7210                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7211                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7212                     "Unknown"),
7213                    netdev->dev_addr);
7214         ixgbe_read_pba_num_generic(hw, &part_num);
7215         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7216                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7217                            "PBA No: %06x-%03x\n",
7218                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7219                            (part_num >> 8), (part_num & 0xff));
7220         else
7221                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7222                            hw->mac.type, hw->phy.type,
7223                            (part_num >> 8), (part_num & 0xff));
7224
7225         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7226                 e_dev_warn("PCI-Express bandwidth available for this card is "
7227                            "not sufficient for optimal performance.\n");
7228                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7229                            "is required.\n");
7230         }
7231
7232         /* save off EEPROM version number */
7233         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7234
7235         /* reset the hardware with the new settings */
7236         err = hw->mac.ops.start_hw(hw);
7237
7238         if (err == IXGBE_ERR_EEPROM_VERSION) {
7239                 /* We are running on a pre-production device, log a warning */
7240                 e_dev_warn("This device is a pre-production adapter/LOM. "
7241                            "Please be aware there may be issues associated "
7242                            "with your hardware.  If you are experiencing "
7243                            "problems please contact your Intel or hardware "
7244                            "representative who provided you with this "
7245                            "hardware.\n");
7246         }
7247         strcpy(netdev->name, "eth%d");
7248         err = register_netdev(netdev);
7249         if (err)
7250                 goto err_register;
7251
7252         /* carrier off reporting is important to ethtool even BEFORE open */
7253         netif_carrier_off(netdev);
7254
7255         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7256             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7257                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7258
7259         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7260                 INIT_WORK(&adapter->check_overtemp_task,
7261                           ixgbe_check_overtemp_task);
7262 #ifdef CONFIG_IXGBE_DCA
7263         if (dca_add_requester(&pdev->dev) == 0) {
7264                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7265                 ixgbe_setup_dca(adapter);
7266         }
7267 #endif
7268         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7269                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7270                 for (i = 0; i < adapter->num_vfs; i++)
7271                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7272         }
7273
7274         /* add san mac addr to netdev */
7275         ixgbe_add_sanmac_netdev(netdev);
7276
7277         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7278         cards_found++;
7279         return 0;
7280
7281 err_register:
7282         ixgbe_release_hw_control(adapter);
7283         ixgbe_clear_interrupt_scheme(adapter);
7284 err_sw_init:
7285 err_eeprom:
7286         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7287                 ixgbe_disable_sriov(adapter);
7288         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7289         del_timer_sync(&adapter->sfp_timer);
7290         cancel_work_sync(&adapter->sfp_task);
7291         cancel_work_sync(&adapter->multispeed_fiber_task);
7292         cancel_work_sync(&adapter->sfp_config_module_task);
7293         iounmap(hw->hw_addr);
7294 err_ioremap:
7295         free_netdev(netdev);
7296 err_alloc_etherdev:
7297         pci_release_selected_regions(pdev,
7298                                      pci_select_bars(pdev, IORESOURCE_MEM));
7299 err_pci_reg:
7300 err_dma:
7301         pci_disable_device(pdev);
7302         return err;
7303 }
7304
7305 /**
7306  * ixgbe_remove - Device Removal Routine
7307  * @pdev: PCI device information struct
7308  *
7309  * ixgbe_remove is called by the PCI subsystem to alert the driver
7310  * that it should release a PCI device.  The could be caused by a
7311  * Hot-Plug event, or because the driver is going to be removed from
7312  * memory.
7313  **/
7314 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7315 {
7316         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7317         struct net_device *netdev = adapter->netdev;
7318
7319         set_bit(__IXGBE_DOWN, &adapter->state);
7320         /* clear the module not found bit to make sure the worker won't
7321          * reschedule
7322          */
7323         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7324         del_timer_sync(&adapter->watchdog_timer);
7325
7326         del_timer_sync(&adapter->sfp_timer);
7327         cancel_work_sync(&adapter->watchdog_task);
7328         cancel_work_sync(&adapter->sfp_task);
7329         cancel_work_sync(&adapter->multispeed_fiber_task);
7330         cancel_work_sync(&adapter->sfp_config_module_task);
7331         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7332             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7333                 cancel_work_sync(&adapter->fdir_reinit_task);
7334         flush_scheduled_work();
7335
7336 #ifdef CONFIG_IXGBE_DCA
7337         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7338                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7339                 dca_remove_requester(&pdev->dev);
7340                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7341         }
7342
7343 #endif
7344 #ifdef IXGBE_FCOE
7345         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7346                 ixgbe_cleanup_fcoe(adapter);
7347
7348 #endif /* IXGBE_FCOE */
7349
7350         /* remove the added san mac */
7351         ixgbe_del_sanmac_netdev(netdev);
7352
7353         if (netdev->reg_state == NETREG_REGISTERED)
7354                 unregister_netdev(netdev);
7355
7356         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7357                 ixgbe_disable_sriov(adapter);
7358
7359         ixgbe_clear_interrupt_scheme(adapter);
7360
7361         ixgbe_release_hw_control(adapter);
7362
7363         iounmap(adapter->hw.hw_addr);
7364         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7365                                      IORESOURCE_MEM));
7366
7367         e_dev_info("complete\n");
7368
7369         free_netdev(netdev);
7370
7371         pci_disable_pcie_error_reporting(pdev);
7372
7373         pci_disable_device(pdev);
7374 }
7375
7376 /**
7377  * ixgbe_io_error_detected - called when PCI error is detected
7378  * @pdev: Pointer to PCI device
7379  * @state: The current pci connection state
7380  *
7381  * This function is called after a PCI bus error affecting
7382  * this device has been detected.
7383  */
7384 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7385                                                 pci_channel_state_t state)
7386 {
7387         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7388         struct net_device *netdev = adapter->netdev;
7389
7390         netif_device_detach(netdev);
7391
7392         if (state == pci_channel_io_perm_failure)
7393                 return PCI_ERS_RESULT_DISCONNECT;
7394
7395         if (netif_running(netdev))
7396                 ixgbe_down(adapter);
7397         pci_disable_device(pdev);
7398
7399         /* Request a slot reset. */
7400         return PCI_ERS_RESULT_NEED_RESET;
7401 }
7402
7403 /**
7404  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7405  * @pdev: Pointer to PCI device
7406  *
7407  * Restart the card from scratch, as if from a cold-boot.
7408  */
7409 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7410 {
7411         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7412         pci_ers_result_t result;
7413         int err;
7414
7415         if (pci_enable_device_mem(pdev)) {
7416                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7417                 result = PCI_ERS_RESULT_DISCONNECT;
7418         } else {
7419                 pci_set_master(pdev);
7420                 pci_restore_state(pdev);
7421                 pci_save_state(pdev);
7422
7423                 pci_wake_from_d3(pdev, false);
7424
7425                 ixgbe_reset(adapter);
7426                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7427                 result = PCI_ERS_RESULT_RECOVERED;
7428         }
7429
7430         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7431         if (err) {
7432                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7433                           "failed 0x%0x\n", err);
7434                 /* non-fatal, continue */
7435         }
7436
7437         return result;
7438 }
7439
7440 /**
7441  * ixgbe_io_resume - called when traffic can start flowing again.
7442  * @pdev: Pointer to PCI device
7443  *
7444  * This callback is called when the error recovery driver tells us that
7445  * its OK to resume normal operation.
7446  */
7447 static void ixgbe_io_resume(struct pci_dev *pdev)
7448 {
7449         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7450         struct net_device *netdev = adapter->netdev;
7451
7452         if (netif_running(netdev)) {
7453                 if (ixgbe_up(adapter)) {
7454                         e_info(probe, "ixgbe_up failed after reset\n");
7455                         return;
7456                 }
7457         }
7458
7459         netif_device_attach(netdev);
7460 }
7461
7462 static struct pci_error_handlers ixgbe_err_handler = {
7463         .error_detected = ixgbe_io_error_detected,
7464         .slot_reset = ixgbe_io_slot_reset,
7465         .resume = ixgbe_io_resume,
7466 };
7467
7468 static struct pci_driver ixgbe_driver = {
7469         .name     = ixgbe_driver_name,
7470         .id_table = ixgbe_pci_tbl,
7471         .probe    = ixgbe_probe,
7472         .remove   = __devexit_p(ixgbe_remove),
7473 #ifdef CONFIG_PM
7474         .suspend  = ixgbe_suspend,
7475         .resume   = ixgbe_resume,
7476 #endif
7477         .shutdown = ixgbe_shutdown,
7478         .err_handler = &ixgbe_err_handler
7479 };
7480
7481 /**
7482  * ixgbe_init_module - Driver Registration Routine
7483  *
7484  * ixgbe_init_module is the first routine called when the driver is
7485  * loaded. All it does is register with the PCI subsystem.
7486  **/
7487 static int __init ixgbe_init_module(void)
7488 {
7489         int ret;
7490         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7491         pr_info("%s\n", ixgbe_copyright);
7492
7493 #ifdef CONFIG_IXGBE_DCA
7494         dca_register_notify(&dca_notifier);
7495 #endif
7496
7497         ret = pci_register_driver(&ixgbe_driver);
7498         return ret;
7499 }
7500
7501 module_init(ixgbe_init_module);
7502
7503 /**
7504  * ixgbe_exit_module - Driver Exit Cleanup Routine
7505  *
7506  * ixgbe_exit_module is called just before the driver is removed
7507  * from memory.
7508  **/
7509 static void __exit ixgbe_exit_module(void)
7510 {
7511 #ifdef CONFIG_IXGBE_DCA
7512         dca_unregister_notify(&dca_notifier);
7513 #endif
7514         pci_unregister_driver(&ixgbe_driver);
7515         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7516 }
7517
7518 #ifdef CONFIG_IXGBE_DCA
7519 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7520                             void *p)
7521 {
7522         int ret_val;
7523
7524         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7525                                          __ixgbe_notify_dca);
7526
7527         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7528 }
7529
7530 #endif /* CONFIG_IXGBE_DCA */
7531
7532 /**
7533  * ixgbe_get_hw_dev return device
7534  * used by hardware layer to print debugging information
7535  **/
7536 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7537 {
7538         struct ixgbe_adapter *adapter = hw->back;
7539         return adapter->netdev;
7540 }
7541
7542 module_exit(ixgbe_exit_module);
7543
7544 /* ixgbe_main.c */