drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         clear_check_for_tx_hang(tx_ring);
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int total_bytes = 0, total_packets = 0;
 739         u16 i, eop, count = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774         tx_ring->total_bytes += total_bytes;
 775         tx_ring->total_packets += total_packets;
 776         u64_stats_update_begin(&tx_ring->syncp);
 777         tx_ring->stats.packets += total_packets;
 778         tx_ring->stats.bytes += total_bytes;
 779         u64_stats_update_end(&tx_ring->syncp);
 780
 781         if (check_for_tx_hang(tx_ring) &&
 782             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 783                 /* schedule immediate reset if we believe we hung */
 784                 e_info(probe, "tx hang %d detected, resetting "
 785                        "adapter\n", adapter->tx_timeout_count + 1);
 786                 ixgbe_tx_timeout(adapter->netdev);
 787
 788                 /* the adapter is about to reset, no point in enabling stuff */
 789                 return true;
 790         }
 791
 792 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 793         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 794                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 795                 /* Make sure that anybody stopping the queue after this
 796                  * sees the new next_to_clean.
 797                  */
 798                 smp_mb();
 799                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 800                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 801                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 802                         ++tx_ring->tx_stats.restart_queue;
 803                 }
 804         }
 805
 806         return count < tx_ring->work_limit;
 807 }
 808
 809 #ifdef CONFIG_IXGBE_DCA
 810 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 811                                 struct ixgbe_ring *rx_ring,
 812                                 int cpu)
 813 {
 814         struct ixgbe_hw *hw = &adapter->hw;
 815         u32 rxctrl;
 816         u8 reg_idx = rx_ring->reg_idx;
 817
 818         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 819         switch (hw->mac.type) {
 820         case ixgbe_mac_82598EB:
 821                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 822                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 823                 break;
 824         case ixgbe_mac_82599EB:
 825                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 826                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 827                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 828                 break;
 829         default:
 830                 break;
 831         }
 832         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 833         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 834         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 835         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 836                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 837         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 838 }
 839
 840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 841                                 struct ixgbe_ring *tx_ring,
 842                                 int cpu)
 843 {
 844         struct ixgbe_hw *hw = &adapter->hw;
 845         u32 txctrl;
 846         u8 reg_idx = tx_ring->reg_idx;
 847
 848         switch (hw->mac.type) {
 849         case ixgbe_mac_82598EB:
 850                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 851                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 852                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 853                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 854                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 855                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 856                 break;
 857         case ixgbe_mac_82599EB:
 858                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 859                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 860                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 861                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 862                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 863                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 864                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 865                 break;
 866         default:
 867                 break;
 868         }
 869 }
 870
 871 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 872 {
 873         struct ixgbe_adapter *adapter = q_vector->adapter;
 874         int cpu = get_cpu();
 875         long r_idx;
 876         int i;
 877
 878         if (q_vector->cpu == cpu)
 879                 goto out_no_update;
 880
 881         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 882         for (i = 0; i < q_vector->txr_count; i++) {
 883                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 884                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 885                                       r_idx + 1);
 886         }
 887
 888         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 889         for (i = 0; i < q_vector->rxr_count; i++) {
 890                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 891                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 892                                       r_idx + 1);
 893         }
 894
 895         q_vector->cpu = cpu;
 896 out_no_update:
 897         put_cpu();
 898 }
 899
 900 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 901 {
 902         int num_q_vectors;
 903         int i;
 904
 905         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 906                 return;
 907
 908         /* always use CB2 mode, difference is masked in the CB driver */
 909         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 910
 911         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 912                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 913         else
 914                 num_q_vectors = 1;
 915
 916         for (i = 0; i < num_q_vectors; i++) {
 917                 adapter->q_vector[i]->cpu = -1;
 918                 ixgbe_update_dca(adapter->q_vector[i]);
 919         }
 920 }
 921
 922 static int __ixgbe_notify_dca(struct device *dev, void *data)
 923 {
 924         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 925         unsigned long event = *(unsigned long *)data;
 926
 927         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 928                 return 0;
 929
 930         switch (event) {
 931         case DCA_PROVIDER_ADD:
 932                 /* if we're already enabled, don't do it again */
 933                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 934                         break;
 935                 if (dca_add_requester(dev) == 0) {
 936                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 937                         ixgbe_setup_dca(adapter);
 938                         break;
 939                 }
 940                 /* Fall Through since DCA is disabled. */
 941         case DCA_PROVIDER_REMOVE:
 942                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 943                         dca_remove_requester(dev);
 944                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 945                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 946                 }
 947                 break;
 948         }
 949
 950         return 0;
 951 }
 952
 953 #endif /* CONFIG_IXGBE_DCA */
 954 /**
 955  * ixgbe_receive_skb - Send a completed packet up the stack
 956  * @adapter: board private structure
 957  * @skb: packet to send up
 958  * @status: hardware indication of status of receive
 959  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 960  * @rx_desc: rx descriptor
 961  **/
 962 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 963                               struct sk_buff *skb, u8 status,
 964                               struct ixgbe_ring *ring,
 965                               union ixgbe_adv_rx_desc *rx_desc)
 966 {
 967         struct ixgbe_adapter *adapter = q_vector->adapter;
 968         struct napi_struct *napi = &q_vector->napi;
 969         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 970         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 971
 972         if (is_vlan && (tag & VLAN_VID_MASK))
 973                 __vlan_hwaccel_put_tag(skb, tag);
 974
 975         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 976                 napi_gro_receive(napi, skb);
 977         else
 978                 netif_rx(skb);
 979 }
 980
 981 /**
 982  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 983  * @adapter: address of board private structure
 984  * @status_err: hardware indication of status of receive
 985  * @skb: skb currently being received and modified
 986  **/
 987 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 988                                      union ixgbe_adv_rx_desc *rx_desc,
 989                                      struct sk_buff *skb)
 990 {
 991         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 992
 993         skb_checksum_none_assert(skb);
 994
 995         /* Rx csum disabled */
 996         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 997                 return;
 998
 999         /* if IP and error */
1000         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1001             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1002                 adapter->hw_csum_rx_error++;
1003                 return;
1004         }
1005
1006         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1007                 return;
1008
1009         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1010                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012                 /*
1013                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1014                  * checksum errors.
1015                  */
1016                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1017                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1018                         return;
1019
1020                 adapter->hw_csum_rx_error++;
1021                 return;
1022         }
1023
1024         /* It must be a TCP or UDP packet with a valid checksum */
1025         skb->ip_summed = CHECKSUM_UNNECESSARY;
1026 }
1027
1028 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1029 {
1030         /*
1031          * Force memory writes to complete before letting h/w
1032          * know there are new descriptors to fetch.  (Only
1033          * applicable for weak-ordered memory model archs,
1034          * such as IA-64).
1035          */
1036         wmb();
1037         writel(val, rx_ring->tail);
1038 }
1039
1040 /**
1041  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1042  * @rx_ring: ring to place buffers on
1043  * @cleaned_count: number of buffers to replace
1044  **/
1045 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1046 {
1047         union ixgbe_adv_rx_desc *rx_desc;
1048         struct ixgbe_rx_buffer *bi;
1049         struct sk_buff *skb;
1050         u16 i = rx_ring->next_to_use;
1051
1052         /* do nothing if no valid netdev defined */
1053         if (!rx_ring->netdev)
1054                 return;
1055
1056         while (cleaned_count--) {
1057                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1058                 bi = &rx_ring->rx_buffer_info[i];
1059                 skb = bi->skb;
1060
1061                 if (!skb) {
1062                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1063                                                         rx_ring->rx_buf_len);
1064                         if (!skb) {
1065                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1066                                 goto no_buffers;
1067                         }
1068                         /* initialize queue mapping */
1069                         skb_record_rx_queue(skb, rx_ring->queue_index);
1070                         bi->skb = skb;
1071                 }
1072
1073                 if (!bi->dma) {
1074                         bi->dma = dma_map_single(rx_ring->dev,
1075                                                  skb->data,
1076                                                  rx_ring->rx_buf_len,
1077                                                  DMA_FROM_DEVICE);
1078                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1079                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1080                                 bi->dma = 0;
1081                                 goto no_buffers;
1082                         }
1083                 }
1084
1085                 if (ring_is_ps_enabled(rx_ring)) {
1086                         if (!bi->page) {
1087                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1088                                 if (!bi->page) {
1089                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1090                                         goto no_buffers;
1091                                 }
1092                         }
1093
1094                         if (!bi->page_dma) {
1095                                 /* use a half page if we're re-using */
1096                                 bi->page_offset ^= PAGE_SIZE / 2;
1097                                 bi->page_dma = dma_map_page(rx_ring->dev,
1098                                                             bi->page,
1099                                                             bi->page_offset,
1100                                                             PAGE_SIZE / 2,
1101                                                             DMA_FROM_DEVICE);
1102                                 if (dma_mapping_error(rx_ring->dev,
1103                                                       bi->page_dma)) {
1104                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1105                                         bi->page_dma = 0;
1106                                         goto no_buffers;
1107                                 }
1108                         }
1109
1110                         /* Refresh the desc even if buffer_addrs didn't change
1111                          * because each write-back erases this info. */
1112                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1113                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1114                 } else {
1115                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1116                         rx_desc->read.hdr_addr = 0;
1117                 }
1118
1119                 i++;
1120                 if (i == rx_ring->count)
1121                         i = 0;
1122         }
1123
1124 no_buffers:
1125         if (rx_ring->next_to_use != i) {
1126                 rx_ring->next_to_use = i;
1127                 ixgbe_release_rx_desc(rx_ring, i);
1128         }
1129 }
1130
1131 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1132 {
1133         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1134 }
1135
1136 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1137 {
1138         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1139 }
1140
1141 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1142 {
1143         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1144                 IXGBE_RXDADV_RSCCNT_MASK) >>
1145                 IXGBE_RXDADV_RSCCNT_SHIFT;
1146 }
1147
1148 /**
1149  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1150  * @skb: pointer to the last skb in the rsc queue
1151  * @count: pointer to number of packets coalesced in this context
1152  *
1153  * This function changes a queue full of hw rsc buffers into a completed
1154  * packet.  It uses the ->prev pointers to find the first packet and then
1155  * turns it into the frag list owner.
1156  **/
1157 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1158                                                         u64 *count)
1159 {
1160         unsigned int frag_list_size = 0;
1161
1162         while (skb->prev) {
1163                 struct sk_buff *prev = skb->prev;
1164                 frag_list_size += skb->len;
1165                 skb->prev = NULL;
1166                 skb = prev;
1167                 *count += 1;
1168         }
1169
1170         skb_shinfo(skb)->frag_list = skb->next;
1171         skb->next = NULL;
1172         skb->len += frag_list_size;
1173         skb->data_len += frag_list_size;
1174         skb->truesize += frag_list_size;
1175         return skb;
1176 }
1177
1178 struct ixgbe_rsc_cb {
1179         dma_addr_t dma;
1180         bool delay_unmap;
1181 };
1182
1183 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1184
1185 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1186                                struct ixgbe_ring *rx_ring,
1187                                int *work_done, int work_to_do)
1188 {
1189         struct ixgbe_adapter *adapter = q_vector->adapter;
1190         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1191         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1192         struct sk_buff *skb;
1193         unsigned int i, rsc_count = 0;
1194         u32 len, staterr;
1195         u16 hdr_info;
1196         bool cleaned = false;
1197         int cleaned_count = 0;
1198         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1199 #ifdef IXGBE_FCOE
1200         int ddp_bytes = 0;
1201 #endif /* IXGBE_FCOE */
1202
1203         i = rx_ring->next_to_clean;
1204         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1205         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1206         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1207
1208         while (staterr & IXGBE_RXD_STAT_DD) {
1209                 u32 upper_len = 0;
1210                 if (*work_done >= work_to_do)
1211                         break;
1212                 (*work_done)++;
1213
1214                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215                 if (ring_is_ps_enabled(rx_ring)) {
1216                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1217                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1218                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1219                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1220                         if ((len > IXGBE_RX_HDR_SIZE) ||
1221                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1222                                 len = IXGBE_RX_HDR_SIZE;
1223                 } else {
1224                         len = le16_to_cpu(rx_desc->wb.upper.length);
1225                 }
1226
1227                 cleaned = true;
1228                 skb = rx_buffer_info->skb;
1229                 prefetch(skb->data);
1230                 rx_buffer_info->skb = NULL;
1231
1232                 if (rx_buffer_info->dma) {
1233                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1234                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1235                                  (!(skb->prev))) {
1236                                 /*
1237                                  * When HWRSC is enabled, delay unmapping
1238                                  * of the first packet. It carries the
1239                                  * header information, HW may still
1240                                  * access the header after the writeback.
1241                                  * Only unmap it when EOP is reached
1242                                  */
1243                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1244                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1245                         } else {
1246                                 dma_unmap_single(rx_ring->dev,
1247                                                  rx_buffer_info->dma,
1248                                                  rx_ring->rx_buf_len,
1249                                                  DMA_FROM_DEVICE);
1250                         }
1251                         rx_buffer_info->dma = 0;
1252                         skb_put(skb, len);
1253                 }
1254
1255                 if (upper_len) {
1256                         dma_unmap_page(rx_ring->dev,
1257                                        rx_buffer_info->page_dma,
1258                                        PAGE_SIZE / 2,
1259                                        DMA_FROM_DEVICE);
1260                         rx_buffer_info->page_dma = 0;
1261                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1262                                            rx_buffer_info->page,
1263                                            rx_buffer_info->page_offset,
1264                                            upper_len);
1265
1266                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1267                             (page_count(rx_buffer_info->page) != 1))
1268                                 rx_buffer_info->page = NULL;
1269                         else
1270                                 get_page(rx_buffer_info->page);
1271
1272                         skb->len += upper_len;
1273                         skb->data_len += upper_len;
1274                         skb->truesize += upper_len;
1275                 }
1276
1277                 i++;
1278                 if (i == rx_ring->count)
1279                         i = 0;
1280
1281                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1282                 prefetch(next_rxd);
1283                 cleaned_count++;
1284
1285                 if (ring_is_rsc_enabled(rx_ring))
1286                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1287
1288                 if (rsc_count) {
1289                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1290                                      IXGBE_RXDADV_NEXTP_SHIFT;
1291                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1292                 } else {
1293                         next_buffer = &rx_ring->rx_buffer_info[i];
1294                 }
1295
1296                 if (staterr & IXGBE_RXD_STAT_EOP) {
1297                         if (skb->prev)
1298                                 skb = ixgbe_transform_rsc_queue(skb,
1299                                                 &(rx_ring->rx_stats.rsc_count));
1300                         if (ring_is_rsc_enabled(rx_ring)) {
1301                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1302                                         dma_unmap_single(rx_ring->dev,
1303                                                          IXGBE_RSC_CB(skb)->dma,
1304                                                          rx_ring->rx_buf_len,
1305                                                          DMA_FROM_DEVICE);
1306                                         IXGBE_RSC_CB(skb)->dma = 0;
1307                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1308                                 }
1309                                 if (ring_is_ps_enabled(rx_ring))
1310                                         rx_ring->rx_stats.rsc_count +=
1311                                                  skb_shinfo(skb)->nr_frags;
1312                                 else
1313                                         rx_ring->rx_stats.rsc_count++;
1314                                 rx_ring->rx_stats.rsc_flush++;
1315                         }
1316                         u64_stats_update_begin(&rx_ring->syncp);
1317                         rx_ring->stats.packets++;
1318                         rx_ring->stats.bytes += skb->len;
1319                         u64_stats_update_end(&rx_ring->syncp);
1320                 } else {
1321                         if (ring_is_ps_enabled(rx_ring)) {
1322                                 rx_buffer_info->skb = next_buffer->skb;
1323                                 rx_buffer_info->dma = next_buffer->dma;
1324                                 next_buffer->skb = skb;
1325                                 next_buffer->dma = 0;
1326                         } else {
1327                                 skb->next = next_buffer->skb;
1328                                 skb->next->prev = skb;
1329                         }
1330                         rx_ring->rx_stats.non_eop_descs++;
1331                         goto next_desc;
1332                 }
1333
1334                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1335                         dev_kfree_skb_irq(skb);
1336                         goto next_desc;
1337                 }
1338
1339                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1340
1341                 /* probably a little skewed due to removing CRC */
1342                 total_rx_bytes += skb->len;
1343                 total_rx_packets++;
1344
1345                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1346 #ifdef IXGBE_FCOE
1347                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1348                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1349                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1350                         if (!ddp_bytes)
1351                                 goto next_desc;
1352                 }
1353 #endif /* IXGBE_FCOE */
1354                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1355
1356 next_desc:
1357                 rx_desc->wb.upper.status_error = 0;
1358
1359                 /* return some buffers to hardware, one at a time is too slow */
1360                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1361                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1362                         cleaned_count = 0;
1363                 }
1364
1365                 /* use prefetched values */
1366                 rx_desc = next_rxd;
1367                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1368
1369                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1370         }
1371
1372         rx_ring->next_to_clean = i;
1373         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1374
1375         if (cleaned_count)
1376                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1377
1378 #ifdef IXGBE_FCOE
1379         /* include DDPed FCoE data */
1380         if (ddp_bytes > 0) {
1381                 unsigned int mss;
1382
1383                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1384                         sizeof(struct fc_frame_header) -
1385                         sizeof(struct fcoe_crc_eof);
1386                 if (mss > 512)
1387                         mss &= ~511;
1388                 total_rx_bytes += ddp_bytes;
1389                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1390         }
1391 #endif /* IXGBE_FCOE */
1392
1393         rx_ring->total_packets += total_rx_packets;
1394         rx_ring->total_bytes += total_rx_bytes;
1395
1396         return cleaned;
1397 }
1398
1399 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1400 /**
1401  * ixgbe_configure_msix - Configure MSI-X hardware
1402  * @adapter: board private structure
1403  *
1404  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1405  * interrupts.
1406  **/
1407 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1408 {
1409         struct ixgbe_q_vector *q_vector;
1410         int i, j, q_vectors, v_idx, r_idx;
1411         u32 mask;
1412
1413         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1414
1415         /*
1416          * Populate the IVAR table and set the ITR values to the
1417          * corresponding register.
1418          */
1419         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1420                 q_vector = adapter->q_vector[v_idx];
1421                 /* XXX for_each_set_bit(...) */
1422                 r_idx = find_first_bit(q_vector->rxr_idx,
1423                                        adapter->num_rx_queues);
1424
1425                 for (i = 0; i < q_vector->rxr_count; i++) {
1426                         j = adapter->rx_ring[r_idx]->reg_idx;
1427                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1428                         r_idx = find_next_bit(q_vector->rxr_idx,
1429                                               adapter->num_rx_queues,
1430                                               r_idx + 1);
1431                 }
1432                 r_idx = find_first_bit(q_vector->txr_idx,
1433                                        adapter->num_tx_queues);
1434
1435                 for (i = 0; i < q_vector->txr_count; i++) {
1436                         j = adapter->tx_ring[r_idx]->reg_idx;
1437                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1438                         r_idx = find_next_bit(q_vector->txr_idx,
1439                                               adapter->num_tx_queues,
1440                                               r_idx + 1);
1441                 }
1442
1443                 if (q_vector->txr_count && !q_vector->rxr_count)
1444                         /* tx only */
1445                         q_vector->eitr = adapter->tx_eitr_param;
1446                 else if (q_vector->rxr_count)
1447                         /* rx or mixed */
1448                         q_vector->eitr = adapter->rx_eitr_param;
1449
1450                 ixgbe_write_eitr(q_vector);
1451                 /* If Flow Director is enabled, set interrupt affinity */
1452                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1453                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1454                         /*
1455                          * Allocate the affinity_hint cpumask, assign the mask
1456                          * for this vector, and set our affinity_hint for
1457                          * this irq.
1458                          */
1459                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1460                                                GFP_KERNEL))
1461                                 return;
1462                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1463                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1464                                               q_vector->affinity_mask);
1465                 }
1466         }
1467
1468         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1469                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1470                                v_idx);
1471         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1472                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1473         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1474
1475         /* set up to autoclear timer, and the vectors */
1476         mask = IXGBE_EIMS_ENABLE_MASK;
1477         if (adapter->num_vfs)
1478                 mask &= ~(IXGBE_EIMS_OTHER |
1479                           IXGBE_EIMS_MAILBOX |
1480                           IXGBE_EIMS_LSC);
1481         else
1482                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1483         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1484 }
1485
1486 enum latency_range {
1487         lowest_latency = 0,
1488         low_latency = 1,
1489         bulk_latency = 2,
1490         latency_invalid = 255
1491 };
1492
1493 /**
1494  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1495  * @adapter: pointer to adapter
1496  * @eitr: eitr setting (ints per sec) to give last timeslice
1497  * @itr_setting: current throttle rate in ints/second
1498  * @packets: the number of packets during this measurement interval
1499  * @bytes: the number of bytes during this measurement interval
1500  *
1501  *      Stores a new ITR value based on packets and byte
1502  *      counts during the last interrupt.  The advantage of per interrupt
1503  *      computation is faster updates and more accurate ITR for the current
1504  *      traffic pattern.  Constants in this function were computed
1505  *      based on theoretical maximum wire speed and thresholds were set based
1506  *      on testing data as well as attempting to minimize response time
1507  *      while increasing bulk throughput.
1508  *      this functionality is controlled by the InterruptThrottleRate module
1509  *      parameter (see ixgbe_param.c)
1510  **/
1511 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1512                            u32 eitr, u8 itr_setting,
1513                            int packets, int bytes)
1514 {
1515         unsigned int retval = itr_setting;
1516         u32 timepassed_us;
1517         u64 bytes_perint;
1518
1519         if (packets == 0)
1520                 goto update_itr_done;
1521
1522
1523         /* simple throttlerate management
1524          *    0-20MB/s lowest (100000 ints/s)
1525          *   20-100MB/s low   (20000 ints/s)
1526          *  100-1249MB/s bulk (8000 ints/s)
1527          */
1528         /* what was last interrupt timeslice? */
1529         timepassed_us = 1000000/eitr;
1530         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1531
1532         switch (itr_setting) {
1533         case lowest_latency:
1534                 if (bytes_perint > adapter->eitr_low)
1535                         retval = low_latency;
1536                 break;
1537         case low_latency:
1538                 if (bytes_perint > adapter->eitr_high)
1539                         retval = bulk_latency;
1540                 else if (bytes_perint <= adapter->eitr_low)
1541                         retval = lowest_latency;
1542                 break;
1543         case bulk_latency:
1544                 if (bytes_perint <= adapter->eitr_high)
1545                         retval = low_latency;
1546                 break;
1547         }
1548
1549 update_itr_done:
1550         return retval;
1551 }
1552
1553 /**
1554  * ixgbe_write_eitr - write EITR register in hardware specific way
1555  * @q_vector: structure containing interrupt and ring information
1556  *
1557  * This function is made to be called by ethtool and by the driver
1558  * when it needs to update EITR registers at runtime.  Hardware
1559  * specific quirks/differences are taken care of here.
1560  */
1561 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1562 {
1563         struct ixgbe_adapter *adapter = q_vector->adapter;
1564         struct ixgbe_hw *hw = &adapter->hw;
1565         int v_idx = q_vector->v_idx;
1566         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1567
1568         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1569                 /* must write high and low 16 bits to reset counter */
1570                 itr_reg |= (itr_reg << 16);
1571         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1572                 /*
1573                  * 82599 can support a value of zero, so allow it for
1574                  * max interrupt rate, but there is an errata where it can
1575                  * not be zero with RSC
1576                  */
1577                 if (itr_reg == 8 &&
1578                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1579                         itr_reg = 0;
1580
1581                 /*
1582                  * set the WDIS bit to not clear the timer bits and cause an
1583                  * immediate assertion of the interrupt
1584                  */
1585                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1586         }
1587         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1588 }
1589
1590 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1591 {
1592         struct ixgbe_adapter *adapter = q_vector->adapter;
1593         u32 new_itr;
1594         u8 current_itr, ret_itr;
1595         int i, r_idx;
1596         struct ixgbe_ring *rx_ring, *tx_ring;
1597
1598         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1599         for (i = 0; i < q_vector->txr_count; i++) {
1600                 tx_ring = adapter->tx_ring[r_idx];
1601                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1602                                            q_vector->tx_itr,
1603                                            tx_ring->total_packets,
1604                                            tx_ring->total_bytes);
1605                 /* if the result for this queue would decrease interrupt
1606                  * rate for this vector then use that result */
1607                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1608                                     q_vector->tx_itr - 1 : ret_itr);
1609                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1610                                       r_idx + 1);
1611         }
1612
1613         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1614         for (i = 0; i < q_vector->rxr_count; i++) {
1615                 rx_ring = adapter->rx_ring[r_idx];
1616                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1617                                            q_vector->rx_itr,
1618                                            rx_ring->total_packets,
1619                                            rx_ring->total_bytes);
1620                 /* if the result for this queue would decrease interrupt
1621                  * rate for this vector then use that result */
1622                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1623                                     q_vector->rx_itr - 1 : ret_itr);
1624                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1625                                       r_idx + 1);
1626         }
1627
1628         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1629
1630         switch (current_itr) {
1631         /* counts and packets in update_itr are dependent on these numbers */
1632         case lowest_latency:
1633                 new_itr = 100000;
1634                 break;
1635         case low_latency:
1636                 new_itr = 20000; /* aka hwitr = ~200 */
1637                 break;
1638         case bulk_latency:
1639         default:
1640                 new_itr = 8000;
1641                 break;
1642         }
1643
1644         if (new_itr != q_vector->eitr) {
1645                 /* do an exponential smoothing */
1646                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1647
1648                 /* save the algorithm value here, not the smoothed one */
1649                 q_vector->eitr = new_itr;
1650
1651                 ixgbe_write_eitr(q_vector);
1652         }
1653 }
1654
1655 /**
1656  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1657  * @work: pointer to work_struct containing our data
1658  **/
1659 static void ixgbe_check_overtemp_task(struct work_struct *work)
1660 {
1661         struct ixgbe_adapter *adapter = container_of(work,
1662                                                      struct ixgbe_adapter,
1663                                                      check_overtemp_task);
1664         struct ixgbe_hw *hw = &adapter->hw;
1665         u32 eicr = adapter->interrupt_event;
1666
1667         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1668                 return;
1669
1670         switch (hw->device_id) {
1671         case IXGBE_DEV_ID_82599_T3_LOM: {
1672                 u32 autoneg;
1673                 bool link_up = false;
1674
1675                 if (hw->mac.ops.check_link)
1676                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1677
1678                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1679                     (eicr & IXGBE_EICR_LSC))
1680                         /* Check if this is due to overtemp */
1681                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1682                                 break;
1683                 return;
1684         }
1685         default:
1686                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1687                         return;
1688                 break;
1689         }
1690         e_crit(drv,
1691                "Network adapter has been stopped because it has over heated. "
1692                "Restart the computer. If the problem persists, "
1693                "power off the system and replace the adapter\n");
1694         /* write to clear the interrupt */
1695         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1696 }
1697
1698 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1699 {
1700         struct ixgbe_hw *hw = &adapter->hw;
1701
1702         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1703             (eicr & IXGBE_EICR_GPI_SDP1)) {
1704                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1705                 /* write to clear the interrupt */
1706                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1707         }
1708 }
1709
1710 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1711 {
1712         struct ixgbe_hw *hw = &adapter->hw;
1713
1714         if (eicr & IXGBE_EICR_GPI_SDP2) {
1715                 /* Clear the interrupt */
1716                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1717                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1718                         schedule_work(&adapter->sfp_config_module_task);
1719         }
1720
1721         if (eicr & IXGBE_EICR_GPI_SDP1) {
1722                 /* Clear the interrupt */
1723                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1724                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1725                         schedule_work(&adapter->multispeed_fiber_task);
1726         }
1727 }
1728
1729 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1730 {
1731         struct ixgbe_hw *hw = &adapter->hw;
1732
1733         adapter->lsc_int++;
1734         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1735         adapter->link_check_timeout = jiffies;
1736         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1737                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1738                 IXGBE_WRITE_FLUSH(hw);
1739                 schedule_work(&adapter->watchdog_task);
1740         }
1741 }
1742
1743 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1744 {
1745         struct net_device *netdev = data;
1746         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1747         struct ixgbe_hw *hw = &adapter->hw;
1748         u32 eicr;
1749
1750         /*
1751          * Workaround for Silicon errata.  Use clear-by-write instead
1752          * of clear-by-read.  Reading with EICS will return the
1753          * interrupt causes without clearing, which later be done
1754          * with the write to EICR.
1755          */
1756         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1757         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1758
1759         if (eicr & IXGBE_EICR_LSC)
1760                 ixgbe_check_lsc(adapter);
1761
1762         if (eicr & IXGBE_EICR_MAILBOX)
1763                 ixgbe_msg_task(adapter);
1764
1765         if (hw->mac.type == ixgbe_mac_82598EB)
1766                 ixgbe_check_fan_failure(adapter, eicr);
1767
1768         if (hw->mac.type == ixgbe_mac_82599EB) {
1769                 ixgbe_check_sfp_event(adapter, eicr);
1770                 adapter->interrupt_event = eicr;
1771                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1772                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1773                         schedule_work(&adapter->check_overtemp_task);
1774
1775                 /* Handle Flow Director Full threshold interrupt */
1776                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1777                         int i;
1778                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1779                         /* Disable transmits before FDIR Re-initialization */
1780                         netif_tx_stop_all_queues(netdev);
1781                         for (i = 0; i < adapter->num_tx_queues; i++) {
1782                                 struct ixgbe_ring *tx_ring =
1783                                                             adapter->tx_ring[i];
1784                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1785                                                        &tx_ring->state))
1786                                         schedule_work(&adapter->fdir_reinit_task);
1787                         }
1788                 }
1789         }
1790         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1791                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1792
1793         return IRQ_HANDLED;
1794 }
1795
1796 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1797                                            u64 qmask)
1798 {
1799         u32 mask;
1800
1801         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1802                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1803                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1804         } else {
1805                 mask = (qmask & 0xFFFFFFFF);
1806                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1807                 mask = (qmask >> 32);
1808                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1809         }
1810         /* skip the flush */
1811 }
1812
1813 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1814                                             u64 qmask)
1815 {
1816         u32 mask;
1817
1818         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1819                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1820                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1821         } else {
1822                 mask = (qmask & 0xFFFFFFFF);
1823                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1824                 mask = (qmask >> 32);
1825                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1826         }
1827         /* skip the flush */
1828 }
1829
1830 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1831 {
1832         struct ixgbe_q_vector *q_vector = data;
1833         struct ixgbe_adapter  *adapter = q_vector->adapter;
1834         struct ixgbe_ring     *tx_ring;
1835         int i, r_idx;
1836
1837         if (!q_vector->txr_count)
1838                 return IRQ_HANDLED;
1839
1840         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1841         for (i = 0; i < q_vector->txr_count; i++) {
1842                 tx_ring = adapter->tx_ring[r_idx];
1843                 tx_ring->total_bytes = 0;
1844                 tx_ring->total_packets = 0;
1845                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1846                                       r_idx + 1);
1847         }
1848
1849         /* EIAM disabled interrupts (on this vector) for us */
1850         napi_schedule(&q_vector->napi);
1851
1852         return IRQ_HANDLED;
1853 }
1854
1855 /**
1856  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1857  * @irq: unused
1858  * @data: pointer to our q_vector struct for this interrupt vector
1859  **/
1860 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1861 {
1862         struct ixgbe_q_vector *q_vector = data;
1863         struct ixgbe_adapter  *adapter = q_vector->adapter;
1864         struct ixgbe_ring  *rx_ring;
1865         int r_idx;
1866         int i;
1867
1868 #ifdef CONFIG_IXGBE_DCA
1869         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1870                 ixgbe_update_dca(q_vector);
1871 #endif
1872
1873         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1874         for (i = 0; i < q_vector->rxr_count; i++) {
1875                 rx_ring = adapter->rx_ring[r_idx];
1876                 rx_ring->total_bytes = 0;
1877                 rx_ring->total_packets = 0;
1878                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1879                                       r_idx + 1);
1880         }
1881
1882         if (!q_vector->rxr_count)
1883                 return IRQ_HANDLED;
1884
1885         /* EIAM disabled interrupts (on this vector) for us */
1886         napi_schedule(&q_vector->napi);
1887
1888         return IRQ_HANDLED;
1889 }
1890
1891 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1892 {
1893         struct ixgbe_q_vector *q_vector = data;
1894         struct ixgbe_adapter  *adapter = q_vector->adapter;
1895         struct ixgbe_ring  *ring;
1896         int r_idx;
1897         int i;
1898
1899         if (!q_vector->txr_count && !q_vector->rxr_count)
1900                 return IRQ_HANDLED;
1901
1902         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1903         for (i = 0; i < q_vector->txr_count; i++) {
1904                 ring = adapter->tx_ring[r_idx];
1905                 ring->total_bytes = 0;
1906                 ring->total_packets = 0;
1907                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1908                                       r_idx + 1);
1909         }
1910
1911         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1912         for (i = 0; i < q_vector->rxr_count; i++) {
1913                 ring = adapter->rx_ring[r_idx];
1914                 ring->total_bytes = 0;
1915                 ring->total_packets = 0;
1916                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1917                                       r_idx + 1);
1918         }
1919
1920         /* EIAM disabled interrupts (on this vector) for us */
1921         napi_schedule(&q_vector->napi);
1922
1923         return IRQ_HANDLED;
1924 }
1925
1926 /**
1927  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1928  * @napi: napi struct with our devices info in it
1929  * @budget: amount of work driver is allowed to do this pass, in packets
1930  *
1931  * This function is optimized for cleaning one queue only on a single
1932  * q_vector!!!
1933  **/
1934 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1935 {
1936         struct ixgbe_q_vector *q_vector =
1937                                container_of(napi, struct ixgbe_q_vector, napi);
1938         struct ixgbe_adapter *adapter = q_vector->adapter;
1939         struct ixgbe_ring *rx_ring = NULL;
1940         int work_done = 0;
1941         long r_idx;
1942
1943 #ifdef CONFIG_IXGBE_DCA
1944         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1945                 ixgbe_update_dca(q_vector);
1946 #endif
1947
1948         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1949         rx_ring = adapter->rx_ring[r_idx];
1950
1951         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1952
1953         /* If all Rx work done, exit the polling mode */
1954         if (work_done < budget) {
1955                 napi_complete(napi);
1956                 if (adapter->rx_itr_setting & 1)
1957                         ixgbe_set_itr_msix(q_vector);
1958                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1959                         ixgbe_irq_enable_queues(adapter,
1960                                                 ((u64)1 << q_vector->v_idx));
1961         }
1962
1963         return work_done;
1964 }
1965
1966 /**
1967  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1968  * @napi: napi struct with our devices info in it
1969  * @budget: amount of work driver is allowed to do this pass, in packets
1970  *
1971  * This function will clean more than one rx queue associated with a
1972  * q_vector.
1973  **/
1974 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1975 {
1976         struct ixgbe_q_vector *q_vector =
1977                                container_of(napi, struct ixgbe_q_vector, napi);
1978         struct ixgbe_adapter *adapter = q_vector->adapter;
1979         struct ixgbe_ring *ring = NULL;
1980         int work_done = 0, i;
1981         long r_idx;
1982         bool tx_clean_complete = true;
1983
1984 #ifdef CONFIG_IXGBE_DCA
1985         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1986                 ixgbe_update_dca(q_vector);
1987 #endif
1988
1989         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1990         for (i = 0; i < q_vector->txr_count; i++) {
1991                 ring = adapter->tx_ring[r_idx];
1992                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1993                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1994                                       r_idx + 1);
1995         }
1996
1997         /* attempt to distribute budget to each queue fairly, but don't allow
1998          * the budget to go below 1 because we'll exit polling */
1999         budget /= (q_vector->rxr_count ?: 1);
2000         budget = max(budget, 1);
2001         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2002         for (i = 0; i < q_vector->rxr_count; i++) {
2003                 ring = adapter->rx_ring[r_idx];
2004                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2005                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2006                                       r_idx + 1);
2007         }
2008
2009         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2010         ring = adapter->rx_ring[r_idx];
2011         /* If all Rx work done, exit the polling mode */
2012         if (work_done < budget) {
2013                 napi_complete(napi);
2014                 if (adapter->rx_itr_setting & 1)
2015                         ixgbe_set_itr_msix(q_vector);
2016                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2017                         ixgbe_irq_enable_queues(adapter,
2018                                                 ((u64)1 << q_vector->v_idx));
2019                 return 0;
2020         }
2021
2022         return work_done;
2023 }
2024
2025 /**
2026  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2027  * @napi: napi struct with our devices info in it
2028  * @budget: amount of work driver is allowed to do this pass, in packets
2029  *
2030  * This function is optimized for cleaning one queue only on a single
2031  * q_vector!!!
2032  **/
2033 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2034 {
2035         struct ixgbe_q_vector *q_vector =
2036                                container_of(napi, struct ixgbe_q_vector, napi);
2037         struct ixgbe_adapter *adapter = q_vector->adapter;
2038         struct ixgbe_ring *tx_ring = NULL;
2039         int work_done = 0;
2040         long r_idx;
2041
2042 #ifdef CONFIG_IXGBE_DCA
2043         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2044                 ixgbe_update_dca(q_vector);
2045 #endif
2046
2047         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2048         tx_ring = adapter->tx_ring[r_idx];
2049
2050         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2051                 work_done = budget;
2052
2053         /* If all Tx work done, exit the polling mode */
2054         if (work_done < budget) {
2055                 napi_complete(napi);
2056                 if (adapter->tx_itr_setting & 1)
2057                         ixgbe_set_itr_msix(q_vector);
2058                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2059                         ixgbe_irq_enable_queues(adapter,
2060                                                 ((u64)1 << q_vector->v_idx));
2061         }
2062
2063         return work_done;
2064 }
2065
2066 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2067                                      int r_idx)
2068 {
2069         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2070
2071         set_bit(r_idx, q_vector->rxr_idx);
2072         q_vector->rxr_count++;
2073 }
2074
2075 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2076                                      int t_idx)
2077 {
2078         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2079
2080         set_bit(t_idx, q_vector->txr_idx);
2081         q_vector->txr_count++;
2082 }
2083
2084 /**
2085  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2086  * @adapter: board private structure to initialize
2087  * @vectors: allotted vector count for descriptor rings
2088  *
2089  * This function maps descriptor rings to the queue-specific vectors
2090  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2091  * one vector per ring/queue, but on a constrained vector budget, we
2092  * group the rings as "efficiently" as possible.  You would add new
2093  * mapping configurations in here.
2094  **/
2095 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2096                                       int vectors)
2097 {
2098         int v_start = 0;
2099         int rxr_idx = 0, txr_idx = 0;
2100         int rxr_remaining = adapter->num_rx_queues;
2101         int txr_remaining = adapter->num_tx_queues;
2102         int i, j;
2103         int rqpv, tqpv;
2104         int err = 0;
2105
2106         /* No mapping required if MSI-X is disabled. */
2107         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2108                 goto out;
2109
2110         /*
2111          * The ideal configuration...
2112          * We have enough vectors to map one per queue.
2113          */
2114         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2115                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2116                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2117
2118                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2119                         map_vector_to_txq(adapter, v_start, txr_idx);
2120
2121                 goto out;
2122         }
2123
2124         /*
2125          * If we don't have enough vectors for a 1-to-1
2126          * mapping, we'll have to group them so there are
2127          * multiple queues per vector.
2128          */
2129         /* Re-adjusting *qpv takes care of the remainder. */
2130         for (i = v_start; i < vectors; i++) {
2131                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2132                 for (j = 0; j < rqpv; j++) {
2133                         map_vector_to_rxq(adapter, i, rxr_idx);
2134                         rxr_idx++;
2135                         rxr_remaining--;
2136                 }
2137         }
2138         for (i = v_start; i < vectors; i++) {
2139                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2140                 for (j = 0; j < tqpv; j++) {
2141                         map_vector_to_txq(adapter, i, txr_idx);
2142                         txr_idx++;
2143                         txr_remaining--;
2144                 }
2145         }
2146
2147 out:
2148         return err;
2149 }
2150
2151 /**
2152  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2153  * @adapter: board private structure
2154  *
2155  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2156  * interrupts from the kernel.
2157  **/
2158 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2159 {
2160         struct net_device *netdev = adapter->netdev;
2161         irqreturn_t (*handler)(int, void *);
2162         int i, vector, q_vectors, err;
2163         int ri = 0, ti = 0;
2164
2165         /* Decrement for Other and TCP Timer vectors */
2166         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2167
2168         /* Map the Tx/Rx rings to the vectors we were allotted. */
2169         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2170         if (err)
2171                 goto out;
2172
2173 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2174                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2175                          &ixgbe_msix_clean_many)
2176         for (vector = 0; vector < q_vectors; vector++) {
2177                 handler = SET_HANDLER(adapter->q_vector[vector]);
2178
2179                 if (handler == &ixgbe_msix_clean_rx) {
2180                         sprintf(adapter->name[vector], "%s-%s-%d",
2181                                 netdev->name, "rx", ri++);
2182                 } else if (handler == &ixgbe_msix_clean_tx) {
2183                         sprintf(adapter->name[vector], "%s-%s-%d",
2184                                 netdev->name, "tx", ti++);
2185                 } else {
2186                         sprintf(adapter->name[vector], "%s-%s-%d",
2187                                 netdev->name, "TxRx", ri++);
2188                         ti++;
2189                 }
2190
2191                 err = request_irq(adapter->msix_entries[vector].vector,
2192                                   handler, 0, adapter->name[vector],
2193                                   adapter->q_vector[vector]);
2194                 if (err) {
2195                         e_err(probe, "request_irq failed for MSIX interrupt "
2196                               "Error: %d\n", err);
2197                         goto free_queue_irqs;
2198                 }
2199         }
2200
2201         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2202         err = request_irq(adapter->msix_entries[vector].vector,
2203                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2204         if (err) {
2205                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2206                 goto free_queue_irqs;
2207         }
2208
2209         return 0;
2210
2211 free_queue_irqs:
2212         for (i = vector - 1; i >= 0; i--)
2213                 free_irq(adapter->msix_entries[--vector].vector,
2214                          adapter->q_vector[i]);
2215         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2216         pci_disable_msix(adapter->pdev);
2217         kfree(adapter->msix_entries);
2218         adapter->msix_entries = NULL;
2219 out:
2220         return err;
2221 }
2222
2223 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2224 {
2225         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2226         u8 current_itr;
2227         u32 new_itr = q_vector->eitr;
2228         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2229         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2230
2231         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2232                                             q_vector->tx_itr,
2233                                             tx_ring->total_packets,
2234                                             tx_ring->total_bytes);
2235         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2236                                             q_vector->rx_itr,
2237                                             rx_ring->total_packets,
2238                                             rx_ring->total_bytes);
2239
2240         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2241
2242         switch (current_itr) {
2243         /* counts and packets in update_itr are dependent on these numbers */
2244         case lowest_latency:
2245                 new_itr = 100000;
2246                 break;
2247         case low_latency:
2248                 new_itr = 20000; /* aka hwitr = ~200 */
2249                 break;
2250         case bulk_latency:
2251                 new_itr = 8000;
2252                 break;
2253         default:
2254                 break;
2255         }
2256
2257         if (new_itr != q_vector->eitr) {
2258                 /* do an exponential smoothing */
2259                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2260
2261                 /* save the algorithm value here, not the smoothed one */
2262                 q_vector->eitr = new_itr;
2263
2264                 ixgbe_write_eitr(q_vector);
2265         }
2266 }
2267
2268 /**
2269  * ixgbe_irq_enable - Enable default interrupt generation settings
2270  * @adapter: board private structure
2271  **/
2272 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2273                                     bool flush)
2274 {
2275         u32 mask;
2276
2277         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2278         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2279                 mask |= IXGBE_EIMS_GPI_SDP0;
2280         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2281                 mask |= IXGBE_EIMS_GPI_SDP1;
2282         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2283                 mask |= IXGBE_EIMS_ECC;
2284                 mask |= IXGBE_EIMS_GPI_SDP1;
2285                 mask |= IXGBE_EIMS_GPI_SDP2;
2286                 if (adapter->num_vfs)
2287                         mask |= IXGBE_EIMS_MAILBOX;
2288         }
2289         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2290             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2291                 mask |= IXGBE_EIMS_FLOW_DIR;
2292
2293         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2294         if (queues)
2295                 ixgbe_irq_enable_queues(adapter, ~0);
2296         if (flush)
2297                 IXGBE_WRITE_FLUSH(&adapter->hw);
2298
2299         if (adapter->num_vfs > 32) {
2300                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2301                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2302         }
2303 }
2304
2305 /**
2306  * ixgbe_intr - legacy mode Interrupt Handler
2307  * @irq: interrupt number
2308  * @data: pointer to a network interface device structure
2309  **/
2310 static irqreturn_t ixgbe_intr(int irq, void *data)
2311 {
2312         struct net_device *netdev = data;
2313         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2314         struct ixgbe_hw *hw = &adapter->hw;
2315         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2316         u32 eicr;
2317
2318         /*
2319          * Workaround for silicon errata on 82598.  Mask the interrupts
2320          * before the read of EICR.
2321          */
2322         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2323
2324         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2325          * therefore no explict interrupt disable is necessary */
2326         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2327         if (!eicr) {
2328                 /*
2329                  * shared interrupt alert!
2330                  * make sure interrupts are enabled because the read will
2331                  * have disabled interrupts due to EIAM
2332                  * finish the workaround of silicon errata on 82598.  Unmask
2333                  * the interrupt that we masked before the EICR read.
2334                  */
2335                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2336                         ixgbe_irq_enable(adapter, true, true);
2337                 return IRQ_NONE;        /* Not our interrupt */
2338         }
2339
2340         if (eicr & IXGBE_EICR_LSC)
2341                 ixgbe_check_lsc(adapter);
2342
2343         if (hw->mac.type == ixgbe_mac_82599EB)
2344                 ixgbe_check_sfp_event(adapter, eicr);
2345
2346         ixgbe_check_fan_failure(adapter, eicr);
2347         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2348             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2349                 schedule_work(&adapter->check_overtemp_task);
2350
2351         if (napi_schedule_prep(&(q_vector->napi))) {
2352                 adapter->tx_ring[0]->total_packets = 0;
2353                 adapter->tx_ring[0]->total_bytes = 0;
2354                 adapter->rx_ring[0]->total_packets = 0;
2355                 adapter->rx_ring[0]->total_bytes = 0;
2356                 /* would disable interrupts here but EIAM disabled it */
2357                 __napi_schedule(&(q_vector->napi));
2358         }
2359
2360         /*
2361          * re-enable link(maybe) and non-queue interrupts, no flush.
2362          * ixgbe_poll will re-enable the queue interrupts
2363          */
2364
2365         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2366                 ixgbe_irq_enable(adapter, false, false);
2367
2368         return IRQ_HANDLED;
2369 }
2370
2371 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2372 {
2373         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2374
2375         for (i = 0; i < q_vectors; i++) {
2376                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2377                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2378                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2379                 q_vector->rxr_count = 0;
2380                 q_vector->txr_count = 0;
2381         }
2382 }
2383
2384 /**
2385  * ixgbe_request_irq - initialize interrupts
2386  * @adapter: board private structure
2387  *
2388  * Attempts to configure interrupts using the best available
2389  * capabilities of the hardware and kernel.
2390  **/
2391 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2392 {
2393         struct net_device *netdev = adapter->netdev;
2394         int err;
2395
2396         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2397                 err = ixgbe_request_msix_irqs(adapter);
2398         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2399                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2400                                   netdev->name, netdev);
2401         } else {
2402                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2403                                   netdev->name, netdev);
2404         }
2405
2406         if (err)
2407                 e_err(probe, "request_irq failed, Error %d\n", err);
2408
2409         return err;
2410 }
2411
2412 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2413 {
2414         struct net_device *netdev = adapter->netdev;
2415
2416         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2417                 int i, q_vectors;
2418
2419                 q_vectors = adapter->num_msix_vectors;
2420
2421                 i = q_vectors - 1;
2422                 free_irq(adapter->msix_entries[i].vector, netdev);
2423
2424                 i--;
2425                 for (; i >= 0; i--) {
2426                         free_irq(adapter->msix_entries[i].vector,
2427                                  adapter->q_vector[i]);
2428                 }
2429
2430                 ixgbe_reset_q_vectors(adapter);
2431         } else {
2432                 free_irq(adapter->pdev->irq, netdev);
2433         }
2434 }
2435
2436 /**
2437  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2438  * @adapter: board private structure
2439  **/
2440 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2441 {
2442         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2443                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2444         } else {
2445                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2446                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2447                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2448                 if (adapter->num_vfs > 32)
2449                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2450         }
2451         IXGBE_WRITE_FLUSH(&adapter->hw);
2452         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2453                 int i;
2454                 for (i = 0; i < adapter->num_msix_vectors; i++)
2455                         synchronize_irq(adapter->msix_entries[i].vector);
2456         } else {
2457                 synchronize_irq(adapter->pdev->irq);
2458         }
2459 }
2460
2461 /**
2462  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2463  *
2464  **/
2465 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2466 {
2467         struct ixgbe_hw *hw = &adapter->hw;
2468
2469         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2470                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2471
2472         ixgbe_set_ivar(adapter, 0, 0, 0);
2473         ixgbe_set_ivar(adapter, 1, 0, 0);
2474
2475         map_vector_to_rxq(adapter, 0, 0);
2476         map_vector_to_txq(adapter, 0, 0);
2477
2478         e_info(hw, "Legacy interrupt IVAR setup done\n");
2479 }
2480
2481 /**
2482  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2483  * @adapter: board private structure
2484  * @ring: structure containing ring specific data
2485  *
2486  * Configure the Tx descriptor ring after a reset.
2487  **/
2488 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2489                              struct ixgbe_ring *ring)
2490 {
2491         struct ixgbe_hw *hw = &adapter->hw;
2492         u64 tdba = ring->dma;
2493         int wait_loop = 10;
2494         u32 txdctl;
2495         u16 reg_idx = ring->reg_idx;
2496
2497         /* disable queue to avoid issues while updating state */
2498         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2499         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2500                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2501         IXGBE_WRITE_FLUSH(hw);
2502
2503         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2504                         (tdba & DMA_BIT_MASK(32)));
2505         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2506         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2507                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2508         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2509         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2510         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2511
2512         /* configure fetching thresholds */
2513         if (adapter->rx_itr_setting == 0) {
2514                 /* cannot set wthresh when itr==0 */
2515                 txdctl &= ~0x007F0000;
2516         } else {
2517                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2518                 txdctl |= (8 << 16);
2519         }
2520         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2521                 /* PThresh workaround for Tx hang with DFP enabled. */
2522                 txdctl |= 32;
2523         }
2524
2525         /* reinitialize flowdirector state */
2526         set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2527
2528         /* enable queue */
2529         txdctl |= IXGBE_TXDCTL_ENABLE;
2530         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2531
2532         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2533         if (hw->mac.type == ixgbe_mac_82598EB &&
2534             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2535                 return;
2536
2537         /* poll to verify queue is enabled */
2538         do {
2539                 msleep(1);
2540                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2541         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2542         if (!wait_loop)
2543                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2544 }
2545
2546 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2547 {
2548         struct ixgbe_hw *hw = &adapter->hw;
2549         u32 rttdcs;
2550         u32 mask;
2551
2552         if (hw->mac.type == ixgbe_mac_82598EB)
2553                 return;
2554
2555         /* disable the arbiter while setting MTQC */
2556         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2557         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2558         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2559
2560         /* set transmit pool layout */
2561         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2562         switch (adapter->flags & mask) {
2563
2564         case (IXGBE_FLAG_SRIOV_ENABLED):
2565                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2566                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2567                 break;
2568
2569         case (IXGBE_FLAG_DCB_ENABLED):
2570                 /* We enable 8 traffic classes, DCB only */
2571                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2572                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2573                 break;
2574
2575         default:
2576                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2577                 break;
2578         }
2579
2580         /* re-enable the arbiter */
2581         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2582         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2583 }
2584
2585 /**
2586  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2587  * @adapter: board private structure
2588  *
2589  * Configure the Tx unit of the MAC after a reset.
2590  **/
2591 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2592 {
2593         struct ixgbe_hw *hw = &adapter->hw;
2594         u32 dmatxctl;
2595         u32 i;
2596
2597         ixgbe_setup_mtqc(adapter);
2598
2599         if (hw->mac.type != ixgbe_mac_82598EB) {
2600                 /* DMATXCTL.EN must be before Tx queues are enabled */
2601                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2602                 dmatxctl |= IXGBE_DMATXCTL_TE;
2603                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2604         }
2605
2606         /* Setup the HW Tx Head and Tail descriptor pointers */
2607         for (i = 0; i < adapter->num_tx_queues; i++)
2608                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2609 }
2610
2611 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2612
2613 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2614                                    struct ixgbe_ring *rx_ring)
2615 {
2616         u32 srrctl;
2617         int index;
2618         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2619
2620         index = rx_ring->reg_idx;
2621         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2622                 unsigned long mask;
2623                 mask = (unsigned long) feature[RING_F_RSS].mask;
2624                 index = index & mask;
2625         }
2626         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2627
2628         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2629         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2630         if (adapter->num_vfs)
2631                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2632
2633         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2634                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2635
2636         if (ring_is_ps_enabled(rx_ring)) {
2637 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2638                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2639 #else
2640                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2641 #endif
2642                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2643         } else {
2644                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2645                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2646                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2647         }
2648
2649         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2650 }
2651
2652 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2653 {
2654         struct ixgbe_hw *hw = &adapter->hw;
2655         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2656                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2657                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2658         u32 mrqc = 0, reta = 0;
2659         u32 rxcsum;
2660         int i, j;
2661         int mask;
2662
2663         /* Fill out hash function seeds */
2664         for (i = 0; i < 10; i++)
2665                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2666
2667         /* Fill out redirection table */
2668         for (i = 0, j = 0; i < 128; i++, j++) {
2669                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2670                         j = 0;
2671                 /* reta = 4-byte sliding window of
2672                  * 0x00..(indices-1)(indices-1)00..etc. */
2673                 reta = (reta << 8) | (j * 0x11);
2674                 if ((i & 3) == 3)
2675                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2676         }
2677
2678         /* Disable indicating checksum in descriptor, enables RSS hash */
2679         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2680         rxcsum |= IXGBE_RXCSUM_PCSD;
2681         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2682
2683         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2684                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2685         else
2686                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2687 #ifdef CONFIG_IXGBE_DCB
2688                                          | IXGBE_FLAG_DCB_ENABLED
2689 #endif
2690                                          | IXGBE_FLAG_SRIOV_ENABLED
2691                                         );
2692
2693         switch (mask) {
2694         case (IXGBE_FLAG_RSS_ENABLED):
2695                 mrqc = IXGBE_MRQC_RSSEN;
2696                 break;
2697         case (IXGBE_FLAG_SRIOV_ENABLED):
2698                 mrqc = IXGBE_MRQC_VMDQEN;
2699                 break;
2700 #ifdef CONFIG_IXGBE_DCB
2701         case (IXGBE_FLAG_DCB_ENABLED):
2702                 mrqc = IXGBE_MRQC_RT8TCEN;
2703                 break;
2704 #endif /* CONFIG_IXGBE_DCB */
2705         default:
2706                 break;
2707         }
2708
2709         /* Perform hash on these packet types */
2710         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2711               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2712               | IXGBE_MRQC_RSS_FIELD_IPV6
2713               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2714
2715         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2716 }
2717
2718 /**
2719  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2720  * @adapter:    address of board private structure
2721  * @index:      index of ring to set
2722  **/
2723 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2724                                    struct ixgbe_ring *ring)
2725 {
2726         struct ixgbe_hw *hw = &adapter->hw;
2727         u32 rscctrl;
2728         int rx_buf_len;
2729         u16 reg_idx = ring->reg_idx;
2730
2731         if (!ring_is_rsc_enabled(ring))
2732                 return;
2733
2734         rx_buf_len = ring->rx_buf_len;
2735         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2736         rscctrl |= IXGBE_RSCCTL_RSCEN;
2737         /*
2738          * we must limit the number of descriptors so that the
2739          * total size of max desc * buf_len is not greater
2740          * than 65535
2741          */
2742         if (ring_is_ps_enabled(ring)) {
2743 #if (MAX_SKB_FRAGS > 16)
2744                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2745 #elif (MAX_SKB_FRAGS > 8)
2746                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2747 #elif (MAX_SKB_FRAGS > 4)
2748                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2749 #else
2750                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2751 #endif
2752         } else {
2753                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2754                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2755                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2756                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2757                 else
2758                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2759         }
2760         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2761 }
2762
2763 /**
2764  *  ixgbe_set_uta - Set unicast filter table address
2765  *  @adapter: board private structure
2766  *
2767  *  The unicast table address is a register array of 32-bit registers.
2768  *  The table is meant to be used in a way similar to how the MTA is used
2769  *  however due to certain limitations in the hardware it is necessary to
2770  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2771  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2772  **/
2773 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2774 {
2775         struct ixgbe_hw *hw = &adapter->hw;
2776         int i;
2777
2778         /* The UTA table only exists on 82599 hardware and newer */
2779         if (hw->mac.type < ixgbe_mac_82599EB)
2780                 return;
2781
2782         /* we only need to do this if VMDq is enabled */
2783         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2784                 return;
2785
2786         for (i = 0; i < 128; i++)
2787                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2788 }
2789
2790 #define IXGBE_MAX_RX_DESC_POLL 10
2791 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2792                                        struct ixgbe_ring *ring)
2793 {
2794         struct ixgbe_hw *hw = &adapter->hw;
2795         int reg_idx = ring->reg_idx;
2796         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2797         u32 rxdctl;
2798
2799         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2800         if (hw->mac.type == ixgbe_mac_82598EB &&
2801             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2802                 return;
2803
2804         do {
2805                 msleep(1);
2806                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2807         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2808
2809         if (!wait_loop) {
2810                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2811                       "the polling period\n", reg_idx);
2812         }
2813 }
2814
2815 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2816                              struct ixgbe_ring *ring)
2817 {
2818         struct ixgbe_hw *hw = &adapter->hw;
2819         u64 rdba = ring->dma;
2820         u32 rxdctl;
2821         u16 reg_idx = ring->reg_idx;
2822
2823         /* disable queue to avoid issues while updating state */
2824         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2825         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2826                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2827         IXGBE_WRITE_FLUSH(hw);
2828
2829         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2830         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2831         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2832                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2833         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2834         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2835         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2836
2837         ixgbe_configure_srrctl(adapter, ring);
2838         ixgbe_configure_rscctl(adapter, ring);
2839
2840         if (hw->mac.type == ixgbe_mac_82598EB) {
2841                 /*
2842                  * enable cache line friendly hardware writes:
2843                  * PTHRESH=32 descriptors (half the internal cache),
2844                  * this also removes ugly rx_no_buffer_count increment
2845                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2846                  * WTHRESH=8 burst writeback up to two cache lines
2847                  */
2848                 rxdctl &= ~0x3FFFFF;
2849                 rxdctl |=  0x080420;
2850         }
2851
2852         /* enable receive descriptor ring */
2853         rxdctl |= IXGBE_RXDCTL_ENABLE;
2854         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2855
2856         ixgbe_rx_desc_queue_enable(adapter, ring);
2857         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2858 }
2859
2860 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2861 {
2862         struct ixgbe_hw *hw = &adapter->hw;
2863         int p;
2864
2865         /* PSRTYPE must be initialized in non 82598 adapters */
2866         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2867                       IXGBE_PSRTYPE_UDPHDR |
2868                       IXGBE_PSRTYPE_IPV4HDR |
2869                       IXGBE_PSRTYPE_L2HDR |
2870                       IXGBE_PSRTYPE_IPV6HDR;
2871
2872         if (hw->mac.type == ixgbe_mac_82598EB)
2873                 return;
2874
2875         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2876                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2877
2878         for (p = 0; p < adapter->num_rx_pools; p++)
2879                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2880                                 psrtype);
2881 }
2882
2883 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2884 {
2885         struct ixgbe_hw *hw = &adapter->hw;
2886         u32 gcr_ext;
2887         u32 vt_reg_bits;
2888         u32 reg_offset, vf_shift;
2889         u32 vmdctl;
2890
2891         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2892                 return;
2893
2894         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2895         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2896         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2897         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2898
2899         vf_shift = adapter->num_vfs % 32;
2900         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2901
2902         /* Enable only the PF's pool for Tx/Rx */
2903         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2904         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2905         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2906         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2907         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2908
2909         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2910         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2911
2912         /*
2913          * Set up VF register offsets for selected VT Mode,
2914          * i.e. 32 or 64 VFs for SR-IOV
2915          */
2916         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2917         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2918         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2919         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2920
2921         /* enable Tx loopback for VF/PF communication */
2922         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2923 }
2924
2925 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2926 {
2927         struct ixgbe_hw *hw = &adapter->hw;
2928         struct net_device *netdev = adapter->netdev;
2929         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2930         int rx_buf_len;
2931         struct ixgbe_ring *rx_ring;
2932         int i;
2933         u32 mhadd, hlreg0;
2934
2935         /* Decide whether to use packet split mode or not */
2936         /* Do not use packet split if we're in SR-IOV Mode */
2937         if (!adapter->num_vfs)
2938                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2939
2940         /* Set the RX buffer length according to the mode */
2941         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2942                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2943         } else {
2944                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2945                     (netdev->mtu <= ETH_DATA_LEN))
2946                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2947                 else
2948                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2949         }
2950
2951 #ifdef IXGBE_FCOE
2952         /* adjust max frame to be able to do baby jumbo for FCoE */
2953         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2954             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2955                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2956
2957 #endif /* IXGBE_FCOE */
2958         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2959         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2960                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2961                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2962
2963                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2964         }
2965
2966         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2967         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2968         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2969         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2970
2971         /*
2972          * Setup the HW Rx Head and Tail Descriptor Pointers and
2973          * the Base and Length of the Rx Descriptor Ring
2974          */
2975         for (i = 0; i < adapter->num_rx_queues; i++) {
2976                 rx_ring = adapter->rx_ring[i];
2977                 rx_ring->rx_buf_len = rx_buf_len;
2978
2979                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2980                         set_ring_ps_enabled(rx_ring);
2981                 else
2982                         clear_ring_ps_enabled(rx_ring);
2983
2984                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2985                         set_ring_rsc_enabled(rx_ring);
2986                 else
2987                         clear_ring_rsc_enabled(rx_ring);
2988
2989 #ifdef IXGBE_FCOE
2990                 if (netdev->features & NETIF_F_FCOE_MTU) {
2991                         struct ixgbe_ring_feature *f;
2992                         f = &adapter->ring_feature[RING_F_FCOE];
2993                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2994                                 clear_ring_ps_enabled(rx_ring);
2995                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2996                                         rx_ring->rx_buf_len =
2997                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2998                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2999                                    !ring_is_ps_enabled(rx_ring)) {
3000                                 rx_ring->rx_buf_len =
3001                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3002                         }
3003                 }
3004 #endif /* IXGBE_FCOE */
3005         }
3006
3007 }
3008
3009 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3010 {
3011         struct ixgbe_hw *hw = &adapter->hw;
3012         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3013
3014         switch (hw->mac.type) {
3015         case ixgbe_mac_82598EB:
3016                 /*
3017                  * For VMDq support of different descriptor types or
3018                  * buffer sizes through the use of multiple SRRCTL
3019                  * registers, RDRXCTL.MVMEN must be set to 1
3020                  *
3021                  * also, the manual doesn't mention it clearly but DCA hints
3022                  * will only use queue 0's tags unless this bit is set.  Side
3023                  * effects of setting this bit are only that SRRCTL must be
3024                  * fully programmed [0..15]
3025                  */
3026                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3027                 break;
3028         case ixgbe_mac_82599EB:
3029                 /* Disable RSC for ACK packets */
3030                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3031                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3032                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3033                 /* hardware requires some bits to be set by default */
3034                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3035                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3036                 break;
3037         default:
3038                 /* We should do nothing since we don't know this hardware */
3039                 return;
3040         }
3041
3042         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3043 }
3044
3045 /**
3046  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3047  * @adapter: board private structure
3048  *
3049  * Configure the Rx unit of the MAC after a reset.
3050  **/
3051 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3052 {
3053         struct ixgbe_hw *hw = &adapter->hw;
3054         int i;
3055         u32 rxctrl;
3056
3057         /* disable receives while setting up the descriptors */
3058         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3059         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3060
3061         ixgbe_setup_psrtype(adapter);
3062         ixgbe_setup_rdrxctl(adapter);
3063
3064         /* Program registers for the distribution of queues */
3065         ixgbe_setup_mrqc(adapter);
3066
3067         ixgbe_set_uta(adapter);
3068
3069         /* set_rx_buffer_len must be called before ring initialization */
3070         ixgbe_set_rx_buffer_len(adapter);
3071
3072         /*
3073          * Setup the HW Rx Head and Tail Descriptor Pointers and
3074          * the Base and Length of the Rx Descriptor Ring
3075          */
3076         for (i = 0; i < adapter->num_rx_queues; i++)
3077                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3078
3079         /* disable drop enable for 82598 parts */
3080         if (hw->mac.type == ixgbe_mac_82598EB)
3081                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3082
3083         /* enable all receives */
3084         rxctrl |= IXGBE_RXCTRL_RXEN;
3085         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3086 }
3087
3088 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3089 {
3090         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3091         struct ixgbe_hw *hw = &adapter->hw;
3092         int pool_ndx = adapter->num_vfs;
3093
3094         /* add VID to filter table */
3095         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3096         set_bit(vid, adapter->active_vlans);
3097 }
3098
3099 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3100 {
3101         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3102         struct ixgbe_hw *hw = &adapter->hw;
3103         int pool_ndx = adapter->num_vfs;
3104
3105         /* remove VID from filter table */
3106         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3107         clear_bit(vid, adapter->active_vlans);
3108 }
3109
3110 /**
3111  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3112  * @adapter: driver data
3113  */
3114 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3115 {
3116         struct ixgbe_hw *hw = &adapter->hw;
3117         u32 vlnctrl;
3118
3119         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3120         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3121         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3122 }
3123
3124 /**
3125  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3126  * @adapter: driver data
3127  */
3128 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3129 {
3130         struct ixgbe_hw *hw = &adapter->hw;
3131         u32 vlnctrl;
3132
3133         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3134         vlnctrl |= IXGBE_VLNCTRL_VFE;
3135         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3136         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3137 }
3138
3139 /**
3140  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3141  * @adapter: driver data
3142  */
3143 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3144 {
3145         struct ixgbe_hw *hw = &adapter->hw;
3146         u32 vlnctrl;
3147         int i, j;
3148
3149         switch (hw->mac.type) {
3150         case ixgbe_mac_82598EB:
3151                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3152                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3153                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3154                 break;
3155         case ixgbe_mac_82599EB:
3156                 for (i = 0; i < adapter->num_rx_queues; i++) {
3157                         j = adapter->rx_ring[i]->reg_idx;
3158                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3159                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3160                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3161                 }
3162                 break;
3163         default:
3164                 break;
3165         }
3166 }
3167
3168 /**
3169  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3170  * @adapter: driver data
3171  */
3172 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3173 {
3174         struct ixgbe_hw *hw = &adapter->hw;
3175         u32 vlnctrl;
3176         int i, j;
3177
3178         switch (hw->mac.type) {
3179         case ixgbe_mac_82598EB:
3180                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3181                 vlnctrl |= IXGBE_VLNCTRL_VME;
3182                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3183                 break;
3184         case ixgbe_mac_82599EB:
3185                 for (i = 0; i < adapter->num_rx_queues; i++) {
3186                         j = adapter->rx_ring[i]->reg_idx;
3187                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3188                         vlnctrl |= IXGBE_RXDCTL_VME;
3189                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3190                 }
3191                 break;
3192         default:
3193                 break;
3194         }
3195 }
3196
3197 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3198 {
3199         u16 vid;
3200
3201         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3202
3203         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3204                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3205 }
3206
3207 /**
3208  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3209  * @netdev: network interface device structure
3210  *
3211  * Writes unicast address list to the RAR table.
3212  * Returns: -ENOMEM on failure/insufficient address space
3213  *                0 on no addresses written
3214  *                X on writing X addresses to the RAR table
3215  **/
3216 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3217 {
3218         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3219         struct ixgbe_hw *hw = &adapter->hw;
3220         unsigned int vfn = adapter->num_vfs;
3221         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3222         int count = 0;
3223
3224         /* return ENOMEM indicating insufficient memory for addresses */
3225         if (netdev_uc_count(netdev) > rar_entries)
3226                 return -ENOMEM;
3227
3228         if (!netdev_uc_empty(netdev) && rar_entries) {
3229                 struct netdev_hw_addr *ha;
3230                 /* return error if we do not support writing to RAR table */
3231                 if (!hw->mac.ops.set_rar)
3232                         return -ENOMEM;
3233
3234                 netdev_for_each_uc_addr(ha, netdev) {
3235                         if (!rar_entries)
3236                                 break;
3237                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3238                                             vfn, IXGBE_RAH_AV);
3239                         count++;
3240                 }
3241         }
3242         /* write the addresses in reverse order to avoid write combining */
3243         for (; rar_entries > 0 ; rar_entries--)
3244                 hw->mac.ops.clear_rar(hw, rar_entries);
3245
3246         return count;
3247 }
3248
3249 /**
3250  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3251  * @netdev: network interface device structure
3252  *
3253  * The set_rx_method entry point is called whenever the unicast/multicast
3254  * address list or the network interface flags are updated.  This routine is
3255  * responsible for configuring the hardware for proper unicast, multicast and
3256  * promiscuous mode.
3257  **/
3258 void ixgbe_set_rx_mode(struct net_device *netdev)
3259 {
3260         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3261         struct ixgbe_hw *hw = &adapter->hw;
3262         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3263         int count;
3264
3265         /* Check for Promiscuous and All Multicast modes */
3266
3267         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3268
3269         /* set all bits that we expect to always be set */
3270         fctrl |= IXGBE_FCTRL_BAM;
3271         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3272         fctrl |= IXGBE_FCTRL_PMCF;
3273
3274         /* clear the bits we are changing the status of */
3275         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3276
3277         if (netdev->flags & IFF_PROMISC) {
3278                 hw->addr_ctrl.user_set_promisc = true;
3279                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3280                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3281                 /* don't hardware filter vlans in promisc mode */
3282                 ixgbe_vlan_filter_disable(adapter);
3283         } else {
3284                 if (netdev->flags & IFF_ALLMULTI) {
3285                         fctrl |= IXGBE_FCTRL_MPE;
3286                         vmolr |= IXGBE_VMOLR_MPE;
3287                 } else {
3288                         /*
3289                          * Write addresses to the MTA, if the attempt fails
3290                          * then we should just turn on promiscous mode so
3291                          * that we can at least receive multicast traffic
3292                          */
3293                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3294                         vmolr |= IXGBE_VMOLR_ROMPE;
3295                 }
3296                 ixgbe_vlan_filter_enable(adapter);
3297                 hw->addr_ctrl.user_set_promisc = false;
3298                 /*
3299                  * Write addresses to available RAR registers, if there is not
3300                  * sufficient space to store all the addresses then enable
3301                  * unicast promiscous mode
3302                  */
3303                 count = ixgbe_write_uc_addr_list(netdev);
3304                 if (count < 0) {
3305                         fctrl |= IXGBE_FCTRL_UPE;
3306                         vmolr |= IXGBE_VMOLR_ROPE;
3307                 }
3308         }
3309
3310         if (adapter->num_vfs) {
3311                 ixgbe_restore_vf_multicasts(adapter);
3312                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3313                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3314                            IXGBE_VMOLR_ROPE);
3315                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3316         }
3317
3318         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3319
3320         if (netdev->features & NETIF_F_HW_VLAN_RX)
3321                 ixgbe_vlan_strip_enable(adapter);
3322         else
3323                 ixgbe_vlan_strip_disable(adapter);
3324 }
3325
3326 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3327 {
3328         int q_idx;
3329         struct ixgbe_q_vector *q_vector;
3330         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3331
3332         /* legacy and MSI only use one vector */
3333         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3334                 q_vectors = 1;
3335
3336         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3337                 struct napi_struct *napi;
3338                 q_vector = adapter->q_vector[q_idx];
3339                 napi = &q_vector->napi;
3340                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3341                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3342                                 if (q_vector->txr_count == 1)
3343                                         napi->poll = &ixgbe_clean_txonly;
3344                                 else if (q_vector->rxr_count == 1)
3345                                         napi->poll = &ixgbe_clean_rxonly;
3346                         }
3347                 }
3348
3349                 napi_enable(napi);
3350         }
3351 }
3352
3353 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3354 {
3355         int q_idx;
3356         struct ixgbe_q_vector *q_vector;
3357         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3358
3359         /* legacy and MSI only use one vector */
3360         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3361                 q_vectors = 1;
3362
3363         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3364                 q_vector = adapter->q_vector[q_idx];
3365                 napi_disable(&q_vector->napi);
3366         }
3367 }
3368
3369 #ifdef CONFIG_IXGBE_DCB
3370 /*
3371  * ixgbe_configure_dcb - Configure DCB hardware
3372  * @adapter: ixgbe adapter struct
3373  *
3374  * This is called by the driver on open to configure the DCB hardware.
3375  * This is also called by the gennetlink interface when reconfiguring
3376  * the DCB state.
3377  */
3378 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3379 {
3380         struct ixgbe_hw *hw = &adapter->hw;
3381         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3382
3383         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3384                 if (hw->mac.type == ixgbe_mac_82598EB)
3385                         netif_set_gso_max_size(adapter->netdev, 65536);
3386                 return;
3387         }
3388
3389         if (hw->mac.type == ixgbe_mac_82598EB)
3390                 netif_set_gso_max_size(adapter->netdev, 32768);
3391
3392 #ifdef CONFIG_FCOE
3393         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3394                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3395 #endif
3396
3397         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3398                                         DCB_TX_CONFIG);
3399         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3400                                         DCB_RX_CONFIG);
3401
3402         /* Enable VLAN tag insert/strip */
3403         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3404
3405         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3406
3407         /* reconfigure the hardware */
3408         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3409 }
3410
3411 #endif
3412 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3413 {
3414         struct net_device *netdev = adapter->netdev;
3415         struct ixgbe_hw *hw = &adapter->hw;
3416         int i;
3417
3418 #ifdef CONFIG_IXGBE_DCB
3419         ixgbe_configure_dcb(adapter);
3420 #endif
3421
3422         ixgbe_set_rx_mode(netdev);
3423         ixgbe_restore_vlan(adapter);
3424
3425 #ifdef IXGBE_FCOE
3426         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3427                 ixgbe_configure_fcoe(adapter);
3428
3429 #endif /* IXGBE_FCOE */
3430         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3431                 for (i = 0; i < adapter->num_tx_queues; i++)
3432                         adapter->tx_ring[i]->atr_sample_rate =
3433                                                        adapter->atr_sample_rate;
3434                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3435         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3436                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3437         }
3438         ixgbe_configure_virtualization(adapter);
3439
3440         ixgbe_configure_tx(adapter);
3441         ixgbe_configure_rx(adapter);
3442 }
3443
3444 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3445 {
3446         switch (hw->phy.type) {
3447         case ixgbe_phy_sfp_avago:
3448         case ixgbe_phy_sfp_ftl:
3449         case ixgbe_phy_sfp_intel:
3450         case ixgbe_phy_sfp_unknown:
3451         case ixgbe_phy_sfp_passive_tyco:
3452         case ixgbe_phy_sfp_passive_unknown:
3453         case ixgbe_phy_sfp_active_unknown:
3454         case ixgbe_phy_sfp_ftl_active:
3455                 return true;
3456         default:
3457                 return false;
3458         }
3459 }
3460
3461 /**
3462  * ixgbe_sfp_link_config - set up SFP+ link
3463  * @adapter: pointer to private adapter struct
3464  **/
3465 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3466 {
3467         struct ixgbe_hw *hw = &adapter->hw;
3468
3469                 if (hw->phy.multispeed_fiber) {
3470                         /*
3471                          * In multispeed fiber setups, the device may not have
3472                          * had a physical connection when the driver loaded.
3473                          * If that's the case, the initial link configuration
3474                          * couldn't get the MAC into 10G or 1G mode, so we'll
3475                          * never have a link status change interrupt fire.
3476                          * We need to try and force an autonegotiation
3477                          * session, then bring up link.
3478                          */
3479                         hw->mac.ops.setup_sfp(hw);
3480                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3481                                 schedule_work(&adapter->multispeed_fiber_task);
3482                 } else {
3483                         /*
3484                          * Direct Attach Cu and non-multispeed fiber modules
3485                          * still need to be configured properly prior to
3486                          * attempting link.
3487                          */
3488                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3489                                 schedule_work(&adapter->sfp_config_module_task);
3490                 }
3491 }
3492
3493 /**
3494  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3495  * @hw: pointer to private hardware struct
3496  *
3497  * Returns 0 on success, negative on failure
3498  **/
3499 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3500 {
3501         u32 autoneg;
3502         bool negotiation, link_up = false;
3503         u32 ret = IXGBE_ERR_LINK_SETUP;
3504
3505         if (hw->mac.ops.check_link)
3506                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3507
3508         if (ret)
3509                 goto link_cfg_out;
3510
3511         if (hw->mac.ops.get_link_capabilities)
3512                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3513                                                         &negotiation);
3514         if (ret)
3515                 goto link_cfg_out;
3516
3517         if (hw->mac.ops.setup_link)
3518                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3519 link_cfg_out:
3520         return ret;
3521 }
3522
3523 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3524 {
3525         struct ixgbe_hw *hw = &adapter->hw;
3526         u32 gpie = 0;
3527
3528         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3529                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3530                        IXGBE_GPIE_OCD;
3531                 gpie |= IXGBE_GPIE_EIAME;
3532                 /*
3533                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3534                  * this saves a register write for every interrupt
3535                  */
3536                 switch (hw->mac.type) {
3537                 case ixgbe_mac_82598EB:
3538                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3539                         break;
3540                 default:
3541                 case ixgbe_mac_82599EB:
3542                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3543                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3544                         break;
3545                 }
3546         } else {
3547                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3548                  * specifically only auto mask tx and rx interrupts */
3549                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3550         }
3551
3552         /* XXX: to interrupt immediately for EICS writes, enable this */
3553         /* gpie |= IXGBE_GPIE_EIMEN; */
3554
3555         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3556                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3557                 gpie |= IXGBE_GPIE_VTMODE_64;
3558         }
3559
3560         /* Enable fan failure interrupt */
3561         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3562                 gpie |= IXGBE_SDP1_GPIEN;
3563
3564         if (hw->mac.type == ixgbe_mac_82599EB)
3565                 gpie |= IXGBE_SDP1_GPIEN;
3566                 gpie |= IXGBE_SDP2_GPIEN;
3567
3568         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3569 }
3570
3571 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3572 {
3573         struct ixgbe_hw *hw = &adapter->hw;
3574         int err;
3575         u32 ctrl_ext;
3576
3577         ixgbe_get_hw_control(adapter);
3578         ixgbe_setup_gpie(adapter);
3579
3580         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3581                 ixgbe_configure_msix(adapter);
3582         else
3583                 ixgbe_configure_msi_and_legacy(adapter);
3584
3585         /* enable the optics */
3586         if (hw->phy.multispeed_fiber)
3587                 hw->mac.ops.enable_tx_laser(hw);
3588
3589         clear_bit(__IXGBE_DOWN, &adapter->state);
3590         ixgbe_napi_enable_all(adapter);
3591
3592         if (ixgbe_is_sfp(hw)) {
3593                 ixgbe_sfp_link_config(adapter);
3594         } else {
3595                 err = ixgbe_non_sfp_link_config(hw);
3596                 if (err)
3597                         e_err(probe, "link_config FAILED %d\n", err);
3598         }
3599
3600         /* clear any pending interrupts, may auto mask */
3601         IXGBE_READ_REG(hw, IXGBE_EICR);
3602         ixgbe_irq_enable(adapter, true, true);
3603
3604         /*
3605          * If this adapter has a fan, check to see if we had a failure
3606          * before we enabled the interrupt.
3607          */
3608         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3609                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3610                 if (esdp & IXGBE_ESDP_SDP1)
3611                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3612         }
3613
3614         /*
3615          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3616          * arrived before interrupts were enabled but after probe.  Such
3617          * devices wouldn't have their type identified yet. We need to
3618          * kick off the SFP+ module setup first, then try to bring up link.
3619          * If we're not hot-pluggable SFP+, we just need to configure link
3620          * and bring it up.
3621          */
3622         if (hw->phy.type == ixgbe_phy_unknown)
3623                 schedule_work(&adapter->sfp_config_module_task);
3624
3625         /* enable transmits */
3626         netif_tx_start_all_queues(adapter->netdev);
3627
3628         /* bring the link up in the watchdog, this could race with our first
3629          * link up interrupt but shouldn't be a problem */
3630         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3631         adapter->link_check_timeout = jiffies;
3632         mod_timer(&adapter->watchdog_timer, jiffies);
3633
3634         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3635         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3636         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3637         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3638
3639         return 0;
3640 }
3641
3642 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3643 {
3644         WARN_ON(in_interrupt());
3645         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3646                 msleep(1);
3647         ixgbe_down(adapter);
3648         /*
3649          * If SR-IOV enabled then wait a bit before bringing the adapter
3650          * back up to give the VFs time to respond to the reset.  The
3651          * two second wait is based upon the watchdog timer cycle in
3652          * the VF driver.
3653          */
3654         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3655                 msleep(2000);
3656         ixgbe_up(adapter);
3657         clear_bit(__IXGBE_RESETTING, &adapter->state);
3658 }
3659
3660 int ixgbe_up(struct ixgbe_adapter *adapter)
3661 {
3662         /* hardware has been reset, we need to reload some things */
3663         ixgbe_configure(adapter);
3664
3665         return ixgbe_up_complete(adapter);
3666 }
3667
3668 void ixgbe_reset(struct ixgbe_adapter *adapter)
3669 {
3670         struct ixgbe_hw *hw = &adapter->hw;
3671         int err;
3672
3673         err = hw->mac.ops.init_hw(hw);
3674         switch (err) {
3675         case 0:
3676         case IXGBE_ERR_SFP_NOT_PRESENT:
3677                 break;
3678         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3679                 e_dev_err("master disable timed out\n");
3680                 break;
3681         case IXGBE_ERR_EEPROM_VERSION:
3682                 /* We are running on a pre-production device, log a warning */
3683                 e_dev_warn("This device is a pre-production adapter/LOM. "
3684                            "Please be aware there may be issuesassociated with "
3685                            "your hardware.  If you are experiencing problems "
3686                            "please contact your Intel or hardware "
3687                            "representative who provided you with this "
3688                            "hardware.\n");
3689                 break;
3690         default:
3691                 e_dev_err("Hardware Error: %d\n", err);
3692         }
3693
3694         /* reprogram the RAR[0] in case user changed it. */
3695         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3696                             IXGBE_RAH_AV);
3697 }
3698
3699 /**
3700  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3701  * @rx_ring: ring to free buffers from
3702  **/
3703 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3704 {
3705         struct device *dev = rx_ring->dev;
3706         unsigned long size;
3707         u16 i;
3708
3709         /* ring already cleared, nothing to do */
3710         if (!rx_ring->rx_buffer_info)
3711                 return;
3712
3713         /* Free all the Rx ring sk_buffs */
3714         for (i = 0; i < rx_ring->count; i++) {
3715                 struct ixgbe_rx_buffer *rx_buffer_info;
3716
3717                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3718                 if (rx_buffer_info->dma) {
3719                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3720                                          rx_ring->rx_buf_len,
3721                                          DMA_FROM_DEVICE);
3722                         rx_buffer_info->dma = 0;
3723                 }
3724                 if (rx_buffer_info->skb) {
3725                         struct sk_buff *skb = rx_buffer_info->skb;
3726                         rx_buffer_info->skb = NULL;
3727                         do {
3728                                 struct sk_buff *this = skb;
3729                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3730                                         dma_unmap_single(dev,
3731                                                          IXGBE_RSC_CB(this)->dma,
3732                                                          rx_ring->rx_buf_len,
3733                                                          DMA_FROM_DEVICE);
3734                                         IXGBE_RSC_CB(this)->dma = 0;
3735                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3736                                 }
3737                                 skb = skb->prev;
3738                                 dev_kfree_skb(this);
3739                         } while (skb);
3740                 }
3741                 if (!rx_buffer_info->page)
3742                         continue;
3743                 if (rx_buffer_info->page_dma) {
3744                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3745                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3746                         rx_buffer_info->page_dma = 0;
3747                 }
3748                 put_page(rx_buffer_info->page);
3749                 rx_buffer_info->page = NULL;
3750                 rx_buffer_info->page_offset = 0;
3751         }
3752
3753         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3754         memset(rx_ring->rx_buffer_info, 0, size);
3755
3756         /* Zero out the descriptor ring */
3757         memset(rx_ring->desc, 0, rx_ring->size);
3758
3759         rx_ring->next_to_clean = 0;
3760         rx_ring->next_to_use = 0;
3761 }
3762
3763 /**
3764  * ixgbe_clean_tx_ring - Free Tx Buffers
3765  * @tx_ring: ring to be cleaned
3766  **/
3767 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3768 {
3769         struct ixgbe_tx_buffer *tx_buffer_info;
3770         unsigned long size;
3771         u16 i;
3772
3773         /* ring already cleared, nothing to do */
3774         if (!tx_ring->tx_buffer_info)
3775                 return;
3776
3777         /* Free all the Tx ring sk_buffs */
3778         for (i = 0; i < tx_ring->count; i++) {
3779                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3780                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3781         }
3782
3783         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3784         memset(tx_ring->tx_buffer_info, 0, size);
3785
3786         /* Zero out the descriptor ring */
3787         memset(tx_ring->desc, 0, tx_ring->size);
3788
3789         tx_ring->next_to_use = 0;
3790         tx_ring->next_to_clean = 0;
3791 }
3792
3793 /**
3794  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3795  * @adapter: board private structure
3796  **/
3797 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3798 {
3799         int i;
3800
3801         for (i = 0; i < adapter->num_rx_queues; i++)
3802                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3803 }
3804
3805 /**
3806  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3807  * @adapter: board private structure
3808  **/
3809 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3810 {
3811         int i;
3812
3813         for (i = 0; i < adapter->num_tx_queues; i++)
3814                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3815 }
3816
3817 void ixgbe_down(struct ixgbe_adapter *adapter)
3818 {
3819         struct net_device *netdev = adapter->netdev;
3820         struct ixgbe_hw *hw = &adapter->hw;
3821         u32 rxctrl;
3822         u32 txdctl;
3823         int i, j;
3824         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3825
3826         /* signal that we are down to the interrupt handler */
3827         set_bit(__IXGBE_DOWN, &adapter->state);
3828
3829         /* disable receive for all VFs and wait one second */
3830         if (adapter->num_vfs) {
3831                 /* ping all the active vfs to let them know we are going down */
3832                 ixgbe_ping_all_vfs(adapter);
3833
3834                 /* Disable all VFTE/VFRE TX/RX */
3835                 ixgbe_disable_tx_rx(adapter);
3836
3837                 /* Mark all the VFs as inactive */
3838                 for (i = 0 ; i < adapter->num_vfs; i++)
3839                         adapter->vfinfo[i].clear_to_send = 0;
3840         }
3841
3842         /* disable receives */
3843         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3844         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3845
3846         IXGBE_WRITE_FLUSH(hw);
3847         msleep(10);
3848
3849         netif_tx_stop_all_queues(netdev);
3850
3851         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3852         del_timer_sync(&adapter->sfp_timer);
3853         del_timer_sync(&adapter->watchdog_timer);
3854         cancel_work_sync(&adapter->watchdog_task);
3855
3856         netif_carrier_off(netdev);
3857         netif_tx_disable(netdev);
3858
3859         ixgbe_irq_disable(adapter);
3860
3861         ixgbe_napi_disable_all(adapter);
3862
3863         /* Cleanup the affinity_hint CPU mask memory and callback */
3864         for (i = 0; i < num_q_vectors; i++) {
3865                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3866                 /* clear the affinity_mask in the IRQ descriptor */
3867                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3868                 /* release the CPU mask memory */
3869                 free_cpumask_var(q_vector->affinity_mask);
3870         }
3871
3872         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3873             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3874                 cancel_work_sync(&adapter->fdir_reinit_task);
3875
3876         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3877                 cancel_work_sync(&adapter->check_overtemp_task);
3878
3879         /* disable transmits in the hardware now that interrupts are off */
3880         for (i = 0; i < adapter->num_tx_queues; i++) {
3881                 j = adapter->tx_ring[i]->reg_idx;
3882                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3883                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3884                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3885         }
3886         /* Disable the Tx DMA engine on 82599 */
3887         if (hw->mac.type == ixgbe_mac_82599EB)
3888                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3889                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3890                                  ~IXGBE_DMATXCTL_TE));
3891
3892         /* power down the optics */
3893         if (hw->phy.multispeed_fiber)
3894                 hw->mac.ops.disable_tx_laser(hw);
3895
3896         /* clear n-tuple filters that are cached */
3897         ethtool_ntuple_flush(netdev);
3898
3899         if (!pci_channel_offline(adapter->pdev))
3900                 ixgbe_reset(adapter);
3901         ixgbe_clean_all_tx_rings(adapter);
3902         ixgbe_clean_all_rx_rings(adapter);
3903
3904 #ifdef CONFIG_IXGBE_DCA
3905         /* since we reset the hardware DCA settings were cleared */
3906         ixgbe_setup_dca(adapter);
3907 #endif
3908 }
3909
3910 /**
3911  * ixgbe_poll - NAPI Rx polling callback
3912  * @napi: structure for representing this polling device
3913  * @budget: how many packets driver is allowed to clean
3914  *
3915  * This function is used for legacy and MSI, NAPI mode
3916  **/
3917 static int ixgbe_poll(struct napi_struct *napi, int budget)
3918 {
3919         struct ixgbe_q_vector *q_vector =
3920                                 container_of(napi, struct ixgbe_q_vector, napi);
3921         struct ixgbe_adapter *adapter = q_vector->adapter;
3922         int tx_clean_complete, work_done = 0;
3923
3924 #ifdef CONFIG_IXGBE_DCA
3925         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3926                 ixgbe_update_dca(q_vector);
3927 #endif
3928
3929         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3930         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3931
3932         if (!tx_clean_complete)
3933                 work_done = budget;
3934
3935         /* If budget not fully consumed, exit the polling mode */
3936         if (work_done < budget) {
3937                 napi_complete(napi);
3938                 if (adapter->rx_itr_setting & 1)
3939                         ixgbe_set_itr(adapter);
3940                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3941                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3942         }
3943         return work_done;
3944 }
3945
3946 /**
3947  * ixgbe_tx_timeout - Respond to a Tx Hang
3948  * @netdev: network interface device structure
3949  **/
3950 static void ixgbe_tx_timeout(struct net_device *netdev)
3951 {
3952         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3953
3954         /* Do the reset outside of interrupt context */
3955         schedule_work(&adapter->reset_task);
3956 }
3957
3958 static void ixgbe_reset_task(struct work_struct *work)
3959 {
3960         struct ixgbe_adapter *adapter;
3961         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3962
3963         /* If we're already down or resetting, just bail */
3964         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3965             test_bit(__IXGBE_RESETTING, &adapter->state))
3966                 return;
3967
3968         adapter->tx_timeout_count++;
3969
3970         ixgbe_dump(adapter);
3971         netdev_err(adapter->netdev, "Reset adapter\n");
3972         ixgbe_reinit_locked(adapter);
3973 }
3974
3975 #ifdef CONFIG_IXGBE_DCB
3976 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3977 {
3978         bool ret = false;
3979         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3980
3981         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3982                 return ret;
3983
3984         f->mask = 0x7 << 3;
3985         adapter->num_rx_queues = f->indices;
3986         adapter->num_tx_queues = f->indices;
3987         ret = true;
3988
3989         return ret;
3990 }
3991 #endif
3992
3993 /**
3994  * ixgbe_set_rss_queues: Allocate queues for RSS
3995  * @adapter: board private structure to initialize
3996  *
3997  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3998  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3999  *
4000  **/
4001 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4002 {
4003         bool ret = false;
4004         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4005
4006         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4007                 f->mask = 0xF;
4008                 adapter->num_rx_queues = f->indices;
4009                 adapter->num_tx_queues = f->indices;
4010                 ret = true;
4011         } else {
4012                 ret = false;
4013         }
4014
4015         return ret;
4016 }
4017
4018 /**
4019  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4020  * @adapter: board private structure to initialize
4021  *
4022  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4023  * to the original CPU that initiated the Tx session.  This runs in addition
4024  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4025  * Rx load across CPUs using RSS.
4026  *
4027  **/
4028 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4029 {
4030         bool ret = false;
4031         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4032
4033         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4034         f_fdir->mask = 0;
4035
4036         /* Flow Director must have RSS enabled */
4037         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4038             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4039              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4040                 adapter->num_tx_queues = f_fdir->indices;
4041                 adapter->num_rx_queues = f_fdir->indices;
4042                 ret = true;
4043         } else {
4044                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4045                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4046         }
4047         return ret;
4048 }
4049
4050 #ifdef IXGBE_FCOE
4051 /**
4052  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4053  * @adapter: board private structure to initialize
4054  *
4055  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4056  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4057  * rx queues out of the max number of rx queues, instead, it is used as the
4058  * index of the first rx queue used by FCoE.
4059  *
4060  **/
4061 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4062 {
4063         bool ret = false;
4064         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4065
4066         f->indices = min((int)num_online_cpus(), f->indices);
4067         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4068                 adapter->num_rx_queues = 1;
4069                 adapter->num_tx_queues = 1;
4070 #ifdef CONFIG_IXGBE_DCB
4071                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4072                         e_info(probe, "FCoE enabled with DCB\n");
4073                         ixgbe_set_dcb_queues(adapter);
4074                 }
4075 #endif
4076                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4077                         e_info(probe, "FCoE enabled with RSS\n");
4078                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4079                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4080                                 ixgbe_set_fdir_queues(adapter);
4081                         else
4082                                 ixgbe_set_rss_queues(adapter);
4083                 }
4084                 /* adding FCoE rx rings to the end */
4085                 f->mask = adapter->num_rx_queues;
4086                 adapter->num_rx_queues += f->indices;
4087                 adapter->num_tx_queues += f->indices;
4088
4089                 ret = true;
4090         }
4091
4092         return ret;
4093 }
4094
4095 #endif /* IXGBE_FCOE */
4096 /**
4097  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4098  * @adapter: board private structure to initialize
4099  *
4100  * IOV doesn't actually use anything, so just NAK the
4101  * request for now and let the other queue routines
4102  * figure out what to do.
4103  */
4104 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4105 {
4106         return false;
4107 }
4108
4109 /*
4110  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4111  * @adapter: board private structure to initialize
4112  *
4113  * This is the top level queue allocation routine.  The order here is very
4114  * important, starting with the "most" number of features turned on at once,
4115  * and ending with the smallest set of features.  This way large combinations
4116  * can be allocated if they're turned on, and smaller combinations are the
4117  * fallthrough conditions.
4118  *
4119  **/
4120 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4121 {
4122         /* Start with base case */
4123         adapter->num_rx_queues = 1;
4124         adapter->num_tx_queues = 1;
4125         adapter->num_rx_pools = adapter->num_rx_queues;
4126         adapter->num_rx_queues_per_pool = 1;
4127
4128         if (ixgbe_set_sriov_queues(adapter))
4129                 goto done;
4130
4131 #ifdef IXGBE_FCOE
4132         if (ixgbe_set_fcoe_queues(adapter))
4133                 goto done;
4134
4135 #endif /* IXGBE_FCOE */
4136 #ifdef CONFIG_IXGBE_DCB
4137         if (ixgbe_set_dcb_queues(adapter))
4138                 goto done;
4139
4140 #endif
4141         if (ixgbe_set_fdir_queues(adapter))
4142                 goto done;
4143
4144         if (ixgbe_set_rss_queues(adapter))
4145                 goto done;
4146
4147         /* fallback to base case */
4148         adapter->num_rx_queues = 1;
4149         adapter->num_tx_queues = 1;
4150
4151 done:
4152         /* Notify the stack of the (possibly) reduced queue counts. */
4153         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4154         return netif_set_real_num_rx_queues(adapter->netdev,
4155                                             adapter->num_rx_queues);
4156 }
4157
4158 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4159                                        int vectors)
4160 {
4161         int err, vector_threshold;
4162
4163         /* We'll want at least 3 (vector_threshold):
4164          * 1) TxQ[0] Cleanup
4165          * 2) RxQ[0] Cleanup
4166          * 3) Other (Link Status Change, etc.)
4167          * 4) TCP Timer (optional)
4168          */
4169         vector_threshold = MIN_MSIX_COUNT;
4170
4171         /* The more we get, the more we will assign to Tx/Rx Cleanup
4172          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4173          * Right now, we simply care about how many we'll get; we'll
4174          * set them up later while requesting irq's.
4175          */
4176         while (vectors >= vector_threshold) {
4177                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4178                                       vectors);
4179                 if (!err) /* Success in acquiring all requested vectors. */
4180                         break;
4181                 else if (err < 0)
4182                         vectors = 0; /* Nasty failure, quit now */
4183                 else /* err == number of vectors we should try again with */
4184                         vectors = err;
4185         }
4186
4187         if (vectors < vector_threshold) {
4188                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4189                  * This just means we'll go with either a single MSI
4190                  * vector or fall back to legacy interrupts.
4191                  */
4192                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4193                              "Unable to allocate MSI-X interrupts\n");
4194                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4195                 kfree(adapter->msix_entries);
4196                 adapter->msix_entries = NULL;
4197         } else {
4198                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4199                 /*
4200                  * Adjust for only the vectors we'll use, which is minimum
4201                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4202                  * vectors we were allocated.
4203                  */
4204                 adapter->num_msix_vectors = min(vectors,
4205                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4206         }
4207 }
4208
4209 /**
4210  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4211  * @adapter: board private structure to initialize
4212  *
4213  * Cache the descriptor ring offsets for RSS to the assigned rings.
4214  *
4215  **/
4216 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4217 {
4218         int i;
4219         bool ret = false;
4220
4221         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4222                 for (i = 0; i < adapter->num_rx_queues; i++)
4223                         adapter->rx_ring[i]->reg_idx = i;
4224                 for (i = 0; i < adapter->num_tx_queues; i++)
4225                         adapter->tx_ring[i]->reg_idx = i;
4226                 ret = true;
4227         } else {
4228                 ret = false;
4229         }
4230
4231         return ret;
4232 }
4233
4234 #ifdef CONFIG_IXGBE_DCB
4235 /**
4236  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4237  * @adapter: board private structure to initialize
4238  *
4239  * Cache the descriptor ring offsets for DCB to the assigned rings.
4240  *
4241  **/
4242 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4243 {
4244         int i;
4245         bool ret = false;
4246         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4247
4248         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4249                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4250                         /* the number of queues is assumed to be symmetric */
4251                         for (i = 0; i < dcb_i; i++) {
4252                                 adapter->rx_ring[i]->reg_idx = i << 3;
4253                                 adapter->tx_ring[i]->reg_idx = i << 2;
4254                         }
4255                         ret = true;
4256                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4257                         if (dcb_i == 8) {
4258                                 /*
4259                                  * Tx TC0 starts at: descriptor queue 0
4260                                  * Tx TC1 starts at: descriptor queue 32
4261                                  * Tx TC2 starts at: descriptor queue 64
4262                                  * Tx TC3 starts at: descriptor queue 80
4263                                  * Tx TC4 starts at: descriptor queue 96
4264                                  * Tx TC5 starts at: descriptor queue 104
4265                                  * Tx TC6 starts at: descriptor queue 112
4266                                  * Tx TC7 starts at: descriptor queue 120
4267                                  *
4268                                  * Rx TC0-TC7 are offset by 16 queues each
4269                                  */
4270                                 for (i = 0; i < 3; i++) {
4271                                         adapter->tx_ring[i]->reg_idx = i << 5;
4272                                         adapter->rx_ring[i]->reg_idx = i << 4;
4273                                 }
4274                                 for ( ; i < 5; i++) {
4275                                         adapter->tx_ring[i]->reg_idx =
4276                                                                  ((i + 2) << 4);
4277                                         adapter->rx_ring[i]->reg_idx = i << 4;
4278                                 }
4279                                 for ( ; i < dcb_i; i++) {
4280                                         adapter->tx_ring[i]->reg_idx =
4281                                                                  ((i + 8) << 3);
4282                                         adapter->rx_ring[i]->reg_idx = i << 4;
4283                                 }
4284
4285                                 ret = true;
4286                         } else if (dcb_i == 4) {
4287                                 /*
4288                                  * Tx TC0 starts at: descriptor queue 0
4289                                  * Tx TC1 starts at: descriptor queue 64
4290                                  * Tx TC2 starts at: descriptor queue 96
4291                                  * Tx TC3 starts at: descriptor queue 112
4292                                  *
4293                                  * Rx TC0-TC3 are offset by 32 queues each
4294                                  */
4295                                 adapter->tx_ring[0]->reg_idx = 0;
4296                                 adapter->tx_ring[1]->reg_idx = 64;
4297                                 adapter->tx_ring[2]->reg_idx = 96;
4298                                 adapter->tx_ring[3]->reg_idx = 112;
4299                                 for (i = 0 ; i < dcb_i; i++)
4300                                         adapter->rx_ring[i]->reg_idx = i << 5;
4301
4302                                 ret = true;
4303                         } else {
4304                                 ret = false;
4305                         }
4306                 } else {
4307                         ret = false;
4308                 }
4309         } else {
4310                 ret = false;
4311         }
4312
4313         return ret;
4314 }
4315 #endif
4316
4317 /**
4318  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4319  * @adapter: board private structure to initialize
4320  *
4321  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4322  *
4323  **/
4324 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4325 {
4326         int i;
4327         bool ret = false;
4328
4329         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4330             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4331              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4332                 for (i = 0; i < adapter->num_rx_queues; i++)
4333                         adapter->rx_ring[i]->reg_idx = i;
4334                 for (i = 0; i < adapter->num_tx_queues; i++)
4335                         adapter->tx_ring[i]->reg_idx = i;
4336                 ret = true;
4337         }
4338
4339         return ret;
4340 }
4341
4342 #ifdef IXGBE_FCOE
4343 /**
4344  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4345  * @adapter: board private structure to initialize
4346  *
4347  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4348  *
4349  */
4350 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4351 {
4352         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4353         bool ret = false;
4354         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4355
4356         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4357 #ifdef CONFIG_IXGBE_DCB
4358                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4359                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4360
4361                         ixgbe_cache_ring_dcb(adapter);
4362                         /* find out queues in TC for FCoE */
4363                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4364                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4365                         /*
4366                          * In 82599, the number of Tx queues for each traffic
4367                          * class for both 8-TC and 4-TC modes are:
4368                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4369                          * 8 TCs:  32  32  16  16   8   8   8   8
4370                          * 4 TCs:  64  64  32  32
4371                          * We have max 8 queues for FCoE, where 8 the is
4372                          * FCoE redirection table size. If TC for FCoE is
4373                          * less than or equal to TC3, we have enough queues
4374                          * to add max of 8 queues for FCoE, so we start FCoE
4375                          * tx descriptor from the next one, i.e., reg_idx + 1.
4376                          * If TC for FCoE is above TC3, implying 8 TC mode,
4377                          * and we need 8 for FCoE, we have to take all queues
4378                          * in that traffic class for FCoE.
4379                          */
4380                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4381                                 fcoe_tx_i--;
4382                 }
4383 #endif /* CONFIG_IXGBE_DCB */
4384                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4385                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4386                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4387                                 ixgbe_cache_ring_fdir(adapter);
4388                         else
4389                                 ixgbe_cache_ring_rss(adapter);
4390
4391                         fcoe_rx_i = f->mask;
4392                         fcoe_tx_i = f->mask;
4393                 }
4394                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4395                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4396                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4397                 }
4398                 ret = true;
4399         }
4400         return ret;
4401 }
4402
4403 #endif /* IXGBE_FCOE */
4404 /**
4405  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4406  * @adapter: board private structure to initialize
4407  *
4408  * SR-IOV doesn't use any descriptor rings but changes the default if
4409  * no other mapping is used.
4410  *
4411  */
4412 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4413 {
4414         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4415         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4416         if (adapter->num_vfs)
4417                 return true;
4418         else
4419                 return false;
4420 }
4421
4422 /**
4423  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4424  * @adapter: board private structure to initialize
4425  *
4426  * Once we know the feature-set enabled for the device, we'll cache
4427  * the register offset the descriptor ring is assigned to.
4428  *
4429  * Note, the order the various feature calls is important.  It must start with
4430  * the "most" features enabled at the same time, then trickle down to the
4431  * least amount of features turned on at once.
4432  **/
4433 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4434 {
4435         /* start with default case */
4436         adapter->rx_ring[0]->reg_idx = 0;
4437         adapter->tx_ring[0]->reg_idx = 0;
4438
4439         if (ixgbe_cache_ring_sriov(adapter))
4440                 return;
4441
4442 #ifdef IXGBE_FCOE
4443         if (ixgbe_cache_ring_fcoe(adapter))
4444                 return;
4445
4446 #endif /* IXGBE_FCOE */
4447 #ifdef CONFIG_IXGBE_DCB
4448         if (ixgbe_cache_ring_dcb(adapter))
4449                 return;
4450
4451 #endif
4452         if (ixgbe_cache_ring_fdir(adapter))
4453                 return;
4454
4455         if (ixgbe_cache_ring_rss(adapter))
4456                 return;
4457 }
4458
4459 /**
4460  * ixgbe_alloc_queues - Allocate memory for all rings
4461  * @adapter: board private structure to initialize
4462  *
4463  * We allocate one ring per queue at run-time since we don't know the
4464  * number of queues at compile-time.  The polling_netdev array is
4465  * intended for Multiqueue, but should work fine with a single queue.
4466  **/
4467 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4468 {
4469         int i;
4470         int rx_count;
4471         int orig_node = adapter->node;
4472
4473         for (i = 0; i < adapter->num_tx_queues; i++) {
4474                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4475                 if (orig_node == -1) {
4476                         int cur_node = next_online_node(adapter->node);
4477                         if (cur_node == MAX_NUMNODES)
4478                                 cur_node = first_online_node;
4479                         adapter->node = cur_node;
4480                 }
4481                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4482                                     adapter->node);
4483                 if (!ring)
4484                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4485                 if (!ring)
4486                         goto err_tx_ring_allocation;
4487                 ring->count = adapter->tx_ring_count;
4488                 ring->queue_index = i;
4489                 ring->dev = &adapter->pdev->dev;
4490                 ring->netdev = adapter->netdev;
4491                 ring->numa_node = adapter->node;
4492
4493                 adapter->tx_ring[i] = ring;
4494         }
4495
4496         /* Restore the adapter's original node */
4497         adapter->node = orig_node;
4498
4499         rx_count = adapter->rx_ring_count;
4500         for (i = 0; i < adapter->num_rx_queues; i++) {
4501                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4502                 if (orig_node == -1) {
4503                         int cur_node = next_online_node(adapter->node);
4504                         if (cur_node == MAX_NUMNODES)
4505                                 cur_node = first_online_node;
4506                         adapter->node = cur_node;
4507                 }
4508                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4509                                     adapter->node);
4510                 if (!ring)
4511                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4512                 if (!ring)
4513                         goto err_rx_ring_allocation;
4514                 ring->count = rx_count;
4515                 ring->queue_index = i;
4516                 ring->dev = &adapter->pdev->dev;
4517                 ring->netdev = adapter->netdev;
4518                 ring->numa_node = adapter->node;
4519
4520                 adapter->rx_ring[i] = ring;
4521         }
4522
4523         /* Restore the adapter's original node */
4524         adapter->node = orig_node;
4525
4526         ixgbe_cache_ring_register(adapter);
4527
4528         return 0;
4529
4530 err_rx_ring_allocation:
4531         for (i = 0; i < adapter->num_tx_queues; i++)
4532                 kfree(adapter->tx_ring[i]);
4533 err_tx_ring_allocation:
4534         return -ENOMEM;
4535 }
4536
4537 /**
4538  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4539  * @adapter: board private structure to initialize
4540  *
4541  * Attempt to configure the interrupts using the best available
4542  * capabilities of the hardware and the kernel.
4543  **/
4544 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4545 {
4546         struct ixgbe_hw *hw = &adapter->hw;
4547         int err = 0;
4548         int vector, v_budget;
4549
4550         /*
4551          * It's easy to be greedy for MSI-X vectors, but it really
4552          * doesn't do us much good if we have a lot more vectors
4553          * than CPU's.  So let's be conservative and only ask for
4554          * (roughly) the same number of vectors as there are CPU's.
4555          */
4556         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4557                        (int)num_online_cpus()) + NON_Q_VECTORS;
4558
4559         /*
4560          * At the same time, hardware can only support a maximum of
4561          * hw.mac->max_msix_vectors vectors.  With features
4562          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4563          * descriptor queues supported by our device.  Thus, we cap it off in
4564          * those rare cases where the cpu count also exceeds our vector limit.
4565          */
4566         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4567
4568         /* A failure in MSI-X entry allocation isn't fatal, but it does
4569          * mean we disable MSI-X capabilities of the adapter. */
4570         adapter->msix_entries = kcalloc(v_budget,
4571                                         sizeof(struct msix_entry), GFP_KERNEL);
4572         if (adapter->msix_entries) {
4573                 for (vector = 0; vector < v_budget; vector++)
4574                         adapter->msix_entries[vector].entry = vector;
4575
4576                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4577
4578                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4579                         goto out;
4580         }
4581
4582         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4583         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4584         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4585         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4586         adapter->atr_sample_rate = 0;
4587         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4588                 ixgbe_disable_sriov(adapter);
4589
4590         err = ixgbe_set_num_queues(adapter);
4591         if (err)
4592                 return err;
4593
4594         err = pci_enable_msi(adapter->pdev);
4595         if (!err) {
4596                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4597         } else {
4598                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4599                              "Unable to allocate MSI interrupt, "
4600                              "falling back to legacy.  Error: %d\n", err);
4601                 /* reset err */
4602                 err = 0;
4603         }
4604
4605 out:
4606         return err;
4607 }
4608
4609 /**
4610  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4611  * @adapter: board private structure to initialize
4612  *
4613  * We allocate one q_vector per queue interrupt.  If allocation fails we
4614  * return -ENOMEM.
4615  **/
4616 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4617 {
4618         int q_idx, num_q_vectors;
4619         struct ixgbe_q_vector *q_vector;
4620         int napi_vectors;
4621         int (*poll)(struct napi_struct *, int);
4622
4623         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4624                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4625                 napi_vectors = adapter->num_rx_queues;
4626                 poll = &ixgbe_clean_rxtx_many;
4627         } else {
4628                 num_q_vectors = 1;
4629                 napi_vectors = 1;
4630                 poll = &ixgbe_poll;
4631         }
4632
4633         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4634                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4635                                         GFP_KERNEL, adapter->node);
4636                 if (!q_vector)
4637                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4638                                            GFP_KERNEL);
4639                 if (!q_vector)
4640                         goto err_out;
4641                 q_vector->adapter = adapter;
4642                 if (q_vector->txr_count && !q_vector->rxr_count)
4643                         q_vector->eitr = adapter->tx_eitr_param;
4644                 else
4645                         q_vector->eitr = adapter->rx_eitr_param;
4646                 q_vector->v_idx = q_idx;
4647                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4648                 adapter->q_vector[q_idx] = q_vector;
4649         }
4650
4651         return 0;
4652
4653 err_out:
4654         while (q_idx) {
4655                 q_idx--;
4656                 q_vector = adapter->q_vector[q_idx];
4657                 netif_napi_del(&q_vector->napi);
4658                 kfree(q_vector);
4659                 adapter->q_vector[q_idx] = NULL;
4660         }
4661         return -ENOMEM;
4662 }
4663
4664 /**
4665  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4666  * @adapter: board private structure to initialize
4667  *
4668  * This function frees the memory allocated to the q_vectors.  In addition if
4669  * NAPI is enabled it will delete any references to the NAPI struct prior
4670  * to freeing the q_vector.
4671  **/
4672 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4673 {
4674         int q_idx, num_q_vectors;
4675
4676         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4677                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4678         else
4679                 num_q_vectors = 1;
4680
4681         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4682                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4683                 adapter->q_vector[q_idx] = NULL;
4684                 netif_napi_del(&q_vector->napi);
4685                 kfree(q_vector);
4686         }
4687 }
4688
4689 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4690 {
4691         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4692                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4693                 pci_disable_msix(adapter->pdev);
4694                 kfree(adapter->msix_entries);
4695                 adapter->msix_entries = NULL;
4696         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4697                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4698                 pci_disable_msi(adapter->pdev);
4699         }
4700 }
4701
4702 /**
4703  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4704  * @adapter: board private structure to initialize
4705  *
4706  * We determine which interrupt scheme to use based on...
4707  * - Kernel support (MSI, MSI-X)
4708  *   - which can be user-defined (via MODULE_PARAM)
4709  * - Hardware queue count (num_*_queues)
4710  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4711  **/
4712 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4713 {
4714         int err;
4715
4716         /* Number of supported queues */
4717         err = ixgbe_set_num_queues(adapter);
4718         if (err)
4719                 return err;
4720
4721         err = ixgbe_set_interrupt_capability(adapter);
4722         if (err) {
4723                 e_dev_err("Unable to setup interrupt capabilities\n");
4724                 goto err_set_interrupt;
4725         }
4726
4727         err = ixgbe_alloc_q_vectors(adapter);
4728         if (err) {
4729                 e_dev_err("Unable to allocate memory for queue vectors\n");
4730                 goto err_alloc_q_vectors;
4731         }
4732
4733         err = ixgbe_alloc_queues(adapter);
4734         if (err) {
4735                 e_dev_err("Unable to allocate memory for queues\n");
4736                 goto err_alloc_queues;
4737         }
4738
4739         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4740                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4741                    adapter->num_rx_queues, adapter->num_tx_queues);
4742
4743         set_bit(__IXGBE_DOWN, &adapter->state);
4744
4745         return 0;
4746
4747 err_alloc_queues:
4748         ixgbe_free_q_vectors(adapter);
4749 err_alloc_q_vectors:
4750         ixgbe_reset_interrupt_capability(adapter);
4751 err_set_interrupt:
4752         return err;
4753 }
4754
4755 static void ring_free_rcu(struct rcu_head *head)
4756 {
4757         kfree(container_of(head, struct ixgbe_ring, rcu));
4758 }
4759
4760 /**
4761  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4762  * @adapter: board private structure to clear interrupt scheme on
4763  *
4764  * We go through and clear interrupt specific resources and reset the structure
4765  * to pre-load conditions
4766  **/
4767 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4768 {
4769         int i;
4770
4771         for (i = 0; i < adapter->num_tx_queues; i++) {
4772                 kfree(adapter->tx_ring[i]);
4773                 adapter->tx_ring[i] = NULL;
4774         }
4775         for (i = 0; i < adapter->num_rx_queues; i++) {
4776                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4777
4778                 /* ixgbe_get_stats64() might access this ring, we must wait
4779                  * a grace period before freeing it.
4780                  */
4781                 call_rcu(&ring->rcu, ring_free_rcu);
4782                 adapter->rx_ring[i] = NULL;
4783         }
4784
4785         ixgbe_free_q_vectors(adapter);
4786         ixgbe_reset_interrupt_capability(adapter);
4787 }
4788
4789 /**
4790  * ixgbe_sfp_timer - worker thread to find a missing module
4791  * @data: pointer to our adapter struct
4792  **/
4793 static void ixgbe_sfp_timer(unsigned long data)
4794 {
4795         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4796
4797         /*
4798          * Do the sfp_timer outside of interrupt context due to the
4799          * delays that sfp+ detection requires
4800          */
4801         schedule_work(&adapter->sfp_task);
4802 }
4803
4804 /**
4805  * ixgbe_sfp_task - worker thread to find a missing module
4806  * @work: pointer to work_struct containing our data
4807  **/
4808 static void ixgbe_sfp_task(struct work_struct *work)
4809 {
4810         struct ixgbe_adapter *adapter = container_of(work,
4811                                                      struct ixgbe_adapter,
4812                                                      sfp_task);
4813         struct ixgbe_hw *hw = &adapter->hw;
4814
4815         if ((hw->phy.type == ixgbe_phy_nl) &&
4816             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4817                 s32 ret = hw->phy.ops.identify_sfp(hw);
4818                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4819                         goto reschedule;
4820                 ret = hw->phy.ops.reset(hw);
4821                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4822                         e_dev_err("failed to initialize because an unsupported "
4823                                   "SFP+ module type was detected.\n");
4824                         e_dev_err("Reload the driver after installing a "
4825                                   "supported module.\n");
4826                         unregister_netdev(adapter->netdev);
4827                 } else {
4828                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4829                 }
4830                 /* don't need this routine any more */
4831                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4832         }
4833         return;
4834 reschedule:
4835         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4836                 mod_timer(&adapter->sfp_timer,
4837                           round_jiffies(jiffies + (2 * HZ)));
4838 }
4839
4840 /**
4841  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4842  * @adapter: board private structure to initialize
4843  *
4844  * ixgbe_sw_init initializes the Adapter private data structure.
4845  * Fields are initialized based on PCI device information and
4846  * OS network device settings (MTU size).
4847  **/
4848 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4849 {
4850         struct ixgbe_hw *hw = &adapter->hw;
4851         struct pci_dev *pdev = adapter->pdev;
4852         struct net_device *dev = adapter->netdev;
4853         unsigned int rss;
4854 #ifdef CONFIG_IXGBE_DCB
4855         int j;
4856         struct tc_configuration *tc;
4857 #endif
4858         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4859
4860         /* PCI config space info */
4861
4862         hw->vendor_id = pdev->vendor;
4863         hw->device_id = pdev->device;
4864         hw->revision_id = pdev->revision;
4865         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4866         hw->subsystem_device_id = pdev->subsystem_device;
4867
4868         /* Set capability flags */
4869         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4870         adapter->ring_feature[RING_F_RSS].indices = rss;
4871         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4872         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4873         if (hw->mac.type == ixgbe_mac_82598EB) {
4874                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4875                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4876                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4877         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4878                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4879                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4880                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4881                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4882                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4883                 if (dev->features & NETIF_F_NTUPLE) {
4884                         /* Flow Director perfect filter enabled */
4885                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4886                         adapter->atr_sample_rate = 0;
4887                         spin_lock_init(&adapter->fdir_perfect_lock);
4888                 } else {
4889                         /* Flow Director hash filters enabled */
4890                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4891                         adapter->atr_sample_rate = 20;
4892                 }
4893                 adapter->ring_feature[RING_F_FDIR].indices =
4894                                                          IXGBE_MAX_FDIR_INDICES;
4895                 adapter->fdir_pballoc = 0;
4896 #ifdef IXGBE_FCOE
4897                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4898                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4899                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4900 #ifdef CONFIG_IXGBE_DCB
4901                 /* Default traffic class to use for FCoE */
4902                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4903                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4904 #endif
4905 #endif /* IXGBE_FCOE */
4906         }
4907
4908 #ifdef CONFIG_IXGBE_DCB
4909         /* Configure DCB traffic classes */
4910         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4911                 tc = &adapter->dcb_cfg.tc_config[j];
4912                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4913                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4914                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4915                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4916                 tc->dcb_pfc = pfc_disabled;
4917         }
4918         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4919         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4920         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4921         adapter->dcb_cfg.pfc_mode_enable = false;
4922         adapter->dcb_cfg.round_robin_enable = false;
4923         adapter->dcb_set_bitmap = 0x00;
4924         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4925                            adapter->ring_feature[RING_F_DCB].indices);
4926
4927 #endif
4928
4929         /* default flow control settings */
4930         hw->fc.requested_mode = ixgbe_fc_full;
4931         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4932 #ifdef CONFIG_DCB
4933         adapter->last_lfc_mode = hw->fc.current_mode;
4934 #endif
4935         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4936         hw->fc.low_water = FC_LOW_WATER(max_frame);
4937         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4938         hw->fc.send_xon = true;
4939         hw->fc.disable_fc_autoneg = false;
4940
4941         /* enable itr by default in dynamic mode */
4942         adapter->rx_itr_setting = 1;
4943         adapter->rx_eitr_param = 20000;
4944         adapter->tx_itr_setting = 1;
4945         adapter->tx_eitr_param = 10000;
4946
4947         /* set defaults for eitr in MegaBytes */
4948         adapter->eitr_low = 10;
4949         adapter->eitr_high = 20;
4950
4951         /* set default ring sizes */
4952         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4953         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4954
4955         /* initialize eeprom parameters */
4956         if (ixgbe_init_eeprom_params_generic(hw)) {
4957                 e_dev_err("EEPROM initialization failed\n");
4958                 return -EIO;
4959         }
4960
4961         /* enable rx csum by default */
4962         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4963
4964         /* get assigned NUMA node */
4965         adapter->node = dev_to_node(&pdev->dev);
4966
4967         set_bit(__IXGBE_DOWN, &adapter->state);
4968
4969         return 0;
4970 }
4971
4972 /**
4973  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4974  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4975  *
4976  * Return 0 on success, negative on failure
4977  **/
4978 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4979 {
4980         struct device *dev = tx_ring->dev;
4981         int size;
4982
4983         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4984         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4985         if (!tx_ring->tx_buffer_info)
4986                 tx_ring->tx_buffer_info = vmalloc(size);
4987         if (!tx_ring->tx_buffer_info)
4988                 goto err;
4989         memset(tx_ring->tx_buffer_info, 0, size);
4990
4991         /* round up to nearest 4K */
4992         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4993         tx_ring->size = ALIGN(tx_ring->size, 4096);
4994
4995         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4996                                            &tx_ring->dma, GFP_KERNEL);
4997         if (!tx_ring->desc)
4998                 goto err;
4999
5000         tx_ring->next_to_use = 0;
5001         tx_ring->next_to_clean = 0;
5002         tx_ring->work_limit = tx_ring->count;
5003         return 0;
5004
5005 err:
5006         vfree(tx_ring->tx_buffer_info);
5007         tx_ring->tx_buffer_info = NULL;
5008         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5009         return -ENOMEM;
5010 }
5011
5012 /**
5013  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5014  * @adapter: board private structure
5015  *
5016  * If this function returns with an error, then it's possible one or
5017  * more of the rings is populated (while the rest are not).  It is the
5018  * callers duty to clean those orphaned rings.
5019  *
5020  * Return 0 on success, negative on failure
5021  **/
5022 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5023 {
5024         int i, err = 0;
5025
5026         for (i = 0; i < adapter->num_tx_queues; i++) {
5027                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5028                 if (!err)
5029                         continue;
5030                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5031                 break;
5032         }
5033
5034         return err;
5035 }
5036
5037 /**
5038  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5039  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5040  *
5041  * Returns 0 on success, negative on failure
5042  **/
5043 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5044 {
5045         struct device *dev = rx_ring->dev;
5046         int size;
5047
5048         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5049         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5050         if (!rx_ring->rx_buffer_info)
5051                 rx_ring->rx_buffer_info = vmalloc(size);
5052         if (!rx_ring->rx_buffer_info)
5053                 goto err;
5054         memset(rx_ring->rx_buffer_info, 0, size);
5055
5056         /* Round up to nearest 4K */
5057         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5058         rx_ring->size = ALIGN(rx_ring->size, 4096);
5059
5060         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5061                                            &rx_ring->dma, GFP_KERNEL);
5062
5063         if (!rx_ring->desc)
5064                 goto err;
5065
5066         rx_ring->next_to_clean = 0;
5067         rx_ring->next_to_use = 0;
5068
5069         return 0;
5070 err:
5071         vfree(rx_ring->rx_buffer_info);
5072         rx_ring->rx_buffer_info = NULL;
5073         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5074         return -ENOMEM;
5075 }
5076
5077 /**
5078  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5079  * @adapter: board private structure
5080  *
5081  * If this function returns with an error, then it's possible one or
5082  * more of the rings is populated (while the rest are not).  It is the
5083  * callers duty to clean those orphaned rings.
5084  *
5085  * Return 0 on success, negative on failure
5086  **/
5087 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5088 {
5089         int i, err = 0;
5090
5091         for (i = 0; i < adapter->num_rx_queues; i++) {
5092                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5093                 if (!err)
5094                         continue;
5095                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5096                 break;
5097         }
5098
5099         return err;
5100 }
5101
5102 /**
5103  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5104  * @tx_ring: Tx descriptor ring for a specific queue
5105  *
5106  * Free all transmit software resources
5107  **/
5108 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5109 {
5110         ixgbe_clean_tx_ring(tx_ring);
5111
5112         vfree(tx_ring->tx_buffer_info);
5113         tx_ring->tx_buffer_info = NULL;
5114
5115         /* if not set, then don't free */
5116         if (!tx_ring->desc)
5117                 return;
5118
5119         dma_free_coherent(tx_ring->dev, tx_ring->size,
5120                           tx_ring->desc, tx_ring->dma);
5121
5122         tx_ring->desc = NULL;
5123 }
5124
5125 /**
5126  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5127  * @adapter: board private structure
5128  *
5129  * Free all transmit software resources
5130  **/
5131 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5132 {
5133         int i;
5134
5135         for (i = 0; i < adapter->num_tx_queues; i++)
5136                 if (adapter->tx_ring[i]->desc)
5137                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5138 }
5139
5140 /**
5141  * ixgbe_free_rx_resources - Free Rx Resources
5142  * @rx_ring: ring to clean the resources from
5143  *
5144  * Free all receive software resources
5145  **/
5146 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5147 {
5148         ixgbe_clean_rx_ring(rx_ring);
5149
5150         vfree(rx_ring->rx_buffer_info);
5151         rx_ring->rx_buffer_info = NULL;
5152
5153         /* if not set, then don't free */
5154         if (!rx_ring->desc)
5155                 return;
5156
5157         dma_free_coherent(rx_ring->dev, rx_ring->size,
5158                           rx_ring->desc, rx_ring->dma);
5159
5160         rx_ring->desc = NULL;
5161 }
5162
5163 /**
5164  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5165  * @adapter: board private structure
5166  *
5167  * Free all receive software resources
5168  **/
5169 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5170 {
5171         int i;
5172
5173         for (i = 0; i < adapter->num_rx_queues; i++)
5174                 if (adapter->rx_ring[i]->desc)
5175                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5176 }
5177
5178 /**
5179  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5180  * @netdev: network interface device structure
5181  * @new_mtu: new value for maximum frame size
5182  *
5183  * Returns 0 on success, negative on failure
5184  **/
5185 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5186 {
5187         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5188         struct ixgbe_hw *hw = &adapter->hw;
5189         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5190
5191         /* MTU < 68 is an error and causes problems on some kernels */
5192         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5193                 return -EINVAL;
5194
5195         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5196         /* must set new MTU before calling down or up */
5197         netdev->mtu = new_mtu;
5198
5199         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5200         hw->fc.low_water = FC_LOW_WATER(max_frame);
5201
5202         if (netif_running(netdev))
5203                 ixgbe_reinit_locked(adapter);
5204
5205         return 0;
5206 }
5207
5208 /**
5209  * ixgbe_open - Called when a network interface is made active
5210  * @netdev: network interface device structure
5211  *
5212  * Returns 0 on success, negative value on failure
5213  *
5214  * The open entry point is called when a network interface is made
5215  * active by the system (IFF_UP).  At this point all resources needed
5216  * for transmit and receive operations are allocated, the interrupt
5217  * handler is registered with the OS, the watchdog timer is started,
5218  * and the stack is notified that the interface is ready.
5219  **/
5220 static int ixgbe_open(struct net_device *netdev)
5221 {
5222         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5223         int err;
5224
5225         /* disallow open during test */
5226         if (test_bit(__IXGBE_TESTING, &adapter->state))
5227                 return -EBUSY;
5228
5229         netif_carrier_off(netdev);
5230
5231         /* allocate transmit descriptors */
5232         err = ixgbe_setup_all_tx_resources(adapter);
5233         if (err)
5234                 goto err_setup_tx;
5235
5236         /* allocate receive descriptors */
5237         err = ixgbe_setup_all_rx_resources(adapter);
5238         if (err)
5239                 goto err_setup_rx;
5240
5241         ixgbe_configure(adapter);
5242
5243         err = ixgbe_request_irq(adapter);
5244         if (err)
5245                 goto err_req_irq;
5246
5247         err = ixgbe_up_complete(adapter);
5248         if (err)
5249                 goto err_up;
5250
5251         netif_tx_start_all_queues(netdev);
5252
5253         return 0;
5254
5255 err_up:
5256         ixgbe_release_hw_control(adapter);
5257         ixgbe_free_irq(adapter);
5258 err_req_irq:
5259 err_setup_rx:
5260         ixgbe_free_all_rx_resources(adapter);
5261 err_setup_tx:
5262         ixgbe_free_all_tx_resources(adapter);
5263         ixgbe_reset(adapter);
5264
5265         return err;
5266 }
5267
5268 /**
5269  * ixgbe_close - Disables a network interface
5270  * @netdev: network interface device structure
5271  *
5272  * Returns 0, this is not allowed to fail
5273  *
5274  * The close entry point is called when an interface is de-activated
5275  * by the OS.  The hardware is still under the drivers control, but
5276  * needs to be disabled.  A global MAC reset is issued to stop the
5277  * hardware, and all transmit and receive resources are freed.
5278  **/
5279 static int ixgbe_close(struct net_device *netdev)
5280 {
5281         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5282
5283         ixgbe_down(adapter);
5284         ixgbe_free_irq(adapter);
5285
5286         ixgbe_free_all_tx_resources(adapter);
5287         ixgbe_free_all_rx_resources(adapter);
5288
5289         ixgbe_release_hw_control(adapter);
5290
5291         return 0;
5292 }
5293
5294 #ifdef CONFIG_PM
5295 static int ixgbe_resume(struct pci_dev *pdev)
5296 {
5297         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5298         struct net_device *netdev = adapter->netdev;
5299         u32 err;
5300
5301         pci_set_power_state(pdev, PCI_D0);
5302         pci_restore_state(pdev);
5303         /*
5304          * pci_restore_state clears dev->state_saved so call
5305          * pci_save_state to restore it.
5306          */
5307         pci_save_state(pdev);
5308
5309         err = pci_enable_device_mem(pdev);
5310         if (err) {
5311                 e_dev_err("Cannot enable PCI device from suspend\n");
5312                 return err;
5313         }
5314         pci_set_master(pdev);
5315
5316         pci_wake_from_d3(pdev, false);
5317
5318         err = ixgbe_init_interrupt_scheme(adapter);
5319         if (err) {
5320                 e_dev_err("Cannot initialize interrupts for device\n");
5321                 return err;
5322         }
5323
5324         ixgbe_reset(adapter);
5325
5326         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5327
5328         if (netif_running(netdev)) {
5329                 err = ixgbe_open(netdev);
5330                 if (err)
5331                         return err;
5332         }
5333
5334         netif_device_attach(netdev);
5335
5336         return 0;
5337 }
5338 #endif /* CONFIG_PM */
5339
5340 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5341 {
5342         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5343         struct net_device *netdev = adapter->netdev;
5344         struct ixgbe_hw *hw = &adapter->hw;
5345         u32 ctrl, fctrl;
5346         u32 wufc = adapter->wol;
5347 #ifdef CONFIG_PM
5348         int retval = 0;
5349 #endif
5350
5351         netif_device_detach(netdev);
5352
5353         if (netif_running(netdev)) {
5354                 ixgbe_down(adapter);
5355                 ixgbe_free_irq(adapter);
5356                 ixgbe_free_all_tx_resources(adapter);
5357                 ixgbe_free_all_rx_resources(adapter);
5358         }
5359
5360         ixgbe_clear_interrupt_scheme(adapter);
5361
5362 #ifdef CONFIG_PM
5363         retval = pci_save_state(pdev);
5364         if (retval)
5365                 return retval;
5366
5367 #endif
5368         if (wufc) {
5369                 ixgbe_set_rx_mode(netdev);
5370
5371                 /* turn on all-multi mode if wake on multicast is enabled */
5372                 if (wufc & IXGBE_WUFC_MC) {
5373                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5374                         fctrl |= IXGBE_FCTRL_MPE;
5375                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5376                 }
5377
5378                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5379                 ctrl |= IXGBE_CTRL_GIO_DIS;
5380                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5381
5382                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5383         } else {
5384                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5385                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5386         }
5387
5388         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5389                 pci_wake_from_d3(pdev, true);
5390         else
5391                 pci_wake_from_d3(pdev, false);
5392
5393         *enable_wake = !!wufc;
5394
5395         ixgbe_release_hw_control(adapter);
5396
5397         pci_disable_device(pdev);
5398
5399         return 0;
5400 }
5401
5402 #ifdef CONFIG_PM
5403 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5404 {
5405         int retval;
5406         bool wake;
5407
5408         retval = __ixgbe_shutdown(pdev, &wake);
5409         if (retval)
5410                 return retval;
5411
5412         if (wake) {
5413                 pci_prepare_to_sleep(pdev);
5414         } else {
5415                 pci_wake_from_d3(pdev, false);
5416                 pci_set_power_state(pdev, PCI_D3hot);
5417         }
5418
5419         return 0;
5420 }
5421 #endif /* CONFIG_PM */
5422
5423 static void ixgbe_shutdown(struct pci_dev *pdev)
5424 {
5425         bool wake;
5426
5427         __ixgbe_shutdown(pdev, &wake);
5428
5429         if (system_state == SYSTEM_POWER_OFF) {
5430                 pci_wake_from_d3(pdev, wake);
5431                 pci_set_power_state(pdev, PCI_D3hot);
5432         }
5433 }
5434
5435 /**
5436  * ixgbe_update_stats - Update the board statistics counters.
5437  * @adapter: board private structure
5438  **/
5439 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5440 {
5441         struct net_device *netdev = adapter->netdev;
5442         struct ixgbe_hw *hw = &adapter->hw;
5443         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5444         u64 total_mpc = 0;
5445         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5446         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5447         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5448         u64 bytes = 0, packets = 0;
5449
5450         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5451             test_bit(__IXGBE_RESETTING, &adapter->state))
5452                 return;
5453
5454         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5455                 u64 rsc_count = 0;
5456                 u64 rsc_flush = 0;
5457                 for (i = 0; i < 16; i++)
5458                         adapter->hw_rx_no_dma_resources +=
5459                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5460                 for (i = 0; i < adapter->num_rx_queues; i++) {
5461                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5462                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5463                 }
5464                 adapter->rsc_total_count = rsc_count;
5465                 adapter->rsc_total_flush = rsc_flush;
5466         }
5467
5468         for (i = 0; i < adapter->num_rx_queues; i++) {
5469                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5470                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5471                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5472                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5473                 bytes += rx_ring->stats.bytes;
5474                 packets += rx_ring->stats.packets;
5475         }
5476         adapter->non_eop_descs = non_eop_descs;
5477         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5478         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5479         netdev->stats.rx_bytes = bytes;
5480         netdev->stats.rx_packets = packets;
5481
5482         bytes = 0;
5483         packets = 0;
5484         /* gather some stats to the adapter struct that are per queue */
5485         for (i = 0; i < adapter->num_tx_queues; i++) {
5486                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5487                 restart_queue += tx_ring->tx_stats.restart_queue;
5488                 tx_busy += tx_ring->tx_stats.tx_busy;
5489                 bytes += tx_ring->stats.bytes;
5490                 packets += tx_ring->stats.packets;
5491         }
5492         adapter->restart_queue = restart_queue;
5493         adapter->tx_busy = tx_busy;
5494         netdev->stats.tx_bytes = bytes;
5495         netdev->stats.tx_packets = packets;
5496
5497         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5498         for (i = 0; i < 8; i++) {
5499                 /* for packet buffers not used, the register should read 0 */
5500                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5501                 missed_rx += mpc;
5502                 hwstats->mpc[i] += mpc;
5503                 total_mpc += hwstats->mpc[i];
5504                 if (hw->mac.type == ixgbe_mac_82598EB)
5505                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5506                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5507                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5508                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5509                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5510                 if (hw->mac.type == ixgbe_mac_82599EB) {
5511                         hwstats->pxonrxc[i] +=
5512                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5513                         hwstats->pxoffrxc[i] +=
5514                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5515                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5516                 } else {
5517                         hwstats->pxonrxc[i] +=
5518                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5519                         hwstats->pxoffrxc[i] +=
5520                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5521                 }
5522                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5523                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5524         }
5525         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5526         /* work around hardware counting issue */
5527         hwstats->gprc -= missed_rx;
5528
5529         /* 82598 hardware only has a 32 bit counter in the high register */
5530         if (hw->mac.type == ixgbe_mac_82599EB) {
5531                 u64 tmp;
5532                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5533                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5534                                                 /* 4 high bits of GORC */
5535                 hwstats->gorc += (tmp << 32);
5536                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5537                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5538                                                 /* 4 high bits of GOTC */
5539                 hwstats->gotc += (tmp << 32);
5540                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5541                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5542                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5543                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5544                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5545                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5546 #ifdef IXGBE_FCOE
5547                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5548                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5549                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5550                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5551                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5552                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5553 #endif /* IXGBE_FCOE */
5554         } else {
5555                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5556                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5557                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5558                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5559                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5560         }
5561         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5562         hwstats->bprc += bprc;
5563         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5564         if (hw->mac.type == ixgbe_mac_82598EB)
5565                 hwstats->mprc -= bprc;
5566         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5567         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5568         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5569         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5570         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5571         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5572         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5573         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5574         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5575         hwstats->lxontxc += lxon;
5576         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5577         hwstats->lxofftxc += lxoff;
5578         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5579         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5580         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5581         /*
5582          * 82598 errata - tx of flow control packets is included in tx counters
5583          */
5584         xon_off_tot = lxon + lxoff;
5585         hwstats->gptc -= xon_off_tot;
5586         hwstats->mptc -= xon_off_tot;
5587         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5588         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5589         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5590         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5591         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5592         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5593         hwstats->ptc64 -= xon_off_tot;
5594         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5595         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5596         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5597         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5598         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5599         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5600
5601         /* Fill out the OS statistics structure */
5602         netdev->stats.multicast = hwstats->mprc;
5603
5604         /* Rx Errors */
5605         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5606         netdev->stats.rx_dropped = 0;
5607         netdev->stats.rx_length_errors = hwstats->rlec;
5608         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5609         netdev->stats.rx_missed_errors = total_mpc;
5610 }
5611
5612 /**
5613  * ixgbe_watchdog - Timer Call-back
5614  * @data: pointer to adapter cast into an unsigned long
5615  **/
5616 static void ixgbe_watchdog(unsigned long data)
5617 {
5618         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5619         struct ixgbe_hw *hw = &adapter->hw;
5620         u64 eics = 0;
5621         int i;
5622
5623         /*
5624          *  Do the watchdog outside of interrupt context due to the lovely
5625          * delays that some of the newer hardware requires
5626          */
5627
5628         if (test_bit(__IXGBE_DOWN, &adapter->state))
5629                 goto watchdog_short_circuit;
5630
5631         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5632                 /*
5633                  * for legacy and MSI interrupts don't set any bits
5634                  * that are enabled for EIAM, because this operation
5635                  * would set *both* EIMS and EICS for any bit in EIAM
5636                  */
5637                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5638                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5639                 goto watchdog_reschedule;
5640         }
5641
5642         /* get one bit for every active tx/rx interrupt vector */
5643         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5644                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5645                 if (qv->rxr_count || qv->txr_count)
5646                         eics |= ((u64)1 << i);
5647         }
5648
5649         /* Cause software interrupt to ensure rx rings are cleaned */
5650         ixgbe_irq_rearm_queues(adapter, eics);
5651
5652 watchdog_reschedule:
5653         /* Reset the timer */
5654         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5655
5656 watchdog_short_circuit:
5657         schedule_work(&adapter->watchdog_task);
5658 }
5659
5660 /**
5661  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5662  * @work: pointer to work_struct containing our data
5663  **/
5664 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5665 {
5666         struct ixgbe_adapter *adapter = container_of(work,
5667                                                      struct ixgbe_adapter,
5668                                                      multispeed_fiber_task);
5669         struct ixgbe_hw *hw = &adapter->hw;
5670         u32 autoneg;
5671         bool negotiation;
5672
5673         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5674         autoneg = hw->phy.autoneg_advertised;
5675         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5676                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5677         hw->mac.autotry_restart = false;
5678         if (hw->mac.ops.setup_link)
5679                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5680         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5681         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5682 }
5683
5684 /**
5685  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5686  * @work: pointer to work_struct containing our data
5687  **/
5688 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5689 {
5690         struct ixgbe_adapter *adapter = container_of(work,
5691                                                      struct ixgbe_adapter,
5692                                                      sfp_config_module_task);
5693         struct ixgbe_hw *hw = &adapter->hw;
5694         u32 err;
5695
5696         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5697
5698         /* Time for electrical oscillations to settle down */
5699         msleep(100);
5700         err = hw->phy.ops.identify_sfp(hw);
5701
5702         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5703                 e_dev_err("failed to initialize because an unsupported SFP+ "
5704                           "module type was detected.\n");
5705                 e_dev_err("Reload the driver after installing a supported "
5706                           "module.\n");
5707                 unregister_netdev(adapter->netdev);
5708                 return;
5709         }
5710         hw->mac.ops.setup_sfp(hw);
5711
5712         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5713                 /* This will also work for DA Twinax connections */
5714                 schedule_work(&adapter->multispeed_fiber_task);
5715         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5716 }
5717
5718 /**
5719  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5720  * @work: pointer to work_struct containing our data
5721  **/
5722 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5723 {
5724         struct ixgbe_adapter *adapter = container_of(work,
5725                                                      struct ixgbe_adapter,
5726                                                      fdir_reinit_task);
5727         struct ixgbe_hw *hw = &adapter->hw;
5728         int i;
5729
5730         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5731                 for (i = 0; i < adapter->num_tx_queues; i++)
5732                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5733                                 &(adapter->tx_ring[i]->state));
5734         } else {
5735                 e_err(probe, "failed to finish FDIR re-initialization, "
5736                       "ignored adding FDIR ATR filters\n");
5737         }
5738         /* Done FDIR Re-initialization, enable transmits */
5739         netif_tx_start_all_queues(adapter->netdev);
5740 }
5741
5742 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5743
5744 /**
5745  * ixgbe_watchdog_task - worker thread to bring link up
5746  * @work: pointer to work_struct containing our data
5747  **/
5748 static void ixgbe_watchdog_task(struct work_struct *work)
5749 {
5750         struct ixgbe_adapter *adapter = container_of(work,
5751                                                      struct ixgbe_adapter,
5752                                                      watchdog_task);
5753         struct net_device *netdev = adapter->netdev;
5754         struct ixgbe_hw *hw = &adapter->hw;
5755         u32 link_speed;
5756         bool link_up;
5757         int i;
5758         struct ixgbe_ring *tx_ring;
5759         int some_tx_pending = 0;
5760
5761         mutex_lock(&ixgbe_watchdog_lock);
5762
5763         link_up = adapter->link_up;
5764         link_speed = adapter->link_speed;
5765
5766         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5767                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5768                 if (link_up) {
5769 #ifdef CONFIG_DCB
5770                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5771                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5772                                         hw->mac.ops.fc_enable(hw, i);
5773                         } else {
5774                                 hw->mac.ops.fc_enable(hw, 0);
5775                         }
5776 #else
5777                         hw->mac.ops.fc_enable(hw, 0);
5778 #endif
5779                 }
5780
5781                 if (link_up ||
5782                     time_after(jiffies, (adapter->link_check_timeout +
5783                                          IXGBE_TRY_LINK_TIMEOUT))) {
5784                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5785                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5786                 }
5787                 adapter->link_up = link_up;
5788                 adapter->link_speed = link_speed;
5789         }
5790
5791         if (link_up) {
5792                 if (!netif_carrier_ok(netdev)) {
5793                         bool flow_rx, flow_tx;
5794
5795                         if (hw->mac.type == ixgbe_mac_82599EB) {
5796                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5797                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5798                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5799                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5800                         } else {
5801                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5802                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5803                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5804                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5805                         }
5806
5807                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5808                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5809                                "10 Gbps" :
5810                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5811                                "1 Gbps" : "unknown speed")),
5812                                ((flow_rx && flow_tx) ? "RX/TX" :
5813                                (flow_rx ? "RX" :
5814                                (flow_tx ? "TX" : "None"))));
5815
5816                         netif_carrier_on(netdev);
5817                 } else {
5818                         /* Force detection of hung controller */
5819                         for (i = 0; i < adapter->num_tx_queues; i++) {
5820                                 tx_ring = adapter->tx_ring[i];
5821                                 set_check_for_tx_hang(tx_ring);
5822                         }
5823                 }
5824         } else {
5825                 adapter->link_up = false;
5826                 adapter->link_speed = 0;
5827                 if (netif_carrier_ok(netdev)) {
5828                         e_info(drv, "NIC Link is Down\n");
5829                         netif_carrier_off(netdev);
5830                 }
5831         }
5832
5833         if (!netif_carrier_ok(netdev)) {
5834                 for (i = 0; i < adapter->num_tx_queues; i++) {
5835                         tx_ring = adapter->tx_ring[i];
5836                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5837                                 some_tx_pending = 1;
5838                                 break;
5839                         }
5840                 }
5841
5842                 if (some_tx_pending) {
5843                         /* We've lost link, so the controller stops DMA,
5844                          * but we've got queued Tx work that's never going
5845                          * to get done, so reset controller to flush Tx.
5846                          * (Do the reset outside of interrupt context).
5847                          */
5848                          schedule_work(&adapter->reset_task);
5849                 }
5850         }
5851
5852         ixgbe_update_stats(adapter);
5853         mutex_unlock(&ixgbe_watchdog_lock);
5854 }
5855
5856 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5857                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5858                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5859 {
5860         struct ixgbe_adv_tx_context_desc *context_desc;
5861         unsigned int i;
5862         int err;
5863         struct ixgbe_tx_buffer *tx_buffer_info;
5864         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5865         u32 mss_l4len_idx, l4len;
5866
5867         if (skb_is_gso(skb)) {
5868                 if (skb_header_cloned(skb)) {
5869                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5870                         if (err)
5871                                 return err;
5872                 }
5873                 l4len = tcp_hdrlen(skb);
5874                 *hdr_len += l4len;
5875
5876                 if (protocol == htons(ETH_P_IP)) {
5877                         struct iphdr *iph = ip_hdr(skb);
5878                         iph->tot_len = 0;
5879                         iph->check = 0;
5880                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5881                                                                  iph->daddr, 0,
5882                                                                  IPPROTO_TCP,
5883                                                                  0);
5884                 } else if (skb_is_gso_v6(skb)) {
5885                         ipv6_hdr(skb)->payload_len = 0;
5886                         tcp_hdr(skb)->check =
5887                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5888                                              &ipv6_hdr(skb)->daddr,
5889                                              0, IPPROTO_TCP, 0);
5890                 }
5891
5892                 i = tx_ring->next_to_use;
5893
5894                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5895                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5896
5897                 /* VLAN MACLEN IPLEN */
5898                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5899                         vlan_macip_lens |=
5900                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5901                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5902                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5903                 *hdr_len += skb_network_offset(skb);
5904                 vlan_macip_lens |=
5905                     (skb_transport_header(skb) - skb_network_header(skb));
5906                 *hdr_len +=
5907                     (skb_transport_header(skb) - skb_network_header(skb));
5908                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5909                 context_desc->seqnum_seed = 0;
5910
5911                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5912                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5913                                    IXGBE_ADVTXD_DTYP_CTXT);
5914
5915                 if (protocol == htons(ETH_P_IP))
5916                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5917                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5918                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5919
5920                 /* MSS L4LEN IDX */
5921                 mss_l4len_idx =
5922                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5923                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5924                 /* use index 1 for TSO */
5925                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5926                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5927
5928                 tx_buffer_info->time_stamp = jiffies;
5929                 tx_buffer_info->next_to_watch = i;
5930
5931                 i++;
5932                 if (i == tx_ring->count)
5933                         i = 0;
5934                 tx_ring->next_to_use = i;
5935
5936                 return true;
5937         }
5938         return false;
5939 }
5940
5941 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5942                       __be16 protocol)
5943 {
5944         u32 rtn = 0;
5945
5946         switch (protocol) {
5947         case cpu_to_be16(ETH_P_IP):
5948                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5949                 switch (ip_hdr(skb)->protocol) {
5950                 case IPPROTO_TCP:
5951                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5952                         break;
5953                 case IPPROTO_SCTP:
5954                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5955                         break;
5956                 }
5957                 break;
5958         case cpu_to_be16(ETH_P_IPV6):
5959                 /* XXX what about other V6 headers?? */
5960                 switch (ipv6_hdr(skb)->nexthdr) {
5961                 case IPPROTO_TCP:
5962                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5963                         break;
5964                 case IPPROTO_SCTP:
5965                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5966                         break;
5967                 }
5968                 break;
5969         default:
5970                 if (unlikely(net_ratelimit()))
5971                         e_warn(probe, "partial checksum but proto=%x!\n",
5972                                protocol);
5973                 break;
5974         }
5975
5976         return rtn;
5977 }
5978
5979 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5980                           struct ixgbe_ring *tx_ring,
5981                           struct sk_buff *skb, u32 tx_flags,
5982                           __be16 protocol)
5983 {
5984         struct ixgbe_adv_tx_context_desc *context_desc;
5985         unsigned int i;
5986         struct ixgbe_tx_buffer *tx_buffer_info;
5987         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5988
5989         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5990             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5991                 i = tx_ring->next_to_use;
5992                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5993                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5994
5995                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5996                         vlan_macip_lens |=
5997                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5998                 vlan_macip_lens |= (skb_network_offset(skb) <<
5999                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6000                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6001                         vlan_macip_lens |= (skb_transport_header(skb) -
6002                                             skb_network_header(skb));
6003
6004                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6005                 context_desc->seqnum_seed = 0;
6006
6007                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6008                                     IXGBE_ADVTXD_DTYP_CTXT);
6009
6010                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6011                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6012
6013                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6014                 /* use index zero for tx checksum offload */
6015                 context_desc->mss_l4len_idx = 0;
6016
6017                 tx_buffer_info->time_stamp = jiffies;
6018                 tx_buffer_info->next_to_watch = i;
6019
6020                 i++;
6021                 if (i == tx_ring->count)
6022                         i = 0;
6023                 tx_ring->next_to_use = i;
6024
6025                 return true;
6026         }
6027
6028         return false;
6029 }
6030
6031 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6032                         struct ixgbe_ring *tx_ring,
6033                         struct sk_buff *skb, u32 tx_flags,
6034                         unsigned int first, const u8 hdr_len)
6035 {
6036         struct device *dev = tx_ring->dev;
6037         struct ixgbe_tx_buffer *tx_buffer_info;
6038         unsigned int len;
6039         unsigned int total = skb->len;
6040         unsigned int offset = 0, size, count = 0, i;
6041         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6042         unsigned int f;
6043         unsigned int bytecount = skb->len;
6044         u16 gso_segs = 1;
6045
6046         i = tx_ring->next_to_use;
6047
6048         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6049                 /* excluding fcoe_crc_eof for FCoE */
6050                 total -= sizeof(struct fcoe_crc_eof);
6051
6052         len = min(skb_headlen(skb), total);
6053         while (len) {
6054                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6055                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6056
6057                 tx_buffer_info->length = size;
6058                 tx_buffer_info->mapped_as_page = false;
6059                 tx_buffer_info->dma = dma_map_single(dev,
6060                                                      skb->data + offset,
6061                                                      size, DMA_TO_DEVICE);
6062                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6063                         goto dma_error;
6064                 tx_buffer_info->time_stamp = jiffies;
6065                 tx_buffer_info->next_to_watch = i;
6066
6067                 len -= size;
6068                 total -= size;
6069                 offset += size;
6070                 count++;
6071
6072                 if (len) {
6073                         i++;
6074                         if (i == tx_ring->count)
6075                                 i = 0;
6076                 }
6077         }
6078
6079         for (f = 0; f < nr_frags; f++) {
6080                 struct skb_frag_struct *frag;
6081
6082                 frag = &skb_shinfo(skb)->frags[f];
6083                 len = min((unsigned int)frag->size, total);
6084                 offset = frag->page_offset;
6085
6086                 while (len) {
6087                         i++;
6088                         if (i == tx_ring->count)
6089                                 i = 0;
6090
6091                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6092                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6093
6094                         tx_buffer_info->length = size;
6095                         tx_buffer_info->dma = dma_map_page(dev,
6096                                                            frag->page,
6097                                                            offset, size,
6098                                                            DMA_TO_DEVICE);
6099                         tx_buffer_info->mapped_as_page = true;
6100                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6101                                 goto dma_error;
6102                         tx_buffer_info->time_stamp = jiffies;
6103                         tx_buffer_info->next_to_watch = i;
6104
6105                         len -= size;
6106                         total -= size;
6107                         offset += size;
6108                         count++;
6109                 }
6110                 if (total == 0)
6111                         break;
6112         }
6113
6114         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6115                 gso_segs = skb_shinfo(skb)->gso_segs;
6116 #ifdef IXGBE_FCOE
6117         /* adjust for FCoE Sequence Offload */
6118         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6119                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6120                                         skb_shinfo(skb)->gso_size);
6121 #endif /* IXGBE_FCOE */
6122         bytecount += (gso_segs - 1) * hdr_len;
6123
6124         /* multiply data chunks by size of headers */
6125         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6126         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6127         tx_ring->tx_buffer_info[i].skb = skb;
6128         tx_ring->tx_buffer_info[first].next_to_watch = i;
6129
6130         return count;
6131
6132 dma_error:
6133         e_dev_err("TX DMA map failed\n");
6134
6135         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6136         tx_buffer_info->dma = 0;
6137         tx_buffer_info->time_stamp = 0;
6138         tx_buffer_info->next_to_watch = 0;
6139         if (count)
6140                 count--;
6141
6142         /* clear timestamp and dma mappings for remaining portion of packet */
6143         while (count--) {
6144                 if (i == 0)
6145                         i += tx_ring->count;
6146                 i--;
6147                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6148                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6149         }
6150
6151         return 0;
6152 }
6153
6154 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6155                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6156 {
6157         union ixgbe_adv_tx_desc *tx_desc = NULL;
6158         struct ixgbe_tx_buffer *tx_buffer_info;
6159         u32 olinfo_status = 0, cmd_type_len = 0;
6160         unsigned int i;
6161         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6162
6163         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6164
6165         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6166
6167         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6168                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6169
6170         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6171                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6172
6173                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6174                                  IXGBE_ADVTXD_POPTS_SHIFT;
6175
6176                 /* use index 1 context for tso */
6177                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6178                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6179                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6180                                          IXGBE_ADVTXD_POPTS_SHIFT;
6181
6182         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6183                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6184                                  IXGBE_ADVTXD_POPTS_SHIFT;
6185
6186         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6187                 olinfo_status |= IXGBE_ADVTXD_CC;
6188                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6189                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6190                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6191         }
6192
6193         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6194
6195         i = tx_ring->next_to_use;
6196         while (count--) {
6197                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6198                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6199                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6200                 tx_desc->read.cmd_type_len =
6201                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6202                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6203                 i++;
6204                 if (i == tx_ring->count)
6205                         i = 0;
6206         }
6207
6208         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6209
6210         /*
6211          * Force memory writes to complete before letting h/w
6212          * know there are new descriptors to fetch.  (Only
6213          * applicable for weak-ordered memory model archs,
6214          * such as IA-64).
6215          */
6216         wmb();
6217
6218         tx_ring->next_to_use = i;
6219         writel(i, tx_ring->tail);
6220 }
6221
6222 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6223                       int queue, u32 tx_flags, __be16 protocol)
6224 {
6225         struct ixgbe_atr_input atr_input;
6226         struct tcphdr *th;
6227         struct iphdr *iph = ip_hdr(skb);
6228         struct ethhdr *eth = (struct ethhdr *)skb->data;
6229         u16 vlan_id, src_port, dst_port, flex_bytes;
6230         u32 src_ipv4_addr, dst_ipv4_addr;
6231         u8 l4type = 0;
6232
6233         /* Right now, we support IPv4 only */
6234         if (protocol != htons(ETH_P_IP))
6235                 return;
6236         /* check if we're UDP or TCP */
6237         if (iph->protocol == IPPROTO_TCP) {
6238                 th = tcp_hdr(skb);
6239                 src_port = th->source;
6240                 dst_port = th->dest;
6241                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6242                 /* l4type IPv4 type is 0, no need to assign */
6243         } else {
6244                 /* Unsupported L4 header, just bail here */
6245                 return;
6246         }
6247
6248         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6249
6250         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6251                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6252         src_ipv4_addr = iph->saddr;
6253         dst_ipv4_addr = iph->daddr;
6254         flex_bytes = eth->h_proto;
6255
6256         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6257         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6258         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6259         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6260         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6261         /* src and dst are inverted, think how the receiver sees them */
6262         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6263         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6264
6265         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6266         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6267 }
6268
6269 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6270 {
6271         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6272         /* Herbert's original patch had:
6273          *  smp_mb__after_netif_stop_queue();
6274          * but since that doesn't exist yet, just open code it. */
6275         smp_mb();
6276
6277         /* We need to check again in a case another CPU has just
6278          * made room available. */
6279         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6280                 return -EBUSY;
6281
6282         /* A reprieve! - use start_queue because it doesn't call schedule */
6283         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6284         ++tx_ring->tx_stats.restart_queue;
6285         return 0;
6286 }
6287
6288 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6289 {
6290         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6291                 return 0;
6292         return __ixgbe_maybe_stop_tx(tx_ring, size);
6293 }
6294
6295 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6296 {
6297         struct ixgbe_adapter *adapter = netdev_priv(dev);
6298         int txq = smp_processor_id();
6299 #ifdef IXGBE_FCOE
6300         __be16 protocol;
6301
6302         protocol = vlan_get_protocol(skb);
6303
6304         if ((protocol == htons(ETH_P_FCOE)) ||
6305             (protocol == htons(ETH_P_FIP))) {
6306                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6307                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6308                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6309                         return txq;
6310 #ifdef CONFIG_IXGBE_DCB
6311                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6312                         txq = adapter->fcoe.up;
6313                         return txq;
6314 #endif
6315                 }
6316         }
6317 #endif
6318
6319         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6320                 while (unlikely(txq >= dev->real_num_tx_queues))
6321                         txq -= dev->real_num_tx_queues;
6322                 return txq;
6323         }
6324
6325         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6326                 if (skb->priority == TC_PRIO_CONTROL)
6327                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6328                 else
6329                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6330                                >> 13;
6331                 return txq;
6332         }
6333
6334         return skb_tx_hash(dev, skb);
6335 }
6336
6337 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6338                           struct ixgbe_adapter *adapter,
6339                           struct ixgbe_ring *tx_ring)
6340 {
6341         struct net_device *netdev = tx_ring->netdev;
6342         struct netdev_queue *txq;
6343         unsigned int first;
6344         unsigned int tx_flags = 0;
6345         u8 hdr_len = 0;
6346         int tso;
6347         int count = 0;
6348         unsigned int f;
6349         __be16 protocol;
6350
6351         protocol = vlan_get_protocol(skb);
6352
6353         if (vlan_tx_tag_present(skb)) {
6354                 tx_flags |= vlan_tx_tag_get(skb);
6355                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6356                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6357                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6358                 }
6359                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6360                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6361         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6362                    skb->priority != TC_PRIO_CONTROL) {
6363                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6364                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6365                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6366         }
6367
6368 #ifdef IXGBE_FCOE
6369         /* for FCoE with DCB, we force the priority to what
6370          * was specified by the switch */
6371         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6372             (protocol == htons(ETH_P_FCOE) ||
6373              protocol == htons(ETH_P_FIP))) {
6374 #ifdef CONFIG_IXGBE_DCB
6375                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6376                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6377                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6378                         tx_flags |= ((adapter->fcoe.up << 13)
6379                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6380                 }
6381 #endif
6382                 /* flag for FCoE offloads */
6383                 if (protocol == htons(ETH_P_FCOE))
6384                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6385         }
6386 #endif
6387
6388         /* four things can cause us to need a context descriptor */
6389         if (skb_is_gso(skb) ||
6390             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6391             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6392             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6393                 count++;
6394
6395         count += TXD_USE_COUNT(skb_headlen(skb));
6396         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6397                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6398
6399         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6400                 tx_ring->tx_stats.tx_busy++;
6401                 return NETDEV_TX_BUSY;
6402         }
6403
6404         first = tx_ring->next_to_use;
6405         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6406 #ifdef IXGBE_FCOE
6407                 /* setup tx offload for FCoE */
6408                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6409                 if (tso < 0) {
6410                         dev_kfree_skb_any(skb);
6411                         return NETDEV_TX_OK;
6412                 }
6413                 if (tso)
6414                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6415 #endif /* IXGBE_FCOE */
6416         } else {
6417                 if (protocol == htons(ETH_P_IP))
6418                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6419                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6420                                 protocol);
6421                 if (tso < 0) {
6422                         dev_kfree_skb_any(skb);
6423                         return NETDEV_TX_OK;
6424                 }
6425
6426                 if (tso)
6427                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6428                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6429                                        protocol) &&
6430                          (skb->ip_summed == CHECKSUM_PARTIAL))
6431                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6432         }
6433
6434         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6435         if (count) {
6436                 /* add the ATR filter if ATR is on */
6437                 if (tx_ring->atr_sample_rate) {
6438                         ++tx_ring->atr_count;
6439                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6440                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6441                                       &tx_ring->state)) {
6442                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6443                                           tx_flags, protocol);
6444                                 tx_ring->atr_count = 0;
6445                         }
6446                 }
6447                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6448                 txq->tx_bytes += skb->len;
6449                 txq->tx_packets++;
6450                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6451                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6452
6453         } else {
6454                 dev_kfree_skb_any(skb);
6455                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6456                 tx_ring->next_to_use = first;
6457         }
6458
6459         return NETDEV_TX_OK;
6460 }
6461
6462 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6463 {
6464         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6465         struct ixgbe_ring *tx_ring;
6466
6467         tx_ring = adapter->tx_ring[skb->queue_mapping];
6468         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6469 }
6470
6471 /**
6472  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6473  * @netdev: network interface device structure
6474  * @p: pointer to an address structure
6475  *
6476  * Returns 0 on success, negative on failure
6477  **/
6478 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6479 {
6480         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6481         struct ixgbe_hw *hw = &adapter->hw;
6482         struct sockaddr *addr = p;
6483
6484         if (!is_valid_ether_addr(addr->sa_data))
6485                 return -EADDRNOTAVAIL;
6486
6487         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6488         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6489
6490         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6491                             IXGBE_RAH_AV);
6492
6493         return 0;
6494 }
6495
6496 static int
6497 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6498 {
6499         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6500         struct ixgbe_hw *hw = &adapter->hw;
6501         u16 value;
6502         int rc;
6503
6504         if (prtad != hw->phy.mdio.prtad)
6505                 return -EINVAL;
6506         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6507         if (!rc)
6508                 rc = value;
6509         return rc;
6510 }
6511
6512 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6513                             u16 addr, u16 value)
6514 {
6515         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6516         struct ixgbe_hw *hw = &adapter->hw;
6517
6518         if (prtad != hw->phy.mdio.prtad)
6519                 return -EINVAL;
6520         return hw->phy.ops.write_reg(hw, addr, devad, value);
6521 }
6522
6523 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6524 {
6525         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6526
6527         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6528 }
6529
6530 /**
6531  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6532  * netdev->dev_addrs
6533  * @netdev: network interface device structure
6534  *
6535  * Returns non-zero on failure
6536  **/
6537 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6538 {
6539         int err = 0;
6540         struct ixgbe_adapter *adapter = netdev_priv(dev);
6541         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6542
6543         if (is_valid_ether_addr(mac->san_addr)) {
6544                 rtnl_lock();
6545                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6546                 rtnl_unlock();
6547         }
6548         return err;
6549 }
6550
6551 /**
6552  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6553  * netdev->dev_addrs
6554  * @netdev: network interface device structure
6555  *
6556  * Returns non-zero on failure
6557  **/
6558 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6559 {
6560         int err = 0;
6561         struct ixgbe_adapter *adapter = netdev_priv(dev);
6562         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6563
6564         if (is_valid_ether_addr(mac->san_addr)) {
6565                 rtnl_lock();
6566                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6567                 rtnl_unlock();
6568         }
6569         return err;
6570 }
6571
6572 #ifdef CONFIG_NET_POLL_CONTROLLER
6573 /*
6574  * Polling 'interrupt' - used by things like netconsole to send skbs
6575  * without having to re-enable interrupts. It's not called while
6576  * the interrupt routine is executing.
6577  */
6578 static void ixgbe_netpoll(struct net_device *netdev)
6579 {
6580         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6581         int i;
6582
6583         /* if interface is down do nothing */
6584         if (test_bit(__IXGBE_DOWN, &adapter->state))
6585                 return;
6586
6587         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6588         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6589                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6590                 for (i = 0; i < num_q_vectors; i++) {
6591                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6592                         ixgbe_msix_clean_many(0, q_vector);
6593                 }
6594         } else {
6595                 ixgbe_intr(adapter->pdev->irq, netdev);
6596         }
6597         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6598 }
6599 #endif
6600
6601 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6602                                                    struct rtnl_link_stats64 *stats)
6603 {
6604         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6605         int i;
6606
6607         /* accurate rx/tx bytes/packets stats */
6608         dev_txq_stats_fold(netdev, stats);
6609         rcu_read_lock();
6610         for (i = 0; i < adapter->num_rx_queues; i++) {
6611                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6612                 u64 bytes, packets;
6613                 unsigned int start;
6614
6615                 if (ring) {
6616                         do {
6617                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6618                                 packets = ring->stats.packets;
6619                                 bytes   = ring->stats.bytes;
6620                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6621                         stats->rx_packets += packets;
6622                         stats->rx_bytes   += bytes;
6623                 }
6624         }
6625         rcu_read_unlock();
6626         /* following stats updated by ixgbe_watchdog_task() */
6627         stats->multicast        = netdev->stats.multicast;
6628         stats->rx_errors        = netdev->stats.rx_errors;
6629         stats->rx_length_errors = netdev->stats.rx_length_errors;
6630         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6631         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6632         return stats;
6633 }
6634
6635
6636 static const struct net_device_ops ixgbe_netdev_ops = {
6637         .ndo_open               = ixgbe_open,
6638         .ndo_stop               = ixgbe_close,
6639         .ndo_start_xmit         = ixgbe_xmit_frame,
6640         .ndo_select_queue       = ixgbe_select_queue,
6641         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6642         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6643         .ndo_validate_addr      = eth_validate_addr,
6644         .ndo_set_mac_address    = ixgbe_set_mac,
6645         .ndo_change_mtu         = ixgbe_change_mtu,
6646         .ndo_tx_timeout         = ixgbe_tx_timeout,
6647         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6648         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6649         .ndo_do_ioctl           = ixgbe_ioctl,
6650         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6651         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6652         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6653         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6654         .ndo_get_stats64        = ixgbe_get_stats64,
6655 #ifdef CONFIG_NET_POLL_CONTROLLER
6656         .ndo_poll_controller    = ixgbe_netpoll,
6657 #endif
6658 #ifdef IXGBE_FCOE
6659         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6660         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6661         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6662         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6663         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6664 #endif /* IXGBE_FCOE */
6665 };
6666
6667 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6668                            const struct ixgbe_info *ii)
6669 {
6670 #ifdef CONFIG_PCI_IOV
6671         struct ixgbe_hw *hw = &adapter->hw;
6672         int err;
6673
6674         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6675                 return;
6676
6677         /* The 82599 supports up to 64 VFs per physical function
6678          * but this implementation limits allocation to 63 so that
6679          * basic networking resources are still available to the
6680          * physical function
6681          */
6682         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6683         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6684         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6685         if (err) {
6686                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6687                 goto err_novfs;
6688         }
6689         /* If call to enable VFs succeeded then allocate memory
6690          * for per VF control structures.
6691          */
6692         adapter->vfinfo =
6693                 kcalloc(adapter->num_vfs,
6694                         sizeof(struct vf_data_storage), GFP_KERNEL);
6695         if (adapter->vfinfo) {
6696                 /* Now that we're sure SR-IOV is enabled
6697                  * and memory allocated set up the mailbox parameters
6698                  */
6699                 ixgbe_init_mbx_params_pf(hw);
6700                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6701                        sizeof(hw->mbx.ops));
6702
6703                 /* Disable RSC when in SR-IOV mode */
6704                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6705                                      IXGBE_FLAG2_RSC_ENABLED);
6706                 return;
6707         }
6708
6709         /* Oh oh */
6710         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6711               "SRIOV disabled\n");
6712         pci_disable_sriov(adapter->pdev);
6713
6714 err_novfs:
6715         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6716         adapter->num_vfs = 0;
6717 #endif /* CONFIG_PCI_IOV */
6718 }
6719
6720 /**
6721  * ixgbe_probe - Device Initialization Routine
6722  * @pdev: PCI device information struct
6723  * @ent: entry in ixgbe_pci_tbl
6724  *
6725  * Returns 0 on success, negative on failure
6726  *
6727  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6728  * The OS initialization, configuring of the adapter private structure,
6729  * and a hardware reset occur.
6730  **/
6731 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6732                                  const struct pci_device_id *ent)
6733 {
6734         struct net_device *netdev;
6735         struct ixgbe_adapter *adapter = NULL;
6736         struct ixgbe_hw *hw;
6737         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6738         static int cards_found;
6739         int i, err, pci_using_dac;
6740         unsigned int indices = num_possible_cpus();
6741 #ifdef IXGBE_FCOE
6742         u16 device_caps;
6743 #endif
6744         u32 part_num, eec;
6745
6746         /* Catch broken hardware that put the wrong VF device ID in
6747          * the PCIe SR-IOV capability.
6748          */
6749         if (pdev->is_virtfn) {
6750                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6751                      pci_name(pdev), pdev->vendor, pdev->device);
6752                 return -EINVAL;
6753         }
6754
6755         err = pci_enable_device_mem(pdev);
6756         if (err)
6757                 return err;
6758
6759         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6760             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6761                 pci_using_dac = 1;
6762         } else {
6763                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6764                 if (err) {
6765                         err = dma_set_coherent_mask(&pdev->dev,
6766                                                     DMA_BIT_MASK(32));
6767                         if (err) {
6768                                 dev_err(&pdev->dev,
6769                                         "No usable DMA configuration, aborting\n");
6770                                 goto err_dma;
6771                         }
6772                 }
6773                 pci_using_dac = 0;
6774         }
6775
6776         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6777                                            IORESOURCE_MEM), ixgbe_driver_name);
6778         if (err) {
6779                 dev_err(&pdev->dev,
6780                         "pci_request_selected_regions failed 0x%x\n", err);
6781                 goto err_pci_reg;
6782         }
6783
6784         pci_enable_pcie_error_reporting(pdev);
6785
6786         pci_set_master(pdev);
6787         pci_save_state(pdev);
6788
6789         if (ii->mac == ixgbe_mac_82598EB)
6790                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6791         else
6792                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6793
6794         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6795 #ifdef IXGBE_FCOE
6796         indices += min_t(unsigned int, num_possible_cpus(),
6797                          IXGBE_MAX_FCOE_INDICES);
6798 #endif
6799         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6800         if (!netdev) {
6801                 err = -ENOMEM;
6802                 goto err_alloc_etherdev;
6803         }
6804
6805         SET_NETDEV_DEV(netdev, &pdev->dev);
6806
6807         adapter = netdev_priv(netdev);
6808         pci_set_drvdata(pdev, adapter);
6809
6810         adapter->netdev = netdev;
6811         adapter->pdev = pdev;
6812         hw = &adapter->hw;
6813         hw->back = adapter;
6814         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6815
6816         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6817                               pci_resource_len(pdev, 0));
6818         if (!hw->hw_addr) {
6819                 err = -EIO;
6820                 goto err_ioremap;
6821         }
6822
6823         for (i = 1; i <= 5; i++) {
6824                 if (pci_resource_len(pdev, i) == 0)
6825                         continue;
6826         }
6827
6828         netdev->netdev_ops = &ixgbe_netdev_ops;
6829         ixgbe_set_ethtool_ops(netdev);
6830         netdev->watchdog_timeo = 5 * HZ;
6831         strcpy(netdev->name, pci_name(pdev));
6832
6833         adapter->bd_number = cards_found;
6834
6835         /* Setup hw api */
6836         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6837         hw->mac.type  = ii->mac;
6838
6839         /* EEPROM */
6840         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6841         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6842         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6843         if (!(eec & (1 << 8)))
6844                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6845
6846         /* PHY */
6847         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6848         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6849         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6850         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6851         hw->phy.mdio.mmds = 0;
6852         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6853         hw->phy.mdio.dev = netdev;
6854         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6855         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6856
6857         /* set up this timer and work struct before calling get_invariants
6858          * which might start the timer
6859          */
6860         init_timer(&adapter->sfp_timer);
6861         adapter->sfp_timer.function = ixgbe_sfp_timer;
6862         adapter->sfp_timer.data = (unsigned long) adapter;
6863
6864         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6865
6866         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6867         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6868
6869         /* a new SFP+ module arrival, called from GPI SDP2 context */
6870         INIT_WORK(&adapter->sfp_config_module_task,
6871                   ixgbe_sfp_config_module_task);
6872
6873         ii->get_invariants(hw);
6874
6875         /* setup the private structure */
6876         err = ixgbe_sw_init(adapter);
6877         if (err)
6878                 goto err_sw_init;
6879
6880         /* Make it possible the adapter to be woken up via WOL */
6881         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6882                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6883
6884         /*
6885          * If there is a fan on this device and it has failed log the
6886          * failure.
6887          */
6888         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6889                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6890                 if (esdp & IXGBE_ESDP_SDP1)
6891                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6892         }
6893
6894         /* reset_hw fills in the perm_addr as well */
6895         hw->phy.reset_if_overtemp = true;
6896         err = hw->mac.ops.reset_hw(hw);
6897         hw->phy.reset_if_overtemp = false;
6898         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6899             hw->mac.type == ixgbe_mac_82598EB) {
6900                 /*
6901                  * Start a kernel thread to watch for a module to arrive.
6902                  * Only do this for 82598, since 82599 will generate
6903                  * interrupts on module arrival.
6904                  */
6905                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6906                 mod_timer(&adapter->sfp_timer,
6907                           round_jiffies(jiffies + (2 * HZ)));
6908                 err = 0;
6909         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6910                 e_dev_err("failed to initialize because an unsupported SFP+ "
6911                           "module type was detected.\n");
6912                 e_dev_err("Reload the driver after installing a supported "
6913                           "module.\n");
6914                 goto err_sw_init;
6915         } else if (err) {
6916                 e_dev_err("HW Init failed: %d\n", err);
6917                 goto err_sw_init;
6918         }
6919
6920         ixgbe_probe_vf(adapter, ii);
6921
6922         netdev->features = NETIF_F_SG |
6923                            NETIF_F_IP_CSUM |
6924                            NETIF_F_HW_VLAN_TX |
6925                            NETIF_F_HW_VLAN_RX |
6926                            NETIF_F_HW_VLAN_FILTER;
6927
6928         netdev->features |= NETIF_F_IPV6_CSUM;
6929         netdev->features |= NETIF_F_TSO;
6930         netdev->features |= NETIF_F_TSO6;
6931         netdev->features |= NETIF_F_GRO;
6932
6933         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6934                 netdev->features |= NETIF_F_SCTP_CSUM;
6935
6936         netdev->vlan_features |= NETIF_F_TSO;
6937         netdev->vlan_features |= NETIF_F_TSO6;
6938         netdev->vlan_features |= NETIF_F_IP_CSUM;
6939         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6940         netdev->vlan_features |= NETIF_F_SG;
6941
6942         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6943                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6944                                     IXGBE_FLAG_DCB_ENABLED);
6945         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6946                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6947
6948 #ifdef CONFIG_IXGBE_DCB
6949         netdev->dcbnl_ops = &dcbnl_ops;
6950 #endif
6951
6952 #ifdef IXGBE_FCOE
6953         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6954                 if (hw->mac.ops.get_device_caps) {
6955                         hw->mac.ops.get_device_caps(hw, &device_caps);
6956                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6957                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6958                 }
6959         }
6960         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6961                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6962                 netdev->vlan_features |= NETIF_F_FSO;
6963                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6964         }
6965 #endif /* IXGBE_FCOE */
6966         if (pci_using_dac) {
6967                 netdev->features |= NETIF_F_HIGHDMA;
6968                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6969         }
6970
6971         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6972                 netdev->features |= NETIF_F_LRO;
6973
6974         /* make sure the EEPROM is good */
6975         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6976                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6977                 err = -EIO;
6978                 goto err_eeprom;
6979         }
6980
6981         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6982         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6983
6984         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6985                 e_dev_err("invalid MAC address\n");
6986                 err = -EIO;
6987                 goto err_eeprom;
6988         }
6989
6990         /* power down the optics */
6991         if (hw->phy.multispeed_fiber)
6992                 hw->mac.ops.disable_tx_laser(hw);
6993
6994         init_timer(&adapter->watchdog_timer);
6995         adapter->watchdog_timer.function = ixgbe_watchdog;
6996         adapter->watchdog_timer.data = (unsigned long)adapter;
6997
6998         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6999         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7000
7001         err = ixgbe_init_interrupt_scheme(adapter);
7002         if (err)
7003                 goto err_sw_init;
7004
7005         switch (pdev->device) {
7006         case IXGBE_DEV_ID_82599_KX4:
7007                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7008                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7009                 break;
7010         default:
7011                 adapter->wol = 0;
7012                 break;
7013         }
7014         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7015
7016         /* pick up the PCI bus settings for reporting later */
7017         hw->mac.ops.get_bus_info(hw);
7018
7019         /* print bus type/speed/width info */
7020         e_dev_info("(PCI Express:%s:%s) %pM\n",
7021                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7022                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7023                     "Unknown"),
7024                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7025                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7026                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7027                     "Unknown"),
7028                    netdev->dev_addr);
7029         ixgbe_read_pba_num_generic(hw, &part_num);
7030         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7031                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7032                            "PBA No: %06x-%03x\n",
7033                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7034                            (part_num >> 8), (part_num & 0xff));
7035         else
7036                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7037                            hw->mac.type, hw->phy.type,
7038                            (part_num >> 8), (part_num & 0xff));
7039
7040         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7041                 e_dev_warn("PCI-Express bandwidth available for this card is "
7042                            "not sufficient for optimal performance.\n");
7043                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7044                            "is required.\n");
7045         }
7046
7047         /* save off EEPROM version number */
7048         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7049
7050         /* reset the hardware with the new settings */
7051         err = hw->mac.ops.start_hw(hw);
7052
7053         if (err == IXGBE_ERR_EEPROM_VERSION) {
7054                 /* We are running on a pre-production device, log a warning */
7055                 e_dev_warn("This device is a pre-production adapter/LOM. "
7056                            "Please be aware there may be issues associated "
7057                            "with your hardware.  If you are experiencing "
7058                            "problems please contact your Intel or hardware "
7059                            "representative who provided you with this "
7060                            "hardware.\n");
7061         }
7062         strcpy(netdev->name, "eth%d");
7063         err = register_netdev(netdev);
7064         if (err)
7065                 goto err_register;
7066
7067         /* carrier off reporting is important to ethtool even BEFORE open */
7068         netif_carrier_off(netdev);
7069
7070         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7071             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7072                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7073
7074         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7075                 INIT_WORK(&adapter->check_overtemp_task,
7076                           ixgbe_check_overtemp_task);
7077 #ifdef CONFIG_IXGBE_DCA
7078         if (dca_add_requester(&pdev->dev) == 0) {
7079                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7080                 ixgbe_setup_dca(adapter);
7081         }
7082 #endif
7083         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7084                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7085                 for (i = 0; i < adapter->num_vfs; i++)
7086                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7087         }
7088
7089         /* add san mac addr to netdev */
7090         ixgbe_add_sanmac_netdev(netdev);
7091
7092         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7093         cards_found++;
7094         return 0;
7095
7096 err_register:
7097         ixgbe_release_hw_control(adapter);
7098         ixgbe_clear_interrupt_scheme(adapter);
7099 err_sw_init:
7100 err_eeprom:
7101         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7102                 ixgbe_disable_sriov(adapter);
7103         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7104         del_timer_sync(&adapter->sfp_timer);
7105         cancel_work_sync(&adapter->sfp_task);
7106         cancel_work_sync(&adapter->multispeed_fiber_task);
7107         cancel_work_sync(&adapter->sfp_config_module_task);
7108         iounmap(hw->hw_addr);
7109 err_ioremap:
7110         free_netdev(netdev);
7111 err_alloc_etherdev:
7112         pci_release_selected_regions(pdev,
7113                                      pci_select_bars(pdev, IORESOURCE_MEM));
7114 err_pci_reg:
7115 err_dma:
7116         pci_disable_device(pdev);
7117         return err;
7118 }
7119
7120 /**
7121  * ixgbe_remove - Device Removal Routine
7122  * @pdev: PCI device information struct
7123  *
7124  * ixgbe_remove is called by the PCI subsystem to alert the driver
7125  * that it should release a PCI device.  The could be caused by a
7126  * Hot-Plug event, or because the driver is going to be removed from
7127  * memory.
7128  **/
7129 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7130 {
7131         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7132         struct net_device *netdev = adapter->netdev;
7133
7134         set_bit(__IXGBE_DOWN, &adapter->state);
7135         /* clear the module not found bit to make sure the worker won't
7136          * reschedule
7137          */
7138         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7139         del_timer_sync(&adapter->watchdog_timer);
7140
7141         del_timer_sync(&adapter->sfp_timer);
7142         cancel_work_sync(&adapter->watchdog_task);
7143         cancel_work_sync(&adapter->sfp_task);
7144         cancel_work_sync(&adapter->multispeed_fiber_task);
7145         cancel_work_sync(&adapter->sfp_config_module_task);
7146         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7147             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7148                 cancel_work_sync(&adapter->fdir_reinit_task);
7149         flush_scheduled_work();
7150
7151 #ifdef CONFIG_IXGBE_DCA
7152         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7153                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7154                 dca_remove_requester(&pdev->dev);
7155                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7156         }
7157
7158 #endif
7159 #ifdef IXGBE_FCOE
7160         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7161                 ixgbe_cleanup_fcoe(adapter);
7162
7163 #endif /* IXGBE_FCOE */
7164
7165         /* remove the added san mac */
7166         ixgbe_del_sanmac_netdev(netdev);
7167
7168         if (netdev->reg_state == NETREG_REGISTERED)
7169                 unregister_netdev(netdev);
7170
7171         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7172                 ixgbe_disable_sriov(adapter);
7173
7174         ixgbe_clear_interrupt_scheme(adapter);
7175
7176         ixgbe_release_hw_control(adapter);
7177
7178         iounmap(adapter->hw.hw_addr);
7179         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7180                                      IORESOURCE_MEM));
7181
7182         e_dev_info("complete\n");
7183
7184         free_netdev(netdev);
7185
7186         pci_disable_pcie_error_reporting(pdev);
7187
7188         pci_disable_device(pdev);
7189 }
7190
7191 /**
7192  * ixgbe_io_error_detected - called when PCI error is detected
7193  * @pdev: Pointer to PCI device
7194  * @state: The current pci connection state
7195  *
7196  * This function is called after a PCI bus error affecting
7197  * this device has been detected.
7198  */
7199 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7200                                                 pci_channel_state_t state)
7201 {
7202         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7203         struct net_device *netdev = adapter->netdev;
7204
7205         netif_device_detach(netdev);
7206
7207         if (state == pci_channel_io_perm_failure)
7208                 return PCI_ERS_RESULT_DISCONNECT;
7209
7210         if (netif_running(netdev))
7211                 ixgbe_down(adapter);
7212         pci_disable_device(pdev);
7213
7214         /* Request a slot reset. */
7215         return PCI_ERS_RESULT_NEED_RESET;
7216 }
7217
7218 /**
7219  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7220  * @pdev: Pointer to PCI device
7221  *
7222  * Restart the card from scratch, as if from a cold-boot.
7223  */
7224 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7225 {
7226         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7227         pci_ers_result_t result;
7228         int err;
7229
7230         if (pci_enable_device_mem(pdev)) {
7231                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7232                 result = PCI_ERS_RESULT_DISCONNECT;
7233         } else {
7234                 pci_set_master(pdev);
7235                 pci_restore_state(pdev);
7236                 pci_save_state(pdev);
7237
7238                 pci_wake_from_d3(pdev, false);
7239
7240                 ixgbe_reset(adapter);
7241                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7242                 result = PCI_ERS_RESULT_RECOVERED;
7243         }
7244
7245         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7246         if (err) {
7247                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7248                           "failed 0x%0x\n", err);
7249                 /* non-fatal, continue */
7250         }
7251
7252         return result;
7253 }
7254
7255 /**
7256  * ixgbe_io_resume - called when traffic can start flowing again.
7257  * @pdev: Pointer to PCI device
7258  *
7259  * This callback is called when the error recovery driver tells us that
7260  * its OK to resume normal operation.
7261  */
7262 static void ixgbe_io_resume(struct pci_dev *pdev)
7263 {
7264         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7265         struct net_device *netdev = adapter->netdev;
7266
7267         if (netif_running(netdev)) {
7268                 if (ixgbe_up(adapter)) {
7269                         e_info(probe, "ixgbe_up failed after reset\n");
7270                         return;
7271                 }
7272         }
7273
7274         netif_device_attach(netdev);
7275 }
7276
7277 static struct pci_error_handlers ixgbe_err_handler = {
7278         .error_detected = ixgbe_io_error_detected,
7279         .slot_reset = ixgbe_io_slot_reset,
7280         .resume = ixgbe_io_resume,
7281 };
7282
7283 static struct pci_driver ixgbe_driver = {
7284         .name     = ixgbe_driver_name,
7285         .id_table = ixgbe_pci_tbl,
7286         .probe    = ixgbe_probe,
7287         .remove   = __devexit_p(ixgbe_remove),
7288 #ifdef CONFIG_PM
7289         .suspend  = ixgbe_suspend,
7290         .resume   = ixgbe_resume,
7291 #endif
7292         .shutdown = ixgbe_shutdown,
7293         .err_handler = &ixgbe_err_handler
7294 };
7295
7296 /**
7297  * ixgbe_init_module - Driver Registration Routine
7298  *
7299  * ixgbe_init_module is the first routine called when the driver is
7300  * loaded. All it does is register with the PCI subsystem.
7301  **/
7302 static int __init ixgbe_init_module(void)
7303 {
7304         int ret;
7305         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7306         pr_info("%s\n", ixgbe_copyright);
7307
7308 #ifdef CONFIG_IXGBE_DCA
7309         dca_register_notify(&dca_notifier);
7310 #endif
7311
7312         ret = pci_register_driver(&ixgbe_driver);
7313         return ret;
7314 }
7315
7316 module_init(ixgbe_init_module);
7317
7318 /**
7319  * ixgbe_exit_module - Driver Exit Cleanup Routine
7320  *
7321  * ixgbe_exit_module is called just before the driver is removed
7322  * from memory.
7323  **/
7324 static void __exit ixgbe_exit_module(void)
7325 {
7326 #ifdef CONFIG_IXGBE_DCA
7327         dca_unregister_notify(&dca_notifier);
7328 #endif
7329         pci_unregister_driver(&ixgbe_driver);
7330         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7331 }
7332
7333 #ifdef CONFIG_IXGBE_DCA
7334 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7335                             void *p)
7336 {
7337         int ret_val;
7338
7339         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7340                                          __ixgbe_notify_dca);
7341
7342         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7343 }
7344
7345 #endif /* CONFIG_IXGBE_DCA */
7346
7347 /**
7348  * ixgbe_get_hw_dev return device
7349  * used by hardware layer to print debugging information
7350  **/
7351 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7352 {
7353         struct ixgbe_adapter *adapter = hw->back;
7354         return adapter->netdev;
7355 }
7356
7357 module_exit(ixgbe_exit_module);
7358
7359 /* ixgbe_main.c */