drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         clear_check_for_tx_hang(tx_ring);
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int total_bytes = 0, total_packets = 0;
 739         u16 i, eop, count = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774         tx_ring->total_bytes += total_bytes;
 775         tx_ring->total_packets += total_packets;
 776         u64_stats_update_begin(&tx_ring->syncp);
 777         tx_ring->stats.packets += total_packets;
 778         tx_ring->stats.bytes += total_bytes;
 779         u64_stats_update_end(&tx_ring->syncp);
 780
 781         if (check_for_tx_hang(tx_ring) &&
 782             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 783                 /* schedule immediate reset if we believe we hung */
 784                 e_info(probe, "tx hang %d detected, resetting "
 785                        "adapter\n", adapter->tx_timeout_count + 1);
 786                 ixgbe_tx_timeout(adapter->netdev);
 787
 788                 /* the adapter is about to reset, no point in enabling stuff */
 789                 return true;
 790         }
 791
 792 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 793         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 794                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 795                 /* Make sure that anybody stopping the queue after this
 796                  * sees the new next_to_clean.
 797                  */
 798                 smp_mb();
 799                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 800                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 801                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 802                         ++tx_ring->tx_stats.restart_queue;
 803                 }
 804         }
 805
 806         return count < tx_ring->work_limit;
 807 }
 808
 809 #ifdef CONFIG_IXGBE_DCA
 810 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 811                                 struct ixgbe_ring *rx_ring,
 812                                 int cpu)
 813 {
 814         struct ixgbe_hw *hw = &adapter->hw;
 815         u32 rxctrl;
 816         u8 reg_idx = rx_ring->reg_idx;
 817
 818         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 819         switch (hw->mac.type) {
 820         case ixgbe_mac_82598EB:
 821                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 822                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 823                 break;
 824         case ixgbe_mac_82599EB:
 825                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 826                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 827                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 828                 break;
 829         default:
 830                 break;
 831         }
 832         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 833         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 834         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 835         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 836                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 837         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 838 }
 839
 840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 841                                 struct ixgbe_ring *tx_ring,
 842                                 int cpu)
 843 {
 844         struct ixgbe_hw *hw = &adapter->hw;
 845         u32 txctrl;
 846         u8 reg_idx = tx_ring->reg_idx;
 847
 848         switch (hw->mac.type) {
 849         case ixgbe_mac_82598EB:
 850                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 851                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 852                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 853                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 854                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 855                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 856                 break;
 857         case ixgbe_mac_82599EB:
 858                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 859                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 860                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 861                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 862                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 863                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 864                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 865                 break;
 866         default:
 867                 break;
 868         }
 869 }
 870
 871 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 872 {
 873         struct ixgbe_adapter *adapter = q_vector->adapter;
 874         int cpu = get_cpu();
 875         long r_idx;
 876         int i;
 877
 878         if (q_vector->cpu == cpu)
 879                 goto out_no_update;
 880
 881         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 882         for (i = 0; i < q_vector->txr_count; i++) {
 883                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 884                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 885                                       r_idx + 1);
 886         }
 887
 888         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 889         for (i = 0; i < q_vector->rxr_count; i++) {
 890                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 891                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 892                                       r_idx + 1);
 893         }
 894
 895         q_vector->cpu = cpu;
 896 out_no_update:
 897         put_cpu();
 898 }
 899
 900 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 901 {
 902         int num_q_vectors;
 903         int i;
 904
 905         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 906                 return;
 907
 908         /* always use CB2 mode, difference is masked in the CB driver */
 909         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 910
 911         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 912                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 913         else
 914                 num_q_vectors = 1;
 915
 916         for (i = 0; i < num_q_vectors; i++) {
 917                 adapter->q_vector[i]->cpu = -1;
 918                 ixgbe_update_dca(adapter->q_vector[i]);
 919         }
 920 }
 921
 922 static int __ixgbe_notify_dca(struct device *dev, void *data)
 923 {
 924         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 925         unsigned long event = *(unsigned long *)data;
 926
 927         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 928                 return 0;
 929
 930         switch (event) {
 931         case DCA_PROVIDER_ADD:
 932                 /* if we're already enabled, don't do it again */
 933                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 934                         break;
 935                 if (dca_add_requester(dev) == 0) {
 936                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 937                         ixgbe_setup_dca(adapter);
 938                         break;
 939                 }
 940                 /* Fall Through since DCA is disabled. */
 941         case DCA_PROVIDER_REMOVE:
 942                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 943                         dca_remove_requester(dev);
 944                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 945                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 946                 }
 947                 break;
 948         }
 949
 950         return 0;
 951 }
 952
 953 #endif /* CONFIG_IXGBE_DCA */
 954 /**
 955  * ixgbe_receive_skb - Send a completed packet up the stack
 956  * @adapter: board private structure
 957  * @skb: packet to send up
 958  * @status: hardware indication of status of receive
 959  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 960  * @rx_desc: rx descriptor
 961  **/
 962 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 963                               struct sk_buff *skb, u8 status,
 964                               struct ixgbe_ring *ring,
 965                               union ixgbe_adv_rx_desc *rx_desc)
 966 {
 967         struct ixgbe_adapter *adapter = q_vector->adapter;
 968         struct napi_struct *napi = &q_vector->napi;
 969         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 970         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 971
 972         if (is_vlan && (tag & VLAN_VID_MASK))
 973                 __vlan_hwaccel_put_tag(skb, tag);
 974
 975         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 976                 napi_gro_receive(napi, skb);
 977         else
 978                 netif_rx(skb);
 979 }
 980
 981 /**
 982  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 983  * @adapter: address of board private structure
 984  * @status_err: hardware indication of status of receive
 985  * @skb: skb currently being received and modified
 986  **/
 987 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 988                                      union ixgbe_adv_rx_desc *rx_desc,
 989                                      struct sk_buff *skb)
 990 {
 991         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 992
 993         skb_checksum_none_assert(skb);
 994
 995         /* Rx csum disabled */
 996         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 997                 return;
 998
 999         /* if IP and error */
1000         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1001             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1002                 adapter->hw_csum_rx_error++;
1003                 return;
1004         }
1005
1006         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1007                 return;
1008
1009         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1010                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012                 /*
1013                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1014                  * checksum errors.
1015                  */
1016                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1017                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1018                         return;
1019
1020                 adapter->hw_csum_rx_error++;
1021                 return;
1022         }
1023
1024         /* It must be a TCP or UDP packet with a valid checksum */
1025         skb->ip_summed = CHECKSUM_UNNECESSARY;
1026 }
1027
1028 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1029 {
1030         /*
1031          * Force memory writes to complete before letting h/w
1032          * know there are new descriptors to fetch.  (Only
1033          * applicable for weak-ordered memory model archs,
1034          * such as IA-64).
1035          */
1036         wmb();
1037         writel(val, rx_ring->tail);
1038 }
1039
1040 /**
1041  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1042  * @rx_ring: ring to place buffers on
1043  * @cleaned_count: number of buffers to replace
1044  **/
1045 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1046 {
1047         union ixgbe_adv_rx_desc *rx_desc;
1048         struct ixgbe_rx_buffer *bi;
1049         struct sk_buff *skb;
1050         u16 i = rx_ring->next_to_use;
1051
1052         /* do nothing if no valid netdev defined */
1053         if (!rx_ring->netdev)
1054                 return;
1055
1056         while (cleaned_count--) {
1057                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1058                 bi = &rx_ring->rx_buffer_info[i];
1059                 skb = bi->skb;
1060
1061                 if (!skb) {
1062                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1063                                                         rx_ring->rx_buf_len);
1064                         if (!skb) {
1065                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1066                                 goto no_buffers;
1067                         }
1068                         /* initialize queue mapping */
1069                         skb_record_rx_queue(skb, rx_ring->queue_index);
1070                         bi->skb = skb;
1071                 }
1072
1073                 if (!bi->dma) {
1074                         bi->dma = dma_map_single(rx_ring->dev,
1075                                                  skb->data,
1076                                                  rx_ring->rx_buf_len,
1077                                                  DMA_FROM_DEVICE);
1078                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1079                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1080                                 bi->dma = 0;
1081                                 goto no_buffers;
1082                         }
1083                 }
1084
1085                 if (ring_is_ps_enabled(rx_ring)) {
1086                         if (!bi->page) {
1087                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1088                                 if (!bi->page) {
1089                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1090                                         goto no_buffers;
1091                                 }
1092                         }
1093
1094                         if (!bi->page_dma) {
1095                                 /* use a half page if we're re-using */
1096                                 bi->page_offset ^= PAGE_SIZE / 2;
1097                                 bi->page_dma = dma_map_page(rx_ring->dev,
1098                                                             bi->page,
1099                                                             bi->page_offset,
1100                                                             PAGE_SIZE / 2,
1101                                                             DMA_FROM_DEVICE);
1102                                 if (dma_mapping_error(rx_ring->dev,
1103                                                       bi->page_dma)) {
1104                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1105                                         bi->page_dma = 0;
1106                                         goto no_buffers;
1107                                 }
1108                         }
1109
1110                         /* Refresh the desc even if buffer_addrs didn't change
1111                          * because each write-back erases this info. */
1112                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1113                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1114                 } else {
1115                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1116                         rx_desc->read.hdr_addr = 0;
1117                 }
1118
1119                 i++;
1120                 if (i == rx_ring->count)
1121                         i = 0;
1122         }
1123
1124 no_buffers:
1125         if (rx_ring->next_to_use != i) {
1126                 rx_ring->next_to_use = i;
1127                 ixgbe_release_rx_desc(rx_ring, i);
1128         }
1129 }
1130
1131 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1132 {
1133         /* HW will not DMA in data larger than the given buffer, even if it
1134          * parses the (NFS, of course) header to be larger.  In that case, it
1135          * fills the header buffer and spills the rest into the page.
1136          */
1137         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1138         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1139                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1140         if (hlen > IXGBE_RX_HDR_SIZE)
1141                 hlen = IXGBE_RX_HDR_SIZE;
1142         return hlen;
1143 }
1144
1145 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1146 {
1147         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1148                 IXGBE_RXDADV_RSCCNT_MASK) >>
1149                 IXGBE_RXDADV_RSCCNT_SHIFT;
1150 }
1151
1152 /**
1153  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1154  * @skb: pointer to the last skb in the rsc queue
1155  * @count: pointer to number of packets coalesced in this context
1156  *
1157  * This function changes a queue full of hw rsc buffers into a completed
1158  * packet.  It uses the ->prev pointers to find the first packet and then
1159  * turns it into the frag list owner.
1160  **/
1161 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1162                                                         u64 *count)
1163 {
1164         unsigned int frag_list_size = 0;
1165
1166         while (skb->prev) {
1167                 struct sk_buff *prev = skb->prev;
1168                 frag_list_size += skb->len;
1169                 skb->prev = NULL;
1170                 skb = prev;
1171                 *count += 1;
1172         }
1173
1174         skb_shinfo(skb)->frag_list = skb->next;
1175         skb->next = NULL;
1176         skb->len += frag_list_size;
1177         skb->data_len += frag_list_size;
1178         skb->truesize += frag_list_size;
1179         return skb;
1180 }
1181
1182 struct ixgbe_rsc_cb {
1183         dma_addr_t dma;
1184         bool delay_unmap;
1185 };
1186
1187 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1188
1189 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1190                                struct ixgbe_ring *rx_ring,
1191                                int *work_done, int work_to_do)
1192 {
1193         struct ixgbe_adapter *adapter = q_vector->adapter;
1194         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1195         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1196         struct sk_buff *skb;
1197         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1198         const int current_node = numa_node_id();
1199         unsigned int rsc_count = 0;
1200 #ifdef IXGBE_FCOE
1201         int ddp_bytes = 0;
1202 #endif /* IXGBE_FCOE */
1203         u32 staterr;
1204         u16 i;
1205         u16 cleaned_count = 0;
1206
1207         i = rx_ring->next_to_clean;
1208         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1209         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1210
1211         while (staterr & IXGBE_RXD_STAT_DD) {
1212                 u32 upper_len = 0;
1213
1214                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215
1216                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1217
1218                 skb = rx_buffer_info->skb;
1219                 rx_buffer_info->skb = NULL;
1220                 prefetch(skb->data);
1221
1222                 if (ring_is_rsc_enabled(rx_ring))
1223                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1224
1225                 /* if this is a skb from previous receive DMA will be 0 */
1226                 if (rx_buffer_info->dma) {
1227                         u16 hlen;
1228                         if (rsc_count &&
1229                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1230                             !skb->prev) {
1231                                 /*
1232                                  * When HWRSC is enabled, delay unmapping
1233                                  * of the first packet. It carries the
1234                                  * header information, HW may still
1235                                  * access the header after the writeback.
1236                                  * Only unmap it when EOP is reached
1237                                  */
1238                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1239                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1240                         } else {
1241                                 dma_unmap_single(rx_ring->dev,
1242                                                  rx_buffer_info->dma,
1243                                                  rx_ring->rx_buf_len,
1244                                                  DMA_FROM_DEVICE);
1245                         }
1246                         rx_buffer_info->dma = 0;
1247
1248                         if (ring_is_ps_enabled(rx_ring)) {
1249                                 hlen = ixgbe_get_hlen(rx_desc);
1250                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1251                         } else {
1252                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1253                         }
1254
1255                         skb_put(skb, hlen);
1256                 } else {
1257                         /* assume packet split since header is unmapped */
1258                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1259                 }
1260
1261                 if (upper_len) {
1262                         dma_unmap_page(rx_ring->dev,
1263                                        rx_buffer_info->page_dma,
1264                                        PAGE_SIZE / 2,
1265                                        DMA_FROM_DEVICE);
1266                         rx_buffer_info->page_dma = 0;
1267                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1268                                            rx_buffer_info->page,
1269                                            rx_buffer_info->page_offset,
1270                                            upper_len);
1271
1272                         if ((page_count(rx_buffer_info->page) == 1) &&
1273                             (page_to_nid(rx_buffer_info->page) == current_node))
1274                                 get_page(rx_buffer_info->page);
1275                         else
1276                                 rx_buffer_info->page = NULL;
1277
1278                         skb->len += upper_len;
1279                         skb->data_len += upper_len;
1280                         skb->truesize += upper_len;
1281                 }
1282
1283                 i++;
1284                 if (i == rx_ring->count)
1285                         i = 0;
1286
1287                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1288                 prefetch(next_rxd);
1289                 cleaned_count++;
1290
1291                 if (rsc_count) {
1292                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1293                                      IXGBE_RXDADV_NEXTP_SHIFT;
1294                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1295                 } else {
1296                         next_buffer = &rx_ring->rx_buffer_info[i];
1297                 }
1298
1299                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1300                         if (ring_is_ps_enabled(rx_ring)) {
1301                                 rx_buffer_info->skb = next_buffer->skb;
1302                                 rx_buffer_info->dma = next_buffer->dma;
1303                                 next_buffer->skb = skb;
1304                                 next_buffer->dma = 0;
1305                         } else {
1306                                 skb->next = next_buffer->skb;
1307                                 skb->next->prev = skb;
1308                         }
1309                         rx_ring->rx_stats.non_eop_descs++;
1310                         goto next_desc;
1311                 }
1312
1313                 if (skb->prev)
1314                         skb = ixgbe_transform_rsc_queue(skb,
1315                                                 &(rx_ring->rx_stats.rsc_count));
1316
1317                 if (ring_is_rsc_enabled(rx_ring)) {
1318                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1319                                 dma_unmap_single(rx_ring->dev,
1320                                                  IXGBE_RSC_CB(skb)->dma,
1321                                                  rx_ring->rx_buf_len,
1322                                                  DMA_FROM_DEVICE);
1323                                 IXGBE_RSC_CB(skb)->dma = 0;
1324                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1325                         }
1326                         if (ring_is_ps_enabled(rx_ring))
1327                                 rx_ring->rx_stats.rsc_count +=
1328                                          skb_shinfo(skb)->nr_frags;
1329                         else
1330                                 rx_ring->rx_stats.rsc_count++;
1331                         rx_ring->rx_stats.rsc_flush++;
1332                 }
1333
1334                 /* ERR_MASK will only have valid bits if EOP set */
1335                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1336                         /* trim packet back to size 0 and recycle it */
1337                         __pskb_trim(skb, 0);
1338                         rx_buffer_info->skb = skb;
1339                         goto next_desc;
1340                 }
1341
1342                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1343
1344                 /* probably a little skewed due to removing CRC */
1345                 total_rx_bytes += skb->len;
1346                 total_rx_packets++;
1347
1348                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1349 #ifdef IXGBE_FCOE
1350                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1351                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1352                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1353                         if (!ddp_bytes)
1354                                 goto next_desc;
1355                 }
1356 #endif /* IXGBE_FCOE */
1357                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1358
1359 next_desc:
1360                 rx_desc->wb.upper.status_error = 0;
1361
1362                 (*work_done)++;
1363                 if (*work_done >= work_to_do)
1364                         break;
1365
1366                 /* return some buffers to hardware, one at a time is too slow */
1367                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1368                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1369                         cleaned_count = 0;
1370                 }
1371
1372                 /* use prefetched values */
1373                 rx_desc = next_rxd;
1374                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1375         }
1376
1377         rx_ring->next_to_clean = i;
1378         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1379
1380         if (cleaned_count)
1381                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1382
1383 #ifdef IXGBE_FCOE
1384         /* include DDPed FCoE data */
1385         if (ddp_bytes > 0) {
1386                 unsigned int mss;
1387
1388                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1389                         sizeof(struct fc_frame_header) -
1390                         sizeof(struct fcoe_crc_eof);
1391                 if (mss > 512)
1392                         mss &= ~511;
1393                 total_rx_bytes += ddp_bytes;
1394                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1395         }
1396 #endif /* IXGBE_FCOE */
1397
1398         rx_ring->total_packets += total_rx_packets;
1399         rx_ring->total_bytes += total_rx_bytes;
1400         u64_stats_update_begin(&rx_ring->syncp);
1401         rx_ring->stats.packets += total_rx_packets;
1402         rx_ring->stats.bytes += total_rx_bytes;
1403         u64_stats_update_end(&rx_ring->syncp);
1404 }
1405
1406 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1407 /**
1408  * ixgbe_configure_msix - Configure MSI-X hardware
1409  * @adapter: board private structure
1410  *
1411  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1412  * interrupts.
1413  **/
1414 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1415 {
1416         struct ixgbe_q_vector *q_vector;
1417         int i, j, q_vectors, v_idx, r_idx;
1418         u32 mask;
1419
1420         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1421
1422         /*
1423          * Populate the IVAR table and set the ITR values to the
1424          * corresponding register.
1425          */
1426         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1427                 q_vector = adapter->q_vector[v_idx];
1428                 /* XXX for_each_set_bit(...) */
1429                 r_idx = find_first_bit(q_vector->rxr_idx,
1430                                        adapter->num_rx_queues);
1431
1432                 for (i = 0; i < q_vector->rxr_count; i++) {
1433                         j = adapter->rx_ring[r_idx]->reg_idx;
1434                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1435                         r_idx = find_next_bit(q_vector->rxr_idx,
1436                                               adapter->num_rx_queues,
1437                                               r_idx + 1);
1438                 }
1439                 r_idx = find_first_bit(q_vector->txr_idx,
1440                                        adapter->num_tx_queues);
1441
1442                 for (i = 0; i < q_vector->txr_count; i++) {
1443                         j = adapter->tx_ring[r_idx]->reg_idx;
1444                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1445                         r_idx = find_next_bit(q_vector->txr_idx,
1446                                               adapter->num_tx_queues,
1447                                               r_idx + 1);
1448                 }
1449
1450                 if (q_vector->txr_count && !q_vector->rxr_count)
1451                         /* tx only */
1452                         q_vector->eitr = adapter->tx_eitr_param;
1453                 else if (q_vector->rxr_count)
1454                         /* rx or mixed */
1455                         q_vector->eitr = adapter->rx_eitr_param;
1456
1457                 ixgbe_write_eitr(q_vector);
1458                 /* If Flow Director is enabled, set interrupt affinity */
1459                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1460                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1461                         /*
1462                          * Allocate the affinity_hint cpumask, assign the mask
1463                          * for this vector, and set our affinity_hint for
1464                          * this irq.
1465                          */
1466                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1467                                                GFP_KERNEL))
1468                                 return;
1469                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1470                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1471                                               q_vector->affinity_mask);
1472                 }
1473         }
1474
1475         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1476                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1477                                v_idx);
1478         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1479                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1480         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1481
1482         /* set up to autoclear timer, and the vectors */
1483         mask = IXGBE_EIMS_ENABLE_MASK;
1484         if (adapter->num_vfs)
1485                 mask &= ~(IXGBE_EIMS_OTHER |
1486                           IXGBE_EIMS_MAILBOX |
1487                           IXGBE_EIMS_LSC);
1488         else
1489                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1490         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1491 }
1492
1493 enum latency_range {
1494         lowest_latency = 0,
1495         low_latency = 1,
1496         bulk_latency = 2,
1497         latency_invalid = 255
1498 };
1499
1500 /**
1501  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1502  * @adapter: pointer to adapter
1503  * @eitr: eitr setting (ints per sec) to give last timeslice
1504  * @itr_setting: current throttle rate in ints/second
1505  * @packets: the number of packets during this measurement interval
1506  * @bytes: the number of bytes during this measurement interval
1507  *
1508  *      Stores a new ITR value based on packets and byte
1509  *      counts during the last interrupt.  The advantage of per interrupt
1510  *      computation is faster updates and more accurate ITR for the current
1511  *      traffic pattern.  Constants in this function were computed
1512  *      based on theoretical maximum wire speed and thresholds were set based
1513  *      on testing data as well as attempting to minimize response time
1514  *      while increasing bulk throughput.
1515  *      this functionality is controlled by the InterruptThrottleRate module
1516  *      parameter (see ixgbe_param.c)
1517  **/
1518 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1519                            u32 eitr, u8 itr_setting,
1520                            int packets, int bytes)
1521 {
1522         unsigned int retval = itr_setting;
1523         u32 timepassed_us;
1524         u64 bytes_perint;
1525
1526         if (packets == 0)
1527                 goto update_itr_done;
1528
1529
1530         /* simple throttlerate management
1531          *    0-20MB/s lowest (100000 ints/s)
1532          *   20-100MB/s low   (20000 ints/s)
1533          *  100-1249MB/s bulk (8000 ints/s)
1534          */
1535         /* what was last interrupt timeslice? */
1536         timepassed_us = 1000000/eitr;
1537         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1538
1539         switch (itr_setting) {
1540         case lowest_latency:
1541                 if (bytes_perint > adapter->eitr_low)
1542                         retval = low_latency;
1543                 break;
1544         case low_latency:
1545                 if (bytes_perint > adapter->eitr_high)
1546                         retval = bulk_latency;
1547                 else if (bytes_perint <= adapter->eitr_low)
1548                         retval = lowest_latency;
1549                 break;
1550         case bulk_latency:
1551                 if (bytes_perint <= adapter->eitr_high)
1552                         retval = low_latency;
1553                 break;
1554         }
1555
1556 update_itr_done:
1557         return retval;
1558 }
1559
1560 /**
1561  * ixgbe_write_eitr - write EITR register in hardware specific way
1562  * @q_vector: structure containing interrupt and ring information
1563  *
1564  * This function is made to be called by ethtool and by the driver
1565  * when it needs to update EITR registers at runtime.  Hardware
1566  * specific quirks/differences are taken care of here.
1567  */
1568 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1569 {
1570         struct ixgbe_adapter *adapter = q_vector->adapter;
1571         struct ixgbe_hw *hw = &adapter->hw;
1572         int v_idx = q_vector->v_idx;
1573         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1574
1575         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1576                 /* must write high and low 16 bits to reset counter */
1577                 itr_reg |= (itr_reg << 16);
1578         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1579                 /*
1580                  * 82599 can support a value of zero, so allow it for
1581                  * max interrupt rate, but there is an errata where it can
1582                  * not be zero with RSC
1583                  */
1584                 if (itr_reg == 8 &&
1585                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1586                         itr_reg = 0;
1587
1588                 /*
1589                  * set the WDIS bit to not clear the timer bits and cause an
1590                  * immediate assertion of the interrupt
1591                  */
1592                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1593         }
1594         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1595 }
1596
1597 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1598 {
1599         struct ixgbe_adapter *adapter = q_vector->adapter;
1600         u32 new_itr;
1601         u8 current_itr, ret_itr;
1602         int i, r_idx;
1603         struct ixgbe_ring *rx_ring, *tx_ring;
1604
1605         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1606         for (i = 0; i < q_vector->txr_count; i++) {
1607                 tx_ring = adapter->tx_ring[r_idx];
1608                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1609                                            q_vector->tx_itr,
1610                                            tx_ring->total_packets,
1611                                            tx_ring->total_bytes);
1612                 /* if the result for this queue would decrease interrupt
1613                  * rate for this vector then use that result */
1614                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1615                                     q_vector->tx_itr - 1 : ret_itr);
1616                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1617                                       r_idx + 1);
1618         }
1619
1620         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1621         for (i = 0; i < q_vector->rxr_count; i++) {
1622                 rx_ring = adapter->rx_ring[r_idx];
1623                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1624                                            q_vector->rx_itr,
1625                                            rx_ring->total_packets,
1626                                            rx_ring->total_bytes);
1627                 /* if the result for this queue would decrease interrupt
1628                  * rate for this vector then use that result */
1629                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1630                                     q_vector->rx_itr - 1 : ret_itr);
1631                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1632                                       r_idx + 1);
1633         }
1634
1635         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1636
1637         switch (current_itr) {
1638         /* counts and packets in update_itr are dependent on these numbers */
1639         case lowest_latency:
1640                 new_itr = 100000;
1641                 break;
1642         case low_latency:
1643                 new_itr = 20000; /* aka hwitr = ~200 */
1644                 break;
1645         case bulk_latency:
1646         default:
1647                 new_itr = 8000;
1648                 break;
1649         }
1650
1651         if (new_itr != q_vector->eitr) {
1652                 /* do an exponential smoothing */
1653                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1654
1655                 /* save the algorithm value here, not the smoothed one */
1656                 q_vector->eitr = new_itr;
1657
1658                 ixgbe_write_eitr(q_vector);
1659         }
1660 }
1661
1662 /**
1663  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1664  * @work: pointer to work_struct containing our data
1665  **/
1666 static void ixgbe_check_overtemp_task(struct work_struct *work)
1667 {
1668         struct ixgbe_adapter *adapter = container_of(work,
1669                                                      struct ixgbe_adapter,
1670                                                      check_overtemp_task);
1671         struct ixgbe_hw *hw = &adapter->hw;
1672         u32 eicr = adapter->interrupt_event;
1673
1674         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1675                 return;
1676
1677         switch (hw->device_id) {
1678         case IXGBE_DEV_ID_82599_T3_LOM: {
1679                 u32 autoneg;
1680                 bool link_up = false;
1681
1682                 if (hw->mac.ops.check_link)
1683                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1684
1685                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1686                     (eicr & IXGBE_EICR_LSC))
1687                         /* Check if this is due to overtemp */
1688                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1689                                 break;
1690                 return;
1691         }
1692         default:
1693                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1694                         return;
1695                 break;
1696         }
1697         e_crit(drv,
1698                "Network adapter has been stopped because it has over heated. "
1699                "Restart the computer. If the problem persists, "
1700                "power off the system and replace the adapter\n");
1701         /* write to clear the interrupt */
1702         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1703 }
1704
1705 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1706 {
1707         struct ixgbe_hw *hw = &adapter->hw;
1708
1709         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1710             (eicr & IXGBE_EICR_GPI_SDP1)) {
1711                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1712                 /* write to clear the interrupt */
1713                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1714         }
1715 }
1716
1717 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1718 {
1719         struct ixgbe_hw *hw = &adapter->hw;
1720
1721         if (eicr & IXGBE_EICR_GPI_SDP2) {
1722                 /* Clear the interrupt */
1723                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1724                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1725                         schedule_work(&adapter->sfp_config_module_task);
1726         }
1727
1728         if (eicr & IXGBE_EICR_GPI_SDP1) {
1729                 /* Clear the interrupt */
1730                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1731                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1732                         schedule_work(&adapter->multispeed_fiber_task);
1733         }
1734 }
1735
1736 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1737 {
1738         struct ixgbe_hw *hw = &adapter->hw;
1739
1740         adapter->lsc_int++;
1741         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1742         adapter->link_check_timeout = jiffies;
1743         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1744                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1745                 IXGBE_WRITE_FLUSH(hw);
1746                 schedule_work(&adapter->watchdog_task);
1747         }
1748 }
1749
1750 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1751 {
1752         struct net_device *netdev = data;
1753         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1754         struct ixgbe_hw *hw = &adapter->hw;
1755         u32 eicr;
1756
1757         /*
1758          * Workaround for Silicon errata.  Use clear-by-write instead
1759          * of clear-by-read.  Reading with EICS will return the
1760          * interrupt causes without clearing, which later be done
1761          * with the write to EICR.
1762          */
1763         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1764         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1765
1766         if (eicr & IXGBE_EICR_LSC)
1767                 ixgbe_check_lsc(adapter);
1768
1769         if (eicr & IXGBE_EICR_MAILBOX)
1770                 ixgbe_msg_task(adapter);
1771
1772         if (hw->mac.type == ixgbe_mac_82598EB)
1773                 ixgbe_check_fan_failure(adapter, eicr);
1774
1775         if (hw->mac.type == ixgbe_mac_82599EB) {
1776                 ixgbe_check_sfp_event(adapter, eicr);
1777                 adapter->interrupt_event = eicr;
1778                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1779                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1780                         schedule_work(&adapter->check_overtemp_task);
1781
1782                 /* Handle Flow Director Full threshold interrupt */
1783                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1784                         int i;
1785                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1786                         /* Disable transmits before FDIR Re-initialization */
1787                         netif_tx_stop_all_queues(netdev);
1788                         for (i = 0; i < adapter->num_tx_queues; i++) {
1789                                 struct ixgbe_ring *tx_ring =
1790                                                             adapter->tx_ring[i];
1791                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1792                                                        &tx_ring->state))
1793                                         schedule_work(&adapter->fdir_reinit_task);
1794                         }
1795                 }
1796         }
1797         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1798                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1799
1800         return IRQ_HANDLED;
1801 }
1802
1803 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1804                                            u64 qmask)
1805 {
1806         u32 mask;
1807
1808         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1809                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1810                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1811         } else {
1812                 mask = (qmask & 0xFFFFFFFF);
1813                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1814                 mask = (qmask >> 32);
1815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1816         }
1817         /* skip the flush */
1818 }
1819
1820 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1821                                             u64 qmask)
1822 {
1823         u32 mask;
1824
1825         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1827                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1828         } else {
1829                 mask = (qmask & 0xFFFFFFFF);
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1831                 mask = (qmask >> 32);
1832                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1833         }
1834         /* skip the flush */
1835 }
1836
1837 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1838 {
1839         struct ixgbe_q_vector *q_vector = data;
1840         struct ixgbe_adapter  *adapter = q_vector->adapter;
1841         struct ixgbe_ring     *tx_ring;
1842         int i, r_idx;
1843
1844         if (!q_vector->txr_count)
1845                 return IRQ_HANDLED;
1846
1847         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1848         for (i = 0; i < q_vector->txr_count; i++) {
1849                 tx_ring = adapter->tx_ring[r_idx];
1850                 tx_ring->total_bytes = 0;
1851                 tx_ring->total_packets = 0;
1852                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1853                                       r_idx + 1);
1854         }
1855
1856         /* EIAM disabled interrupts (on this vector) for us */
1857         napi_schedule(&q_vector->napi);
1858
1859         return IRQ_HANDLED;
1860 }
1861
1862 /**
1863  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1864  * @irq: unused
1865  * @data: pointer to our q_vector struct for this interrupt vector
1866  **/
1867 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1868 {
1869         struct ixgbe_q_vector *q_vector = data;
1870         struct ixgbe_adapter  *adapter = q_vector->adapter;
1871         struct ixgbe_ring  *rx_ring;
1872         int r_idx;
1873         int i;
1874
1875 #ifdef CONFIG_IXGBE_DCA
1876         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1877                 ixgbe_update_dca(q_vector);
1878 #endif
1879
1880         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1881         for (i = 0; i < q_vector->rxr_count; i++) {
1882                 rx_ring = adapter->rx_ring[r_idx];
1883                 rx_ring->total_bytes = 0;
1884                 rx_ring->total_packets = 0;
1885                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1886                                       r_idx + 1);
1887         }
1888
1889         if (!q_vector->rxr_count)
1890                 return IRQ_HANDLED;
1891
1892         /* EIAM disabled interrupts (on this vector) for us */
1893         napi_schedule(&q_vector->napi);
1894
1895         return IRQ_HANDLED;
1896 }
1897
1898 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1899 {
1900         struct ixgbe_q_vector *q_vector = data;
1901         struct ixgbe_adapter  *adapter = q_vector->adapter;
1902         struct ixgbe_ring  *ring;
1903         int r_idx;
1904         int i;
1905
1906         if (!q_vector->txr_count && !q_vector->rxr_count)
1907                 return IRQ_HANDLED;
1908
1909         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1910         for (i = 0; i < q_vector->txr_count; i++) {
1911                 ring = adapter->tx_ring[r_idx];
1912                 ring->total_bytes = 0;
1913                 ring->total_packets = 0;
1914                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1915                                       r_idx + 1);
1916         }
1917
1918         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1919         for (i = 0; i < q_vector->rxr_count; i++) {
1920                 ring = adapter->rx_ring[r_idx];
1921                 ring->total_bytes = 0;
1922                 ring->total_packets = 0;
1923                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1924                                       r_idx + 1);
1925         }
1926
1927         /* EIAM disabled interrupts (on this vector) for us */
1928         napi_schedule(&q_vector->napi);
1929
1930         return IRQ_HANDLED;
1931 }
1932
1933 /**
1934  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1935  * @napi: napi struct with our devices info in it
1936  * @budget: amount of work driver is allowed to do this pass, in packets
1937  *
1938  * This function is optimized for cleaning one queue only on a single
1939  * q_vector!!!
1940  **/
1941 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1942 {
1943         struct ixgbe_q_vector *q_vector =
1944                                container_of(napi, struct ixgbe_q_vector, napi);
1945         struct ixgbe_adapter *adapter = q_vector->adapter;
1946         struct ixgbe_ring *rx_ring = NULL;
1947         int work_done = 0;
1948         long r_idx;
1949
1950 #ifdef CONFIG_IXGBE_DCA
1951         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1952                 ixgbe_update_dca(q_vector);
1953 #endif
1954
1955         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1956         rx_ring = adapter->rx_ring[r_idx];
1957
1958         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1959
1960         /* If all Rx work done, exit the polling mode */
1961         if (work_done < budget) {
1962                 napi_complete(napi);
1963                 if (adapter->rx_itr_setting & 1)
1964                         ixgbe_set_itr_msix(q_vector);
1965                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1966                         ixgbe_irq_enable_queues(adapter,
1967                                                 ((u64)1 << q_vector->v_idx));
1968         }
1969
1970         return work_done;
1971 }
1972
1973 /**
1974  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1975  * @napi: napi struct with our devices info in it
1976  * @budget: amount of work driver is allowed to do this pass, in packets
1977  *
1978  * This function will clean more than one rx queue associated with a
1979  * q_vector.
1980  **/
1981 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1982 {
1983         struct ixgbe_q_vector *q_vector =
1984                                container_of(napi, struct ixgbe_q_vector, napi);
1985         struct ixgbe_adapter *adapter = q_vector->adapter;
1986         struct ixgbe_ring *ring = NULL;
1987         int work_done = 0, i;
1988         long r_idx;
1989         bool tx_clean_complete = true;
1990
1991 #ifdef CONFIG_IXGBE_DCA
1992         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1993                 ixgbe_update_dca(q_vector);
1994 #endif
1995
1996         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1997         for (i = 0; i < q_vector->txr_count; i++) {
1998                 ring = adapter->tx_ring[r_idx];
1999                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2000                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2001                                       r_idx + 1);
2002         }
2003
2004         /* attempt to distribute budget to each queue fairly, but don't allow
2005          * the budget to go below 1 because we'll exit polling */
2006         budget /= (q_vector->rxr_count ?: 1);
2007         budget = max(budget, 1);
2008         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2009         for (i = 0; i < q_vector->rxr_count; i++) {
2010                 ring = adapter->rx_ring[r_idx];
2011                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2012                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2013                                       r_idx + 1);
2014         }
2015
2016         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2017         ring = adapter->rx_ring[r_idx];
2018         /* If all Rx work done, exit the polling mode */
2019         if (work_done < budget) {
2020                 napi_complete(napi);
2021                 if (adapter->rx_itr_setting & 1)
2022                         ixgbe_set_itr_msix(q_vector);
2023                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2024                         ixgbe_irq_enable_queues(adapter,
2025                                                 ((u64)1 << q_vector->v_idx));
2026                 return 0;
2027         }
2028
2029         return work_done;
2030 }
2031
2032 /**
2033  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2034  * @napi: napi struct with our devices info in it
2035  * @budget: amount of work driver is allowed to do this pass, in packets
2036  *
2037  * This function is optimized for cleaning one queue only on a single
2038  * q_vector!!!
2039  **/
2040 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2041 {
2042         struct ixgbe_q_vector *q_vector =
2043                                container_of(napi, struct ixgbe_q_vector, napi);
2044         struct ixgbe_adapter *adapter = q_vector->adapter;
2045         struct ixgbe_ring *tx_ring = NULL;
2046         int work_done = 0;
2047         long r_idx;
2048
2049 #ifdef CONFIG_IXGBE_DCA
2050         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2051                 ixgbe_update_dca(q_vector);
2052 #endif
2053
2054         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2055         tx_ring = adapter->tx_ring[r_idx];
2056
2057         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2058                 work_done = budget;
2059
2060         /* If all Tx work done, exit the polling mode */
2061         if (work_done < budget) {
2062                 napi_complete(napi);
2063                 if (adapter->tx_itr_setting & 1)
2064                         ixgbe_set_itr_msix(q_vector);
2065                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2066                         ixgbe_irq_enable_queues(adapter,
2067                                                 ((u64)1 << q_vector->v_idx));
2068         }
2069
2070         return work_done;
2071 }
2072
2073 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2074                                      int r_idx)
2075 {
2076         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2077
2078         set_bit(r_idx, q_vector->rxr_idx);
2079         q_vector->rxr_count++;
2080 }
2081
2082 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2083                                      int t_idx)
2084 {
2085         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2086
2087         set_bit(t_idx, q_vector->txr_idx);
2088         q_vector->txr_count++;
2089 }
2090
2091 /**
2092  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2093  * @adapter: board private structure to initialize
2094  * @vectors: allotted vector count for descriptor rings
2095  *
2096  * This function maps descriptor rings to the queue-specific vectors
2097  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2098  * one vector per ring/queue, but on a constrained vector budget, we
2099  * group the rings as "efficiently" as possible.  You would add new
2100  * mapping configurations in here.
2101  **/
2102 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2103                                       int vectors)
2104 {
2105         int v_start = 0;
2106         int rxr_idx = 0, txr_idx = 0;
2107         int rxr_remaining = adapter->num_rx_queues;
2108         int txr_remaining = adapter->num_tx_queues;
2109         int i, j;
2110         int rqpv, tqpv;
2111         int err = 0;
2112
2113         /* No mapping required if MSI-X is disabled. */
2114         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2115                 goto out;
2116
2117         /*
2118          * The ideal configuration...
2119          * We have enough vectors to map one per queue.
2120          */
2121         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2122                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2123                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2124
2125                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2126                         map_vector_to_txq(adapter, v_start, txr_idx);
2127
2128                 goto out;
2129         }
2130
2131         /*
2132          * If we don't have enough vectors for a 1-to-1
2133          * mapping, we'll have to group them so there are
2134          * multiple queues per vector.
2135          */
2136         /* Re-adjusting *qpv takes care of the remainder. */
2137         for (i = v_start; i < vectors; i++) {
2138                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2139                 for (j = 0; j < rqpv; j++) {
2140                         map_vector_to_rxq(adapter, i, rxr_idx);
2141                         rxr_idx++;
2142                         rxr_remaining--;
2143                 }
2144         }
2145         for (i = v_start; i < vectors; i++) {
2146                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2147                 for (j = 0; j < tqpv; j++) {
2148                         map_vector_to_txq(adapter, i, txr_idx);
2149                         txr_idx++;
2150                         txr_remaining--;
2151                 }
2152         }
2153
2154 out:
2155         return err;
2156 }
2157
2158 /**
2159  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2160  * @adapter: board private structure
2161  *
2162  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2163  * interrupts from the kernel.
2164  **/
2165 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2166 {
2167         struct net_device *netdev = adapter->netdev;
2168         irqreturn_t (*handler)(int, void *);
2169         int i, vector, q_vectors, err;
2170         int ri = 0, ti = 0;
2171
2172         /* Decrement for Other and TCP Timer vectors */
2173         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2174
2175         /* Map the Tx/Rx rings to the vectors we were allotted. */
2176         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2177         if (err)
2178                 goto out;
2179
2180 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2181                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2182                          &ixgbe_msix_clean_many)
2183         for (vector = 0; vector < q_vectors; vector++) {
2184                 handler = SET_HANDLER(adapter->q_vector[vector]);
2185
2186                 if (handler == &ixgbe_msix_clean_rx) {
2187                         sprintf(adapter->name[vector], "%s-%s-%d",
2188                                 netdev->name, "rx", ri++);
2189                 } else if (handler == &ixgbe_msix_clean_tx) {
2190                         sprintf(adapter->name[vector], "%s-%s-%d",
2191                                 netdev->name, "tx", ti++);
2192                 } else {
2193                         sprintf(adapter->name[vector], "%s-%s-%d",
2194                                 netdev->name, "TxRx", ri++);
2195                         ti++;
2196                 }
2197
2198                 err = request_irq(adapter->msix_entries[vector].vector,
2199                                   handler, 0, adapter->name[vector],
2200                                   adapter->q_vector[vector]);
2201                 if (err) {
2202                         e_err(probe, "request_irq failed for MSIX interrupt "
2203                               "Error: %d\n", err);
2204                         goto free_queue_irqs;
2205                 }
2206         }
2207
2208         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2209         err = request_irq(adapter->msix_entries[vector].vector,
2210                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2211         if (err) {
2212                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2213                 goto free_queue_irqs;
2214         }
2215
2216         return 0;
2217
2218 free_queue_irqs:
2219         for (i = vector - 1; i >= 0; i--)
2220                 free_irq(adapter->msix_entries[--vector].vector,
2221                          adapter->q_vector[i]);
2222         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2223         pci_disable_msix(adapter->pdev);
2224         kfree(adapter->msix_entries);
2225         adapter->msix_entries = NULL;
2226 out:
2227         return err;
2228 }
2229
2230 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2231 {
2232         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2233         u8 current_itr;
2234         u32 new_itr = q_vector->eitr;
2235         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2236         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2237
2238         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2239                                             q_vector->tx_itr,
2240                                             tx_ring->total_packets,
2241                                             tx_ring->total_bytes);
2242         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2243                                             q_vector->rx_itr,
2244                                             rx_ring->total_packets,
2245                                             rx_ring->total_bytes);
2246
2247         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2248
2249         switch (current_itr) {
2250         /* counts and packets in update_itr are dependent on these numbers */
2251         case lowest_latency:
2252                 new_itr = 100000;
2253                 break;
2254         case low_latency:
2255                 new_itr = 20000; /* aka hwitr = ~200 */
2256                 break;
2257         case bulk_latency:
2258                 new_itr = 8000;
2259                 break;
2260         default:
2261                 break;
2262         }
2263
2264         if (new_itr != q_vector->eitr) {
2265                 /* do an exponential smoothing */
2266                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2267
2268                 /* save the algorithm value here, not the smoothed one */
2269                 q_vector->eitr = new_itr;
2270
2271                 ixgbe_write_eitr(q_vector);
2272         }
2273 }
2274
2275 /**
2276  * ixgbe_irq_enable - Enable default interrupt generation settings
2277  * @adapter: board private structure
2278  **/
2279 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2280                                     bool flush)
2281 {
2282         u32 mask;
2283
2284         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2285         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2286                 mask |= IXGBE_EIMS_GPI_SDP0;
2287         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2288                 mask |= IXGBE_EIMS_GPI_SDP1;
2289         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2290                 mask |= IXGBE_EIMS_ECC;
2291                 mask |= IXGBE_EIMS_GPI_SDP1;
2292                 mask |= IXGBE_EIMS_GPI_SDP2;
2293                 if (adapter->num_vfs)
2294                         mask |= IXGBE_EIMS_MAILBOX;
2295         }
2296         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2297             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2298                 mask |= IXGBE_EIMS_FLOW_DIR;
2299
2300         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2301         if (queues)
2302                 ixgbe_irq_enable_queues(adapter, ~0);
2303         if (flush)
2304                 IXGBE_WRITE_FLUSH(&adapter->hw);
2305
2306         if (adapter->num_vfs > 32) {
2307                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2308                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2309         }
2310 }
2311
2312 /**
2313  * ixgbe_intr - legacy mode Interrupt Handler
2314  * @irq: interrupt number
2315  * @data: pointer to a network interface device structure
2316  **/
2317 static irqreturn_t ixgbe_intr(int irq, void *data)
2318 {
2319         struct net_device *netdev = data;
2320         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2321         struct ixgbe_hw *hw = &adapter->hw;
2322         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2323         u32 eicr;
2324
2325         /*
2326          * Workaround for silicon errata on 82598.  Mask the interrupts
2327          * before the read of EICR.
2328          */
2329         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2330
2331         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2332          * therefore no explict interrupt disable is necessary */
2333         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2334         if (!eicr) {
2335                 /*
2336                  * shared interrupt alert!
2337                  * make sure interrupts are enabled because the read will
2338                  * have disabled interrupts due to EIAM
2339                  * finish the workaround of silicon errata on 82598.  Unmask
2340                  * the interrupt that we masked before the EICR read.
2341                  */
2342                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2343                         ixgbe_irq_enable(adapter, true, true);
2344                 return IRQ_NONE;        /* Not our interrupt */
2345         }
2346
2347         if (eicr & IXGBE_EICR_LSC)
2348                 ixgbe_check_lsc(adapter);
2349
2350         if (hw->mac.type == ixgbe_mac_82599EB)
2351                 ixgbe_check_sfp_event(adapter, eicr);
2352
2353         ixgbe_check_fan_failure(adapter, eicr);
2354         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2355             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2356                 schedule_work(&adapter->check_overtemp_task);
2357
2358         if (napi_schedule_prep(&(q_vector->napi))) {
2359                 adapter->tx_ring[0]->total_packets = 0;
2360                 adapter->tx_ring[0]->total_bytes = 0;
2361                 adapter->rx_ring[0]->total_packets = 0;
2362                 adapter->rx_ring[0]->total_bytes = 0;
2363                 /* would disable interrupts here but EIAM disabled it */
2364                 __napi_schedule(&(q_vector->napi));
2365         }
2366
2367         /*
2368          * re-enable link(maybe) and non-queue interrupts, no flush.
2369          * ixgbe_poll will re-enable the queue interrupts
2370          */
2371
2372         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2373                 ixgbe_irq_enable(adapter, false, false);
2374
2375         return IRQ_HANDLED;
2376 }
2377
2378 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2379 {
2380         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2381
2382         for (i = 0; i < q_vectors; i++) {
2383                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2384                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2385                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2386                 q_vector->rxr_count = 0;
2387                 q_vector->txr_count = 0;
2388         }
2389 }
2390
2391 /**
2392  * ixgbe_request_irq - initialize interrupts
2393  * @adapter: board private structure
2394  *
2395  * Attempts to configure interrupts using the best available
2396  * capabilities of the hardware and kernel.
2397  **/
2398 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2399 {
2400         struct net_device *netdev = adapter->netdev;
2401         int err;
2402
2403         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2404                 err = ixgbe_request_msix_irqs(adapter);
2405         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2406                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2407                                   netdev->name, netdev);
2408         } else {
2409                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2410                                   netdev->name, netdev);
2411         }
2412
2413         if (err)
2414                 e_err(probe, "request_irq failed, Error %d\n", err);
2415
2416         return err;
2417 }
2418
2419 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2420 {
2421         struct net_device *netdev = adapter->netdev;
2422
2423         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2424                 int i, q_vectors;
2425
2426                 q_vectors = adapter->num_msix_vectors;
2427
2428                 i = q_vectors - 1;
2429                 free_irq(adapter->msix_entries[i].vector, netdev);
2430
2431                 i--;
2432                 for (; i >= 0; i--) {
2433                         free_irq(adapter->msix_entries[i].vector,
2434                                  adapter->q_vector[i]);
2435                 }
2436
2437                 ixgbe_reset_q_vectors(adapter);
2438         } else {
2439                 free_irq(adapter->pdev->irq, netdev);
2440         }
2441 }
2442
2443 /**
2444  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2445  * @adapter: board private structure
2446  **/
2447 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2448 {
2449         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2450                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2451         } else {
2452                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2453                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2454                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2455                 if (adapter->num_vfs > 32)
2456                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2457         }
2458         IXGBE_WRITE_FLUSH(&adapter->hw);
2459         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2460                 int i;
2461                 for (i = 0; i < adapter->num_msix_vectors; i++)
2462                         synchronize_irq(adapter->msix_entries[i].vector);
2463         } else {
2464                 synchronize_irq(adapter->pdev->irq);
2465         }
2466 }
2467
2468 /**
2469  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2470  *
2471  **/
2472 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2473 {
2474         struct ixgbe_hw *hw = &adapter->hw;
2475
2476         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2477                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2478
2479         ixgbe_set_ivar(adapter, 0, 0, 0);
2480         ixgbe_set_ivar(adapter, 1, 0, 0);
2481
2482         map_vector_to_rxq(adapter, 0, 0);
2483         map_vector_to_txq(adapter, 0, 0);
2484
2485         e_info(hw, "Legacy interrupt IVAR setup done\n");
2486 }
2487
2488 /**
2489  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2490  * @adapter: board private structure
2491  * @ring: structure containing ring specific data
2492  *
2493  * Configure the Tx descriptor ring after a reset.
2494  **/
2495 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2496                              struct ixgbe_ring *ring)
2497 {
2498         struct ixgbe_hw *hw = &adapter->hw;
2499         u64 tdba = ring->dma;
2500         int wait_loop = 10;
2501         u32 txdctl;
2502         u16 reg_idx = ring->reg_idx;
2503
2504         /* disable queue to avoid issues while updating state */
2505         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2506         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2507                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2508         IXGBE_WRITE_FLUSH(hw);
2509
2510         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2511                         (tdba & DMA_BIT_MASK(32)));
2512         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2513         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2514                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2515         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2516         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2517         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2518
2519         /* configure fetching thresholds */
2520         if (adapter->rx_itr_setting == 0) {
2521                 /* cannot set wthresh when itr==0 */
2522                 txdctl &= ~0x007F0000;
2523         } else {
2524                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2525                 txdctl |= (8 << 16);
2526         }
2527         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2528                 /* PThresh workaround for Tx hang with DFP enabled. */
2529                 txdctl |= 32;
2530         }
2531
2532         /* reinitialize flowdirector state */
2533         set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2534
2535         /* enable queue */
2536         txdctl |= IXGBE_TXDCTL_ENABLE;
2537         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2538
2539         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2540         if (hw->mac.type == ixgbe_mac_82598EB &&
2541             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2542                 return;
2543
2544         /* poll to verify queue is enabled */
2545         do {
2546                 msleep(1);
2547                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2548         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2549         if (!wait_loop)
2550                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2551 }
2552
2553 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2554 {
2555         struct ixgbe_hw *hw = &adapter->hw;
2556         u32 rttdcs;
2557         u32 mask;
2558
2559         if (hw->mac.type == ixgbe_mac_82598EB)
2560                 return;
2561
2562         /* disable the arbiter while setting MTQC */
2563         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2564         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2565         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2566
2567         /* set transmit pool layout */
2568         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2569         switch (adapter->flags & mask) {
2570
2571         case (IXGBE_FLAG_SRIOV_ENABLED):
2572                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2573                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2574                 break;
2575
2576         case (IXGBE_FLAG_DCB_ENABLED):
2577                 /* We enable 8 traffic classes, DCB only */
2578                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2579                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2580                 break;
2581
2582         default:
2583                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2584                 break;
2585         }
2586
2587         /* re-enable the arbiter */
2588         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2589         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2590 }
2591
2592 /**
2593  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2594  * @adapter: board private structure
2595  *
2596  * Configure the Tx unit of the MAC after a reset.
2597  **/
2598 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2599 {
2600         struct ixgbe_hw *hw = &adapter->hw;
2601         u32 dmatxctl;
2602         u32 i;
2603
2604         ixgbe_setup_mtqc(adapter);
2605
2606         if (hw->mac.type != ixgbe_mac_82598EB) {
2607                 /* DMATXCTL.EN must be before Tx queues are enabled */
2608                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2609                 dmatxctl |= IXGBE_DMATXCTL_TE;
2610                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2611         }
2612
2613         /* Setup the HW Tx Head and Tail descriptor pointers */
2614         for (i = 0; i < adapter->num_tx_queues; i++)
2615                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2616 }
2617
2618 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2619
2620 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2621                                    struct ixgbe_ring *rx_ring)
2622 {
2623         u32 srrctl;
2624         int index;
2625         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2626
2627         index = rx_ring->reg_idx;
2628         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2629                 unsigned long mask;
2630                 mask = (unsigned long) feature[RING_F_RSS].mask;
2631                 index = index & mask;
2632         }
2633         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2634
2635         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2636         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2637         if (adapter->num_vfs)
2638                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2639
2640         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2641                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2642
2643         if (ring_is_ps_enabled(rx_ring)) {
2644 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2645                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2646 #else
2647                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2648 #endif
2649                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2650         } else {
2651                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2652                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2653                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2654         }
2655
2656         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2657 }
2658
2659 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2660 {
2661         struct ixgbe_hw *hw = &adapter->hw;
2662         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2663                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2664                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2665         u32 mrqc = 0, reta = 0;
2666         u32 rxcsum;
2667         int i, j;
2668         int mask;
2669
2670         /* Fill out hash function seeds */
2671         for (i = 0; i < 10; i++)
2672                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2673
2674         /* Fill out redirection table */
2675         for (i = 0, j = 0; i < 128; i++, j++) {
2676                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2677                         j = 0;
2678                 /* reta = 4-byte sliding window of
2679                  * 0x00..(indices-1)(indices-1)00..etc. */
2680                 reta = (reta << 8) | (j * 0x11);
2681                 if ((i & 3) == 3)
2682                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2683         }
2684
2685         /* Disable indicating checksum in descriptor, enables RSS hash */
2686         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2687         rxcsum |= IXGBE_RXCSUM_PCSD;
2688         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2689
2690         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2691                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2692         else
2693                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2694 #ifdef CONFIG_IXGBE_DCB
2695                                          | IXGBE_FLAG_DCB_ENABLED
2696 #endif
2697                                          | IXGBE_FLAG_SRIOV_ENABLED
2698                                         );
2699
2700         switch (mask) {
2701         case (IXGBE_FLAG_RSS_ENABLED):
2702                 mrqc = IXGBE_MRQC_RSSEN;
2703                 break;
2704         case (IXGBE_FLAG_SRIOV_ENABLED):
2705                 mrqc = IXGBE_MRQC_VMDQEN;
2706                 break;
2707 #ifdef CONFIG_IXGBE_DCB
2708         case (IXGBE_FLAG_DCB_ENABLED):
2709                 mrqc = IXGBE_MRQC_RT8TCEN;
2710                 break;
2711 #endif /* CONFIG_IXGBE_DCB */
2712         default:
2713                 break;
2714         }
2715
2716         /* Perform hash on these packet types */
2717         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2718               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2719               | IXGBE_MRQC_RSS_FIELD_IPV6
2720               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2721
2722         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2723 }
2724
2725 /**
2726  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2727  * @adapter:    address of board private structure
2728  * @index:      index of ring to set
2729  **/
2730 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2731                                    struct ixgbe_ring *ring)
2732 {
2733         struct ixgbe_hw *hw = &adapter->hw;
2734         u32 rscctrl;
2735         int rx_buf_len;
2736         u16 reg_idx = ring->reg_idx;
2737
2738         if (!ring_is_rsc_enabled(ring))
2739                 return;
2740
2741         rx_buf_len = ring->rx_buf_len;
2742         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2743         rscctrl |= IXGBE_RSCCTL_RSCEN;
2744         /*
2745          * we must limit the number of descriptors so that the
2746          * total size of max desc * buf_len is not greater
2747          * than 65535
2748          */
2749         if (ring_is_ps_enabled(ring)) {
2750 #if (MAX_SKB_FRAGS > 16)
2751                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2752 #elif (MAX_SKB_FRAGS > 8)
2753                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2754 #elif (MAX_SKB_FRAGS > 4)
2755                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2756 #else
2757                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2758 #endif
2759         } else {
2760                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2761                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2762                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2763                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2764                 else
2765                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2766         }
2767         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2768 }
2769
2770 /**
2771  *  ixgbe_set_uta - Set unicast filter table address
2772  *  @adapter: board private structure
2773  *
2774  *  The unicast table address is a register array of 32-bit registers.
2775  *  The table is meant to be used in a way similar to how the MTA is used
2776  *  however due to certain limitations in the hardware it is necessary to
2777  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2778  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2779  **/
2780 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2781 {
2782         struct ixgbe_hw *hw = &adapter->hw;
2783         int i;
2784
2785         /* The UTA table only exists on 82599 hardware and newer */
2786         if (hw->mac.type < ixgbe_mac_82599EB)
2787                 return;
2788
2789         /* we only need to do this if VMDq is enabled */
2790         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2791                 return;
2792
2793         for (i = 0; i < 128; i++)
2794                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2795 }
2796
2797 #define IXGBE_MAX_RX_DESC_POLL 10
2798 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2799                                        struct ixgbe_ring *ring)
2800 {
2801         struct ixgbe_hw *hw = &adapter->hw;
2802         int reg_idx = ring->reg_idx;
2803         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2804         u32 rxdctl;
2805
2806         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2807         if (hw->mac.type == ixgbe_mac_82598EB &&
2808             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2809                 return;
2810
2811         do {
2812                 msleep(1);
2813                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2814         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2815
2816         if (!wait_loop) {
2817                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2818                       "the polling period\n", reg_idx);
2819         }
2820 }
2821
2822 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2823                              struct ixgbe_ring *ring)
2824 {
2825         struct ixgbe_hw *hw = &adapter->hw;
2826         u64 rdba = ring->dma;
2827         u32 rxdctl;
2828         u16 reg_idx = ring->reg_idx;
2829
2830         /* disable queue to avoid issues while updating state */
2831         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2832         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2833                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2834         IXGBE_WRITE_FLUSH(hw);
2835
2836         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2837         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2838         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2839                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2840         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2841         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2842         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2843
2844         ixgbe_configure_srrctl(adapter, ring);
2845         ixgbe_configure_rscctl(adapter, ring);
2846
2847         if (hw->mac.type == ixgbe_mac_82598EB) {
2848                 /*
2849                  * enable cache line friendly hardware writes:
2850                  * PTHRESH=32 descriptors (half the internal cache),
2851                  * this also removes ugly rx_no_buffer_count increment
2852                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2853                  * WTHRESH=8 burst writeback up to two cache lines
2854                  */
2855                 rxdctl &= ~0x3FFFFF;
2856                 rxdctl |=  0x080420;
2857         }
2858
2859         /* enable receive descriptor ring */
2860         rxdctl |= IXGBE_RXDCTL_ENABLE;
2861         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2862
2863         ixgbe_rx_desc_queue_enable(adapter, ring);
2864         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2865 }
2866
2867 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2868 {
2869         struct ixgbe_hw *hw = &adapter->hw;
2870         int p;
2871
2872         /* PSRTYPE must be initialized in non 82598 adapters */
2873         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2874                       IXGBE_PSRTYPE_UDPHDR |
2875                       IXGBE_PSRTYPE_IPV4HDR |
2876                       IXGBE_PSRTYPE_L2HDR |
2877                       IXGBE_PSRTYPE_IPV6HDR;
2878
2879         if (hw->mac.type == ixgbe_mac_82598EB)
2880                 return;
2881
2882         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2883                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2884
2885         for (p = 0; p < adapter->num_rx_pools; p++)
2886                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2887                                 psrtype);
2888 }
2889
2890 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2891 {
2892         struct ixgbe_hw *hw = &adapter->hw;
2893         u32 gcr_ext;
2894         u32 vt_reg_bits;
2895         u32 reg_offset, vf_shift;
2896         u32 vmdctl;
2897
2898         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2899                 return;
2900
2901         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2902         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2903         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2904         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2905
2906         vf_shift = adapter->num_vfs % 32;
2907         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2908
2909         /* Enable only the PF's pool for Tx/Rx */
2910         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2911         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2912         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2913         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2914         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2915
2916         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2917         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2918
2919         /*
2920          * Set up VF register offsets for selected VT Mode,
2921          * i.e. 32 or 64 VFs for SR-IOV
2922          */
2923         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2924         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2925         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2926         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2927
2928         /* enable Tx loopback for VF/PF communication */
2929         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2930 }
2931
2932 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2933 {
2934         struct ixgbe_hw *hw = &adapter->hw;
2935         struct net_device *netdev = adapter->netdev;
2936         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2937         int rx_buf_len;
2938         struct ixgbe_ring *rx_ring;
2939         int i;
2940         u32 mhadd, hlreg0;
2941
2942         /* Decide whether to use packet split mode or not */
2943         /* Do not use packet split if we're in SR-IOV Mode */
2944         if (!adapter->num_vfs)
2945                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2946
2947         /* Set the RX buffer length according to the mode */
2948         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2949                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2950         } else {
2951                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2952                     (netdev->mtu <= ETH_DATA_LEN))
2953                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2954                 else
2955                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2956         }
2957
2958 #ifdef IXGBE_FCOE
2959         /* adjust max frame to be able to do baby jumbo for FCoE */
2960         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2961             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2962                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2963
2964 #endif /* IXGBE_FCOE */
2965         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2966         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2967                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2968                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2969
2970                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2971         }
2972
2973         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2974         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2975         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2976         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2977
2978         /*
2979          * Setup the HW Rx Head and Tail Descriptor Pointers and
2980          * the Base and Length of the Rx Descriptor Ring
2981          */
2982         for (i = 0; i < adapter->num_rx_queues; i++) {
2983                 rx_ring = adapter->rx_ring[i];
2984                 rx_ring->rx_buf_len = rx_buf_len;
2985
2986                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2987                         set_ring_ps_enabled(rx_ring);
2988                 else
2989                         clear_ring_ps_enabled(rx_ring);
2990
2991                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2992                         set_ring_rsc_enabled(rx_ring);
2993                 else
2994                         clear_ring_rsc_enabled(rx_ring);
2995
2996 #ifdef IXGBE_FCOE
2997                 if (netdev->features & NETIF_F_FCOE_MTU) {
2998                         struct ixgbe_ring_feature *f;
2999                         f = &adapter->ring_feature[RING_F_FCOE];
3000                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3001                                 clear_ring_ps_enabled(rx_ring);
3002                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3003                                         rx_ring->rx_buf_len =
3004                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3005                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3006                                    !ring_is_ps_enabled(rx_ring)) {
3007                                 rx_ring->rx_buf_len =
3008                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3009                         }
3010                 }
3011 #endif /* IXGBE_FCOE */
3012         }
3013
3014 }
3015
3016 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3017 {
3018         struct ixgbe_hw *hw = &adapter->hw;
3019         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3020
3021         switch (hw->mac.type) {
3022         case ixgbe_mac_82598EB:
3023                 /*
3024                  * For VMDq support of different descriptor types or
3025                  * buffer sizes through the use of multiple SRRCTL
3026                  * registers, RDRXCTL.MVMEN must be set to 1
3027                  *
3028                  * also, the manual doesn't mention it clearly but DCA hints
3029                  * will only use queue 0's tags unless this bit is set.  Side
3030                  * effects of setting this bit are only that SRRCTL must be
3031                  * fully programmed [0..15]
3032                  */
3033                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3034                 break;
3035         case ixgbe_mac_82599EB:
3036                 /* Disable RSC for ACK packets */
3037                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3038                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3039                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3040                 /* hardware requires some bits to be set by default */
3041                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3042                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3043                 break;
3044         default:
3045                 /* We should do nothing since we don't know this hardware */
3046                 return;
3047         }
3048
3049         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3050 }
3051
3052 /**
3053  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3054  * @adapter: board private structure
3055  *
3056  * Configure the Rx unit of the MAC after a reset.
3057  **/
3058 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3059 {
3060         struct ixgbe_hw *hw = &adapter->hw;
3061         int i;
3062         u32 rxctrl;
3063
3064         /* disable receives while setting up the descriptors */
3065         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3066         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3067
3068         ixgbe_setup_psrtype(adapter);
3069         ixgbe_setup_rdrxctl(adapter);
3070
3071         /* Program registers for the distribution of queues */
3072         ixgbe_setup_mrqc(adapter);
3073
3074         ixgbe_set_uta(adapter);
3075
3076         /* set_rx_buffer_len must be called before ring initialization */
3077         ixgbe_set_rx_buffer_len(adapter);
3078
3079         /*
3080          * Setup the HW Rx Head and Tail Descriptor Pointers and
3081          * the Base and Length of the Rx Descriptor Ring
3082          */
3083         for (i = 0; i < adapter->num_rx_queues; i++)
3084                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3085
3086         /* disable drop enable for 82598 parts */
3087         if (hw->mac.type == ixgbe_mac_82598EB)
3088                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3089
3090         /* enable all receives */
3091         rxctrl |= IXGBE_RXCTRL_RXEN;
3092         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3093 }
3094
3095 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3096 {
3097         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3098         struct ixgbe_hw *hw = &adapter->hw;
3099         int pool_ndx = adapter->num_vfs;
3100
3101         /* add VID to filter table */
3102         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3103         set_bit(vid, adapter->active_vlans);
3104 }
3105
3106 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3107 {
3108         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3109         struct ixgbe_hw *hw = &adapter->hw;
3110         int pool_ndx = adapter->num_vfs;
3111
3112         /* remove VID from filter table */
3113         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3114         clear_bit(vid, adapter->active_vlans);
3115 }
3116
3117 /**
3118  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3119  * @adapter: driver data
3120  */
3121 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3122 {
3123         struct ixgbe_hw *hw = &adapter->hw;
3124         u32 vlnctrl;
3125
3126         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3127         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3128         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3129 }
3130
3131 /**
3132  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3133  * @adapter: driver data
3134  */
3135 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3136 {
3137         struct ixgbe_hw *hw = &adapter->hw;
3138         u32 vlnctrl;
3139
3140         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3141         vlnctrl |= IXGBE_VLNCTRL_VFE;
3142         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3143         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3144 }
3145
3146 /**
3147  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3148  * @adapter: driver data
3149  */
3150 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3151 {
3152         struct ixgbe_hw *hw = &adapter->hw;
3153         u32 vlnctrl;
3154         int i, j;
3155
3156         switch (hw->mac.type) {
3157         case ixgbe_mac_82598EB:
3158                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3159                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3160                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3161                 break;
3162         case ixgbe_mac_82599EB:
3163                 for (i = 0; i < adapter->num_rx_queues; i++) {
3164                         j = adapter->rx_ring[i]->reg_idx;
3165                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3166                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3167                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3168                 }
3169                 break;
3170         default:
3171                 break;
3172         }
3173 }
3174
3175 /**
3176  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3177  * @adapter: driver data
3178  */
3179 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3180 {
3181         struct ixgbe_hw *hw = &adapter->hw;
3182         u32 vlnctrl;
3183         int i, j;
3184
3185         switch (hw->mac.type) {
3186         case ixgbe_mac_82598EB:
3187                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3188                 vlnctrl |= IXGBE_VLNCTRL_VME;
3189                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3190                 break;
3191         case ixgbe_mac_82599EB:
3192                 for (i = 0; i < adapter->num_rx_queues; i++) {
3193                         j = adapter->rx_ring[i]->reg_idx;
3194                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3195                         vlnctrl |= IXGBE_RXDCTL_VME;
3196                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3197                 }
3198                 break;
3199         default:
3200                 break;
3201         }
3202 }
3203
3204 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3205 {
3206         u16 vid;
3207
3208         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3209
3210         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3211                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3212 }
3213
3214 /**
3215  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3216  * @netdev: network interface device structure
3217  *
3218  * Writes unicast address list to the RAR table.
3219  * Returns: -ENOMEM on failure/insufficient address space
3220  *                0 on no addresses written
3221  *                X on writing X addresses to the RAR table
3222  **/
3223 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3224 {
3225         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3226         struct ixgbe_hw *hw = &adapter->hw;
3227         unsigned int vfn = adapter->num_vfs;
3228         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3229         int count = 0;
3230
3231         /* return ENOMEM indicating insufficient memory for addresses */
3232         if (netdev_uc_count(netdev) > rar_entries)
3233                 return -ENOMEM;
3234
3235         if (!netdev_uc_empty(netdev) && rar_entries) {
3236                 struct netdev_hw_addr *ha;
3237                 /* return error if we do not support writing to RAR table */
3238                 if (!hw->mac.ops.set_rar)
3239                         return -ENOMEM;
3240
3241                 netdev_for_each_uc_addr(ha, netdev) {
3242                         if (!rar_entries)
3243                                 break;
3244                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3245                                             vfn, IXGBE_RAH_AV);
3246                         count++;
3247                 }
3248         }
3249         /* write the addresses in reverse order to avoid write combining */
3250         for (; rar_entries > 0 ; rar_entries--)
3251                 hw->mac.ops.clear_rar(hw, rar_entries);
3252
3253         return count;
3254 }
3255
3256 /**
3257  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3258  * @netdev: network interface device structure
3259  *
3260  * The set_rx_method entry point is called whenever the unicast/multicast
3261  * address list or the network interface flags are updated.  This routine is
3262  * responsible for configuring the hardware for proper unicast, multicast and
3263  * promiscuous mode.
3264  **/
3265 void ixgbe_set_rx_mode(struct net_device *netdev)
3266 {
3267         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3268         struct ixgbe_hw *hw = &adapter->hw;
3269         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3270         int count;
3271
3272         /* Check for Promiscuous and All Multicast modes */
3273
3274         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3275
3276         /* set all bits that we expect to always be set */
3277         fctrl |= IXGBE_FCTRL_BAM;
3278         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3279         fctrl |= IXGBE_FCTRL_PMCF;
3280
3281         /* clear the bits we are changing the status of */
3282         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3283
3284         if (netdev->flags & IFF_PROMISC) {
3285                 hw->addr_ctrl.user_set_promisc = true;
3286                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3287                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3288                 /* don't hardware filter vlans in promisc mode */
3289                 ixgbe_vlan_filter_disable(adapter);
3290         } else {
3291                 if (netdev->flags & IFF_ALLMULTI) {
3292                         fctrl |= IXGBE_FCTRL_MPE;
3293                         vmolr |= IXGBE_VMOLR_MPE;
3294                 } else {
3295                         /*
3296                          * Write addresses to the MTA, if the attempt fails
3297                          * then we should just turn on promiscous mode so
3298                          * that we can at least receive multicast traffic
3299                          */
3300                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3301                         vmolr |= IXGBE_VMOLR_ROMPE;
3302                 }
3303                 ixgbe_vlan_filter_enable(adapter);
3304                 hw->addr_ctrl.user_set_promisc = false;
3305                 /*
3306                  * Write addresses to available RAR registers, if there is not
3307                  * sufficient space to store all the addresses then enable
3308                  * unicast promiscous mode
3309                  */
3310                 count = ixgbe_write_uc_addr_list(netdev);
3311                 if (count < 0) {
3312                         fctrl |= IXGBE_FCTRL_UPE;
3313                         vmolr |= IXGBE_VMOLR_ROPE;
3314                 }
3315         }
3316
3317         if (adapter->num_vfs) {
3318                 ixgbe_restore_vf_multicasts(adapter);
3319                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3320                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3321                            IXGBE_VMOLR_ROPE);
3322                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3323         }
3324
3325         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3326
3327         if (netdev->features & NETIF_F_HW_VLAN_RX)
3328                 ixgbe_vlan_strip_enable(adapter);
3329         else
3330                 ixgbe_vlan_strip_disable(adapter);
3331 }
3332
3333 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3334 {
3335         int q_idx;
3336         struct ixgbe_q_vector *q_vector;
3337         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3338
3339         /* legacy and MSI only use one vector */
3340         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3341                 q_vectors = 1;
3342
3343         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3344                 struct napi_struct *napi;
3345                 q_vector = adapter->q_vector[q_idx];
3346                 napi = &q_vector->napi;
3347                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3348                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3349                                 if (q_vector->txr_count == 1)
3350                                         napi->poll = &ixgbe_clean_txonly;
3351                                 else if (q_vector->rxr_count == 1)
3352                                         napi->poll = &ixgbe_clean_rxonly;
3353                         }
3354                 }
3355
3356                 napi_enable(napi);
3357         }
3358 }
3359
3360 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3361 {
3362         int q_idx;
3363         struct ixgbe_q_vector *q_vector;
3364         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3365
3366         /* legacy and MSI only use one vector */
3367         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3368                 q_vectors = 1;
3369
3370         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3371                 q_vector = adapter->q_vector[q_idx];
3372                 napi_disable(&q_vector->napi);
3373         }
3374 }
3375
3376 #ifdef CONFIG_IXGBE_DCB
3377 /*
3378  * ixgbe_configure_dcb - Configure DCB hardware
3379  * @adapter: ixgbe adapter struct
3380  *
3381  * This is called by the driver on open to configure the DCB hardware.
3382  * This is also called by the gennetlink interface when reconfiguring
3383  * the DCB state.
3384  */
3385 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3386 {
3387         struct ixgbe_hw *hw = &adapter->hw;
3388         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3389
3390         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3391                 if (hw->mac.type == ixgbe_mac_82598EB)
3392                         netif_set_gso_max_size(adapter->netdev, 65536);
3393                 return;
3394         }
3395
3396         if (hw->mac.type == ixgbe_mac_82598EB)
3397                 netif_set_gso_max_size(adapter->netdev, 32768);
3398
3399 #ifdef CONFIG_FCOE
3400         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3401                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3402 #endif
3403
3404         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3405                                         DCB_TX_CONFIG);
3406         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3407                                         DCB_RX_CONFIG);
3408
3409         /* Enable VLAN tag insert/strip */
3410         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3411
3412         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3413
3414         /* reconfigure the hardware */
3415         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3416 }
3417
3418 #endif
3419 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3420 {
3421         struct net_device *netdev = adapter->netdev;
3422         struct ixgbe_hw *hw = &adapter->hw;
3423         int i;
3424
3425 #ifdef CONFIG_IXGBE_DCB
3426         ixgbe_configure_dcb(adapter);
3427 #endif
3428
3429         ixgbe_set_rx_mode(netdev);
3430         ixgbe_restore_vlan(adapter);
3431
3432 #ifdef IXGBE_FCOE
3433         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3434                 ixgbe_configure_fcoe(adapter);
3435
3436 #endif /* IXGBE_FCOE */
3437         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3438                 for (i = 0; i < adapter->num_tx_queues; i++)
3439                         adapter->tx_ring[i]->atr_sample_rate =
3440                                                        adapter->atr_sample_rate;
3441                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3442         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3443                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3444         }
3445         ixgbe_configure_virtualization(adapter);
3446
3447         ixgbe_configure_tx(adapter);
3448         ixgbe_configure_rx(adapter);
3449 }
3450
3451 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3452 {
3453         switch (hw->phy.type) {
3454         case ixgbe_phy_sfp_avago:
3455         case ixgbe_phy_sfp_ftl:
3456         case ixgbe_phy_sfp_intel:
3457         case ixgbe_phy_sfp_unknown:
3458         case ixgbe_phy_sfp_passive_tyco:
3459         case ixgbe_phy_sfp_passive_unknown:
3460         case ixgbe_phy_sfp_active_unknown:
3461         case ixgbe_phy_sfp_ftl_active:
3462                 return true;
3463         default:
3464                 return false;
3465         }
3466 }
3467
3468 /**
3469  * ixgbe_sfp_link_config - set up SFP+ link
3470  * @adapter: pointer to private adapter struct
3471  **/
3472 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3473 {
3474         struct ixgbe_hw *hw = &adapter->hw;
3475
3476                 if (hw->phy.multispeed_fiber) {
3477                         /*
3478                          * In multispeed fiber setups, the device may not have
3479                          * had a physical connection when the driver loaded.
3480                          * If that's the case, the initial link configuration
3481                          * couldn't get the MAC into 10G or 1G mode, so we'll
3482                          * never have a link status change interrupt fire.
3483                          * We need to try and force an autonegotiation
3484                          * session, then bring up link.
3485                          */
3486                         hw->mac.ops.setup_sfp(hw);
3487                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3488                                 schedule_work(&adapter->multispeed_fiber_task);
3489                 } else {
3490                         /*
3491                          * Direct Attach Cu and non-multispeed fiber modules
3492                          * still need to be configured properly prior to
3493                          * attempting link.
3494                          */
3495                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3496                                 schedule_work(&adapter->sfp_config_module_task);
3497                 }
3498 }
3499
3500 /**
3501  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3502  * @hw: pointer to private hardware struct
3503  *
3504  * Returns 0 on success, negative on failure
3505  **/
3506 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3507 {
3508         u32 autoneg;
3509         bool negotiation, link_up = false;
3510         u32 ret = IXGBE_ERR_LINK_SETUP;
3511
3512         if (hw->mac.ops.check_link)
3513                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3514
3515         if (ret)
3516                 goto link_cfg_out;
3517
3518         if (hw->mac.ops.get_link_capabilities)
3519                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3520                                                         &negotiation);
3521         if (ret)
3522                 goto link_cfg_out;
3523
3524         if (hw->mac.ops.setup_link)
3525                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3526 link_cfg_out:
3527         return ret;
3528 }
3529
3530 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3531 {
3532         struct ixgbe_hw *hw = &adapter->hw;
3533         u32 gpie = 0;
3534
3535         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3536                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3537                        IXGBE_GPIE_OCD;
3538                 gpie |= IXGBE_GPIE_EIAME;
3539                 /*
3540                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3541                  * this saves a register write for every interrupt
3542                  */
3543                 switch (hw->mac.type) {
3544                 case ixgbe_mac_82598EB:
3545                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3546                         break;
3547                 default:
3548                 case ixgbe_mac_82599EB:
3549                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3550                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3551                         break;
3552                 }
3553         } else {
3554                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3555                  * specifically only auto mask tx and rx interrupts */
3556                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3557         }
3558
3559         /* XXX: to interrupt immediately for EICS writes, enable this */
3560         /* gpie |= IXGBE_GPIE_EIMEN; */
3561
3562         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3563                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3564                 gpie |= IXGBE_GPIE_VTMODE_64;
3565         }
3566
3567         /* Enable fan failure interrupt */
3568         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3569                 gpie |= IXGBE_SDP1_GPIEN;
3570
3571         if (hw->mac.type == ixgbe_mac_82599EB)
3572                 gpie |= IXGBE_SDP1_GPIEN;
3573                 gpie |= IXGBE_SDP2_GPIEN;
3574
3575         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3576 }
3577
3578 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3579 {
3580         struct ixgbe_hw *hw = &adapter->hw;
3581         int err;
3582         u32 ctrl_ext;
3583
3584         ixgbe_get_hw_control(adapter);
3585         ixgbe_setup_gpie(adapter);
3586
3587         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3588                 ixgbe_configure_msix(adapter);
3589         else
3590                 ixgbe_configure_msi_and_legacy(adapter);
3591
3592         /* enable the optics */
3593         if (hw->phy.multispeed_fiber)
3594                 hw->mac.ops.enable_tx_laser(hw);
3595
3596         clear_bit(__IXGBE_DOWN, &adapter->state);
3597         ixgbe_napi_enable_all(adapter);
3598
3599         if (ixgbe_is_sfp(hw)) {
3600                 ixgbe_sfp_link_config(adapter);
3601         } else {
3602                 err = ixgbe_non_sfp_link_config(hw);
3603                 if (err)
3604                         e_err(probe, "link_config FAILED %d\n", err);
3605         }
3606
3607         /* clear any pending interrupts, may auto mask */
3608         IXGBE_READ_REG(hw, IXGBE_EICR);
3609         ixgbe_irq_enable(adapter, true, true);
3610
3611         /*
3612          * If this adapter has a fan, check to see if we had a failure
3613          * before we enabled the interrupt.
3614          */
3615         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3616                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3617                 if (esdp & IXGBE_ESDP_SDP1)
3618                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3619         }
3620
3621         /*
3622          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3623          * arrived before interrupts were enabled but after probe.  Such
3624          * devices wouldn't have their type identified yet. We need to
3625          * kick off the SFP+ module setup first, then try to bring up link.
3626          * If we're not hot-pluggable SFP+, we just need to configure link
3627          * and bring it up.
3628          */
3629         if (hw->phy.type == ixgbe_phy_unknown)
3630                 schedule_work(&adapter->sfp_config_module_task);
3631
3632         /* enable transmits */
3633         netif_tx_start_all_queues(adapter->netdev);
3634
3635         /* bring the link up in the watchdog, this could race with our first
3636          * link up interrupt but shouldn't be a problem */
3637         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3638         adapter->link_check_timeout = jiffies;
3639         mod_timer(&adapter->watchdog_timer, jiffies);
3640
3641         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3642         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3643         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3644         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3645
3646         return 0;
3647 }
3648
3649 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3650 {
3651         WARN_ON(in_interrupt());
3652         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3653                 msleep(1);
3654         ixgbe_down(adapter);
3655         /*
3656          * If SR-IOV enabled then wait a bit before bringing the adapter
3657          * back up to give the VFs time to respond to the reset.  The
3658          * two second wait is based upon the watchdog timer cycle in
3659          * the VF driver.
3660          */
3661         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3662                 msleep(2000);
3663         ixgbe_up(adapter);
3664         clear_bit(__IXGBE_RESETTING, &adapter->state);
3665 }
3666
3667 int ixgbe_up(struct ixgbe_adapter *adapter)
3668 {
3669         /* hardware has been reset, we need to reload some things */
3670         ixgbe_configure(adapter);
3671
3672         return ixgbe_up_complete(adapter);
3673 }
3674
3675 void ixgbe_reset(struct ixgbe_adapter *adapter)
3676 {
3677         struct ixgbe_hw *hw = &adapter->hw;
3678         int err;
3679
3680         err = hw->mac.ops.init_hw(hw);
3681         switch (err) {
3682         case 0:
3683         case IXGBE_ERR_SFP_NOT_PRESENT:
3684                 break;
3685         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3686                 e_dev_err("master disable timed out\n");
3687                 break;
3688         case IXGBE_ERR_EEPROM_VERSION:
3689                 /* We are running on a pre-production device, log a warning */
3690                 e_dev_warn("This device is a pre-production adapter/LOM. "
3691                            "Please be aware there may be issuesassociated with "
3692                            "your hardware.  If you are experiencing problems "
3693                            "please contact your Intel or hardware "
3694                            "representative who provided you with this "
3695                            "hardware.\n");
3696                 break;
3697         default:
3698                 e_dev_err("Hardware Error: %d\n", err);
3699         }
3700
3701         /* reprogram the RAR[0] in case user changed it. */
3702         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3703                             IXGBE_RAH_AV);
3704 }
3705
3706 /**
3707  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3708  * @rx_ring: ring to free buffers from
3709  **/
3710 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3711 {
3712         struct device *dev = rx_ring->dev;
3713         unsigned long size;
3714         u16 i;
3715
3716         /* ring already cleared, nothing to do */
3717         if (!rx_ring->rx_buffer_info)
3718                 return;
3719
3720         /* Free all the Rx ring sk_buffs */
3721         for (i = 0; i < rx_ring->count; i++) {
3722                 struct ixgbe_rx_buffer *rx_buffer_info;
3723
3724                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3725                 if (rx_buffer_info->dma) {
3726                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3727                                          rx_ring->rx_buf_len,
3728                                          DMA_FROM_DEVICE);
3729                         rx_buffer_info->dma = 0;
3730                 }
3731                 if (rx_buffer_info->skb) {
3732                         struct sk_buff *skb = rx_buffer_info->skb;
3733                         rx_buffer_info->skb = NULL;
3734                         do {
3735                                 struct sk_buff *this = skb;
3736                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3737                                         dma_unmap_single(dev,
3738                                                          IXGBE_RSC_CB(this)->dma,
3739                                                          rx_ring->rx_buf_len,
3740                                                          DMA_FROM_DEVICE);
3741                                         IXGBE_RSC_CB(this)->dma = 0;
3742                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3743                                 }
3744                                 skb = skb->prev;
3745                                 dev_kfree_skb(this);
3746                         } while (skb);
3747                 }
3748                 if (!rx_buffer_info->page)
3749                         continue;
3750                 if (rx_buffer_info->page_dma) {
3751                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3752                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3753                         rx_buffer_info->page_dma = 0;
3754                 }
3755                 put_page(rx_buffer_info->page);
3756                 rx_buffer_info->page = NULL;
3757                 rx_buffer_info->page_offset = 0;
3758         }
3759
3760         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3761         memset(rx_ring->rx_buffer_info, 0, size);
3762
3763         /* Zero out the descriptor ring */
3764         memset(rx_ring->desc, 0, rx_ring->size);
3765
3766         rx_ring->next_to_clean = 0;
3767         rx_ring->next_to_use = 0;
3768 }
3769
3770 /**
3771  * ixgbe_clean_tx_ring - Free Tx Buffers
3772  * @tx_ring: ring to be cleaned
3773  **/
3774 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3775 {
3776         struct ixgbe_tx_buffer *tx_buffer_info;
3777         unsigned long size;
3778         u16 i;
3779
3780         /* ring already cleared, nothing to do */
3781         if (!tx_ring->tx_buffer_info)
3782                 return;
3783
3784         /* Free all the Tx ring sk_buffs */
3785         for (i = 0; i < tx_ring->count; i++) {
3786                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3787                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3788         }
3789
3790         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3791         memset(tx_ring->tx_buffer_info, 0, size);
3792
3793         /* Zero out the descriptor ring */
3794         memset(tx_ring->desc, 0, tx_ring->size);
3795
3796         tx_ring->next_to_use = 0;
3797         tx_ring->next_to_clean = 0;
3798 }
3799
3800 /**
3801  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3802  * @adapter: board private structure
3803  **/
3804 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3805 {
3806         int i;
3807
3808         for (i = 0; i < adapter->num_rx_queues; i++)
3809                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3810 }
3811
3812 /**
3813  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3814  * @adapter: board private structure
3815  **/
3816 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3817 {
3818         int i;
3819
3820         for (i = 0; i < adapter->num_tx_queues; i++)
3821                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3822 }
3823
3824 void ixgbe_down(struct ixgbe_adapter *adapter)
3825 {
3826         struct net_device *netdev = adapter->netdev;
3827         struct ixgbe_hw *hw = &adapter->hw;
3828         u32 rxctrl;
3829         u32 txdctl;
3830         int i, j;
3831         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3832
3833         /* signal that we are down to the interrupt handler */
3834         set_bit(__IXGBE_DOWN, &adapter->state);
3835
3836         /* disable receive for all VFs and wait one second */
3837         if (adapter->num_vfs) {
3838                 /* ping all the active vfs to let them know we are going down */
3839                 ixgbe_ping_all_vfs(adapter);
3840
3841                 /* Disable all VFTE/VFRE TX/RX */
3842                 ixgbe_disable_tx_rx(adapter);
3843
3844                 /* Mark all the VFs as inactive */
3845                 for (i = 0 ; i < adapter->num_vfs; i++)
3846                         adapter->vfinfo[i].clear_to_send = 0;
3847         }
3848
3849         /* disable receives */
3850         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3851         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3852
3853         IXGBE_WRITE_FLUSH(hw);
3854         msleep(10);
3855
3856         netif_tx_stop_all_queues(netdev);
3857
3858         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3859         del_timer_sync(&adapter->sfp_timer);
3860         del_timer_sync(&adapter->watchdog_timer);
3861         cancel_work_sync(&adapter->watchdog_task);
3862
3863         netif_carrier_off(netdev);
3864         netif_tx_disable(netdev);
3865
3866         ixgbe_irq_disable(adapter);
3867
3868         ixgbe_napi_disable_all(adapter);
3869
3870         /* Cleanup the affinity_hint CPU mask memory and callback */
3871         for (i = 0; i < num_q_vectors; i++) {
3872                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3873                 /* clear the affinity_mask in the IRQ descriptor */
3874                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3875                 /* release the CPU mask memory */
3876                 free_cpumask_var(q_vector->affinity_mask);
3877         }
3878
3879         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3880             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3881                 cancel_work_sync(&adapter->fdir_reinit_task);
3882
3883         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3884                 cancel_work_sync(&adapter->check_overtemp_task);
3885
3886         /* disable transmits in the hardware now that interrupts are off */
3887         for (i = 0; i < adapter->num_tx_queues; i++) {
3888                 j = adapter->tx_ring[i]->reg_idx;
3889                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3890                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3891                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3892         }
3893         /* Disable the Tx DMA engine on 82599 */
3894         if (hw->mac.type == ixgbe_mac_82599EB)
3895                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3896                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3897                                  ~IXGBE_DMATXCTL_TE));
3898
3899         /* power down the optics */
3900         if (hw->phy.multispeed_fiber)
3901                 hw->mac.ops.disable_tx_laser(hw);
3902
3903         /* clear n-tuple filters that are cached */
3904         ethtool_ntuple_flush(netdev);
3905
3906         if (!pci_channel_offline(adapter->pdev))
3907                 ixgbe_reset(adapter);
3908         ixgbe_clean_all_tx_rings(adapter);
3909         ixgbe_clean_all_rx_rings(adapter);
3910
3911 #ifdef CONFIG_IXGBE_DCA
3912         /* since we reset the hardware DCA settings were cleared */
3913         ixgbe_setup_dca(adapter);
3914 #endif
3915 }
3916
3917 /**
3918  * ixgbe_poll - NAPI Rx polling callback
3919  * @napi: structure for representing this polling device
3920  * @budget: how many packets driver is allowed to clean
3921  *
3922  * This function is used for legacy and MSI, NAPI mode
3923  **/
3924 static int ixgbe_poll(struct napi_struct *napi, int budget)
3925 {
3926         struct ixgbe_q_vector *q_vector =
3927                                 container_of(napi, struct ixgbe_q_vector, napi);
3928         struct ixgbe_adapter *adapter = q_vector->adapter;
3929         int tx_clean_complete, work_done = 0;
3930
3931 #ifdef CONFIG_IXGBE_DCA
3932         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3933                 ixgbe_update_dca(q_vector);
3934 #endif
3935
3936         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3937         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3938
3939         if (!tx_clean_complete)
3940                 work_done = budget;
3941
3942         /* If budget not fully consumed, exit the polling mode */
3943         if (work_done < budget) {
3944                 napi_complete(napi);
3945                 if (adapter->rx_itr_setting & 1)
3946                         ixgbe_set_itr(adapter);
3947                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3948                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3949         }
3950         return work_done;
3951 }
3952
3953 /**
3954  * ixgbe_tx_timeout - Respond to a Tx Hang
3955  * @netdev: network interface device structure
3956  **/
3957 static void ixgbe_tx_timeout(struct net_device *netdev)
3958 {
3959         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3960
3961         /* Do the reset outside of interrupt context */
3962         schedule_work(&adapter->reset_task);
3963 }
3964
3965 static void ixgbe_reset_task(struct work_struct *work)
3966 {
3967         struct ixgbe_adapter *adapter;
3968         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3969
3970         /* If we're already down or resetting, just bail */
3971         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3972             test_bit(__IXGBE_RESETTING, &adapter->state))
3973                 return;
3974
3975         adapter->tx_timeout_count++;
3976
3977         ixgbe_dump(adapter);
3978         netdev_err(adapter->netdev, "Reset adapter\n");
3979         ixgbe_reinit_locked(adapter);
3980 }
3981
3982 #ifdef CONFIG_IXGBE_DCB
3983 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3984 {
3985         bool ret = false;
3986         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3987
3988         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3989                 return ret;
3990
3991         f->mask = 0x7 << 3;
3992         adapter->num_rx_queues = f->indices;
3993         adapter->num_tx_queues = f->indices;
3994         ret = true;
3995
3996         return ret;
3997 }
3998 #endif
3999
4000 /**
4001  * ixgbe_set_rss_queues: Allocate queues for RSS
4002  * @adapter: board private structure to initialize
4003  *
4004  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4005  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4006  *
4007  **/
4008 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4009 {
4010         bool ret = false;
4011         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4012
4013         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4014                 f->mask = 0xF;
4015                 adapter->num_rx_queues = f->indices;
4016                 adapter->num_tx_queues = f->indices;
4017                 ret = true;
4018         } else {
4019                 ret = false;
4020         }
4021
4022         return ret;
4023 }
4024
4025 /**
4026  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4027  * @adapter: board private structure to initialize
4028  *
4029  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4030  * to the original CPU that initiated the Tx session.  This runs in addition
4031  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4032  * Rx load across CPUs using RSS.
4033  *
4034  **/
4035 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4036 {
4037         bool ret = false;
4038         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4039
4040         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4041         f_fdir->mask = 0;
4042
4043         /* Flow Director must have RSS enabled */
4044         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4045             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4046              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4047                 adapter->num_tx_queues = f_fdir->indices;
4048                 adapter->num_rx_queues = f_fdir->indices;
4049                 ret = true;
4050         } else {
4051                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4052                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4053         }
4054         return ret;
4055 }
4056
4057 #ifdef IXGBE_FCOE
4058 /**
4059  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4060  * @adapter: board private structure to initialize
4061  *
4062  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4063  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4064  * rx queues out of the max number of rx queues, instead, it is used as the
4065  * index of the first rx queue used by FCoE.
4066  *
4067  **/
4068 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4069 {
4070         bool ret = false;
4071         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4072
4073         f->indices = min((int)num_online_cpus(), f->indices);
4074         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4075                 adapter->num_rx_queues = 1;
4076                 adapter->num_tx_queues = 1;
4077 #ifdef CONFIG_IXGBE_DCB
4078                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4079                         e_info(probe, "FCoE enabled with DCB\n");
4080                         ixgbe_set_dcb_queues(adapter);
4081                 }
4082 #endif
4083                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4084                         e_info(probe, "FCoE enabled with RSS\n");
4085                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4086                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4087                                 ixgbe_set_fdir_queues(adapter);
4088                         else
4089                                 ixgbe_set_rss_queues(adapter);
4090                 }
4091                 /* adding FCoE rx rings to the end */
4092                 f->mask = adapter->num_rx_queues;
4093                 adapter->num_rx_queues += f->indices;
4094                 adapter->num_tx_queues += f->indices;
4095
4096                 ret = true;
4097         }
4098
4099         return ret;
4100 }
4101
4102 #endif /* IXGBE_FCOE */
4103 /**
4104  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4105  * @adapter: board private structure to initialize
4106  *
4107  * IOV doesn't actually use anything, so just NAK the
4108  * request for now and let the other queue routines
4109  * figure out what to do.
4110  */
4111 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4112 {
4113         return false;
4114 }
4115
4116 /*
4117  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4118  * @adapter: board private structure to initialize
4119  *
4120  * This is the top level queue allocation routine.  The order here is very
4121  * important, starting with the "most" number of features turned on at once,
4122  * and ending with the smallest set of features.  This way large combinations
4123  * can be allocated if they're turned on, and smaller combinations are the
4124  * fallthrough conditions.
4125  *
4126  **/
4127 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4128 {
4129         /* Start with base case */
4130         adapter->num_rx_queues = 1;
4131         adapter->num_tx_queues = 1;
4132         adapter->num_rx_pools = adapter->num_rx_queues;
4133         adapter->num_rx_queues_per_pool = 1;
4134
4135         if (ixgbe_set_sriov_queues(adapter))
4136                 goto done;
4137
4138 #ifdef IXGBE_FCOE
4139         if (ixgbe_set_fcoe_queues(adapter))
4140                 goto done;
4141
4142 #endif /* IXGBE_FCOE */
4143 #ifdef CONFIG_IXGBE_DCB
4144         if (ixgbe_set_dcb_queues(adapter))
4145                 goto done;
4146
4147 #endif
4148         if (ixgbe_set_fdir_queues(adapter))
4149                 goto done;
4150
4151         if (ixgbe_set_rss_queues(adapter))
4152                 goto done;
4153
4154         /* fallback to base case */
4155         adapter->num_rx_queues = 1;
4156         adapter->num_tx_queues = 1;
4157
4158 done:
4159         /* Notify the stack of the (possibly) reduced queue counts. */
4160         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4161         return netif_set_real_num_rx_queues(adapter->netdev,
4162                                             adapter->num_rx_queues);
4163 }
4164
4165 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4166                                        int vectors)
4167 {
4168         int err, vector_threshold;
4169
4170         /* We'll want at least 3 (vector_threshold):
4171          * 1) TxQ[0] Cleanup
4172          * 2) RxQ[0] Cleanup
4173          * 3) Other (Link Status Change, etc.)
4174          * 4) TCP Timer (optional)
4175          */
4176         vector_threshold = MIN_MSIX_COUNT;
4177
4178         /* The more we get, the more we will assign to Tx/Rx Cleanup
4179          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4180          * Right now, we simply care about how many we'll get; we'll
4181          * set them up later while requesting irq's.
4182          */
4183         while (vectors >= vector_threshold) {
4184                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4185                                       vectors);
4186                 if (!err) /* Success in acquiring all requested vectors. */
4187                         break;
4188                 else if (err < 0)
4189                         vectors = 0; /* Nasty failure, quit now */
4190                 else /* err == number of vectors we should try again with */
4191                         vectors = err;
4192         }
4193
4194         if (vectors < vector_threshold) {
4195                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4196                  * This just means we'll go with either a single MSI
4197                  * vector or fall back to legacy interrupts.
4198                  */
4199                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4200                              "Unable to allocate MSI-X interrupts\n");
4201                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4202                 kfree(adapter->msix_entries);
4203                 adapter->msix_entries = NULL;
4204         } else {
4205                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4206                 /*
4207                  * Adjust for only the vectors we'll use, which is minimum
4208                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4209                  * vectors we were allocated.
4210                  */
4211                 adapter->num_msix_vectors = min(vectors,
4212                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4213         }
4214 }
4215
4216 /**
4217  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4218  * @adapter: board private structure to initialize
4219  *
4220  * Cache the descriptor ring offsets for RSS to the assigned rings.
4221  *
4222  **/
4223 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4224 {
4225         int i;
4226         bool ret = false;
4227
4228         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4229                 for (i = 0; i < adapter->num_rx_queues; i++)
4230                         adapter->rx_ring[i]->reg_idx = i;
4231                 for (i = 0; i < adapter->num_tx_queues; i++)
4232                         adapter->tx_ring[i]->reg_idx = i;
4233                 ret = true;
4234         } else {
4235                 ret = false;
4236         }
4237
4238         return ret;
4239 }
4240
4241 #ifdef CONFIG_IXGBE_DCB
4242 /**
4243  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4244  * @adapter: board private structure to initialize
4245  *
4246  * Cache the descriptor ring offsets for DCB to the assigned rings.
4247  *
4248  **/
4249 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4250 {
4251         int i;
4252         bool ret = false;
4253         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4254
4255         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4256                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4257                         /* the number of queues is assumed to be symmetric */
4258                         for (i = 0; i < dcb_i; i++) {
4259                                 adapter->rx_ring[i]->reg_idx = i << 3;
4260                                 adapter->tx_ring[i]->reg_idx = i << 2;
4261                         }
4262                         ret = true;
4263                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4264                         if (dcb_i == 8) {
4265                                 /*
4266                                  * Tx TC0 starts at: descriptor queue 0
4267                                  * Tx TC1 starts at: descriptor queue 32
4268                                  * Tx TC2 starts at: descriptor queue 64
4269                                  * Tx TC3 starts at: descriptor queue 80
4270                                  * Tx TC4 starts at: descriptor queue 96
4271                                  * Tx TC5 starts at: descriptor queue 104
4272                                  * Tx TC6 starts at: descriptor queue 112
4273                                  * Tx TC7 starts at: descriptor queue 120
4274                                  *
4275                                  * Rx TC0-TC7 are offset by 16 queues each
4276                                  */
4277                                 for (i = 0; i < 3; i++) {
4278                                         adapter->tx_ring[i]->reg_idx = i << 5;
4279                                         adapter->rx_ring[i]->reg_idx = i << 4;
4280                                 }
4281                                 for ( ; i < 5; i++) {
4282                                         adapter->tx_ring[i]->reg_idx =
4283                                                                  ((i + 2) << 4);
4284                                         adapter->rx_ring[i]->reg_idx = i << 4;
4285                                 }
4286                                 for ( ; i < dcb_i; i++) {
4287                                         adapter->tx_ring[i]->reg_idx =
4288                                                                  ((i + 8) << 3);
4289                                         adapter->rx_ring[i]->reg_idx = i << 4;
4290                                 }
4291
4292                                 ret = true;
4293                         } else if (dcb_i == 4) {
4294                                 /*
4295                                  * Tx TC0 starts at: descriptor queue 0
4296                                  * Tx TC1 starts at: descriptor queue 64
4297                                  * Tx TC2 starts at: descriptor queue 96
4298                                  * Tx TC3 starts at: descriptor queue 112
4299                                  *
4300                                  * Rx TC0-TC3 are offset by 32 queues each
4301                                  */
4302                                 adapter->tx_ring[0]->reg_idx = 0;
4303                                 adapter->tx_ring[1]->reg_idx = 64;
4304                                 adapter->tx_ring[2]->reg_idx = 96;
4305                                 adapter->tx_ring[3]->reg_idx = 112;
4306                                 for (i = 0 ; i < dcb_i; i++)
4307                                         adapter->rx_ring[i]->reg_idx = i << 5;
4308
4309                                 ret = true;
4310                         } else {
4311                                 ret = false;
4312                         }
4313                 } else {
4314                         ret = false;
4315                 }
4316         } else {
4317                 ret = false;
4318         }
4319
4320         return ret;
4321 }
4322 #endif
4323
4324 /**
4325  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4326  * @adapter: board private structure to initialize
4327  *
4328  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4329  *
4330  **/
4331 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4332 {
4333         int i;
4334         bool ret = false;
4335
4336         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4337             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4338              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4339                 for (i = 0; i < adapter->num_rx_queues; i++)
4340                         adapter->rx_ring[i]->reg_idx = i;
4341                 for (i = 0; i < adapter->num_tx_queues; i++)
4342                         adapter->tx_ring[i]->reg_idx = i;
4343                 ret = true;
4344         }
4345
4346         return ret;
4347 }
4348
4349 #ifdef IXGBE_FCOE
4350 /**
4351  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4352  * @adapter: board private structure to initialize
4353  *
4354  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4355  *
4356  */
4357 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4358 {
4359         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4360         bool ret = false;
4361         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4362
4363         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4364 #ifdef CONFIG_IXGBE_DCB
4365                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4366                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4367
4368                         ixgbe_cache_ring_dcb(adapter);
4369                         /* find out queues in TC for FCoE */
4370                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4371                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4372                         /*
4373                          * In 82599, the number of Tx queues for each traffic
4374                          * class for both 8-TC and 4-TC modes are:
4375                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4376                          * 8 TCs:  32  32  16  16   8   8   8   8
4377                          * 4 TCs:  64  64  32  32
4378                          * We have max 8 queues for FCoE, where 8 the is
4379                          * FCoE redirection table size. If TC for FCoE is
4380                          * less than or equal to TC3, we have enough queues
4381                          * to add max of 8 queues for FCoE, so we start FCoE
4382                          * tx descriptor from the next one, i.e., reg_idx + 1.
4383                          * If TC for FCoE is above TC3, implying 8 TC mode,
4384                          * and we need 8 for FCoE, we have to take all queues
4385                          * in that traffic class for FCoE.
4386                          */
4387                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4388                                 fcoe_tx_i--;
4389                 }
4390 #endif /* CONFIG_IXGBE_DCB */
4391                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4392                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4393                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4394                                 ixgbe_cache_ring_fdir(adapter);
4395                         else
4396                                 ixgbe_cache_ring_rss(adapter);
4397
4398                         fcoe_rx_i = f->mask;
4399                         fcoe_tx_i = f->mask;
4400                 }
4401                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4402                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4403                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4404                 }
4405                 ret = true;
4406         }
4407         return ret;
4408 }
4409
4410 #endif /* IXGBE_FCOE */
4411 /**
4412  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4413  * @adapter: board private structure to initialize
4414  *
4415  * SR-IOV doesn't use any descriptor rings but changes the default if
4416  * no other mapping is used.
4417  *
4418  */
4419 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4420 {
4421         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4422         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4423         if (adapter->num_vfs)
4424                 return true;
4425         else
4426                 return false;
4427 }
4428
4429 /**
4430  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4431  * @adapter: board private structure to initialize
4432  *
4433  * Once we know the feature-set enabled for the device, we'll cache
4434  * the register offset the descriptor ring is assigned to.
4435  *
4436  * Note, the order the various feature calls is important.  It must start with
4437  * the "most" features enabled at the same time, then trickle down to the
4438  * least amount of features turned on at once.
4439  **/
4440 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4441 {
4442         /* start with default case */
4443         adapter->rx_ring[0]->reg_idx = 0;
4444         adapter->tx_ring[0]->reg_idx = 0;
4445
4446         if (ixgbe_cache_ring_sriov(adapter))
4447                 return;
4448
4449 #ifdef IXGBE_FCOE
4450         if (ixgbe_cache_ring_fcoe(adapter))
4451                 return;
4452
4453 #endif /* IXGBE_FCOE */
4454 #ifdef CONFIG_IXGBE_DCB
4455         if (ixgbe_cache_ring_dcb(adapter))
4456                 return;
4457
4458 #endif
4459         if (ixgbe_cache_ring_fdir(adapter))
4460                 return;
4461
4462         if (ixgbe_cache_ring_rss(adapter))
4463                 return;
4464 }
4465
4466 /**
4467  * ixgbe_alloc_queues - Allocate memory for all rings
4468  * @adapter: board private structure to initialize
4469  *
4470  * We allocate one ring per queue at run-time since we don't know the
4471  * number of queues at compile-time.  The polling_netdev array is
4472  * intended for Multiqueue, but should work fine with a single queue.
4473  **/
4474 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4475 {
4476         int i;
4477         int rx_count;
4478         int orig_node = adapter->node;
4479
4480         for (i = 0; i < adapter->num_tx_queues; i++) {
4481                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4482                 if (orig_node == -1) {
4483                         int cur_node = next_online_node(adapter->node);
4484                         if (cur_node == MAX_NUMNODES)
4485                                 cur_node = first_online_node;
4486                         adapter->node = cur_node;
4487                 }
4488                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4489                                     adapter->node);
4490                 if (!ring)
4491                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4492                 if (!ring)
4493                         goto err_tx_ring_allocation;
4494                 ring->count = adapter->tx_ring_count;
4495                 ring->queue_index = i;
4496                 ring->dev = &adapter->pdev->dev;
4497                 ring->netdev = adapter->netdev;
4498                 ring->numa_node = adapter->node;
4499
4500                 adapter->tx_ring[i] = ring;
4501         }
4502
4503         /* Restore the adapter's original node */
4504         adapter->node = orig_node;
4505
4506         rx_count = adapter->rx_ring_count;
4507         for (i = 0; i < adapter->num_rx_queues; i++) {
4508                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4509                 if (orig_node == -1) {
4510                         int cur_node = next_online_node(adapter->node);
4511                         if (cur_node == MAX_NUMNODES)
4512                                 cur_node = first_online_node;
4513                         adapter->node = cur_node;
4514                 }
4515                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4516                                     adapter->node);
4517                 if (!ring)
4518                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4519                 if (!ring)
4520                         goto err_rx_ring_allocation;
4521                 ring->count = rx_count;
4522                 ring->queue_index = i;
4523                 ring->dev = &adapter->pdev->dev;
4524                 ring->netdev = adapter->netdev;
4525                 ring->numa_node = adapter->node;
4526
4527                 adapter->rx_ring[i] = ring;
4528         }
4529
4530         /* Restore the adapter's original node */
4531         adapter->node = orig_node;
4532
4533         ixgbe_cache_ring_register(adapter);
4534
4535         return 0;
4536
4537 err_rx_ring_allocation:
4538         for (i = 0; i < adapter->num_tx_queues; i++)
4539                 kfree(adapter->tx_ring[i]);
4540 err_tx_ring_allocation:
4541         return -ENOMEM;
4542 }
4543
4544 /**
4545  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4546  * @adapter: board private structure to initialize
4547  *
4548  * Attempt to configure the interrupts using the best available
4549  * capabilities of the hardware and the kernel.
4550  **/
4551 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4552 {
4553         struct ixgbe_hw *hw = &adapter->hw;
4554         int err = 0;
4555         int vector, v_budget;
4556
4557         /*
4558          * It's easy to be greedy for MSI-X vectors, but it really
4559          * doesn't do us much good if we have a lot more vectors
4560          * than CPU's.  So let's be conservative and only ask for
4561          * (roughly) the same number of vectors as there are CPU's.
4562          */
4563         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4564                        (int)num_online_cpus()) + NON_Q_VECTORS;
4565
4566         /*
4567          * At the same time, hardware can only support a maximum of
4568          * hw.mac->max_msix_vectors vectors.  With features
4569          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4570          * descriptor queues supported by our device.  Thus, we cap it off in
4571          * those rare cases where the cpu count also exceeds our vector limit.
4572          */
4573         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4574
4575         /* A failure in MSI-X entry allocation isn't fatal, but it does
4576          * mean we disable MSI-X capabilities of the adapter. */
4577         adapter->msix_entries = kcalloc(v_budget,
4578                                         sizeof(struct msix_entry), GFP_KERNEL);
4579         if (adapter->msix_entries) {
4580                 for (vector = 0; vector < v_budget; vector++)
4581                         adapter->msix_entries[vector].entry = vector;
4582
4583                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4584
4585                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4586                         goto out;
4587         }
4588
4589         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4590         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4591         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4592         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4593         adapter->atr_sample_rate = 0;
4594         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4595                 ixgbe_disable_sriov(adapter);
4596
4597         err = ixgbe_set_num_queues(adapter);
4598         if (err)
4599                 return err;
4600
4601         err = pci_enable_msi(adapter->pdev);
4602         if (!err) {
4603                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4604         } else {
4605                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4606                              "Unable to allocate MSI interrupt, "
4607                              "falling back to legacy.  Error: %d\n", err);
4608                 /* reset err */
4609                 err = 0;
4610         }
4611
4612 out:
4613         return err;
4614 }
4615
4616 /**
4617  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4618  * @adapter: board private structure to initialize
4619  *
4620  * We allocate one q_vector per queue interrupt.  If allocation fails we
4621  * return -ENOMEM.
4622  **/
4623 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4624 {
4625         int q_idx, num_q_vectors;
4626         struct ixgbe_q_vector *q_vector;
4627         int napi_vectors;
4628         int (*poll)(struct napi_struct *, int);
4629
4630         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4631                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4632                 napi_vectors = adapter->num_rx_queues;
4633                 poll = &ixgbe_clean_rxtx_many;
4634         } else {
4635                 num_q_vectors = 1;
4636                 napi_vectors = 1;
4637                 poll = &ixgbe_poll;
4638         }
4639
4640         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4641                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4642                                         GFP_KERNEL, adapter->node);
4643                 if (!q_vector)
4644                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4645                                            GFP_KERNEL);
4646                 if (!q_vector)
4647                         goto err_out;
4648                 q_vector->adapter = adapter;
4649                 if (q_vector->txr_count && !q_vector->rxr_count)
4650                         q_vector->eitr = adapter->tx_eitr_param;
4651                 else
4652                         q_vector->eitr = adapter->rx_eitr_param;
4653                 q_vector->v_idx = q_idx;
4654                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4655                 adapter->q_vector[q_idx] = q_vector;
4656         }
4657
4658         return 0;
4659
4660 err_out:
4661         while (q_idx) {
4662                 q_idx--;
4663                 q_vector = adapter->q_vector[q_idx];
4664                 netif_napi_del(&q_vector->napi);
4665                 kfree(q_vector);
4666                 adapter->q_vector[q_idx] = NULL;
4667         }
4668         return -ENOMEM;
4669 }
4670
4671 /**
4672  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4673  * @adapter: board private structure to initialize
4674  *
4675  * This function frees the memory allocated to the q_vectors.  In addition if
4676  * NAPI is enabled it will delete any references to the NAPI struct prior
4677  * to freeing the q_vector.
4678  **/
4679 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4680 {
4681         int q_idx, num_q_vectors;
4682
4683         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4684                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4685         else
4686                 num_q_vectors = 1;
4687
4688         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4689                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4690                 adapter->q_vector[q_idx] = NULL;
4691                 netif_napi_del(&q_vector->napi);
4692                 kfree(q_vector);
4693         }
4694 }
4695
4696 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4697 {
4698         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4699                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4700                 pci_disable_msix(adapter->pdev);
4701                 kfree(adapter->msix_entries);
4702                 adapter->msix_entries = NULL;
4703         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4704                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4705                 pci_disable_msi(adapter->pdev);
4706         }
4707 }
4708
4709 /**
4710  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4711  * @adapter: board private structure to initialize
4712  *
4713  * We determine which interrupt scheme to use based on...
4714  * - Kernel support (MSI, MSI-X)
4715  *   - which can be user-defined (via MODULE_PARAM)
4716  * - Hardware queue count (num_*_queues)
4717  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4718  **/
4719 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4720 {
4721         int err;
4722
4723         /* Number of supported queues */
4724         err = ixgbe_set_num_queues(adapter);
4725         if (err)
4726                 return err;
4727
4728         err = ixgbe_set_interrupt_capability(adapter);
4729         if (err) {
4730                 e_dev_err("Unable to setup interrupt capabilities\n");
4731                 goto err_set_interrupt;
4732         }
4733
4734         err = ixgbe_alloc_q_vectors(adapter);
4735         if (err) {
4736                 e_dev_err("Unable to allocate memory for queue vectors\n");
4737                 goto err_alloc_q_vectors;
4738         }
4739
4740         err = ixgbe_alloc_queues(adapter);
4741         if (err) {
4742                 e_dev_err("Unable to allocate memory for queues\n");
4743                 goto err_alloc_queues;
4744         }
4745
4746         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4747                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4748                    adapter->num_rx_queues, adapter->num_tx_queues);
4749
4750         set_bit(__IXGBE_DOWN, &adapter->state);
4751
4752         return 0;
4753
4754 err_alloc_queues:
4755         ixgbe_free_q_vectors(adapter);
4756 err_alloc_q_vectors:
4757         ixgbe_reset_interrupt_capability(adapter);
4758 err_set_interrupt:
4759         return err;
4760 }
4761
4762 static void ring_free_rcu(struct rcu_head *head)
4763 {
4764         kfree(container_of(head, struct ixgbe_ring, rcu));
4765 }
4766
4767 /**
4768  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4769  * @adapter: board private structure to clear interrupt scheme on
4770  *
4771  * We go through and clear interrupt specific resources and reset the structure
4772  * to pre-load conditions
4773  **/
4774 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4775 {
4776         int i;
4777
4778         for (i = 0; i < adapter->num_tx_queues; i++) {
4779                 kfree(adapter->tx_ring[i]);
4780                 adapter->tx_ring[i] = NULL;
4781         }
4782         for (i = 0; i < adapter->num_rx_queues; i++) {
4783                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4784
4785                 /* ixgbe_get_stats64() might access this ring, we must wait
4786                  * a grace period before freeing it.
4787                  */
4788                 call_rcu(&ring->rcu, ring_free_rcu);
4789                 adapter->rx_ring[i] = NULL;
4790         }
4791
4792         ixgbe_free_q_vectors(adapter);
4793         ixgbe_reset_interrupt_capability(adapter);
4794 }
4795
4796 /**
4797  * ixgbe_sfp_timer - worker thread to find a missing module
4798  * @data: pointer to our adapter struct
4799  **/
4800 static void ixgbe_sfp_timer(unsigned long data)
4801 {
4802         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4803
4804         /*
4805          * Do the sfp_timer outside of interrupt context due to the
4806          * delays that sfp+ detection requires
4807          */
4808         schedule_work(&adapter->sfp_task);
4809 }
4810
4811 /**
4812  * ixgbe_sfp_task - worker thread to find a missing module
4813  * @work: pointer to work_struct containing our data
4814  **/
4815 static void ixgbe_sfp_task(struct work_struct *work)
4816 {
4817         struct ixgbe_adapter *adapter = container_of(work,
4818                                                      struct ixgbe_adapter,
4819                                                      sfp_task);
4820         struct ixgbe_hw *hw = &adapter->hw;
4821
4822         if ((hw->phy.type == ixgbe_phy_nl) &&
4823             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4824                 s32 ret = hw->phy.ops.identify_sfp(hw);
4825                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4826                         goto reschedule;
4827                 ret = hw->phy.ops.reset(hw);
4828                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4829                         e_dev_err("failed to initialize because an unsupported "
4830                                   "SFP+ module type was detected.\n");
4831                         e_dev_err("Reload the driver after installing a "
4832                                   "supported module.\n");
4833                         unregister_netdev(adapter->netdev);
4834                 } else {
4835                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4836                 }
4837                 /* don't need this routine any more */
4838                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4839         }
4840         return;
4841 reschedule:
4842         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4843                 mod_timer(&adapter->sfp_timer,
4844                           round_jiffies(jiffies + (2 * HZ)));
4845 }
4846
4847 /**
4848  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4849  * @adapter: board private structure to initialize
4850  *
4851  * ixgbe_sw_init initializes the Adapter private data structure.
4852  * Fields are initialized based on PCI device information and
4853  * OS network device settings (MTU size).
4854  **/
4855 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4856 {
4857         struct ixgbe_hw *hw = &adapter->hw;
4858         struct pci_dev *pdev = adapter->pdev;
4859         struct net_device *dev = adapter->netdev;
4860         unsigned int rss;
4861 #ifdef CONFIG_IXGBE_DCB
4862         int j;
4863         struct tc_configuration *tc;
4864 #endif
4865         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4866
4867         /* PCI config space info */
4868
4869         hw->vendor_id = pdev->vendor;
4870         hw->device_id = pdev->device;
4871         hw->revision_id = pdev->revision;
4872         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4873         hw->subsystem_device_id = pdev->subsystem_device;
4874
4875         /* Set capability flags */
4876         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4877         adapter->ring_feature[RING_F_RSS].indices = rss;
4878         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4879         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4880         if (hw->mac.type == ixgbe_mac_82598EB) {
4881                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4882                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4883                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4884         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4885                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4886                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4887                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4888                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4889                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4890                 if (dev->features & NETIF_F_NTUPLE) {
4891                         /* Flow Director perfect filter enabled */
4892                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4893                         adapter->atr_sample_rate = 0;
4894                         spin_lock_init(&adapter->fdir_perfect_lock);
4895                 } else {
4896                         /* Flow Director hash filters enabled */
4897                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4898                         adapter->atr_sample_rate = 20;
4899                 }
4900                 adapter->ring_feature[RING_F_FDIR].indices =
4901                                                          IXGBE_MAX_FDIR_INDICES;
4902                 adapter->fdir_pballoc = 0;
4903 #ifdef IXGBE_FCOE
4904                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4905                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4906                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4907 #ifdef CONFIG_IXGBE_DCB
4908                 /* Default traffic class to use for FCoE */
4909                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4910                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4911 #endif
4912 #endif /* IXGBE_FCOE */
4913         }
4914
4915 #ifdef CONFIG_IXGBE_DCB
4916         /* Configure DCB traffic classes */
4917         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4918                 tc = &adapter->dcb_cfg.tc_config[j];
4919                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4920                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4921                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4922                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4923                 tc->dcb_pfc = pfc_disabled;
4924         }
4925         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4926         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4927         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4928         adapter->dcb_cfg.pfc_mode_enable = false;
4929         adapter->dcb_cfg.round_robin_enable = false;
4930         adapter->dcb_set_bitmap = 0x00;
4931         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4932                            adapter->ring_feature[RING_F_DCB].indices);
4933
4934 #endif
4935
4936         /* default flow control settings */
4937         hw->fc.requested_mode = ixgbe_fc_full;
4938         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4939 #ifdef CONFIG_DCB
4940         adapter->last_lfc_mode = hw->fc.current_mode;
4941 #endif
4942         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4943         hw->fc.low_water = FC_LOW_WATER(max_frame);
4944         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4945         hw->fc.send_xon = true;
4946         hw->fc.disable_fc_autoneg = false;
4947
4948         /* enable itr by default in dynamic mode */
4949         adapter->rx_itr_setting = 1;
4950         adapter->rx_eitr_param = 20000;
4951         adapter->tx_itr_setting = 1;
4952         adapter->tx_eitr_param = 10000;
4953
4954         /* set defaults for eitr in MegaBytes */
4955         adapter->eitr_low = 10;
4956         adapter->eitr_high = 20;
4957
4958         /* set default ring sizes */
4959         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4960         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4961
4962         /* initialize eeprom parameters */
4963         if (ixgbe_init_eeprom_params_generic(hw)) {
4964                 e_dev_err("EEPROM initialization failed\n");
4965                 return -EIO;
4966         }
4967
4968         /* enable rx csum by default */
4969         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4970
4971         /* get assigned NUMA node */
4972         adapter->node = dev_to_node(&pdev->dev);
4973
4974         set_bit(__IXGBE_DOWN, &adapter->state);
4975
4976         return 0;
4977 }
4978
4979 /**
4980  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4981  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4982  *
4983  * Return 0 on success, negative on failure
4984  **/
4985 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4986 {
4987         struct device *dev = tx_ring->dev;
4988         int size;
4989
4990         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4991         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4992         if (!tx_ring->tx_buffer_info)
4993                 tx_ring->tx_buffer_info = vmalloc(size);
4994         if (!tx_ring->tx_buffer_info)
4995                 goto err;
4996         memset(tx_ring->tx_buffer_info, 0, size);
4997
4998         /* round up to nearest 4K */
4999         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5000         tx_ring->size = ALIGN(tx_ring->size, 4096);
5001
5002         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5003                                            &tx_ring->dma, GFP_KERNEL);
5004         if (!tx_ring->desc)
5005                 goto err;
5006
5007         tx_ring->next_to_use = 0;
5008         tx_ring->next_to_clean = 0;
5009         tx_ring->work_limit = tx_ring->count;
5010         return 0;
5011
5012 err:
5013         vfree(tx_ring->tx_buffer_info);
5014         tx_ring->tx_buffer_info = NULL;
5015         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5016         return -ENOMEM;
5017 }
5018
5019 /**
5020  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5021  * @adapter: board private structure
5022  *
5023  * If this function returns with an error, then it's possible one or
5024  * more of the rings is populated (while the rest are not).  It is the
5025  * callers duty to clean those orphaned rings.
5026  *
5027  * Return 0 on success, negative on failure
5028  **/
5029 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5030 {
5031         int i, err = 0;
5032
5033         for (i = 0; i < adapter->num_tx_queues; i++) {
5034                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5035                 if (!err)
5036                         continue;
5037                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5038                 break;
5039         }
5040
5041         return err;
5042 }
5043
5044 /**
5045  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5046  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5047  *
5048  * Returns 0 on success, negative on failure
5049  **/
5050 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5051 {
5052         struct device *dev = rx_ring->dev;
5053         int size;
5054
5055         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5056         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5057         if (!rx_ring->rx_buffer_info)
5058                 rx_ring->rx_buffer_info = vmalloc(size);
5059         if (!rx_ring->rx_buffer_info)
5060                 goto err;
5061         memset(rx_ring->rx_buffer_info, 0, size);
5062
5063         /* Round up to nearest 4K */
5064         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5065         rx_ring->size = ALIGN(rx_ring->size, 4096);
5066
5067         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5068                                            &rx_ring->dma, GFP_KERNEL);
5069
5070         if (!rx_ring->desc)
5071                 goto err;
5072
5073         rx_ring->next_to_clean = 0;
5074         rx_ring->next_to_use = 0;
5075
5076         return 0;
5077 err:
5078         vfree(rx_ring->rx_buffer_info);
5079         rx_ring->rx_buffer_info = NULL;
5080         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5081         return -ENOMEM;
5082 }
5083
5084 /**
5085  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5086  * @adapter: board private structure
5087  *
5088  * If this function returns with an error, then it's possible one or
5089  * more of the rings is populated (while the rest are not).  It is the
5090  * callers duty to clean those orphaned rings.
5091  *
5092  * Return 0 on success, negative on failure
5093  **/
5094 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5095 {
5096         int i, err = 0;
5097
5098         for (i = 0; i < adapter->num_rx_queues; i++) {
5099                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5100                 if (!err)
5101                         continue;
5102                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5103                 break;
5104         }
5105
5106         return err;
5107 }
5108
5109 /**
5110  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5111  * @tx_ring: Tx descriptor ring for a specific queue
5112  *
5113  * Free all transmit software resources
5114  **/
5115 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5116 {
5117         ixgbe_clean_tx_ring(tx_ring);
5118
5119         vfree(tx_ring->tx_buffer_info);
5120         tx_ring->tx_buffer_info = NULL;
5121
5122         /* if not set, then don't free */
5123         if (!tx_ring->desc)
5124                 return;
5125
5126         dma_free_coherent(tx_ring->dev, tx_ring->size,
5127                           tx_ring->desc, tx_ring->dma);
5128
5129         tx_ring->desc = NULL;
5130 }
5131
5132 /**
5133  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5134  * @adapter: board private structure
5135  *
5136  * Free all transmit software resources
5137  **/
5138 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5139 {
5140         int i;
5141
5142         for (i = 0; i < adapter->num_tx_queues; i++)
5143                 if (adapter->tx_ring[i]->desc)
5144                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5145 }
5146
5147 /**
5148  * ixgbe_free_rx_resources - Free Rx Resources
5149  * @rx_ring: ring to clean the resources from
5150  *
5151  * Free all receive software resources
5152  **/
5153 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5154 {
5155         ixgbe_clean_rx_ring(rx_ring);
5156
5157         vfree(rx_ring->rx_buffer_info);
5158         rx_ring->rx_buffer_info = NULL;
5159
5160         /* if not set, then don't free */
5161         if (!rx_ring->desc)
5162                 return;
5163
5164         dma_free_coherent(rx_ring->dev, rx_ring->size,
5165                           rx_ring->desc, rx_ring->dma);
5166
5167         rx_ring->desc = NULL;
5168 }
5169
5170 /**
5171  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5172  * @adapter: board private structure
5173  *
5174  * Free all receive software resources
5175  **/
5176 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5177 {
5178         int i;
5179
5180         for (i = 0; i < adapter->num_rx_queues; i++)
5181                 if (adapter->rx_ring[i]->desc)
5182                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5183 }
5184
5185 /**
5186  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5187  * @netdev: network interface device structure
5188  * @new_mtu: new value for maximum frame size
5189  *
5190  * Returns 0 on success, negative on failure
5191  **/
5192 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5193 {
5194         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5195         struct ixgbe_hw *hw = &adapter->hw;
5196         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5197
5198         /* MTU < 68 is an error and causes problems on some kernels */
5199         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5200                 return -EINVAL;
5201
5202         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5203         /* must set new MTU before calling down or up */
5204         netdev->mtu = new_mtu;
5205
5206         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5207         hw->fc.low_water = FC_LOW_WATER(max_frame);
5208
5209         if (netif_running(netdev))
5210                 ixgbe_reinit_locked(adapter);
5211
5212         return 0;
5213 }
5214
5215 /**
5216  * ixgbe_open - Called when a network interface is made active
5217  * @netdev: network interface device structure
5218  *
5219  * Returns 0 on success, negative value on failure
5220  *
5221  * The open entry point is called when a network interface is made
5222  * active by the system (IFF_UP).  At this point all resources needed
5223  * for transmit and receive operations are allocated, the interrupt
5224  * handler is registered with the OS, the watchdog timer is started,
5225  * and the stack is notified that the interface is ready.
5226  **/
5227 static int ixgbe_open(struct net_device *netdev)
5228 {
5229         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5230         int err;
5231
5232         /* disallow open during test */
5233         if (test_bit(__IXGBE_TESTING, &adapter->state))
5234                 return -EBUSY;
5235
5236         netif_carrier_off(netdev);
5237
5238         /* allocate transmit descriptors */
5239         err = ixgbe_setup_all_tx_resources(adapter);
5240         if (err)
5241                 goto err_setup_tx;
5242
5243         /* allocate receive descriptors */
5244         err = ixgbe_setup_all_rx_resources(adapter);
5245         if (err)
5246                 goto err_setup_rx;
5247
5248         ixgbe_configure(adapter);
5249
5250         err = ixgbe_request_irq(adapter);
5251         if (err)
5252                 goto err_req_irq;
5253
5254         err = ixgbe_up_complete(adapter);
5255         if (err)
5256                 goto err_up;
5257
5258         netif_tx_start_all_queues(netdev);
5259
5260         return 0;
5261
5262 err_up:
5263         ixgbe_release_hw_control(adapter);
5264         ixgbe_free_irq(adapter);
5265 err_req_irq:
5266 err_setup_rx:
5267         ixgbe_free_all_rx_resources(adapter);
5268 err_setup_tx:
5269         ixgbe_free_all_tx_resources(adapter);
5270         ixgbe_reset(adapter);
5271
5272         return err;
5273 }
5274
5275 /**
5276  * ixgbe_close - Disables a network interface
5277  * @netdev: network interface device structure
5278  *
5279  * Returns 0, this is not allowed to fail
5280  *
5281  * The close entry point is called when an interface is de-activated
5282  * by the OS.  The hardware is still under the drivers control, but
5283  * needs to be disabled.  A global MAC reset is issued to stop the
5284  * hardware, and all transmit and receive resources are freed.
5285  **/
5286 static int ixgbe_close(struct net_device *netdev)
5287 {
5288         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5289
5290         ixgbe_down(adapter);
5291         ixgbe_free_irq(adapter);
5292
5293         ixgbe_free_all_tx_resources(adapter);
5294         ixgbe_free_all_rx_resources(adapter);
5295
5296         ixgbe_release_hw_control(adapter);
5297
5298         return 0;
5299 }
5300
5301 #ifdef CONFIG_PM
5302 static int ixgbe_resume(struct pci_dev *pdev)
5303 {
5304         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5305         struct net_device *netdev = adapter->netdev;
5306         u32 err;
5307
5308         pci_set_power_state(pdev, PCI_D0);
5309         pci_restore_state(pdev);
5310         /*
5311          * pci_restore_state clears dev->state_saved so call
5312          * pci_save_state to restore it.
5313          */
5314         pci_save_state(pdev);
5315
5316         err = pci_enable_device_mem(pdev);
5317         if (err) {
5318                 e_dev_err("Cannot enable PCI device from suspend\n");
5319                 return err;
5320         }
5321         pci_set_master(pdev);
5322
5323         pci_wake_from_d3(pdev, false);
5324
5325         err = ixgbe_init_interrupt_scheme(adapter);
5326         if (err) {
5327                 e_dev_err("Cannot initialize interrupts for device\n");
5328                 return err;
5329         }
5330
5331         ixgbe_reset(adapter);
5332
5333         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5334
5335         if (netif_running(netdev)) {
5336                 err = ixgbe_open(netdev);
5337                 if (err)
5338                         return err;
5339         }
5340
5341         netif_device_attach(netdev);
5342
5343         return 0;
5344 }
5345 #endif /* CONFIG_PM */
5346
5347 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5348 {
5349         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5350         struct net_device *netdev = adapter->netdev;
5351         struct ixgbe_hw *hw = &adapter->hw;
5352         u32 ctrl, fctrl;
5353         u32 wufc = adapter->wol;
5354 #ifdef CONFIG_PM
5355         int retval = 0;
5356 #endif
5357
5358         netif_device_detach(netdev);
5359
5360         if (netif_running(netdev)) {
5361                 ixgbe_down(adapter);
5362                 ixgbe_free_irq(adapter);
5363                 ixgbe_free_all_tx_resources(adapter);
5364                 ixgbe_free_all_rx_resources(adapter);
5365         }
5366
5367         ixgbe_clear_interrupt_scheme(adapter);
5368
5369 #ifdef CONFIG_PM
5370         retval = pci_save_state(pdev);
5371         if (retval)
5372                 return retval;
5373
5374 #endif
5375         if (wufc) {
5376                 ixgbe_set_rx_mode(netdev);
5377
5378                 /* turn on all-multi mode if wake on multicast is enabled */
5379                 if (wufc & IXGBE_WUFC_MC) {
5380                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5381                         fctrl |= IXGBE_FCTRL_MPE;
5382                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5383                 }
5384
5385                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5386                 ctrl |= IXGBE_CTRL_GIO_DIS;
5387                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5388
5389                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5390         } else {
5391                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5392                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5393         }
5394
5395         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5396                 pci_wake_from_d3(pdev, true);
5397         else
5398                 pci_wake_from_d3(pdev, false);
5399
5400         *enable_wake = !!wufc;
5401
5402         ixgbe_release_hw_control(adapter);
5403
5404         pci_disable_device(pdev);
5405
5406         return 0;
5407 }
5408
5409 #ifdef CONFIG_PM
5410 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5411 {
5412         int retval;
5413         bool wake;
5414
5415         retval = __ixgbe_shutdown(pdev, &wake);
5416         if (retval)
5417                 return retval;
5418
5419         if (wake) {
5420                 pci_prepare_to_sleep(pdev);
5421         } else {
5422                 pci_wake_from_d3(pdev, false);
5423                 pci_set_power_state(pdev, PCI_D3hot);
5424         }
5425
5426         return 0;
5427 }
5428 #endif /* CONFIG_PM */
5429
5430 static void ixgbe_shutdown(struct pci_dev *pdev)
5431 {
5432         bool wake;
5433
5434         __ixgbe_shutdown(pdev, &wake);
5435
5436         if (system_state == SYSTEM_POWER_OFF) {
5437                 pci_wake_from_d3(pdev, wake);
5438                 pci_set_power_state(pdev, PCI_D3hot);
5439         }
5440 }
5441
5442 /**
5443  * ixgbe_update_stats - Update the board statistics counters.
5444  * @adapter: board private structure
5445  **/
5446 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5447 {
5448         struct net_device *netdev = adapter->netdev;
5449         struct ixgbe_hw *hw = &adapter->hw;
5450         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5451         u64 total_mpc = 0;
5452         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5453         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5454         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5455         u64 bytes = 0, packets = 0;
5456
5457         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5458             test_bit(__IXGBE_RESETTING, &adapter->state))
5459                 return;
5460
5461         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5462                 u64 rsc_count = 0;
5463                 u64 rsc_flush = 0;
5464                 for (i = 0; i < 16; i++)
5465                         adapter->hw_rx_no_dma_resources +=
5466                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5467                 for (i = 0; i < adapter->num_rx_queues; i++) {
5468                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5469                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5470                 }
5471                 adapter->rsc_total_count = rsc_count;
5472                 adapter->rsc_total_flush = rsc_flush;
5473         }
5474
5475         for (i = 0; i < adapter->num_rx_queues; i++) {
5476                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5477                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5478                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5479                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5480                 bytes += rx_ring->stats.bytes;
5481                 packets += rx_ring->stats.packets;
5482         }
5483         adapter->non_eop_descs = non_eop_descs;
5484         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5485         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5486         netdev->stats.rx_bytes = bytes;
5487         netdev->stats.rx_packets = packets;
5488
5489         bytes = 0;
5490         packets = 0;
5491         /* gather some stats to the adapter struct that are per queue */
5492         for (i = 0; i < adapter->num_tx_queues; i++) {
5493                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5494                 restart_queue += tx_ring->tx_stats.restart_queue;
5495                 tx_busy += tx_ring->tx_stats.tx_busy;
5496                 bytes += tx_ring->stats.bytes;
5497                 packets += tx_ring->stats.packets;
5498         }
5499         adapter->restart_queue = restart_queue;
5500         adapter->tx_busy = tx_busy;
5501         netdev->stats.tx_bytes = bytes;
5502         netdev->stats.tx_packets = packets;
5503
5504         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5505         for (i = 0; i < 8; i++) {
5506                 /* for packet buffers not used, the register should read 0 */
5507                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5508                 missed_rx += mpc;
5509                 hwstats->mpc[i] += mpc;
5510                 total_mpc += hwstats->mpc[i];
5511                 if (hw->mac.type == ixgbe_mac_82598EB)
5512                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5513                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5514                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5515                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5516                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5517                 if (hw->mac.type == ixgbe_mac_82599EB) {
5518                         hwstats->pxonrxc[i] +=
5519                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5520                         hwstats->pxoffrxc[i] +=
5521                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5522                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5523                 } else {
5524                         hwstats->pxonrxc[i] +=
5525                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5526                         hwstats->pxoffrxc[i] +=
5527                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5528                 }
5529                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5530                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5531         }
5532         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5533         /* work around hardware counting issue */
5534         hwstats->gprc -= missed_rx;
5535
5536         /* 82598 hardware only has a 32 bit counter in the high register */
5537         if (hw->mac.type == ixgbe_mac_82599EB) {
5538                 u64 tmp;
5539                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5540                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5541                                                 /* 4 high bits of GORC */
5542                 hwstats->gorc += (tmp << 32);
5543                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5544                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5545                                                 /* 4 high bits of GOTC */
5546                 hwstats->gotc += (tmp << 32);
5547                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5548                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5549                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5550                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5551                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5552                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5553 #ifdef IXGBE_FCOE
5554                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5555                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5556                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5557                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5558                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5559                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5560 #endif /* IXGBE_FCOE */
5561         } else {
5562                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5563                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5564                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5565                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5566                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5567         }
5568         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5569         hwstats->bprc += bprc;
5570         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5571         if (hw->mac.type == ixgbe_mac_82598EB)
5572                 hwstats->mprc -= bprc;
5573         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5574         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5575         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5576         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5577         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5578         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5579         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5580         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5581         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5582         hwstats->lxontxc += lxon;
5583         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5584         hwstats->lxofftxc += lxoff;
5585         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5586         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5587         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5588         /*
5589          * 82598 errata - tx of flow control packets is included in tx counters
5590          */
5591         xon_off_tot = lxon + lxoff;
5592         hwstats->gptc -= xon_off_tot;
5593         hwstats->mptc -= xon_off_tot;
5594         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5595         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5596         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5597         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5598         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5599         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5600         hwstats->ptc64 -= xon_off_tot;
5601         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5602         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5603         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5604         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5605         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5606         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5607
5608         /* Fill out the OS statistics structure */
5609         netdev->stats.multicast = hwstats->mprc;
5610
5611         /* Rx Errors */
5612         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5613         netdev->stats.rx_dropped = 0;
5614         netdev->stats.rx_length_errors = hwstats->rlec;
5615         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5616         netdev->stats.rx_missed_errors = total_mpc;
5617 }
5618
5619 /**
5620  * ixgbe_watchdog - Timer Call-back
5621  * @data: pointer to adapter cast into an unsigned long
5622  **/
5623 static void ixgbe_watchdog(unsigned long data)
5624 {
5625         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5626         struct ixgbe_hw *hw = &adapter->hw;
5627         u64 eics = 0;
5628         int i;
5629
5630         /*
5631          *  Do the watchdog outside of interrupt context due to the lovely
5632          * delays that some of the newer hardware requires
5633          */
5634
5635         if (test_bit(__IXGBE_DOWN, &adapter->state))
5636                 goto watchdog_short_circuit;
5637
5638         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5639                 /*
5640                  * for legacy and MSI interrupts don't set any bits
5641                  * that are enabled for EIAM, because this operation
5642                  * would set *both* EIMS and EICS for any bit in EIAM
5643                  */
5644                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5645                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5646                 goto watchdog_reschedule;
5647         }
5648
5649         /* get one bit for every active tx/rx interrupt vector */
5650         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5651                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5652                 if (qv->rxr_count || qv->txr_count)
5653                         eics |= ((u64)1 << i);
5654         }
5655
5656         /* Cause software interrupt to ensure rx rings are cleaned */
5657         ixgbe_irq_rearm_queues(adapter, eics);
5658
5659 watchdog_reschedule:
5660         /* Reset the timer */
5661         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5662
5663 watchdog_short_circuit:
5664         schedule_work(&adapter->watchdog_task);
5665 }
5666
5667 /**
5668  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5669  * @work: pointer to work_struct containing our data
5670  **/
5671 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5672 {
5673         struct ixgbe_adapter *adapter = container_of(work,
5674                                                      struct ixgbe_adapter,
5675                                                      multispeed_fiber_task);
5676         struct ixgbe_hw *hw = &adapter->hw;
5677         u32 autoneg;
5678         bool negotiation;
5679
5680         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5681         autoneg = hw->phy.autoneg_advertised;
5682         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5683                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5684         hw->mac.autotry_restart = false;
5685         if (hw->mac.ops.setup_link)
5686                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5687         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5688         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5689 }
5690
5691 /**
5692  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5693  * @work: pointer to work_struct containing our data
5694  **/
5695 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5696 {
5697         struct ixgbe_adapter *adapter = container_of(work,
5698                                                      struct ixgbe_adapter,
5699                                                      sfp_config_module_task);
5700         struct ixgbe_hw *hw = &adapter->hw;
5701         u32 err;
5702
5703         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5704
5705         /* Time for electrical oscillations to settle down */
5706         msleep(100);
5707         err = hw->phy.ops.identify_sfp(hw);
5708
5709         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5710                 e_dev_err("failed to initialize because an unsupported SFP+ "
5711                           "module type was detected.\n");
5712                 e_dev_err("Reload the driver after installing a supported "
5713                           "module.\n");
5714                 unregister_netdev(adapter->netdev);
5715                 return;
5716         }
5717         hw->mac.ops.setup_sfp(hw);
5718
5719         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5720                 /* This will also work for DA Twinax connections */
5721                 schedule_work(&adapter->multispeed_fiber_task);
5722         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5723 }
5724
5725 /**
5726  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5727  * @work: pointer to work_struct containing our data
5728  **/
5729 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5730 {
5731         struct ixgbe_adapter *adapter = container_of(work,
5732                                                      struct ixgbe_adapter,
5733                                                      fdir_reinit_task);
5734         struct ixgbe_hw *hw = &adapter->hw;
5735         int i;
5736
5737         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5738                 for (i = 0; i < adapter->num_tx_queues; i++)
5739                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5740                                 &(adapter->tx_ring[i]->state));
5741         } else {
5742                 e_err(probe, "failed to finish FDIR re-initialization, "
5743                       "ignored adding FDIR ATR filters\n");
5744         }
5745         /* Done FDIR Re-initialization, enable transmits */
5746         netif_tx_start_all_queues(adapter->netdev);
5747 }
5748
5749 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5750
5751 /**
5752  * ixgbe_watchdog_task - worker thread to bring link up
5753  * @work: pointer to work_struct containing our data
5754  **/
5755 static void ixgbe_watchdog_task(struct work_struct *work)
5756 {
5757         struct ixgbe_adapter *adapter = container_of(work,
5758                                                      struct ixgbe_adapter,
5759                                                      watchdog_task);
5760         struct net_device *netdev = adapter->netdev;
5761         struct ixgbe_hw *hw = &adapter->hw;
5762         u32 link_speed;
5763         bool link_up;
5764         int i;
5765         struct ixgbe_ring *tx_ring;
5766         int some_tx_pending = 0;
5767
5768         mutex_lock(&ixgbe_watchdog_lock);
5769
5770         link_up = adapter->link_up;
5771         link_speed = adapter->link_speed;
5772
5773         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5774                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5775                 if (link_up) {
5776 #ifdef CONFIG_DCB
5777                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5778                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5779                                         hw->mac.ops.fc_enable(hw, i);
5780                         } else {
5781                                 hw->mac.ops.fc_enable(hw, 0);
5782                         }
5783 #else
5784                         hw->mac.ops.fc_enable(hw, 0);
5785 #endif
5786                 }
5787
5788                 if (link_up ||
5789                     time_after(jiffies, (adapter->link_check_timeout +
5790                                          IXGBE_TRY_LINK_TIMEOUT))) {
5791                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5792                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5793                 }
5794                 adapter->link_up = link_up;
5795                 adapter->link_speed = link_speed;
5796         }
5797
5798         if (link_up) {
5799                 if (!netif_carrier_ok(netdev)) {
5800                         bool flow_rx, flow_tx;
5801
5802                         if (hw->mac.type == ixgbe_mac_82599EB) {
5803                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5804                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5805                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5806                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5807                         } else {
5808                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5809                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5810                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5811                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5812                         }
5813
5814                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5815                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5816                                "10 Gbps" :
5817                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5818                                "1 Gbps" : "unknown speed")),
5819                                ((flow_rx && flow_tx) ? "RX/TX" :
5820                                (flow_rx ? "RX" :
5821                                (flow_tx ? "TX" : "None"))));
5822
5823                         netif_carrier_on(netdev);
5824                 } else {
5825                         /* Force detection of hung controller */
5826                         for (i = 0; i < adapter->num_tx_queues; i++) {
5827                                 tx_ring = adapter->tx_ring[i];
5828                                 set_check_for_tx_hang(tx_ring);
5829                         }
5830                 }
5831         } else {
5832                 adapter->link_up = false;
5833                 adapter->link_speed = 0;
5834                 if (netif_carrier_ok(netdev)) {
5835                         e_info(drv, "NIC Link is Down\n");
5836                         netif_carrier_off(netdev);
5837                 }
5838         }
5839
5840         if (!netif_carrier_ok(netdev)) {
5841                 for (i = 0; i < adapter->num_tx_queues; i++) {
5842                         tx_ring = adapter->tx_ring[i];
5843                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5844                                 some_tx_pending = 1;
5845                                 break;
5846                         }
5847                 }
5848
5849                 if (some_tx_pending) {
5850                         /* We've lost link, so the controller stops DMA,
5851                          * but we've got queued Tx work that's never going
5852                          * to get done, so reset controller to flush Tx.
5853                          * (Do the reset outside of interrupt context).
5854                          */
5855                          schedule_work(&adapter->reset_task);
5856                 }
5857         }
5858
5859         ixgbe_update_stats(adapter);
5860         mutex_unlock(&ixgbe_watchdog_lock);
5861 }
5862
5863 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5864                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5865                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5866 {
5867         struct ixgbe_adv_tx_context_desc *context_desc;
5868         unsigned int i;
5869         int err;
5870         struct ixgbe_tx_buffer *tx_buffer_info;
5871         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5872         u32 mss_l4len_idx, l4len;
5873
5874         if (skb_is_gso(skb)) {
5875                 if (skb_header_cloned(skb)) {
5876                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5877                         if (err)
5878                                 return err;
5879                 }
5880                 l4len = tcp_hdrlen(skb);
5881                 *hdr_len += l4len;
5882
5883                 if (protocol == htons(ETH_P_IP)) {
5884                         struct iphdr *iph = ip_hdr(skb);
5885                         iph->tot_len = 0;
5886                         iph->check = 0;
5887                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5888                                                                  iph->daddr, 0,
5889                                                                  IPPROTO_TCP,
5890                                                                  0);
5891                 } else if (skb_is_gso_v6(skb)) {
5892                         ipv6_hdr(skb)->payload_len = 0;
5893                         tcp_hdr(skb)->check =
5894                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5895                                              &ipv6_hdr(skb)->daddr,
5896                                              0, IPPROTO_TCP, 0);
5897                 }
5898
5899                 i = tx_ring->next_to_use;
5900
5901                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5902                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5903
5904                 /* VLAN MACLEN IPLEN */
5905                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5906                         vlan_macip_lens |=
5907                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5908                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5909                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5910                 *hdr_len += skb_network_offset(skb);
5911                 vlan_macip_lens |=
5912                     (skb_transport_header(skb) - skb_network_header(skb));
5913                 *hdr_len +=
5914                     (skb_transport_header(skb) - skb_network_header(skb));
5915                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5916                 context_desc->seqnum_seed = 0;
5917
5918                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5919                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5920                                    IXGBE_ADVTXD_DTYP_CTXT);
5921
5922                 if (protocol == htons(ETH_P_IP))
5923                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5924                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5925                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5926
5927                 /* MSS L4LEN IDX */
5928                 mss_l4len_idx =
5929                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5930                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5931                 /* use index 1 for TSO */
5932                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5933                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5934
5935                 tx_buffer_info->time_stamp = jiffies;
5936                 tx_buffer_info->next_to_watch = i;
5937
5938                 i++;
5939                 if (i == tx_ring->count)
5940                         i = 0;
5941                 tx_ring->next_to_use = i;
5942
5943                 return true;
5944         }
5945         return false;
5946 }
5947
5948 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5949                       __be16 protocol)
5950 {
5951         u32 rtn = 0;
5952
5953         switch (protocol) {
5954         case cpu_to_be16(ETH_P_IP):
5955                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5956                 switch (ip_hdr(skb)->protocol) {
5957                 case IPPROTO_TCP:
5958                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5959                         break;
5960                 case IPPROTO_SCTP:
5961                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5962                         break;
5963                 }
5964                 break;
5965         case cpu_to_be16(ETH_P_IPV6):
5966                 /* XXX what about other V6 headers?? */
5967                 switch (ipv6_hdr(skb)->nexthdr) {
5968                 case IPPROTO_TCP:
5969                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5970                         break;
5971                 case IPPROTO_SCTP:
5972                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5973                         break;
5974                 }
5975                 break;
5976         default:
5977                 if (unlikely(net_ratelimit()))
5978                         e_warn(probe, "partial checksum but proto=%x!\n",
5979                                protocol);
5980                 break;
5981         }
5982
5983         return rtn;
5984 }
5985
5986 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5987                           struct ixgbe_ring *tx_ring,
5988                           struct sk_buff *skb, u32 tx_flags,
5989                           __be16 protocol)
5990 {
5991         struct ixgbe_adv_tx_context_desc *context_desc;
5992         unsigned int i;
5993         struct ixgbe_tx_buffer *tx_buffer_info;
5994         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5995
5996         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5997             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5998                 i = tx_ring->next_to_use;
5999                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6000                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6001
6002                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6003                         vlan_macip_lens |=
6004                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6005                 vlan_macip_lens |= (skb_network_offset(skb) <<
6006                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6007                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6008                         vlan_macip_lens |= (skb_transport_header(skb) -
6009                                             skb_network_header(skb));
6010
6011                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6012                 context_desc->seqnum_seed = 0;
6013
6014                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6015                                     IXGBE_ADVTXD_DTYP_CTXT);
6016
6017                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6018                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6019
6020                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6021                 /* use index zero for tx checksum offload */
6022                 context_desc->mss_l4len_idx = 0;
6023
6024                 tx_buffer_info->time_stamp = jiffies;
6025                 tx_buffer_info->next_to_watch = i;
6026
6027                 i++;
6028                 if (i == tx_ring->count)
6029                         i = 0;
6030                 tx_ring->next_to_use = i;
6031
6032                 return true;
6033         }
6034
6035         return false;
6036 }
6037
6038 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6039                         struct ixgbe_ring *tx_ring,
6040                         struct sk_buff *skb, u32 tx_flags,
6041                         unsigned int first, const u8 hdr_len)
6042 {
6043         struct device *dev = tx_ring->dev;
6044         struct ixgbe_tx_buffer *tx_buffer_info;
6045         unsigned int len;
6046         unsigned int total = skb->len;
6047         unsigned int offset = 0, size, count = 0, i;
6048         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6049         unsigned int f;
6050         unsigned int bytecount = skb->len;
6051         u16 gso_segs = 1;
6052
6053         i = tx_ring->next_to_use;
6054
6055         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6056                 /* excluding fcoe_crc_eof for FCoE */
6057                 total -= sizeof(struct fcoe_crc_eof);
6058
6059         len = min(skb_headlen(skb), total);
6060         while (len) {
6061                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6062                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6063
6064                 tx_buffer_info->length = size;
6065                 tx_buffer_info->mapped_as_page = false;
6066                 tx_buffer_info->dma = dma_map_single(dev,
6067                                                      skb->data + offset,
6068                                                      size, DMA_TO_DEVICE);
6069                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6070                         goto dma_error;
6071                 tx_buffer_info->time_stamp = jiffies;
6072                 tx_buffer_info->next_to_watch = i;
6073
6074                 len -= size;
6075                 total -= size;
6076                 offset += size;
6077                 count++;
6078
6079                 if (len) {
6080                         i++;
6081                         if (i == tx_ring->count)
6082                                 i = 0;
6083                 }
6084         }
6085
6086         for (f = 0; f < nr_frags; f++) {
6087                 struct skb_frag_struct *frag;
6088
6089                 frag = &skb_shinfo(skb)->frags[f];
6090                 len = min((unsigned int)frag->size, total);
6091                 offset = frag->page_offset;
6092
6093                 while (len) {
6094                         i++;
6095                         if (i == tx_ring->count)
6096                                 i = 0;
6097
6098                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6099                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6100
6101                         tx_buffer_info->length = size;
6102                         tx_buffer_info->dma = dma_map_page(dev,
6103                                                            frag->page,
6104                                                            offset, size,
6105                                                            DMA_TO_DEVICE);
6106                         tx_buffer_info->mapped_as_page = true;
6107                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6108                                 goto dma_error;
6109                         tx_buffer_info->time_stamp = jiffies;
6110                         tx_buffer_info->next_to_watch = i;
6111
6112                         len -= size;
6113                         total -= size;
6114                         offset += size;
6115                         count++;
6116                 }
6117                 if (total == 0)
6118                         break;
6119         }
6120
6121         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6122                 gso_segs = skb_shinfo(skb)->gso_segs;
6123 #ifdef IXGBE_FCOE
6124         /* adjust for FCoE Sequence Offload */
6125         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6126                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6127                                         skb_shinfo(skb)->gso_size);
6128 #endif /* IXGBE_FCOE */
6129         bytecount += (gso_segs - 1) * hdr_len;
6130
6131         /* multiply data chunks by size of headers */
6132         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6133         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6134         tx_ring->tx_buffer_info[i].skb = skb;
6135         tx_ring->tx_buffer_info[first].next_to_watch = i;
6136
6137         return count;
6138
6139 dma_error:
6140         e_dev_err("TX DMA map failed\n");
6141
6142         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6143         tx_buffer_info->dma = 0;
6144         tx_buffer_info->time_stamp = 0;
6145         tx_buffer_info->next_to_watch = 0;
6146         if (count)
6147                 count--;
6148
6149         /* clear timestamp and dma mappings for remaining portion of packet */
6150         while (count--) {
6151                 if (i == 0)
6152                         i += tx_ring->count;
6153                 i--;
6154                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6155                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6156         }
6157
6158         return 0;
6159 }
6160
6161 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6162                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6163 {
6164         union ixgbe_adv_tx_desc *tx_desc = NULL;
6165         struct ixgbe_tx_buffer *tx_buffer_info;
6166         u32 olinfo_status = 0, cmd_type_len = 0;
6167         unsigned int i;
6168         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6169
6170         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6171
6172         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6173
6174         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6175                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6176
6177         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6178                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6179
6180                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6181                                  IXGBE_ADVTXD_POPTS_SHIFT;
6182
6183                 /* use index 1 context for tso */
6184                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6185                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6186                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6187                                          IXGBE_ADVTXD_POPTS_SHIFT;
6188
6189         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6190                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6191                                  IXGBE_ADVTXD_POPTS_SHIFT;
6192
6193         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6194                 olinfo_status |= IXGBE_ADVTXD_CC;
6195                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6196                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6197                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6198         }
6199
6200         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6201
6202         i = tx_ring->next_to_use;
6203         while (count--) {
6204                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6205                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6206                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6207                 tx_desc->read.cmd_type_len =
6208                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6209                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6210                 i++;
6211                 if (i == tx_ring->count)
6212                         i = 0;
6213         }
6214
6215         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6216
6217         /*
6218          * Force memory writes to complete before letting h/w
6219          * know there are new descriptors to fetch.  (Only
6220          * applicable for weak-ordered memory model archs,
6221          * such as IA-64).
6222          */
6223         wmb();
6224
6225         tx_ring->next_to_use = i;
6226         writel(i, tx_ring->tail);
6227 }
6228
6229 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6230                       int queue, u32 tx_flags, __be16 protocol)
6231 {
6232         struct ixgbe_atr_input atr_input;
6233         struct tcphdr *th;
6234         struct iphdr *iph = ip_hdr(skb);
6235         struct ethhdr *eth = (struct ethhdr *)skb->data;
6236         u16 vlan_id, src_port, dst_port, flex_bytes;
6237         u32 src_ipv4_addr, dst_ipv4_addr;
6238         u8 l4type = 0;
6239
6240         /* Right now, we support IPv4 only */
6241         if (protocol != htons(ETH_P_IP))
6242                 return;
6243         /* check if we're UDP or TCP */
6244         if (iph->protocol == IPPROTO_TCP) {
6245                 th = tcp_hdr(skb);
6246                 src_port = th->source;
6247                 dst_port = th->dest;
6248                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6249                 /* l4type IPv4 type is 0, no need to assign */
6250         } else {
6251                 /* Unsupported L4 header, just bail here */
6252                 return;
6253         }
6254
6255         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6256
6257         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6258                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6259         src_ipv4_addr = iph->saddr;
6260         dst_ipv4_addr = iph->daddr;
6261         flex_bytes = eth->h_proto;
6262
6263         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6264         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6265         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6266         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6267         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6268         /* src and dst are inverted, think how the receiver sees them */
6269         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6270         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6271
6272         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6273         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6274 }
6275
6276 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6277 {
6278         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6279         /* Herbert's original patch had:
6280          *  smp_mb__after_netif_stop_queue();
6281          * but since that doesn't exist yet, just open code it. */
6282         smp_mb();
6283
6284         /* We need to check again in a case another CPU has just
6285          * made room available. */
6286         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6287                 return -EBUSY;
6288
6289         /* A reprieve! - use start_queue because it doesn't call schedule */
6290         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6291         ++tx_ring->tx_stats.restart_queue;
6292         return 0;
6293 }
6294
6295 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6296 {
6297         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6298                 return 0;
6299         return __ixgbe_maybe_stop_tx(tx_ring, size);
6300 }
6301
6302 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6303 {
6304         struct ixgbe_adapter *adapter = netdev_priv(dev);
6305         int txq = smp_processor_id();
6306 #ifdef IXGBE_FCOE
6307         __be16 protocol;
6308
6309         protocol = vlan_get_protocol(skb);
6310
6311         if ((protocol == htons(ETH_P_FCOE)) ||
6312             (protocol == htons(ETH_P_FIP))) {
6313                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6314                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6315                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6316                         return txq;
6317 #ifdef CONFIG_IXGBE_DCB
6318                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6319                         txq = adapter->fcoe.up;
6320                         return txq;
6321 #endif
6322                 }
6323         }
6324 #endif
6325
6326         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6327                 while (unlikely(txq >= dev->real_num_tx_queues))
6328                         txq -= dev->real_num_tx_queues;
6329                 return txq;
6330         }
6331
6332         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6333                 if (skb->priority == TC_PRIO_CONTROL)
6334                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6335                 else
6336                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6337                                >> 13;
6338                 return txq;
6339         }
6340
6341         return skb_tx_hash(dev, skb);
6342 }
6343
6344 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6345                           struct ixgbe_adapter *adapter,
6346                           struct ixgbe_ring *tx_ring)
6347 {
6348         struct net_device *netdev = tx_ring->netdev;
6349         struct netdev_queue *txq;
6350         unsigned int first;
6351         unsigned int tx_flags = 0;
6352         u8 hdr_len = 0;
6353         int tso;
6354         int count = 0;
6355         unsigned int f;
6356         __be16 protocol;
6357
6358         protocol = vlan_get_protocol(skb);
6359
6360         if (vlan_tx_tag_present(skb)) {
6361                 tx_flags |= vlan_tx_tag_get(skb);
6362                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6363                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6364                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6365                 }
6366                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6367                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6368         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6369                    skb->priority != TC_PRIO_CONTROL) {
6370                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6371                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6372                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6373         }
6374
6375 #ifdef IXGBE_FCOE
6376         /* for FCoE with DCB, we force the priority to what
6377          * was specified by the switch */
6378         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6379             (protocol == htons(ETH_P_FCOE) ||
6380              protocol == htons(ETH_P_FIP))) {
6381 #ifdef CONFIG_IXGBE_DCB
6382                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6383                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6384                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6385                         tx_flags |= ((adapter->fcoe.up << 13)
6386                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6387                 }
6388 #endif
6389                 /* flag for FCoE offloads */
6390                 if (protocol == htons(ETH_P_FCOE))
6391                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6392         }
6393 #endif
6394
6395         /* four things can cause us to need a context descriptor */
6396         if (skb_is_gso(skb) ||
6397             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6398             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6399             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6400                 count++;
6401
6402         count += TXD_USE_COUNT(skb_headlen(skb));
6403         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6404                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6405
6406         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6407                 tx_ring->tx_stats.tx_busy++;
6408                 return NETDEV_TX_BUSY;
6409         }
6410
6411         first = tx_ring->next_to_use;
6412         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6413 #ifdef IXGBE_FCOE
6414                 /* setup tx offload for FCoE */
6415                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6416                 if (tso < 0) {
6417                         dev_kfree_skb_any(skb);
6418                         return NETDEV_TX_OK;
6419                 }
6420                 if (tso)
6421                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6422 #endif /* IXGBE_FCOE */
6423         } else {
6424                 if (protocol == htons(ETH_P_IP))
6425                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6426                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6427                                 protocol);
6428                 if (tso < 0) {
6429                         dev_kfree_skb_any(skb);
6430                         return NETDEV_TX_OK;
6431                 }
6432
6433                 if (tso)
6434                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6435                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6436                                        protocol) &&
6437                          (skb->ip_summed == CHECKSUM_PARTIAL))
6438                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6439         }
6440
6441         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6442         if (count) {
6443                 /* add the ATR filter if ATR is on */
6444                 if (tx_ring->atr_sample_rate) {
6445                         ++tx_ring->atr_count;
6446                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6447                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6448                                       &tx_ring->state)) {
6449                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6450                                           tx_flags, protocol);
6451                                 tx_ring->atr_count = 0;
6452                         }
6453                 }
6454                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6455                 txq->tx_bytes += skb->len;
6456                 txq->tx_packets++;
6457                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6458                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6459
6460         } else {
6461                 dev_kfree_skb_any(skb);
6462                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6463                 tx_ring->next_to_use = first;
6464         }
6465
6466         return NETDEV_TX_OK;
6467 }
6468
6469 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6470 {
6471         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6472         struct ixgbe_ring *tx_ring;
6473
6474         tx_ring = adapter->tx_ring[skb->queue_mapping];
6475         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6476 }
6477
6478 /**
6479  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6480  * @netdev: network interface device structure
6481  * @p: pointer to an address structure
6482  *
6483  * Returns 0 on success, negative on failure
6484  **/
6485 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6486 {
6487         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6488         struct ixgbe_hw *hw = &adapter->hw;
6489         struct sockaddr *addr = p;
6490
6491         if (!is_valid_ether_addr(addr->sa_data))
6492                 return -EADDRNOTAVAIL;
6493
6494         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6495         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6496
6497         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6498                             IXGBE_RAH_AV);
6499
6500         return 0;
6501 }
6502
6503 static int
6504 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6505 {
6506         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6507         struct ixgbe_hw *hw = &adapter->hw;
6508         u16 value;
6509         int rc;
6510
6511         if (prtad != hw->phy.mdio.prtad)
6512                 return -EINVAL;
6513         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6514         if (!rc)
6515                 rc = value;
6516         return rc;
6517 }
6518
6519 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6520                             u16 addr, u16 value)
6521 {
6522         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6523         struct ixgbe_hw *hw = &adapter->hw;
6524
6525         if (prtad != hw->phy.mdio.prtad)
6526                 return -EINVAL;
6527         return hw->phy.ops.write_reg(hw, addr, devad, value);
6528 }
6529
6530 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6531 {
6532         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6533
6534         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6535 }
6536
6537 /**
6538  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6539  * netdev->dev_addrs
6540  * @netdev: network interface device structure
6541  *
6542  * Returns non-zero on failure
6543  **/
6544 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6545 {
6546         int err = 0;
6547         struct ixgbe_adapter *adapter = netdev_priv(dev);
6548         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6549
6550         if (is_valid_ether_addr(mac->san_addr)) {
6551                 rtnl_lock();
6552                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6553                 rtnl_unlock();
6554         }
6555         return err;
6556 }
6557
6558 /**
6559  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6560  * netdev->dev_addrs
6561  * @netdev: network interface device structure
6562  *
6563  * Returns non-zero on failure
6564  **/
6565 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6566 {
6567         int err = 0;
6568         struct ixgbe_adapter *adapter = netdev_priv(dev);
6569         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6570
6571         if (is_valid_ether_addr(mac->san_addr)) {
6572                 rtnl_lock();
6573                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6574                 rtnl_unlock();
6575         }
6576         return err;
6577 }
6578
6579 #ifdef CONFIG_NET_POLL_CONTROLLER
6580 /*
6581  * Polling 'interrupt' - used by things like netconsole to send skbs
6582  * without having to re-enable interrupts. It's not called while
6583  * the interrupt routine is executing.
6584  */
6585 static void ixgbe_netpoll(struct net_device *netdev)
6586 {
6587         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6588         int i;
6589
6590         /* if interface is down do nothing */
6591         if (test_bit(__IXGBE_DOWN, &adapter->state))
6592                 return;
6593
6594         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6595         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6596                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6597                 for (i = 0; i < num_q_vectors; i++) {
6598                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6599                         ixgbe_msix_clean_many(0, q_vector);
6600                 }
6601         } else {
6602                 ixgbe_intr(adapter->pdev->irq, netdev);
6603         }
6604         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6605 }
6606 #endif
6607
6608 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6609                                                    struct rtnl_link_stats64 *stats)
6610 {
6611         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6612         int i;
6613
6614         /* accurate rx/tx bytes/packets stats */
6615         dev_txq_stats_fold(netdev, stats);
6616         rcu_read_lock();
6617         for (i = 0; i < adapter->num_rx_queues; i++) {
6618                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6619                 u64 bytes, packets;
6620                 unsigned int start;
6621
6622                 if (ring) {
6623                         do {
6624                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6625                                 packets = ring->stats.packets;
6626                                 bytes   = ring->stats.bytes;
6627                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6628                         stats->rx_packets += packets;
6629                         stats->rx_bytes   += bytes;
6630                 }
6631         }
6632         rcu_read_unlock();
6633         /* following stats updated by ixgbe_watchdog_task() */
6634         stats->multicast        = netdev->stats.multicast;
6635         stats->rx_errors        = netdev->stats.rx_errors;
6636         stats->rx_length_errors = netdev->stats.rx_length_errors;
6637         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6638         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6639         return stats;
6640 }
6641
6642
6643 static const struct net_device_ops ixgbe_netdev_ops = {
6644         .ndo_open               = ixgbe_open,
6645         .ndo_stop               = ixgbe_close,
6646         .ndo_start_xmit         = ixgbe_xmit_frame,
6647         .ndo_select_queue       = ixgbe_select_queue,
6648         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6649         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6650         .ndo_validate_addr      = eth_validate_addr,
6651         .ndo_set_mac_address    = ixgbe_set_mac,
6652         .ndo_change_mtu         = ixgbe_change_mtu,
6653         .ndo_tx_timeout         = ixgbe_tx_timeout,
6654         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6655         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6656         .ndo_do_ioctl           = ixgbe_ioctl,
6657         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6658         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6659         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6660         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6661         .ndo_get_stats64        = ixgbe_get_stats64,
6662 #ifdef CONFIG_NET_POLL_CONTROLLER
6663         .ndo_poll_controller    = ixgbe_netpoll,
6664 #endif
6665 #ifdef IXGBE_FCOE
6666         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6667         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6668         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6669         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6670         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6671 #endif /* IXGBE_FCOE */
6672 };
6673
6674 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6675                            const struct ixgbe_info *ii)
6676 {
6677 #ifdef CONFIG_PCI_IOV
6678         struct ixgbe_hw *hw = &adapter->hw;
6679         int err;
6680
6681         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6682                 return;
6683
6684         /* The 82599 supports up to 64 VFs per physical function
6685          * but this implementation limits allocation to 63 so that
6686          * basic networking resources are still available to the
6687          * physical function
6688          */
6689         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6690         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6691         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6692         if (err) {
6693                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6694                 goto err_novfs;
6695         }
6696         /* If call to enable VFs succeeded then allocate memory
6697          * for per VF control structures.
6698          */
6699         adapter->vfinfo =
6700                 kcalloc(adapter->num_vfs,
6701                         sizeof(struct vf_data_storage), GFP_KERNEL);
6702         if (adapter->vfinfo) {
6703                 /* Now that we're sure SR-IOV is enabled
6704                  * and memory allocated set up the mailbox parameters
6705                  */
6706                 ixgbe_init_mbx_params_pf(hw);
6707                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6708                        sizeof(hw->mbx.ops));
6709
6710                 /* Disable RSC when in SR-IOV mode */
6711                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6712                                      IXGBE_FLAG2_RSC_ENABLED);
6713                 return;
6714         }
6715
6716         /* Oh oh */
6717         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6718               "SRIOV disabled\n");
6719         pci_disable_sriov(adapter->pdev);
6720
6721 err_novfs:
6722         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6723         adapter->num_vfs = 0;
6724 #endif /* CONFIG_PCI_IOV */
6725 }
6726
6727 /**
6728  * ixgbe_probe - Device Initialization Routine
6729  * @pdev: PCI device information struct
6730  * @ent: entry in ixgbe_pci_tbl
6731  *
6732  * Returns 0 on success, negative on failure
6733  *
6734  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6735  * The OS initialization, configuring of the adapter private structure,
6736  * and a hardware reset occur.
6737  **/
6738 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6739                                  const struct pci_device_id *ent)
6740 {
6741         struct net_device *netdev;
6742         struct ixgbe_adapter *adapter = NULL;
6743         struct ixgbe_hw *hw;
6744         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6745         static int cards_found;
6746         int i, err, pci_using_dac;
6747         unsigned int indices = num_possible_cpus();
6748 #ifdef IXGBE_FCOE
6749         u16 device_caps;
6750 #endif
6751         u32 part_num, eec;
6752
6753         /* Catch broken hardware that put the wrong VF device ID in
6754          * the PCIe SR-IOV capability.
6755          */
6756         if (pdev->is_virtfn) {
6757                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6758                      pci_name(pdev), pdev->vendor, pdev->device);
6759                 return -EINVAL;
6760         }
6761
6762         err = pci_enable_device_mem(pdev);
6763         if (err)
6764                 return err;
6765
6766         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6767             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6768                 pci_using_dac = 1;
6769         } else {
6770                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6771                 if (err) {
6772                         err = dma_set_coherent_mask(&pdev->dev,
6773                                                     DMA_BIT_MASK(32));
6774                         if (err) {
6775                                 dev_err(&pdev->dev,
6776                                         "No usable DMA configuration, aborting\n");
6777                                 goto err_dma;
6778                         }
6779                 }
6780                 pci_using_dac = 0;
6781         }
6782
6783         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6784                                            IORESOURCE_MEM), ixgbe_driver_name);
6785         if (err) {
6786                 dev_err(&pdev->dev,
6787                         "pci_request_selected_regions failed 0x%x\n", err);
6788                 goto err_pci_reg;
6789         }
6790
6791         pci_enable_pcie_error_reporting(pdev);
6792
6793         pci_set_master(pdev);
6794         pci_save_state(pdev);
6795
6796         if (ii->mac == ixgbe_mac_82598EB)
6797                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6798         else
6799                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6800
6801         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6802 #ifdef IXGBE_FCOE
6803         indices += min_t(unsigned int, num_possible_cpus(),
6804                          IXGBE_MAX_FCOE_INDICES);
6805 #endif
6806         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6807         if (!netdev) {
6808                 err = -ENOMEM;
6809                 goto err_alloc_etherdev;
6810         }
6811
6812         SET_NETDEV_DEV(netdev, &pdev->dev);
6813
6814         adapter = netdev_priv(netdev);
6815         pci_set_drvdata(pdev, adapter);
6816
6817         adapter->netdev = netdev;
6818         adapter->pdev = pdev;
6819         hw = &adapter->hw;
6820         hw->back = adapter;
6821         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6822
6823         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6824                               pci_resource_len(pdev, 0));
6825         if (!hw->hw_addr) {
6826                 err = -EIO;
6827                 goto err_ioremap;
6828         }
6829
6830         for (i = 1; i <= 5; i++) {
6831                 if (pci_resource_len(pdev, i) == 0)
6832                         continue;
6833         }
6834
6835         netdev->netdev_ops = &ixgbe_netdev_ops;
6836         ixgbe_set_ethtool_ops(netdev);
6837         netdev->watchdog_timeo = 5 * HZ;
6838         strcpy(netdev->name, pci_name(pdev));
6839
6840         adapter->bd_number = cards_found;
6841
6842         /* Setup hw api */
6843         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6844         hw->mac.type  = ii->mac;
6845
6846         /* EEPROM */
6847         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6848         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6849         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6850         if (!(eec & (1 << 8)))
6851                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6852
6853         /* PHY */
6854         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6855         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6856         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6857         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6858         hw->phy.mdio.mmds = 0;
6859         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6860         hw->phy.mdio.dev = netdev;
6861         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6862         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6863
6864         /* set up this timer and work struct before calling get_invariants
6865          * which might start the timer
6866          */
6867         init_timer(&adapter->sfp_timer);
6868         adapter->sfp_timer.function = ixgbe_sfp_timer;
6869         adapter->sfp_timer.data = (unsigned long) adapter;
6870
6871         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6872
6873         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6874         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6875
6876         /* a new SFP+ module arrival, called from GPI SDP2 context */
6877         INIT_WORK(&adapter->sfp_config_module_task,
6878                   ixgbe_sfp_config_module_task);
6879
6880         ii->get_invariants(hw);
6881
6882         /* setup the private structure */
6883         err = ixgbe_sw_init(adapter);
6884         if (err)
6885                 goto err_sw_init;
6886
6887         /* Make it possible the adapter to be woken up via WOL */
6888         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6889                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6890
6891         /*
6892          * If there is a fan on this device and it has failed log the
6893          * failure.
6894          */
6895         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6896                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6897                 if (esdp & IXGBE_ESDP_SDP1)
6898                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6899         }
6900
6901         /* reset_hw fills in the perm_addr as well */
6902         hw->phy.reset_if_overtemp = true;
6903         err = hw->mac.ops.reset_hw(hw);
6904         hw->phy.reset_if_overtemp = false;
6905         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6906             hw->mac.type == ixgbe_mac_82598EB) {
6907                 /*
6908                  * Start a kernel thread to watch for a module to arrive.
6909                  * Only do this for 82598, since 82599 will generate
6910                  * interrupts on module arrival.
6911                  */
6912                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6913                 mod_timer(&adapter->sfp_timer,
6914                           round_jiffies(jiffies + (2 * HZ)));
6915                 err = 0;
6916         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6917                 e_dev_err("failed to initialize because an unsupported SFP+ "
6918                           "module type was detected.\n");
6919                 e_dev_err("Reload the driver after installing a supported "
6920                           "module.\n");
6921                 goto err_sw_init;
6922         } else if (err) {
6923                 e_dev_err("HW Init failed: %d\n", err);
6924                 goto err_sw_init;
6925         }
6926
6927         ixgbe_probe_vf(adapter, ii);
6928
6929         netdev->features = NETIF_F_SG |
6930                            NETIF_F_IP_CSUM |
6931                            NETIF_F_HW_VLAN_TX |
6932                            NETIF_F_HW_VLAN_RX |
6933                            NETIF_F_HW_VLAN_FILTER;
6934
6935         netdev->features |= NETIF_F_IPV6_CSUM;
6936         netdev->features |= NETIF_F_TSO;
6937         netdev->features |= NETIF_F_TSO6;
6938         netdev->features |= NETIF_F_GRO;
6939
6940         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6941                 netdev->features |= NETIF_F_SCTP_CSUM;
6942
6943         netdev->vlan_features |= NETIF_F_TSO;
6944         netdev->vlan_features |= NETIF_F_TSO6;
6945         netdev->vlan_features |= NETIF_F_IP_CSUM;
6946         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6947         netdev->vlan_features |= NETIF_F_SG;
6948
6949         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6950                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6951                                     IXGBE_FLAG_DCB_ENABLED);
6952         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6953                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6954
6955 #ifdef CONFIG_IXGBE_DCB
6956         netdev->dcbnl_ops = &dcbnl_ops;
6957 #endif
6958
6959 #ifdef IXGBE_FCOE
6960         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6961                 if (hw->mac.ops.get_device_caps) {
6962                         hw->mac.ops.get_device_caps(hw, &device_caps);
6963                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6964                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6965                 }
6966         }
6967         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6968                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6969                 netdev->vlan_features |= NETIF_F_FSO;
6970                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6971         }
6972 #endif /* IXGBE_FCOE */
6973         if (pci_using_dac) {
6974                 netdev->features |= NETIF_F_HIGHDMA;
6975                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6976         }
6977
6978         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6979                 netdev->features |= NETIF_F_LRO;
6980
6981         /* make sure the EEPROM is good */
6982         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6983                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6984                 err = -EIO;
6985                 goto err_eeprom;
6986         }
6987
6988         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6989         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6990
6991         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6992                 e_dev_err("invalid MAC address\n");
6993                 err = -EIO;
6994                 goto err_eeprom;
6995         }
6996
6997         /* power down the optics */
6998         if (hw->phy.multispeed_fiber)
6999                 hw->mac.ops.disable_tx_laser(hw);
7000
7001         init_timer(&adapter->watchdog_timer);
7002         adapter->watchdog_timer.function = ixgbe_watchdog;
7003         adapter->watchdog_timer.data = (unsigned long)adapter;
7004
7005         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7006         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7007
7008         err = ixgbe_init_interrupt_scheme(adapter);
7009         if (err)
7010                 goto err_sw_init;
7011
7012         switch (pdev->device) {
7013         case IXGBE_DEV_ID_82599_KX4:
7014                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7015                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7016                 break;
7017         default:
7018                 adapter->wol = 0;
7019                 break;
7020         }
7021         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7022
7023         /* pick up the PCI bus settings for reporting later */
7024         hw->mac.ops.get_bus_info(hw);
7025
7026         /* print bus type/speed/width info */
7027         e_dev_info("(PCI Express:%s:%s) %pM\n",
7028                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7029                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7030                     "Unknown"),
7031                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7032                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7033                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7034                     "Unknown"),
7035                    netdev->dev_addr);
7036         ixgbe_read_pba_num_generic(hw, &part_num);
7037         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7038                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7039                            "PBA No: %06x-%03x\n",
7040                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7041                            (part_num >> 8), (part_num & 0xff));
7042         else
7043                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7044                            hw->mac.type, hw->phy.type,
7045                            (part_num >> 8), (part_num & 0xff));
7046
7047         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7048                 e_dev_warn("PCI-Express bandwidth available for this card is "
7049                            "not sufficient for optimal performance.\n");
7050                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7051                            "is required.\n");
7052         }
7053
7054         /* save off EEPROM version number */
7055         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7056
7057         /* reset the hardware with the new settings */
7058         err = hw->mac.ops.start_hw(hw);
7059
7060         if (err == IXGBE_ERR_EEPROM_VERSION) {
7061                 /* We are running on a pre-production device, log a warning */
7062                 e_dev_warn("This device is a pre-production adapter/LOM. "
7063                            "Please be aware there may be issues associated "
7064                            "with your hardware.  If you are experiencing "
7065                            "problems please contact your Intel or hardware "
7066                            "representative who provided you with this "
7067                            "hardware.\n");
7068         }
7069         strcpy(netdev->name, "eth%d");
7070         err = register_netdev(netdev);
7071         if (err)
7072                 goto err_register;
7073
7074         /* carrier off reporting is important to ethtool even BEFORE open */
7075         netif_carrier_off(netdev);
7076
7077         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7078             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7079                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7080
7081         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7082                 INIT_WORK(&adapter->check_overtemp_task,
7083                           ixgbe_check_overtemp_task);
7084 #ifdef CONFIG_IXGBE_DCA
7085         if (dca_add_requester(&pdev->dev) == 0) {
7086                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7087                 ixgbe_setup_dca(adapter);
7088         }
7089 #endif
7090         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7091                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7092                 for (i = 0; i < adapter->num_vfs; i++)
7093                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7094         }
7095
7096         /* add san mac addr to netdev */
7097         ixgbe_add_sanmac_netdev(netdev);
7098
7099         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7100         cards_found++;
7101         return 0;
7102
7103 err_register:
7104         ixgbe_release_hw_control(adapter);
7105         ixgbe_clear_interrupt_scheme(adapter);
7106 err_sw_init:
7107 err_eeprom:
7108         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7109                 ixgbe_disable_sriov(adapter);
7110         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7111         del_timer_sync(&adapter->sfp_timer);
7112         cancel_work_sync(&adapter->sfp_task);
7113         cancel_work_sync(&adapter->multispeed_fiber_task);
7114         cancel_work_sync(&adapter->sfp_config_module_task);
7115         iounmap(hw->hw_addr);
7116 err_ioremap:
7117         free_netdev(netdev);
7118 err_alloc_etherdev:
7119         pci_release_selected_regions(pdev,
7120                                      pci_select_bars(pdev, IORESOURCE_MEM));
7121 err_pci_reg:
7122 err_dma:
7123         pci_disable_device(pdev);
7124         return err;
7125 }
7126
7127 /**
7128  * ixgbe_remove - Device Removal Routine
7129  * @pdev: PCI device information struct
7130  *
7131  * ixgbe_remove is called by the PCI subsystem to alert the driver
7132  * that it should release a PCI device.  The could be caused by a
7133  * Hot-Plug event, or because the driver is going to be removed from
7134  * memory.
7135  **/
7136 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7137 {
7138         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7139         struct net_device *netdev = adapter->netdev;
7140
7141         set_bit(__IXGBE_DOWN, &adapter->state);
7142         /* clear the module not found bit to make sure the worker won't
7143          * reschedule
7144          */
7145         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7146         del_timer_sync(&adapter->watchdog_timer);
7147
7148         del_timer_sync(&adapter->sfp_timer);
7149         cancel_work_sync(&adapter->watchdog_task);
7150         cancel_work_sync(&adapter->sfp_task);
7151         cancel_work_sync(&adapter->multispeed_fiber_task);
7152         cancel_work_sync(&adapter->sfp_config_module_task);
7153         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7154             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7155                 cancel_work_sync(&adapter->fdir_reinit_task);
7156         flush_scheduled_work();
7157
7158 #ifdef CONFIG_IXGBE_DCA
7159         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7160                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7161                 dca_remove_requester(&pdev->dev);
7162                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7163         }
7164
7165 #endif
7166 #ifdef IXGBE_FCOE
7167         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7168                 ixgbe_cleanup_fcoe(adapter);
7169
7170 #endif /* IXGBE_FCOE */
7171
7172         /* remove the added san mac */
7173         ixgbe_del_sanmac_netdev(netdev);
7174
7175         if (netdev->reg_state == NETREG_REGISTERED)
7176                 unregister_netdev(netdev);
7177
7178         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7179                 ixgbe_disable_sriov(adapter);
7180
7181         ixgbe_clear_interrupt_scheme(adapter);
7182
7183         ixgbe_release_hw_control(adapter);
7184
7185         iounmap(adapter->hw.hw_addr);
7186         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7187                                      IORESOURCE_MEM));
7188
7189         e_dev_info("complete\n");
7190
7191         free_netdev(netdev);
7192
7193         pci_disable_pcie_error_reporting(pdev);
7194
7195         pci_disable_device(pdev);
7196 }
7197
7198 /**
7199  * ixgbe_io_error_detected - called when PCI error is detected
7200  * @pdev: Pointer to PCI device
7201  * @state: The current pci connection state
7202  *
7203  * This function is called after a PCI bus error affecting
7204  * this device has been detected.
7205  */
7206 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7207                                                 pci_channel_state_t state)
7208 {
7209         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7210         struct net_device *netdev = adapter->netdev;
7211
7212         netif_device_detach(netdev);
7213
7214         if (state == pci_channel_io_perm_failure)
7215                 return PCI_ERS_RESULT_DISCONNECT;
7216
7217         if (netif_running(netdev))
7218                 ixgbe_down(adapter);
7219         pci_disable_device(pdev);
7220
7221         /* Request a slot reset. */
7222         return PCI_ERS_RESULT_NEED_RESET;
7223 }
7224
7225 /**
7226  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7227  * @pdev: Pointer to PCI device
7228  *
7229  * Restart the card from scratch, as if from a cold-boot.
7230  */
7231 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7232 {
7233         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7234         pci_ers_result_t result;
7235         int err;
7236
7237         if (pci_enable_device_mem(pdev)) {
7238                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7239                 result = PCI_ERS_RESULT_DISCONNECT;
7240         } else {
7241                 pci_set_master(pdev);
7242                 pci_restore_state(pdev);
7243                 pci_save_state(pdev);
7244
7245                 pci_wake_from_d3(pdev, false);
7246
7247                 ixgbe_reset(adapter);
7248                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7249                 result = PCI_ERS_RESULT_RECOVERED;
7250         }
7251
7252         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7253         if (err) {
7254                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7255                           "failed 0x%0x\n", err);
7256                 /* non-fatal, continue */
7257         }
7258
7259         return result;
7260 }
7261
7262 /**
7263  * ixgbe_io_resume - called when traffic can start flowing again.
7264  * @pdev: Pointer to PCI device
7265  *
7266  * This callback is called when the error recovery driver tells us that
7267  * its OK to resume normal operation.
7268  */
7269 static void ixgbe_io_resume(struct pci_dev *pdev)
7270 {
7271         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7272         struct net_device *netdev = adapter->netdev;
7273
7274         if (netif_running(netdev)) {
7275                 if (ixgbe_up(adapter)) {
7276                         e_info(probe, "ixgbe_up failed after reset\n");
7277                         return;
7278                 }
7279         }
7280
7281         netif_device_attach(netdev);
7282 }
7283
7284 static struct pci_error_handlers ixgbe_err_handler = {
7285         .error_detected = ixgbe_io_error_detected,
7286         .slot_reset = ixgbe_io_slot_reset,
7287         .resume = ixgbe_io_resume,
7288 };
7289
7290 static struct pci_driver ixgbe_driver = {
7291         .name     = ixgbe_driver_name,
7292         .id_table = ixgbe_pci_tbl,
7293         .probe    = ixgbe_probe,
7294         .remove   = __devexit_p(ixgbe_remove),
7295 #ifdef CONFIG_PM
7296         .suspend  = ixgbe_suspend,
7297         .resume   = ixgbe_resume,
7298 #endif
7299         .shutdown = ixgbe_shutdown,
7300         .err_handler = &ixgbe_err_handler
7301 };
7302
7303 /**
7304  * ixgbe_init_module - Driver Registration Routine
7305  *
7306  * ixgbe_init_module is the first routine called when the driver is
7307  * loaded. All it does is register with the PCI subsystem.
7308  **/
7309 static int __init ixgbe_init_module(void)
7310 {
7311         int ret;
7312         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7313         pr_info("%s\n", ixgbe_copyright);
7314
7315 #ifdef CONFIG_IXGBE_DCA
7316         dca_register_notify(&dca_notifier);
7317 #endif
7318
7319         ret = pci_register_driver(&ixgbe_driver);
7320         return ret;
7321 }
7322
7323 module_init(ixgbe_init_module);
7324
7325 /**
7326  * ixgbe_exit_module - Driver Exit Cleanup Routine
7327  *
7328  * ixgbe_exit_module is called just before the driver is removed
7329  * from memory.
7330  **/
7331 static void __exit ixgbe_exit_module(void)
7332 {
7333 #ifdef CONFIG_IXGBE_DCA
7334         dca_unregister_notify(&dca_notifier);
7335 #endif
7336         pci_unregister_driver(&ixgbe_driver);
7337         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7338 }
7339
7340 #ifdef CONFIG_IXGBE_DCA
7341 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7342                             void *p)
7343 {
7344         int ret_val;
7345
7346         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7347                                          __ixgbe_notify_dca);
7348
7349         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7350 }
7351
7352 #endif /* CONFIG_IXGBE_DCA */
7353
7354 /**
7355  * ixgbe_get_hw_dev return device
7356  * used by hardware layer to print debugging information
7357  **/
7358 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7359 {
7360         struct ixgbe_adapter *adapter = hw->back;
7361         return adapter->netdev;
7362 }
7363
7364 module_exit(ixgbe_exit_module);
7365
7366 /* ixgbe_main.c */