drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         clear_check_for_tx_hang(tx_ring);
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int total_bytes = 0, total_packets = 0;
 739         u16 i, eop, count = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774         tx_ring->total_bytes += total_bytes;
 775         tx_ring->total_packets += total_packets;
 776         u64_stats_update_begin(&tx_ring->syncp);
 777         tx_ring->stats.packets += total_packets;
 778         tx_ring->stats.bytes += total_bytes;
 779         u64_stats_update_end(&tx_ring->syncp);
 780
 781         if (check_for_tx_hang(tx_ring) &&
 782             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 783                 /* schedule immediate reset if we believe we hung */
 784                 e_info(probe, "tx hang %d detected, resetting "
 785                        "adapter\n", adapter->tx_timeout_count + 1);
 786                 ixgbe_tx_timeout(adapter->netdev);
 787
 788                 /* the adapter is about to reset, no point in enabling stuff */
 789                 return true;
 790         }
 791
 792 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 793         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 794                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 795                 /* Make sure that anybody stopping the queue after this
 796                  * sees the new next_to_clean.
 797                  */
 798                 smp_mb();
 799                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 800                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 801                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 802                         ++tx_ring->tx_stats.restart_queue;
 803                 }
 804         }
 805
 806         return count < tx_ring->work_limit;
 807 }
 808
 809 #ifdef CONFIG_IXGBE_DCA
 810 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 811                                 struct ixgbe_ring *rx_ring,
 812                                 int cpu)
 813 {
 814         struct ixgbe_hw *hw = &adapter->hw;
 815         u32 rxctrl;
 816         u8 reg_idx = rx_ring->reg_idx;
 817
 818         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 819         switch (hw->mac.type) {
 820         case ixgbe_mac_82598EB:
 821                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 822                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 823                 break;
 824         case ixgbe_mac_82599EB:
 825                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 826                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 827                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 828                 break;
 829         default:
 830                 break;
 831         }
 832         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 833         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 834         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 835         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 836                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 837         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 838 }
 839
 840 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 841                                 struct ixgbe_ring *tx_ring,
 842                                 int cpu)
 843 {
 844         struct ixgbe_hw *hw = &adapter->hw;
 845         u32 txctrl;
 846         u8 reg_idx = tx_ring->reg_idx;
 847
 848         switch (hw->mac.type) {
 849         case ixgbe_mac_82598EB:
 850                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 851                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 852                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 853                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 854                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 855                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 856                 break;
 857         case ixgbe_mac_82599EB:
 858                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 859                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 860                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 861                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 862                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 863                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 864                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 865                 break;
 866         default:
 867                 break;
 868         }
 869 }
 870
 871 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 872 {
 873         struct ixgbe_adapter *adapter = q_vector->adapter;
 874         int cpu = get_cpu();
 875         long r_idx;
 876         int i;
 877
 878         if (q_vector->cpu == cpu)
 879                 goto out_no_update;
 880
 881         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 882         for (i = 0; i < q_vector->txr_count; i++) {
 883                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 884                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 885                                       r_idx + 1);
 886         }
 887
 888         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 889         for (i = 0; i < q_vector->rxr_count; i++) {
 890                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 891                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 892                                       r_idx + 1);
 893         }
 894
 895         q_vector->cpu = cpu;
 896 out_no_update:
 897         put_cpu();
 898 }
 899
 900 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 901 {
 902         int num_q_vectors;
 903         int i;
 904
 905         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 906                 return;
 907
 908         /* always use CB2 mode, difference is masked in the CB driver */
 909         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 910
 911         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 912                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 913         else
 914                 num_q_vectors = 1;
 915
 916         for (i = 0; i < num_q_vectors; i++) {
 917                 adapter->q_vector[i]->cpu = -1;
 918                 ixgbe_update_dca(adapter->q_vector[i]);
 919         }
 920 }
 921
 922 static int __ixgbe_notify_dca(struct device *dev, void *data)
 923 {
 924         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 925         unsigned long event = *(unsigned long *)data;
 926
 927         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 928                 return 0;
 929
 930         switch (event) {
 931         case DCA_PROVIDER_ADD:
 932                 /* if we're already enabled, don't do it again */
 933                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 934                         break;
 935                 if (dca_add_requester(dev) == 0) {
 936                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 937                         ixgbe_setup_dca(adapter);
 938                         break;
 939                 }
 940                 /* Fall Through since DCA is disabled. */
 941         case DCA_PROVIDER_REMOVE:
 942                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 943                         dca_remove_requester(dev);
 944                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 945                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 946                 }
 947                 break;
 948         }
 949
 950         return 0;
 951 }
 952
 953 #endif /* CONFIG_IXGBE_DCA */
 954 /**
 955  * ixgbe_receive_skb - Send a completed packet up the stack
 956  * @adapter: board private structure
 957  * @skb: packet to send up
 958  * @status: hardware indication of status of receive
 959  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 960  * @rx_desc: rx descriptor
 961  **/
 962 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 963                               struct sk_buff *skb, u8 status,
 964                               struct ixgbe_ring *ring,
 965                               union ixgbe_adv_rx_desc *rx_desc)
 966 {
 967         struct ixgbe_adapter *adapter = q_vector->adapter;
 968         struct napi_struct *napi = &q_vector->napi;
 969         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 970         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 971
 972         if (is_vlan && (tag & VLAN_VID_MASK))
 973                 __vlan_hwaccel_put_tag(skb, tag);
 974
 975         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 976                 napi_gro_receive(napi, skb);
 977         else
 978                 netif_rx(skb);
 979 }
 980
 981 /**
 982  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 983  * @adapter: address of board private structure
 984  * @status_err: hardware indication of status of receive
 985  * @skb: skb currently being received and modified
 986  **/
 987 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 988                                      union ixgbe_adv_rx_desc *rx_desc,
 989                                      struct sk_buff *skb)
 990 {
 991         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 992
 993         skb_checksum_none_assert(skb);
 994
 995         /* Rx csum disabled */
 996         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 997                 return;
 998
 999         /* if IP and error */
1000         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1001             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1002                 adapter->hw_csum_rx_error++;
1003                 return;
1004         }
1005
1006         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1007                 return;
1008
1009         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1010                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1011
1012                 /*
1013                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1014                  * checksum errors.
1015                  */
1016                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1017                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1018                         return;
1019
1020                 adapter->hw_csum_rx_error++;
1021                 return;
1022         }
1023
1024         /* It must be a TCP or UDP packet with a valid checksum */
1025         skb->ip_summed = CHECKSUM_UNNECESSARY;
1026 }
1027
1028 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1029 {
1030         /*
1031          * Force memory writes to complete before letting h/w
1032          * know there are new descriptors to fetch.  (Only
1033          * applicable for weak-ordered memory model archs,
1034          * such as IA-64).
1035          */
1036         wmb();
1037         writel(val, rx_ring->tail);
1038 }
1039
1040 /**
1041  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1042  * @rx_ring: ring to place buffers on
1043  * @cleaned_count: number of buffers to replace
1044  **/
1045 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1046 {
1047         union ixgbe_adv_rx_desc *rx_desc;
1048         struct ixgbe_rx_buffer *bi;
1049         struct sk_buff *skb;
1050         u16 i = rx_ring->next_to_use;
1051
1052         /* do nothing if no valid netdev defined */
1053         if (!rx_ring->netdev)
1054                 return;
1055
1056         while (cleaned_count--) {
1057                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1058                 bi = &rx_ring->rx_buffer_info[i];
1059                 skb = bi->skb;
1060
1061                 if (!skb) {
1062                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1063                                                         rx_ring->rx_buf_len);
1064                         if (!skb) {
1065                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1066                                 goto no_buffers;
1067                         }
1068                         /* initialize queue mapping */
1069                         skb_record_rx_queue(skb, rx_ring->queue_index);
1070                         bi->skb = skb;
1071                 }
1072
1073                 if (!bi->dma) {
1074                         bi->dma = dma_map_single(rx_ring->dev,
1075                                                  skb->data,
1076                                                  rx_ring->rx_buf_len,
1077                                                  DMA_FROM_DEVICE);
1078                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1079                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1080                                 bi->dma = 0;
1081                                 goto no_buffers;
1082                         }
1083                 }
1084
1085                 if (ring_is_ps_enabled(rx_ring)) {
1086                         if (!bi->page) {
1087                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1088                                 if (!bi->page) {
1089                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1090                                         goto no_buffers;
1091                                 }
1092                         }
1093
1094                         if (!bi->page_dma) {
1095                                 /* use a half page if we're re-using */
1096                                 bi->page_offset ^= PAGE_SIZE / 2;
1097                                 bi->page_dma = dma_map_page(rx_ring->dev,
1098                                                             bi->page,
1099                                                             bi->page_offset,
1100                                                             PAGE_SIZE / 2,
1101                                                             DMA_FROM_DEVICE);
1102                                 if (dma_mapping_error(rx_ring->dev,
1103                                                       bi->page_dma)) {
1104                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1105                                         bi->page_dma = 0;
1106                                         goto no_buffers;
1107                                 }
1108                         }
1109
1110                         /* Refresh the desc even if buffer_addrs didn't change
1111                          * because each write-back erases this info. */
1112                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1113                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1114                 } else {
1115                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1116                         rx_desc->read.hdr_addr = 0;
1117                 }
1118
1119                 i++;
1120                 if (i == rx_ring->count)
1121                         i = 0;
1122         }
1123
1124 no_buffers:
1125         if (rx_ring->next_to_use != i) {
1126                 rx_ring->next_to_use = i;
1127                 ixgbe_release_rx_desc(rx_ring, i);
1128         }
1129 }
1130
1131 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1132 {
1133         /* HW will not DMA in data larger than the given buffer, even if it
1134          * parses the (NFS, of course) header to be larger.  In that case, it
1135          * fills the header buffer and spills the rest into the page.
1136          */
1137         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1138         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1139                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1140         if (hlen > IXGBE_RX_HDR_SIZE)
1141                 hlen = IXGBE_RX_HDR_SIZE;
1142         return hlen;
1143 }
1144
1145 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1146 {
1147         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1148                 IXGBE_RXDADV_RSCCNT_MASK) >>
1149                 IXGBE_RXDADV_RSCCNT_SHIFT;
1150 }
1151
1152 /**
1153  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1154  * @skb: pointer to the last skb in the rsc queue
1155  * @count: pointer to number of packets coalesced in this context
1156  *
1157  * This function changes a queue full of hw rsc buffers into a completed
1158  * packet.  It uses the ->prev pointers to find the first packet and then
1159  * turns it into the frag list owner.
1160  **/
1161 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1162                                                         u64 *count)
1163 {
1164         unsigned int frag_list_size = 0;
1165
1166         while (skb->prev) {
1167                 struct sk_buff *prev = skb->prev;
1168                 frag_list_size += skb->len;
1169                 skb->prev = NULL;
1170                 skb = prev;
1171                 *count += 1;
1172         }
1173
1174         skb_shinfo(skb)->frag_list = skb->next;
1175         skb->next = NULL;
1176         skb->len += frag_list_size;
1177         skb->data_len += frag_list_size;
1178         skb->truesize += frag_list_size;
1179         return skb;
1180 }
1181
1182 struct ixgbe_rsc_cb {
1183         dma_addr_t dma;
1184         bool delay_unmap;
1185 };
1186
1187 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1188
1189 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1190                                struct ixgbe_ring *rx_ring,
1191                                int *work_done, int work_to_do)
1192 {
1193         struct ixgbe_adapter *adapter = q_vector->adapter;
1194         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1195         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1196         struct sk_buff *skb;
1197         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1198         const int current_node = numa_node_id();
1199         unsigned int rsc_count = 0;
1200 #ifdef IXGBE_FCOE
1201         int ddp_bytes = 0;
1202 #endif /* IXGBE_FCOE */
1203         u32 staterr;
1204         u16 i;
1205         u16 cleaned_count = 0;
1206
1207         i = rx_ring->next_to_clean;
1208         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1209         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1210
1211         while (staterr & IXGBE_RXD_STAT_DD) {
1212                 u32 upper_len = 0;
1213
1214                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1215
1216                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1217
1218                 skb = rx_buffer_info->skb;
1219                 rx_buffer_info->skb = NULL;
1220                 prefetch(skb->data);
1221
1222                 if (ring_is_rsc_enabled(rx_ring))
1223                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1224
1225                 /* if this is a skb from previous receive DMA will be 0 */
1226                 if (rx_buffer_info->dma) {
1227                         u16 hlen;
1228                         if (rsc_count &&
1229                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1230                             !skb->prev) {
1231                                 /*
1232                                  * When HWRSC is enabled, delay unmapping
1233                                  * of the first packet. It carries the
1234                                  * header information, HW may still
1235                                  * access the header after the writeback.
1236                                  * Only unmap it when EOP is reached
1237                                  */
1238                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1239                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1240                         } else {
1241                                 dma_unmap_single(rx_ring->dev,
1242                                                  rx_buffer_info->dma,
1243                                                  rx_ring->rx_buf_len,
1244                                                  DMA_FROM_DEVICE);
1245                         }
1246                         rx_buffer_info->dma = 0;
1247
1248                         if (ring_is_ps_enabled(rx_ring)) {
1249                                 hlen = ixgbe_get_hlen(rx_desc);
1250                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1251                         } else {
1252                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1253                         }
1254
1255                         skb_put(skb, hlen);
1256                 } else {
1257                         /* assume packet split since header is unmapped */
1258                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1259                 }
1260
1261                 if (upper_len) {
1262                         dma_unmap_page(rx_ring->dev,
1263                                        rx_buffer_info->page_dma,
1264                                        PAGE_SIZE / 2,
1265                                        DMA_FROM_DEVICE);
1266                         rx_buffer_info->page_dma = 0;
1267                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1268                                            rx_buffer_info->page,
1269                                            rx_buffer_info->page_offset,
1270                                            upper_len);
1271
1272                         if ((page_count(rx_buffer_info->page) == 1) &&
1273                             (page_to_nid(rx_buffer_info->page) == current_node))
1274                                 get_page(rx_buffer_info->page);
1275                         else
1276                                 rx_buffer_info->page = NULL;
1277
1278                         skb->len += upper_len;
1279                         skb->data_len += upper_len;
1280                         skb->truesize += upper_len;
1281                 }
1282
1283                 i++;
1284                 if (i == rx_ring->count)
1285                         i = 0;
1286
1287                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1288                 prefetch(next_rxd);
1289                 cleaned_count++;
1290
1291                 if (rsc_count) {
1292                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1293                                      IXGBE_RXDADV_NEXTP_SHIFT;
1294                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1295                 } else {
1296                         next_buffer = &rx_ring->rx_buffer_info[i];
1297                 }
1298
1299                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1300                         if (ring_is_ps_enabled(rx_ring)) {
1301                                 rx_buffer_info->skb = next_buffer->skb;
1302                                 rx_buffer_info->dma = next_buffer->dma;
1303                                 next_buffer->skb = skb;
1304                                 next_buffer->dma = 0;
1305                         } else {
1306                                 skb->next = next_buffer->skb;
1307                                 skb->next->prev = skb;
1308                         }
1309                         rx_ring->rx_stats.non_eop_descs++;
1310                         goto next_desc;
1311                 }
1312
1313                 if (skb->prev)
1314                         skb = ixgbe_transform_rsc_queue(skb,
1315                                                 &(rx_ring->rx_stats.rsc_count));
1316
1317                 if (ring_is_rsc_enabled(rx_ring)) {
1318                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1319                                 dma_unmap_single(rx_ring->dev,
1320                                                  IXGBE_RSC_CB(skb)->dma,
1321                                                  rx_ring->rx_buf_len,
1322                                                  DMA_FROM_DEVICE);
1323                                 IXGBE_RSC_CB(skb)->dma = 0;
1324                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1325                         }
1326                         if (ring_is_ps_enabled(rx_ring))
1327                                 rx_ring->rx_stats.rsc_count +=
1328                                          skb_shinfo(skb)->nr_frags;
1329                         else
1330                                 rx_ring->rx_stats.rsc_count++;
1331                         rx_ring->rx_stats.rsc_flush++;
1332                 }
1333
1334                 /* ERR_MASK will only have valid bits if EOP set */
1335                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1336                         /* trim packet back to size 0 and recycle it */
1337                         __pskb_trim(skb, 0);
1338                         rx_buffer_info->skb = skb;
1339                         goto next_desc;
1340                 }
1341
1342                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1343
1344                 /* probably a little skewed due to removing CRC */
1345                 total_rx_bytes += skb->len;
1346                 total_rx_packets++;
1347
1348                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1349 #ifdef IXGBE_FCOE
1350                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1351                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1352                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1353                         if (!ddp_bytes)
1354                                 goto next_desc;
1355                 }
1356 #endif /* IXGBE_FCOE */
1357                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1358
1359 next_desc:
1360                 rx_desc->wb.upper.status_error = 0;
1361
1362                 (*work_done)++;
1363                 if (*work_done >= work_to_do)
1364                         break;
1365
1366                 /* return some buffers to hardware, one at a time is too slow */
1367                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1368                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1369                         cleaned_count = 0;
1370                 }
1371
1372                 /* use prefetched values */
1373                 rx_desc = next_rxd;
1374                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1375         }
1376
1377         rx_ring->next_to_clean = i;
1378         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1379
1380         if (cleaned_count)
1381                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1382
1383 #ifdef IXGBE_FCOE
1384         /* include DDPed FCoE data */
1385         if (ddp_bytes > 0) {
1386                 unsigned int mss;
1387
1388                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1389                         sizeof(struct fc_frame_header) -
1390                         sizeof(struct fcoe_crc_eof);
1391                 if (mss > 512)
1392                         mss &= ~511;
1393                 total_rx_bytes += ddp_bytes;
1394                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1395         }
1396 #endif /* IXGBE_FCOE */
1397
1398         rx_ring->total_packets += total_rx_packets;
1399         rx_ring->total_bytes += total_rx_bytes;
1400         u64_stats_update_begin(&rx_ring->syncp);
1401         rx_ring->stats.packets += total_rx_packets;
1402         rx_ring->stats.bytes += total_rx_bytes;
1403         u64_stats_update_end(&rx_ring->syncp);
1404 }
1405
1406 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1407 /**
1408  * ixgbe_configure_msix - Configure MSI-X hardware
1409  * @adapter: board private structure
1410  *
1411  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1412  * interrupts.
1413  **/
1414 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1415 {
1416         struct ixgbe_q_vector *q_vector;
1417         int i, j, q_vectors, v_idx, r_idx;
1418         u32 mask;
1419
1420         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1421
1422         /*
1423          * Populate the IVAR table and set the ITR values to the
1424          * corresponding register.
1425          */
1426         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1427                 q_vector = adapter->q_vector[v_idx];
1428                 /* XXX for_each_set_bit(...) */
1429                 r_idx = find_first_bit(q_vector->rxr_idx,
1430                                        adapter->num_rx_queues);
1431
1432                 for (i = 0; i < q_vector->rxr_count; i++) {
1433                         j = adapter->rx_ring[r_idx]->reg_idx;
1434                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1435                         r_idx = find_next_bit(q_vector->rxr_idx,
1436                                               adapter->num_rx_queues,
1437                                               r_idx + 1);
1438                 }
1439                 r_idx = find_first_bit(q_vector->txr_idx,
1440                                        adapter->num_tx_queues);
1441
1442                 for (i = 0; i < q_vector->txr_count; i++) {
1443                         j = adapter->tx_ring[r_idx]->reg_idx;
1444                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1445                         r_idx = find_next_bit(q_vector->txr_idx,
1446                                               adapter->num_tx_queues,
1447                                               r_idx + 1);
1448                 }
1449
1450                 if (q_vector->txr_count && !q_vector->rxr_count)
1451                         /* tx only */
1452                         q_vector->eitr = adapter->tx_eitr_param;
1453                 else if (q_vector->rxr_count)
1454                         /* rx or mixed */
1455                         q_vector->eitr = adapter->rx_eitr_param;
1456
1457                 ixgbe_write_eitr(q_vector);
1458                 /* If Flow Director is enabled, set interrupt affinity */
1459                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1460                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1461                         /*
1462                          * Allocate the affinity_hint cpumask, assign the mask
1463                          * for this vector, and set our affinity_hint for
1464                          * this irq.
1465                          */
1466                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1467                                                GFP_KERNEL))
1468                                 return;
1469                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1470                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1471                                               q_vector->affinity_mask);
1472                 }
1473         }
1474
1475         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1476                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1477                                v_idx);
1478         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1479                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1480         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1481
1482         /* set up to autoclear timer, and the vectors */
1483         mask = IXGBE_EIMS_ENABLE_MASK;
1484         if (adapter->num_vfs)
1485                 mask &= ~(IXGBE_EIMS_OTHER |
1486                           IXGBE_EIMS_MAILBOX |
1487                           IXGBE_EIMS_LSC);
1488         else
1489                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1490         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1491 }
1492
1493 enum latency_range {
1494         lowest_latency = 0,
1495         low_latency = 1,
1496         bulk_latency = 2,
1497         latency_invalid = 255
1498 };
1499
1500 /**
1501  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1502  * @adapter: pointer to adapter
1503  * @eitr: eitr setting (ints per sec) to give last timeslice
1504  * @itr_setting: current throttle rate in ints/second
1505  * @packets: the number of packets during this measurement interval
1506  * @bytes: the number of bytes during this measurement interval
1507  *
1508  *      Stores a new ITR value based on packets and byte
1509  *      counts during the last interrupt.  The advantage of per interrupt
1510  *      computation is faster updates and more accurate ITR for the current
1511  *      traffic pattern.  Constants in this function were computed
1512  *      based on theoretical maximum wire speed and thresholds were set based
1513  *      on testing data as well as attempting to minimize response time
1514  *      while increasing bulk throughput.
1515  *      this functionality is controlled by the InterruptThrottleRate module
1516  *      parameter (see ixgbe_param.c)
1517  **/
1518 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1519                            u32 eitr, u8 itr_setting,
1520                            int packets, int bytes)
1521 {
1522         unsigned int retval = itr_setting;
1523         u32 timepassed_us;
1524         u64 bytes_perint;
1525
1526         if (packets == 0)
1527                 goto update_itr_done;
1528
1529
1530         /* simple throttlerate management
1531          *    0-20MB/s lowest (100000 ints/s)
1532          *   20-100MB/s low   (20000 ints/s)
1533          *  100-1249MB/s bulk (8000 ints/s)
1534          */
1535         /* what was last interrupt timeslice? */
1536         timepassed_us = 1000000/eitr;
1537         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1538
1539         switch (itr_setting) {
1540         case lowest_latency:
1541                 if (bytes_perint > adapter->eitr_low)
1542                         retval = low_latency;
1543                 break;
1544         case low_latency:
1545                 if (bytes_perint > adapter->eitr_high)
1546                         retval = bulk_latency;
1547                 else if (bytes_perint <= adapter->eitr_low)
1548                         retval = lowest_latency;
1549                 break;
1550         case bulk_latency:
1551                 if (bytes_perint <= adapter->eitr_high)
1552                         retval = low_latency;
1553                 break;
1554         }
1555
1556 update_itr_done:
1557         return retval;
1558 }
1559
1560 /**
1561  * ixgbe_write_eitr - write EITR register in hardware specific way
1562  * @q_vector: structure containing interrupt and ring information
1563  *
1564  * This function is made to be called by ethtool and by the driver
1565  * when it needs to update EITR registers at runtime.  Hardware
1566  * specific quirks/differences are taken care of here.
1567  */
1568 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1569 {
1570         struct ixgbe_adapter *adapter = q_vector->adapter;
1571         struct ixgbe_hw *hw = &adapter->hw;
1572         int v_idx = q_vector->v_idx;
1573         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1574
1575         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1576                 /* must write high and low 16 bits to reset counter */
1577                 itr_reg |= (itr_reg << 16);
1578         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1579                 /*
1580                  * 82599 can support a value of zero, so allow it for
1581                  * max interrupt rate, but there is an errata where it can
1582                  * not be zero with RSC
1583                  */
1584                 if (itr_reg == 8 &&
1585                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1586                         itr_reg = 0;
1587
1588                 /*
1589                  * set the WDIS bit to not clear the timer bits and cause an
1590                  * immediate assertion of the interrupt
1591                  */
1592                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1593         }
1594         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1595 }
1596
1597 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1598 {
1599         struct ixgbe_adapter *adapter = q_vector->adapter;
1600         u32 new_itr;
1601         u8 current_itr, ret_itr;
1602         int i, r_idx;
1603         struct ixgbe_ring *rx_ring, *tx_ring;
1604
1605         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1606         for (i = 0; i < q_vector->txr_count; i++) {
1607                 tx_ring = adapter->tx_ring[r_idx];
1608                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1609                                            q_vector->tx_itr,
1610                                            tx_ring->total_packets,
1611                                            tx_ring->total_bytes);
1612                 /* if the result for this queue would decrease interrupt
1613                  * rate for this vector then use that result */
1614                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1615                                     q_vector->tx_itr - 1 : ret_itr);
1616                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1617                                       r_idx + 1);
1618         }
1619
1620         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1621         for (i = 0; i < q_vector->rxr_count; i++) {
1622                 rx_ring = adapter->rx_ring[r_idx];
1623                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1624                                            q_vector->rx_itr,
1625                                            rx_ring->total_packets,
1626                                            rx_ring->total_bytes);
1627                 /* if the result for this queue would decrease interrupt
1628                  * rate for this vector then use that result */
1629                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1630                                     q_vector->rx_itr - 1 : ret_itr);
1631                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1632                                       r_idx + 1);
1633         }
1634
1635         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1636
1637         switch (current_itr) {
1638         /* counts and packets in update_itr are dependent on these numbers */
1639         case lowest_latency:
1640                 new_itr = 100000;
1641                 break;
1642         case low_latency:
1643                 new_itr = 20000; /* aka hwitr = ~200 */
1644                 break;
1645         case bulk_latency:
1646         default:
1647                 new_itr = 8000;
1648                 break;
1649         }
1650
1651         if (new_itr != q_vector->eitr) {
1652                 /* do an exponential smoothing */
1653                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1654
1655                 /* save the algorithm value here, not the smoothed one */
1656                 q_vector->eitr = new_itr;
1657
1658                 ixgbe_write_eitr(q_vector);
1659         }
1660 }
1661
1662 /**
1663  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1664  * @work: pointer to work_struct containing our data
1665  **/
1666 static void ixgbe_check_overtemp_task(struct work_struct *work)
1667 {
1668         struct ixgbe_adapter *adapter = container_of(work,
1669                                                      struct ixgbe_adapter,
1670                                                      check_overtemp_task);
1671         struct ixgbe_hw *hw = &adapter->hw;
1672         u32 eicr = adapter->interrupt_event;
1673
1674         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1675                 return;
1676
1677         switch (hw->device_id) {
1678         case IXGBE_DEV_ID_82599_T3_LOM: {
1679                 u32 autoneg;
1680                 bool link_up = false;
1681
1682                 if (hw->mac.ops.check_link)
1683                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1684
1685                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1686                     (eicr & IXGBE_EICR_LSC))
1687                         /* Check if this is due to overtemp */
1688                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1689                                 break;
1690                 return;
1691         }
1692         default:
1693                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1694                         return;
1695                 break;
1696         }
1697         e_crit(drv,
1698                "Network adapter has been stopped because it has over heated. "
1699                "Restart the computer. If the problem persists, "
1700                "power off the system and replace the adapter\n");
1701         /* write to clear the interrupt */
1702         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1703 }
1704
1705 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1706 {
1707         struct ixgbe_hw *hw = &adapter->hw;
1708
1709         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1710             (eicr & IXGBE_EICR_GPI_SDP1)) {
1711                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1712                 /* write to clear the interrupt */
1713                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1714         }
1715 }
1716
1717 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1718 {
1719         struct ixgbe_hw *hw = &adapter->hw;
1720
1721         if (eicr & IXGBE_EICR_GPI_SDP2) {
1722                 /* Clear the interrupt */
1723                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1724                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1725                         schedule_work(&adapter->sfp_config_module_task);
1726         }
1727
1728         if (eicr & IXGBE_EICR_GPI_SDP1) {
1729                 /* Clear the interrupt */
1730                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1731                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1732                         schedule_work(&adapter->multispeed_fiber_task);
1733         }
1734 }
1735
1736 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1737 {
1738         struct ixgbe_hw *hw = &adapter->hw;
1739
1740         adapter->lsc_int++;
1741         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1742         adapter->link_check_timeout = jiffies;
1743         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1744                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1745                 IXGBE_WRITE_FLUSH(hw);
1746                 schedule_work(&adapter->watchdog_task);
1747         }
1748 }
1749
1750 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1751 {
1752         struct net_device *netdev = data;
1753         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1754         struct ixgbe_hw *hw = &adapter->hw;
1755         u32 eicr;
1756
1757         /*
1758          * Workaround for Silicon errata.  Use clear-by-write instead
1759          * of clear-by-read.  Reading with EICS will return the
1760          * interrupt causes without clearing, which later be done
1761          * with the write to EICR.
1762          */
1763         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1764         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1765
1766         if (eicr & IXGBE_EICR_LSC)
1767                 ixgbe_check_lsc(adapter);
1768
1769         if (eicr & IXGBE_EICR_MAILBOX)
1770                 ixgbe_msg_task(adapter);
1771
1772         if (hw->mac.type == ixgbe_mac_82598EB)
1773                 ixgbe_check_fan_failure(adapter, eicr);
1774
1775         if (hw->mac.type == ixgbe_mac_82599EB) {
1776                 ixgbe_check_sfp_event(adapter, eicr);
1777                 adapter->interrupt_event = eicr;
1778                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1779                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1780                         schedule_work(&adapter->check_overtemp_task);
1781
1782                 /* Handle Flow Director Full threshold interrupt */
1783                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1784                         int i;
1785                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1786                         /* Disable transmits before FDIR Re-initialization */
1787                         netif_tx_stop_all_queues(netdev);
1788                         for (i = 0; i < adapter->num_tx_queues; i++) {
1789                                 struct ixgbe_ring *tx_ring =
1790                                                             adapter->tx_ring[i];
1791                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1792                                                        &tx_ring->state))
1793                                         schedule_work(&adapter->fdir_reinit_task);
1794                         }
1795                 }
1796         }
1797         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1798                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1799
1800         return IRQ_HANDLED;
1801 }
1802
1803 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1804                                            u64 qmask)
1805 {
1806         u32 mask;
1807
1808         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1809                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1810                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1811         } else {
1812                 mask = (qmask & 0xFFFFFFFF);
1813                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1814                 mask = (qmask >> 32);
1815                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1816         }
1817         /* skip the flush */
1818 }
1819
1820 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1821                                             u64 qmask)
1822 {
1823         u32 mask;
1824
1825         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1827                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1828         } else {
1829                 mask = (qmask & 0xFFFFFFFF);
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1831                 mask = (qmask >> 32);
1832                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1833         }
1834         /* skip the flush */
1835 }
1836
1837 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1838 {
1839         struct ixgbe_q_vector *q_vector = data;
1840         struct ixgbe_adapter  *adapter = q_vector->adapter;
1841         struct ixgbe_ring     *tx_ring;
1842         int i, r_idx;
1843
1844         if (!q_vector->txr_count)
1845                 return IRQ_HANDLED;
1846
1847         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1848         for (i = 0; i < q_vector->txr_count; i++) {
1849                 tx_ring = adapter->tx_ring[r_idx];
1850                 tx_ring->total_bytes = 0;
1851                 tx_ring->total_packets = 0;
1852                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1853                                       r_idx + 1);
1854         }
1855
1856         /* EIAM disabled interrupts (on this vector) for us */
1857         napi_schedule(&q_vector->napi);
1858
1859         return IRQ_HANDLED;
1860 }
1861
1862 /**
1863  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1864  * @irq: unused
1865  * @data: pointer to our q_vector struct for this interrupt vector
1866  **/
1867 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1868 {
1869         struct ixgbe_q_vector *q_vector = data;
1870         struct ixgbe_adapter  *adapter = q_vector->adapter;
1871         struct ixgbe_ring  *rx_ring;
1872         int r_idx;
1873         int i;
1874
1875 #ifdef CONFIG_IXGBE_DCA
1876         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1877                 ixgbe_update_dca(q_vector);
1878 #endif
1879
1880         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1881         for (i = 0; i < q_vector->rxr_count; i++) {
1882                 rx_ring = adapter->rx_ring[r_idx];
1883                 rx_ring->total_bytes = 0;
1884                 rx_ring->total_packets = 0;
1885                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1886                                       r_idx + 1);
1887         }
1888
1889         if (!q_vector->rxr_count)
1890                 return IRQ_HANDLED;
1891
1892         /* EIAM disabled interrupts (on this vector) for us */
1893         napi_schedule(&q_vector->napi);
1894
1895         return IRQ_HANDLED;
1896 }
1897
1898 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1899 {
1900         struct ixgbe_q_vector *q_vector = data;
1901         struct ixgbe_adapter  *adapter = q_vector->adapter;
1902         struct ixgbe_ring  *ring;
1903         int r_idx;
1904         int i;
1905
1906         if (!q_vector->txr_count && !q_vector->rxr_count)
1907                 return IRQ_HANDLED;
1908
1909         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1910         for (i = 0; i < q_vector->txr_count; i++) {
1911                 ring = adapter->tx_ring[r_idx];
1912                 ring->total_bytes = 0;
1913                 ring->total_packets = 0;
1914                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1915                                       r_idx + 1);
1916         }
1917
1918         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1919         for (i = 0; i < q_vector->rxr_count; i++) {
1920                 ring = adapter->rx_ring[r_idx];
1921                 ring->total_bytes = 0;
1922                 ring->total_packets = 0;
1923                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1924                                       r_idx + 1);
1925         }
1926
1927         /* EIAM disabled interrupts (on this vector) for us */
1928         napi_schedule(&q_vector->napi);
1929
1930         return IRQ_HANDLED;
1931 }
1932
1933 /**
1934  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1935  * @napi: napi struct with our devices info in it
1936  * @budget: amount of work driver is allowed to do this pass, in packets
1937  *
1938  * This function is optimized for cleaning one queue only on a single
1939  * q_vector!!!
1940  **/
1941 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1942 {
1943         struct ixgbe_q_vector *q_vector =
1944                                container_of(napi, struct ixgbe_q_vector, napi);
1945         struct ixgbe_adapter *adapter = q_vector->adapter;
1946         struct ixgbe_ring *rx_ring = NULL;
1947         int work_done = 0;
1948         long r_idx;
1949
1950 #ifdef CONFIG_IXGBE_DCA
1951         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1952                 ixgbe_update_dca(q_vector);
1953 #endif
1954
1955         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1956         rx_ring = adapter->rx_ring[r_idx];
1957
1958         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1959
1960         /* If all Rx work done, exit the polling mode */
1961         if (work_done < budget) {
1962                 napi_complete(napi);
1963                 if (adapter->rx_itr_setting & 1)
1964                         ixgbe_set_itr_msix(q_vector);
1965                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1966                         ixgbe_irq_enable_queues(adapter,
1967                                                 ((u64)1 << q_vector->v_idx));
1968         }
1969
1970         return work_done;
1971 }
1972
1973 /**
1974  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1975  * @napi: napi struct with our devices info in it
1976  * @budget: amount of work driver is allowed to do this pass, in packets
1977  *
1978  * This function will clean more than one rx queue associated with a
1979  * q_vector.
1980  **/
1981 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1982 {
1983         struct ixgbe_q_vector *q_vector =
1984                                container_of(napi, struct ixgbe_q_vector, napi);
1985         struct ixgbe_adapter *adapter = q_vector->adapter;
1986         struct ixgbe_ring *ring = NULL;
1987         int work_done = 0, i;
1988         long r_idx;
1989         bool tx_clean_complete = true;
1990
1991 #ifdef CONFIG_IXGBE_DCA
1992         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1993                 ixgbe_update_dca(q_vector);
1994 #endif
1995
1996         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1997         for (i = 0; i < q_vector->txr_count; i++) {
1998                 ring = adapter->tx_ring[r_idx];
1999                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2000                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2001                                       r_idx + 1);
2002         }
2003
2004         /* attempt to distribute budget to each queue fairly, but don't allow
2005          * the budget to go below 1 because we'll exit polling */
2006         budget /= (q_vector->rxr_count ?: 1);
2007         budget = max(budget, 1);
2008         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2009         for (i = 0; i < q_vector->rxr_count; i++) {
2010                 ring = adapter->rx_ring[r_idx];
2011                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2012                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2013                                       r_idx + 1);
2014         }
2015
2016         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2017         ring = adapter->rx_ring[r_idx];
2018         /* If all Rx work done, exit the polling mode */
2019         if (work_done < budget) {
2020                 napi_complete(napi);
2021                 if (adapter->rx_itr_setting & 1)
2022                         ixgbe_set_itr_msix(q_vector);
2023                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2024                         ixgbe_irq_enable_queues(adapter,
2025                                                 ((u64)1 << q_vector->v_idx));
2026                 return 0;
2027         }
2028
2029         return work_done;
2030 }
2031
2032 /**
2033  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2034  * @napi: napi struct with our devices info in it
2035  * @budget: amount of work driver is allowed to do this pass, in packets
2036  *
2037  * This function is optimized for cleaning one queue only on a single
2038  * q_vector!!!
2039  **/
2040 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2041 {
2042         struct ixgbe_q_vector *q_vector =
2043                                container_of(napi, struct ixgbe_q_vector, napi);
2044         struct ixgbe_adapter *adapter = q_vector->adapter;
2045         struct ixgbe_ring *tx_ring = NULL;
2046         int work_done = 0;
2047         long r_idx;
2048
2049 #ifdef CONFIG_IXGBE_DCA
2050         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2051                 ixgbe_update_dca(q_vector);
2052 #endif
2053
2054         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2055         tx_ring = adapter->tx_ring[r_idx];
2056
2057         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2058                 work_done = budget;
2059
2060         /* If all Tx work done, exit the polling mode */
2061         if (work_done < budget) {
2062                 napi_complete(napi);
2063                 if (adapter->tx_itr_setting & 1)
2064                         ixgbe_set_itr_msix(q_vector);
2065                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2066                         ixgbe_irq_enable_queues(adapter,
2067                                                 ((u64)1 << q_vector->v_idx));
2068         }
2069
2070         return work_done;
2071 }
2072
2073 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2074                                      int r_idx)
2075 {
2076         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2077
2078         set_bit(r_idx, q_vector->rxr_idx);
2079         q_vector->rxr_count++;
2080 }
2081
2082 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2083                                      int t_idx)
2084 {
2085         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2086
2087         set_bit(t_idx, q_vector->txr_idx);
2088         q_vector->txr_count++;
2089 }
2090
2091 /**
2092  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2093  * @adapter: board private structure to initialize
2094  * @vectors: allotted vector count for descriptor rings
2095  *
2096  * This function maps descriptor rings to the queue-specific vectors
2097  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2098  * one vector per ring/queue, but on a constrained vector budget, we
2099  * group the rings as "efficiently" as possible.  You would add new
2100  * mapping configurations in here.
2101  **/
2102 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2103                                       int vectors)
2104 {
2105         int v_start = 0;
2106         int rxr_idx = 0, txr_idx = 0;
2107         int rxr_remaining = adapter->num_rx_queues;
2108         int txr_remaining = adapter->num_tx_queues;
2109         int i, j;
2110         int rqpv, tqpv;
2111         int err = 0;
2112
2113         /* No mapping required if MSI-X is disabled. */
2114         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2115                 goto out;
2116
2117         /*
2118          * The ideal configuration...
2119          * We have enough vectors to map one per queue.
2120          */
2121         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2122                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2123                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2124
2125                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2126                         map_vector_to_txq(adapter, v_start, txr_idx);
2127
2128                 goto out;
2129         }
2130
2131         /*
2132          * If we don't have enough vectors for a 1-to-1
2133          * mapping, we'll have to group them so there are
2134          * multiple queues per vector.
2135          */
2136         /* Re-adjusting *qpv takes care of the remainder. */
2137         for (i = v_start; i < vectors; i++) {
2138                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2139                 for (j = 0; j < rqpv; j++) {
2140                         map_vector_to_rxq(adapter, i, rxr_idx);
2141                         rxr_idx++;
2142                         rxr_remaining--;
2143                 }
2144         }
2145         for (i = v_start; i < vectors; i++) {
2146                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2147                 for (j = 0; j < tqpv; j++) {
2148                         map_vector_to_txq(adapter, i, txr_idx);
2149                         txr_idx++;
2150                         txr_remaining--;
2151                 }
2152         }
2153
2154 out:
2155         return err;
2156 }
2157
2158 /**
2159  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2160  * @adapter: board private structure
2161  *
2162  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2163  * interrupts from the kernel.
2164  **/
2165 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2166 {
2167         struct net_device *netdev = adapter->netdev;
2168         irqreturn_t (*handler)(int, void *);
2169         int i, vector, q_vectors, err;
2170         int ri = 0, ti = 0;
2171
2172         /* Decrement for Other and TCP Timer vectors */
2173         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2174
2175         /* Map the Tx/Rx rings to the vectors we were allotted. */
2176         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2177         if (err)
2178                 goto out;
2179
2180 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2181                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2182                          &ixgbe_msix_clean_many)
2183         for (vector = 0; vector < q_vectors; vector++) {
2184                 handler = SET_HANDLER(adapter->q_vector[vector]);
2185
2186                 if (handler == &ixgbe_msix_clean_rx) {
2187                         sprintf(adapter->name[vector], "%s-%s-%d",
2188                                 netdev->name, "rx", ri++);
2189                 } else if (handler == &ixgbe_msix_clean_tx) {
2190                         sprintf(adapter->name[vector], "%s-%s-%d",
2191                                 netdev->name, "tx", ti++);
2192                 } else {
2193                         sprintf(adapter->name[vector], "%s-%s-%d",
2194                                 netdev->name, "TxRx", ri++);
2195                         ti++;
2196                 }
2197
2198                 err = request_irq(adapter->msix_entries[vector].vector,
2199                                   handler, 0, adapter->name[vector],
2200                                   adapter->q_vector[vector]);
2201                 if (err) {
2202                         e_err(probe, "request_irq failed for MSIX interrupt "
2203                               "Error: %d\n", err);
2204                         goto free_queue_irqs;
2205                 }
2206         }
2207
2208         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2209         err = request_irq(adapter->msix_entries[vector].vector,
2210                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2211         if (err) {
2212                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2213                 goto free_queue_irqs;
2214         }
2215
2216         return 0;
2217
2218 free_queue_irqs:
2219         for (i = vector - 1; i >= 0; i--)
2220                 free_irq(adapter->msix_entries[--vector].vector,
2221                          adapter->q_vector[i]);
2222         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2223         pci_disable_msix(adapter->pdev);
2224         kfree(adapter->msix_entries);
2225         adapter->msix_entries = NULL;
2226 out:
2227         return err;
2228 }
2229
2230 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2231 {
2232         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2233         u8 current_itr;
2234         u32 new_itr = q_vector->eitr;
2235         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2236         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2237
2238         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2239                                             q_vector->tx_itr,
2240                                             tx_ring->total_packets,
2241                                             tx_ring->total_bytes);
2242         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2243                                             q_vector->rx_itr,
2244                                             rx_ring->total_packets,
2245                                             rx_ring->total_bytes);
2246
2247         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2248
2249         switch (current_itr) {
2250         /* counts and packets in update_itr are dependent on these numbers */
2251         case lowest_latency:
2252                 new_itr = 100000;
2253                 break;
2254         case low_latency:
2255                 new_itr = 20000; /* aka hwitr = ~200 */
2256                 break;
2257         case bulk_latency:
2258                 new_itr = 8000;
2259                 break;
2260         default:
2261                 break;
2262         }
2263
2264         if (new_itr != q_vector->eitr) {
2265                 /* do an exponential smoothing */
2266                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2267
2268                 /* save the algorithm value here, not the smoothed one */
2269                 q_vector->eitr = new_itr;
2270
2271                 ixgbe_write_eitr(q_vector);
2272         }
2273 }
2274
2275 /**
2276  * ixgbe_irq_enable - Enable default interrupt generation settings
2277  * @adapter: board private structure
2278  **/
2279 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2280                                     bool flush)
2281 {
2282         u32 mask;
2283
2284         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2285         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2286                 mask |= IXGBE_EIMS_GPI_SDP0;
2287         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2288                 mask |= IXGBE_EIMS_GPI_SDP1;
2289         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2290                 mask |= IXGBE_EIMS_ECC;
2291                 mask |= IXGBE_EIMS_GPI_SDP1;
2292                 mask |= IXGBE_EIMS_GPI_SDP2;
2293                 if (adapter->num_vfs)
2294                         mask |= IXGBE_EIMS_MAILBOX;
2295         }
2296         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2297             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2298                 mask |= IXGBE_EIMS_FLOW_DIR;
2299
2300         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2301         if (queues)
2302                 ixgbe_irq_enable_queues(adapter, ~0);
2303         if (flush)
2304                 IXGBE_WRITE_FLUSH(&adapter->hw);
2305
2306         if (adapter->num_vfs > 32) {
2307                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2308                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2309         }
2310 }
2311
2312 /**
2313  * ixgbe_intr - legacy mode Interrupt Handler
2314  * @irq: interrupt number
2315  * @data: pointer to a network interface device structure
2316  **/
2317 static irqreturn_t ixgbe_intr(int irq, void *data)
2318 {
2319         struct net_device *netdev = data;
2320         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2321         struct ixgbe_hw *hw = &adapter->hw;
2322         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2323         u32 eicr;
2324
2325         /*
2326          * Workaround for silicon errata on 82598.  Mask the interrupts
2327          * before the read of EICR.
2328          */
2329         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2330
2331         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2332          * therefore no explict interrupt disable is necessary */
2333         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2334         if (!eicr) {
2335                 /*
2336                  * shared interrupt alert!
2337                  * make sure interrupts are enabled because the read will
2338                  * have disabled interrupts due to EIAM
2339                  * finish the workaround of silicon errata on 82598.  Unmask
2340                  * the interrupt that we masked before the EICR read.
2341                  */
2342                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2343                         ixgbe_irq_enable(adapter, true, true);
2344                 return IRQ_NONE;        /* Not our interrupt */
2345         }
2346
2347         if (eicr & IXGBE_EICR_LSC)
2348                 ixgbe_check_lsc(adapter);
2349
2350         if (hw->mac.type == ixgbe_mac_82599EB)
2351                 ixgbe_check_sfp_event(adapter, eicr);
2352
2353         ixgbe_check_fan_failure(adapter, eicr);
2354         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2355             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2356                 schedule_work(&adapter->check_overtemp_task);
2357
2358         if (napi_schedule_prep(&(q_vector->napi))) {
2359                 adapter->tx_ring[0]->total_packets = 0;
2360                 adapter->tx_ring[0]->total_bytes = 0;
2361                 adapter->rx_ring[0]->total_packets = 0;
2362                 adapter->rx_ring[0]->total_bytes = 0;
2363                 /* would disable interrupts here but EIAM disabled it */
2364                 __napi_schedule(&(q_vector->napi));
2365         }
2366
2367         /*
2368          * re-enable link(maybe) and non-queue interrupts, no flush.
2369          * ixgbe_poll will re-enable the queue interrupts
2370          */
2371
2372         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2373                 ixgbe_irq_enable(adapter, false, false);
2374
2375         return IRQ_HANDLED;
2376 }
2377
2378 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2379 {
2380         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2381
2382         for (i = 0; i < q_vectors; i++) {
2383                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2384                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2385                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2386                 q_vector->rxr_count = 0;
2387                 q_vector->txr_count = 0;
2388         }
2389 }
2390
2391 /**
2392  * ixgbe_request_irq - initialize interrupts
2393  * @adapter: board private structure
2394  *
2395  * Attempts to configure interrupts using the best available
2396  * capabilities of the hardware and kernel.
2397  **/
2398 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2399 {
2400         struct net_device *netdev = adapter->netdev;
2401         int err;
2402
2403         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2404                 err = ixgbe_request_msix_irqs(adapter);
2405         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2406                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2407                                   netdev->name, netdev);
2408         } else {
2409                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2410                                   netdev->name, netdev);
2411         }
2412
2413         if (err)
2414                 e_err(probe, "request_irq failed, Error %d\n", err);
2415
2416         return err;
2417 }
2418
2419 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2420 {
2421         struct net_device *netdev = adapter->netdev;
2422
2423         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2424                 int i, q_vectors;
2425
2426                 q_vectors = adapter->num_msix_vectors;
2427
2428                 i = q_vectors - 1;
2429                 free_irq(adapter->msix_entries[i].vector, netdev);
2430
2431                 i--;
2432                 for (; i >= 0; i--) {
2433                         free_irq(adapter->msix_entries[i].vector,
2434                                  adapter->q_vector[i]);
2435                 }
2436
2437                 ixgbe_reset_q_vectors(adapter);
2438         } else {
2439                 free_irq(adapter->pdev->irq, netdev);
2440         }
2441 }
2442
2443 /**
2444  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2445  * @adapter: board private structure
2446  **/
2447 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2448 {
2449         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2450                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2451         } else {
2452                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2453                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2454                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2455                 if (adapter->num_vfs > 32)
2456                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2457         }
2458         IXGBE_WRITE_FLUSH(&adapter->hw);
2459         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2460                 int i;
2461                 for (i = 0; i < adapter->num_msix_vectors; i++)
2462                         synchronize_irq(adapter->msix_entries[i].vector);
2463         } else {
2464                 synchronize_irq(adapter->pdev->irq);
2465         }
2466 }
2467
2468 /**
2469  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2470  *
2471  **/
2472 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2473 {
2474         struct ixgbe_hw *hw = &adapter->hw;
2475
2476         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2477                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2478
2479         ixgbe_set_ivar(adapter, 0, 0, 0);
2480         ixgbe_set_ivar(adapter, 1, 0, 0);
2481
2482         map_vector_to_rxq(adapter, 0, 0);
2483         map_vector_to_txq(adapter, 0, 0);
2484
2485         e_info(hw, "Legacy interrupt IVAR setup done\n");
2486 }
2487
2488 /**
2489  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2490  * @adapter: board private structure
2491  * @ring: structure containing ring specific data
2492  *
2493  * Configure the Tx descriptor ring after a reset.
2494  **/
2495 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2496                              struct ixgbe_ring *ring)
2497 {
2498         struct ixgbe_hw *hw = &adapter->hw;
2499         u64 tdba = ring->dma;
2500         int wait_loop = 10;
2501         u32 txdctl;
2502         u16 reg_idx = ring->reg_idx;
2503
2504         /* disable queue to avoid issues while updating state */
2505         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2506         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2507                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2508         IXGBE_WRITE_FLUSH(hw);
2509
2510         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2511                         (tdba & DMA_BIT_MASK(32)));
2512         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2513         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2514                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2515         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2516         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2517         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2518
2519         /* configure fetching thresholds */
2520         if (adapter->rx_itr_setting == 0) {
2521                 /* cannot set wthresh when itr==0 */
2522                 txdctl &= ~0x007F0000;
2523         } else {
2524                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2525                 txdctl |= (8 << 16);
2526         }
2527         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2528                 /* PThresh workaround for Tx hang with DFP enabled. */
2529                 txdctl |= 32;
2530         }
2531
2532         /* reinitialize flowdirector state */
2533         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2534             adapter->atr_sample_rate) {
2535                 ring->atr_sample_rate = adapter->atr_sample_rate;
2536                 ring->atr_count = 0;
2537                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2538         } else {
2539                 ring->atr_sample_rate = 0;
2540         }
2541
2542         /* enable queue */
2543         txdctl |= IXGBE_TXDCTL_ENABLE;
2544         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2545
2546         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2547         if (hw->mac.type == ixgbe_mac_82598EB &&
2548             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2549                 return;
2550
2551         /* poll to verify queue is enabled */
2552         do {
2553                 msleep(1);
2554                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2555         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2556         if (!wait_loop)
2557                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2558 }
2559
2560 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2561 {
2562         struct ixgbe_hw *hw = &adapter->hw;
2563         u32 rttdcs;
2564         u32 mask;
2565
2566         if (hw->mac.type == ixgbe_mac_82598EB)
2567                 return;
2568
2569         /* disable the arbiter while setting MTQC */
2570         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2571         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2572         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2573
2574         /* set transmit pool layout */
2575         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2576         switch (adapter->flags & mask) {
2577
2578         case (IXGBE_FLAG_SRIOV_ENABLED):
2579                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2580                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2581                 break;
2582
2583         case (IXGBE_FLAG_DCB_ENABLED):
2584                 /* We enable 8 traffic classes, DCB only */
2585                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2586                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2587                 break;
2588
2589         default:
2590                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2591                 break;
2592         }
2593
2594         /* re-enable the arbiter */
2595         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2596         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2597 }
2598
2599 /**
2600  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2601  * @adapter: board private structure
2602  *
2603  * Configure the Tx unit of the MAC after a reset.
2604  **/
2605 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2606 {
2607         struct ixgbe_hw *hw = &adapter->hw;
2608         u32 dmatxctl;
2609         u32 i;
2610
2611         ixgbe_setup_mtqc(adapter);
2612
2613         if (hw->mac.type != ixgbe_mac_82598EB) {
2614                 /* DMATXCTL.EN must be before Tx queues are enabled */
2615                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2616                 dmatxctl |= IXGBE_DMATXCTL_TE;
2617                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2618         }
2619
2620         /* Setup the HW Tx Head and Tail descriptor pointers */
2621         for (i = 0; i < adapter->num_tx_queues; i++)
2622                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2623 }
2624
2625 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2626
2627 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2628                                    struct ixgbe_ring *rx_ring)
2629 {
2630         u32 srrctl;
2631         int index;
2632         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2633
2634         index = rx_ring->reg_idx;
2635         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2636                 unsigned long mask;
2637                 mask = (unsigned long) feature[RING_F_RSS].mask;
2638                 index = index & mask;
2639         }
2640         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2641
2642         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2643         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2644         if (adapter->num_vfs)
2645                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2646
2647         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2648                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2649
2650         if (ring_is_ps_enabled(rx_ring)) {
2651 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2652                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2653 #else
2654                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2655 #endif
2656                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2657         } else {
2658                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2659                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2660                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2661         }
2662
2663         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2664 }
2665
2666 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2667 {
2668         struct ixgbe_hw *hw = &adapter->hw;
2669         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2670                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2671                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2672         u32 mrqc = 0, reta = 0;
2673         u32 rxcsum;
2674         int i, j;
2675         int mask;
2676
2677         /* Fill out hash function seeds */
2678         for (i = 0; i < 10; i++)
2679                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2680
2681         /* Fill out redirection table */
2682         for (i = 0, j = 0; i < 128; i++, j++) {
2683                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2684                         j = 0;
2685                 /* reta = 4-byte sliding window of
2686                  * 0x00..(indices-1)(indices-1)00..etc. */
2687                 reta = (reta << 8) | (j * 0x11);
2688                 if ((i & 3) == 3)
2689                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2690         }
2691
2692         /* Disable indicating checksum in descriptor, enables RSS hash */
2693         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2694         rxcsum |= IXGBE_RXCSUM_PCSD;
2695         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2696
2697         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2698                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2699         else
2700                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2701 #ifdef CONFIG_IXGBE_DCB
2702                                          | IXGBE_FLAG_DCB_ENABLED
2703 #endif
2704                                          | IXGBE_FLAG_SRIOV_ENABLED
2705                                         );
2706
2707         switch (mask) {
2708         case (IXGBE_FLAG_RSS_ENABLED):
2709                 mrqc = IXGBE_MRQC_RSSEN;
2710                 break;
2711         case (IXGBE_FLAG_SRIOV_ENABLED):
2712                 mrqc = IXGBE_MRQC_VMDQEN;
2713                 break;
2714 #ifdef CONFIG_IXGBE_DCB
2715         case (IXGBE_FLAG_DCB_ENABLED):
2716                 mrqc = IXGBE_MRQC_RT8TCEN;
2717                 break;
2718 #endif /* CONFIG_IXGBE_DCB */
2719         default:
2720                 break;
2721         }
2722
2723         /* Perform hash on these packet types */
2724         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2725               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2726               | IXGBE_MRQC_RSS_FIELD_IPV6
2727               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2728
2729         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2730 }
2731
2732 /**
2733  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2734  * @adapter:    address of board private structure
2735  * @index:      index of ring to set
2736  **/
2737 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2738                                    struct ixgbe_ring *ring)
2739 {
2740         struct ixgbe_hw *hw = &adapter->hw;
2741         u32 rscctrl;
2742         int rx_buf_len;
2743         u16 reg_idx = ring->reg_idx;
2744
2745         if (!ring_is_rsc_enabled(ring))
2746                 return;
2747
2748         rx_buf_len = ring->rx_buf_len;
2749         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2750         rscctrl |= IXGBE_RSCCTL_RSCEN;
2751         /*
2752          * we must limit the number of descriptors so that the
2753          * total size of max desc * buf_len is not greater
2754          * than 65535
2755          */
2756         if (ring_is_ps_enabled(ring)) {
2757 #if (MAX_SKB_FRAGS > 16)
2758                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2759 #elif (MAX_SKB_FRAGS > 8)
2760                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2761 #elif (MAX_SKB_FRAGS > 4)
2762                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2763 #else
2764                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2765 #endif
2766         } else {
2767                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2768                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2769                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2770                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2771                 else
2772                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2773         }
2774         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2775 }
2776
2777 /**
2778  *  ixgbe_set_uta - Set unicast filter table address
2779  *  @adapter: board private structure
2780  *
2781  *  The unicast table address is a register array of 32-bit registers.
2782  *  The table is meant to be used in a way similar to how the MTA is used
2783  *  however due to certain limitations in the hardware it is necessary to
2784  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2785  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2786  **/
2787 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2788 {
2789         struct ixgbe_hw *hw = &adapter->hw;
2790         int i;
2791
2792         /* The UTA table only exists on 82599 hardware and newer */
2793         if (hw->mac.type < ixgbe_mac_82599EB)
2794                 return;
2795
2796         /* we only need to do this if VMDq is enabled */
2797         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2798                 return;
2799
2800         for (i = 0; i < 128; i++)
2801                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2802 }
2803
2804 #define IXGBE_MAX_RX_DESC_POLL 10
2805 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2806                                        struct ixgbe_ring *ring)
2807 {
2808         struct ixgbe_hw *hw = &adapter->hw;
2809         int reg_idx = ring->reg_idx;
2810         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2811         u32 rxdctl;
2812
2813         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2814         if (hw->mac.type == ixgbe_mac_82598EB &&
2815             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2816                 return;
2817
2818         do {
2819                 msleep(1);
2820                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2821         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2822
2823         if (!wait_loop) {
2824                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2825                       "the polling period\n", reg_idx);
2826         }
2827 }
2828
2829 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2830                              struct ixgbe_ring *ring)
2831 {
2832         struct ixgbe_hw *hw = &adapter->hw;
2833         u64 rdba = ring->dma;
2834         u32 rxdctl;
2835         u16 reg_idx = ring->reg_idx;
2836
2837         /* disable queue to avoid issues while updating state */
2838         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2839         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2840                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2841         IXGBE_WRITE_FLUSH(hw);
2842
2843         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2844         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2845         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2846                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2847         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2848         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2849         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2850
2851         ixgbe_configure_srrctl(adapter, ring);
2852         ixgbe_configure_rscctl(adapter, ring);
2853
2854         if (hw->mac.type == ixgbe_mac_82598EB) {
2855                 /*
2856                  * enable cache line friendly hardware writes:
2857                  * PTHRESH=32 descriptors (half the internal cache),
2858                  * this also removes ugly rx_no_buffer_count increment
2859                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2860                  * WTHRESH=8 burst writeback up to two cache lines
2861                  */
2862                 rxdctl &= ~0x3FFFFF;
2863                 rxdctl |=  0x080420;
2864         }
2865
2866         /* enable receive descriptor ring */
2867         rxdctl |= IXGBE_RXDCTL_ENABLE;
2868         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2869
2870         ixgbe_rx_desc_queue_enable(adapter, ring);
2871         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2872 }
2873
2874 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2875 {
2876         struct ixgbe_hw *hw = &adapter->hw;
2877         int p;
2878
2879         /* PSRTYPE must be initialized in non 82598 adapters */
2880         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2881                       IXGBE_PSRTYPE_UDPHDR |
2882                       IXGBE_PSRTYPE_IPV4HDR |
2883                       IXGBE_PSRTYPE_L2HDR |
2884                       IXGBE_PSRTYPE_IPV6HDR;
2885
2886         if (hw->mac.type == ixgbe_mac_82598EB)
2887                 return;
2888
2889         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2890                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2891
2892         for (p = 0; p < adapter->num_rx_pools; p++)
2893                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2894                                 psrtype);
2895 }
2896
2897 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2898 {
2899         struct ixgbe_hw *hw = &adapter->hw;
2900         u32 gcr_ext;
2901         u32 vt_reg_bits;
2902         u32 reg_offset, vf_shift;
2903         u32 vmdctl;
2904
2905         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2906                 return;
2907
2908         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2909         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2910         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2911         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2912
2913         vf_shift = adapter->num_vfs % 32;
2914         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2915
2916         /* Enable only the PF's pool for Tx/Rx */
2917         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2918         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2919         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2920         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2921         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2922
2923         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2924         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2925
2926         /*
2927          * Set up VF register offsets for selected VT Mode,
2928          * i.e. 32 or 64 VFs for SR-IOV
2929          */
2930         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2931         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2932         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2933         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2934
2935         /* enable Tx loopback for VF/PF communication */
2936         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2937 }
2938
2939 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2940 {
2941         struct ixgbe_hw *hw = &adapter->hw;
2942         struct net_device *netdev = adapter->netdev;
2943         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2944         int rx_buf_len;
2945         struct ixgbe_ring *rx_ring;
2946         int i;
2947         u32 mhadd, hlreg0;
2948
2949         /* Decide whether to use packet split mode or not */
2950         /* Do not use packet split if we're in SR-IOV Mode */
2951         if (!adapter->num_vfs)
2952                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2953
2954         /* Set the RX buffer length according to the mode */
2955         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2956                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2957         } else {
2958                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2959                     (netdev->mtu <= ETH_DATA_LEN))
2960                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2961                 else
2962                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2963         }
2964
2965 #ifdef IXGBE_FCOE
2966         /* adjust max frame to be able to do baby jumbo for FCoE */
2967         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2968             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2969                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2970
2971 #endif /* IXGBE_FCOE */
2972         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2973         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2974                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2975                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2976
2977                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2978         }
2979
2980         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2981         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2982         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2983         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2984
2985         /*
2986          * Setup the HW Rx Head and Tail Descriptor Pointers and
2987          * the Base and Length of the Rx Descriptor Ring
2988          */
2989         for (i = 0; i < adapter->num_rx_queues; i++) {
2990                 rx_ring = adapter->rx_ring[i];
2991                 rx_ring->rx_buf_len = rx_buf_len;
2992
2993                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2994                         set_ring_ps_enabled(rx_ring);
2995                 else
2996                         clear_ring_ps_enabled(rx_ring);
2997
2998                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2999                         set_ring_rsc_enabled(rx_ring);
3000                 else
3001                         clear_ring_rsc_enabled(rx_ring);
3002
3003 #ifdef IXGBE_FCOE
3004                 if (netdev->features & NETIF_F_FCOE_MTU) {
3005                         struct ixgbe_ring_feature *f;
3006                         f = &adapter->ring_feature[RING_F_FCOE];
3007                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3008                                 clear_ring_ps_enabled(rx_ring);
3009                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3010                                         rx_ring->rx_buf_len =
3011                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3012                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3013                                    !ring_is_ps_enabled(rx_ring)) {
3014                                 rx_ring->rx_buf_len =
3015                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3016                         }
3017                 }
3018 #endif /* IXGBE_FCOE */
3019         }
3020
3021 }
3022
3023 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3024 {
3025         struct ixgbe_hw *hw = &adapter->hw;
3026         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3027
3028         switch (hw->mac.type) {
3029         case ixgbe_mac_82598EB:
3030                 /*
3031                  * For VMDq support of different descriptor types or
3032                  * buffer sizes through the use of multiple SRRCTL
3033                  * registers, RDRXCTL.MVMEN must be set to 1
3034                  *
3035                  * also, the manual doesn't mention it clearly but DCA hints
3036                  * will only use queue 0's tags unless this bit is set.  Side
3037                  * effects of setting this bit are only that SRRCTL must be
3038                  * fully programmed [0..15]
3039                  */
3040                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3041                 break;
3042         case ixgbe_mac_82599EB:
3043                 /* Disable RSC for ACK packets */
3044                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3045                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3046                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3047                 /* hardware requires some bits to be set by default */
3048                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3049                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3050                 break;
3051         default:
3052                 /* We should do nothing since we don't know this hardware */
3053                 return;
3054         }
3055
3056         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3057 }
3058
3059 /**
3060  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3061  * @adapter: board private structure
3062  *
3063  * Configure the Rx unit of the MAC after a reset.
3064  **/
3065 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3066 {
3067         struct ixgbe_hw *hw = &adapter->hw;
3068         int i;
3069         u32 rxctrl;
3070
3071         /* disable receives while setting up the descriptors */
3072         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3073         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3074
3075         ixgbe_setup_psrtype(adapter);
3076         ixgbe_setup_rdrxctl(adapter);
3077
3078         /* Program registers for the distribution of queues */
3079         ixgbe_setup_mrqc(adapter);
3080
3081         ixgbe_set_uta(adapter);
3082
3083         /* set_rx_buffer_len must be called before ring initialization */
3084         ixgbe_set_rx_buffer_len(adapter);
3085
3086         /*
3087          * Setup the HW Rx Head and Tail Descriptor Pointers and
3088          * the Base and Length of the Rx Descriptor Ring
3089          */
3090         for (i = 0; i < adapter->num_rx_queues; i++)
3091                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3092
3093         /* disable drop enable for 82598 parts */
3094         if (hw->mac.type == ixgbe_mac_82598EB)
3095                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3096
3097         /* enable all receives */
3098         rxctrl |= IXGBE_RXCTRL_RXEN;
3099         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3100 }
3101
3102 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3103 {
3104         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3105         struct ixgbe_hw *hw = &adapter->hw;
3106         int pool_ndx = adapter->num_vfs;
3107
3108         /* add VID to filter table */
3109         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3110         set_bit(vid, adapter->active_vlans);
3111 }
3112
3113 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3114 {
3115         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3116         struct ixgbe_hw *hw = &adapter->hw;
3117         int pool_ndx = adapter->num_vfs;
3118
3119         /* remove VID from filter table */
3120         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3121         clear_bit(vid, adapter->active_vlans);
3122 }
3123
3124 /**
3125  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3126  * @adapter: driver data
3127  */
3128 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3129 {
3130         struct ixgbe_hw *hw = &adapter->hw;
3131         u32 vlnctrl;
3132
3133         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3134         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3135         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3136 }
3137
3138 /**
3139  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3140  * @adapter: driver data
3141  */
3142 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3143 {
3144         struct ixgbe_hw *hw = &adapter->hw;
3145         u32 vlnctrl;
3146
3147         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3148         vlnctrl |= IXGBE_VLNCTRL_VFE;
3149         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3150         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3151 }
3152
3153 /**
3154  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3155  * @adapter: driver data
3156  */
3157 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3158 {
3159         struct ixgbe_hw *hw = &adapter->hw;
3160         u32 vlnctrl;
3161         int i, j;
3162
3163         switch (hw->mac.type) {
3164         case ixgbe_mac_82598EB:
3165                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3166                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3167                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3168                 break;
3169         case ixgbe_mac_82599EB:
3170                 for (i = 0; i < adapter->num_rx_queues; i++) {
3171                         j = adapter->rx_ring[i]->reg_idx;
3172                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3173                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3174                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3175                 }
3176                 break;
3177         default:
3178                 break;
3179         }
3180 }
3181
3182 /**
3183  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3184  * @adapter: driver data
3185  */
3186 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3187 {
3188         struct ixgbe_hw *hw = &adapter->hw;
3189         u32 vlnctrl;
3190         int i, j;
3191
3192         switch (hw->mac.type) {
3193         case ixgbe_mac_82598EB:
3194                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3195                 vlnctrl |= IXGBE_VLNCTRL_VME;
3196                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3197                 break;
3198         case ixgbe_mac_82599EB:
3199                 for (i = 0; i < adapter->num_rx_queues; i++) {
3200                         j = adapter->rx_ring[i]->reg_idx;
3201                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3202                         vlnctrl |= IXGBE_RXDCTL_VME;
3203                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3204                 }
3205                 break;
3206         default:
3207                 break;
3208         }
3209 }
3210
3211 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3212 {
3213         u16 vid;
3214
3215         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3216
3217         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3218                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3219 }
3220
3221 /**
3222  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3223  * @netdev: network interface device structure
3224  *
3225  * Writes unicast address list to the RAR table.
3226  * Returns: -ENOMEM on failure/insufficient address space
3227  *                0 on no addresses written
3228  *                X on writing X addresses to the RAR table
3229  **/
3230 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3231 {
3232         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3233         struct ixgbe_hw *hw = &adapter->hw;
3234         unsigned int vfn = adapter->num_vfs;
3235         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3236         int count = 0;
3237
3238         /* return ENOMEM indicating insufficient memory for addresses */
3239         if (netdev_uc_count(netdev) > rar_entries)
3240                 return -ENOMEM;
3241
3242         if (!netdev_uc_empty(netdev) && rar_entries) {
3243                 struct netdev_hw_addr *ha;
3244                 /* return error if we do not support writing to RAR table */
3245                 if (!hw->mac.ops.set_rar)
3246                         return -ENOMEM;
3247
3248                 netdev_for_each_uc_addr(ha, netdev) {
3249                         if (!rar_entries)
3250                                 break;
3251                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3252                                             vfn, IXGBE_RAH_AV);
3253                         count++;
3254                 }
3255         }
3256         /* write the addresses in reverse order to avoid write combining */
3257         for (; rar_entries > 0 ; rar_entries--)
3258                 hw->mac.ops.clear_rar(hw, rar_entries);
3259
3260         return count;
3261 }
3262
3263 /**
3264  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3265  * @netdev: network interface device structure
3266  *
3267  * The set_rx_method entry point is called whenever the unicast/multicast
3268  * address list or the network interface flags are updated.  This routine is
3269  * responsible for configuring the hardware for proper unicast, multicast and
3270  * promiscuous mode.
3271  **/
3272 void ixgbe_set_rx_mode(struct net_device *netdev)
3273 {
3274         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3275         struct ixgbe_hw *hw = &adapter->hw;
3276         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3277         int count;
3278
3279         /* Check for Promiscuous and All Multicast modes */
3280
3281         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3282
3283         /* set all bits that we expect to always be set */
3284         fctrl |= IXGBE_FCTRL_BAM;
3285         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3286         fctrl |= IXGBE_FCTRL_PMCF;
3287
3288         /* clear the bits we are changing the status of */
3289         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3290
3291         if (netdev->flags & IFF_PROMISC) {
3292                 hw->addr_ctrl.user_set_promisc = true;
3293                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3294                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3295                 /* don't hardware filter vlans in promisc mode */
3296                 ixgbe_vlan_filter_disable(adapter);
3297         } else {
3298                 if (netdev->flags & IFF_ALLMULTI) {
3299                         fctrl |= IXGBE_FCTRL_MPE;
3300                         vmolr |= IXGBE_VMOLR_MPE;
3301                 } else {
3302                         /*
3303                          * Write addresses to the MTA, if the attempt fails
3304                          * then we should just turn on promiscous mode so
3305                          * that we can at least receive multicast traffic
3306                          */
3307                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3308                         vmolr |= IXGBE_VMOLR_ROMPE;
3309                 }
3310                 ixgbe_vlan_filter_enable(adapter);
3311                 hw->addr_ctrl.user_set_promisc = false;
3312                 /*
3313                  * Write addresses to available RAR registers, if there is not
3314                  * sufficient space to store all the addresses then enable
3315                  * unicast promiscous mode
3316                  */
3317                 count = ixgbe_write_uc_addr_list(netdev);
3318                 if (count < 0) {
3319                         fctrl |= IXGBE_FCTRL_UPE;
3320                         vmolr |= IXGBE_VMOLR_ROPE;
3321                 }
3322         }
3323
3324         if (adapter->num_vfs) {
3325                 ixgbe_restore_vf_multicasts(adapter);
3326                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3327                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3328                            IXGBE_VMOLR_ROPE);
3329                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3330         }
3331
3332         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3333
3334         if (netdev->features & NETIF_F_HW_VLAN_RX)
3335                 ixgbe_vlan_strip_enable(adapter);
3336         else
3337                 ixgbe_vlan_strip_disable(adapter);
3338 }
3339
3340 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3341 {
3342         int q_idx;
3343         struct ixgbe_q_vector *q_vector;
3344         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3345
3346         /* legacy and MSI only use one vector */
3347         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3348                 q_vectors = 1;
3349
3350         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3351                 struct napi_struct *napi;
3352                 q_vector = adapter->q_vector[q_idx];
3353                 napi = &q_vector->napi;
3354                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3355                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3356                                 if (q_vector->txr_count == 1)
3357                                         napi->poll = &ixgbe_clean_txonly;
3358                                 else if (q_vector->rxr_count == 1)
3359                                         napi->poll = &ixgbe_clean_rxonly;
3360                         }
3361                 }
3362
3363                 napi_enable(napi);
3364         }
3365 }
3366
3367 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3368 {
3369         int q_idx;
3370         struct ixgbe_q_vector *q_vector;
3371         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3372
3373         /* legacy and MSI only use one vector */
3374         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3375                 q_vectors = 1;
3376
3377         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3378                 q_vector = adapter->q_vector[q_idx];
3379                 napi_disable(&q_vector->napi);
3380         }
3381 }
3382
3383 #ifdef CONFIG_IXGBE_DCB
3384 /*
3385  * ixgbe_configure_dcb - Configure DCB hardware
3386  * @adapter: ixgbe adapter struct
3387  *
3388  * This is called by the driver on open to configure the DCB hardware.
3389  * This is also called by the gennetlink interface when reconfiguring
3390  * the DCB state.
3391  */
3392 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3393 {
3394         struct ixgbe_hw *hw = &adapter->hw;
3395         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3396
3397         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3398                 if (hw->mac.type == ixgbe_mac_82598EB)
3399                         netif_set_gso_max_size(adapter->netdev, 65536);
3400                 return;
3401         }
3402
3403         if (hw->mac.type == ixgbe_mac_82598EB)
3404                 netif_set_gso_max_size(adapter->netdev, 32768);
3405
3406 #ifdef CONFIG_FCOE
3407         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3408                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3409 #endif
3410
3411         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3412                                         DCB_TX_CONFIG);
3413         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3414                                         DCB_RX_CONFIG);
3415
3416         /* Enable VLAN tag insert/strip */
3417         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3418
3419         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3420
3421         /* reconfigure the hardware */
3422         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3423 }
3424
3425 #endif
3426 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3427 {
3428         struct net_device *netdev = adapter->netdev;
3429         struct ixgbe_hw *hw = &adapter->hw;
3430         int i;
3431
3432 #ifdef CONFIG_IXGBE_DCB
3433         ixgbe_configure_dcb(adapter);
3434 #endif
3435
3436         ixgbe_set_rx_mode(netdev);
3437         ixgbe_restore_vlan(adapter);
3438
3439 #ifdef IXGBE_FCOE
3440         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3441                 ixgbe_configure_fcoe(adapter);
3442
3443 #endif /* IXGBE_FCOE */
3444         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3445                 for (i = 0; i < adapter->num_tx_queues; i++)
3446                         adapter->tx_ring[i]->atr_sample_rate =
3447                                                        adapter->atr_sample_rate;
3448                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3449         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3450                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3451         }
3452         ixgbe_configure_virtualization(adapter);
3453
3454         ixgbe_configure_tx(adapter);
3455         ixgbe_configure_rx(adapter);
3456 }
3457
3458 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3459 {
3460         switch (hw->phy.type) {
3461         case ixgbe_phy_sfp_avago:
3462         case ixgbe_phy_sfp_ftl:
3463         case ixgbe_phy_sfp_intel:
3464         case ixgbe_phy_sfp_unknown:
3465         case ixgbe_phy_sfp_passive_tyco:
3466         case ixgbe_phy_sfp_passive_unknown:
3467         case ixgbe_phy_sfp_active_unknown:
3468         case ixgbe_phy_sfp_ftl_active:
3469                 return true;
3470         default:
3471                 return false;
3472         }
3473 }
3474
3475 /**
3476  * ixgbe_sfp_link_config - set up SFP+ link
3477  * @adapter: pointer to private adapter struct
3478  **/
3479 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3480 {
3481         struct ixgbe_hw *hw = &adapter->hw;
3482
3483                 if (hw->phy.multispeed_fiber) {
3484                         /*
3485                          * In multispeed fiber setups, the device may not have
3486                          * had a physical connection when the driver loaded.
3487                          * If that's the case, the initial link configuration
3488                          * couldn't get the MAC into 10G or 1G mode, so we'll
3489                          * never have a link status change interrupt fire.
3490                          * We need to try and force an autonegotiation
3491                          * session, then bring up link.
3492                          */
3493                         hw->mac.ops.setup_sfp(hw);
3494                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3495                                 schedule_work(&adapter->multispeed_fiber_task);
3496                 } else {
3497                         /*
3498                          * Direct Attach Cu and non-multispeed fiber modules
3499                          * still need to be configured properly prior to
3500                          * attempting link.
3501                          */
3502                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3503                                 schedule_work(&adapter->sfp_config_module_task);
3504                 }
3505 }
3506
3507 /**
3508  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3509  * @hw: pointer to private hardware struct
3510  *
3511  * Returns 0 on success, negative on failure
3512  **/
3513 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3514 {
3515         u32 autoneg;
3516         bool negotiation, link_up = false;
3517         u32 ret = IXGBE_ERR_LINK_SETUP;
3518
3519         if (hw->mac.ops.check_link)
3520                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3521
3522         if (ret)
3523                 goto link_cfg_out;
3524
3525         if (hw->mac.ops.get_link_capabilities)
3526                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3527                                                         &negotiation);
3528         if (ret)
3529                 goto link_cfg_out;
3530
3531         if (hw->mac.ops.setup_link)
3532                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3533 link_cfg_out:
3534         return ret;
3535 }
3536
3537 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3538 {
3539         struct ixgbe_hw *hw = &adapter->hw;
3540         u32 gpie = 0;
3541
3542         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3543                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3544                        IXGBE_GPIE_OCD;
3545                 gpie |= IXGBE_GPIE_EIAME;
3546                 /*
3547                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3548                  * this saves a register write for every interrupt
3549                  */
3550                 switch (hw->mac.type) {
3551                 case ixgbe_mac_82598EB:
3552                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3553                         break;
3554                 default:
3555                 case ixgbe_mac_82599EB:
3556                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3557                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3558                         break;
3559                 }
3560         } else {
3561                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3562                  * specifically only auto mask tx and rx interrupts */
3563                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3564         }
3565
3566         /* XXX: to interrupt immediately for EICS writes, enable this */
3567         /* gpie |= IXGBE_GPIE_EIMEN; */
3568
3569         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3570                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3571                 gpie |= IXGBE_GPIE_VTMODE_64;
3572         }
3573
3574         /* Enable fan failure interrupt */
3575         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3576                 gpie |= IXGBE_SDP1_GPIEN;
3577
3578         if (hw->mac.type == ixgbe_mac_82599EB)
3579                 gpie |= IXGBE_SDP1_GPIEN;
3580                 gpie |= IXGBE_SDP2_GPIEN;
3581
3582         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3583 }
3584
3585 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3586 {
3587         struct ixgbe_hw *hw = &adapter->hw;
3588         int err;
3589         u32 ctrl_ext;
3590
3591         ixgbe_get_hw_control(adapter);
3592         ixgbe_setup_gpie(adapter);
3593
3594         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3595                 ixgbe_configure_msix(adapter);
3596         else
3597                 ixgbe_configure_msi_and_legacy(adapter);
3598
3599         /* enable the optics */
3600         if (hw->phy.multispeed_fiber)
3601                 hw->mac.ops.enable_tx_laser(hw);
3602
3603         clear_bit(__IXGBE_DOWN, &adapter->state);
3604         ixgbe_napi_enable_all(adapter);
3605
3606         if (ixgbe_is_sfp(hw)) {
3607                 ixgbe_sfp_link_config(adapter);
3608         } else {
3609                 err = ixgbe_non_sfp_link_config(hw);
3610                 if (err)
3611                         e_err(probe, "link_config FAILED %d\n", err);
3612         }
3613
3614         /* clear any pending interrupts, may auto mask */
3615         IXGBE_READ_REG(hw, IXGBE_EICR);
3616         ixgbe_irq_enable(adapter, true, true);
3617
3618         /*
3619          * If this adapter has a fan, check to see if we had a failure
3620          * before we enabled the interrupt.
3621          */
3622         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3623                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3624                 if (esdp & IXGBE_ESDP_SDP1)
3625                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3626         }
3627
3628         /*
3629          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3630          * arrived before interrupts were enabled but after probe.  Such
3631          * devices wouldn't have their type identified yet. We need to
3632          * kick off the SFP+ module setup first, then try to bring up link.
3633          * If we're not hot-pluggable SFP+, we just need to configure link
3634          * and bring it up.
3635          */
3636         if (hw->phy.type == ixgbe_phy_unknown)
3637                 schedule_work(&adapter->sfp_config_module_task);
3638
3639         /* enable transmits */
3640         netif_tx_start_all_queues(adapter->netdev);
3641
3642         /* bring the link up in the watchdog, this could race with our first
3643          * link up interrupt but shouldn't be a problem */
3644         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3645         adapter->link_check_timeout = jiffies;
3646         mod_timer(&adapter->watchdog_timer, jiffies);
3647
3648         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3649         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3650         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3651         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3652
3653         return 0;
3654 }
3655
3656 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3657 {
3658         WARN_ON(in_interrupt());
3659         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3660                 msleep(1);
3661         ixgbe_down(adapter);
3662         /*
3663          * If SR-IOV enabled then wait a bit before bringing the adapter
3664          * back up to give the VFs time to respond to the reset.  The
3665          * two second wait is based upon the watchdog timer cycle in
3666          * the VF driver.
3667          */
3668         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3669                 msleep(2000);
3670         ixgbe_up(adapter);
3671         clear_bit(__IXGBE_RESETTING, &adapter->state);
3672 }
3673
3674 int ixgbe_up(struct ixgbe_adapter *adapter)
3675 {
3676         /* hardware has been reset, we need to reload some things */
3677         ixgbe_configure(adapter);
3678
3679         return ixgbe_up_complete(adapter);
3680 }
3681
3682 void ixgbe_reset(struct ixgbe_adapter *adapter)
3683 {
3684         struct ixgbe_hw *hw = &adapter->hw;
3685         int err;
3686
3687         err = hw->mac.ops.init_hw(hw);
3688         switch (err) {
3689         case 0:
3690         case IXGBE_ERR_SFP_NOT_PRESENT:
3691                 break;
3692         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3693                 e_dev_err("master disable timed out\n");
3694                 break;
3695         case IXGBE_ERR_EEPROM_VERSION:
3696                 /* We are running on a pre-production device, log a warning */
3697                 e_dev_warn("This device is a pre-production adapter/LOM. "
3698                            "Please be aware there may be issuesassociated with "
3699                            "your hardware.  If you are experiencing problems "
3700                            "please contact your Intel or hardware "
3701                            "representative who provided you with this "
3702                            "hardware.\n");
3703                 break;
3704         default:
3705                 e_dev_err("Hardware Error: %d\n", err);
3706         }
3707
3708         /* reprogram the RAR[0] in case user changed it. */
3709         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3710                             IXGBE_RAH_AV);
3711 }
3712
3713 /**
3714  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3715  * @rx_ring: ring to free buffers from
3716  **/
3717 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3718 {
3719         struct device *dev = rx_ring->dev;
3720         unsigned long size;
3721         u16 i;
3722
3723         /* ring already cleared, nothing to do */
3724         if (!rx_ring->rx_buffer_info)
3725                 return;
3726
3727         /* Free all the Rx ring sk_buffs */
3728         for (i = 0; i < rx_ring->count; i++) {
3729                 struct ixgbe_rx_buffer *rx_buffer_info;
3730
3731                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3732                 if (rx_buffer_info->dma) {
3733                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3734                                          rx_ring->rx_buf_len,
3735                                          DMA_FROM_DEVICE);
3736                         rx_buffer_info->dma = 0;
3737                 }
3738                 if (rx_buffer_info->skb) {
3739                         struct sk_buff *skb = rx_buffer_info->skb;
3740                         rx_buffer_info->skb = NULL;
3741                         do {
3742                                 struct sk_buff *this = skb;
3743                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3744                                         dma_unmap_single(dev,
3745                                                          IXGBE_RSC_CB(this)->dma,
3746                                                          rx_ring->rx_buf_len,
3747                                                          DMA_FROM_DEVICE);
3748                                         IXGBE_RSC_CB(this)->dma = 0;
3749                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3750                                 }
3751                                 skb = skb->prev;
3752                                 dev_kfree_skb(this);
3753                         } while (skb);
3754                 }
3755                 if (!rx_buffer_info->page)
3756                         continue;
3757                 if (rx_buffer_info->page_dma) {
3758                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3759                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3760                         rx_buffer_info->page_dma = 0;
3761                 }
3762                 put_page(rx_buffer_info->page);
3763                 rx_buffer_info->page = NULL;
3764                 rx_buffer_info->page_offset = 0;
3765         }
3766
3767         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3768         memset(rx_ring->rx_buffer_info, 0, size);
3769
3770         /* Zero out the descriptor ring */
3771         memset(rx_ring->desc, 0, rx_ring->size);
3772
3773         rx_ring->next_to_clean = 0;
3774         rx_ring->next_to_use = 0;
3775 }
3776
3777 /**
3778  * ixgbe_clean_tx_ring - Free Tx Buffers
3779  * @tx_ring: ring to be cleaned
3780  **/
3781 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3782 {
3783         struct ixgbe_tx_buffer *tx_buffer_info;
3784         unsigned long size;
3785         u16 i;
3786
3787         /* ring already cleared, nothing to do */
3788         if (!tx_ring->tx_buffer_info)
3789                 return;
3790
3791         /* Free all the Tx ring sk_buffs */
3792         for (i = 0; i < tx_ring->count; i++) {
3793                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3794                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3795         }
3796
3797         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3798         memset(tx_ring->tx_buffer_info, 0, size);
3799
3800         /* Zero out the descriptor ring */
3801         memset(tx_ring->desc, 0, tx_ring->size);
3802
3803         tx_ring->next_to_use = 0;
3804         tx_ring->next_to_clean = 0;
3805 }
3806
3807 /**
3808  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3809  * @adapter: board private structure
3810  **/
3811 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3812 {
3813         int i;
3814
3815         for (i = 0; i < adapter->num_rx_queues; i++)
3816                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3817 }
3818
3819 /**
3820  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3821  * @adapter: board private structure
3822  **/
3823 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3824 {
3825         int i;
3826
3827         for (i = 0; i < adapter->num_tx_queues; i++)
3828                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3829 }
3830
3831 void ixgbe_down(struct ixgbe_adapter *adapter)
3832 {
3833         struct net_device *netdev = adapter->netdev;
3834         struct ixgbe_hw *hw = &adapter->hw;
3835         u32 rxctrl;
3836         u32 txdctl;
3837         int i, j;
3838         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3839
3840         /* signal that we are down to the interrupt handler */
3841         set_bit(__IXGBE_DOWN, &adapter->state);
3842
3843         /* disable receive for all VFs and wait one second */
3844         if (adapter->num_vfs) {
3845                 /* ping all the active vfs to let them know we are going down */
3846                 ixgbe_ping_all_vfs(adapter);
3847
3848                 /* Disable all VFTE/VFRE TX/RX */
3849                 ixgbe_disable_tx_rx(adapter);
3850
3851                 /* Mark all the VFs as inactive */
3852                 for (i = 0 ; i < adapter->num_vfs; i++)
3853                         adapter->vfinfo[i].clear_to_send = 0;
3854         }
3855
3856         /* disable receives */
3857         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3858         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3859
3860         IXGBE_WRITE_FLUSH(hw);
3861         msleep(10);
3862
3863         netif_tx_stop_all_queues(netdev);
3864
3865         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3866         del_timer_sync(&adapter->sfp_timer);
3867         del_timer_sync(&adapter->watchdog_timer);
3868         cancel_work_sync(&adapter->watchdog_task);
3869
3870         netif_carrier_off(netdev);
3871         netif_tx_disable(netdev);
3872
3873         ixgbe_irq_disable(adapter);
3874
3875         ixgbe_napi_disable_all(adapter);
3876
3877         /* Cleanup the affinity_hint CPU mask memory and callback */
3878         for (i = 0; i < num_q_vectors; i++) {
3879                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3880                 /* clear the affinity_mask in the IRQ descriptor */
3881                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3882                 /* release the CPU mask memory */
3883                 free_cpumask_var(q_vector->affinity_mask);
3884         }
3885
3886         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3887             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3888                 cancel_work_sync(&adapter->fdir_reinit_task);
3889
3890         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3891                 cancel_work_sync(&adapter->check_overtemp_task);
3892
3893         /* disable transmits in the hardware now that interrupts are off */
3894         for (i = 0; i < adapter->num_tx_queues; i++) {
3895                 j = adapter->tx_ring[i]->reg_idx;
3896                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3897                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3898                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3899         }
3900         /* Disable the Tx DMA engine on 82599 */
3901         if (hw->mac.type == ixgbe_mac_82599EB)
3902                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3903                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3904                                  ~IXGBE_DMATXCTL_TE));
3905
3906         /* power down the optics */
3907         if (hw->phy.multispeed_fiber)
3908                 hw->mac.ops.disable_tx_laser(hw);
3909
3910         /* clear n-tuple filters that are cached */
3911         ethtool_ntuple_flush(netdev);
3912
3913         if (!pci_channel_offline(adapter->pdev))
3914                 ixgbe_reset(adapter);
3915         ixgbe_clean_all_tx_rings(adapter);
3916         ixgbe_clean_all_rx_rings(adapter);
3917
3918 #ifdef CONFIG_IXGBE_DCA
3919         /* since we reset the hardware DCA settings were cleared */
3920         ixgbe_setup_dca(adapter);
3921 #endif
3922 }
3923
3924 /**
3925  * ixgbe_poll - NAPI Rx polling callback
3926  * @napi: structure for representing this polling device
3927  * @budget: how many packets driver is allowed to clean
3928  *
3929  * This function is used for legacy and MSI, NAPI mode
3930  **/
3931 static int ixgbe_poll(struct napi_struct *napi, int budget)
3932 {
3933         struct ixgbe_q_vector *q_vector =
3934                                 container_of(napi, struct ixgbe_q_vector, napi);
3935         struct ixgbe_adapter *adapter = q_vector->adapter;
3936         int tx_clean_complete, work_done = 0;
3937
3938 #ifdef CONFIG_IXGBE_DCA
3939         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3940                 ixgbe_update_dca(q_vector);
3941 #endif
3942
3943         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3944         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3945
3946         if (!tx_clean_complete)
3947                 work_done = budget;
3948
3949         /* If budget not fully consumed, exit the polling mode */
3950         if (work_done < budget) {
3951                 napi_complete(napi);
3952                 if (adapter->rx_itr_setting & 1)
3953                         ixgbe_set_itr(adapter);
3954                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3955                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3956         }
3957         return work_done;
3958 }
3959
3960 /**
3961  * ixgbe_tx_timeout - Respond to a Tx Hang
3962  * @netdev: network interface device structure
3963  **/
3964 static void ixgbe_tx_timeout(struct net_device *netdev)
3965 {
3966         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3967
3968         /* Do the reset outside of interrupt context */
3969         schedule_work(&adapter->reset_task);
3970 }
3971
3972 static void ixgbe_reset_task(struct work_struct *work)
3973 {
3974         struct ixgbe_adapter *adapter;
3975         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3976
3977         /* If we're already down or resetting, just bail */
3978         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3979             test_bit(__IXGBE_RESETTING, &adapter->state))
3980                 return;
3981
3982         adapter->tx_timeout_count++;
3983
3984         ixgbe_dump(adapter);
3985         netdev_err(adapter->netdev, "Reset adapter\n");
3986         ixgbe_reinit_locked(adapter);
3987 }
3988
3989 #ifdef CONFIG_IXGBE_DCB
3990 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3991 {
3992         bool ret = false;
3993         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3994
3995         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3996                 return ret;
3997
3998         f->mask = 0x7 << 3;
3999         adapter->num_rx_queues = f->indices;
4000         adapter->num_tx_queues = f->indices;
4001         ret = true;
4002
4003         return ret;
4004 }
4005 #endif
4006
4007 /**
4008  * ixgbe_set_rss_queues: Allocate queues for RSS
4009  * @adapter: board private structure to initialize
4010  *
4011  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4012  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4013  *
4014  **/
4015 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4016 {
4017         bool ret = false;
4018         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4019
4020         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4021                 f->mask = 0xF;
4022                 adapter->num_rx_queues = f->indices;
4023                 adapter->num_tx_queues = f->indices;
4024                 ret = true;
4025         } else {
4026                 ret = false;
4027         }
4028
4029         return ret;
4030 }
4031
4032 /**
4033  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4034  * @adapter: board private structure to initialize
4035  *
4036  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4037  * to the original CPU that initiated the Tx session.  This runs in addition
4038  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4039  * Rx load across CPUs using RSS.
4040  *
4041  **/
4042 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4043 {
4044         bool ret = false;
4045         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4046
4047         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4048         f_fdir->mask = 0;
4049
4050         /* Flow Director must have RSS enabled */
4051         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4052             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4053              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4054                 adapter->num_tx_queues = f_fdir->indices;
4055                 adapter->num_rx_queues = f_fdir->indices;
4056                 ret = true;
4057         } else {
4058                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4059                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4060         }
4061         return ret;
4062 }
4063
4064 #ifdef IXGBE_FCOE
4065 /**
4066  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4067  * @adapter: board private structure to initialize
4068  *
4069  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4070  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4071  * rx queues out of the max number of rx queues, instead, it is used as the
4072  * index of the first rx queue used by FCoE.
4073  *
4074  **/
4075 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4076 {
4077         bool ret = false;
4078         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4079
4080         f->indices = min((int)num_online_cpus(), f->indices);
4081         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4082                 adapter->num_rx_queues = 1;
4083                 adapter->num_tx_queues = 1;
4084 #ifdef CONFIG_IXGBE_DCB
4085                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4086                         e_info(probe, "FCoE enabled with DCB\n");
4087                         ixgbe_set_dcb_queues(adapter);
4088                 }
4089 #endif
4090                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4091                         e_info(probe, "FCoE enabled with RSS\n");
4092                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4093                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4094                                 ixgbe_set_fdir_queues(adapter);
4095                         else
4096                                 ixgbe_set_rss_queues(adapter);
4097                 }
4098                 /* adding FCoE rx rings to the end */
4099                 f->mask = adapter->num_rx_queues;
4100                 adapter->num_rx_queues += f->indices;
4101                 adapter->num_tx_queues += f->indices;
4102
4103                 ret = true;
4104         }
4105
4106         return ret;
4107 }
4108
4109 #endif /* IXGBE_FCOE */
4110 /**
4111  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4112  * @adapter: board private structure to initialize
4113  *
4114  * IOV doesn't actually use anything, so just NAK the
4115  * request for now and let the other queue routines
4116  * figure out what to do.
4117  */
4118 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4119 {
4120         return false;
4121 }
4122
4123 /*
4124  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4125  * @adapter: board private structure to initialize
4126  *
4127  * This is the top level queue allocation routine.  The order here is very
4128  * important, starting with the "most" number of features turned on at once,
4129  * and ending with the smallest set of features.  This way large combinations
4130  * can be allocated if they're turned on, and smaller combinations are the
4131  * fallthrough conditions.
4132  *
4133  **/
4134 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4135 {
4136         /* Start with base case */
4137         adapter->num_rx_queues = 1;
4138         adapter->num_tx_queues = 1;
4139         adapter->num_rx_pools = adapter->num_rx_queues;
4140         adapter->num_rx_queues_per_pool = 1;
4141
4142         if (ixgbe_set_sriov_queues(adapter))
4143                 goto done;
4144
4145 #ifdef IXGBE_FCOE
4146         if (ixgbe_set_fcoe_queues(adapter))
4147                 goto done;
4148
4149 #endif /* IXGBE_FCOE */
4150 #ifdef CONFIG_IXGBE_DCB
4151         if (ixgbe_set_dcb_queues(adapter))
4152                 goto done;
4153
4154 #endif
4155         if (ixgbe_set_fdir_queues(adapter))
4156                 goto done;
4157
4158         if (ixgbe_set_rss_queues(adapter))
4159                 goto done;
4160
4161         /* fallback to base case */
4162         adapter->num_rx_queues = 1;
4163         adapter->num_tx_queues = 1;
4164
4165 done:
4166         /* Notify the stack of the (possibly) reduced queue counts. */
4167         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4168         return netif_set_real_num_rx_queues(adapter->netdev,
4169                                             adapter->num_rx_queues);
4170 }
4171
4172 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4173                                        int vectors)
4174 {
4175         int err, vector_threshold;
4176
4177         /* We'll want at least 3 (vector_threshold):
4178          * 1) TxQ[0] Cleanup
4179          * 2) RxQ[0] Cleanup
4180          * 3) Other (Link Status Change, etc.)
4181          * 4) TCP Timer (optional)
4182          */
4183         vector_threshold = MIN_MSIX_COUNT;
4184
4185         /* The more we get, the more we will assign to Tx/Rx Cleanup
4186          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4187          * Right now, we simply care about how many we'll get; we'll
4188          * set them up later while requesting irq's.
4189          */
4190         while (vectors >= vector_threshold) {
4191                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4192                                       vectors);
4193                 if (!err) /* Success in acquiring all requested vectors. */
4194                         break;
4195                 else if (err < 0)
4196                         vectors = 0; /* Nasty failure, quit now */
4197                 else /* err == number of vectors we should try again with */
4198                         vectors = err;
4199         }
4200
4201         if (vectors < vector_threshold) {
4202                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4203                  * This just means we'll go with either a single MSI
4204                  * vector or fall back to legacy interrupts.
4205                  */
4206                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4207                              "Unable to allocate MSI-X interrupts\n");
4208                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4209                 kfree(adapter->msix_entries);
4210                 adapter->msix_entries = NULL;
4211         } else {
4212                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4213                 /*
4214                  * Adjust for only the vectors we'll use, which is minimum
4215                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4216                  * vectors we were allocated.
4217                  */
4218                 adapter->num_msix_vectors = min(vectors,
4219                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4220         }
4221 }
4222
4223 /**
4224  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4225  * @adapter: board private structure to initialize
4226  *
4227  * Cache the descriptor ring offsets for RSS to the assigned rings.
4228  *
4229  **/
4230 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4231 {
4232         int i;
4233         bool ret = false;
4234
4235         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4236                 for (i = 0; i < adapter->num_rx_queues; i++)
4237                         adapter->rx_ring[i]->reg_idx = i;
4238                 for (i = 0; i < adapter->num_tx_queues; i++)
4239                         adapter->tx_ring[i]->reg_idx = i;
4240                 ret = true;
4241         } else {
4242                 ret = false;
4243         }
4244
4245         return ret;
4246 }
4247
4248 #ifdef CONFIG_IXGBE_DCB
4249 /**
4250  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4251  * @adapter: board private structure to initialize
4252  *
4253  * Cache the descriptor ring offsets for DCB to the assigned rings.
4254  *
4255  **/
4256 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4257 {
4258         int i;
4259         bool ret = false;
4260         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4261
4262         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4263                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4264                         /* the number of queues is assumed to be symmetric */
4265                         for (i = 0; i < dcb_i; i++) {
4266                                 adapter->rx_ring[i]->reg_idx = i << 3;
4267                                 adapter->tx_ring[i]->reg_idx = i << 2;
4268                         }
4269                         ret = true;
4270                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4271                         if (dcb_i == 8) {
4272                                 /*
4273                                  * Tx TC0 starts at: descriptor queue 0
4274                                  * Tx TC1 starts at: descriptor queue 32
4275                                  * Tx TC2 starts at: descriptor queue 64
4276                                  * Tx TC3 starts at: descriptor queue 80
4277                                  * Tx TC4 starts at: descriptor queue 96
4278                                  * Tx TC5 starts at: descriptor queue 104
4279                                  * Tx TC6 starts at: descriptor queue 112
4280                                  * Tx TC7 starts at: descriptor queue 120
4281                                  *
4282                                  * Rx TC0-TC7 are offset by 16 queues each
4283                                  */
4284                                 for (i = 0; i < 3; i++) {
4285                                         adapter->tx_ring[i]->reg_idx = i << 5;
4286                                         adapter->rx_ring[i]->reg_idx = i << 4;
4287                                 }
4288                                 for ( ; i < 5; i++) {
4289                                         adapter->tx_ring[i]->reg_idx =
4290                                                                  ((i + 2) << 4);
4291                                         adapter->rx_ring[i]->reg_idx = i << 4;
4292                                 }
4293                                 for ( ; i < dcb_i; i++) {
4294                                         adapter->tx_ring[i]->reg_idx =
4295                                                                  ((i + 8) << 3);
4296                                         adapter->rx_ring[i]->reg_idx = i << 4;
4297                                 }
4298
4299                                 ret = true;
4300                         } else if (dcb_i == 4) {
4301                                 /*
4302                                  * Tx TC0 starts at: descriptor queue 0
4303                                  * Tx TC1 starts at: descriptor queue 64
4304                                  * Tx TC2 starts at: descriptor queue 96
4305                                  * Tx TC3 starts at: descriptor queue 112
4306                                  *
4307                                  * Rx TC0-TC3 are offset by 32 queues each
4308                                  */
4309                                 adapter->tx_ring[0]->reg_idx = 0;
4310                                 adapter->tx_ring[1]->reg_idx = 64;
4311                                 adapter->tx_ring[2]->reg_idx = 96;
4312                                 adapter->tx_ring[3]->reg_idx = 112;
4313                                 for (i = 0 ; i < dcb_i; i++)
4314                                         adapter->rx_ring[i]->reg_idx = i << 5;
4315
4316                                 ret = true;
4317                         } else {
4318                                 ret = false;
4319                         }
4320                 } else {
4321                         ret = false;
4322                 }
4323         } else {
4324                 ret = false;
4325         }
4326
4327         return ret;
4328 }
4329 #endif
4330
4331 /**
4332  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4333  * @adapter: board private structure to initialize
4334  *
4335  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4336  *
4337  **/
4338 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4339 {
4340         int i;
4341         bool ret = false;
4342
4343         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4344             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4345              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4346                 for (i = 0; i < adapter->num_rx_queues; i++)
4347                         adapter->rx_ring[i]->reg_idx = i;
4348                 for (i = 0; i < adapter->num_tx_queues; i++)
4349                         adapter->tx_ring[i]->reg_idx = i;
4350                 ret = true;
4351         }
4352
4353         return ret;
4354 }
4355
4356 #ifdef IXGBE_FCOE
4357 /**
4358  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4359  * @adapter: board private structure to initialize
4360  *
4361  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4362  *
4363  */
4364 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4365 {
4366         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4367         bool ret = false;
4368         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4369
4370         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4371 #ifdef CONFIG_IXGBE_DCB
4372                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4373                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4374
4375                         ixgbe_cache_ring_dcb(adapter);
4376                         /* find out queues in TC for FCoE */
4377                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4378                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4379                         /*
4380                          * In 82599, the number of Tx queues for each traffic
4381                          * class for both 8-TC and 4-TC modes are:
4382                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4383                          * 8 TCs:  32  32  16  16   8   8   8   8
4384                          * 4 TCs:  64  64  32  32
4385                          * We have max 8 queues for FCoE, where 8 the is
4386                          * FCoE redirection table size. If TC for FCoE is
4387                          * less than or equal to TC3, we have enough queues
4388                          * to add max of 8 queues for FCoE, so we start FCoE
4389                          * tx descriptor from the next one, i.e., reg_idx + 1.
4390                          * If TC for FCoE is above TC3, implying 8 TC mode,
4391                          * and we need 8 for FCoE, we have to take all queues
4392                          * in that traffic class for FCoE.
4393                          */
4394                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4395                                 fcoe_tx_i--;
4396                 }
4397 #endif /* CONFIG_IXGBE_DCB */
4398                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4399                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4400                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4401                                 ixgbe_cache_ring_fdir(adapter);
4402                         else
4403                                 ixgbe_cache_ring_rss(adapter);
4404
4405                         fcoe_rx_i = f->mask;
4406                         fcoe_tx_i = f->mask;
4407                 }
4408                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4409                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4410                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4411                 }
4412                 ret = true;
4413         }
4414         return ret;
4415 }
4416
4417 #endif /* IXGBE_FCOE */
4418 /**
4419  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4420  * @adapter: board private structure to initialize
4421  *
4422  * SR-IOV doesn't use any descriptor rings but changes the default if
4423  * no other mapping is used.
4424  *
4425  */
4426 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4427 {
4428         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4429         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4430         if (adapter->num_vfs)
4431                 return true;
4432         else
4433                 return false;
4434 }
4435
4436 /**
4437  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4438  * @adapter: board private structure to initialize
4439  *
4440  * Once we know the feature-set enabled for the device, we'll cache
4441  * the register offset the descriptor ring is assigned to.
4442  *
4443  * Note, the order the various feature calls is important.  It must start with
4444  * the "most" features enabled at the same time, then trickle down to the
4445  * least amount of features turned on at once.
4446  **/
4447 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4448 {
4449         /* start with default case */
4450         adapter->rx_ring[0]->reg_idx = 0;
4451         adapter->tx_ring[0]->reg_idx = 0;
4452
4453         if (ixgbe_cache_ring_sriov(adapter))
4454                 return;
4455
4456 #ifdef IXGBE_FCOE
4457         if (ixgbe_cache_ring_fcoe(adapter))
4458                 return;
4459
4460 #endif /* IXGBE_FCOE */
4461 #ifdef CONFIG_IXGBE_DCB
4462         if (ixgbe_cache_ring_dcb(adapter))
4463                 return;
4464
4465 #endif
4466         if (ixgbe_cache_ring_fdir(adapter))
4467                 return;
4468
4469         if (ixgbe_cache_ring_rss(adapter))
4470                 return;
4471 }
4472
4473 /**
4474  * ixgbe_alloc_queues - Allocate memory for all rings
4475  * @adapter: board private structure to initialize
4476  *
4477  * We allocate one ring per queue at run-time since we don't know the
4478  * number of queues at compile-time.  The polling_netdev array is
4479  * intended for Multiqueue, but should work fine with a single queue.
4480  **/
4481 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4482 {
4483         int i;
4484         int rx_count;
4485         int orig_node = adapter->node;
4486
4487         for (i = 0; i < adapter->num_tx_queues; i++) {
4488                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4489                 if (orig_node == -1) {
4490                         int cur_node = next_online_node(adapter->node);
4491                         if (cur_node == MAX_NUMNODES)
4492                                 cur_node = first_online_node;
4493                         adapter->node = cur_node;
4494                 }
4495                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4496                                     adapter->node);
4497                 if (!ring)
4498                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4499                 if (!ring)
4500                         goto err_tx_ring_allocation;
4501                 ring->count = adapter->tx_ring_count;
4502                 ring->queue_index = i;
4503                 ring->dev = &adapter->pdev->dev;
4504                 ring->netdev = adapter->netdev;
4505                 ring->numa_node = adapter->node;
4506
4507                 adapter->tx_ring[i] = ring;
4508         }
4509
4510         /* Restore the adapter's original node */
4511         adapter->node = orig_node;
4512
4513         rx_count = adapter->rx_ring_count;
4514         for (i = 0; i < adapter->num_rx_queues; i++) {
4515                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4516                 if (orig_node == -1) {
4517                         int cur_node = next_online_node(adapter->node);
4518                         if (cur_node == MAX_NUMNODES)
4519                                 cur_node = first_online_node;
4520                         adapter->node = cur_node;
4521                 }
4522                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4523                                     adapter->node);
4524                 if (!ring)
4525                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4526                 if (!ring)
4527                         goto err_rx_ring_allocation;
4528                 ring->count = rx_count;
4529                 ring->queue_index = i;
4530                 ring->dev = &adapter->pdev->dev;
4531                 ring->netdev = adapter->netdev;
4532                 ring->numa_node = adapter->node;
4533
4534                 adapter->rx_ring[i] = ring;
4535         }
4536
4537         /* Restore the adapter's original node */
4538         adapter->node = orig_node;
4539
4540         ixgbe_cache_ring_register(adapter);
4541
4542         return 0;
4543
4544 err_rx_ring_allocation:
4545         for (i = 0; i < adapter->num_tx_queues; i++)
4546                 kfree(adapter->tx_ring[i]);
4547 err_tx_ring_allocation:
4548         return -ENOMEM;
4549 }
4550
4551 /**
4552  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4553  * @adapter: board private structure to initialize
4554  *
4555  * Attempt to configure the interrupts using the best available
4556  * capabilities of the hardware and the kernel.
4557  **/
4558 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4559 {
4560         struct ixgbe_hw *hw = &adapter->hw;
4561         int err = 0;
4562         int vector, v_budget;
4563
4564         /*
4565          * It's easy to be greedy for MSI-X vectors, but it really
4566          * doesn't do us much good if we have a lot more vectors
4567          * than CPU's.  So let's be conservative and only ask for
4568          * (roughly) the same number of vectors as there are CPU's.
4569          */
4570         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4571                        (int)num_online_cpus()) + NON_Q_VECTORS;
4572
4573         /*
4574          * At the same time, hardware can only support a maximum of
4575          * hw.mac->max_msix_vectors vectors.  With features
4576          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4577          * descriptor queues supported by our device.  Thus, we cap it off in
4578          * those rare cases where the cpu count also exceeds our vector limit.
4579          */
4580         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4581
4582         /* A failure in MSI-X entry allocation isn't fatal, but it does
4583          * mean we disable MSI-X capabilities of the adapter. */
4584         adapter->msix_entries = kcalloc(v_budget,
4585                                         sizeof(struct msix_entry), GFP_KERNEL);
4586         if (adapter->msix_entries) {
4587                 for (vector = 0; vector < v_budget; vector++)
4588                         adapter->msix_entries[vector].entry = vector;
4589
4590                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4591
4592                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4593                         goto out;
4594         }
4595
4596         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4597         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4598         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4599         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4600         adapter->atr_sample_rate = 0;
4601         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4602                 ixgbe_disable_sriov(adapter);
4603
4604         err = ixgbe_set_num_queues(adapter);
4605         if (err)
4606                 return err;
4607
4608         err = pci_enable_msi(adapter->pdev);
4609         if (!err) {
4610                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4611         } else {
4612                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4613                              "Unable to allocate MSI interrupt, "
4614                              "falling back to legacy.  Error: %d\n", err);
4615                 /* reset err */
4616                 err = 0;
4617         }
4618
4619 out:
4620         return err;
4621 }
4622
4623 /**
4624  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4625  * @adapter: board private structure to initialize
4626  *
4627  * We allocate one q_vector per queue interrupt.  If allocation fails we
4628  * return -ENOMEM.
4629  **/
4630 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4631 {
4632         int q_idx, num_q_vectors;
4633         struct ixgbe_q_vector *q_vector;
4634         int napi_vectors;
4635         int (*poll)(struct napi_struct *, int);
4636
4637         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4638                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4639                 napi_vectors = adapter->num_rx_queues;
4640                 poll = &ixgbe_clean_rxtx_many;
4641         } else {
4642                 num_q_vectors = 1;
4643                 napi_vectors = 1;
4644                 poll = &ixgbe_poll;
4645         }
4646
4647         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4648                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4649                                         GFP_KERNEL, adapter->node);
4650                 if (!q_vector)
4651                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4652                                            GFP_KERNEL);
4653                 if (!q_vector)
4654                         goto err_out;
4655                 q_vector->adapter = adapter;
4656                 if (q_vector->txr_count && !q_vector->rxr_count)
4657                         q_vector->eitr = adapter->tx_eitr_param;
4658                 else
4659                         q_vector->eitr = adapter->rx_eitr_param;
4660                 q_vector->v_idx = q_idx;
4661                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4662                 adapter->q_vector[q_idx] = q_vector;
4663         }
4664
4665         return 0;
4666
4667 err_out:
4668         while (q_idx) {
4669                 q_idx--;
4670                 q_vector = adapter->q_vector[q_idx];
4671                 netif_napi_del(&q_vector->napi);
4672                 kfree(q_vector);
4673                 adapter->q_vector[q_idx] = NULL;
4674         }
4675         return -ENOMEM;
4676 }
4677
4678 /**
4679  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4680  * @adapter: board private structure to initialize
4681  *
4682  * This function frees the memory allocated to the q_vectors.  In addition if
4683  * NAPI is enabled it will delete any references to the NAPI struct prior
4684  * to freeing the q_vector.
4685  **/
4686 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4687 {
4688         int q_idx, num_q_vectors;
4689
4690         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4691                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4692         else
4693                 num_q_vectors = 1;
4694
4695         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4696                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4697                 adapter->q_vector[q_idx] = NULL;
4698                 netif_napi_del(&q_vector->napi);
4699                 kfree(q_vector);
4700         }
4701 }
4702
4703 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4704 {
4705         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4706                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4707                 pci_disable_msix(adapter->pdev);
4708                 kfree(adapter->msix_entries);
4709                 adapter->msix_entries = NULL;
4710         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4711                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4712                 pci_disable_msi(adapter->pdev);
4713         }
4714 }
4715
4716 /**
4717  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4718  * @adapter: board private structure to initialize
4719  *
4720  * We determine which interrupt scheme to use based on...
4721  * - Kernel support (MSI, MSI-X)
4722  *   - which can be user-defined (via MODULE_PARAM)
4723  * - Hardware queue count (num_*_queues)
4724  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4725  **/
4726 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4727 {
4728         int err;
4729
4730         /* Number of supported queues */
4731         err = ixgbe_set_num_queues(adapter);
4732         if (err)
4733                 return err;
4734
4735         err = ixgbe_set_interrupt_capability(adapter);
4736         if (err) {
4737                 e_dev_err("Unable to setup interrupt capabilities\n");
4738                 goto err_set_interrupt;
4739         }
4740
4741         err = ixgbe_alloc_q_vectors(adapter);
4742         if (err) {
4743                 e_dev_err("Unable to allocate memory for queue vectors\n");
4744                 goto err_alloc_q_vectors;
4745         }
4746
4747         err = ixgbe_alloc_queues(adapter);
4748         if (err) {
4749                 e_dev_err("Unable to allocate memory for queues\n");
4750                 goto err_alloc_queues;
4751         }
4752
4753         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4754                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4755                    adapter->num_rx_queues, adapter->num_tx_queues);
4756
4757         set_bit(__IXGBE_DOWN, &adapter->state);
4758
4759         return 0;
4760
4761 err_alloc_queues:
4762         ixgbe_free_q_vectors(adapter);
4763 err_alloc_q_vectors:
4764         ixgbe_reset_interrupt_capability(adapter);
4765 err_set_interrupt:
4766         return err;
4767 }
4768
4769 static void ring_free_rcu(struct rcu_head *head)
4770 {
4771         kfree(container_of(head, struct ixgbe_ring, rcu));
4772 }
4773
4774 /**
4775  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4776  * @adapter: board private structure to clear interrupt scheme on
4777  *
4778  * We go through and clear interrupt specific resources and reset the structure
4779  * to pre-load conditions
4780  **/
4781 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4782 {
4783         int i;
4784
4785         for (i = 0; i < adapter->num_tx_queues; i++) {
4786                 kfree(adapter->tx_ring[i]);
4787                 adapter->tx_ring[i] = NULL;
4788         }
4789         for (i = 0; i < adapter->num_rx_queues; i++) {
4790                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4791
4792                 /* ixgbe_get_stats64() might access this ring, we must wait
4793                  * a grace period before freeing it.
4794                  */
4795                 call_rcu(&ring->rcu, ring_free_rcu);
4796                 adapter->rx_ring[i] = NULL;
4797         }
4798
4799         ixgbe_free_q_vectors(adapter);
4800         ixgbe_reset_interrupt_capability(adapter);
4801 }
4802
4803 /**
4804  * ixgbe_sfp_timer - worker thread to find a missing module
4805  * @data: pointer to our adapter struct
4806  **/
4807 static void ixgbe_sfp_timer(unsigned long data)
4808 {
4809         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4810
4811         /*
4812          * Do the sfp_timer outside of interrupt context due to the
4813          * delays that sfp+ detection requires
4814          */
4815         schedule_work(&adapter->sfp_task);
4816 }
4817
4818 /**
4819  * ixgbe_sfp_task - worker thread to find a missing module
4820  * @work: pointer to work_struct containing our data
4821  **/
4822 static void ixgbe_sfp_task(struct work_struct *work)
4823 {
4824         struct ixgbe_adapter *adapter = container_of(work,
4825                                                      struct ixgbe_adapter,
4826                                                      sfp_task);
4827         struct ixgbe_hw *hw = &adapter->hw;
4828
4829         if ((hw->phy.type == ixgbe_phy_nl) &&
4830             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4831                 s32 ret = hw->phy.ops.identify_sfp(hw);
4832                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4833                         goto reschedule;
4834                 ret = hw->phy.ops.reset(hw);
4835                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4836                         e_dev_err("failed to initialize because an unsupported "
4837                                   "SFP+ module type was detected.\n");
4838                         e_dev_err("Reload the driver after installing a "
4839                                   "supported module.\n");
4840                         unregister_netdev(adapter->netdev);
4841                 } else {
4842                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4843                 }
4844                 /* don't need this routine any more */
4845                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4846         }
4847         return;
4848 reschedule:
4849         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4850                 mod_timer(&adapter->sfp_timer,
4851                           round_jiffies(jiffies + (2 * HZ)));
4852 }
4853
4854 /**
4855  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4856  * @adapter: board private structure to initialize
4857  *
4858  * ixgbe_sw_init initializes the Adapter private data structure.
4859  * Fields are initialized based on PCI device information and
4860  * OS network device settings (MTU size).
4861  **/
4862 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4863 {
4864         struct ixgbe_hw *hw = &adapter->hw;
4865         struct pci_dev *pdev = adapter->pdev;
4866         struct net_device *dev = adapter->netdev;
4867         unsigned int rss;
4868 #ifdef CONFIG_IXGBE_DCB
4869         int j;
4870         struct tc_configuration *tc;
4871 #endif
4872         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4873
4874         /* PCI config space info */
4875
4876         hw->vendor_id = pdev->vendor;
4877         hw->device_id = pdev->device;
4878         hw->revision_id = pdev->revision;
4879         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4880         hw->subsystem_device_id = pdev->subsystem_device;
4881
4882         /* Set capability flags */
4883         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4884         adapter->ring_feature[RING_F_RSS].indices = rss;
4885         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4886         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4887         if (hw->mac.type == ixgbe_mac_82598EB) {
4888                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4889                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4890                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4891         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4892                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4893                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4894                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4895                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4896                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4897                 if (dev->features & NETIF_F_NTUPLE) {
4898                         /* Flow Director perfect filter enabled */
4899                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4900                         adapter->atr_sample_rate = 0;
4901                         spin_lock_init(&adapter->fdir_perfect_lock);
4902                 } else {
4903                         /* Flow Director hash filters enabled */
4904                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4905                         adapter->atr_sample_rate = 20;
4906                 }
4907                 adapter->ring_feature[RING_F_FDIR].indices =
4908                                                          IXGBE_MAX_FDIR_INDICES;
4909                 adapter->fdir_pballoc = 0;
4910 #ifdef IXGBE_FCOE
4911                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4912                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4913                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4914 #ifdef CONFIG_IXGBE_DCB
4915                 /* Default traffic class to use for FCoE */
4916                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4917                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4918 #endif
4919 #endif /* IXGBE_FCOE */
4920         }
4921
4922 #ifdef CONFIG_IXGBE_DCB
4923         /* Configure DCB traffic classes */
4924         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4925                 tc = &adapter->dcb_cfg.tc_config[j];
4926                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4927                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4928                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4929                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4930                 tc->dcb_pfc = pfc_disabled;
4931         }
4932         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4933         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4934         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4935         adapter->dcb_cfg.pfc_mode_enable = false;
4936         adapter->dcb_cfg.round_robin_enable = false;
4937         adapter->dcb_set_bitmap = 0x00;
4938         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4939                            adapter->ring_feature[RING_F_DCB].indices);
4940
4941 #endif
4942
4943         /* default flow control settings */
4944         hw->fc.requested_mode = ixgbe_fc_full;
4945         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4946 #ifdef CONFIG_DCB
4947         adapter->last_lfc_mode = hw->fc.current_mode;
4948 #endif
4949         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4950         hw->fc.low_water = FC_LOW_WATER(max_frame);
4951         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4952         hw->fc.send_xon = true;
4953         hw->fc.disable_fc_autoneg = false;
4954
4955         /* enable itr by default in dynamic mode */
4956         adapter->rx_itr_setting = 1;
4957         adapter->rx_eitr_param = 20000;
4958         adapter->tx_itr_setting = 1;
4959         adapter->tx_eitr_param = 10000;
4960
4961         /* set defaults for eitr in MegaBytes */
4962         adapter->eitr_low = 10;
4963         adapter->eitr_high = 20;
4964
4965         /* set default ring sizes */
4966         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4967         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4968
4969         /* initialize eeprom parameters */
4970         if (ixgbe_init_eeprom_params_generic(hw)) {
4971                 e_dev_err("EEPROM initialization failed\n");
4972                 return -EIO;
4973         }
4974
4975         /* enable rx csum by default */
4976         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4977
4978         /* get assigned NUMA node */
4979         adapter->node = dev_to_node(&pdev->dev);
4980
4981         set_bit(__IXGBE_DOWN, &adapter->state);
4982
4983         return 0;
4984 }
4985
4986 /**
4987  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4988  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4989  *
4990  * Return 0 on success, negative on failure
4991  **/
4992 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4993 {
4994         struct device *dev = tx_ring->dev;
4995         int size;
4996
4997         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4998         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4999         if (!tx_ring->tx_buffer_info)
5000                 tx_ring->tx_buffer_info = vmalloc(size);
5001         if (!tx_ring->tx_buffer_info)
5002                 goto err;
5003         memset(tx_ring->tx_buffer_info, 0, size);
5004
5005         /* round up to nearest 4K */
5006         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5007         tx_ring->size = ALIGN(tx_ring->size, 4096);
5008
5009         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5010                                            &tx_ring->dma, GFP_KERNEL);
5011         if (!tx_ring->desc)
5012                 goto err;
5013
5014         tx_ring->next_to_use = 0;
5015         tx_ring->next_to_clean = 0;
5016         tx_ring->work_limit = tx_ring->count;
5017         return 0;
5018
5019 err:
5020         vfree(tx_ring->tx_buffer_info);
5021         tx_ring->tx_buffer_info = NULL;
5022         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5023         return -ENOMEM;
5024 }
5025
5026 /**
5027  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5028  * @adapter: board private structure
5029  *
5030  * If this function returns with an error, then it's possible one or
5031  * more of the rings is populated (while the rest are not).  It is the
5032  * callers duty to clean those orphaned rings.
5033  *
5034  * Return 0 on success, negative on failure
5035  **/
5036 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5037 {
5038         int i, err = 0;
5039
5040         for (i = 0; i < adapter->num_tx_queues; i++) {
5041                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5042                 if (!err)
5043                         continue;
5044                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5045                 break;
5046         }
5047
5048         return err;
5049 }
5050
5051 /**
5052  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5053  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5054  *
5055  * Returns 0 on success, negative on failure
5056  **/
5057 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5058 {
5059         struct device *dev = rx_ring->dev;
5060         int size;
5061
5062         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5063         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5064         if (!rx_ring->rx_buffer_info)
5065                 rx_ring->rx_buffer_info = vmalloc(size);
5066         if (!rx_ring->rx_buffer_info)
5067                 goto err;
5068         memset(rx_ring->rx_buffer_info, 0, size);
5069
5070         /* Round up to nearest 4K */
5071         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5072         rx_ring->size = ALIGN(rx_ring->size, 4096);
5073
5074         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5075                                            &rx_ring->dma, GFP_KERNEL);
5076
5077         if (!rx_ring->desc)
5078                 goto err;
5079
5080         rx_ring->next_to_clean = 0;
5081         rx_ring->next_to_use = 0;
5082
5083         return 0;
5084 err:
5085         vfree(rx_ring->rx_buffer_info);
5086         rx_ring->rx_buffer_info = NULL;
5087         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5088         return -ENOMEM;
5089 }
5090
5091 /**
5092  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5093  * @adapter: board private structure
5094  *
5095  * If this function returns with an error, then it's possible one or
5096  * more of the rings is populated (while the rest are not).  It is the
5097  * callers duty to clean those orphaned rings.
5098  *
5099  * Return 0 on success, negative on failure
5100  **/
5101 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5102 {
5103         int i, err = 0;
5104
5105         for (i = 0; i < adapter->num_rx_queues; i++) {
5106                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5107                 if (!err)
5108                         continue;
5109                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5110                 break;
5111         }
5112
5113         return err;
5114 }
5115
5116 /**
5117  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5118  * @tx_ring: Tx descriptor ring for a specific queue
5119  *
5120  * Free all transmit software resources
5121  **/
5122 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5123 {
5124         ixgbe_clean_tx_ring(tx_ring);
5125
5126         vfree(tx_ring->tx_buffer_info);
5127         tx_ring->tx_buffer_info = NULL;
5128
5129         /* if not set, then don't free */
5130         if (!tx_ring->desc)
5131                 return;
5132
5133         dma_free_coherent(tx_ring->dev, tx_ring->size,
5134                           tx_ring->desc, tx_ring->dma);
5135
5136         tx_ring->desc = NULL;
5137 }
5138
5139 /**
5140  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5141  * @adapter: board private structure
5142  *
5143  * Free all transmit software resources
5144  **/
5145 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5146 {
5147         int i;
5148
5149         for (i = 0; i < adapter->num_tx_queues; i++)
5150                 if (adapter->tx_ring[i]->desc)
5151                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5152 }
5153
5154 /**
5155  * ixgbe_free_rx_resources - Free Rx Resources
5156  * @rx_ring: ring to clean the resources from
5157  *
5158  * Free all receive software resources
5159  **/
5160 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5161 {
5162         ixgbe_clean_rx_ring(rx_ring);
5163
5164         vfree(rx_ring->rx_buffer_info);
5165         rx_ring->rx_buffer_info = NULL;
5166
5167         /* if not set, then don't free */
5168         if (!rx_ring->desc)
5169                 return;
5170
5171         dma_free_coherent(rx_ring->dev, rx_ring->size,
5172                           rx_ring->desc, rx_ring->dma);
5173
5174         rx_ring->desc = NULL;
5175 }
5176
5177 /**
5178  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5179  * @adapter: board private structure
5180  *
5181  * Free all receive software resources
5182  **/
5183 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5184 {
5185         int i;
5186
5187         for (i = 0; i < adapter->num_rx_queues; i++)
5188                 if (adapter->rx_ring[i]->desc)
5189                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5190 }
5191
5192 /**
5193  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5194  * @netdev: network interface device structure
5195  * @new_mtu: new value for maximum frame size
5196  *
5197  * Returns 0 on success, negative on failure
5198  **/
5199 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5200 {
5201         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5202         struct ixgbe_hw *hw = &adapter->hw;
5203         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5204
5205         /* MTU < 68 is an error and causes problems on some kernels */
5206         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5207                 return -EINVAL;
5208
5209         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5210         /* must set new MTU before calling down or up */
5211         netdev->mtu = new_mtu;
5212
5213         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5214         hw->fc.low_water = FC_LOW_WATER(max_frame);
5215
5216         if (netif_running(netdev))
5217                 ixgbe_reinit_locked(adapter);
5218
5219         return 0;
5220 }
5221
5222 /**
5223  * ixgbe_open - Called when a network interface is made active
5224  * @netdev: network interface device structure
5225  *
5226  * Returns 0 on success, negative value on failure
5227  *
5228  * The open entry point is called when a network interface is made
5229  * active by the system (IFF_UP).  At this point all resources needed
5230  * for transmit and receive operations are allocated, the interrupt
5231  * handler is registered with the OS, the watchdog timer is started,
5232  * and the stack is notified that the interface is ready.
5233  **/
5234 static int ixgbe_open(struct net_device *netdev)
5235 {
5236         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5237         int err;
5238
5239         /* disallow open during test */
5240         if (test_bit(__IXGBE_TESTING, &adapter->state))
5241                 return -EBUSY;
5242
5243         netif_carrier_off(netdev);
5244
5245         /* allocate transmit descriptors */
5246         err = ixgbe_setup_all_tx_resources(adapter);
5247         if (err)
5248                 goto err_setup_tx;
5249
5250         /* allocate receive descriptors */
5251         err = ixgbe_setup_all_rx_resources(adapter);
5252         if (err)
5253                 goto err_setup_rx;
5254
5255         ixgbe_configure(adapter);
5256
5257         err = ixgbe_request_irq(adapter);
5258         if (err)
5259                 goto err_req_irq;
5260
5261         err = ixgbe_up_complete(adapter);
5262         if (err)
5263                 goto err_up;
5264
5265         netif_tx_start_all_queues(netdev);
5266
5267         return 0;
5268
5269 err_up:
5270         ixgbe_release_hw_control(adapter);
5271         ixgbe_free_irq(adapter);
5272 err_req_irq:
5273 err_setup_rx:
5274         ixgbe_free_all_rx_resources(adapter);
5275 err_setup_tx:
5276         ixgbe_free_all_tx_resources(adapter);
5277         ixgbe_reset(adapter);
5278
5279         return err;
5280 }
5281
5282 /**
5283  * ixgbe_close - Disables a network interface
5284  * @netdev: network interface device structure
5285  *
5286  * Returns 0, this is not allowed to fail
5287  *
5288  * The close entry point is called when an interface is de-activated
5289  * by the OS.  The hardware is still under the drivers control, but
5290  * needs to be disabled.  A global MAC reset is issued to stop the
5291  * hardware, and all transmit and receive resources are freed.
5292  **/
5293 static int ixgbe_close(struct net_device *netdev)
5294 {
5295         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5296
5297         ixgbe_down(adapter);
5298         ixgbe_free_irq(adapter);
5299
5300         ixgbe_free_all_tx_resources(adapter);
5301         ixgbe_free_all_rx_resources(adapter);
5302
5303         ixgbe_release_hw_control(adapter);
5304
5305         return 0;
5306 }
5307
5308 #ifdef CONFIG_PM
5309 static int ixgbe_resume(struct pci_dev *pdev)
5310 {
5311         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5312         struct net_device *netdev = adapter->netdev;
5313         u32 err;
5314
5315         pci_set_power_state(pdev, PCI_D0);
5316         pci_restore_state(pdev);
5317         /*
5318          * pci_restore_state clears dev->state_saved so call
5319          * pci_save_state to restore it.
5320          */
5321         pci_save_state(pdev);
5322
5323         err = pci_enable_device_mem(pdev);
5324         if (err) {
5325                 e_dev_err("Cannot enable PCI device from suspend\n");
5326                 return err;
5327         }
5328         pci_set_master(pdev);
5329
5330         pci_wake_from_d3(pdev, false);
5331
5332         err = ixgbe_init_interrupt_scheme(adapter);
5333         if (err) {
5334                 e_dev_err("Cannot initialize interrupts for device\n");
5335                 return err;
5336         }
5337
5338         ixgbe_reset(adapter);
5339
5340         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5341
5342         if (netif_running(netdev)) {
5343                 err = ixgbe_open(netdev);
5344                 if (err)
5345                         return err;
5346         }
5347
5348         netif_device_attach(netdev);
5349
5350         return 0;
5351 }
5352 #endif /* CONFIG_PM */
5353
5354 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5355 {
5356         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5357         struct net_device *netdev = adapter->netdev;
5358         struct ixgbe_hw *hw = &adapter->hw;
5359         u32 ctrl, fctrl;
5360         u32 wufc = adapter->wol;
5361 #ifdef CONFIG_PM
5362         int retval = 0;
5363 #endif
5364
5365         netif_device_detach(netdev);
5366
5367         if (netif_running(netdev)) {
5368                 ixgbe_down(adapter);
5369                 ixgbe_free_irq(adapter);
5370                 ixgbe_free_all_tx_resources(adapter);
5371                 ixgbe_free_all_rx_resources(adapter);
5372         }
5373
5374         ixgbe_clear_interrupt_scheme(adapter);
5375
5376 #ifdef CONFIG_PM
5377         retval = pci_save_state(pdev);
5378         if (retval)
5379                 return retval;
5380
5381 #endif
5382         if (wufc) {
5383                 ixgbe_set_rx_mode(netdev);
5384
5385                 /* turn on all-multi mode if wake on multicast is enabled */
5386                 if (wufc & IXGBE_WUFC_MC) {
5387                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5388                         fctrl |= IXGBE_FCTRL_MPE;
5389                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5390                 }
5391
5392                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5393                 ctrl |= IXGBE_CTRL_GIO_DIS;
5394                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5395
5396                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5397         } else {
5398                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5399                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5400         }
5401
5402         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5403                 pci_wake_from_d3(pdev, true);
5404         else
5405                 pci_wake_from_d3(pdev, false);
5406
5407         *enable_wake = !!wufc;
5408
5409         ixgbe_release_hw_control(adapter);
5410
5411         pci_disable_device(pdev);
5412
5413         return 0;
5414 }
5415
5416 #ifdef CONFIG_PM
5417 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5418 {
5419         int retval;
5420         bool wake;
5421
5422         retval = __ixgbe_shutdown(pdev, &wake);
5423         if (retval)
5424                 return retval;
5425
5426         if (wake) {
5427                 pci_prepare_to_sleep(pdev);
5428         } else {
5429                 pci_wake_from_d3(pdev, false);
5430                 pci_set_power_state(pdev, PCI_D3hot);
5431         }
5432
5433         return 0;
5434 }
5435 #endif /* CONFIG_PM */
5436
5437 static void ixgbe_shutdown(struct pci_dev *pdev)
5438 {
5439         bool wake;
5440
5441         __ixgbe_shutdown(pdev, &wake);
5442
5443         if (system_state == SYSTEM_POWER_OFF) {
5444                 pci_wake_from_d3(pdev, wake);
5445                 pci_set_power_state(pdev, PCI_D3hot);
5446         }
5447 }
5448
5449 /**
5450  * ixgbe_update_stats - Update the board statistics counters.
5451  * @adapter: board private structure
5452  **/
5453 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5454 {
5455         struct net_device *netdev = adapter->netdev;
5456         struct ixgbe_hw *hw = &adapter->hw;
5457         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5458         u64 total_mpc = 0;
5459         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5460         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5461         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5462         u64 bytes = 0, packets = 0;
5463
5464         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5465             test_bit(__IXGBE_RESETTING, &adapter->state))
5466                 return;
5467
5468         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5469                 u64 rsc_count = 0;
5470                 u64 rsc_flush = 0;
5471                 for (i = 0; i < 16; i++)
5472                         adapter->hw_rx_no_dma_resources +=
5473                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5474                 for (i = 0; i < adapter->num_rx_queues; i++) {
5475                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5476                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5477                 }
5478                 adapter->rsc_total_count = rsc_count;
5479                 adapter->rsc_total_flush = rsc_flush;
5480         }
5481
5482         for (i = 0; i < adapter->num_rx_queues; i++) {
5483                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5484                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5485                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5486                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5487                 bytes += rx_ring->stats.bytes;
5488                 packets += rx_ring->stats.packets;
5489         }
5490         adapter->non_eop_descs = non_eop_descs;
5491         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5492         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5493         netdev->stats.rx_bytes = bytes;
5494         netdev->stats.rx_packets = packets;
5495
5496         bytes = 0;
5497         packets = 0;
5498         /* gather some stats to the adapter struct that are per queue */
5499         for (i = 0; i < adapter->num_tx_queues; i++) {
5500                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5501                 restart_queue += tx_ring->tx_stats.restart_queue;
5502                 tx_busy += tx_ring->tx_stats.tx_busy;
5503                 bytes += tx_ring->stats.bytes;
5504                 packets += tx_ring->stats.packets;
5505         }
5506         adapter->restart_queue = restart_queue;
5507         adapter->tx_busy = tx_busy;
5508         netdev->stats.tx_bytes = bytes;
5509         netdev->stats.tx_packets = packets;
5510
5511         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5512         for (i = 0; i < 8; i++) {
5513                 /* for packet buffers not used, the register should read 0 */
5514                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5515                 missed_rx += mpc;
5516                 hwstats->mpc[i] += mpc;
5517                 total_mpc += hwstats->mpc[i];
5518                 if (hw->mac.type == ixgbe_mac_82598EB)
5519                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5520                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5521                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5522                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5523                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5524                 if (hw->mac.type == ixgbe_mac_82599EB) {
5525                         hwstats->pxonrxc[i] +=
5526                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5527                         hwstats->pxoffrxc[i] +=
5528                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5529                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5530                 } else {
5531                         hwstats->pxonrxc[i] +=
5532                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5533                         hwstats->pxoffrxc[i] +=
5534                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5535                 }
5536                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5537                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5538         }
5539         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5540         /* work around hardware counting issue */
5541         hwstats->gprc -= missed_rx;
5542
5543         /* 82598 hardware only has a 32 bit counter in the high register */
5544         if (hw->mac.type == ixgbe_mac_82599EB) {
5545                 u64 tmp;
5546                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5547                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5548                                                 /* 4 high bits of GORC */
5549                 hwstats->gorc += (tmp << 32);
5550                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5551                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5552                                                 /* 4 high bits of GOTC */
5553                 hwstats->gotc += (tmp << 32);
5554                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5555                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5556                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5557                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5558                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5559                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5560 #ifdef IXGBE_FCOE
5561                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5562                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5563                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5564                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5565                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5566                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5567 #endif /* IXGBE_FCOE */
5568         } else {
5569                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5570                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5571                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5572                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5573                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5574         }
5575         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5576         hwstats->bprc += bprc;
5577         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5578         if (hw->mac.type == ixgbe_mac_82598EB)
5579                 hwstats->mprc -= bprc;
5580         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5581         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5582         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5583         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5584         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5585         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5586         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5587         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5588         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5589         hwstats->lxontxc += lxon;
5590         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5591         hwstats->lxofftxc += lxoff;
5592         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5593         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5594         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5595         /*
5596          * 82598 errata - tx of flow control packets is included in tx counters
5597          */
5598         xon_off_tot = lxon + lxoff;
5599         hwstats->gptc -= xon_off_tot;
5600         hwstats->mptc -= xon_off_tot;
5601         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5602         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5603         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5604         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5605         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5606         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5607         hwstats->ptc64 -= xon_off_tot;
5608         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5609         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5610         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5611         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5612         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5613         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5614
5615         /* Fill out the OS statistics structure */
5616         netdev->stats.multicast = hwstats->mprc;
5617
5618         /* Rx Errors */
5619         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5620         netdev->stats.rx_dropped = 0;
5621         netdev->stats.rx_length_errors = hwstats->rlec;
5622         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5623         netdev->stats.rx_missed_errors = total_mpc;
5624 }
5625
5626 /**
5627  * ixgbe_watchdog - Timer Call-back
5628  * @data: pointer to adapter cast into an unsigned long
5629  **/
5630 static void ixgbe_watchdog(unsigned long data)
5631 {
5632         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5633         struct ixgbe_hw *hw = &adapter->hw;
5634         u64 eics = 0;
5635         int i;
5636
5637         /*
5638          *  Do the watchdog outside of interrupt context due to the lovely
5639          * delays that some of the newer hardware requires
5640          */
5641
5642         if (test_bit(__IXGBE_DOWN, &adapter->state))
5643                 goto watchdog_short_circuit;
5644
5645         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5646                 /*
5647                  * for legacy and MSI interrupts don't set any bits
5648                  * that are enabled for EIAM, because this operation
5649                  * would set *both* EIMS and EICS for any bit in EIAM
5650                  */
5651                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5652                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5653                 goto watchdog_reschedule;
5654         }
5655
5656         /* get one bit for every active tx/rx interrupt vector */
5657         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5658                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5659                 if (qv->rxr_count || qv->txr_count)
5660                         eics |= ((u64)1 << i);
5661         }
5662
5663         /* Cause software interrupt to ensure rx rings are cleaned */
5664         ixgbe_irq_rearm_queues(adapter, eics);
5665
5666 watchdog_reschedule:
5667         /* Reset the timer */
5668         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5669
5670 watchdog_short_circuit:
5671         schedule_work(&adapter->watchdog_task);
5672 }
5673
5674 /**
5675  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5676  * @work: pointer to work_struct containing our data
5677  **/
5678 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5679 {
5680         struct ixgbe_adapter *adapter = container_of(work,
5681                                                      struct ixgbe_adapter,
5682                                                      multispeed_fiber_task);
5683         struct ixgbe_hw *hw = &adapter->hw;
5684         u32 autoneg;
5685         bool negotiation;
5686
5687         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5688         autoneg = hw->phy.autoneg_advertised;
5689         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5690                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5691         hw->mac.autotry_restart = false;
5692         if (hw->mac.ops.setup_link)
5693                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5694         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5695         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5696 }
5697
5698 /**
5699  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5700  * @work: pointer to work_struct containing our data
5701  **/
5702 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5703 {
5704         struct ixgbe_adapter *adapter = container_of(work,
5705                                                      struct ixgbe_adapter,
5706                                                      sfp_config_module_task);
5707         struct ixgbe_hw *hw = &adapter->hw;
5708         u32 err;
5709
5710         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5711
5712         /* Time for electrical oscillations to settle down */
5713         msleep(100);
5714         err = hw->phy.ops.identify_sfp(hw);
5715
5716         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5717                 e_dev_err("failed to initialize because an unsupported SFP+ "
5718                           "module type was detected.\n");
5719                 e_dev_err("Reload the driver after installing a supported "
5720                           "module.\n");
5721                 unregister_netdev(adapter->netdev);
5722                 return;
5723         }
5724         hw->mac.ops.setup_sfp(hw);
5725
5726         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5727                 /* This will also work for DA Twinax connections */
5728                 schedule_work(&adapter->multispeed_fiber_task);
5729         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5730 }
5731
5732 /**
5733  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5734  * @work: pointer to work_struct containing our data
5735  **/
5736 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5737 {
5738         struct ixgbe_adapter *adapter = container_of(work,
5739                                                      struct ixgbe_adapter,
5740                                                      fdir_reinit_task);
5741         struct ixgbe_hw *hw = &adapter->hw;
5742         int i;
5743
5744         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5745                 for (i = 0; i < adapter->num_tx_queues; i++)
5746                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5747                                 &(adapter->tx_ring[i]->state));
5748         } else {
5749                 e_err(probe, "failed to finish FDIR re-initialization, "
5750                       "ignored adding FDIR ATR filters\n");
5751         }
5752         /* Done FDIR Re-initialization, enable transmits */
5753         netif_tx_start_all_queues(adapter->netdev);
5754 }
5755
5756 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5757
5758 /**
5759  * ixgbe_watchdog_task - worker thread to bring link up
5760  * @work: pointer to work_struct containing our data
5761  **/
5762 static void ixgbe_watchdog_task(struct work_struct *work)
5763 {
5764         struct ixgbe_adapter *adapter = container_of(work,
5765                                                      struct ixgbe_adapter,
5766                                                      watchdog_task);
5767         struct net_device *netdev = adapter->netdev;
5768         struct ixgbe_hw *hw = &adapter->hw;
5769         u32 link_speed;
5770         bool link_up;
5771         int i;
5772         struct ixgbe_ring *tx_ring;
5773         int some_tx_pending = 0;
5774
5775         mutex_lock(&ixgbe_watchdog_lock);
5776
5777         link_up = adapter->link_up;
5778         link_speed = adapter->link_speed;
5779
5780         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5781                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5782                 if (link_up) {
5783 #ifdef CONFIG_DCB
5784                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5785                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5786                                         hw->mac.ops.fc_enable(hw, i);
5787                         } else {
5788                                 hw->mac.ops.fc_enable(hw, 0);
5789                         }
5790 #else
5791                         hw->mac.ops.fc_enable(hw, 0);
5792 #endif
5793                 }
5794
5795                 if (link_up ||
5796                     time_after(jiffies, (adapter->link_check_timeout +
5797                                          IXGBE_TRY_LINK_TIMEOUT))) {
5798                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5799                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5800                 }
5801                 adapter->link_up = link_up;
5802                 adapter->link_speed = link_speed;
5803         }
5804
5805         if (link_up) {
5806                 if (!netif_carrier_ok(netdev)) {
5807                         bool flow_rx, flow_tx;
5808
5809                         if (hw->mac.type == ixgbe_mac_82599EB) {
5810                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5811                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5812                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5813                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5814                         } else {
5815                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5816                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5817                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5818                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5819                         }
5820
5821                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5822                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5823                                "10 Gbps" :
5824                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5825                                "1 Gbps" : "unknown speed")),
5826                                ((flow_rx && flow_tx) ? "RX/TX" :
5827                                (flow_rx ? "RX" :
5828                                (flow_tx ? "TX" : "None"))));
5829
5830                         netif_carrier_on(netdev);
5831                 } else {
5832                         /* Force detection of hung controller */
5833                         for (i = 0; i < adapter->num_tx_queues; i++) {
5834                                 tx_ring = adapter->tx_ring[i];
5835                                 set_check_for_tx_hang(tx_ring);
5836                         }
5837                 }
5838         } else {
5839                 adapter->link_up = false;
5840                 adapter->link_speed = 0;
5841                 if (netif_carrier_ok(netdev)) {
5842                         e_info(drv, "NIC Link is Down\n");
5843                         netif_carrier_off(netdev);
5844                 }
5845         }
5846
5847         if (!netif_carrier_ok(netdev)) {
5848                 for (i = 0; i < adapter->num_tx_queues; i++) {
5849                         tx_ring = adapter->tx_ring[i];
5850                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5851                                 some_tx_pending = 1;
5852                                 break;
5853                         }
5854                 }
5855
5856                 if (some_tx_pending) {
5857                         /* We've lost link, so the controller stops DMA,
5858                          * but we've got queued Tx work that's never going
5859                          * to get done, so reset controller to flush Tx.
5860                          * (Do the reset outside of interrupt context).
5861                          */
5862                          schedule_work(&adapter->reset_task);
5863                 }
5864         }
5865
5866         ixgbe_update_stats(adapter);
5867         mutex_unlock(&ixgbe_watchdog_lock);
5868 }
5869
5870 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5871                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5872                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5873 {
5874         struct ixgbe_adv_tx_context_desc *context_desc;
5875         unsigned int i;
5876         int err;
5877         struct ixgbe_tx_buffer *tx_buffer_info;
5878         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5879         u32 mss_l4len_idx, l4len;
5880
5881         if (skb_is_gso(skb)) {
5882                 if (skb_header_cloned(skb)) {
5883                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5884                         if (err)
5885                                 return err;
5886                 }
5887                 l4len = tcp_hdrlen(skb);
5888                 *hdr_len += l4len;
5889
5890                 if (protocol == htons(ETH_P_IP)) {
5891                         struct iphdr *iph = ip_hdr(skb);
5892                         iph->tot_len = 0;
5893                         iph->check = 0;
5894                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5895                                                                  iph->daddr, 0,
5896                                                                  IPPROTO_TCP,
5897                                                                  0);
5898                 } else if (skb_is_gso_v6(skb)) {
5899                         ipv6_hdr(skb)->payload_len = 0;
5900                         tcp_hdr(skb)->check =
5901                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5902                                              &ipv6_hdr(skb)->daddr,
5903                                              0, IPPROTO_TCP, 0);
5904                 }
5905
5906                 i = tx_ring->next_to_use;
5907
5908                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5909                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5910
5911                 /* VLAN MACLEN IPLEN */
5912                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5913                         vlan_macip_lens |=
5914                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5915                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5916                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5917                 *hdr_len += skb_network_offset(skb);
5918                 vlan_macip_lens |=
5919                     (skb_transport_header(skb) - skb_network_header(skb));
5920                 *hdr_len +=
5921                     (skb_transport_header(skb) - skb_network_header(skb));
5922                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5923                 context_desc->seqnum_seed = 0;
5924
5925                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5926                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5927                                    IXGBE_ADVTXD_DTYP_CTXT);
5928
5929                 if (protocol == htons(ETH_P_IP))
5930                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5931                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5932                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5933
5934                 /* MSS L4LEN IDX */
5935                 mss_l4len_idx =
5936                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5937                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5938                 /* use index 1 for TSO */
5939                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5940                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5941
5942                 tx_buffer_info->time_stamp = jiffies;
5943                 tx_buffer_info->next_to_watch = i;
5944
5945                 i++;
5946                 if (i == tx_ring->count)
5947                         i = 0;
5948                 tx_ring->next_to_use = i;
5949
5950                 return true;
5951         }
5952         return false;
5953 }
5954
5955 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5956                       __be16 protocol)
5957 {
5958         u32 rtn = 0;
5959
5960         switch (protocol) {
5961         case cpu_to_be16(ETH_P_IP):
5962                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5963                 switch (ip_hdr(skb)->protocol) {
5964                 case IPPROTO_TCP:
5965                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5966                         break;
5967                 case IPPROTO_SCTP:
5968                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5969                         break;
5970                 }
5971                 break;
5972         case cpu_to_be16(ETH_P_IPV6):
5973                 /* XXX what about other V6 headers?? */
5974                 switch (ipv6_hdr(skb)->nexthdr) {
5975                 case IPPROTO_TCP:
5976                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5977                         break;
5978                 case IPPROTO_SCTP:
5979                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5980                         break;
5981                 }
5982                 break;
5983         default:
5984                 if (unlikely(net_ratelimit()))
5985                         e_warn(probe, "partial checksum but proto=%x!\n",
5986                                protocol);
5987                 break;
5988         }
5989
5990         return rtn;
5991 }
5992
5993 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5994                           struct ixgbe_ring *tx_ring,
5995                           struct sk_buff *skb, u32 tx_flags,
5996                           __be16 protocol)
5997 {
5998         struct ixgbe_adv_tx_context_desc *context_desc;
5999         unsigned int i;
6000         struct ixgbe_tx_buffer *tx_buffer_info;
6001         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6002
6003         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6004             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6005                 i = tx_ring->next_to_use;
6006                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6007                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6008
6009                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6010                         vlan_macip_lens |=
6011                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6012                 vlan_macip_lens |= (skb_network_offset(skb) <<
6013                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6014                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6015                         vlan_macip_lens |= (skb_transport_header(skb) -
6016                                             skb_network_header(skb));
6017
6018                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6019                 context_desc->seqnum_seed = 0;
6020
6021                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6022                                     IXGBE_ADVTXD_DTYP_CTXT);
6023
6024                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6025                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6026
6027                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6028                 /* use index zero for tx checksum offload */
6029                 context_desc->mss_l4len_idx = 0;
6030
6031                 tx_buffer_info->time_stamp = jiffies;
6032                 tx_buffer_info->next_to_watch = i;
6033
6034                 i++;
6035                 if (i == tx_ring->count)
6036                         i = 0;
6037                 tx_ring->next_to_use = i;
6038
6039                 return true;
6040         }
6041
6042         return false;
6043 }
6044
6045 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6046                         struct ixgbe_ring *tx_ring,
6047                         struct sk_buff *skb, u32 tx_flags,
6048                         unsigned int first, const u8 hdr_len)
6049 {
6050         struct device *dev = tx_ring->dev;
6051         struct ixgbe_tx_buffer *tx_buffer_info;
6052         unsigned int len;
6053         unsigned int total = skb->len;
6054         unsigned int offset = 0, size, count = 0, i;
6055         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6056         unsigned int f;
6057         unsigned int bytecount = skb->len;
6058         u16 gso_segs = 1;
6059
6060         i = tx_ring->next_to_use;
6061
6062         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6063                 /* excluding fcoe_crc_eof for FCoE */
6064                 total -= sizeof(struct fcoe_crc_eof);
6065
6066         len = min(skb_headlen(skb), total);
6067         while (len) {
6068                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6069                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6070
6071                 tx_buffer_info->length = size;
6072                 tx_buffer_info->mapped_as_page = false;
6073                 tx_buffer_info->dma = dma_map_single(dev,
6074                                                      skb->data + offset,
6075                                                      size, DMA_TO_DEVICE);
6076                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6077                         goto dma_error;
6078                 tx_buffer_info->time_stamp = jiffies;
6079                 tx_buffer_info->next_to_watch = i;
6080
6081                 len -= size;
6082                 total -= size;
6083                 offset += size;
6084                 count++;
6085
6086                 if (len) {
6087                         i++;
6088                         if (i == tx_ring->count)
6089                                 i = 0;
6090                 }
6091         }
6092
6093         for (f = 0; f < nr_frags; f++) {
6094                 struct skb_frag_struct *frag;
6095
6096                 frag = &skb_shinfo(skb)->frags[f];
6097                 len = min((unsigned int)frag->size, total);
6098                 offset = frag->page_offset;
6099
6100                 while (len) {
6101                         i++;
6102                         if (i == tx_ring->count)
6103                                 i = 0;
6104
6105                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6106                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6107
6108                         tx_buffer_info->length = size;
6109                         tx_buffer_info->dma = dma_map_page(dev,
6110                                                            frag->page,
6111                                                            offset, size,
6112                                                            DMA_TO_DEVICE);
6113                         tx_buffer_info->mapped_as_page = true;
6114                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6115                                 goto dma_error;
6116                         tx_buffer_info->time_stamp = jiffies;
6117                         tx_buffer_info->next_to_watch = i;
6118
6119                         len -= size;
6120                         total -= size;
6121                         offset += size;
6122                         count++;
6123                 }
6124                 if (total == 0)
6125                         break;
6126         }
6127
6128         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6129                 gso_segs = skb_shinfo(skb)->gso_segs;
6130 #ifdef IXGBE_FCOE
6131         /* adjust for FCoE Sequence Offload */
6132         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6133                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6134                                         skb_shinfo(skb)->gso_size);
6135 #endif /* IXGBE_FCOE */
6136         bytecount += (gso_segs - 1) * hdr_len;
6137
6138         /* multiply data chunks by size of headers */
6139         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6140         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6141         tx_ring->tx_buffer_info[i].skb = skb;
6142         tx_ring->tx_buffer_info[first].next_to_watch = i;
6143
6144         return count;
6145
6146 dma_error:
6147         e_dev_err("TX DMA map failed\n");
6148
6149         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6150         tx_buffer_info->dma = 0;
6151         tx_buffer_info->time_stamp = 0;
6152         tx_buffer_info->next_to_watch = 0;
6153         if (count)
6154                 count--;
6155
6156         /* clear timestamp and dma mappings for remaining portion of packet */
6157         while (count--) {
6158                 if (i == 0)
6159                         i += tx_ring->count;
6160                 i--;
6161                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6162                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6163         }
6164
6165         return 0;
6166 }
6167
6168 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6169                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6170 {
6171         union ixgbe_adv_tx_desc *tx_desc = NULL;
6172         struct ixgbe_tx_buffer *tx_buffer_info;
6173         u32 olinfo_status = 0, cmd_type_len = 0;
6174         unsigned int i;
6175         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6176
6177         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6178
6179         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6180
6181         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6182                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6183
6184         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6185                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6186
6187                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6188                                  IXGBE_ADVTXD_POPTS_SHIFT;
6189
6190                 /* use index 1 context for tso */
6191                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6192                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6193                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6194                                          IXGBE_ADVTXD_POPTS_SHIFT;
6195
6196         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6197                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6198                                  IXGBE_ADVTXD_POPTS_SHIFT;
6199
6200         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6201                 olinfo_status |= IXGBE_ADVTXD_CC;
6202                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6203                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6204                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6205         }
6206
6207         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6208
6209         i = tx_ring->next_to_use;
6210         while (count--) {
6211                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6212                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6213                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6214                 tx_desc->read.cmd_type_len =
6215                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6216                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6217                 i++;
6218                 if (i == tx_ring->count)
6219                         i = 0;
6220         }
6221
6222         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6223
6224         /*
6225          * Force memory writes to complete before letting h/w
6226          * know there are new descriptors to fetch.  (Only
6227          * applicable for weak-ordered memory model archs,
6228          * such as IA-64).
6229          */
6230         wmb();
6231
6232         tx_ring->next_to_use = i;
6233         writel(i, tx_ring->tail);
6234 }
6235
6236 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6237                       u8 queue, u32 tx_flags, __be16 protocol)
6238 {
6239         struct ixgbe_atr_input atr_input;
6240         struct iphdr *iph = ip_hdr(skb);
6241         struct ethhdr *eth = (struct ethhdr *)skb->data;
6242         struct tcphdr *th;
6243         u16 vlan_id;
6244
6245         /* Right now, we support IPv4 w/ TCP only */
6246         if (protocol != htons(ETH_P_IP) ||
6247             iph->protocol != IPPROTO_TCP)
6248                 return;
6249
6250         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6251
6252         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6253                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6254
6255         th = tcp_hdr(skb);
6256
6257         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6258         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6259         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6260         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6261         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6262         /* src and dst are inverted, think how the receiver sees them */
6263         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6264         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6265
6266         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6267         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6268 }
6269
6270 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6271 {
6272         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6273         /* Herbert's original patch had:
6274          *  smp_mb__after_netif_stop_queue();
6275          * but since that doesn't exist yet, just open code it. */
6276         smp_mb();
6277
6278         /* We need to check again in a case another CPU has just
6279          * made room available. */
6280         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6281                 return -EBUSY;
6282
6283         /* A reprieve! - use start_queue because it doesn't call schedule */
6284         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6285         ++tx_ring->tx_stats.restart_queue;
6286         return 0;
6287 }
6288
6289 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6290 {
6291         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6292                 return 0;
6293         return __ixgbe_maybe_stop_tx(tx_ring, size);
6294 }
6295
6296 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6297 {
6298         struct ixgbe_adapter *adapter = netdev_priv(dev);
6299         int txq = smp_processor_id();
6300 #ifdef IXGBE_FCOE
6301         __be16 protocol;
6302
6303         protocol = vlan_get_protocol(skb);
6304
6305         if ((protocol == htons(ETH_P_FCOE)) ||
6306             (protocol == htons(ETH_P_FIP))) {
6307                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6308                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6309                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6310                         return txq;
6311 #ifdef CONFIG_IXGBE_DCB
6312                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6313                         txq = adapter->fcoe.up;
6314                         return txq;
6315 #endif
6316                 }
6317         }
6318 #endif
6319
6320         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6321                 while (unlikely(txq >= dev->real_num_tx_queues))
6322                         txq -= dev->real_num_tx_queues;
6323                 return txq;
6324         }
6325
6326         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6327                 if (skb->priority == TC_PRIO_CONTROL)
6328                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6329                 else
6330                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6331                                >> 13;
6332                 return txq;
6333         }
6334
6335         return skb_tx_hash(dev, skb);
6336 }
6337
6338 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6339                           struct ixgbe_adapter *adapter,
6340                           struct ixgbe_ring *tx_ring)
6341 {
6342         struct net_device *netdev = tx_ring->netdev;
6343         struct netdev_queue *txq;
6344         unsigned int first;
6345         unsigned int tx_flags = 0;
6346         u8 hdr_len = 0;
6347         int tso;
6348         int count = 0;
6349         unsigned int f;
6350         __be16 protocol;
6351
6352         protocol = vlan_get_protocol(skb);
6353
6354         if (vlan_tx_tag_present(skb)) {
6355                 tx_flags |= vlan_tx_tag_get(skb);
6356                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6357                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6358                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6359                 }
6360                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6361                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6362         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6363                    skb->priority != TC_PRIO_CONTROL) {
6364                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6365                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6366                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6367         }
6368
6369 #ifdef IXGBE_FCOE
6370         /* for FCoE with DCB, we force the priority to what
6371          * was specified by the switch */
6372         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6373             (protocol == htons(ETH_P_FCOE) ||
6374              protocol == htons(ETH_P_FIP))) {
6375 #ifdef CONFIG_IXGBE_DCB
6376                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6377                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6378                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6379                         tx_flags |= ((adapter->fcoe.up << 13)
6380                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6381                 }
6382 #endif
6383                 /* flag for FCoE offloads */
6384                 if (protocol == htons(ETH_P_FCOE))
6385                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6386         }
6387 #endif
6388
6389         /* four things can cause us to need a context descriptor */
6390         if (skb_is_gso(skb) ||
6391             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6392             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6393             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6394                 count++;
6395
6396         count += TXD_USE_COUNT(skb_headlen(skb));
6397         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6398                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6399
6400         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6401                 tx_ring->tx_stats.tx_busy++;
6402                 return NETDEV_TX_BUSY;
6403         }
6404
6405         first = tx_ring->next_to_use;
6406         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6407 #ifdef IXGBE_FCOE
6408                 /* setup tx offload for FCoE */
6409                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6410                 if (tso < 0) {
6411                         dev_kfree_skb_any(skb);
6412                         return NETDEV_TX_OK;
6413                 }
6414                 if (tso)
6415                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6416 #endif /* IXGBE_FCOE */
6417         } else {
6418                 if (protocol == htons(ETH_P_IP))
6419                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6420                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6421                                 protocol);
6422                 if (tso < 0) {
6423                         dev_kfree_skb_any(skb);
6424                         return NETDEV_TX_OK;
6425                 }
6426
6427                 if (tso)
6428                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6429                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6430                                        protocol) &&
6431                          (skb->ip_summed == CHECKSUM_PARTIAL))
6432                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6433         }
6434
6435         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6436         if (count) {
6437                 /* add the ATR filter if ATR is on */
6438                 if (tx_ring->atr_sample_rate) {
6439                         ++tx_ring->atr_count;
6440                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6441                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6442                                       &tx_ring->state)) {
6443                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6444                                           tx_flags, protocol);
6445                                 tx_ring->atr_count = 0;
6446                         }
6447                 }
6448                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6449                 txq->tx_bytes += skb->len;
6450                 txq->tx_packets++;
6451                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6452                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6453
6454         } else {
6455                 dev_kfree_skb_any(skb);
6456                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6457                 tx_ring->next_to_use = first;
6458         }
6459
6460         return NETDEV_TX_OK;
6461 }
6462
6463 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6464 {
6465         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6466         struct ixgbe_ring *tx_ring;
6467
6468         tx_ring = adapter->tx_ring[skb->queue_mapping];
6469         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6470 }
6471
6472 /**
6473  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6474  * @netdev: network interface device structure
6475  * @p: pointer to an address structure
6476  *
6477  * Returns 0 on success, negative on failure
6478  **/
6479 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6480 {
6481         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6482         struct ixgbe_hw *hw = &adapter->hw;
6483         struct sockaddr *addr = p;
6484
6485         if (!is_valid_ether_addr(addr->sa_data))
6486                 return -EADDRNOTAVAIL;
6487
6488         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6489         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6490
6491         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6492                             IXGBE_RAH_AV);
6493
6494         return 0;
6495 }
6496
6497 static int
6498 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6499 {
6500         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6501         struct ixgbe_hw *hw = &adapter->hw;
6502         u16 value;
6503         int rc;
6504
6505         if (prtad != hw->phy.mdio.prtad)
6506                 return -EINVAL;
6507         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6508         if (!rc)
6509                 rc = value;
6510         return rc;
6511 }
6512
6513 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6514                             u16 addr, u16 value)
6515 {
6516         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6517         struct ixgbe_hw *hw = &adapter->hw;
6518
6519         if (prtad != hw->phy.mdio.prtad)
6520                 return -EINVAL;
6521         return hw->phy.ops.write_reg(hw, addr, devad, value);
6522 }
6523
6524 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6525 {
6526         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6527
6528         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6529 }
6530
6531 /**
6532  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6533  * netdev->dev_addrs
6534  * @netdev: network interface device structure
6535  *
6536  * Returns non-zero on failure
6537  **/
6538 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6539 {
6540         int err = 0;
6541         struct ixgbe_adapter *adapter = netdev_priv(dev);
6542         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6543
6544         if (is_valid_ether_addr(mac->san_addr)) {
6545                 rtnl_lock();
6546                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6547                 rtnl_unlock();
6548         }
6549         return err;
6550 }
6551
6552 /**
6553  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6554  * netdev->dev_addrs
6555  * @netdev: network interface device structure
6556  *
6557  * Returns non-zero on failure
6558  **/
6559 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6560 {
6561         int err = 0;
6562         struct ixgbe_adapter *adapter = netdev_priv(dev);
6563         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6564
6565         if (is_valid_ether_addr(mac->san_addr)) {
6566                 rtnl_lock();
6567                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6568                 rtnl_unlock();
6569         }
6570         return err;
6571 }
6572
6573 #ifdef CONFIG_NET_POLL_CONTROLLER
6574 /*
6575  * Polling 'interrupt' - used by things like netconsole to send skbs
6576  * without having to re-enable interrupts. It's not called while
6577  * the interrupt routine is executing.
6578  */
6579 static void ixgbe_netpoll(struct net_device *netdev)
6580 {
6581         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6582         int i;
6583
6584         /* if interface is down do nothing */
6585         if (test_bit(__IXGBE_DOWN, &adapter->state))
6586                 return;
6587
6588         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6589         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6590                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6591                 for (i = 0; i < num_q_vectors; i++) {
6592                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6593                         ixgbe_msix_clean_many(0, q_vector);
6594                 }
6595         } else {
6596                 ixgbe_intr(adapter->pdev->irq, netdev);
6597         }
6598         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6599 }
6600 #endif
6601
6602 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6603                                                    struct rtnl_link_stats64 *stats)
6604 {
6605         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6606         int i;
6607
6608         /* accurate rx/tx bytes/packets stats */
6609         dev_txq_stats_fold(netdev, stats);
6610         rcu_read_lock();
6611         for (i = 0; i < adapter->num_rx_queues; i++) {
6612                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6613                 u64 bytes, packets;
6614                 unsigned int start;
6615
6616                 if (ring) {
6617                         do {
6618                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6619                                 packets = ring->stats.packets;
6620                                 bytes   = ring->stats.bytes;
6621                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6622                         stats->rx_packets += packets;
6623                         stats->rx_bytes   += bytes;
6624                 }
6625         }
6626         rcu_read_unlock();
6627         /* following stats updated by ixgbe_watchdog_task() */
6628         stats->multicast        = netdev->stats.multicast;
6629         stats->rx_errors        = netdev->stats.rx_errors;
6630         stats->rx_length_errors = netdev->stats.rx_length_errors;
6631         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6632         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6633         return stats;
6634 }
6635
6636
6637 static const struct net_device_ops ixgbe_netdev_ops = {
6638         .ndo_open               = ixgbe_open,
6639         .ndo_stop               = ixgbe_close,
6640         .ndo_start_xmit         = ixgbe_xmit_frame,
6641         .ndo_select_queue       = ixgbe_select_queue,
6642         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6643         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6644         .ndo_validate_addr      = eth_validate_addr,
6645         .ndo_set_mac_address    = ixgbe_set_mac,
6646         .ndo_change_mtu         = ixgbe_change_mtu,
6647         .ndo_tx_timeout         = ixgbe_tx_timeout,
6648         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6649         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6650         .ndo_do_ioctl           = ixgbe_ioctl,
6651         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6652         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6653         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6654         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6655         .ndo_get_stats64        = ixgbe_get_stats64,
6656 #ifdef CONFIG_NET_POLL_CONTROLLER
6657         .ndo_poll_controller    = ixgbe_netpoll,
6658 #endif
6659 #ifdef IXGBE_FCOE
6660         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6661         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6662         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6663         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6664         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6665 #endif /* IXGBE_FCOE */
6666 };
6667
6668 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6669                            const struct ixgbe_info *ii)
6670 {
6671 #ifdef CONFIG_PCI_IOV
6672         struct ixgbe_hw *hw = &adapter->hw;
6673         int err;
6674
6675         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6676                 return;
6677
6678         /* The 82599 supports up to 64 VFs per physical function
6679          * but this implementation limits allocation to 63 so that
6680          * basic networking resources are still available to the
6681          * physical function
6682          */
6683         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6684         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6685         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6686         if (err) {
6687                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6688                 goto err_novfs;
6689         }
6690         /* If call to enable VFs succeeded then allocate memory
6691          * for per VF control structures.
6692          */
6693         adapter->vfinfo =
6694                 kcalloc(adapter->num_vfs,
6695                         sizeof(struct vf_data_storage), GFP_KERNEL);
6696         if (adapter->vfinfo) {
6697                 /* Now that we're sure SR-IOV is enabled
6698                  * and memory allocated set up the mailbox parameters
6699                  */
6700                 ixgbe_init_mbx_params_pf(hw);
6701                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6702                        sizeof(hw->mbx.ops));
6703
6704                 /* Disable RSC when in SR-IOV mode */
6705                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6706                                      IXGBE_FLAG2_RSC_ENABLED);
6707                 return;
6708         }
6709
6710         /* Oh oh */
6711         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6712               "SRIOV disabled\n");
6713         pci_disable_sriov(adapter->pdev);
6714
6715 err_novfs:
6716         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6717         adapter->num_vfs = 0;
6718 #endif /* CONFIG_PCI_IOV */
6719 }
6720
6721 /**
6722  * ixgbe_probe - Device Initialization Routine
6723  * @pdev: PCI device information struct
6724  * @ent: entry in ixgbe_pci_tbl
6725  *
6726  * Returns 0 on success, negative on failure
6727  *
6728  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6729  * The OS initialization, configuring of the adapter private structure,
6730  * and a hardware reset occur.
6731  **/
6732 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6733                                  const struct pci_device_id *ent)
6734 {
6735         struct net_device *netdev;
6736         struct ixgbe_adapter *adapter = NULL;
6737         struct ixgbe_hw *hw;
6738         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6739         static int cards_found;
6740         int i, err, pci_using_dac;
6741         unsigned int indices = num_possible_cpus();
6742 #ifdef IXGBE_FCOE
6743         u16 device_caps;
6744 #endif
6745         u32 part_num, eec;
6746
6747         /* Catch broken hardware that put the wrong VF device ID in
6748          * the PCIe SR-IOV capability.
6749          */
6750         if (pdev->is_virtfn) {
6751                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6752                      pci_name(pdev), pdev->vendor, pdev->device);
6753                 return -EINVAL;
6754         }
6755
6756         err = pci_enable_device_mem(pdev);
6757         if (err)
6758                 return err;
6759
6760         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6761             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6762                 pci_using_dac = 1;
6763         } else {
6764                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6765                 if (err) {
6766                         err = dma_set_coherent_mask(&pdev->dev,
6767                                                     DMA_BIT_MASK(32));
6768                         if (err) {
6769                                 dev_err(&pdev->dev,
6770                                         "No usable DMA configuration, aborting\n");
6771                                 goto err_dma;
6772                         }
6773                 }
6774                 pci_using_dac = 0;
6775         }
6776
6777         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6778                                            IORESOURCE_MEM), ixgbe_driver_name);
6779         if (err) {
6780                 dev_err(&pdev->dev,
6781                         "pci_request_selected_regions failed 0x%x\n", err);
6782                 goto err_pci_reg;
6783         }
6784
6785         pci_enable_pcie_error_reporting(pdev);
6786
6787         pci_set_master(pdev);
6788         pci_save_state(pdev);
6789
6790         if (ii->mac == ixgbe_mac_82598EB)
6791                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6792         else
6793                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6794
6795         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6796 #ifdef IXGBE_FCOE
6797         indices += min_t(unsigned int, num_possible_cpus(),
6798                          IXGBE_MAX_FCOE_INDICES);
6799 #endif
6800         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6801         if (!netdev) {
6802                 err = -ENOMEM;
6803                 goto err_alloc_etherdev;
6804         }
6805
6806         SET_NETDEV_DEV(netdev, &pdev->dev);
6807
6808         adapter = netdev_priv(netdev);
6809         pci_set_drvdata(pdev, adapter);
6810
6811         adapter->netdev = netdev;
6812         adapter->pdev = pdev;
6813         hw = &adapter->hw;
6814         hw->back = adapter;
6815         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6816
6817         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6818                               pci_resource_len(pdev, 0));
6819         if (!hw->hw_addr) {
6820                 err = -EIO;
6821                 goto err_ioremap;
6822         }
6823
6824         for (i = 1; i <= 5; i++) {
6825                 if (pci_resource_len(pdev, i) == 0)
6826                         continue;
6827         }
6828
6829         netdev->netdev_ops = &ixgbe_netdev_ops;
6830         ixgbe_set_ethtool_ops(netdev);
6831         netdev->watchdog_timeo = 5 * HZ;
6832         strcpy(netdev->name, pci_name(pdev));
6833
6834         adapter->bd_number = cards_found;
6835
6836         /* Setup hw api */
6837         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6838         hw->mac.type  = ii->mac;
6839
6840         /* EEPROM */
6841         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6842         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6843         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6844         if (!(eec & (1 << 8)))
6845                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6846
6847         /* PHY */
6848         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6849         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6850         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6851         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6852         hw->phy.mdio.mmds = 0;
6853         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6854         hw->phy.mdio.dev = netdev;
6855         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6856         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6857
6858         /* set up this timer and work struct before calling get_invariants
6859          * which might start the timer
6860          */
6861         init_timer(&adapter->sfp_timer);
6862         adapter->sfp_timer.function = ixgbe_sfp_timer;
6863         adapter->sfp_timer.data = (unsigned long) adapter;
6864
6865         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6866
6867         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6868         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6869
6870         /* a new SFP+ module arrival, called from GPI SDP2 context */
6871         INIT_WORK(&adapter->sfp_config_module_task,
6872                   ixgbe_sfp_config_module_task);
6873
6874         ii->get_invariants(hw);
6875
6876         /* setup the private structure */
6877         err = ixgbe_sw_init(adapter);
6878         if (err)
6879                 goto err_sw_init;
6880
6881         /* Make it possible the adapter to be woken up via WOL */
6882         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6883                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6884
6885         /*
6886          * If there is a fan on this device and it has failed log the
6887          * failure.
6888          */
6889         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6890                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6891                 if (esdp & IXGBE_ESDP_SDP1)
6892                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6893         }
6894
6895         /* reset_hw fills in the perm_addr as well */
6896         hw->phy.reset_if_overtemp = true;
6897         err = hw->mac.ops.reset_hw(hw);
6898         hw->phy.reset_if_overtemp = false;
6899         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6900             hw->mac.type == ixgbe_mac_82598EB) {
6901                 /*
6902                  * Start a kernel thread to watch for a module to arrive.
6903                  * Only do this for 82598, since 82599 will generate
6904                  * interrupts on module arrival.
6905                  */
6906                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6907                 mod_timer(&adapter->sfp_timer,
6908                           round_jiffies(jiffies + (2 * HZ)));
6909                 err = 0;
6910         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6911                 e_dev_err("failed to initialize because an unsupported SFP+ "
6912                           "module type was detected.\n");
6913                 e_dev_err("Reload the driver after installing a supported "
6914                           "module.\n");
6915                 goto err_sw_init;
6916         } else if (err) {
6917                 e_dev_err("HW Init failed: %d\n", err);
6918                 goto err_sw_init;
6919         }
6920
6921         ixgbe_probe_vf(adapter, ii);
6922
6923         netdev->features = NETIF_F_SG |
6924                            NETIF_F_IP_CSUM |
6925                            NETIF_F_HW_VLAN_TX |
6926                            NETIF_F_HW_VLAN_RX |
6927                            NETIF_F_HW_VLAN_FILTER;
6928
6929         netdev->features |= NETIF_F_IPV6_CSUM;
6930         netdev->features |= NETIF_F_TSO;
6931         netdev->features |= NETIF_F_TSO6;
6932         netdev->features |= NETIF_F_GRO;
6933
6934         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6935                 netdev->features |= NETIF_F_SCTP_CSUM;
6936
6937         netdev->vlan_features |= NETIF_F_TSO;
6938         netdev->vlan_features |= NETIF_F_TSO6;
6939         netdev->vlan_features |= NETIF_F_IP_CSUM;
6940         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6941         netdev->vlan_features |= NETIF_F_SG;
6942
6943         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6944                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6945                                     IXGBE_FLAG_DCB_ENABLED);
6946         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6947                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6948
6949 #ifdef CONFIG_IXGBE_DCB
6950         netdev->dcbnl_ops = &dcbnl_ops;
6951 #endif
6952
6953 #ifdef IXGBE_FCOE
6954         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6955                 if (hw->mac.ops.get_device_caps) {
6956                         hw->mac.ops.get_device_caps(hw, &device_caps);
6957                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6958                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6959                 }
6960         }
6961         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6962                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6963                 netdev->vlan_features |= NETIF_F_FSO;
6964                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6965         }
6966 #endif /* IXGBE_FCOE */
6967         if (pci_using_dac) {
6968                 netdev->features |= NETIF_F_HIGHDMA;
6969                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6970         }
6971
6972         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6973                 netdev->features |= NETIF_F_LRO;
6974
6975         /* make sure the EEPROM is good */
6976         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6977                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6978                 err = -EIO;
6979                 goto err_eeprom;
6980         }
6981
6982         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6983         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6984
6985         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6986                 e_dev_err("invalid MAC address\n");
6987                 err = -EIO;
6988                 goto err_eeprom;
6989         }
6990
6991         /* power down the optics */
6992         if (hw->phy.multispeed_fiber)
6993                 hw->mac.ops.disable_tx_laser(hw);
6994
6995         init_timer(&adapter->watchdog_timer);
6996         adapter->watchdog_timer.function = ixgbe_watchdog;
6997         adapter->watchdog_timer.data = (unsigned long)adapter;
6998
6999         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7000         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7001
7002         err = ixgbe_init_interrupt_scheme(adapter);
7003         if (err)
7004                 goto err_sw_init;
7005
7006         switch (pdev->device) {
7007         case IXGBE_DEV_ID_82599_KX4:
7008                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7009                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7010                 break;
7011         default:
7012                 adapter->wol = 0;
7013                 break;
7014         }
7015         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7016
7017         /* pick up the PCI bus settings for reporting later */
7018         hw->mac.ops.get_bus_info(hw);
7019
7020         /* print bus type/speed/width info */
7021         e_dev_info("(PCI Express:%s:%s) %pM\n",
7022                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7023                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7024                     "Unknown"),
7025                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7026                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7027                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7028                     "Unknown"),
7029                    netdev->dev_addr);
7030         ixgbe_read_pba_num_generic(hw, &part_num);
7031         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7032                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7033                            "PBA No: %06x-%03x\n",
7034                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7035                            (part_num >> 8), (part_num & 0xff));
7036         else
7037                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7038                            hw->mac.type, hw->phy.type,
7039                            (part_num >> 8), (part_num & 0xff));
7040
7041         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7042                 e_dev_warn("PCI-Express bandwidth available for this card is "
7043                            "not sufficient for optimal performance.\n");
7044                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7045                            "is required.\n");
7046         }
7047
7048         /* save off EEPROM version number */
7049         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7050
7051         /* reset the hardware with the new settings */
7052         err = hw->mac.ops.start_hw(hw);
7053
7054         if (err == IXGBE_ERR_EEPROM_VERSION) {
7055                 /* We are running on a pre-production device, log a warning */
7056                 e_dev_warn("This device is a pre-production adapter/LOM. "
7057                            "Please be aware there may be issues associated "
7058                            "with your hardware.  If you are experiencing "
7059                            "problems please contact your Intel or hardware "
7060                            "representative who provided you with this "
7061                            "hardware.\n");
7062         }
7063         strcpy(netdev->name, "eth%d");
7064         err = register_netdev(netdev);
7065         if (err)
7066                 goto err_register;
7067
7068         /* carrier off reporting is important to ethtool even BEFORE open */
7069         netif_carrier_off(netdev);
7070
7071         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7072             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7073                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7074
7075         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7076                 INIT_WORK(&adapter->check_overtemp_task,
7077                           ixgbe_check_overtemp_task);
7078 #ifdef CONFIG_IXGBE_DCA
7079         if (dca_add_requester(&pdev->dev) == 0) {
7080                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7081                 ixgbe_setup_dca(adapter);
7082         }
7083 #endif
7084         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7085                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7086                 for (i = 0; i < adapter->num_vfs; i++)
7087                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7088         }
7089
7090         /* add san mac addr to netdev */
7091         ixgbe_add_sanmac_netdev(netdev);
7092
7093         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7094         cards_found++;
7095         return 0;
7096
7097 err_register:
7098         ixgbe_release_hw_control(adapter);
7099         ixgbe_clear_interrupt_scheme(adapter);
7100 err_sw_init:
7101 err_eeprom:
7102         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7103                 ixgbe_disable_sriov(adapter);
7104         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7105         del_timer_sync(&adapter->sfp_timer);
7106         cancel_work_sync(&adapter->sfp_task);
7107         cancel_work_sync(&adapter->multispeed_fiber_task);
7108         cancel_work_sync(&adapter->sfp_config_module_task);
7109         iounmap(hw->hw_addr);
7110 err_ioremap:
7111         free_netdev(netdev);
7112 err_alloc_etherdev:
7113         pci_release_selected_regions(pdev,
7114                                      pci_select_bars(pdev, IORESOURCE_MEM));
7115 err_pci_reg:
7116 err_dma:
7117         pci_disable_device(pdev);
7118         return err;
7119 }
7120
7121 /**
7122  * ixgbe_remove - Device Removal Routine
7123  * @pdev: PCI device information struct
7124  *
7125  * ixgbe_remove is called by the PCI subsystem to alert the driver
7126  * that it should release a PCI device.  The could be caused by a
7127  * Hot-Plug event, or because the driver is going to be removed from
7128  * memory.
7129  **/
7130 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7131 {
7132         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7133         struct net_device *netdev = adapter->netdev;
7134
7135         set_bit(__IXGBE_DOWN, &adapter->state);
7136         /* clear the module not found bit to make sure the worker won't
7137          * reschedule
7138          */
7139         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7140         del_timer_sync(&adapter->watchdog_timer);
7141
7142         del_timer_sync(&adapter->sfp_timer);
7143         cancel_work_sync(&adapter->watchdog_task);
7144         cancel_work_sync(&adapter->sfp_task);
7145         cancel_work_sync(&adapter->multispeed_fiber_task);
7146         cancel_work_sync(&adapter->sfp_config_module_task);
7147         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7148             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7149                 cancel_work_sync(&adapter->fdir_reinit_task);
7150         flush_scheduled_work();
7151
7152 #ifdef CONFIG_IXGBE_DCA
7153         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7154                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7155                 dca_remove_requester(&pdev->dev);
7156                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7157         }
7158
7159 #endif
7160 #ifdef IXGBE_FCOE
7161         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7162                 ixgbe_cleanup_fcoe(adapter);
7163
7164 #endif /* IXGBE_FCOE */
7165
7166         /* remove the added san mac */
7167         ixgbe_del_sanmac_netdev(netdev);
7168
7169         if (netdev->reg_state == NETREG_REGISTERED)
7170                 unregister_netdev(netdev);
7171
7172         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7173                 ixgbe_disable_sriov(adapter);
7174
7175         ixgbe_clear_interrupt_scheme(adapter);
7176
7177         ixgbe_release_hw_control(adapter);
7178
7179         iounmap(adapter->hw.hw_addr);
7180         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7181                                      IORESOURCE_MEM));
7182
7183         e_dev_info("complete\n");
7184
7185         free_netdev(netdev);
7186
7187         pci_disable_pcie_error_reporting(pdev);
7188
7189         pci_disable_device(pdev);
7190 }
7191
7192 /**
7193  * ixgbe_io_error_detected - called when PCI error is detected
7194  * @pdev: Pointer to PCI device
7195  * @state: The current pci connection state
7196  *
7197  * This function is called after a PCI bus error affecting
7198  * this device has been detected.
7199  */
7200 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7201                                                 pci_channel_state_t state)
7202 {
7203         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7204         struct net_device *netdev = adapter->netdev;
7205
7206         netif_device_detach(netdev);
7207
7208         if (state == pci_channel_io_perm_failure)
7209                 return PCI_ERS_RESULT_DISCONNECT;
7210
7211         if (netif_running(netdev))
7212                 ixgbe_down(adapter);
7213         pci_disable_device(pdev);
7214
7215         /* Request a slot reset. */
7216         return PCI_ERS_RESULT_NEED_RESET;
7217 }
7218
7219 /**
7220  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7221  * @pdev: Pointer to PCI device
7222  *
7223  * Restart the card from scratch, as if from a cold-boot.
7224  */
7225 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7226 {
7227         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7228         pci_ers_result_t result;
7229         int err;
7230
7231         if (pci_enable_device_mem(pdev)) {
7232                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7233                 result = PCI_ERS_RESULT_DISCONNECT;
7234         } else {
7235                 pci_set_master(pdev);
7236                 pci_restore_state(pdev);
7237                 pci_save_state(pdev);
7238
7239                 pci_wake_from_d3(pdev, false);
7240
7241                 ixgbe_reset(adapter);
7242                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7243                 result = PCI_ERS_RESULT_RECOVERED;
7244         }
7245
7246         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7247         if (err) {
7248                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7249                           "failed 0x%0x\n", err);
7250                 /* non-fatal, continue */
7251         }
7252
7253         return result;
7254 }
7255
7256 /**
7257  * ixgbe_io_resume - called when traffic can start flowing again.
7258  * @pdev: Pointer to PCI device
7259  *
7260  * This callback is called when the error recovery driver tells us that
7261  * its OK to resume normal operation.
7262  */
7263 static void ixgbe_io_resume(struct pci_dev *pdev)
7264 {
7265         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7266         struct net_device *netdev = adapter->netdev;
7267
7268         if (netif_running(netdev)) {
7269                 if (ixgbe_up(adapter)) {
7270                         e_info(probe, "ixgbe_up failed after reset\n");
7271                         return;
7272                 }
7273         }
7274
7275         netif_device_attach(netdev);
7276 }
7277
7278 static struct pci_error_handlers ixgbe_err_handler = {
7279         .error_detected = ixgbe_io_error_detected,
7280         .slot_reset = ixgbe_io_slot_reset,
7281         .resume = ixgbe_io_resume,
7282 };
7283
7284 static struct pci_driver ixgbe_driver = {
7285         .name     = ixgbe_driver_name,
7286         .id_table = ixgbe_pci_tbl,
7287         .probe    = ixgbe_probe,
7288         .remove   = __devexit_p(ixgbe_remove),
7289 #ifdef CONFIG_PM
7290         .suspend  = ixgbe_suspend,
7291         .resume   = ixgbe_resume,
7292 #endif
7293         .shutdown = ixgbe_shutdown,
7294         .err_handler = &ixgbe_err_handler
7295 };
7296
7297 /**
7298  * ixgbe_init_module - Driver Registration Routine
7299  *
7300  * ixgbe_init_module is the first routine called when the driver is
7301  * loaded. All it does is register with the PCI subsystem.
7302  **/
7303 static int __init ixgbe_init_module(void)
7304 {
7305         int ret;
7306         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7307         pr_info("%s\n", ixgbe_copyright);
7308
7309 #ifdef CONFIG_IXGBE_DCA
7310         dca_register_notify(&dca_notifier);
7311 #endif
7312
7313         ret = pci_register_driver(&ixgbe_driver);
7314         return ret;
7315 }
7316
7317 module_init(ixgbe_init_module);
7318
7319 /**
7320  * ixgbe_exit_module - Driver Exit Cleanup Routine
7321  *
7322  * ixgbe_exit_module is called just before the driver is removed
7323  * from memory.
7324  **/
7325 static void __exit ixgbe_exit_module(void)
7326 {
7327 #ifdef CONFIG_IXGBE_DCA
7328         dca_unregister_notify(&dca_notifier);
7329 #endif
7330         pci_unregister_driver(&ixgbe_driver);
7331         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7332 }
7333
7334 #ifdef CONFIG_IXGBE_DCA
7335 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7336                             void *p)
7337 {
7338         int ret_val;
7339
7340         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7341                                          __ixgbe_notify_dca);
7342
7343         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7344 }
7345
7346 #endif /* CONFIG_IXGBE_DCA */
7347
7348 /**
7349  * ixgbe_get_hw_dev return device
7350  * used by hardware layer to print debugging information
7351  **/
7352 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7353 {
7354         struct ixgbe_adapter *adapter = hw->back;
7355         return adapter->netdev;
7356 }
7357
7358 module_exit(ixgbe_exit_module);
7359
7360 /* ixgbe_main.c */