drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         switch (adapter->hw.mac.type) {
 593         case ixgbe_mac_82598EB:
 594                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 595                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 596                 break;
 597         case ixgbe_mac_82599EB:
 598                 mask = (qmask & 0xFFFFFFFF);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 600                 mask = (qmask >> 32);
 601                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 602                 break;
 603         default:
 604                 break;
 605         }
 606 }
 607
 608 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 609                                       struct ixgbe_tx_buffer *tx_buffer_info)
 610 {
 611         if (tx_buffer_info->dma) {
 612                 if (tx_buffer_info->mapped_as_page)
 613                         dma_unmap_page(tx_ring->dev,
 614                                        tx_buffer_info->dma,
 615                                        tx_buffer_info->length,
 616                                        DMA_TO_DEVICE);
 617                 else
 618                         dma_unmap_single(tx_ring->dev,
 619                                          tx_buffer_info->dma,
 620                                          tx_buffer_info->length,
 621                                          DMA_TO_DEVICE);
 622                 tx_buffer_info->dma = 0;
 623         }
 624         if (tx_buffer_info->skb) {
 625                 dev_kfree_skb_any(tx_buffer_info->skb);
 626                 tx_buffer_info->skb = NULL;
 627         }
 628         tx_buffer_info->time_stamp = 0;
 629         /* tx_buffer_info must be completely set up in the transmit path */
 630 }
 631
 632 /**
 633  * ixgbe_tx_xon_state - check the tx ring xon state
 634  * @adapter: the ixgbe adapter
 635  * @tx_ring: the corresponding tx_ring
 636  *
 637  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 638  * corresponding TC of this tx_ring when checking TFCS.
 639  *
 640  * Returns : true if in xon state (currently not paused)
 641  */
 642 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 643                                       struct ixgbe_ring *tx_ring)
 644 {
 645         u32 txoff = IXGBE_TFCS_TXOFF;
 646
 647 #ifdef CONFIG_IXGBE_DCB
 648         if (adapter->dcb_cfg.pfc_mode_enable) {
 649                 int tc;
 650                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 651                 u8 reg_idx = tx_ring->reg_idx;
 652
 653                 switch (adapter->hw.mac.type) {
 654                 case ixgbe_mac_82598EB:
 655                         tc = reg_idx >> 2;
 656                         txoff = IXGBE_TFCS_TXOFF0;
 657                         break;
 658                 case ixgbe_mac_82599EB:
 659                         tc = 0;
 660                         txoff = IXGBE_TFCS_TXOFF;
 661                         if (dcb_i == 8) {
 662                                 /* TC0, TC1 */
 663                                 tc = reg_idx >> 5;
 664                                 if (tc == 2) /* TC2, TC3 */
 665                                         tc += (reg_idx - 64) >> 4;
 666                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 667                                         tc += 1 + ((reg_idx - 96) >> 3);
 668                         } else if (dcb_i == 4) {
 669                                 /* TC0, TC1 */
 670                                 tc = reg_idx >> 6;
 671                                 if (tc == 1) {
 672                                         tc += (reg_idx - 64) >> 5;
 673                                         if (tc == 2) /* TC2, TC3 */
 674                                                 tc += (reg_idx - 96) >> 4;
 675                                 }
 676                         }
 677                         break;
 678                 default:
 679                         tc = 0;
 680                         break;
 681                 }
 682                 txoff <<= tc;
 683         }
 684 #endif
 685         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 686 }
 687
 688 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 689                                        struct ixgbe_ring *tx_ring,
 690                                        unsigned int eop)
 691 {
 692         struct ixgbe_hw *hw = &adapter->hw;
 693
 694         /* Detect a transmit hang in hardware, this serializes the
 695          * check with the clearing of time_stamp and movement of eop */
 696         clear_check_for_tx_hang(tx_ring);
 697         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 698             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 699             ixgbe_tx_xon_state(adapter, tx_ring)) {
 700                 /* detected Tx unit hang */
 701                 union ixgbe_adv_tx_desc *tx_desc;
 702                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 703                 e_err(drv, "Detected Tx Unit Hang\n"
 704                       "  Tx Queue             <%d>\n"
 705                       "  TDH, TDT             <%x>, <%x>\n"
 706                       "  next_to_use          <%x>\n"
 707                       "  next_to_clean        <%x>\n"
 708                       "tx_buffer_info[next_to_clean]\n"
 709                       "  time_stamp           <%lx>\n"
 710                       "  jiffies              <%lx>\n",
 711                       tx_ring->queue_index,
 712                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 713                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 714                       tx_ring->next_to_use, eop,
 715                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 716                 return true;
 717         }
 718
 719         return false;
 720 }
 721
 722 #define IXGBE_MAX_TXD_PWR       14
 723 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 724
 725 /* Tx Descriptors needed, worst case */
 726 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 727                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 728 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 729         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 730
 731 static void ixgbe_tx_timeout(struct net_device *netdev);
 732
 733 /**
 734  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 735  * @q_vector: structure containing interrupt and ring information
 736  * @tx_ring: tx ring to clean
 737  **/
 738 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 739                                struct ixgbe_ring *tx_ring)
 740 {
 741         struct ixgbe_adapter *adapter = q_vector->adapter;
 742         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 743         struct ixgbe_tx_buffer *tx_buffer_info;
 744         unsigned int total_bytes = 0, total_packets = 0;
 745         u16 i, eop, count = 0;
 746
 747         i = tx_ring->next_to_clean;
 748         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 749         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 750
 751         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 752                (count < tx_ring->work_limit)) {
 753                 bool cleaned = false;
 754                 rmb(); /* read buffer_info after eop_desc */
 755                 for ( ; !cleaned; count++) {
 756                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 757                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 758
 759                         tx_desc->wb.status = 0;
 760                         cleaned = (i == eop);
 761
 762                         i++;
 763                         if (i == tx_ring->count)
 764                                 i = 0;
 765
 766                         if (cleaned && tx_buffer_info->skb) {
 767                                 total_bytes += tx_buffer_info->bytecount;
 768                                 total_packets += tx_buffer_info->gso_segs;
 769                         }
 770
 771                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 772                                                          tx_buffer_info);
 773                 }
 774
 775                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 776                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 777         }
 778
 779         tx_ring->next_to_clean = i;
 780         tx_ring->total_bytes += total_bytes;
 781         tx_ring->total_packets += total_packets;
 782         u64_stats_update_begin(&tx_ring->syncp);
 783         tx_ring->stats.packets += total_packets;
 784         tx_ring->stats.bytes += total_bytes;
 785         u64_stats_update_end(&tx_ring->syncp);
 786
 787         if (check_for_tx_hang(tx_ring) &&
 788             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 789                 /* schedule immediate reset if we believe we hung */
 790                 e_info(probe, "tx hang %d detected, resetting "
 791                        "adapter\n", adapter->tx_timeout_count + 1);
 792                 ixgbe_tx_timeout(adapter->netdev);
 793
 794                 /* the adapter is about to reset, no point in enabling stuff */
 795                 return true;
 796         }
 797
 798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 799         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 800                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 801                 /* Make sure that anybody stopping the queue after this
 802                  * sees the new next_to_clean.
 803                  */
 804                 smp_mb();
 805                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 806                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 807                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 808                         ++tx_ring->tx_stats.restart_queue;
 809                 }
 810         }
 811
 812         return count < tx_ring->work_limit;
 813 }
 814
 815 #ifdef CONFIG_IXGBE_DCA
 816 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 817                                 struct ixgbe_ring *rx_ring,
 818                                 int cpu)
 819 {
 820         struct ixgbe_hw *hw = &adapter->hw;
 821         u32 rxctrl;
 822         u8 reg_idx = rx_ring->reg_idx;
 823
 824         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 825         switch (hw->mac.type) {
 826         case ixgbe_mac_82598EB:
 827                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 828                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 829                 break;
 830         case ixgbe_mac_82599EB:
 831                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 832                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 833                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 834                 break;
 835         default:
 836                 break;
 837         }
 838         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 839         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 840         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 841         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 842                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 843         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 844 }
 845
 846 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 847                                 struct ixgbe_ring *tx_ring,
 848                                 int cpu)
 849 {
 850         struct ixgbe_hw *hw = &adapter->hw;
 851         u32 txctrl;
 852         u8 reg_idx = tx_ring->reg_idx;
 853
 854         switch (hw->mac.type) {
 855         case ixgbe_mac_82598EB:
 856                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 857                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 858                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 859                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 860                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 861                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 862                 break;
 863         case ixgbe_mac_82599EB:
 864                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 865                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 866                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 867                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 868                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 869                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 870                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 871                 break;
 872         default:
 873                 break;
 874         }
 875 }
 876
 877 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 878 {
 879         struct ixgbe_adapter *adapter = q_vector->adapter;
 880         int cpu = get_cpu();
 881         long r_idx;
 882         int i;
 883
 884         if (q_vector->cpu == cpu)
 885                 goto out_no_update;
 886
 887         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 888         for (i = 0; i < q_vector->txr_count; i++) {
 889                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 890                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 891                                       r_idx + 1);
 892         }
 893
 894         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 895         for (i = 0; i < q_vector->rxr_count; i++) {
 896                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 897                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 898                                       r_idx + 1);
 899         }
 900
 901         q_vector->cpu = cpu;
 902 out_no_update:
 903         put_cpu();
 904 }
 905
 906 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 907 {
 908         int num_q_vectors;
 909         int i;
 910
 911         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 912                 return;
 913
 914         /* always use CB2 mode, difference is masked in the CB driver */
 915         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 916
 917         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 918                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 919         else
 920                 num_q_vectors = 1;
 921
 922         for (i = 0; i < num_q_vectors; i++) {
 923                 adapter->q_vector[i]->cpu = -1;
 924                 ixgbe_update_dca(adapter->q_vector[i]);
 925         }
 926 }
 927
 928 static int __ixgbe_notify_dca(struct device *dev, void *data)
 929 {
 930         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 931         unsigned long event = *(unsigned long *)data;
 932
 933         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 934                 return 0;
 935
 936         switch (event) {
 937         case DCA_PROVIDER_ADD:
 938                 /* if we're already enabled, don't do it again */
 939                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 940                         break;
 941                 if (dca_add_requester(dev) == 0) {
 942                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 943                         ixgbe_setup_dca(adapter);
 944                         break;
 945                 }
 946                 /* Fall Through since DCA is disabled. */
 947         case DCA_PROVIDER_REMOVE:
 948                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 949                         dca_remove_requester(dev);
 950                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 951                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 952                 }
 953                 break;
 954         }
 955
 956         return 0;
 957 }
 958
 959 #endif /* CONFIG_IXGBE_DCA */
 960 /**
 961  * ixgbe_receive_skb - Send a completed packet up the stack
 962  * @adapter: board private structure
 963  * @skb: packet to send up
 964  * @status: hardware indication of status of receive
 965  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 966  * @rx_desc: rx descriptor
 967  **/
 968 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 969                               struct sk_buff *skb, u8 status,
 970                               struct ixgbe_ring *ring,
 971                               union ixgbe_adv_rx_desc *rx_desc)
 972 {
 973         struct ixgbe_adapter *adapter = q_vector->adapter;
 974         struct napi_struct *napi = &q_vector->napi;
 975         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 976         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 977
 978         if (is_vlan && (tag & VLAN_VID_MASK))
 979                 __vlan_hwaccel_put_tag(skb, tag);
 980
 981         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 982                 napi_gro_receive(napi, skb);
 983         else
 984                 netif_rx(skb);
 985 }
 986
 987 /**
 988  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 989  * @adapter: address of board private structure
 990  * @status_err: hardware indication of status of receive
 991  * @skb: skb currently being received and modified
 992  **/
 993 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 994                                      union ixgbe_adv_rx_desc *rx_desc,
 995                                      struct sk_buff *skb)
 996 {
 997         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 998
 999         skb_checksum_none_assert(skb);
1000
1001         /* Rx csum disabled */
1002         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1003                 return;
1004
1005         /* if IP and error */
1006         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1007             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1008                 adapter->hw_csum_rx_error++;
1009                 return;
1010         }
1011
1012         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1013                 return;
1014
1015         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1016                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1017
1018                 /*
1019                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1020                  * checksum errors.
1021                  */
1022                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1023                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1024                         return;
1025
1026                 adapter->hw_csum_rx_error++;
1027                 return;
1028         }
1029
1030         /* It must be a TCP or UDP packet with a valid checksum */
1031         skb->ip_summed = CHECKSUM_UNNECESSARY;
1032 }
1033
1034 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1035 {
1036         /*
1037          * Force memory writes to complete before letting h/w
1038          * know there are new descriptors to fetch.  (Only
1039          * applicable for weak-ordered memory model archs,
1040          * such as IA-64).
1041          */
1042         wmb();
1043         writel(val, rx_ring->tail);
1044 }
1045
1046 /**
1047  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1048  * @rx_ring: ring to place buffers on
1049  * @cleaned_count: number of buffers to replace
1050  **/
1051 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1052 {
1053         union ixgbe_adv_rx_desc *rx_desc;
1054         struct ixgbe_rx_buffer *bi;
1055         struct sk_buff *skb;
1056         u16 i = rx_ring->next_to_use;
1057
1058         /* do nothing if no valid netdev defined */
1059         if (!rx_ring->netdev)
1060                 return;
1061
1062         while (cleaned_count--) {
1063                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1064                 bi = &rx_ring->rx_buffer_info[i];
1065                 skb = bi->skb;
1066
1067                 if (!skb) {
1068                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1069                                                         rx_ring->rx_buf_len);
1070                         if (!skb) {
1071                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1072                                 goto no_buffers;
1073                         }
1074                         /* initialize queue mapping */
1075                         skb_record_rx_queue(skb, rx_ring->queue_index);
1076                         bi->skb = skb;
1077                 }
1078
1079                 if (!bi->dma) {
1080                         bi->dma = dma_map_single(rx_ring->dev,
1081                                                  skb->data,
1082                                                  rx_ring->rx_buf_len,
1083                                                  DMA_FROM_DEVICE);
1084                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1085                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1086                                 bi->dma = 0;
1087                                 goto no_buffers;
1088                         }
1089                 }
1090
1091                 if (ring_is_ps_enabled(rx_ring)) {
1092                         if (!bi->page) {
1093                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1094                                 if (!bi->page) {
1095                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1096                                         goto no_buffers;
1097                                 }
1098                         }
1099
1100                         if (!bi->page_dma) {
1101                                 /* use a half page if we're re-using */
1102                                 bi->page_offset ^= PAGE_SIZE / 2;
1103                                 bi->page_dma = dma_map_page(rx_ring->dev,
1104                                                             bi->page,
1105                                                             bi->page_offset,
1106                                                             PAGE_SIZE / 2,
1107                                                             DMA_FROM_DEVICE);
1108                                 if (dma_mapping_error(rx_ring->dev,
1109                                                       bi->page_dma)) {
1110                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1111                                         bi->page_dma = 0;
1112                                         goto no_buffers;
1113                                 }
1114                         }
1115
1116                         /* Refresh the desc even if buffer_addrs didn't change
1117                          * because each write-back erases this info. */
1118                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1119                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1120                 } else {
1121                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1122                         rx_desc->read.hdr_addr = 0;
1123                 }
1124
1125                 i++;
1126                 if (i == rx_ring->count)
1127                         i = 0;
1128         }
1129
1130 no_buffers:
1131         if (rx_ring->next_to_use != i) {
1132                 rx_ring->next_to_use = i;
1133                 ixgbe_release_rx_desc(rx_ring, i);
1134         }
1135 }
1136
1137 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1138 {
1139         /* HW will not DMA in data larger than the given buffer, even if it
1140          * parses the (NFS, of course) header to be larger.  In that case, it
1141          * fills the header buffer and spills the rest into the page.
1142          */
1143         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1144         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1145                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1146         if (hlen > IXGBE_RX_HDR_SIZE)
1147                 hlen = IXGBE_RX_HDR_SIZE;
1148         return hlen;
1149 }
1150
1151 /**
1152  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1153  * @skb: pointer to the last skb in the rsc queue
1154  *
1155  * This function changes a queue full of hw rsc buffers into a completed
1156  * packet.  It uses the ->prev pointers to find the first packet and then
1157  * turns it into the frag list owner.
1158  **/
1159 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1160 {
1161         unsigned int frag_list_size = 0;
1162         unsigned int skb_cnt = 1;
1163
1164         while (skb->prev) {
1165                 struct sk_buff *prev = skb->prev;
1166                 frag_list_size += skb->len;
1167                 skb->prev = NULL;
1168                 skb = prev;
1169                 skb_cnt++;
1170         }
1171
1172         skb_shinfo(skb)->frag_list = skb->next;
1173         skb->next = NULL;
1174         skb->len += frag_list_size;
1175         skb->data_len += frag_list_size;
1176         skb->truesize += frag_list_size;
1177         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1178
1179         return skb;
1180 }
1181
1182 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1183 {
1184         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1185                 IXGBE_RXDADV_RSCCNT_MASK);
1186 }
1187
1188 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1189                                struct ixgbe_ring *rx_ring,
1190                                int *work_done, int work_to_do)
1191 {
1192         struct ixgbe_adapter *adapter = q_vector->adapter;
1193         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1194         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1195         struct sk_buff *skb;
1196         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1197         const int current_node = numa_node_id();
1198 #ifdef IXGBE_FCOE
1199         int ddp_bytes = 0;
1200 #endif /* IXGBE_FCOE */
1201         u32 staterr;
1202         u16 i;
1203         u16 cleaned_count = 0;
1204         bool pkt_is_rsc = false;
1205
1206         i = rx_ring->next_to_clean;
1207         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1208         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1209
1210         while (staterr & IXGBE_RXD_STAT_DD) {
1211                 u32 upper_len = 0;
1212
1213                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1214
1215                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1216
1217                 skb = rx_buffer_info->skb;
1218                 rx_buffer_info->skb = NULL;
1219                 prefetch(skb->data);
1220
1221                 if (ring_is_rsc_enabled(rx_ring))
1222                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1223
1224                 /* if this is a skb from previous receive DMA will be 0 */
1225                 if (rx_buffer_info->dma) {
1226                         u16 hlen;
1227                         if (pkt_is_rsc &&
1228                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1229                             !skb->prev) {
1230                                 /*
1231                                  * When HWRSC is enabled, delay unmapping
1232                                  * of the first packet. It carries the
1233                                  * header information, HW may still
1234                                  * access the header after the writeback.
1235                                  * Only unmap it when EOP is reached
1236                                  */
1237                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1238                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1239                         } else {
1240                                 dma_unmap_single(rx_ring->dev,
1241                                                  rx_buffer_info->dma,
1242                                                  rx_ring->rx_buf_len,
1243                                                  DMA_FROM_DEVICE);
1244                         }
1245                         rx_buffer_info->dma = 0;
1246
1247                         if (ring_is_ps_enabled(rx_ring)) {
1248                                 hlen = ixgbe_get_hlen(rx_desc);
1249                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1250                         } else {
1251                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1252                         }
1253
1254                         skb_put(skb, hlen);
1255                 } else {
1256                         /* assume packet split since header is unmapped */
1257                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1258                 }
1259
1260                 if (upper_len) {
1261                         dma_unmap_page(rx_ring->dev,
1262                                        rx_buffer_info->page_dma,
1263                                        PAGE_SIZE / 2,
1264                                        DMA_FROM_DEVICE);
1265                         rx_buffer_info->page_dma = 0;
1266                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1267                                            rx_buffer_info->page,
1268                                            rx_buffer_info->page_offset,
1269                                            upper_len);
1270
1271                         if ((page_count(rx_buffer_info->page) == 1) &&
1272                             (page_to_nid(rx_buffer_info->page) == current_node))
1273                                 get_page(rx_buffer_info->page);
1274                         else
1275                                 rx_buffer_info->page = NULL;
1276
1277                         skb->len += upper_len;
1278                         skb->data_len += upper_len;
1279                         skb->truesize += upper_len;
1280                 }
1281
1282                 i++;
1283                 if (i == rx_ring->count)
1284                         i = 0;
1285
1286                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1287                 prefetch(next_rxd);
1288                 cleaned_count++;
1289
1290                 if (pkt_is_rsc) {
1291                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1292                                      IXGBE_RXDADV_NEXTP_SHIFT;
1293                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1294                 } else {
1295                         next_buffer = &rx_ring->rx_buffer_info[i];
1296                 }
1297
1298                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1299                         if (ring_is_ps_enabled(rx_ring)) {
1300                                 rx_buffer_info->skb = next_buffer->skb;
1301                                 rx_buffer_info->dma = next_buffer->dma;
1302                                 next_buffer->skb = skb;
1303                                 next_buffer->dma = 0;
1304                         } else {
1305                                 skb->next = next_buffer->skb;
1306                                 skb->next->prev = skb;
1307                         }
1308                         rx_ring->rx_stats.non_eop_descs++;
1309                         goto next_desc;
1310                 }
1311
1312                 if (skb->prev) {
1313                         skb = ixgbe_transform_rsc_queue(skb);
1314                         /* if we got here without RSC the packet is invalid */
1315                         if (!pkt_is_rsc) {
1316                                 __pskb_trim(skb, 0);
1317                                 rx_buffer_info->skb = skb;
1318                                 goto next_desc;
1319                         }
1320                 }
1321
1322                 if (ring_is_rsc_enabled(rx_ring)) {
1323                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1324                                 dma_unmap_single(rx_ring->dev,
1325                                                  IXGBE_RSC_CB(skb)->dma,
1326                                                  rx_ring->rx_buf_len,
1327                                                  DMA_FROM_DEVICE);
1328                                 IXGBE_RSC_CB(skb)->dma = 0;
1329                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1330                         }
1331                 }
1332                 if (pkt_is_rsc) {
1333                         if (ring_is_ps_enabled(rx_ring))
1334                                 rx_ring->rx_stats.rsc_count +=
1335                                         skb_shinfo(skb)->nr_frags;
1336                         else
1337                                 rx_ring->rx_stats.rsc_count +=
1338                                         IXGBE_RSC_CB(skb)->skb_cnt;
1339                         rx_ring->rx_stats.rsc_flush++;
1340                 }
1341
1342                 /* ERR_MASK will only have valid bits if EOP set */
1343                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1344                         /* trim packet back to size 0 and recycle it */
1345                         __pskb_trim(skb, 0);
1346                         rx_buffer_info->skb = skb;
1347                         goto next_desc;
1348                 }
1349
1350                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1351
1352                 /* probably a little skewed due to removing CRC */
1353                 total_rx_bytes += skb->len;
1354                 total_rx_packets++;
1355
1356                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1357 #ifdef IXGBE_FCOE
1358                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1359                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1360                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1361                         if (!ddp_bytes)
1362                                 goto next_desc;
1363                 }
1364 #endif /* IXGBE_FCOE */
1365                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1366
1367 next_desc:
1368                 rx_desc->wb.upper.status_error = 0;
1369
1370                 (*work_done)++;
1371                 if (*work_done >= work_to_do)
1372                         break;
1373
1374                 /* return some buffers to hardware, one at a time is too slow */
1375                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1376                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1377                         cleaned_count = 0;
1378                 }
1379
1380                 /* use prefetched values */
1381                 rx_desc = next_rxd;
1382                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1383         }
1384
1385         rx_ring->next_to_clean = i;
1386         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1387
1388         if (cleaned_count)
1389                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1390
1391 #ifdef IXGBE_FCOE
1392         /* include DDPed FCoE data */
1393         if (ddp_bytes > 0) {
1394                 unsigned int mss;
1395
1396                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1397                         sizeof(struct fc_frame_header) -
1398                         sizeof(struct fcoe_crc_eof);
1399                 if (mss > 512)
1400                         mss &= ~511;
1401                 total_rx_bytes += ddp_bytes;
1402                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1403         }
1404 #endif /* IXGBE_FCOE */
1405
1406         rx_ring->total_packets += total_rx_packets;
1407         rx_ring->total_bytes += total_rx_bytes;
1408         u64_stats_update_begin(&rx_ring->syncp);
1409         rx_ring->stats.packets += total_rx_packets;
1410         rx_ring->stats.bytes += total_rx_bytes;
1411         u64_stats_update_end(&rx_ring->syncp);
1412 }
1413
1414 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1415 /**
1416  * ixgbe_configure_msix - Configure MSI-X hardware
1417  * @adapter: board private structure
1418  *
1419  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1420  * interrupts.
1421  **/
1422 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1423 {
1424         struct ixgbe_q_vector *q_vector;
1425         int i, q_vectors, v_idx, r_idx;
1426         u32 mask;
1427
1428         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1429
1430         /*
1431          * Populate the IVAR table and set the ITR values to the
1432          * corresponding register.
1433          */
1434         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1435                 q_vector = adapter->q_vector[v_idx];
1436                 /* XXX for_each_set_bit(...) */
1437                 r_idx = find_first_bit(q_vector->rxr_idx,
1438                                        adapter->num_rx_queues);
1439
1440                 for (i = 0; i < q_vector->rxr_count; i++) {
1441                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1442                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1443                         r_idx = find_next_bit(q_vector->rxr_idx,
1444                                               adapter->num_rx_queues,
1445                                               r_idx + 1);
1446                 }
1447                 r_idx = find_first_bit(q_vector->txr_idx,
1448                                        adapter->num_tx_queues);
1449
1450                 for (i = 0; i < q_vector->txr_count; i++) {
1451                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1452                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1453                         r_idx = find_next_bit(q_vector->txr_idx,
1454                                               adapter->num_tx_queues,
1455                                               r_idx + 1);
1456                 }
1457
1458                 if (q_vector->txr_count && !q_vector->rxr_count)
1459                         /* tx only */
1460                         q_vector->eitr = adapter->tx_eitr_param;
1461                 else if (q_vector->rxr_count)
1462                         /* rx or mixed */
1463                         q_vector->eitr = adapter->rx_eitr_param;
1464
1465                 ixgbe_write_eitr(q_vector);
1466                 /* If Flow Director is enabled, set interrupt affinity */
1467                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1468                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1469                         /*
1470                          * Allocate the affinity_hint cpumask, assign the mask
1471                          * for this vector, and set our affinity_hint for
1472                          * this irq.
1473                          */
1474                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1475                                                GFP_KERNEL))
1476                                 return;
1477                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1478                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1479                                               q_vector->affinity_mask);
1480                 }
1481         }
1482
1483         switch (adapter->hw.mac.type) {
1484         case ixgbe_mac_82598EB:
1485                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1486                                v_idx);
1487                 break;
1488         case ixgbe_mac_82599EB:
1489                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1490                 break;
1491
1492         default:
1493                 break;
1494         }
1495         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1496
1497         /* set up to autoclear timer, and the vectors */
1498         mask = IXGBE_EIMS_ENABLE_MASK;
1499         if (adapter->num_vfs)
1500                 mask &= ~(IXGBE_EIMS_OTHER |
1501                           IXGBE_EIMS_MAILBOX |
1502                           IXGBE_EIMS_LSC);
1503         else
1504                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1505         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1506 }
1507
1508 enum latency_range {
1509         lowest_latency = 0,
1510         low_latency = 1,
1511         bulk_latency = 2,
1512         latency_invalid = 255
1513 };
1514
1515 /**
1516  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1517  * @adapter: pointer to adapter
1518  * @eitr: eitr setting (ints per sec) to give last timeslice
1519  * @itr_setting: current throttle rate in ints/second
1520  * @packets: the number of packets during this measurement interval
1521  * @bytes: the number of bytes during this measurement interval
1522  *
1523  *      Stores a new ITR value based on packets and byte
1524  *      counts during the last interrupt.  The advantage of per interrupt
1525  *      computation is faster updates and more accurate ITR for the current
1526  *      traffic pattern.  Constants in this function were computed
1527  *      based on theoretical maximum wire speed and thresholds were set based
1528  *      on testing data as well as attempting to minimize response time
1529  *      while increasing bulk throughput.
1530  *      this functionality is controlled by the InterruptThrottleRate module
1531  *      parameter (see ixgbe_param.c)
1532  **/
1533 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1534                            u32 eitr, u8 itr_setting,
1535                            int packets, int bytes)
1536 {
1537         unsigned int retval = itr_setting;
1538         u32 timepassed_us;
1539         u64 bytes_perint;
1540
1541         if (packets == 0)
1542                 goto update_itr_done;
1543
1544
1545         /* simple throttlerate management
1546          *    0-20MB/s lowest (100000 ints/s)
1547          *   20-100MB/s low   (20000 ints/s)
1548          *  100-1249MB/s bulk (8000 ints/s)
1549          */
1550         /* what was last interrupt timeslice? */
1551         timepassed_us = 1000000/eitr;
1552         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1553
1554         switch (itr_setting) {
1555         case lowest_latency:
1556                 if (bytes_perint > adapter->eitr_low)
1557                         retval = low_latency;
1558                 break;
1559         case low_latency:
1560                 if (bytes_perint > adapter->eitr_high)
1561                         retval = bulk_latency;
1562                 else if (bytes_perint <= adapter->eitr_low)
1563                         retval = lowest_latency;
1564                 break;
1565         case bulk_latency:
1566                 if (bytes_perint <= adapter->eitr_high)
1567                         retval = low_latency;
1568                 break;
1569         }
1570
1571 update_itr_done:
1572         return retval;
1573 }
1574
1575 /**
1576  * ixgbe_write_eitr - write EITR register in hardware specific way
1577  * @q_vector: structure containing interrupt and ring information
1578  *
1579  * This function is made to be called by ethtool and by the driver
1580  * when it needs to update EITR registers at runtime.  Hardware
1581  * specific quirks/differences are taken care of here.
1582  */
1583 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1584 {
1585         struct ixgbe_adapter *adapter = q_vector->adapter;
1586         struct ixgbe_hw *hw = &adapter->hw;
1587         int v_idx = q_vector->v_idx;
1588         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1589
1590         switch (adapter->hw.mac.type) {
1591         case ixgbe_mac_82598EB:
1592                 /* must write high and low 16 bits to reset counter */
1593                 itr_reg |= (itr_reg << 16);
1594                 break;
1595         case ixgbe_mac_82599EB:
1596                 /*
1597                  * 82599 can support a value of zero, so allow it for
1598                  * max interrupt rate, but there is an errata where it can
1599                  * not be zero with RSC
1600                  */
1601                 if (itr_reg == 8 &&
1602                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1603                         itr_reg = 0;
1604
1605                 /*
1606                  * set the WDIS bit to not clear the timer bits and cause an
1607                  * immediate assertion of the interrupt
1608                  */
1609                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1610                 break;
1611         default:
1612                 break;
1613         }
1614         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1615 }
1616
1617 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1618 {
1619         struct ixgbe_adapter *adapter = q_vector->adapter;
1620         int i, r_idx;
1621         u32 new_itr;
1622         u8 current_itr, ret_itr;
1623
1624         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1625         for (i = 0; i < q_vector->txr_count; i++) {
1626                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1627                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1628                                            q_vector->tx_itr,
1629                                            tx_ring->total_packets,
1630                                            tx_ring->total_bytes);
1631                 /* if the result for this queue would decrease interrupt
1632                  * rate for this vector then use that result */
1633                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1634                                     q_vector->tx_itr - 1 : ret_itr);
1635                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1636                                       r_idx + 1);
1637         }
1638
1639         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1640         for (i = 0; i < q_vector->rxr_count; i++) {
1641                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1642                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1643                                            q_vector->rx_itr,
1644                                            rx_ring->total_packets,
1645                                            rx_ring->total_bytes);
1646                 /* if the result for this queue would decrease interrupt
1647                  * rate for this vector then use that result */
1648                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1649                                     q_vector->rx_itr - 1 : ret_itr);
1650                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1651                                       r_idx + 1);
1652         }
1653
1654         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1655
1656         switch (current_itr) {
1657         /* counts and packets in update_itr are dependent on these numbers */
1658         case lowest_latency:
1659                 new_itr = 100000;
1660                 break;
1661         case low_latency:
1662                 new_itr = 20000; /* aka hwitr = ~200 */
1663                 break;
1664         case bulk_latency:
1665         default:
1666                 new_itr = 8000;
1667                 break;
1668         }
1669
1670         if (new_itr != q_vector->eitr) {
1671                 /* do an exponential smoothing */
1672                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1673
1674                 /* save the algorithm value here, not the smoothed one */
1675                 q_vector->eitr = new_itr;
1676
1677                 ixgbe_write_eitr(q_vector);
1678         }
1679 }
1680
1681 /**
1682  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1683  * @work: pointer to work_struct containing our data
1684  **/
1685 static void ixgbe_check_overtemp_task(struct work_struct *work)
1686 {
1687         struct ixgbe_adapter *adapter = container_of(work,
1688                                                      struct ixgbe_adapter,
1689                                                      check_overtemp_task);
1690         struct ixgbe_hw *hw = &adapter->hw;
1691         u32 eicr = adapter->interrupt_event;
1692
1693         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1694                 return;
1695
1696         switch (hw->device_id) {
1697         case IXGBE_DEV_ID_82599_T3_LOM: {
1698                 u32 autoneg;
1699                 bool link_up = false;
1700
1701                 if (hw->mac.ops.check_link)
1702                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1703
1704                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1705                     (eicr & IXGBE_EICR_LSC))
1706                         /* Check if this is due to overtemp */
1707                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1708                                 break;
1709                 return;
1710         }
1711         default:
1712                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1713                         return;
1714                 break;
1715         }
1716         e_crit(drv,
1717                "Network adapter has been stopped because it has over heated. "
1718                "Restart the computer. If the problem persists, "
1719                "power off the system and replace the adapter\n");
1720         /* write to clear the interrupt */
1721         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1722 }
1723
1724 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1725 {
1726         struct ixgbe_hw *hw = &adapter->hw;
1727
1728         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1729             (eicr & IXGBE_EICR_GPI_SDP1)) {
1730                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1731                 /* write to clear the interrupt */
1732                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1733         }
1734 }
1735
1736 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1737 {
1738         struct ixgbe_hw *hw = &adapter->hw;
1739
1740         if (eicr & IXGBE_EICR_GPI_SDP2) {
1741                 /* Clear the interrupt */
1742                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1743                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1744                         schedule_work(&adapter->sfp_config_module_task);
1745         }
1746
1747         if (eicr & IXGBE_EICR_GPI_SDP1) {
1748                 /* Clear the interrupt */
1749                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1750                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1751                         schedule_work(&adapter->multispeed_fiber_task);
1752         }
1753 }
1754
1755 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1756 {
1757         struct ixgbe_hw *hw = &adapter->hw;
1758
1759         adapter->lsc_int++;
1760         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1761         adapter->link_check_timeout = jiffies;
1762         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1763                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1764                 IXGBE_WRITE_FLUSH(hw);
1765                 schedule_work(&adapter->watchdog_task);
1766         }
1767 }
1768
1769 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1770 {
1771         struct net_device *netdev = data;
1772         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1773         struct ixgbe_hw *hw = &adapter->hw;
1774         u32 eicr;
1775
1776         /*
1777          * Workaround for Silicon errata.  Use clear-by-write instead
1778          * of clear-by-read.  Reading with EICS will return the
1779          * interrupt causes without clearing, which later be done
1780          * with the write to EICR.
1781          */
1782         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1783         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1784
1785         if (eicr & IXGBE_EICR_LSC)
1786                 ixgbe_check_lsc(adapter);
1787
1788         if (eicr & IXGBE_EICR_MAILBOX)
1789                 ixgbe_msg_task(adapter);
1790
1791         switch (hw->mac.type) {
1792         case ixgbe_mac_82599EB:
1793                 /* Handle Flow Director Full threshold interrupt */
1794                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1795                         int i;
1796                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1797                         /* Disable transmits before FDIR Re-initialization */
1798                         netif_tx_stop_all_queues(netdev);
1799                         for (i = 0; i < adapter->num_tx_queues; i++) {
1800                                 struct ixgbe_ring *tx_ring =
1801                                                             adapter->tx_ring[i];
1802                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1803                                                        &tx_ring->state))
1804                                         schedule_work(&adapter->fdir_reinit_task);
1805                         }
1806                 }
1807                 ixgbe_check_sfp_event(adapter, eicr);
1808                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1809                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1810                         adapter->interrupt_event = eicr;
1811                         schedule_work(&adapter->check_overtemp_task);
1812                 }
1813                 break;
1814         default:
1815                 break;
1816         }
1817
1818         ixgbe_check_fan_failure(adapter, eicr);
1819
1820         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1821                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1822
1823         return IRQ_HANDLED;
1824 }
1825
1826 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1827                                            u64 qmask)
1828 {
1829         u32 mask;
1830         struct ixgbe_hw *hw = &adapter->hw;
1831
1832         switch (hw->mac.type) {
1833         case ixgbe_mac_82598EB:
1834                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1835                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1836                 break;
1837         case ixgbe_mac_82599EB:
1838                 mask = (qmask & 0xFFFFFFFF);
1839                 if (mask)
1840                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1841                 mask = (qmask >> 32);
1842                 if (mask)
1843                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1844                 break;
1845         default:
1846                 break;
1847         }
1848         /* skip the flush */
1849 }
1850
1851 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1852                                             u64 qmask)
1853 {
1854         u32 mask;
1855         struct ixgbe_hw *hw = &adapter->hw;
1856
1857         switch (hw->mac.type) {
1858         case ixgbe_mac_82598EB:
1859                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1860                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1861                 break;
1862         case ixgbe_mac_82599EB:
1863                 mask = (qmask & 0xFFFFFFFF);
1864                 if (mask)
1865                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1866                 mask = (qmask >> 32);
1867                 if (mask)
1868                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1869                 break;
1870         default:
1871                 break;
1872         }
1873         /* skip the flush */
1874 }
1875
1876 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1877 {
1878         struct ixgbe_q_vector *q_vector = data;
1879         struct ixgbe_adapter  *adapter = q_vector->adapter;
1880         struct ixgbe_ring     *tx_ring;
1881         int i, r_idx;
1882
1883         if (!q_vector->txr_count)
1884                 return IRQ_HANDLED;
1885
1886         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1887         for (i = 0; i < q_vector->txr_count; i++) {
1888                 tx_ring = adapter->tx_ring[r_idx];
1889                 tx_ring->total_bytes = 0;
1890                 tx_ring->total_packets = 0;
1891                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1892                                       r_idx + 1);
1893         }
1894
1895         /* EIAM disabled interrupts (on this vector) for us */
1896         napi_schedule(&q_vector->napi);
1897
1898         return IRQ_HANDLED;
1899 }
1900
1901 /**
1902  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1903  * @irq: unused
1904  * @data: pointer to our q_vector struct for this interrupt vector
1905  **/
1906 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1907 {
1908         struct ixgbe_q_vector *q_vector = data;
1909         struct ixgbe_adapter  *adapter = q_vector->adapter;
1910         struct ixgbe_ring  *rx_ring;
1911         int r_idx;
1912         int i;
1913
1914 #ifdef CONFIG_IXGBE_DCA
1915         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1916                 ixgbe_update_dca(q_vector);
1917 #endif
1918
1919         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1920         for (i = 0; i < q_vector->rxr_count; i++) {
1921                 rx_ring = adapter->rx_ring[r_idx];
1922                 rx_ring->total_bytes = 0;
1923                 rx_ring->total_packets = 0;
1924                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1925                                       r_idx + 1);
1926         }
1927
1928         if (!q_vector->rxr_count)
1929                 return IRQ_HANDLED;
1930
1931         /* EIAM disabled interrupts (on this vector) for us */
1932         napi_schedule(&q_vector->napi);
1933
1934         return IRQ_HANDLED;
1935 }
1936
1937 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1938 {
1939         struct ixgbe_q_vector *q_vector = data;
1940         struct ixgbe_adapter  *adapter = q_vector->adapter;
1941         struct ixgbe_ring  *ring;
1942         int r_idx;
1943         int i;
1944
1945         if (!q_vector->txr_count && !q_vector->rxr_count)
1946                 return IRQ_HANDLED;
1947
1948         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1949         for (i = 0; i < q_vector->txr_count; i++) {
1950                 ring = adapter->tx_ring[r_idx];
1951                 ring->total_bytes = 0;
1952                 ring->total_packets = 0;
1953                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1954                                       r_idx + 1);
1955         }
1956
1957         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1958         for (i = 0; i < q_vector->rxr_count; i++) {
1959                 ring = adapter->rx_ring[r_idx];
1960                 ring->total_bytes = 0;
1961                 ring->total_packets = 0;
1962                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1963                                       r_idx + 1);
1964         }
1965
1966         /* EIAM disabled interrupts (on this vector) for us */
1967         napi_schedule(&q_vector->napi);
1968
1969         return IRQ_HANDLED;
1970 }
1971
1972 /**
1973  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1974  * @napi: napi struct with our devices info in it
1975  * @budget: amount of work driver is allowed to do this pass, in packets
1976  *
1977  * This function is optimized for cleaning one queue only on a single
1978  * q_vector!!!
1979  **/
1980 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1981 {
1982         struct ixgbe_q_vector *q_vector =
1983                                container_of(napi, struct ixgbe_q_vector, napi);
1984         struct ixgbe_adapter *adapter = q_vector->adapter;
1985         struct ixgbe_ring *rx_ring = NULL;
1986         int work_done = 0;
1987         long r_idx;
1988
1989 #ifdef CONFIG_IXGBE_DCA
1990         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1991                 ixgbe_update_dca(q_vector);
1992 #endif
1993
1994         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1995         rx_ring = adapter->rx_ring[r_idx];
1996
1997         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1998
1999         /* If all Rx work done, exit the polling mode */
2000         if (work_done < budget) {
2001                 napi_complete(napi);
2002                 if (adapter->rx_itr_setting & 1)
2003                         ixgbe_set_itr_msix(q_vector);
2004                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2005                         ixgbe_irq_enable_queues(adapter,
2006                                                 ((u64)1 << q_vector->v_idx));
2007         }
2008
2009         return work_done;
2010 }
2011
2012 /**
2013  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2014  * @napi: napi struct with our devices info in it
2015  * @budget: amount of work driver is allowed to do this pass, in packets
2016  *
2017  * This function will clean more than one rx queue associated with a
2018  * q_vector.
2019  **/
2020 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2021 {
2022         struct ixgbe_q_vector *q_vector =
2023                                container_of(napi, struct ixgbe_q_vector, napi);
2024         struct ixgbe_adapter *adapter = q_vector->adapter;
2025         struct ixgbe_ring *ring = NULL;
2026         int work_done = 0, i;
2027         long r_idx;
2028         bool tx_clean_complete = true;
2029
2030 #ifdef CONFIG_IXGBE_DCA
2031         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2032                 ixgbe_update_dca(q_vector);
2033 #endif
2034
2035         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2036         for (i = 0; i < q_vector->txr_count; i++) {
2037                 ring = adapter->tx_ring[r_idx];
2038                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2039                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2040                                       r_idx + 1);
2041         }
2042
2043         /* attempt to distribute budget to each queue fairly, but don't allow
2044          * the budget to go below 1 because we'll exit polling */
2045         budget /= (q_vector->rxr_count ?: 1);
2046         budget = max(budget, 1);
2047         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2048         for (i = 0; i < q_vector->rxr_count; i++) {
2049                 ring = adapter->rx_ring[r_idx];
2050                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2051                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2052                                       r_idx + 1);
2053         }
2054
2055         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2056         ring = adapter->rx_ring[r_idx];
2057         /* If all Rx work done, exit the polling mode */
2058         if (work_done < budget) {
2059                 napi_complete(napi);
2060                 if (adapter->rx_itr_setting & 1)
2061                         ixgbe_set_itr_msix(q_vector);
2062                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2063                         ixgbe_irq_enable_queues(adapter,
2064                                                 ((u64)1 << q_vector->v_idx));
2065                 return 0;
2066         }
2067
2068         return work_done;
2069 }
2070
2071 /**
2072  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2073  * @napi: napi struct with our devices info in it
2074  * @budget: amount of work driver is allowed to do this pass, in packets
2075  *
2076  * This function is optimized for cleaning one queue only on a single
2077  * q_vector!!!
2078  **/
2079 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2080 {
2081         struct ixgbe_q_vector *q_vector =
2082                                container_of(napi, struct ixgbe_q_vector, napi);
2083         struct ixgbe_adapter *adapter = q_vector->adapter;
2084         struct ixgbe_ring *tx_ring = NULL;
2085         int work_done = 0;
2086         long r_idx;
2087
2088 #ifdef CONFIG_IXGBE_DCA
2089         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2090                 ixgbe_update_dca(q_vector);
2091 #endif
2092
2093         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2094         tx_ring = adapter->tx_ring[r_idx];
2095
2096         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2097                 work_done = budget;
2098
2099         /* If all Tx work done, exit the polling mode */
2100         if (work_done < budget) {
2101                 napi_complete(napi);
2102                 if (adapter->tx_itr_setting & 1)
2103                         ixgbe_set_itr_msix(q_vector);
2104                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2105                         ixgbe_irq_enable_queues(adapter,
2106                                                 ((u64)1 << q_vector->v_idx));
2107         }
2108
2109         return work_done;
2110 }
2111
2112 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2113                                      int r_idx)
2114 {
2115         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2116
2117         set_bit(r_idx, q_vector->rxr_idx);
2118         q_vector->rxr_count++;
2119 }
2120
2121 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2122                                      int t_idx)
2123 {
2124         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2125
2126         set_bit(t_idx, q_vector->txr_idx);
2127         q_vector->txr_count++;
2128 }
2129
2130 /**
2131  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2132  * @adapter: board private structure to initialize
2133  * @vectors: allotted vector count for descriptor rings
2134  *
2135  * This function maps descriptor rings to the queue-specific vectors
2136  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2137  * one vector per ring/queue, but on a constrained vector budget, we
2138  * group the rings as "efficiently" as possible.  You would add new
2139  * mapping configurations in here.
2140  **/
2141 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2142                                       int vectors)
2143 {
2144         int v_start = 0;
2145         int rxr_idx = 0, txr_idx = 0;
2146         int rxr_remaining = adapter->num_rx_queues;
2147         int txr_remaining = adapter->num_tx_queues;
2148         int i, j;
2149         int rqpv, tqpv;
2150         int err = 0;
2151
2152         /* No mapping required if MSI-X is disabled. */
2153         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2154                 goto out;
2155
2156         /*
2157          * The ideal configuration...
2158          * We have enough vectors to map one per queue.
2159          */
2160         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2161                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2162                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2163
2164                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2165                         map_vector_to_txq(adapter, v_start, txr_idx);
2166
2167                 goto out;
2168         }
2169
2170         /*
2171          * If we don't have enough vectors for a 1-to-1
2172          * mapping, we'll have to group them so there are
2173          * multiple queues per vector.
2174          */
2175         /* Re-adjusting *qpv takes care of the remainder. */
2176         for (i = v_start; i < vectors; i++) {
2177                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2178                 for (j = 0; j < rqpv; j++) {
2179                         map_vector_to_rxq(adapter, i, rxr_idx);
2180                         rxr_idx++;
2181                         rxr_remaining--;
2182                 }
2183         }
2184         for (i = v_start; i < vectors; i++) {
2185                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2186                 for (j = 0; j < tqpv; j++) {
2187                         map_vector_to_txq(adapter, i, txr_idx);
2188                         txr_idx++;
2189                         txr_remaining--;
2190                 }
2191         }
2192
2193 out:
2194         return err;
2195 }
2196
2197 /**
2198  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2199  * @adapter: board private structure
2200  *
2201  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2202  * interrupts from the kernel.
2203  **/
2204 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2205 {
2206         struct net_device *netdev = adapter->netdev;
2207         irqreturn_t (*handler)(int, void *);
2208         int i, vector, q_vectors, err;
2209         int ri = 0, ti = 0;
2210
2211         /* Decrement for Other and TCP Timer vectors */
2212         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2213
2214         /* Map the Tx/Rx rings to the vectors we were allotted. */
2215         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2216         if (err)
2217                 goto out;
2218
2219 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2220                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2221                          &ixgbe_msix_clean_many)
2222         for (vector = 0; vector < q_vectors; vector++) {
2223                 handler = SET_HANDLER(adapter->q_vector[vector]);
2224
2225                 if (handler == &ixgbe_msix_clean_rx) {
2226                         sprintf(adapter->name[vector], "%s-%s-%d",
2227                                 netdev->name, "rx", ri++);
2228                 } else if (handler == &ixgbe_msix_clean_tx) {
2229                         sprintf(adapter->name[vector], "%s-%s-%d",
2230                                 netdev->name, "tx", ti++);
2231                 } else {
2232                         sprintf(adapter->name[vector], "%s-%s-%d",
2233                                 netdev->name, "TxRx", ri++);
2234                         ti++;
2235                 }
2236
2237                 err = request_irq(adapter->msix_entries[vector].vector,
2238                                   handler, 0, adapter->name[vector],
2239                                   adapter->q_vector[vector]);
2240                 if (err) {
2241                         e_err(probe, "request_irq failed for MSIX interrupt "
2242                               "Error: %d\n", err);
2243                         goto free_queue_irqs;
2244                 }
2245         }
2246
2247         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2248         err = request_irq(adapter->msix_entries[vector].vector,
2249                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2250         if (err) {
2251                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2252                 goto free_queue_irqs;
2253         }
2254
2255         return 0;
2256
2257 free_queue_irqs:
2258         for (i = vector - 1; i >= 0; i--)
2259                 free_irq(adapter->msix_entries[--vector].vector,
2260                          adapter->q_vector[i]);
2261         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2262         pci_disable_msix(adapter->pdev);
2263         kfree(adapter->msix_entries);
2264         adapter->msix_entries = NULL;
2265 out:
2266         return err;
2267 }
2268
2269 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2270 {
2271         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2272         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2273         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2274         u32 new_itr = q_vector->eitr;
2275         u8 current_itr;
2276
2277         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2278                                             q_vector->tx_itr,
2279                                             tx_ring->total_packets,
2280                                             tx_ring->total_bytes);
2281         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2282                                             q_vector->rx_itr,
2283                                             rx_ring->total_packets,
2284                                             rx_ring->total_bytes);
2285
2286         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2287
2288         switch (current_itr) {
2289         /* counts and packets in update_itr are dependent on these numbers */
2290         case lowest_latency:
2291                 new_itr = 100000;
2292                 break;
2293         case low_latency:
2294                 new_itr = 20000; /* aka hwitr = ~200 */
2295                 break;
2296         case bulk_latency:
2297                 new_itr = 8000;
2298                 break;
2299         default:
2300                 break;
2301         }
2302
2303         if (new_itr != q_vector->eitr) {
2304                 /* do an exponential smoothing */
2305                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2306
2307                 /* save the algorithm value here */
2308                 q_vector->eitr = new_itr;
2309
2310                 ixgbe_write_eitr(q_vector);
2311         }
2312 }
2313
2314 /**
2315  * ixgbe_irq_enable - Enable default interrupt generation settings
2316  * @adapter: board private structure
2317  **/
2318 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2319                                     bool flush)
2320 {
2321         u32 mask;
2322
2323         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2324         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2325                 mask |= IXGBE_EIMS_GPI_SDP0;
2326         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2327                 mask |= IXGBE_EIMS_GPI_SDP1;
2328         switch (adapter->hw.mac.type) {
2329         case ixgbe_mac_82599EB:
2330                 mask |= IXGBE_EIMS_ECC;
2331                 mask |= IXGBE_EIMS_GPI_SDP1;
2332                 mask |= IXGBE_EIMS_GPI_SDP2;
2333                 if (adapter->num_vfs)
2334                         mask |= IXGBE_EIMS_MAILBOX;
2335                 break;
2336         default:
2337                 break;
2338         }
2339         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2340             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2341                 mask |= IXGBE_EIMS_FLOW_DIR;
2342
2343         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2344         if (queues)
2345                 ixgbe_irq_enable_queues(adapter, ~0);
2346         if (flush)
2347                 IXGBE_WRITE_FLUSH(&adapter->hw);
2348
2349         if (adapter->num_vfs > 32) {
2350                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2351                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2352         }
2353 }
2354
2355 /**
2356  * ixgbe_intr - legacy mode Interrupt Handler
2357  * @irq: interrupt number
2358  * @data: pointer to a network interface device structure
2359  **/
2360 static irqreturn_t ixgbe_intr(int irq, void *data)
2361 {
2362         struct net_device *netdev = data;
2363         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2364         struct ixgbe_hw *hw = &adapter->hw;
2365         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2366         u32 eicr;
2367
2368         /*
2369          * Workaround for silicon errata on 82598.  Mask the interrupts
2370          * before the read of EICR.
2371          */
2372         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2373
2374         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2375          * therefore no explict interrupt disable is necessary */
2376         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2377         if (!eicr) {
2378                 /*
2379                  * shared interrupt alert!
2380                  * make sure interrupts are enabled because the read will
2381                  * have disabled interrupts due to EIAM
2382                  * finish the workaround of silicon errata on 82598.  Unmask
2383                  * the interrupt that we masked before the EICR read.
2384                  */
2385                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2386                         ixgbe_irq_enable(adapter, true, true);
2387                 return IRQ_NONE;        /* Not our interrupt */
2388         }
2389
2390         if (eicr & IXGBE_EICR_LSC)
2391                 ixgbe_check_lsc(adapter);
2392
2393         switch (hw->mac.type) {
2394         case ixgbe_mac_82599EB:
2395                 ixgbe_check_sfp_event(adapter, eicr);
2396                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2397                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2398                         adapter->interrupt_event = eicr;
2399                         schedule_work(&adapter->check_overtemp_task);
2400                 }
2401                 break;
2402         default:
2403                 break;
2404         }
2405
2406         ixgbe_check_fan_failure(adapter, eicr);
2407
2408         if (napi_schedule_prep(&(q_vector->napi))) {
2409                 adapter->tx_ring[0]->total_packets = 0;
2410                 adapter->tx_ring[0]->total_bytes = 0;
2411                 adapter->rx_ring[0]->total_packets = 0;
2412                 adapter->rx_ring[0]->total_bytes = 0;
2413                 /* would disable interrupts here but EIAM disabled it */
2414                 __napi_schedule(&(q_vector->napi));
2415         }
2416
2417         /*
2418          * re-enable link(maybe) and non-queue interrupts, no flush.
2419          * ixgbe_poll will re-enable the queue interrupts
2420          */
2421
2422         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2423                 ixgbe_irq_enable(adapter, false, false);
2424
2425         return IRQ_HANDLED;
2426 }
2427
2428 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2429 {
2430         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2431
2432         for (i = 0; i < q_vectors; i++) {
2433                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2434                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2435                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2436                 q_vector->rxr_count = 0;
2437                 q_vector->txr_count = 0;
2438         }
2439 }
2440
2441 /**
2442  * ixgbe_request_irq - initialize interrupts
2443  * @adapter: board private structure
2444  *
2445  * Attempts to configure interrupts using the best available
2446  * capabilities of the hardware and kernel.
2447  **/
2448 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2449 {
2450         struct net_device *netdev = adapter->netdev;
2451         int err;
2452
2453         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2454                 err = ixgbe_request_msix_irqs(adapter);
2455         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2456                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2457                                   netdev->name, netdev);
2458         } else {
2459                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2460                                   netdev->name, netdev);
2461         }
2462
2463         if (err)
2464                 e_err(probe, "request_irq failed, Error %d\n", err);
2465
2466         return err;
2467 }
2468
2469 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2470 {
2471         struct net_device *netdev = adapter->netdev;
2472
2473         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2474                 int i, q_vectors;
2475
2476                 q_vectors = adapter->num_msix_vectors;
2477
2478                 i = q_vectors - 1;
2479                 free_irq(adapter->msix_entries[i].vector, netdev);
2480
2481                 i--;
2482                 for (; i >= 0; i--) {
2483                         free_irq(adapter->msix_entries[i].vector,
2484                                  adapter->q_vector[i]);
2485                 }
2486
2487                 ixgbe_reset_q_vectors(adapter);
2488         } else {
2489                 free_irq(adapter->pdev->irq, netdev);
2490         }
2491 }
2492
2493 /**
2494  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2495  * @adapter: board private structure
2496  **/
2497 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2498 {
2499         switch (adapter->hw.mac.type) {
2500         case ixgbe_mac_82598EB:
2501                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2502                 break;
2503         case ixgbe_mac_82599EB:
2504                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2505                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2506                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2507                 if (adapter->num_vfs > 32)
2508                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2509                 break;
2510         default:
2511                 break;
2512         }
2513         IXGBE_WRITE_FLUSH(&adapter->hw);
2514         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2515                 int i;
2516                 for (i = 0; i < adapter->num_msix_vectors; i++)
2517                         synchronize_irq(adapter->msix_entries[i].vector);
2518         } else {
2519                 synchronize_irq(adapter->pdev->irq);
2520         }
2521 }
2522
2523 /**
2524  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2525  *
2526  **/
2527 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2528 {
2529         struct ixgbe_hw *hw = &adapter->hw;
2530
2531         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2532                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2533
2534         ixgbe_set_ivar(adapter, 0, 0, 0);
2535         ixgbe_set_ivar(adapter, 1, 0, 0);
2536
2537         map_vector_to_rxq(adapter, 0, 0);
2538         map_vector_to_txq(adapter, 0, 0);
2539
2540         e_info(hw, "Legacy interrupt IVAR setup done\n");
2541 }
2542
2543 /**
2544  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2545  * @adapter: board private structure
2546  * @ring: structure containing ring specific data
2547  *
2548  * Configure the Tx descriptor ring after a reset.
2549  **/
2550 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2551                              struct ixgbe_ring *ring)
2552 {
2553         struct ixgbe_hw *hw = &adapter->hw;
2554         u64 tdba = ring->dma;
2555         int wait_loop = 10;
2556         u32 txdctl;
2557         u8 reg_idx = ring->reg_idx;
2558
2559         /* disable queue to avoid issues while updating state */
2560         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2561         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2562                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2563         IXGBE_WRITE_FLUSH(hw);
2564
2565         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2566                         (tdba & DMA_BIT_MASK(32)));
2567         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2568         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2569                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2570         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2571         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2572         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2573
2574         /* configure fetching thresholds */
2575         if (adapter->rx_itr_setting == 0) {
2576                 /* cannot set wthresh when itr==0 */
2577                 txdctl &= ~0x007F0000;
2578         } else {
2579                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2580                 txdctl |= (8 << 16);
2581         }
2582         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2583                 /* PThresh workaround for Tx hang with DFP enabled. */
2584                 txdctl |= 32;
2585         }
2586
2587         /* reinitialize flowdirector state */
2588         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2589             adapter->atr_sample_rate) {
2590                 ring->atr_sample_rate = adapter->atr_sample_rate;
2591                 ring->atr_count = 0;
2592                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2593         } else {
2594                 ring->atr_sample_rate = 0;
2595         }
2596
2597         /* enable queue */
2598         txdctl |= IXGBE_TXDCTL_ENABLE;
2599         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2600
2601         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2602         if (hw->mac.type == ixgbe_mac_82598EB &&
2603             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2604                 return;
2605
2606         /* poll to verify queue is enabled */
2607         do {
2608                 msleep(1);
2609                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2610         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2611         if (!wait_loop)
2612                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2613 }
2614
2615 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2616 {
2617         struct ixgbe_hw *hw = &adapter->hw;
2618         u32 rttdcs;
2619         u32 mask;
2620
2621         if (hw->mac.type == ixgbe_mac_82598EB)
2622                 return;
2623
2624         /* disable the arbiter while setting MTQC */
2625         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2626         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2627         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2628
2629         /* set transmit pool layout */
2630         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2631         switch (adapter->flags & mask) {
2632
2633         case (IXGBE_FLAG_SRIOV_ENABLED):
2634                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2635                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2636                 break;
2637
2638         case (IXGBE_FLAG_DCB_ENABLED):
2639                 /* We enable 8 traffic classes, DCB only */
2640                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2641                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2642                 break;
2643
2644         default:
2645                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2646                 break;
2647         }
2648
2649         /* re-enable the arbiter */
2650         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2651         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2652 }
2653
2654 /**
2655  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2656  * @adapter: board private structure
2657  *
2658  * Configure the Tx unit of the MAC after a reset.
2659  **/
2660 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2661 {
2662         struct ixgbe_hw *hw = &adapter->hw;
2663         u32 dmatxctl;
2664         u32 i;
2665
2666         ixgbe_setup_mtqc(adapter);
2667
2668         if (hw->mac.type != ixgbe_mac_82598EB) {
2669                 /* DMATXCTL.EN must be before Tx queues are enabled */
2670                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2671                 dmatxctl |= IXGBE_DMATXCTL_TE;
2672                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2673         }
2674
2675         /* Setup the HW Tx Head and Tail descriptor pointers */
2676         for (i = 0; i < adapter->num_tx_queues; i++)
2677                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2678 }
2679
2680 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2681
2682 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2683                                    struct ixgbe_ring *rx_ring)
2684 {
2685         u32 srrctl;
2686         u8 reg_idx = rx_ring->reg_idx;
2687
2688         switch (adapter->hw.mac.type) {
2689         case ixgbe_mac_82598EB: {
2690                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2691                 const int mask = feature[RING_F_RSS].mask;
2692                 reg_idx = reg_idx & mask;
2693         }
2694                 break;
2695         case ixgbe_mac_82599EB:
2696         default:
2697                 break;
2698         }
2699
2700         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2701
2702         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2703         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2704         if (adapter->num_vfs)
2705                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2706
2707         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2708                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2709
2710         if (ring_is_ps_enabled(rx_ring)) {
2711 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2712                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2713 #else
2714                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2715 #endif
2716                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2717         } else {
2718                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2719                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2720                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2721         }
2722
2723         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2724 }
2725
2726 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2727 {
2728         struct ixgbe_hw *hw = &adapter->hw;
2729         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2730                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2731                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2732         u32 mrqc = 0, reta = 0;
2733         u32 rxcsum;
2734         int i, j;
2735         int mask;
2736
2737         /* Fill out hash function seeds */
2738         for (i = 0; i < 10; i++)
2739                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2740
2741         /* Fill out redirection table */
2742         for (i = 0, j = 0; i < 128; i++, j++) {
2743                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2744                         j = 0;
2745                 /* reta = 4-byte sliding window of
2746                  * 0x00..(indices-1)(indices-1)00..etc. */
2747                 reta = (reta << 8) | (j * 0x11);
2748                 if ((i & 3) == 3)
2749                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2750         }
2751
2752         /* Disable indicating checksum in descriptor, enables RSS hash */
2753         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2754         rxcsum |= IXGBE_RXCSUM_PCSD;
2755         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2756
2757         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2758                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2759         else
2760                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2761 #ifdef CONFIG_IXGBE_DCB
2762                                          | IXGBE_FLAG_DCB_ENABLED
2763 #endif
2764                                          | IXGBE_FLAG_SRIOV_ENABLED
2765                                         );
2766
2767         switch (mask) {
2768         case (IXGBE_FLAG_RSS_ENABLED):
2769                 mrqc = IXGBE_MRQC_RSSEN;
2770                 break;
2771         case (IXGBE_FLAG_SRIOV_ENABLED):
2772                 mrqc = IXGBE_MRQC_VMDQEN;
2773                 break;
2774 #ifdef CONFIG_IXGBE_DCB
2775         case (IXGBE_FLAG_DCB_ENABLED):
2776                 mrqc = IXGBE_MRQC_RT8TCEN;
2777                 break;
2778 #endif /* CONFIG_IXGBE_DCB */
2779         default:
2780                 break;
2781         }
2782
2783         /* Perform hash on these packet types */
2784         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2785               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2786               | IXGBE_MRQC_RSS_FIELD_IPV6
2787               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2788
2789         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2790 }
2791
2792 /**
2793  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2794  * @adapter:    address of board private structure
2795  * @index:      index of ring to set
2796  **/
2797 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2798                                    struct ixgbe_ring *ring)
2799 {
2800         struct ixgbe_hw *hw = &adapter->hw;
2801         u32 rscctrl;
2802         int rx_buf_len;
2803         u8 reg_idx = ring->reg_idx;
2804
2805         if (!ring_is_rsc_enabled(ring))
2806                 return;
2807
2808         rx_buf_len = ring->rx_buf_len;
2809         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2810         rscctrl |= IXGBE_RSCCTL_RSCEN;
2811         /*
2812          * we must limit the number of descriptors so that the
2813          * total size of max desc * buf_len is not greater
2814          * than 65535
2815          */
2816         if (ring_is_ps_enabled(ring)) {
2817 #if (MAX_SKB_FRAGS > 16)
2818                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2819 #elif (MAX_SKB_FRAGS > 8)
2820                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2821 #elif (MAX_SKB_FRAGS > 4)
2822                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2823 #else
2824                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2825 #endif
2826         } else {
2827                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2828                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2829                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2830                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2831                 else
2832                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2833         }
2834         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2835 }
2836
2837 /**
2838  *  ixgbe_set_uta - Set unicast filter table address
2839  *  @adapter: board private structure
2840  *
2841  *  The unicast table address is a register array of 32-bit registers.
2842  *  The table is meant to be used in a way similar to how the MTA is used
2843  *  however due to certain limitations in the hardware it is necessary to
2844  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2845  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2846  **/
2847 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2848 {
2849         struct ixgbe_hw *hw = &adapter->hw;
2850         int i;
2851
2852         /* The UTA table only exists on 82599 hardware and newer */
2853         if (hw->mac.type < ixgbe_mac_82599EB)
2854                 return;
2855
2856         /* we only need to do this if VMDq is enabled */
2857         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2858                 return;
2859
2860         for (i = 0; i < 128; i++)
2861                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2862 }
2863
2864 #define IXGBE_MAX_RX_DESC_POLL 10
2865 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2866                                        struct ixgbe_ring *ring)
2867 {
2868         struct ixgbe_hw *hw = &adapter->hw;
2869         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2870         u32 rxdctl;
2871         u8 reg_idx = ring->reg_idx;
2872
2873         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2874         if (hw->mac.type == ixgbe_mac_82598EB &&
2875             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2876                 return;
2877
2878         do {
2879                 msleep(1);
2880                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2881         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2882
2883         if (!wait_loop) {
2884                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2885                       "the polling period\n", reg_idx);
2886         }
2887 }
2888
2889 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2890                              struct ixgbe_ring *ring)
2891 {
2892         struct ixgbe_hw *hw = &adapter->hw;
2893         u64 rdba = ring->dma;
2894         u32 rxdctl;
2895         u8 reg_idx = ring->reg_idx;
2896
2897         /* disable queue to avoid issues while updating state */
2898         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2899         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2900                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2901         IXGBE_WRITE_FLUSH(hw);
2902
2903         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2904         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2905         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2906                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2907         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2908         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2909         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2910
2911         ixgbe_configure_srrctl(adapter, ring);
2912         ixgbe_configure_rscctl(adapter, ring);
2913
2914         if (hw->mac.type == ixgbe_mac_82598EB) {
2915                 /*
2916                  * enable cache line friendly hardware writes:
2917                  * PTHRESH=32 descriptors (half the internal cache),
2918                  * this also removes ugly rx_no_buffer_count increment
2919                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2920                  * WTHRESH=8 burst writeback up to two cache lines
2921                  */
2922                 rxdctl &= ~0x3FFFFF;
2923                 rxdctl |=  0x080420;
2924         }
2925
2926         /* enable receive descriptor ring */
2927         rxdctl |= IXGBE_RXDCTL_ENABLE;
2928         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2929
2930         ixgbe_rx_desc_queue_enable(adapter, ring);
2931         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2932 }
2933
2934 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2935 {
2936         struct ixgbe_hw *hw = &adapter->hw;
2937         int p;
2938
2939         /* PSRTYPE must be initialized in non 82598 adapters */
2940         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2941                       IXGBE_PSRTYPE_UDPHDR |
2942                       IXGBE_PSRTYPE_IPV4HDR |
2943                       IXGBE_PSRTYPE_L2HDR |
2944                       IXGBE_PSRTYPE_IPV6HDR;
2945
2946         if (hw->mac.type == ixgbe_mac_82598EB)
2947                 return;
2948
2949         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2950                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2951
2952         for (p = 0; p < adapter->num_rx_pools; p++)
2953                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2954                                 psrtype);
2955 }
2956
2957 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2958 {
2959         struct ixgbe_hw *hw = &adapter->hw;
2960         u32 gcr_ext;
2961         u32 vt_reg_bits;
2962         u32 reg_offset, vf_shift;
2963         u32 vmdctl;
2964
2965         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2966                 return;
2967
2968         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2969         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2970         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2971         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2972
2973         vf_shift = adapter->num_vfs % 32;
2974         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2975
2976         /* Enable only the PF's pool for Tx/Rx */
2977         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2978         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2979         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2980         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2981         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2982
2983         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2984         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2985
2986         /*
2987          * Set up VF register offsets for selected VT Mode,
2988          * i.e. 32 or 64 VFs for SR-IOV
2989          */
2990         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2991         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2992         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2993         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2994
2995         /* enable Tx loopback for VF/PF communication */
2996         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2997 }
2998
2999 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3000 {
3001         struct ixgbe_hw *hw = &adapter->hw;
3002         struct net_device *netdev = adapter->netdev;
3003         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3004         int rx_buf_len;
3005         struct ixgbe_ring *rx_ring;
3006         int i;
3007         u32 mhadd, hlreg0;
3008
3009         /* Decide whether to use packet split mode or not */
3010         /* Do not use packet split if we're in SR-IOV Mode */
3011         if (!adapter->num_vfs)
3012                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3013
3014         /* Set the RX buffer length according to the mode */
3015         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3016                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3017         } else {
3018                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3019                     (netdev->mtu <= ETH_DATA_LEN))
3020                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3021                 else
3022                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3023         }
3024
3025 #ifdef IXGBE_FCOE
3026         /* adjust max frame to be able to do baby jumbo for FCoE */
3027         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3028             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3029                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3030
3031 #endif /* IXGBE_FCOE */
3032         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3033         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3034                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3035                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3036
3037                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3038         }
3039
3040         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3041         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3042         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3043         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3044
3045         /*
3046          * Setup the HW Rx Head and Tail Descriptor Pointers and
3047          * the Base and Length of the Rx Descriptor Ring
3048          */
3049         for (i = 0; i < adapter->num_rx_queues; i++) {
3050                 rx_ring = adapter->rx_ring[i];
3051                 rx_ring->rx_buf_len = rx_buf_len;
3052
3053                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3054                         set_ring_ps_enabled(rx_ring);
3055                 else
3056                         clear_ring_ps_enabled(rx_ring);
3057
3058                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3059                         set_ring_rsc_enabled(rx_ring);
3060                 else
3061                         clear_ring_rsc_enabled(rx_ring);
3062
3063 #ifdef IXGBE_FCOE
3064                 if (netdev->features & NETIF_F_FCOE_MTU) {
3065                         struct ixgbe_ring_feature *f;
3066                         f = &adapter->ring_feature[RING_F_FCOE];
3067                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3068                                 clear_ring_ps_enabled(rx_ring);
3069                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3070                                         rx_ring->rx_buf_len =
3071                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3072                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3073                                    !ring_is_ps_enabled(rx_ring)) {
3074                                 rx_ring->rx_buf_len =
3075                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3076                         }
3077                 }
3078 #endif /* IXGBE_FCOE */
3079         }
3080 }
3081
3082 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3083 {
3084         struct ixgbe_hw *hw = &adapter->hw;
3085         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3086
3087         switch (hw->mac.type) {
3088         case ixgbe_mac_82598EB:
3089                 /*
3090                  * For VMDq support of different descriptor types or
3091                  * buffer sizes through the use of multiple SRRCTL
3092                  * registers, RDRXCTL.MVMEN must be set to 1
3093                  *
3094                  * also, the manual doesn't mention it clearly but DCA hints
3095                  * will only use queue 0's tags unless this bit is set.  Side
3096                  * effects of setting this bit are only that SRRCTL must be
3097                  * fully programmed [0..15]
3098                  */
3099                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3100                 break;
3101         case ixgbe_mac_82599EB:
3102                 /* Disable RSC for ACK packets */
3103                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3104                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3105                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3106                 /* hardware requires some bits to be set by default */
3107                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3108                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3109                 break;
3110         default:
3111                 /* We should do nothing since we don't know this hardware */
3112                 return;
3113         }
3114
3115         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3116 }
3117
3118 /**
3119  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3120  * @adapter: board private structure
3121  *
3122  * Configure the Rx unit of the MAC after a reset.
3123  **/
3124 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3125 {
3126         struct ixgbe_hw *hw = &adapter->hw;
3127         int i;
3128         u32 rxctrl;
3129
3130         /* disable receives while setting up the descriptors */
3131         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3132         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3133
3134         ixgbe_setup_psrtype(adapter);
3135         ixgbe_setup_rdrxctl(adapter);
3136
3137         /* Program registers for the distribution of queues */
3138         ixgbe_setup_mrqc(adapter);
3139
3140         ixgbe_set_uta(adapter);
3141
3142         /* set_rx_buffer_len must be called before ring initialization */
3143         ixgbe_set_rx_buffer_len(adapter);
3144
3145         /*
3146          * Setup the HW Rx Head and Tail Descriptor Pointers and
3147          * the Base and Length of the Rx Descriptor Ring
3148          */
3149         for (i = 0; i < adapter->num_rx_queues; i++)
3150                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3151
3152         /* disable drop enable for 82598 parts */
3153         if (hw->mac.type == ixgbe_mac_82598EB)
3154                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3155
3156         /* enable all receives */
3157         rxctrl |= IXGBE_RXCTRL_RXEN;
3158         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3159 }
3160
3161 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3162 {
3163         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3164         struct ixgbe_hw *hw = &adapter->hw;
3165         int pool_ndx = adapter->num_vfs;
3166
3167         /* add VID to filter table */
3168         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3169         set_bit(vid, adapter->active_vlans);
3170 }
3171
3172 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3173 {
3174         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3175         struct ixgbe_hw *hw = &adapter->hw;
3176         int pool_ndx = adapter->num_vfs;
3177
3178         /* remove VID from filter table */
3179         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3180         clear_bit(vid, adapter->active_vlans);
3181 }
3182
3183 /**
3184  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3185  * @adapter: driver data
3186  */
3187 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3188 {
3189         struct ixgbe_hw *hw = &adapter->hw;
3190         u32 vlnctrl;
3191
3192         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3193         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3194         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3195 }
3196
3197 /**
3198  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3199  * @adapter: driver data
3200  */
3201 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3202 {
3203         struct ixgbe_hw *hw = &adapter->hw;
3204         u32 vlnctrl;
3205
3206         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3207         vlnctrl |= IXGBE_VLNCTRL_VFE;
3208         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3209         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3210 }
3211
3212 /**
3213  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3214  * @adapter: driver data
3215  */
3216 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3217 {
3218         struct ixgbe_hw *hw = &adapter->hw;
3219         u32 vlnctrl;
3220         int i, j;
3221
3222         switch (hw->mac.type) {
3223         case ixgbe_mac_82598EB:
3224                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3225                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3226                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3227                 break;
3228         case ixgbe_mac_82599EB:
3229                 for (i = 0; i < adapter->num_rx_queues; i++) {
3230                         j = adapter->rx_ring[i]->reg_idx;
3231                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3232                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3233                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3234                 }
3235                 break;
3236         default:
3237                 break;
3238         }
3239 }
3240
3241 /**
3242  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3243  * @adapter: driver data
3244  */
3245 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3246 {
3247         struct ixgbe_hw *hw = &adapter->hw;
3248         u32 vlnctrl;
3249         int i, j;
3250
3251         switch (hw->mac.type) {
3252         case ixgbe_mac_82598EB:
3253                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3254                 vlnctrl |= IXGBE_VLNCTRL_VME;
3255                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3256                 break;
3257         case ixgbe_mac_82599EB:
3258                 for (i = 0; i < adapter->num_rx_queues; i++) {
3259                         j = adapter->rx_ring[i]->reg_idx;
3260                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3261                         vlnctrl |= IXGBE_RXDCTL_VME;
3262                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3263                 }
3264                 break;
3265         default:
3266                 break;
3267         }
3268 }
3269
3270 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3271 {
3272         u16 vid;
3273
3274         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3275
3276         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3277                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3278 }
3279
3280 /**
3281  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3282  * @netdev: network interface device structure
3283  *
3284  * Writes unicast address list to the RAR table.
3285  * Returns: -ENOMEM on failure/insufficient address space
3286  *                0 on no addresses written
3287  *                X on writing X addresses to the RAR table
3288  **/
3289 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3290 {
3291         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3292         struct ixgbe_hw *hw = &adapter->hw;
3293         unsigned int vfn = adapter->num_vfs;
3294         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3295         int count = 0;
3296
3297         /* return ENOMEM indicating insufficient memory for addresses */
3298         if (netdev_uc_count(netdev) > rar_entries)
3299                 return -ENOMEM;
3300
3301         if (!netdev_uc_empty(netdev) && rar_entries) {
3302                 struct netdev_hw_addr *ha;
3303                 /* return error if we do not support writing to RAR table */
3304                 if (!hw->mac.ops.set_rar)
3305                         return -ENOMEM;
3306
3307                 netdev_for_each_uc_addr(ha, netdev) {
3308                         if (!rar_entries)
3309                                 break;
3310                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3311                                             vfn, IXGBE_RAH_AV);
3312                         count++;
3313                 }
3314         }
3315         /* write the addresses in reverse order to avoid write combining */
3316         for (; rar_entries > 0 ; rar_entries--)
3317                 hw->mac.ops.clear_rar(hw, rar_entries);
3318
3319         return count;
3320 }
3321
3322 /**
3323  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3324  * @netdev: network interface device structure
3325  *
3326  * The set_rx_method entry point is called whenever the unicast/multicast
3327  * address list or the network interface flags are updated.  This routine is
3328  * responsible for configuring the hardware for proper unicast, multicast and
3329  * promiscuous mode.
3330  **/
3331 void ixgbe_set_rx_mode(struct net_device *netdev)
3332 {
3333         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3334         struct ixgbe_hw *hw = &adapter->hw;
3335         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3336         int count;
3337
3338         /* Check for Promiscuous and All Multicast modes */
3339
3340         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3341
3342         /* set all bits that we expect to always be set */
3343         fctrl |= IXGBE_FCTRL_BAM;
3344         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3345         fctrl |= IXGBE_FCTRL_PMCF;
3346
3347         /* clear the bits we are changing the status of */
3348         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3349
3350         if (netdev->flags & IFF_PROMISC) {
3351                 hw->addr_ctrl.user_set_promisc = true;
3352                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3353                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3354                 /* don't hardware filter vlans in promisc mode */
3355                 ixgbe_vlan_filter_disable(adapter);
3356         } else {
3357                 if (netdev->flags & IFF_ALLMULTI) {
3358                         fctrl |= IXGBE_FCTRL_MPE;
3359                         vmolr |= IXGBE_VMOLR_MPE;
3360                 } else {
3361                         /*
3362                          * Write addresses to the MTA, if the attempt fails
3363                          * then we should just turn on promiscous mode so
3364                          * that we can at least receive multicast traffic
3365                          */
3366                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3367                         vmolr |= IXGBE_VMOLR_ROMPE;
3368                 }
3369                 ixgbe_vlan_filter_enable(adapter);
3370                 hw->addr_ctrl.user_set_promisc = false;
3371                 /*
3372                  * Write addresses to available RAR registers, if there is not
3373                  * sufficient space to store all the addresses then enable
3374                  * unicast promiscous mode
3375                  */
3376                 count = ixgbe_write_uc_addr_list(netdev);
3377                 if (count < 0) {
3378                         fctrl |= IXGBE_FCTRL_UPE;
3379                         vmolr |= IXGBE_VMOLR_ROPE;
3380                 }
3381         }
3382
3383         if (adapter->num_vfs) {
3384                 ixgbe_restore_vf_multicasts(adapter);
3385                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3386                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3387                            IXGBE_VMOLR_ROPE);
3388                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3389         }
3390
3391         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3392
3393         if (netdev->features & NETIF_F_HW_VLAN_RX)
3394                 ixgbe_vlan_strip_enable(adapter);
3395         else
3396                 ixgbe_vlan_strip_disable(adapter);
3397 }
3398
3399 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3400 {
3401         int q_idx;
3402         struct ixgbe_q_vector *q_vector;
3403         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3404
3405         /* legacy and MSI only use one vector */
3406         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3407                 q_vectors = 1;
3408
3409         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3410                 struct napi_struct *napi;
3411                 q_vector = adapter->q_vector[q_idx];
3412                 napi = &q_vector->napi;
3413                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3414                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3415                                 if (q_vector->txr_count == 1)
3416                                         napi->poll = &ixgbe_clean_txonly;
3417                                 else if (q_vector->rxr_count == 1)
3418                                         napi->poll = &ixgbe_clean_rxonly;
3419                         }
3420                 }
3421
3422                 napi_enable(napi);
3423         }
3424 }
3425
3426 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3427 {
3428         int q_idx;
3429         struct ixgbe_q_vector *q_vector;
3430         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3431
3432         /* legacy and MSI only use one vector */
3433         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3434                 q_vectors = 1;
3435
3436         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3437                 q_vector = adapter->q_vector[q_idx];
3438                 napi_disable(&q_vector->napi);
3439         }
3440 }
3441
3442 #ifdef CONFIG_IXGBE_DCB
3443 /*
3444  * ixgbe_configure_dcb - Configure DCB hardware
3445  * @adapter: ixgbe adapter struct
3446  *
3447  * This is called by the driver on open to configure the DCB hardware.
3448  * This is also called by the gennetlink interface when reconfiguring
3449  * the DCB state.
3450  */
3451 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3452 {
3453         struct ixgbe_hw *hw = &adapter->hw;
3454         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3455
3456         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3457                 if (hw->mac.type == ixgbe_mac_82598EB)
3458                         netif_set_gso_max_size(adapter->netdev, 65536);
3459                 return;
3460         }
3461
3462         if (hw->mac.type == ixgbe_mac_82598EB)
3463                 netif_set_gso_max_size(adapter->netdev, 32768);
3464
3465 #ifdef CONFIG_FCOE
3466         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3467                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3468 #endif
3469
3470         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3471                                         DCB_TX_CONFIG);
3472         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3473                                         DCB_RX_CONFIG);
3474
3475         /* Enable VLAN tag insert/strip */
3476         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3477
3478         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3479
3480         /* reconfigure the hardware */
3481         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3482 }
3483
3484 #endif
3485 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3486 {
3487         struct net_device *netdev = adapter->netdev;
3488         struct ixgbe_hw *hw = &adapter->hw;
3489         int i;
3490
3491 #ifdef CONFIG_IXGBE_DCB
3492         ixgbe_configure_dcb(adapter);
3493 #endif
3494
3495         ixgbe_set_rx_mode(netdev);
3496         ixgbe_restore_vlan(adapter);
3497
3498 #ifdef IXGBE_FCOE
3499         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3500                 ixgbe_configure_fcoe(adapter);
3501
3502 #endif /* IXGBE_FCOE */
3503         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3504                 for (i = 0; i < adapter->num_tx_queues; i++)
3505                         adapter->tx_ring[i]->atr_sample_rate =
3506                                                        adapter->atr_sample_rate;
3507                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3508         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3509                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3510         }
3511         ixgbe_configure_virtualization(adapter);
3512
3513         ixgbe_configure_tx(adapter);
3514         ixgbe_configure_rx(adapter);
3515 }
3516
3517 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3518 {
3519         switch (hw->phy.type) {
3520         case ixgbe_phy_sfp_avago:
3521         case ixgbe_phy_sfp_ftl:
3522         case ixgbe_phy_sfp_intel:
3523         case ixgbe_phy_sfp_unknown:
3524         case ixgbe_phy_sfp_passive_tyco:
3525         case ixgbe_phy_sfp_passive_unknown:
3526         case ixgbe_phy_sfp_active_unknown:
3527         case ixgbe_phy_sfp_ftl_active:
3528                 return true;
3529         default:
3530                 return false;
3531         }
3532 }
3533
3534 /**
3535  * ixgbe_sfp_link_config - set up SFP+ link
3536  * @adapter: pointer to private adapter struct
3537  **/
3538 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3539 {
3540         struct ixgbe_hw *hw = &adapter->hw;
3541
3542                 if (hw->phy.multispeed_fiber) {
3543                         /*
3544                          * In multispeed fiber setups, the device may not have
3545                          * had a physical connection when the driver loaded.
3546                          * If that's the case, the initial link configuration
3547                          * couldn't get the MAC into 10G or 1G mode, so we'll
3548                          * never have a link status change interrupt fire.
3549                          * We need to try and force an autonegotiation
3550                          * session, then bring up link.
3551                          */
3552                         hw->mac.ops.setup_sfp(hw);
3553                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3554                                 schedule_work(&adapter->multispeed_fiber_task);
3555                 } else {
3556                         /*
3557                          * Direct Attach Cu and non-multispeed fiber modules
3558                          * still need to be configured properly prior to
3559                          * attempting link.
3560                          */
3561                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3562                                 schedule_work(&adapter->sfp_config_module_task);
3563                 }
3564 }
3565
3566 /**
3567  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3568  * @hw: pointer to private hardware struct
3569  *
3570  * Returns 0 on success, negative on failure
3571  **/
3572 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3573 {
3574         u32 autoneg;
3575         bool negotiation, link_up = false;
3576         u32 ret = IXGBE_ERR_LINK_SETUP;
3577
3578         if (hw->mac.ops.check_link)
3579                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3580
3581         if (ret)
3582                 goto link_cfg_out;
3583
3584         if (hw->mac.ops.get_link_capabilities)
3585                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3586                                                         &negotiation);
3587         if (ret)
3588                 goto link_cfg_out;
3589
3590         if (hw->mac.ops.setup_link)
3591                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3592 link_cfg_out:
3593         return ret;
3594 }
3595
3596 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3597 {
3598         struct ixgbe_hw *hw = &adapter->hw;
3599         u32 gpie = 0;
3600
3601         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3602                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3603                        IXGBE_GPIE_OCD;
3604                 gpie |= IXGBE_GPIE_EIAME;
3605                 /*
3606                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3607                  * this saves a register write for every interrupt
3608                  */
3609                 switch (hw->mac.type) {
3610                 case ixgbe_mac_82598EB:
3611                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3612                         break;
3613                 default:
3614                 case ixgbe_mac_82599EB:
3615                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3616                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3617                         break;
3618                 }
3619         } else {
3620                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3621                  * specifically only auto mask tx and rx interrupts */
3622                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3623         }
3624
3625         /* XXX: to interrupt immediately for EICS writes, enable this */
3626         /* gpie |= IXGBE_GPIE_EIMEN; */
3627
3628         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3629                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3630                 gpie |= IXGBE_GPIE_VTMODE_64;
3631         }
3632
3633         /* Enable fan failure interrupt */
3634         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3635                 gpie |= IXGBE_SDP1_GPIEN;
3636
3637         if (hw->mac.type == ixgbe_mac_82599EB)
3638                 gpie |= IXGBE_SDP1_GPIEN;
3639                 gpie |= IXGBE_SDP2_GPIEN;
3640
3641         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3642 }
3643
3644 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3645 {
3646         struct ixgbe_hw *hw = &adapter->hw;
3647         int err;
3648         u32 ctrl_ext;
3649
3650         ixgbe_get_hw_control(adapter);
3651         ixgbe_setup_gpie(adapter);
3652
3653         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3654                 ixgbe_configure_msix(adapter);
3655         else
3656                 ixgbe_configure_msi_and_legacy(adapter);
3657
3658         /* enable the optics */
3659         if (hw->phy.multispeed_fiber)
3660                 hw->mac.ops.enable_tx_laser(hw);
3661
3662         clear_bit(__IXGBE_DOWN, &adapter->state);
3663         ixgbe_napi_enable_all(adapter);
3664
3665         if (ixgbe_is_sfp(hw)) {
3666                 ixgbe_sfp_link_config(adapter);
3667         } else {
3668                 err = ixgbe_non_sfp_link_config(hw);
3669                 if (err)
3670                         e_err(probe, "link_config FAILED %d\n", err);
3671         }
3672
3673         /* clear any pending interrupts, may auto mask */
3674         IXGBE_READ_REG(hw, IXGBE_EICR);
3675         ixgbe_irq_enable(adapter, true, true);
3676
3677         /*
3678          * If this adapter has a fan, check to see if we had a failure
3679          * before we enabled the interrupt.
3680          */
3681         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3682                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3683                 if (esdp & IXGBE_ESDP_SDP1)
3684                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3685         }
3686
3687         /*
3688          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3689          * arrived before interrupts were enabled but after probe.  Such
3690          * devices wouldn't have their type identified yet. We need to
3691          * kick off the SFP+ module setup first, then try to bring up link.
3692          * If we're not hot-pluggable SFP+, we just need to configure link
3693          * and bring it up.
3694          */
3695         if (hw->phy.type == ixgbe_phy_unknown)
3696                 schedule_work(&adapter->sfp_config_module_task);
3697
3698         /* enable transmits */
3699         netif_tx_start_all_queues(adapter->netdev);
3700
3701         /* bring the link up in the watchdog, this could race with our first
3702          * link up interrupt but shouldn't be a problem */
3703         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3704         adapter->link_check_timeout = jiffies;
3705         mod_timer(&adapter->watchdog_timer, jiffies);
3706
3707         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3708         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3709         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3710         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3711
3712         return 0;
3713 }
3714
3715 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3716 {
3717         WARN_ON(in_interrupt());
3718         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3719                 msleep(1);
3720         ixgbe_down(adapter);
3721         /*
3722          * If SR-IOV enabled then wait a bit before bringing the adapter
3723          * back up to give the VFs time to respond to the reset.  The
3724          * two second wait is based upon the watchdog timer cycle in
3725          * the VF driver.
3726          */
3727         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3728                 msleep(2000);
3729         ixgbe_up(adapter);
3730         clear_bit(__IXGBE_RESETTING, &adapter->state);
3731 }
3732
3733 int ixgbe_up(struct ixgbe_adapter *adapter)
3734 {
3735         /* hardware has been reset, we need to reload some things */
3736         ixgbe_configure(adapter);
3737
3738         return ixgbe_up_complete(adapter);
3739 }
3740
3741 void ixgbe_reset(struct ixgbe_adapter *adapter)
3742 {
3743         struct ixgbe_hw *hw = &adapter->hw;
3744         int err;
3745
3746         err = hw->mac.ops.init_hw(hw);
3747         switch (err) {
3748         case 0:
3749         case IXGBE_ERR_SFP_NOT_PRESENT:
3750                 break;
3751         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3752                 e_dev_err("master disable timed out\n");
3753                 break;
3754         case IXGBE_ERR_EEPROM_VERSION:
3755                 /* We are running on a pre-production device, log a warning */
3756                 e_dev_warn("This device is a pre-production adapter/LOM. "
3757                            "Please be aware there may be issuesassociated with "
3758                            "your hardware.  If you are experiencing problems "
3759                            "please contact your Intel or hardware "
3760                            "representative who provided you with this "
3761                            "hardware.\n");
3762                 break;
3763         default:
3764                 e_dev_err("Hardware Error: %d\n", err);
3765         }
3766
3767         /* reprogram the RAR[0] in case user changed it. */
3768         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3769                             IXGBE_RAH_AV);
3770 }
3771
3772 /**
3773  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3774  * @rx_ring: ring to free buffers from
3775  **/
3776 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3777 {
3778         struct device *dev = rx_ring->dev;
3779         unsigned long size;
3780         u16 i;
3781
3782         /* ring already cleared, nothing to do */
3783         if (!rx_ring->rx_buffer_info)
3784                 return;
3785
3786         /* Free all the Rx ring sk_buffs */
3787         for (i = 0; i < rx_ring->count; i++) {
3788                 struct ixgbe_rx_buffer *rx_buffer_info;
3789
3790                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3791                 if (rx_buffer_info->dma) {
3792                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3793                                          rx_ring->rx_buf_len,
3794                                          DMA_FROM_DEVICE);
3795                         rx_buffer_info->dma = 0;
3796                 }
3797                 if (rx_buffer_info->skb) {
3798                         struct sk_buff *skb = rx_buffer_info->skb;
3799                         rx_buffer_info->skb = NULL;
3800                         do {
3801                                 struct sk_buff *this = skb;
3802                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3803                                         dma_unmap_single(dev,
3804                                                          IXGBE_RSC_CB(this)->dma,
3805                                                          rx_ring->rx_buf_len,
3806                                                          DMA_FROM_DEVICE);
3807                                         IXGBE_RSC_CB(this)->dma = 0;
3808                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3809                                 }
3810                                 skb = skb->prev;
3811                                 dev_kfree_skb(this);
3812                         } while (skb);
3813                 }
3814                 if (!rx_buffer_info->page)
3815                         continue;
3816                 if (rx_buffer_info->page_dma) {
3817                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3818                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3819                         rx_buffer_info->page_dma = 0;
3820                 }
3821                 put_page(rx_buffer_info->page);
3822                 rx_buffer_info->page = NULL;
3823                 rx_buffer_info->page_offset = 0;
3824         }
3825
3826         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3827         memset(rx_ring->rx_buffer_info, 0, size);
3828
3829         /* Zero out the descriptor ring */
3830         memset(rx_ring->desc, 0, rx_ring->size);
3831
3832         rx_ring->next_to_clean = 0;
3833         rx_ring->next_to_use = 0;
3834 }
3835
3836 /**
3837  * ixgbe_clean_tx_ring - Free Tx Buffers
3838  * @tx_ring: ring to be cleaned
3839  **/
3840 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3841 {
3842         struct ixgbe_tx_buffer *tx_buffer_info;
3843         unsigned long size;
3844         u16 i;
3845
3846         /* ring already cleared, nothing to do */
3847         if (!tx_ring->tx_buffer_info)
3848                 return;
3849
3850         /* Free all the Tx ring sk_buffs */
3851         for (i = 0; i < tx_ring->count; i++) {
3852                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3853                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3854         }
3855
3856         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3857         memset(tx_ring->tx_buffer_info, 0, size);
3858
3859         /* Zero out the descriptor ring */
3860         memset(tx_ring->desc, 0, tx_ring->size);
3861
3862         tx_ring->next_to_use = 0;
3863         tx_ring->next_to_clean = 0;
3864 }
3865
3866 /**
3867  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3868  * @adapter: board private structure
3869  **/
3870 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3871 {
3872         int i;
3873
3874         for (i = 0; i < adapter->num_rx_queues; i++)
3875                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3876 }
3877
3878 /**
3879  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3880  * @adapter: board private structure
3881  **/
3882 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3883 {
3884         int i;
3885
3886         for (i = 0; i < adapter->num_tx_queues; i++)
3887                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3888 }
3889
3890 void ixgbe_down(struct ixgbe_adapter *adapter)
3891 {
3892         struct net_device *netdev = adapter->netdev;
3893         struct ixgbe_hw *hw = &adapter->hw;
3894         u32 rxctrl;
3895         u32 txdctl;
3896         int i;
3897         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3898
3899         /* signal that we are down to the interrupt handler */
3900         set_bit(__IXGBE_DOWN, &adapter->state);
3901
3902         /* disable receive for all VFs and wait one second */
3903         if (adapter->num_vfs) {
3904                 /* ping all the active vfs to let them know we are going down */
3905                 ixgbe_ping_all_vfs(adapter);
3906
3907                 /* Disable all VFTE/VFRE TX/RX */
3908                 ixgbe_disable_tx_rx(adapter);
3909
3910                 /* Mark all the VFs as inactive */
3911                 for (i = 0 ; i < adapter->num_vfs; i++)
3912                         adapter->vfinfo[i].clear_to_send = 0;
3913         }
3914
3915         /* disable receives */
3916         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3917         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3918
3919         IXGBE_WRITE_FLUSH(hw);
3920         msleep(10);
3921
3922         netif_tx_stop_all_queues(netdev);
3923
3924         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3925         del_timer_sync(&adapter->sfp_timer);
3926         del_timer_sync(&adapter->watchdog_timer);
3927         cancel_work_sync(&adapter->watchdog_task);
3928
3929         netif_carrier_off(netdev);
3930         netif_tx_disable(netdev);
3931
3932         ixgbe_irq_disable(adapter);
3933
3934         ixgbe_napi_disable_all(adapter);
3935
3936         /* Cleanup the affinity_hint CPU mask memory and callback */
3937         for (i = 0; i < num_q_vectors; i++) {
3938                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3939                 /* clear the affinity_mask in the IRQ descriptor */
3940                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3941                 /* release the CPU mask memory */
3942                 free_cpumask_var(q_vector->affinity_mask);
3943         }
3944
3945         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3946             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3947                 cancel_work_sync(&adapter->fdir_reinit_task);
3948
3949         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3950                 cancel_work_sync(&adapter->check_overtemp_task);
3951
3952         /* disable transmits in the hardware now that interrupts are off */
3953         for (i = 0; i < adapter->num_tx_queues; i++) {
3954                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
3955                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3956                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
3957                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3958         }
3959         /* Disable the Tx DMA engine on 82599 */
3960         switch (hw->mac.type) {
3961         case ixgbe_mac_82599EB:
3962                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3963                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3964                                  ~IXGBE_DMATXCTL_TE));
3965                 break;
3966         default:
3967                 break;
3968         }
3969
3970         /* power down the optics */
3971         if (hw->phy.multispeed_fiber)
3972                 hw->mac.ops.disable_tx_laser(hw);
3973
3974         /* clear n-tuple filters that are cached */
3975         ethtool_ntuple_flush(netdev);
3976
3977         if (!pci_channel_offline(adapter->pdev))
3978                 ixgbe_reset(adapter);
3979         ixgbe_clean_all_tx_rings(adapter);
3980         ixgbe_clean_all_rx_rings(adapter);
3981
3982 #ifdef CONFIG_IXGBE_DCA
3983         /* since we reset the hardware DCA settings were cleared */
3984         ixgbe_setup_dca(adapter);
3985 #endif
3986 }
3987
3988 /**
3989  * ixgbe_poll - NAPI Rx polling callback
3990  * @napi: structure for representing this polling device
3991  * @budget: how many packets driver is allowed to clean
3992  *
3993  * This function is used for legacy and MSI, NAPI mode
3994  **/
3995 static int ixgbe_poll(struct napi_struct *napi, int budget)
3996 {
3997         struct ixgbe_q_vector *q_vector =
3998                                 container_of(napi, struct ixgbe_q_vector, napi);
3999         struct ixgbe_adapter *adapter = q_vector->adapter;
4000         int tx_clean_complete, work_done = 0;
4001
4002 #ifdef CONFIG_IXGBE_DCA
4003         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4004                 ixgbe_update_dca(q_vector);
4005 #endif
4006
4007         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4008         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4009
4010         if (!tx_clean_complete)
4011                 work_done = budget;
4012
4013         /* If budget not fully consumed, exit the polling mode */
4014         if (work_done < budget) {
4015                 napi_complete(napi);
4016                 if (adapter->rx_itr_setting & 1)
4017                         ixgbe_set_itr(adapter);
4018                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4019                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4020         }
4021         return work_done;
4022 }
4023
4024 /**
4025  * ixgbe_tx_timeout - Respond to a Tx Hang
4026  * @netdev: network interface device structure
4027  **/
4028 static void ixgbe_tx_timeout(struct net_device *netdev)
4029 {
4030         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4031
4032         /* Do the reset outside of interrupt context */
4033         schedule_work(&adapter->reset_task);
4034 }
4035
4036 static void ixgbe_reset_task(struct work_struct *work)
4037 {
4038         struct ixgbe_adapter *adapter;
4039         adapter = container_of(work, struct ixgbe_adapter, reset_task);
4040
4041         /* If we're already down or resetting, just bail */
4042         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
4043             test_bit(__IXGBE_RESETTING, &adapter->state))
4044                 return;
4045
4046         adapter->tx_timeout_count++;
4047
4048         ixgbe_dump(adapter);
4049         netdev_err(adapter->netdev, "Reset adapter\n");
4050         ixgbe_reinit_locked(adapter);
4051 }
4052
4053 #ifdef CONFIG_IXGBE_DCB
4054 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4055 {
4056         bool ret = false;
4057         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4058
4059         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4060                 return ret;
4061
4062         f->mask = 0x7 << 3;
4063         adapter->num_rx_queues = f->indices;
4064         adapter->num_tx_queues = f->indices;
4065         ret = true;
4066
4067         return ret;
4068 }
4069 #endif
4070
4071 /**
4072  * ixgbe_set_rss_queues: Allocate queues for RSS
4073  * @adapter: board private structure to initialize
4074  *
4075  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4076  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4077  *
4078  **/
4079 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4080 {
4081         bool ret = false;
4082         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4083
4084         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4085                 f->mask = 0xF;
4086                 adapter->num_rx_queues = f->indices;
4087                 adapter->num_tx_queues = f->indices;
4088                 ret = true;
4089         } else {
4090                 ret = false;
4091         }
4092
4093         return ret;
4094 }
4095
4096 /**
4097  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4098  * @adapter: board private structure to initialize
4099  *
4100  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4101  * to the original CPU that initiated the Tx session.  This runs in addition
4102  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4103  * Rx load across CPUs using RSS.
4104  *
4105  **/
4106 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4107 {
4108         bool ret = false;
4109         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4110
4111         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4112         f_fdir->mask = 0;
4113
4114         /* Flow Director must have RSS enabled */
4115         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4116             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4117              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4118                 adapter->num_tx_queues = f_fdir->indices;
4119                 adapter->num_rx_queues = f_fdir->indices;
4120                 ret = true;
4121         } else {
4122                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4123                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4124         }
4125         return ret;
4126 }
4127
4128 #ifdef IXGBE_FCOE
4129 /**
4130  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4131  * @adapter: board private structure to initialize
4132  *
4133  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4134  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4135  * rx queues out of the max number of rx queues, instead, it is used as the
4136  * index of the first rx queue used by FCoE.
4137  *
4138  **/
4139 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4140 {
4141         bool ret = false;
4142         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4143
4144         f->indices = min((int)num_online_cpus(), f->indices);
4145         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4146                 adapter->num_rx_queues = 1;
4147                 adapter->num_tx_queues = 1;
4148 #ifdef CONFIG_IXGBE_DCB
4149                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4150                         e_info(probe, "FCoE enabled with DCB\n");
4151                         ixgbe_set_dcb_queues(adapter);
4152                 }
4153 #endif
4154                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4155                         e_info(probe, "FCoE enabled with RSS\n");
4156                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4157                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4158                                 ixgbe_set_fdir_queues(adapter);
4159                         else
4160                                 ixgbe_set_rss_queues(adapter);
4161                 }
4162                 /* adding FCoE rx rings to the end */
4163                 f->mask = adapter->num_rx_queues;
4164                 adapter->num_rx_queues += f->indices;
4165                 adapter->num_tx_queues += f->indices;
4166
4167                 ret = true;
4168         }
4169
4170         return ret;
4171 }
4172
4173 #endif /* IXGBE_FCOE */
4174 /**
4175  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4176  * @adapter: board private structure to initialize
4177  *
4178  * IOV doesn't actually use anything, so just NAK the
4179  * request for now and let the other queue routines
4180  * figure out what to do.
4181  */
4182 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4183 {
4184         return false;
4185 }
4186
4187 /*
4188  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4189  * @adapter: board private structure to initialize
4190  *
4191  * This is the top level queue allocation routine.  The order here is very
4192  * important, starting with the "most" number of features turned on at once,
4193  * and ending with the smallest set of features.  This way large combinations
4194  * can be allocated if they're turned on, and smaller combinations are the
4195  * fallthrough conditions.
4196  *
4197  **/
4198 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4199 {
4200         /* Start with base case */
4201         adapter->num_rx_queues = 1;
4202         adapter->num_tx_queues = 1;
4203         adapter->num_rx_pools = adapter->num_rx_queues;
4204         adapter->num_rx_queues_per_pool = 1;
4205
4206         if (ixgbe_set_sriov_queues(adapter))
4207                 goto done;
4208
4209 #ifdef IXGBE_FCOE
4210         if (ixgbe_set_fcoe_queues(adapter))
4211                 goto done;
4212
4213 #endif /* IXGBE_FCOE */
4214 #ifdef CONFIG_IXGBE_DCB
4215         if (ixgbe_set_dcb_queues(adapter))
4216                 goto done;
4217
4218 #endif
4219         if (ixgbe_set_fdir_queues(adapter))
4220                 goto done;
4221
4222         if (ixgbe_set_rss_queues(adapter))
4223                 goto done;
4224
4225         /* fallback to base case */
4226         adapter->num_rx_queues = 1;
4227         adapter->num_tx_queues = 1;
4228
4229 done:
4230         /* Notify the stack of the (possibly) reduced queue counts. */
4231         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4232         return netif_set_real_num_rx_queues(adapter->netdev,
4233                                             adapter->num_rx_queues);
4234 }
4235
4236 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4237                                        int vectors)
4238 {
4239         int err, vector_threshold;
4240
4241         /* We'll want at least 3 (vector_threshold):
4242          * 1) TxQ[0] Cleanup
4243          * 2) RxQ[0] Cleanup
4244          * 3) Other (Link Status Change, etc.)
4245          * 4) TCP Timer (optional)
4246          */
4247         vector_threshold = MIN_MSIX_COUNT;
4248
4249         /* The more we get, the more we will assign to Tx/Rx Cleanup
4250          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4251          * Right now, we simply care about how many we'll get; we'll
4252          * set them up later while requesting irq's.
4253          */
4254         while (vectors >= vector_threshold) {
4255                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4256                                       vectors);
4257                 if (!err) /* Success in acquiring all requested vectors. */
4258                         break;
4259                 else if (err < 0)
4260                         vectors = 0; /* Nasty failure, quit now */
4261                 else /* err == number of vectors we should try again with */
4262                         vectors = err;
4263         }
4264
4265         if (vectors < vector_threshold) {
4266                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4267                  * This just means we'll go with either a single MSI
4268                  * vector or fall back to legacy interrupts.
4269                  */
4270                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4271                              "Unable to allocate MSI-X interrupts\n");
4272                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4273                 kfree(adapter->msix_entries);
4274                 adapter->msix_entries = NULL;
4275         } else {
4276                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4277                 /*
4278                  * Adjust for only the vectors we'll use, which is minimum
4279                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4280                  * vectors we were allocated.
4281                  */
4282                 adapter->num_msix_vectors = min(vectors,
4283                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4284         }
4285 }
4286
4287 /**
4288  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4289  * @adapter: board private structure to initialize
4290  *
4291  * Cache the descriptor ring offsets for RSS to the assigned rings.
4292  *
4293  **/
4294 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4295 {
4296         int i;
4297
4298         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4299                 return false;
4300
4301         for (i = 0; i < adapter->num_rx_queues; i++)
4302                 adapter->rx_ring[i]->reg_idx = i;
4303         for (i = 0; i < adapter->num_tx_queues; i++)
4304                 adapter->tx_ring[i]->reg_idx = i;
4305
4306         return true;
4307 }
4308
4309 #ifdef CONFIG_IXGBE_DCB
4310 /**
4311  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4312  * @adapter: board private structure to initialize
4313  *
4314  * Cache the descriptor ring offsets for DCB to the assigned rings.
4315  *
4316  **/
4317 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4318 {
4319         int i;
4320         bool ret = false;
4321         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4322
4323         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4324                 return false;
4325
4326         /* the number of queues is assumed to be symmetric */
4327         switch (adapter->hw.mac.type) {
4328         case ixgbe_mac_82598EB:
4329                 for (i = 0; i < dcb_i; i++) {
4330                         adapter->rx_ring[i]->reg_idx = i << 3;
4331                         adapter->tx_ring[i]->reg_idx = i << 2;
4332                 }
4333                 ret = true;
4334                 break;
4335         case ixgbe_mac_82599EB:
4336                 if (dcb_i == 8) {
4337                         /*
4338                          * Tx TC0 starts at: descriptor queue 0
4339                          * Tx TC1 starts at: descriptor queue 32
4340                          * Tx TC2 starts at: descriptor queue 64
4341                          * Tx TC3 starts at: descriptor queue 80
4342                          * Tx TC4 starts at: descriptor queue 96
4343                          * Tx TC5 starts at: descriptor queue 104
4344                          * Tx TC6 starts at: descriptor queue 112
4345                          * Tx TC7 starts at: descriptor queue 120
4346                          *
4347                          * Rx TC0-TC7 are offset by 16 queues each
4348                          */
4349                         for (i = 0; i < 3; i++) {
4350                                 adapter->tx_ring[i]->reg_idx = i << 5;
4351                                 adapter->rx_ring[i]->reg_idx = i << 4;
4352                         }
4353                         for ( ; i < 5; i++) {
4354                                 adapter->tx_ring[i]->reg_idx = ((i + 2) << 4);
4355                                 adapter->rx_ring[i]->reg_idx = i << 4;
4356                         }
4357                         for ( ; i < dcb_i; i++) {
4358                                 adapter->tx_ring[i]->reg_idx = ((i + 8) << 3);
4359                                 adapter->rx_ring[i]->reg_idx = i << 4;
4360                         }
4361                         ret = true;
4362                 } else if (dcb_i == 4) {
4363                         /*
4364                          * Tx TC0 starts at: descriptor queue 0
4365                          * Tx TC1 starts at: descriptor queue 64
4366                          * Tx TC2 starts at: descriptor queue 96
4367                          * Tx TC3 starts at: descriptor queue 112
4368                          *
4369                          * Rx TC0-TC3 are offset by 32 queues each
4370                          */
4371                         adapter->tx_ring[0]->reg_idx = 0;
4372                         adapter->tx_ring[1]->reg_idx = 64;
4373                         adapter->tx_ring[2]->reg_idx = 96;
4374                         adapter->tx_ring[3]->reg_idx = 112;
4375                         for (i = 0 ; i < dcb_i; i++)
4376                                 adapter->rx_ring[i]->reg_idx = i << 5;
4377                         ret = true;
4378                 }
4379                 break;
4380         default:
4381                 break;
4382         }
4383         return ret;
4384 }
4385 #endif
4386
4387 /**
4388  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4389  * @adapter: board private structure to initialize
4390  *
4391  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4392  *
4393  **/
4394 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4395 {
4396         int i;
4397         bool ret = false;
4398
4399         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4400             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4401              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4402                 for (i = 0; i < adapter->num_rx_queues; i++)
4403                         adapter->rx_ring[i]->reg_idx = i;
4404                 for (i = 0; i < adapter->num_tx_queues; i++)
4405                         adapter->tx_ring[i]->reg_idx = i;
4406                 ret = true;
4407         }
4408
4409         return ret;
4410 }
4411
4412 #ifdef IXGBE_FCOE
4413 /**
4414  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4415  * @adapter: board private structure to initialize
4416  *
4417  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4418  *
4419  */
4420 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4421 {
4422         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4423         int i;
4424         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4425
4426         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4427                 return false;
4428
4429 #ifdef CONFIG_IXGBE_DCB
4430         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4431                 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4432
4433                 ixgbe_cache_ring_dcb(adapter);
4434                 /* find out queues in TC for FCoE */
4435                 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4436                 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4437                 /*
4438                  * In 82599, the number of Tx queues for each traffic
4439                  * class for both 8-TC and 4-TC modes are:
4440                  * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4441                  * 8 TCs:  32  32  16  16   8   8   8   8
4442                  * 4 TCs:  64  64  32  32
4443                  * We have max 8 queues for FCoE, where 8 the is
4444                  * FCoE redirection table size. If TC for FCoE is
4445                  * less than or equal to TC3, we have enough queues
4446                  * to add max of 8 queues for FCoE, so we start FCoE
4447                  * Tx queue from the next one, i.e., reg_idx + 1.
4448                  * If TC for FCoE is above TC3, implying 8 TC mode,
4449                  * and we need 8 for FCoE, we have to take all queues
4450                  * in that traffic class for FCoE.
4451                  */
4452                 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4453                         fcoe_tx_i--;
4454         }
4455 #endif /* CONFIG_IXGBE_DCB */
4456         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4457                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4458                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4459                         ixgbe_cache_ring_fdir(adapter);
4460                 else
4461                         ixgbe_cache_ring_rss(adapter);
4462
4463                 fcoe_rx_i = f->mask;
4464                 fcoe_tx_i = f->mask;
4465         }
4466         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4467                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4468                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4469         }
4470         return true;
4471 }
4472
4473 #endif /* IXGBE_FCOE */
4474 /**
4475  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4476  * @adapter: board private structure to initialize
4477  *
4478  * SR-IOV doesn't use any descriptor rings but changes the default if
4479  * no other mapping is used.
4480  *
4481  */
4482 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4483 {
4484         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4485         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4486         if (adapter->num_vfs)
4487                 return true;
4488         else
4489                 return false;
4490 }
4491
4492 /**
4493  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4494  * @adapter: board private structure to initialize
4495  *
4496  * Once we know the feature-set enabled for the device, we'll cache
4497  * the register offset the descriptor ring is assigned to.
4498  *
4499  * Note, the order the various feature calls is important.  It must start with
4500  * the "most" features enabled at the same time, then trickle down to the
4501  * least amount of features turned on at once.
4502  **/
4503 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4504 {
4505         /* start with default case */
4506         adapter->rx_ring[0]->reg_idx = 0;
4507         adapter->tx_ring[0]->reg_idx = 0;
4508
4509         if (ixgbe_cache_ring_sriov(adapter))
4510                 return;
4511
4512 #ifdef IXGBE_FCOE
4513         if (ixgbe_cache_ring_fcoe(adapter))
4514                 return;
4515
4516 #endif /* IXGBE_FCOE */
4517 #ifdef CONFIG_IXGBE_DCB
4518         if (ixgbe_cache_ring_dcb(adapter))
4519                 return;
4520
4521 #endif
4522         if (ixgbe_cache_ring_fdir(adapter))
4523                 return;
4524
4525         if (ixgbe_cache_ring_rss(adapter))
4526                 return;
4527 }
4528
4529 /**
4530  * ixgbe_alloc_queues - Allocate memory for all rings
4531  * @adapter: board private structure to initialize
4532  *
4533  * We allocate one ring per queue at run-time since we don't know the
4534  * number of queues at compile-time.  The polling_netdev array is
4535  * intended for Multiqueue, but should work fine with a single queue.
4536  **/
4537 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4538 {
4539         int i;
4540         int rx_count;
4541         int orig_node = adapter->node;
4542
4543         for (i = 0; i < adapter->num_tx_queues; i++) {
4544                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4545                 if (orig_node == -1) {
4546                         int cur_node = next_online_node(adapter->node);
4547                         if (cur_node == MAX_NUMNODES)
4548                                 cur_node = first_online_node;
4549                         adapter->node = cur_node;
4550                 }
4551                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4552                                     adapter->node);
4553                 if (!ring)
4554                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4555                 if (!ring)
4556                         goto err_tx_ring_allocation;
4557                 ring->count = adapter->tx_ring_count;
4558                 ring->queue_index = i;
4559                 ring->dev = &adapter->pdev->dev;
4560                 ring->netdev = adapter->netdev;
4561                 ring->numa_node = adapter->node;
4562
4563                 adapter->tx_ring[i] = ring;
4564         }
4565
4566         /* Restore the adapter's original node */
4567         adapter->node = orig_node;
4568
4569         rx_count = adapter->rx_ring_count;
4570         for (i = 0; i < adapter->num_rx_queues; i++) {
4571                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4572                 if (orig_node == -1) {
4573                         int cur_node = next_online_node(adapter->node);
4574                         if (cur_node == MAX_NUMNODES)
4575                                 cur_node = first_online_node;
4576                         adapter->node = cur_node;
4577                 }
4578                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4579                                     adapter->node);
4580                 if (!ring)
4581                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4582                 if (!ring)
4583                         goto err_rx_ring_allocation;
4584                 ring->count = rx_count;
4585                 ring->queue_index = i;
4586                 ring->dev = &adapter->pdev->dev;
4587                 ring->netdev = adapter->netdev;
4588                 ring->numa_node = adapter->node;
4589
4590                 adapter->rx_ring[i] = ring;
4591         }
4592
4593         /* Restore the adapter's original node */
4594         adapter->node = orig_node;
4595
4596         ixgbe_cache_ring_register(adapter);
4597
4598         return 0;
4599
4600 err_rx_ring_allocation:
4601         for (i = 0; i < adapter->num_tx_queues; i++)
4602                 kfree(adapter->tx_ring[i]);
4603 err_tx_ring_allocation:
4604         return -ENOMEM;
4605 }
4606
4607 /**
4608  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4609  * @adapter: board private structure to initialize
4610  *
4611  * Attempt to configure the interrupts using the best available
4612  * capabilities of the hardware and the kernel.
4613  **/
4614 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4615 {
4616         struct ixgbe_hw *hw = &adapter->hw;
4617         int err = 0;
4618         int vector, v_budget;
4619
4620         /*
4621          * It's easy to be greedy for MSI-X vectors, but it really
4622          * doesn't do us much good if we have a lot more vectors
4623          * than CPU's.  So let's be conservative and only ask for
4624          * (roughly) the same number of vectors as there are CPU's.
4625          */
4626         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4627                        (int)num_online_cpus()) + NON_Q_VECTORS;
4628
4629         /*
4630          * At the same time, hardware can only support a maximum of
4631          * hw.mac->max_msix_vectors vectors.  With features
4632          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4633          * descriptor queues supported by our device.  Thus, we cap it off in
4634          * those rare cases where the cpu count also exceeds our vector limit.
4635          */
4636         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4637
4638         /* A failure in MSI-X entry allocation isn't fatal, but it does
4639          * mean we disable MSI-X capabilities of the adapter. */
4640         adapter->msix_entries = kcalloc(v_budget,
4641                                         sizeof(struct msix_entry), GFP_KERNEL);
4642         if (adapter->msix_entries) {
4643                 for (vector = 0; vector < v_budget; vector++)
4644                         adapter->msix_entries[vector].entry = vector;
4645
4646                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4647
4648                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4649                         goto out;
4650         }
4651
4652         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4653         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4654         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4655         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4656         adapter->atr_sample_rate = 0;
4657         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4658                 ixgbe_disable_sriov(adapter);
4659
4660         err = ixgbe_set_num_queues(adapter);
4661         if (err)
4662                 return err;
4663
4664         err = pci_enable_msi(adapter->pdev);
4665         if (!err) {
4666                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4667         } else {
4668                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4669                              "Unable to allocate MSI interrupt, "
4670                              "falling back to legacy.  Error: %d\n", err);
4671                 /* reset err */
4672                 err = 0;
4673         }
4674
4675 out:
4676         return err;
4677 }
4678
4679 /**
4680  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4681  * @adapter: board private structure to initialize
4682  *
4683  * We allocate one q_vector per queue interrupt.  If allocation fails we
4684  * return -ENOMEM.
4685  **/
4686 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4687 {
4688         int q_idx, num_q_vectors;
4689         struct ixgbe_q_vector *q_vector;
4690         int napi_vectors;
4691         int (*poll)(struct napi_struct *, int);
4692
4693         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4694                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4695                 napi_vectors = adapter->num_rx_queues;
4696                 poll = &ixgbe_clean_rxtx_many;
4697         } else {
4698                 num_q_vectors = 1;
4699                 napi_vectors = 1;
4700                 poll = &ixgbe_poll;
4701         }
4702
4703         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4704                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4705                                         GFP_KERNEL, adapter->node);
4706                 if (!q_vector)
4707                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4708                                            GFP_KERNEL);
4709                 if (!q_vector)
4710                         goto err_out;
4711                 q_vector->adapter = adapter;
4712                 if (q_vector->txr_count && !q_vector->rxr_count)
4713                         q_vector->eitr = adapter->tx_eitr_param;
4714                 else
4715                         q_vector->eitr = adapter->rx_eitr_param;
4716                 q_vector->v_idx = q_idx;
4717                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4718                 adapter->q_vector[q_idx] = q_vector;
4719         }
4720
4721         return 0;
4722
4723 err_out:
4724         while (q_idx) {
4725                 q_idx--;
4726                 q_vector = adapter->q_vector[q_idx];
4727                 netif_napi_del(&q_vector->napi);
4728                 kfree(q_vector);
4729                 adapter->q_vector[q_idx] = NULL;
4730         }
4731         return -ENOMEM;
4732 }
4733
4734 /**
4735  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4736  * @adapter: board private structure to initialize
4737  *
4738  * This function frees the memory allocated to the q_vectors.  In addition if
4739  * NAPI is enabled it will delete any references to the NAPI struct prior
4740  * to freeing the q_vector.
4741  **/
4742 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4743 {
4744         int q_idx, num_q_vectors;
4745
4746         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4747                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4748         else
4749                 num_q_vectors = 1;
4750
4751         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4752                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4753                 adapter->q_vector[q_idx] = NULL;
4754                 netif_napi_del(&q_vector->napi);
4755                 kfree(q_vector);
4756         }
4757 }
4758
4759 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4760 {
4761         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4762                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4763                 pci_disable_msix(adapter->pdev);
4764                 kfree(adapter->msix_entries);
4765                 adapter->msix_entries = NULL;
4766         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4767                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4768                 pci_disable_msi(adapter->pdev);
4769         }
4770 }
4771
4772 /**
4773  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4774  * @adapter: board private structure to initialize
4775  *
4776  * We determine which interrupt scheme to use based on...
4777  * - Kernel support (MSI, MSI-X)
4778  *   - which can be user-defined (via MODULE_PARAM)
4779  * - Hardware queue count (num_*_queues)
4780  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4781  **/
4782 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4783 {
4784         int err;
4785
4786         /* Number of supported queues */
4787         err = ixgbe_set_num_queues(adapter);
4788         if (err)
4789                 return err;
4790
4791         err = ixgbe_set_interrupt_capability(adapter);
4792         if (err) {
4793                 e_dev_err("Unable to setup interrupt capabilities\n");
4794                 goto err_set_interrupt;
4795         }
4796
4797         err = ixgbe_alloc_q_vectors(adapter);
4798         if (err) {
4799                 e_dev_err("Unable to allocate memory for queue vectors\n");
4800                 goto err_alloc_q_vectors;
4801         }
4802
4803         err = ixgbe_alloc_queues(adapter);
4804         if (err) {
4805                 e_dev_err("Unable to allocate memory for queues\n");
4806                 goto err_alloc_queues;
4807         }
4808
4809         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4810                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4811                    adapter->num_rx_queues, adapter->num_tx_queues);
4812
4813         set_bit(__IXGBE_DOWN, &adapter->state);
4814
4815         return 0;
4816
4817 err_alloc_queues:
4818         ixgbe_free_q_vectors(adapter);
4819 err_alloc_q_vectors:
4820         ixgbe_reset_interrupt_capability(adapter);
4821 err_set_interrupt:
4822         return err;
4823 }
4824
4825 static void ring_free_rcu(struct rcu_head *head)
4826 {
4827         kfree(container_of(head, struct ixgbe_ring, rcu));
4828 }
4829
4830 /**
4831  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4832  * @adapter: board private structure to clear interrupt scheme on
4833  *
4834  * We go through and clear interrupt specific resources and reset the structure
4835  * to pre-load conditions
4836  **/
4837 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4838 {
4839         int i;
4840
4841         for (i = 0; i < adapter->num_tx_queues; i++) {
4842                 kfree(adapter->tx_ring[i]);
4843                 adapter->tx_ring[i] = NULL;
4844         }
4845         for (i = 0; i < adapter->num_rx_queues; i++) {
4846                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4847
4848                 /* ixgbe_get_stats64() might access this ring, we must wait
4849                  * a grace period before freeing it.
4850                  */
4851                 call_rcu(&ring->rcu, ring_free_rcu);
4852                 adapter->rx_ring[i] = NULL;
4853         }
4854
4855         ixgbe_free_q_vectors(adapter);
4856         ixgbe_reset_interrupt_capability(adapter);
4857 }
4858
4859 /**
4860  * ixgbe_sfp_timer - worker thread to find a missing module
4861  * @data: pointer to our adapter struct
4862  **/
4863 static void ixgbe_sfp_timer(unsigned long data)
4864 {
4865         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4866
4867         /*
4868          * Do the sfp_timer outside of interrupt context due to the
4869          * delays that sfp+ detection requires
4870          */
4871         schedule_work(&adapter->sfp_task);
4872 }
4873
4874 /**
4875  * ixgbe_sfp_task - worker thread to find a missing module
4876  * @work: pointer to work_struct containing our data
4877  **/
4878 static void ixgbe_sfp_task(struct work_struct *work)
4879 {
4880         struct ixgbe_adapter *adapter = container_of(work,
4881                                                      struct ixgbe_adapter,
4882                                                      sfp_task);
4883         struct ixgbe_hw *hw = &adapter->hw;
4884
4885         if ((hw->phy.type == ixgbe_phy_nl) &&
4886             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4887                 s32 ret = hw->phy.ops.identify_sfp(hw);
4888                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4889                         goto reschedule;
4890                 ret = hw->phy.ops.reset(hw);
4891                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4892                         e_dev_err("failed to initialize because an unsupported "
4893                                   "SFP+ module type was detected.\n");
4894                         e_dev_err("Reload the driver after installing a "
4895                                   "supported module.\n");
4896                         unregister_netdev(adapter->netdev);
4897                 } else {
4898                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4899                 }
4900                 /* don't need this routine any more */
4901                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4902         }
4903         return;
4904 reschedule:
4905         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4906                 mod_timer(&adapter->sfp_timer,
4907                           round_jiffies(jiffies + (2 * HZ)));
4908 }
4909
4910 /**
4911  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4912  * @adapter: board private structure to initialize
4913  *
4914  * ixgbe_sw_init initializes the Adapter private data structure.
4915  * Fields are initialized based on PCI device information and
4916  * OS network device settings (MTU size).
4917  **/
4918 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4919 {
4920         struct ixgbe_hw *hw = &adapter->hw;
4921         struct pci_dev *pdev = adapter->pdev;
4922         struct net_device *dev = adapter->netdev;
4923         unsigned int rss;
4924 #ifdef CONFIG_IXGBE_DCB
4925         int j;
4926         struct tc_configuration *tc;
4927 #endif
4928         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4929
4930         /* PCI config space info */
4931
4932         hw->vendor_id = pdev->vendor;
4933         hw->device_id = pdev->device;
4934         hw->revision_id = pdev->revision;
4935         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4936         hw->subsystem_device_id = pdev->subsystem_device;
4937
4938         /* Set capability flags */
4939         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4940         adapter->ring_feature[RING_F_RSS].indices = rss;
4941         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4942         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4943         switch (hw->mac.type) {
4944         case ixgbe_mac_82598EB:
4945                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4946                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4947                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4948                 break;
4949         case ixgbe_mac_82599EB:
4950                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4951                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4952                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4953                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4954                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4955                 if (dev->features & NETIF_F_NTUPLE) {
4956                         /* Flow Director perfect filter enabled */
4957                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4958                         adapter->atr_sample_rate = 0;
4959                         spin_lock_init(&adapter->fdir_perfect_lock);
4960                 } else {
4961                         /* Flow Director hash filters enabled */
4962                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4963                         adapter->atr_sample_rate = 20;
4964                 }
4965                 adapter->ring_feature[RING_F_FDIR].indices =
4966                                                          IXGBE_MAX_FDIR_INDICES;
4967                 adapter->fdir_pballoc = 0;
4968 #ifdef IXGBE_FCOE
4969                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4970                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4971                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4972 #ifdef CONFIG_IXGBE_DCB
4973                 /* Default traffic class to use for FCoE */
4974                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4975                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4976 #endif
4977 #endif /* IXGBE_FCOE */
4978                 break;
4979         default:
4980                 break;
4981         }
4982
4983 #ifdef CONFIG_IXGBE_DCB
4984         /* Configure DCB traffic classes */
4985         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4986                 tc = &adapter->dcb_cfg.tc_config[j];
4987                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4988                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4989                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4990                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4991                 tc->dcb_pfc = pfc_disabled;
4992         }
4993         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4994         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4995         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4996         adapter->dcb_cfg.pfc_mode_enable = false;
4997         adapter->dcb_cfg.round_robin_enable = false;
4998         adapter->dcb_set_bitmap = 0x00;
4999         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5000                            adapter->ring_feature[RING_F_DCB].indices);
5001
5002 #endif
5003
5004         /* default flow control settings */
5005         hw->fc.requested_mode = ixgbe_fc_full;
5006         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5007 #ifdef CONFIG_DCB
5008         adapter->last_lfc_mode = hw->fc.current_mode;
5009 #endif
5010         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5011         hw->fc.low_water = FC_LOW_WATER(max_frame);
5012         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5013         hw->fc.send_xon = true;
5014         hw->fc.disable_fc_autoneg = false;
5015
5016         /* enable itr by default in dynamic mode */
5017         adapter->rx_itr_setting = 1;
5018         adapter->rx_eitr_param = 20000;
5019         adapter->tx_itr_setting = 1;
5020         adapter->tx_eitr_param = 10000;
5021
5022         /* set defaults for eitr in MegaBytes */
5023         adapter->eitr_low = 10;
5024         adapter->eitr_high = 20;
5025
5026         /* set default ring sizes */
5027         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5028         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5029
5030         /* initialize eeprom parameters */
5031         if (ixgbe_init_eeprom_params_generic(hw)) {
5032                 e_dev_err("EEPROM initialization failed\n");
5033                 return -EIO;
5034         }
5035
5036         /* enable rx csum by default */
5037         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5038
5039         /* get assigned NUMA node */
5040         adapter->node = dev_to_node(&pdev->dev);
5041
5042         set_bit(__IXGBE_DOWN, &adapter->state);
5043
5044         return 0;
5045 }
5046
5047 /**
5048  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5049  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5050  *
5051  * Return 0 on success, negative on failure
5052  **/
5053 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5054 {
5055         struct device *dev = tx_ring->dev;
5056         int size;
5057
5058         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5059         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
5060         if (!tx_ring->tx_buffer_info)
5061                 tx_ring->tx_buffer_info = vmalloc(size);
5062         if (!tx_ring->tx_buffer_info)
5063                 goto err;
5064         memset(tx_ring->tx_buffer_info, 0, size);
5065
5066         /* round up to nearest 4K */
5067         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5068         tx_ring->size = ALIGN(tx_ring->size, 4096);
5069
5070         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5071                                            &tx_ring->dma, GFP_KERNEL);
5072         if (!tx_ring->desc)
5073                 goto err;
5074
5075         tx_ring->next_to_use = 0;
5076         tx_ring->next_to_clean = 0;
5077         tx_ring->work_limit = tx_ring->count;
5078         return 0;
5079
5080 err:
5081         vfree(tx_ring->tx_buffer_info);
5082         tx_ring->tx_buffer_info = NULL;
5083         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5084         return -ENOMEM;
5085 }
5086
5087 /**
5088  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5089  * @adapter: board private structure
5090  *
5091  * If this function returns with an error, then it's possible one or
5092  * more of the rings is populated (while the rest are not).  It is the
5093  * callers duty to clean those orphaned rings.
5094  *
5095  * Return 0 on success, negative on failure
5096  **/
5097 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5098 {
5099         int i, err = 0;
5100
5101         for (i = 0; i < adapter->num_tx_queues; i++) {
5102                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5103                 if (!err)
5104                         continue;
5105                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5106                 break;
5107         }
5108
5109         return err;
5110 }
5111
5112 /**
5113  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5114  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5115  *
5116  * Returns 0 on success, negative on failure
5117  **/
5118 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5119 {
5120         struct device *dev = rx_ring->dev;
5121         int size;
5122
5123         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5124         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5125         if (!rx_ring->rx_buffer_info)
5126                 rx_ring->rx_buffer_info = vmalloc(size);
5127         if (!rx_ring->rx_buffer_info)
5128                 goto err;
5129         memset(rx_ring->rx_buffer_info, 0, size);
5130
5131         /* Round up to nearest 4K */
5132         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5133         rx_ring->size = ALIGN(rx_ring->size, 4096);
5134
5135         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5136                                            &rx_ring->dma, GFP_KERNEL);
5137
5138         if (!rx_ring->desc)
5139                 goto err;
5140
5141         rx_ring->next_to_clean = 0;
5142         rx_ring->next_to_use = 0;
5143
5144         return 0;
5145 err:
5146         vfree(rx_ring->rx_buffer_info);
5147         rx_ring->rx_buffer_info = NULL;
5148         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5149         return -ENOMEM;
5150 }
5151
5152 /**
5153  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5154  * @adapter: board private structure
5155  *
5156  * If this function returns with an error, then it's possible one or
5157  * more of the rings is populated (while the rest are not).  It is the
5158  * callers duty to clean those orphaned rings.
5159  *
5160  * Return 0 on success, negative on failure
5161  **/
5162 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5163 {
5164         int i, err = 0;
5165
5166         for (i = 0; i < adapter->num_rx_queues; i++) {
5167                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5168                 if (!err)
5169                         continue;
5170                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5171                 break;
5172         }
5173
5174         return err;
5175 }
5176
5177 /**
5178  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5179  * @tx_ring: Tx descriptor ring for a specific queue
5180  *
5181  * Free all transmit software resources
5182  **/
5183 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5184 {
5185         ixgbe_clean_tx_ring(tx_ring);
5186
5187         vfree(tx_ring->tx_buffer_info);
5188         tx_ring->tx_buffer_info = NULL;
5189
5190         /* if not set, then don't free */
5191         if (!tx_ring->desc)
5192                 return;
5193
5194         dma_free_coherent(tx_ring->dev, tx_ring->size,
5195                           tx_ring->desc, tx_ring->dma);
5196
5197         tx_ring->desc = NULL;
5198 }
5199
5200 /**
5201  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5202  * @adapter: board private structure
5203  *
5204  * Free all transmit software resources
5205  **/
5206 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5207 {
5208         int i;
5209
5210         for (i = 0; i < adapter->num_tx_queues; i++)
5211                 if (adapter->tx_ring[i]->desc)
5212                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5213 }
5214
5215 /**
5216  * ixgbe_free_rx_resources - Free Rx Resources
5217  * @rx_ring: ring to clean the resources from
5218  *
5219  * Free all receive software resources
5220  **/
5221 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5222 {
5223         ixgbe_clean_rx_ring(rx_ring);
5224
5225         vfree(rx_ring->rx_buffer_info);
5226         rx_ring->rx_buffer_info = NULL;
5227
5228         /* if not set, then don't free */
5229         if (!rx_ring->desc)
5230                 return;
5231
5232         dma_free_coherent(rx_ring->dev, rx_ring->size,
5233                           rx_ring->desc, rx_ring->dma);
5234
5235         rx_ring->desc = NULL;
5236 }
5237
5238 /**
5239  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5240  * @adapter: board private structure
5241  *
5242  * Free all receive software resources
5243  **/
5244 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5245 {
5246         int i;
5247
5248         for (i = 0; i < adapter->num_rx_queues; i++)
5249                 if (adapter->rx_ring[i]->desc)
5250                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5251 }
5252
5253 /**
5254  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5255  * @netdev: network interface device structure
5256  * @new_mtu: new value for maximum frame size
5257  *
5258  * Returns 0 on success, negative on failure
5259  **/
5260 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5261 {
5262         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5263         struct ixgbe_hw *hw = &adapter->hw;
5264         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5265
5266         /* MTU < 68 is an error and causes problems on some kernels */
5267         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5268                 return -EINVAL;
5269
5270         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5271         /* must set new MTU before calling down or up */
5272         netdev->mtu = new_mtu;
5273
5274         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5275         hw->fc.low_water = FC_LOW_WATER(max_frame);
5276
5277         if (netif_running(netdev))
5278                 ixgbe_reinit_locked(adapter);
5279
5280         return 0;
5281 }
5282
5283 /**
5284  * ixgbe_open - Called when a network interface is made active
5285  * @netdev: network interface device structure
5286  *
5287  * Returns 0 on success, negative value on failure
5288  *
5289  * The open entry point is called when a network interface is made
5290  * active by the system (IFF_UP).  At this point all resources needed
5291  * for transmit and receive operations are allocated, the interrupt
5292  * handler is registered with the OS, the watchdog timer is started,
5293  * and the stack is notified that the interface is ready.
5294  **/
5295 static int ixgbe_open(struct net_device *netdev)
5296 {
5297         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5298         int err;
5299
5300         /* disallow open during test */
5301         if (test_bit(__IXGBE_TESTING, &adapter->state))
5302                 return -EBUSY;
5303
5304         netif_carrier_off(netdev);
5305
5306         /* allocate transmit descriptors */
5307         err = ixgbe_setup_all_tx_resources(adapter);
5308         if (err)
5309                 goto err_setup_tx;
5310
5311         /* allocate receive descriptors */
5312         err = ixgbe_setup_all_rx_resources(adapter);
5313         if (err)
5314                 goto err_setup_rx;
5315
5316         ixgbe_configure(adapter);
5317
5318         err = ixgbe_request_irq(adapter);
5319         if (err)
5320                 goto err_req_irq;
5321
5322         err = ixgbe_up_complete(adapter);
5323         if (err)
5324                 goto err_up;
5325
5326         netif_tx_start_all_queues(netdev);
5327
5328         return 0;
5329
5330 err_up:
5331         ixgbe_release_hw_control(adapter);
5332         ixgbe_free_irq(adapter);
5333 err_req_irq:
5334 err_setup_rx:
5335         ixgbe_free_all_rx_resources(adapter);
5336 err_setup_tx:
5337         ixgbe_free_all_tx_resources(adapter);
5338         ixgbe_reset(adapter);
5339
5340         return err;
5341 }
5342
5343 /**
5344  * ixgbe_close - Disables a network interface
5345  * @netdev: network interface device structure
5346  *
5347  * Returns 0, this is not allowed to fail
5348  *
5349  * The close entry point is called when an interface is de-activated
5350  * by the OS.  The hardware is still under the drivers control, but
5351  * needs to be disabled.  A global MAC reset is issued to stop the
5352  * hardware, and all transmit and receive resources are freed.
5353  **/
5354 static int ixgbe_close(struct net_device *netdev)
5355 {
5356         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5357
5358         ixgbe_down(adapter);
5359         ixgbe_free_irq(adapter);
5360
5361         ixgbe_free_all_tx_resources(adapter);
5362         ixgbe_free_all_rx_resources(adapter);
5363
5364         ixgbe_release_hw_control(adapter);
5365
5366         return 0;
5367 }
5368
5369 #ifdef CONFIG_PM
5370 static int ixgbe_resume(struct pci_dev *pdev)
5371 {
5372         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5373         struct net_device *netdev = adapter->netdev;
5374         u32 err;
5375
5376         pci_set_power_state(pdev, PCI_D0);
5377         pci_restore_state(pdev);
5378         /*
5379          * pci_restore_state clears dev->state_saved so call
5380          * pci_save_state to restore it.
5381          */
5382         pci_save_state(pdev);
5383
5384         err = pci_enable_device_mem(pdev);
5385         if (err) {
5386                 e_dev_err("Cannot enable PCI device from suspend\n");
5387                 return err;
5388         }
5389         pci_set_master(pdev);
5390
5391         pci_wake_from_d3(pdev, false);
5392
5393         err = ixgbe_init_interrupt_scheme(adapter);
5394         if (err) {
5395                 e_dev_err("Cannot initialize interrupts for device\n");
5396                 return err;
5397         }
5398
5399         ixgbe_reset(adapter);
5400
5401         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5402
5403         if (netif_running(netdev)) {
5404                 err = ixgbe_open(netdev);
5405                 if (err)
5406                         return err;
5407         }
5408
5409         netif_device_attach(netdev);
5410
5411         return 0;
5412 }
5413 #endif /* CONFIG_PM */
5414
5415 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5416 {
5417         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5418         struct net_device *netdev = adapter->netdev;
5419         struct ixgbe_hw *hw = &adapter->hw;
5420         u32 ctrl, fctrl;
5421         u32 wufc = adapter->wol;
5422 #ifdef CONFIG_PM
5423         int retval = 0;
5424 #endif
5425
5426         netif_device_detach(netdev);
5427
5428         if (netif_running(netdev)) {
5429                 ixgbe_down(adapter);
5430                 ixgbe_free_irq(adapter);
5431                 ixgbe_free_all_tx_resources(adapter);
5432                 ixgbe_free_all_rx_resources(adapter);
5433         }
5434
5435         ixgbe_clear_interrupt_scheme(adapter);
5436
5437 #ifdef CONFIG_PM
5438         retval = pci_save_state(pdev);
5439         if (retval)
5440                 return retval;
5441
5442 #endif
5443         if (wufc) {
5444                 ixgbe_set_rx_mode(netdev);
5445
5446                 /* turn on all-multi mode if wake on multicast is enabled */
5447                 if (wufc & IXGBE_WUFC_MC) {
5448                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5449                         fctrl |= IXGBE_FCTRL_MPE;
5450                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5451                 }
5452
5453                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5454                 ctrl |= IXGBE_CTRL_GIO_DIS;
5455                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5456
5457                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5458         } else {
5459                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5460                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5461         }
5462
5463         switch (hw->mac.type) {
5464         case ixgbe_mac_82598EB:
5465                 pci_wake_from_d3(pdev, false);
5466                 break;
5467         case ixgbe_mac_82599EB:
5468                 pci_wake_from_d3(pdev, !!wufc);
5469                 break;
5470         default:
5471                 break;
5472         }
5473
5474         *enable_wake = !!wufc;
5475
5476         ixgbe_release_hw_control(adapter);
5477
5478         pci_disable_device(pdev);
5479
5480         return 0;
5481 }
5482
5483 #ifdef CONFIG_PM
5484 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5485 {
5486         int retval;
5487         bool wake;
5488
5489         retval = __ixgbe_shutdown(pdev, &wake);
5490         if (retval)
5491                 return retval;
5492
5493         if (wake) {
5494                 pci_prepare_to_sleep(pdev);
5495         } else {
5496                 pci_wake_from_d3(pdev, false);
5497                 pci_set_power_state(pdev, PCI_D3hot);
5498         }
5499
5500         return 0;
5501 }
5502 #endif /* CONFIG_PM */
5503
5504 static void ixgbe_shutdown(struct pci_dev *pdev)
5505 {
5506         bool wake;
5507
5508         __ixgbe_shutdown(pdev, &wake);
5509
5510         if (system_state == SYSTEM_POWER_OFF) {
5511                 pci_wake_from_d3(pdev, wake);
5512                 pci_set_power_state(pdev, PCI_D3hot);
5513         }
5514 }
5515
5516 /**
5517  * ixgbe_update_stats - Update the board statistics counters.
5518  * @adapter: board private structure
5519  **/
5520 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5521 {
5522         struct net_device *netdev = adapter->netdev;
5523         struct ixgbe_hw *hw = &adapter->hw;
5524         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5525         u64 total_mpc = 0;
5526         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5527         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5528         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5529         u64 bytes = 0, packets = 0;
5530
5531         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5532             test_bit(__IXGBE_RESETTING, &adapter->state))
5533                 return;
5534
5535         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5536                 u64 rsc_count = 0;
5537                 u64 rsc_flush = 0;
5538                 for (i = 0; i < 16; i++)
5539                         adapter->hw_rx_no_dma_resources +=
5540                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5541                 for (i = 0; i < adapter->num_rx_queues; i++) {
5542                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5543                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5544                 }
5545                 adapter->rsc_total_count = rsc_count;
5546                 adapter->rsc_total_flush = rsc_flush;
5547         }
5548
5549         for (i = 0; i < adapter->num_rx_queues; i++) {
5550                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5551                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5552                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5553                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5554                 bytes += rx_ring->stats.bytes;
5555                 packets += rx_ring->stats.packets;
5556         }
5557         adapter->non_eop_descs = non_eop_descs;
5558         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5559         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5560         netdev->stats.rx_bytes = bytes;
5561         netdev->stats.rx_packets = packets;
5562
5563         bytes = 0;
5564         packets = 0;
5565         /* gather some stats to the adapter struct that are per queue */
5566         for (i = 0; i < adapter->num_tx_queues; i++) {
5567                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5568                 restart_queue += tx_ring->tx_stats.restart_queue;
5569                 tx_busy += tx_ring->tx_stats.tx_busy;
5570                 bytes += tx_ring->stats.bytes;
5571                 packets += tx_ring->stats.packets;
5572         }
5573         adapter->restart_queue = restart_queue;
5574         adapter->tx_busy = tx_busy;
5575         netdev->stats.tx_bytes = bytes;
5576         netdev->stats.tx_packets = packets;
5577
5578         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5579         for (i = 0; i < 8; i++) {
5580                 /* for packet buffers not used, the register should read 0 */
5581                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5582                 missed_rx += mpc;
5583                 hwstats->mpc[i] += mpc;
5584                 total_mpc += hwstats->mpc[i];
5585                 if (hw->mac.type == ixgbe_mac_82598EB)
5586                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5587                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5588                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5589                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5590                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5591                 switch (hw->mac.type) {
5592                 case ixgbe_mac_82598EB:
5593                         hwstats->pxonrxc[i] +=
5594                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5595                         hwstats->pxoffrxc[i] +=
5596                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5597                         break;
5598                 case ixgbe_mac_82599EB:
5599                         hwstats->pxonrxc[i] +=
5600                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5601                         hwstats->pxoffrxc[i] +=
5602                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5603                         break;
5604                 default:
5605                         break;
5606                 }
5607                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5608                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5609         }
5610         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5611         /* work around hardware counting issue */
5612         hwstats->gprc -= missed_rx;
5613
5614         /* 82598 hardware only has a 32 bit counter in the high register */
5615         switch (hw->mac.type) {
5616         case ixgbe_mac_82598EB:
5617                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5618                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5619                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5620                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5621                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5622                 break;
5623         case ixgbe_mac_82599EB:
5624                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5625                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5626                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5627                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5628                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5629                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5630                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5631                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5632                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5633                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5634 #ifdef IXGBE_FCOE
5635                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5636                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5637                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5638                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5639                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5640                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5641 #endif /* IXGBE_FCOE */
5642                 break;
5643         default:
5644                 break;
5645         }
5646         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5647         hwstats->bprc += bprc;
5648         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5649         if (hw->mac.type == ixgbe_mac_82598EB)
5650                 hwstats->mprc -= bprc;
5651         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5652         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5653         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5654         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5655         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5656         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5657         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5658         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5659         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5660         hwstats->lxontxc += lxon;
5661         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5662         hwstats->lxofftxc += lxoff;
5663         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5664         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5665         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5666         /*
5667          * 82598 errata - tx of flow control packets is included in tx counters
5668          */
5669         xon_off_tot = lxon + lxoff;
5670         hwstats->gptc -= xon_off_tot;
5671         hwstats->mptc -= xon_off_tot;
5672         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5673         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5674         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5675         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5676         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5677         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5678         hwstats->ptc64 -= xon_off_tot;
5679         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5680         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5681         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5682         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5683         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5684         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5685
5686         /* Fill out the OS statistics structure */
5687         netdev->stats.multicast = hwstats->mprc;
5688
5689         /* Rx Errors */
5690         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5691         netdev->stats.rx_dropped = 0;
5692         netdev->stats.rx_length_errors = hwstats->rlec;
5693         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5694         netdev->stats.rx_missed_errors = total_mpc;
5695 }
5696
5697 /**
5698  * ixgbe_watchdog - Timer Call-back
5699  * @data: pointer to adapter cast into an unsigned long
5700  **/
5701 static void ixgbe_watchdog(unsigned long data)
5702 {
5703         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5704         struct ixgbe_hw *hw = &adapter->hw;
5705         u64 eics = 0;
5706         int i;
5707
5708         /*
5709          *  Do the watchdog outside of interrupt context due to the lovely
5710          * delays that some of the newer hardware requires
5711          */
5712
5713         if (test_bit(__IXGBE_DOWN, &adapter->state))
5714                 goto watchdog_short_circuit;
5715
5716         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5717                 /*
5718                  * for legacy and MSI interrupts don't set any bits
5719                  * that are enabled for EIAM, because this operation
5720                  * would set *both* EIMS and EICS for any bit in EIAM
5721                  */
5722                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5723                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5724                 goto watchdog_reschedule;
5725         }
5726
5727         /* get one bit for every active tx/rx interrupt vector */
5728         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5729                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5730                 if (qv->rxr_count || qv->txr_count)
5731                         eics |= ((u64)1 << i);
5732         }
5733
5734         /* Cause software interrupt to ensure rx rings are cleaned */
5735         ixgbe_irq_rearm_queues(adapter, eics);
5736
5737 watchdog_reschedule:
5738         /* Reset the timer */
5739         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5740
5741 watchdog_short_circuit:
5742         schedule_work(&adapter->watchdog_task);
5743 }
5744
5745 /**
5746  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5747  * @work: pointer to work_struct containing our data
5748  **/
5749 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5750 {
5751         struct ixgbe_adapter *adapter = container_of(work,
5752                                                      struct ixgbe_adapter,
5753                                                      multispeed_fiber_task);
5754         struct ixgbe_hw *hw = &adapter->hw;
5755         u32 autoneg;
5756         bool negotiation;
5757
5758         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5759         autoneg = hw->phy.autoneg_advertised;
5760         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5761                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5762         hw->mac.autotry_restart = false;
5763         if (hw->mac.ops.setup_link)
5764                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5765         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5766         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5767 }
5768
5769 /**
5770  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5771  * @work: pointer to work_struct containing our data
5772  **/
5773 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5774 {
5775         struct ixgbe_adapter *adapter = container_of(work,
5776                                                      struct ixgbe_adapter,
5777                                                      sfp_config_module_task);
5778         struct ixgbe_hw *hw = &adapter->hw;
5779         u32 err;
5780
5781         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5782
5783         /* Time for electrical oscillations to settle down */
5784         msleep(100);
5785         err = hw->phy.ops.identify_sfp(hw);
5786
5787         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5788                 e_dev_err("failed to initialize because an unsupported SFP+ "
5789                           "module type was detected.\n");
5790                 e_dev_err("Reload the driver after installing a supported "
5791                           "module.\n");
5792                 unregister_netdev(adapter->netdev);
5793                 return;
5794         }
5795         hw->mac.ops.setup_sfp(hw);
5796
5797         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5798                 /* This will also work for DA Twinax connections */
5799                 schedule_work(&adapter->multispeed_fiber_task);
5800         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5801 }
5802
5803 /**
5804  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5805  * @work: pointer to work_struct containing our data
5806  **/
5807 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5808 {
5809         struct ixgbe_adapter *adapter = container_of(work,
5810                                                      struct ixgbe_adapter,
5811                                                      fdir_reinit_task);
5812         struct ixgbe_hw *hw = &adapter->hw;
5813         int i;
5814
5815         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5816                 for (i = 0; i < adapter->num_tx_queues; i++)
5817                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5818                                 &(adapter->tx_ring[i]->state));
5819         } else {
5820                 e_err(probe, "failed to finish FDIR re-initialization, "
5821                       "ignored adding FDIR ATR filters\n");
5822         }
5823         /* Done FDIR Re-initialization, enable transmits */
5824         netif_tx_start_all_queues(adapter->netdev);
5825 }
5826
5827 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5828
5829 /**
5830  * ixgbe_watchdog_task - worker thread to bring link up
5831  * @work: pointer to work_struct containing our data
5832  **/
5833 static void ixgbe_watchdog_task(struct work_struct *work)
5834 {
5835         struct ixgbe_adapter *adapter = container_of(work,
5836                                                      struct ixgbe_adapter,
5837                                                      watchdog_task);
5838         struct net_device *netdev = adapter->netdev;
5839         struct ixgbe_hw *hw = &adapter->hw;
5840         u32 link_speed;
5841         bool link_up;
5842         int i;
5843         struct ixgbe_ring *tx_ring;
5844         int some_tx_pending = 0;
5845
5846         mutex_lock(&ixgbe_watchdog_lock);
5847
5848         link_up = adapter->link_up;
5849         link_speed = adapter->link_speed;
5850
5851         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5852                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5853                 if (link_up) {
5854 #ifdef CONFIG_DCB
5855                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5856                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5857                                         hw->mac.ops.fc_enable(hw, i);
5858                         } else {
5859                                 hw->mac.ops.fc_enable(hw, 0);
5860                         }
5861 #else
5862                         hw->mac.ops.fc_enable(hw, 0);
5863 #endif
5864                 }
5865
5866                 if (link_up ||
5867                     time_after(jiffies, (adapter->link_check_timeout +
5868                                          IXGBE_TRY_LINK_TIMEOUT))) {
5869                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5870                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5871                 }
5872                 adapter->link_up = link_up;
5873                 adapter->link_speed = link_speed;
5874         }
5875
5876         if (link_up) {
5877                 if (!netif_carrier_ok(netdev)) {
5878                         bool flow_rx, flow_tx;
5879
5880                         switch (hw->mac.type) {
5881                         case ixgbe_mac_82598EB: {
5882                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5883                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5884                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5885                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5886                         }
5887                                 break;
5888                         case ixgbe_mac_82599EB: {
5889                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5890                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5891                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5892                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5893                         }
5894                                 break;
5895                         default:
5896                                 flow_tx = false;
5897                                 flow_rx = false;
5898                                 break;
5899                         }
5900
5901                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5902                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5903                                "10 Gbps" :
5904                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5905                                "1 Gbps" : "unknown speed")),
5906                                ((flow_rx && flow_tx) ? "RX/TX" :
5907                                (flow_rx ? "RX" :
5908                                (flow_tx ? "TX" : "None"))));
5909
5910                         netif_carrier_on(netdev);
5911                 } else {
5912                         /* Force detection of hung controller */
5913                         for (i = 0; i < adapter->num_tx_queues; i++) {
5914                                 tx_ring = adapter->tx_ring[i];
5915                                 set_check_for_tx_hang(tx_ring);
5916                         }
5917                 }
5918         } else {
5919                 adapter->link_up = false;
5920                 adapter->link_speed = 0;
5921                 if (netif_carrier_ok(netdev)) {
5922                         e_info(drv, "NIC Link is Down\n");
5923                         netif_carrier_off(netdev);
5924                 }
5925         }
5926
5927         if (!netif_carrier_ok(netdev)) {
5928                 for (i = 0; i < adapter->num_tx_queues; i++) {
5929                         tx_ring = adapter->tx_ring[i];
5930                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5931                                 some_tx_pending = 1;
5932                                 break;
5933                         }
5934                 }
5935
5936                 if (some_tx_pending) {
5937                         /* We've lost link, so the controller stops DMA,
5938                          * but we've got queued Tx work that's never going
5939                          * to get done, so reset controller to flush Tx.
5940                          * (Do the reset outside of interrupt context).
5941                          */
5942                          schedule_work(&adapter->reset_task);
5943                 }
5944         }
5945
5946         ixgbe_update_stats(adapter);
5947         mutex_unlock(&ixgbe_watchdog_lock);
5948 }
5949
5950 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5951                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5952                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5953 {
5954         struct ixgbe_adv_tx_context_desc *context_desc;
5955         unsigned int i;
5956         int err;
5957         struct ixgbe_tx_buffer *tx_buffer_info;
5958         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5959         u32 mss_l4len_idx, l4len;
5960
5961         if (skb_is_gso(skb)) {
5962                 if (skb_header_cloned(skb)) {
5963                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5964                         if (err)
5965                                 return err;
5966                 }
5967                 l4len = tcp_hdrlen(skb);
5968                 *hdr_len += l4len;
5969
5970                 if (protocol == htons(ETH_P_IP)) {
5971                         struct iphdr *iph = ip_hdr(skb);
5972                         iph->tot_len = 0;
5973                         iph->check = 0;
5974                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5975                                                                  iph->daddr, 0,
5976                                                                  IPPROTO_TCP,
5977                                                                  0);
5978                 } else if (skb_is_gso_v6(skb)) {
5979                         ipv6_hdr(skb)->payload_len = 0;
5980                         tcp_hdr(skb)->check =
5981                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5982                                              &ipv6_hdr(skb)->daddr,
5983                                              0, IPPROTO_TCP, 0);
5984                 }
5985
5986                 i = tx_ring->next_to_use;
5987
5988                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5989                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5990
5991                 /* VLAN MACLEN IPLEN */
5992                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5993                         vlan_macip_lens |=
5994                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5995                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5996                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5997                 *hdr_len += skb_network_offset(skb);
5998                 vlan_macip_lens |=
5999                     (skb_transport_header(skb) - skb_network_header(skb));
6000                 *hdr_len +=
6001                     (skb_transport_header(skb) - skb_network_header(skb));
6002                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6003                 context_desc->seqnum_seed = 0;
6004
6005                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6006                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6007                                    IXGBE_ADVTXD_DTYP_CTXT);
6008
6009                 if (protocol == htons(ETH_P_IP))
6010                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6011                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6012                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6013
6014                 /* MSS L4LEN IDX */
6015                 mss_l4len_idx =
6016                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6017                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6018                 /* use index 1 for TSO */
6019                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6020                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6021
6022                 tx_buffer_info->time_stamp = jiffies;
6023                 tx_buffer_info->next_to_watch = i;
6024
6025                 i++;
6026                 if (i == tx_ring->count)
6027                         i = 0;
6028                 tx_ring->next_to_use = i;
6029
6030                 return true;
6031         }
6032         return false;
6033 }
6034
6035 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6036                       __be16 protocol)
6037 {
6038         u32 rtn = 0;
6039
6040         switch (protocol) {
6041         case cpu_to_be16(ETH_P_IP):
6042                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6043                 switch (ip_hdr(skb)->protocol) {
6044                 case IPPROTO_TCP:
6045                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6046                         break;
6047                 case IPPROTO_SCTP:
6048                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6049                         break;
6050                 }
6051                 break;
6052         case cpu_to_be16(ETH_P_IPV6):
6053                 /* XXX what about other V6 headers?? */
6054                 switch (ipv6_hdr(skb)->nexthdr) {
6055                 case IPPROTO_TCP:
6056                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6057                         break;
6058                 case IPPROTO_SCTP:
6059                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6060                         break;
6061                 }
6062                 break;
6063         default:
6064                 if (unlikely(net_ratelimit()))
6065                         e_warn(probe, "partial checksum but proto=%x!\n",
6066                                protocol);
6067                 break;
6068         }
6069
6070         return rtn;
6071 }
6072
6073 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6074                           struct ixgbe_ring *tx_ring,
6075                           struct sk_buff *skb, u32 tx_flags,
6076                           __be16 protocol)
6077 {
6078         struct ixgbe_adv_tx_context_desc *context_desc;
6079         unsigned int i;
6080         struct ixgbe_tx_buffer *tx_buffer_info;
6081         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6082
6083         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6084             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6085                 i = tx_ring->next_to_use;
6086                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6087                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6088
6089                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6090                         vlan_macip_lens |=
6091                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6092                 vlan_macip_lens |= (skb_network_offset(skb) <<
6093                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6094                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6095                         vlan_macip_lens |= (skb_transport_header(skb) -
6096                                             skb_network_header(skb));
6097
6098                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6099                 context_desc->seqnum_seed = 0;
6100
6101                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6102                                     IXGBE_ADVTXD_DTYP_CTXT);
6103
6104                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6105                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6106
6107                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6108                 /* use index zero for tx checksum offload */
6109                 context_desc->mss_l4len_idx = 0;
6110
6111                 tx_buffer_info->time_stamp = jiffies;
6112                 tx_buffer_info->next_to_watch = i;
6113
6114                 i++;
6115                 if (i == tx_ring->count)
6116                         i = 0;
6117                 tx_ring->next_to_use = i;
6118
6119                 return true;
6120         }
6121
6122         return false;
6123 }
6124
6125 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6126                         struct ixgbe_ring *tx_ring,
6127                         struct sk_buff *skb, u32 tx_flags,
6128                         unsigned int first, const u8 hdr_len)
6129 {
6130         struct device *dev = tx_ring->dev;
6131         struct ixgbe_tx_buffer *tx_buffer_info;
6132         unsigned int len;
6133         unsigned int total = skb->len;
6134         unsigned int offset = 0, size, count = 0, i;
6135         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6136         unsigned int f;
6137         unsigned int bytecount = skb->len;
6138         u16 gso_segs = 1;
6139
6140         i = tx_ring->next_to_use;
6141
6142         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6143                 /* excluding fcoe_crc_eof for FCoE */
6144                 total -= sizeof(struct fcoe_crc_eof);
6145
6146         len = min(skb_headlen(skb), total);
6147         while (len) {
6148                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6149                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6150
6151                 tx_buffer_info->length = size;
6152                 tx_buffer_info->mapped_as_page = false;
6153                 tx_buffer_info->dma = dma_map_single(dev,
6154                                                      skb->data + offset,
6155                                                      size, DMA_TO_DEVICE);
6156                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6157                         goto dma_error;
6158                 tx_buffer_info->time_stamp = jiffies;
6159                 tx_buffer_info->next_to_watch = i;
6160
6161                 len -= size;
6162                 total -= size;
6163                 offset += size;
6164                 count++;
6165
6166                 if (len) {
6167                         i++;
6168                         if (i == tx_ring->count)
6169                                 i = 0;
6170                 }
6171         }
6172
6173         for (f = 0; f < nr_frags; f++) {
6174                 struct skb_frag_struct *frag;
6175
6176                 frag = &skb_shinfo(skb)->frags[f];
6177                 len = min((unsigned int)frag->size, total);
6178                 offset = frag->page_offset;
6179
6180                 while (len) {
6181                         i++;
6182                         if (i == tx_ring->count)
6183                                 i = 0;
6184
6185                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6186                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6187
6188                         tx_buffer_info->length = size;
6189                         tx_buffer_info->dma = dma_map_page(dev,
6190                                                            frag->page,
6191                                                            offset, size,
6192                                                            DMA_TO_DEVICE);
6193                         tx_buffer_info->mapped_as_page = true;
6194                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6195                                 goto dma_error;
6196                         tx_buffer_info->time_stamp = jiffies;
6197                         tx_buffer_info->next_to_watch = i;
6198
6199                         len -= size;
6200                         total -= size;
6201                         offset += size;
6202                         count++;
6203                 }
6204                 if (total == 0)
6205                         break;
6206         }
6207
6208         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6209                 gso_segs = skb_shinfo(skb)->gso_segs;
6210 #ifdef IXGBE_FCOE
6211         /* adjust for FCoE Sequence Offload */
6212         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6213                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6214                                         skb_shinfo(skb)->gso_size);
6215 #endif /* IXGBE_FCOE */
6216         bytecount += (gso_segs - 1) * hdr_len;
6217
6218         /* multiply data chunks by size of headers */
6219         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6220         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6221         tx_ring->tx_buffer_info[i].skb = skb;
6222         tx_ring->tx_buffer_info[first].next_to_watch = i;
6223
6224         return count;
6225
6226 dma_error:
6227         e_dev_err("TX DMA map failed\n");
6228
6229         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6230         tx_buffer_info->dma = 0;
6231         tx_buffer_info->time_stamp = 0;
6232         tx_buffer_info->next_to_watch = 0;
6233         if (count)
6234                 count--;
6235
6236         /* clear timestamp and dma mappings for remaining portion of packet */
6237         while (count--) {
6238                 if (i == 0)
6239                         i += tx_ring->count;
6240                 i--;
6241                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6242                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6243         }
6244
6245         return 0;
6246 }
6247
6248 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6249                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6250 {
6251         union ixgbe_adv_tx_desc *tx_desc = NULL;
6252         struct ixgbe_tx_buffer *tx_buffer_info;
6253         u32 olinfo_status = 0, cmd_type_len = 0;
6254         unsigned int i;
6255         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6256
6257         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6258
6259         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6260
6261         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6262                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6263
6264         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6265                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6266
6267                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6268                                  IXGBE_ADVTXD_POPTS_SHIFT;
6269
6270                 /* use index 1 context for tso */
6271                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6272                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6273                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6274                                          IXGBE_ADVTXD_POPTS_SHIFT;
6275
6276         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6277                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6278                                  IXGBE_ADVTXD_POPTS_SHIFT;
6279
6280         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6281                 olinfo_status |= IXGBE_ADVTXD_CC;
6282                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6283                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6284                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6285         }
6286
6287         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6288
6289         i = tx_ring->next_to_use;
6290         while (count--) {
6291                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6292                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6293                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6294                 tx_desc->read.cmd_type_len =
6295                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6296                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6297                 i++;
6298                 if (i == tx_ring->count)
6299                         i = 0;
6300         }
6301
6302         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6303
6304         /*
6305          * Force memory writes to complete before letting h/w
6306          * know there are new descriptors to fetch.  (Only
6307          * applicable for weak-ordered memory model archs,
6308          * such as IA-64).
6309          */
6310         wmb();
6311
6312         tx_ring->next_to_use = i;
6313         writel(i, tx_ring->tail);
6314 }
6315
6316 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6317                       u8 queue, u32 tx_flags, __be16 protocol)
6318 {
6319         struct ixgbe_atr_input atr_input;
6320         struct iphdr *iph = ip_hdr(skb);
6321         struct ethhdr *eth = (struct ethhdr *)skb->data;
6322         struct tcphdr *th;
6323         u16 vlan_id;
6324
6325         /* Right now, we support IPv4 w/ TCP only */
6326         if (protocol != htons(ETH_P_IP) ||
6327             iph->protocol != IPPROTO_TCP)
6328                 return;
6329
6330         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6331
6332         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6333                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6334
6335         th = tcp_hdr(skb);
6336
6337         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6338         ixgbe_atr_set_src_port_82599(&atr_input, th->dest);
6339         ixgbe_atr_set_dst_port_82599(&atr_input, th->source);
6340         ixgbe_atr_set_flex_byte_82599(&atr_input, eth->h_proto);
6341         ixgbe_atr_set_l4type_82599(&atr_input, IXGBE_ATR_L4TYPE_TCP);
6342         /* src and dst are inverted, think how the receiver sees them */
6343         ixgbe_atr_set_src_ipv4_82599(&atr_input, iph->daddr);
6344         ixgbe_atr_set_dst_ipv4_82599(&atr_input, iph->saddr);
6345
6346         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6347         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6348 }
6349
6350 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6351 {
6352         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6353         /* Herbert's original patch had:
6354          *  smp_mb__after_netif_stop_queue();
6355          * but since that doesn't exist yet, just open code it. */
6356         smp_mb();
6357
6358         /* We need to check again in a case another CPU has just
6359          * made room available. */
6360         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6361                 return -EBUSY;
6362
6363         /* A reprieve! - use start_queue because it doesn't call schedule */
6364         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6365         ++tx_ring->tx_stats.restart_queue;
6366         return 0;
6367 }
6368
6369 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6370 {
6371         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6372                 return 0;
6373         return __ixgbe_maybe_stop_tx(tx_ring, size);
6374 }
6375
6376 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6377 {
6378         struct ixgbe_adapter *adapter = netdev_priv(dev);
6379         int txq = smp_processor_id();
6380 #ifdef IXGBE_FCOE
6381         __be16 protocol;
6382
6383         protocol = vlan_get_protocol(skb);
6384
6385         if ((protocol == htons(ETH_P_FCOE)) ||
6386             (protocol == htons(ETH_P_FIP))) {
6387                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6388                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6389                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6390                         return txq;
6391 #ifdef CONFIG_IXGBE_DCB
6392                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6393                         txq = adapter->fcoe.up;
6394                         return txq;
6395 #endif
6396                 }
6397         }
6398 #endif
6399
6400         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6401                 while (unlikely(txq >= dev->real_num_tx_queues))
6402                         txq -= dev->real_num_tx_queues;
6403                 return txq;
6404         }
6405
6406         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6407                 if (skb->priority == TC_PRIO_CONTROL)
6408                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6409                 else
6410                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6411                                >> 13;
6412                 return txq;
6413         }
6414
6415         return skb_tx_hash(dev, skb);
6416 }
6417
6418 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6419                           struct ixgbe_adapter *adapter,
6420                           struct ixgbe_ring *tx_ring)
6421 {
6422         struct net_device *netdev = tx_ring->netdev;
6423         struct netdev_queue *txq;
6424         unsigned int first;
6425         unsigned int tx_flags = 0;
6426         u8 hdr_len = 0;
6427         int tso;
6428         int count = 0;
6429         unsigned int f;
6430         __be16 protocol;
6431
6432         protocol = vlan_get_protocol(skb);
6433
6434         if (vlan_tx_tag_present(skb)) {
6435                 tx_flags |= vlan_tx_tag_get(skb);
6436                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6437                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6438                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6439                 }
6440                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6441                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6442         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6443                    skb->priority != TC_PRIO_CONTROL) {
6444                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6445                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6446                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6447         }
6448
6449 #ifdef IXGBE_FCOE
6450         /* for FCoE with DCB, we force the priority to what
6451          * was specified by the switch */
6452         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6453             (protocol == htons(ETH_P_FCOE) ||
6454              protocol == htons(ETH_P_FIP))) {
6455 #ifdef CONFIG_IXGBE_DCB
6456                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6457                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6458                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6459                         tx_flags |= ((adapter->fcoe.up << 13)
6460                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6461                 }
6462 #endif
6463                 /* flag for FCoE offloads */
6464                 if (protocol == htons(ETH_P_FCOE))
6465                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6466         }
6467 #endif
6468
6469         /* four things can cause us to need a context descriptor */
6470         if (skb_is_gso(skb) ||
6471             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6472             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6473             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6474                 count++;
6475
6476         count += TXD_USE_COUNT(skb_headlen(skb));
6477         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6478                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6479
6480         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6481                 tx_ring->tx_stats.tx_busy++;
6482                 return NETDEV_TX_BUSY;
6483         }
6484
6485         first = tx_ring->next_to_use;
6486         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6487 #ifdef IXGBE_FCOE
6488                 /* setup tx offload for FCoE */
6489                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6490                 if (tso < 0) {
6491                         dev_kfree_skb_any(skb);
6492                         return NETDEV_TX_OK;
6493                 }
6494                 if (tso)
6495                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6496 #endif /* IXGBE_FCOE */
6497         } else {
6498                 if (protocol == htons(ETH_P_IP))
6499                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6500                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6501                                 protocol);
6502                 if (tso < 0) {
6503                         dev_kfree_skb_any(skb);
6504                         return NETDEV_TX_OK;
6505                 }
6506
6507                 if (tso)
6508                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6509                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6510                                        protocol) &&
6511                          (skb->ip_summed == CHECKSUM_PARTIAL))
6512                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6513         }
6514
6515         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6516         if (count) {
6517                 /* add the ATR filter if ATR is on */
6518                 if (tx_ring->atr_sample_rate) {
6519                         ++tx_ring->atr_count;
6520                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6521                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6522                                       &tx_ring->state)) {
6523                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6524                                           tx_flags, protocol);
6525                                 tx_ring->atr_count = 0;
6526                         }
6527                 }
6528                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6529                 txq->tx_bytes += skb->len;
6530                 txq->tx_packets++;
6531                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6532                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6533
6534         } else {
6535                 dev_kfree_skb_any(skb);
6536                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6537                 tx_ring->next_to_use = first;
6538         }
6539
6540         return NETDEV_TX_OK;
6541 }
6542
6543 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6544 {
6545         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6546         struct ixgbe_ring *tx_ring;
6547
6548         tx_ring = adapter->tx_ring[skb->queue_mapping];
6549         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6550 }
6551
6552 /**
6553  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6554  * @netdev: network interface device structure
6555  * @p: pointer to an address structure
6556  *
6557  * Returns 0 on success, negative on failure
6558  **/
6559 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6560 {
6561         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6562         struct ixgbe_hw *hw = &adapter->hw;
6563         struct sockaddr *addr = p;
6564
6565         if (!is_valid_ether_addr(addr->sa_data))
6566                 return -EADDRNOTAVAIL;
6567
6568         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6569         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6570
6571         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6572                             IXGBE_RAH_AV);
6573
6574         return 0;
6575 }
6576
6577 static int
6578 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6579 {
6580         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6581         struct ixgbe_hw *hw = &adapter->hw;
6582         u16 value;
6583         int rc;
6584
6585         if (prtad != hw->phy.mdio.prtad)
6586                 return -EINVAL;
6587         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6588         if (!rc)
6589                 rc = value;
6590         return rc;
6591 }
6592
6593 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6594                             u16 addr, u16 value)
6595 {
6596         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6597         struct ixgbe_hw *hw = &adapter->hw;
6598
6599         if (prtad != hw->phy.mdio.prtad)
6600                 return -EINVAL;
6601         return hw->phy.ops.write_reg(hw, addr, devad, value);
6602 }
6603
6604 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6605 {
6606         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6607
6608         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6609 }
6610
6611 /**
6612  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6613  * netdev->dev_addrs
6614  * @netdev: network interface device structure
6615  *
6616  * Returns non-zero on failure
6617  **/
6618 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6619 {
6620         int err = 0;
6621         struct ixgbe_adapter *adapter = netdev_priv(dev);
6622         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6623
6624         if (is_valid_ether_addr(mac->san_addr)) {
6625                 rtnl_lock();
6626                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6627                 rtnl_unlock();
6628         }
6629         return err;
6630 }
6631
6632 /**
6633  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6634  * netdev->dev_addrs
6635  * @netdev: network interface device structure
6636  *
6637  * Returns non-zero on failure
6638  **/
6639 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6640 {
6641         int err = 0;
6642         struct ixgbe_adapter *adapter = netdev_priv(dev);
6643         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6644
6645         if (is_valid_ether_addr(mac->san_addr)) {
6646                 rtnl_lock();
6647                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6648                 rtnl_unlock();
6649         }
6650         return err;
6651 }
6652
6653 #ifdef CONFIG_NET_POLL_CONTROLLER
6654 /*
6655  * Polling 'interrupt' - used by things like netconsole to send skbs
6656  * without having to re-enable interrupts. It's not called while
6657  * the interrupt routine is executing.
6658  */
6659 static void ixgbe_netpoll(struct net_device *netdev)
6660 {
6661         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6662         int i;
6663
6664         /* if interface is down do nothing */
6665         if (test_bit(__IXGBE_DOWN, &adapter->state))
6666                 return;
6667
6668         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6669         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6670                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6671                 for (i = 0; i < num_q_vectors; i++) {
6672                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6673                         ixgbe_msix_clean_many(0, q_vector);
6674                 }
6675         } else {
6676                 ixgbe_intr(adapter->pdev->irq, netdev);
6677         }
6678         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6679 }
6680 #endif
6681
6682 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6683                                                    struct rtnl_link_stats64 *stats)
6684 {
6685         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6686         int i;
6687
6688         /* accurate rx/tx bytes/packets stats */
6689         dev_txq_stats_fold(netdev, stats);
6690         rcu_read_lock();
6691         for (i = 0; i < adapter->num_rx_queues; i++) {
6692                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6693                 u64 bytes, packets;
6694                 unsigned int start;
6695
6696                 if (ring) {
6697                         do {
6698                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6699                                 packets = ring->stats.packets;
6700                                 bytes   = ring->stats.bytes;
6701                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6702                         stats->rx_packets += packets;
6703                         stats->rx_bytes   += bytes;
6704                 }
6705         }
6706         rcu_read_unlock();
6707         /* following stats updated by ixgbe_watchdog_task() */
6708         stats->multicast        = netdev->stats.multicast;
6709         stats->rx_errors        = netdev->stats.rx_errors;
6710         stats->rx_length_errors = netdev->stats.rx_length_errors;
6711         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6712         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6713         return stats;
6714 }
6715
6716
6717 static const struct net_device_ops ixgbe_netdev_ops = {
6718         .ndo_open               = ixgbe_open,
6719         .ndo_stop               = ixgbe_close,
6720         .ndo_start_xmit         = ixgbe_xmit_frame,
6721         .ndo_select_queue       = ixgbe_select_queue,
6722         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6723         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6724         .ndo_validate_addr      = eth_validate_addr,
6725         .ndo_set_mac_address    = ixgbe_set_mac,
6726         .ndo_change_mtu         = ixgbe_change_mtu,
6727         .ndo_tx_timeout         = ixgbe_tx_timeout,
6728         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6729         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6730         .ndo_do_ioctl           = ixgbe_ioctl,
6731         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6732         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6733         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6734         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6735         .ndo_get_stats64        = ixgbe_get_stats64,
6736 #ifdef CONFIG_NET_POLL_CONTROLLER
6737         .ndo_poll_controller    = ixgbe_netpoll,
6738 #endif
6739 #ifdef IXGBE_FCOE
6740         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6741         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6742         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6743         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6744         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6745 #endif /* IXGBE_FCOE */
6746 };
6747
6748 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6749                            const struct ixgbe_info *ii)
6750 {
6751 #ifdef CONFIG_PCI_IOV
6752         struct ixgbe_hw *hw = &adapter->hw;
6753         int err;
6754
6755         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6756                 return;
6757
6758         /* The 82599 supports up to 64 VFs per physical function
6759          * but this implementation limits allocation to 63 so that
6760          * basic networking resources are still available to the
6761          * physical function
6762          */
6763         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6764         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6765         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6766         if (err) {
6767                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6768                 goto err_novfs;
6769         }
6770         /* If call to enable VFs succeeded then allocate memory
6771          * for per VF control structures.
6772          */
6773         adapter->vfinfo =
6774                 kcalloc(adapter->num_vfs,
6775                         sizeof(struct vf_data_storage), GFP_KERNEL);
6776         if (adapter->vfinfo) {
6777                 /* Now that we're sure SR-IOV is enabled
6778                  * and memory allocated set up the mailbox parameters
6779                  */
6780                 ixgbe_init_mbx_params_pf(hw);
6781                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6782                        sizeof(hw->mbx.ops));
6783
6784                 /* Disable RSC when in SR-IOV mode */
6785                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6786                                      IXGBE_FLAG2_RSC_ENABLED);
6787                 return;
6788         }
6789
6790         /* Oh oh */
6791         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6792               "SRIOV disabled\n");
6793         pci_disable_sriov(adapter->pdev);
6794
6795 err_novfs:
6796         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6797         adapter->num_vfs = 0;
6798 #endif /* CONFIG_PCI_IOV */
6799 }
6800
6801 /**
6802  * ixgbe_probe - Device Initialization Routine
6803  * @pdev: PCI device information struct
6804  * @ent: entry in ixgbe_pci_tbl
6805  *
6806  * Returns 0 on success, negative on failure
6807  *
6808  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6809  * The OS initialization, configuring of the adapter private structure,
6810  * and a hardware reset occur.
6811  **/
6812 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6813                                  const struct pci_device_id *ent)
6814 {
6815         struct net_device *netdev;
6816         struct ixgbe_adapter *adapter = NULL;
6817         struct ixgbe_hw *hw;
6818         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6819         static int cards_found;
6820         int i, err, pci_using_dac;
6821         unsigned int indices = num_possible_cpus();
6822 #ifdef IXGBE_FCOE
6823         u16 device_caps;
6824 #endif
6825         u32 part_num, eec;
6826
6827         /* Catch broken hardware that put the wrong VF device ID in
6828          * the PCIe SR-IOV capability.
6829          */
6830         if (pdev->is_virtfn) {
6831                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6832                      pci_name(pdev), pdev->vendor, pdev->device);
6833                 return -EINVAL;
6834         }
6835
6836         err = pci_enable_device_mem(pdev);
6837         if (err)
6838                 return err;
6839
6840         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6841             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6842                 pci_using_dac = 1;
6843         } else {
6844                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6845                 if (err) {
6846                         err = dma_set_coherent_mask(&pdev->dev,
6847                                                     DMA_BIT_MASK(32));
6848                         if (err) {
6849                                 dev_err(&pdev->dev,
6850                                         "No usable DMA configuration, aborting\n");
6851                                 goto err_dma;
6852                         }
6853                 }
6854                 pci_using_dac = 0;
6855         }
6856
6857         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6858                                            IORESOURCE_MEM), ixgbe_driver_name);
6859         if (err) {
6860                 dev_err(&pdev->dev,
6861                         "pci_request_selected_regions failed 0x%x\n", err);
6862                 goto err_pci_reg;
6863         }
6864
6865         pci_enable_pcie_error_reporting(pdev);
6866
6867         pci_set_master(pdev);
6868         pci_save_state(pdev);
6869
6870         if (ii->mac == ixgbe_mac_82598EB)
6871                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6872         else
6873                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6874
6875         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6876 #ifdef IXGBE_FCOE
6877         indices += min_t(unsigned int, num_possible_cpus(),
6878                          IXGBE_MAX_FCOE_INDICES);
6879 #endif
6880         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6881         if (!netdev) {
6882                 err = -ENOMEM;
6883                 goto err_alloc_etherdev;
6884         }
6885
6886         SET_NETDEV_DEV(netdev, &pdev->dev);
6887
6888         adapter = netdev_priv(netdev);
6889         pci_set_drvdata(pdev, adapter);
6890
6891         adapter->netdev = netdev;
6892         adapter->pdev = pdev;
6893         hw = &adapter->hw;
6894         hw->back = adapter;
6895         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6896
6897         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6898                               pci_resource_len(pdev, 0));
6899         if (!hw->hw_addr) {
6900                 err = -EIO;
6901                 goto err_ioremap;
6902         }
6903
6904         for (i = 1; i <= 5; i++) {
6905                 if (pci_resource_len(pdev, i) == 0)
6906                         continue;
6907         }
6908
6909         netdev->netdev_ops = &ixgbe_netdev_ops;
6910         ixgbe_set_ethtool_ops(netdev);
6911         netdev->watchdog_timeo = 5 * HZ;
6912         strcpy(netdev->name, pci_name(pdev));
6913
6914         adapter->bd_number = cards_found;
6915
6916         /* Setup hw api */
6917         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6918         hw->mac.type  = ii->mac;
6919
6920         /* EEPROM */
6921         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6922         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6923         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6924         if (!(eec & (1 << 8)))
6925                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6926
6927         /* PHY */
6928         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6929         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6930         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6931         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6932         hw->phy.mdio.mmds = 0;
6933         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6934         hw->phy.mdio.dev = netdev;
6935         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6936         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6937
6938         /* set up this timer and work struct before calling get_invariants
6939          * which might start the timer
6940          */
6941         init_timer(&adapter->sfp_timer);
6942         adapter->sfp_timer.function = ixgbe_sfp_timer;
6943         adapter->sfp_timer.data = (unsigned long) adapter;
6944
6945         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6946
6947         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6948         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6949
6950         /* a new SFP+ module arrival, called from GPI SDP2 context */
6951         INIT_WORK(&adapter->sfp_config_module_task,
6952                   ixgbe_sfp_config_module_task);
6953
6954         ii->get_invariants(hw);
6955
6956         /* setup the private structure */
6957         err = ixgbe_sw_init(adapter);
6958         if (err)
6959                 goto err_sw_init;
6960
6961         /* Make it possible the adapter to be woken up via WOL */
6962         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6963                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6964
6965         /*
6966          * If there is a fan on this device and it has failed log the
6967          * failure.
6968          */
6969         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6970                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6971                 if (esdp & IXGBE_ESDP_SDP1)
6972                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6973         }
6974
6975         /* reset_hw fills in the perm_addr as well */
6976         hw->phy.reset_if_overtemp = true;
6977         err = hw->mac.ops.reset_hw(hw);
6978         hw->phy.reset_if_overtemp = false;
6979         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6980             hw->mac.type == ixgbe_mac_82598EB) {
6981                 /*
6982                  * Start a kernel thread to watch for a module to arrive.
6983                  * Only do this for 82598, since 82599 will generate
6984                  * interrupts on module arrival.
6985                  */
6986                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6987                 mod_timer(&adapter->sfp_timer,
6988                           round_jiffies(jiffies + (2 * HZ)));
6989                 err = 0;
6990         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6991                 e_dev_err("failed to initialize because an unsupported SFP+ "
6992                           "module type was detected.\n");
6993                 e_dev_err("Reload the driver after installing a supported "
6994                           "module.\n");
6995                 goto err_sw_init;
6996         } else if (err) {
6997                 e_dev_err("HW Init failed: %d\n", err);
6998                 goto err_sw_init;
6999         }
7000
7001         ixgbe_probe_vf(adapter, ii);
7002
7003         netdev->features = NETIF_F_SG |
7004                            NETIF_F_IP_CSUM |
7005                            NETIF_F_HW_VLAN_TX |
7006                            NETIF_F_HW_VLAN_RX |
7007                            NETIF_F_HW_VLAN_FILTER;
7008
7009         netdev->features |= NETIF_F_IPV6_CSUM;
7010         netdev->features |= NETIF_F_TSO;
7011         netdev->features |= NETIF_F_TSO6;
7012         netdev->features |= NETIF_F_GRO;
7013
7014         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
7015                 netdev->features |= NETIF_F_SCTP_CSUM;
7016
7017         netdev->vlan_features |= NETIF_F_TSO;
7018         netdev->vlan_features |= NETIF_F_TSO6;
7019         netdev->vlan_features |= NETIF_F_IP_CSUM;
7020         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7021         netdev->vlan_features |= NETIF_F_SG;
7022
7023         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7024                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7025                                     IXGBE_FLAG_DCB_ENABLED);
7026         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7027                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
7028
7029 #ifdef CONFIG_IXGBE_DCB
7030         netdev->dcbnl_ops = &dcbnl_ops;
7031 #endif
7032
7033 #ifdef IXGBE_FCOE
7034         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7035                 if (hw->mac.ops.get_device_caps) {
7036                         hw->mac.ops.get_device_caps(hw, &device_caps);
7037                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7038                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7039                 }
7040         }
7041         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7042                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7043                 netdev->vlan_features |= NETIF_F_FSO;
7044                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7045         }
7046 #endif /* IXGBE_FCOE */
7047         if (pci_using_dac) {
7048                 netdev->features |= NETIF_F_HIGHDMA;
7049                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7050         }
7051
7052         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7053                 netdev->features |= NETIF_F_LRO;
7054
7055         /* make sure the EEPROM is good */
7056         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7057                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7058                 err = -EIO;
7059                 goto err_eeprom;
7060         }
7061
7062         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7063         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7064
7065         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7066                 e_dev_err("invalid MAC address\n");
7067                 err = -EIO;
7068                 goto err_eeprom;
7069         }
7070
7071         /* power down the optics */
7072         if (hw->phy.multispeed_fiber)
7073                 hw->mac.ops.disable_tx_laser(hw);
7074
7075         init_timer(&adapter->watchdog_timer);
7076         adapter->watchdog_timer.function = ixgbe_watchdog;
7077         adapter->watchdog_timer.data = (unsigned long)adapter;
7078
7079         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
7080         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
7081
7082         err = ixgbe_init_interrupt_scheme(adapter);
7083         if (err)
7084                 goto err_sw_init;
7085
7086         switch (pdev->device) {
7087         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7088                 /* All except this subdevice support WOL */
7089                 if (pdev->subsystem_device ==
7090                     IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) {
7091                         adapter->wol = 0;
7092                         break;
7093                 }
7094         case IXGBE_DEV_ID_82599_KX4:
7095                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7096                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7097                 break;
7098         default:
7099                 adapter->wol = 0;
7100                 break;
7101         }
7102         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7103
7104         /* pick up the PCI bus settings for reporting later */
7105         hw->mac.ops.get_bus_info(hw);
7106
7107         /* print bus type/speed/width info */
7108         e_dev_info("(PCI Express:%s:%s) %pM\n",
7109                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7110                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7111                     "Unknown"),
7112                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7113                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7114                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7115                     "Unknown"),
7116                    netdev->dev_addr);
7117         ixgbe_read_pba_num_generic(hw, &part_num);
7118         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7119                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7120                            "PBA No: %06x-%03x\n",
7121                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7122                            (part_num >> 8), (part_num & 0xff));
7123         else
7124                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7125                            hw->mac.type, hw->phy.type,
7126                            (part_num >> 8), (part_num & 0xff));
7127
7128         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7129                 e_dev_warn("PCI-Express bandwidth available for this card is "
7130                            "not sufficient for optimal performance.\n");
7131                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7132                            "is required.\n");
7133         }
7134
7135         /* save off EEPROM version number */
7136         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7137
7138         /* reset the hardware with the new settings */
7139         err = hw->mac.ops.start_hw(hw);
7140
7141         if (err == IXGBE_ERR_EEPROM_VERSION) {
7142                 /* We are running on a pre-production device, log a warning */
7143                 e_dev_warn("This device is a pre-production adapter/LOM. "
7144                            "Please be aware there may be issues associated "
7145                            "with your hardware.  If you are experiencing "
7146                            "problems please contact your Intel or hardware "
7147                            "representative who provided you with this "
7148                            "hardware.\n");
7149         }
7150         strcpy(netdev->name, "eth%d");
7151         err = register_netdev(netdev);
7152         if (err)
7153                 goto err_register;
7154
7155         /* carrier off reporting is important to ethtool even BEFORE open */
7156         netif_carrier_off(netdev);
7157
7158         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7159             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7160                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7161
7162         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7163                 INIT_WORK(&adapter->check_overtemp_task,
7164                           ixgbe_check_overtemp_task);
7165 #ifdef CONFIG_IXGBE_DCA
7166         if (dca_add_requester(&pdev->dev) == 0) {
7167                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7168                 ixgbe_setup_dca(adapter);
7169         }
7170 #endif
7171         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7172                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7173                 for (i = 0; i < adapter->num_vfs; i++)
7174                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7175         }
7176
7177         /* add san mac addr to netdev */
7178         ixgbe_add_sanmac_netdev(netdev);
7179
7180         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7181         cards_found++;
7182         return 0;
7183
7184 err_register:
7185         ixgbe_release_hw_control(adapter);
7186         ixgbe_clear_interrupt_scheme(adapter);
7187 err_sw_init:
7188 err_eeprom:
7189         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7190                 ixgbe_disable_sriov(adapter);
7191         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7192         del_timer_sync(&adapter->sfp_timer);
7193         cancel_work_sync(&adapter->sfp_task);
7194         cancel_work_sync(&adapter->multispeed_fiber_task);
7195         cancel_work_sync(&adapter->sfp_config_module_task);
7196         iounmap(hw->hw_addr);
7197 err_ioremap:
7198         free_netdev(netdev);
7199 err_alloc_etherdev:
7200         pci_release_selected_regions(pdev,
7201                                      pci_select_bars(pdev, IORESOURCE_MEM));
7202 err_pci_reg:
7203 err_dma:
7204         pci_disable_device(pdev);
7205         return err;
7206 }
7207
7208 /**
7209  * ixgbe_remove - Device Removal Routine
7210  * @pdev: PCI device information struct
7211  *
7212  * ixgbe_remove is called by the PCI subsystem to alert the driver
7213  * that it should release a PCI device.  The could be caused by a
7214  * Hot-Plug event, or because the driver is going to be removed from
7215  * memory.
7216  **/
7217 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7218 {
7219         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7220         struct net_device *netdev = adapter->netdev;
7221
7222         set_bit(__IXGBE_DOWN, &adapter->state);
7223         /* clear the module not found bit to make sure the worker won't
7224          * reschedule
7225          */
7226         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7227         del_timer_sync(&adapter->watchdog_timer);
7228
7229         del_timer_sync(&adapter->sfp_timer);
7230         cancel_work_sync(&adapter->watchdog_task);
7231         cancel_work_sync(&adapter->sfp_task);
7232         cancel_work_sync(&adapter->multispeed_fiber_task);
7233         cancel_work_sync(&adapter->sfp_config_module_task);
7234         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7235             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7236                 cancel_work_sync(&adapter->fdir_reinit_task);
7237         flush_scheduled_work();
7238
7239 #ifdef CONFIG_IXGBE_DCA
7240         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7241                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7242                 dca_remove_requester(&pdev->dev);
7243                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7244         }
7245
7246 #endif
7247 #ifdef IXGBE_FCOE
7248         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7249                 ixgbe_cleanup_fcoe(adapter);
7250
7251 #endif /* IXGBE_FCOE */
7252
7253         /* remove the added san mac */
7254         ixgbe_del_sanmac_netdev(netdev);
7255
7256         if (netdev->reg_state == NETREG_REGISTERED)
7257                 unregister_netdev(netdev);
7258
7259         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7260                 ixgbe_disable_sriov(adapter);
7261
7262         ixgbe_clear_interrupt_scheme(adapter);
7263
7264         ixgbe_release_hw_control(adapter);
7265
7266         iounmap(adapter->hw.hw_addr);
7267         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7268                                      IORESOURCE_MEM));
7269
7270         e_dev_info("complete\n");
7271
7272         free_netdev(netdev);
7273
7274         pci_disable_pcie_error_reporting(pdev);
7275
7276         pci_disable_device(pdev);
7277 }
7278
7279 /**
7280  * ixgbe_io_error_detected - called when PCI error is detected
7281  * @pdev: Pointer to PCI device
7282  * @state: The current pci connection state
7283  *
7284  * This function is called after a PCI bus error affecting
7285  * this device has been detected.
7286  */
7287 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7288                                                 pci_channel_state_t state)
7289 {
7290         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7291         struct net_device *netdev = adapter->netdev;
7292
7293         netif_device_detach(netdev);
7294
7295         if (state == pci_channel_io_perm_failure)
7296                 return PCI_ERS_RESULT_DISCONNECT;
7297
7298         if (netif_running(netdev))
7299                 ixgbe_down(adapter);
7300         pci_disable_device(pdev);
7301
7302         /* Request a slot reset. */
7303         return PCI_ERS_RESULT_NEED_RESET;
7304 }
7305
7306 /**
7307  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7308  * @pdev: Pointer to PCI device
7309  *
7310  * Restart the card from scratch, as if from a cold-boot.
7311  */
7312 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7313 {
7314         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7315         pci_ers_result_t result;
7316         int err;
7317
7318         if (pci_enable_device_mem(pdev)) {
7319                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7320                 result = PCI_ERS_RESULT_DISCONNECT;
7321         } else {
7322                 pci_set_master(pdev);
7323                 pci_restore_state(pdev);
7324                 pci_save_state(pdev);
7325
7326                 pci_wake_from_d3(pdev, false);
7327
7328                 ixgbe_reset(adapter);
7329                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7330                 result = PCI_ERS_RESULT_RECOVERED;
7331         }
7332
7333         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7334         if (err) {
7335                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7336                           "failed 0x%0x\n", err);
7337                 /* non-fatal, continue */
7338         }
7339
7340         return result;
7341 }
7342
7343 /**
7344  * ixgbe_io_resume - called when traffic can start flowing again.
7345  * @pdev: Pointer to PCI device
7346  *
7347  * This callback is called when the error recovery driver tells us that
7348  * its OK to resume normal operation.
7349  */
7350 static void ixgbe_io_resume(struct pci_dev *pdev)
7351 {
7352         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7353         struct net_device *netdev = adapter->netdev;
7354
7355         if (netif_running(netdev)) {
7356                 if (ixgbe_up(adapter)) {
7357                         e_info(probe, "ixgbe_up failed after reset\n");
7358                         return;
7359                 }
7360         }
7361
7362         netif_device_attach(netdev);
7363 }
7364
7365 static struct pci_error_handlers ixgbe_err_handler = {
7366         .error_detected = ixgbe_io_error_detected,
7367         .slot_reset = ixgbe_io_slot_reset,
7368         .resume = ixgbe_io_resume,
7369 };
7370
7371 static struct pci_driver ixgbe_driver = {
7372         .name     = ixgbe_driver_name,
7373         .id_table = ixgbe_pci_tbl,
7374         .probe    = ixgbe_probe,
7375         .remove   = __devexit_p(ixgbe_remove),
7376 #ifdef CONFIG_PM
7377         .suspend  = ixgbe_suspend,
7378         .resume   = ixgbe_resume,
7379 #endif
7380         .shutdown = ixgbe_shutdown,
7381         .err_handler = &ixgbe_err_handler
7382 };
7383
7384 /**
7385  * ixgbe_init_module - Driver Registration Routine
7386  *
7387  * ixgbe_init_module is the first routine called when the driver is
7388  * loaded. All it does is register with the PCI subsystem.
7389  **/
7390 static int __init ixgbe_init_module(void)
7391 {
7392         int ret;
7393         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7394         pr_info("%s\n", ixgbe_copyright);
7395
7396 #ifdef CONFIG_IXGBE_DCA
7397         dca_register_notify(&dca_notifier);
7398 #endif
7399
7400         ret = pci_register_driver(&ixgbe_driver);
7401         return ret;
7402 }
7403
7404 module_init(ixgbe_init_module);
7405
7406 /**
7407  * ixgbe_exit_module - Driver Exit Cleanup Routine
7408  *
7409  * ixgbe_exit_module is called just before the driver is removed
7410  * from memory.
7411  **/
7412 static void __exit ixgbe_exit_module(void)
7413 {
7414 #ifdef CONFIG_IXGBE_DCA
7415         dca_unregister_notify(&dca_notifier);
7416 #endif
7417         pci_unregister_driver(&ixgbe_driver);
7418         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7419 }
7420
7421 #ifdef CONFIG_IXGBE_DCA
7422 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7423                             void *p)
7424 {
7425         int ret_val;
7426
7427         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7428                                          __ixgbe_notify_dca);
7429
7430         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7431 }
7432
7433 #endif /* CONFIG_IXGBE_DCA */
7434
7435 /**
7436  * ixgbe_get_hw_dev return device
7437  * used by hardware layer to print debugging information
7438  **/
7439 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7440 {
7441         struct ixgbe_adapter *adapter = hw->back;
7442         return adapter->netdev;
7443 }
7444
7445 module_exit(ixgbe_exit_module);
7446
7447 /* ixgbe_main.c */