drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2010 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <linux/slab.h>
  40 #include <net/checksum.h>
  41 #include <net/ip6_checksum.h>
  42 #include <linux/ethtool.h>
  43 #include <linux/if_vlan.h>
  44 #include <scsi/fc/fc_fcoe.h>
  45
  46 #include "ixgbe.h"
  47 #include "ixgbe_common.h"
  48 #include "ixgbe_dcb_82599.h"
  49 #include "ixgbe_sriov.h"
  50
  51 char ixgbe_driver_name[] = "ixgbe";
  52 static const char ixgbe_driver_string[] =
  53                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  54
  55 #define DRV_VERSION "2.0.84-k2"
  56 const char ixgbe_driver_version[] = DRV_VERSION;
  57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
  58
  59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  60         [board_82598] = &ixgbe_82598_info,
  61         [board_82599] = &ixgbe_82599_info,
  62 };
  63
  64 /* ixgbe_pci_tbl - PCI Device ID Table
  65  *
  66  * Wildcard entries (PCI_ANY_ID) should come last
  67  * Last entry must be all 0s
  68  *
  69  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  70  *   Class, Class Mask, private data (not used) }
  71  */
  72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  73         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  74          board_82598 },
  75         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  76          board_82598 },
  77         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  78          board_82598 },
  79         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  80          board_82598 },
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  98          board_82599 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 100          board_82599 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 102          board_82599 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 104          board_82599 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 114          board_82599 },
 115
 116         /* required last entry */
 117         {0, }
 118 };
 119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 120
 121 #ifdef CONFIG_IXGBE_DCA
 122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 123                             void *p);
 124 static struct notifier_block dca_notifier = {
 125         .notifier_call = ixgbe_notify_dca,
 126         .next          = NULL,
 127         .priority      = 0
 128 };
 129 #endif
 130
 131 #ifdef CONFIG_PCI_IOV
 132 static unsigned int max_vfs;
 133 module_param(max_vfs, uint, 0);
 134 MODULE_PARM_DESC(max_vfs,
 135                  "Maximum number of virtual functions to allocate per physical function");
 136 #endif /* CONFIG_PCI_IOV */
 137
 138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_VERSION);
 142
 143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 144
 145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 146 {
 147         struct ixgbe_hw *hw = &adapter->hw;
 148         u32 gcr;
 149         u32 gpie;
 150         u32 vmdctl;
 151
 152 #ifdef CONFIG_PCI_IOV
 153         /* disable iov and allow time for transactions to clear */
 154         pci_disable_sriov(adapter->pdev);
 155 #endif
 156
 157         /* turn off device IOV mode */
 158         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 159         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 160         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 161         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 162         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 163         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 164
 165         /* set default pool back to 0 */
 166         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 167         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 168         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 169
 170         /* take a breather then clean up driver data */
 171         msleep(100);
 172
 173         kfree(adapter->vfinfo);
 174         adapter->vfinfo = NULL;
 175
 176         adapter->num_vfs = 0;
 177         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 178 }
 179
 180 struct ixgbe_reg_info {
 181         u32 ofs;
 182         char *name;
 183 };
 184
 185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 186
 187         /* General Registers */
 188         {IXGBE_CTRL, "CTRL"},
 189         {IXGBE_STATUS, "STATUS"},
 190         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 191
 192         /* Interrupt Registers */
 193         {IXGBE_EICR, "EICR"},
 194
 195         /* RX Registers */
 196         {IXGBE_SRRCTL(0), "SRRCTL"},
 197         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 198         {IXGBE_RDLEN(0), "RDLEN"},
 199         {IXGBE_RDH(0), "RDH"},
 200         {IXGBE_RDT(0), "RDT"},
 201         {IXGBE_RXDCTL(0), "RXDCTL"},
 202         {IXGBE_RDBAL(0), "RDBAL"},
 203         {IXGBE_RDBAH(0), "RDBAH"},
 204
 205         /* TX Registers */
 206         {IXGBE_TDBAL(0), "TDBAL"},
 207         {IXGBE_TDBAH(0), "TDBAH"},
 208         {IXGBE_TDLEN(0), "TDLEN"},
 209         {IXGBE_TDH(0), "TDH"},
 210         {IXGBE_TDT(0), "TDT"},
 211         {IXGBE_TXDCTL(0), "TXDCTL"},
 212
 213         /* List Terminator */
 214         {}
 215 };
 216
 217
 218 /*
 219  * ixgbe_regdump - register printout routine
 220  */
 221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 222 {
 223         int i = 0, j = 0;
 224         char rname[16];
 225         u32 regs[64];
 226
 227         switch (reginfo->ofs) {
 228         case IXGBE_SRRCTL(0):
 229                 for (i = 0; i < 64; i++)
 230                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 231                 break;
 232         case IXGBE_DCA_RXCTRL(0):
 233                 for (i = 0; i < 64; i++)
 234                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 235                 break;
 236         case IXGBE_RDLEN(0):
 237                 for (i = 0; i < 64; i++)
 238                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 239                 break;
 240         case IXGBE_RDH(0):
 241                 for (i = 0; i < 64; i++)
 242                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 243                 break;
 244         case IXGBE_RDT(0):
 245                 for (i = 0; i < 64; i++)
 246                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 247                 break;
 248         case IXGBE_RXDCTL(0):
 249                 for (i = 0; i < 64; i++)
 250                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 251                 break;
 252         case IXGBE_RDBAL(0):
 253                 for (i = 0; i < 64; i++)
 254                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 255                 break;
 256         case IXGBE_RDBAH(0):
 257                 for (i = 0; i < 64; i++)
 258                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 259                 break;
 260         case IXGBE_TDBAL(0):
 261                 for (i = 0; i < 64; i++)
 262                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 263                 break;
 264         case IXGBE_TDBAH(0):
 265                 for (i = 0; i < 64; i++)
 266                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 267                 break;
 268         case IXGBE_TDLEN(0):
 269                 for (i = 0; i < 64; i++)
 270                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 271                 break;
 272         case IXGBE_TDH(0):
 273                 for (i = 0; i < 64; i++)
 274                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 275                 break;
 276         case IXGBE_TDT(0):
 277                 for (i = 0; i < 64; i++)
 278                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 279                 break;
 280         case IXGBE_TXDCTL(0):
 281                 for (i = 0; i < 64; i++)
 282                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 283                 break;
 284         default:
 285                 pr_info("%-15s %08x\n", reginfo->name,
 286                         IXGBE_READ_REG(hw, reginfo->ofs));
 287                 return;
 288         }
 289
 290         for (i = 0; i < 8; i++) {
 291                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 292                 pr_err("%-15s", rname);
 293                 for (j = 0; j < 8; j++)
 294                         pr_cont(" %08x", regs[i*8+j]);
 295                 pr_cont("\n");
 296         }
 297
 298 }
 299
 300 /*
 301  * ixgbe_dump - Print registers, tx-rings and rx-rings
 302  */
 303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 304 {
 305         struct net_device *netdev = adapter->netdev;
 306         struct ixgbe_hw *hw = &adapter->hw;
 307         struct ixgbe_reg_info *reginfo;
 308         int n = 0;
 309         struct ixgbe_ring *tx_ring;
 310         struct ixgbe_tx_buffer *tx_buffer_info;
 311         union ixgbe_adv_tx_desc *tx_desc;
 312         struct my_u0 { u64 a; u64 b; } *u0;
 313         struct ixgbe_ring *rx_ring;
 314         union ixgbe_adv_rx_desc *rx_desc;
 315         struct ixgbe_rx_buffer *rx_buffer_info;
 316         u32 staterr;
 317         int i = 0;
 318
 319         if (!netif_msg_hw(adapter))
 320                 return;
 321
 322         /* Print netdevice Info */
 323         if (netdev) {
 324                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 325                 pr_info("Device Name     state            "
 326                         "trans_start      last_rx\n");
 327                 pr_info("%-15s %016lX %016lX %016lX\n",
 328                         netdev->name,
 329                         netdev->state,
 330                         netdev->trans_start,
 331                         netdev->last_rx);
 332         }
 333
 334         /* Print Registers */
 335         dev_info(&adapter->pdev->dev, "Register Dump\n");
 336         pr_info(" Register Name   Value\n");
 337         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 338              reginfo->name; reginfo++) {
 339                 ixgbe_regdump(hw, reginfo);
 340         }
 341
 342         /* Print TX Ring Summary */
 343         if (!netdev || !netif_running(netdev))
 344                 goto exit;
 345
 346         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 347         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 348         for (n = 0; n < adapter->num_tx_queues; n++) {
 349                 tx_ring = adapter->tx_ring[n];
 350                 tx_buffer_info =
 351                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 352                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 353                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 354                            (u64)tx_buffer_info->dma,
 355                            tx_buffer_info->length,
 356                            tx_buffer_info->next_to_watch,
 357                            (u64)tx_buffer_info->time_stamp);
 358         }
 359
 360         /* Print TX Rings */
 361         if (!netif_msg_tx_done(adapter))
 362                 goto rx_ring_summary;
 363
 364         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 365
 366         /* Transmit Descriptor Formats
 367          *
 368          * Advanced Transmit Descriptor
 369          *   +--------------------------------------------------------------+
 370          * 0 |         Buffer Address [63:0]                                |
 371          *   +--------------------------------------------------------------+
 372          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 373          *   +--------------------------------------------------------------+
 374          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 375          */
 376
 377         for (n = 0; n < adapter->num_tx_queues; n++) {
 378                 tx_ring = adapter->tx_ring[n];
 379                 pr_info("------------------------------------\n");
 380                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 381                 pr_info("------------------------------------\n");
 382                 pr_info("T [desc]     [address 63:0  ] "
 383                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 384                         "leng  ntw timestamp        bi->skb\n");
 385
 386                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 387                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 388                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 389                         u0 = (struct my_u0 *)tx_desc;
 390                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 391                                 " %04X  %3X %016llX %p", i,
 392                                 le64_to_cpu(u0->a),
 393                                 le64_to_cpu(u0->b),
 394                                 (u64)tx_buffer_info->dma,
 395                                 tx_buffer_info->length,
 396                                 tx_buffer_info->next_to_watch,
 397                                 (u64)tx_buffer_info->time_stamp,
 398                                 tx_buffer_info->skb);
 399                         if (i == tx_ring->next_to_use &&
 400                                 i == tx_ring->next_to_clean)
 401                                 pr_cont(" NTC/U\n");
 402                         else if (i == tx_ring->next_to_use)
 403                                 pr_cont(" NTU\n");
 404                         else if (i == tx_ring->next_to_clean)
 405                                 pr_cont(" NTC\n");
 406                         else
 407                                 pr_cont("\n");
 408
 409                         if (netif_msg_pktdata(adapter) &&
 410                                 tx_buffer_info->dma != 0)
 411                                 print_hex_dump(KERN_INFO, "",
 412                                         DUMP_PREFIX_ADDRESS, 16, 1,
 413                                         phys_to_virt(tx_buffer_info->dma),
 414                                         tx_buffer_info->length, true);
 415                 }
 416         }
 417
 418         /* Print RX Rings Summary */
 419 rx_ring_summary:
 420         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 421         pr_info("Queue [NTU] [NTC]\n");
 422         for (n = 0; n < adapter->num_rx_queues; n++) {
 423                 rx_ring = adapter->rx_ring[n];
 424                 pr_info("%5d %5X %5X\n",
 425                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 426         }
 427
 428         /* Print RX Rings */
 429         if (!netif_msg_rx_status(adapter))
 430                 goto exit;
 431
 432         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 433
 434         /* Advanced Receive Descriptor (Read) Format
 435          *    63                                           1        0
 436          *    +-----------------------------------------------------+
 437          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 438          *    +----------------------------------------------+------+
 439          *  8 |       Header Buffer Address [63:1]           |  DD  |
 440          *    +-----------------------------------------------------+
 441          *
 442          *
 443          * Advanced Receive Descriptor (Write-Back) Format
 444          *
 445          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 446          *   +------------------------------------------------------+
 447          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 448          *   | Checksum   Ident  |   |           |    | Type | Type |
 449          *   +------------------------------------------------------+
 450          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 451          *   +------------------------------------------------------+
 452          *   63       48 47    32 31            20 19               0
 453          */
 454         for (n = 0; n < adapter->num_rx_queues; n++) {
 455                 rx_ring = adapter->rx_ring[n];
 456                 pr_info("------------------------------------\n");
 457                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 458                 pr_info("------------------------------------\n");
 459                 pr_info("R  [desc]      [ PktBuf     A0] "
 460                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 461                         "<-- Adv Rx Read format\n");
 462                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 463                         "[vl er S cks ln] ---------------- [bi->skb] "
 464                         "<-- Adv Rx Write-Back format\n");
 465
 466                 for (i = 0; i < rx_ring->count; i++) {
 467                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 468                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 469                         u0 = (struct my_u0 *)rx_desc;
 470                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 471                         if (staterr & IXGBE_RXD_STAT_DD) {
 472                                 /* Descriptor Done */
 473                                 pr_info("RWB[0x%03X]     %016llX "
 474                                         "%016llX ---------------- %p", i,
 475                                         le64_to_cpu(u0->a),
 476                                         le64_to_cpu(u0->b),
 477                                         rx_buffer_info->skb);
 478                         } else {
 479                                 pr_info("R  [0x%03X]     %016llX "
 480                                         "%016llX %016llX %p", i,
 481                                         le64_to_cpu(u0->a),
 482                                         le64_to_cpu(u0->b),
 483                                         (u64)rx_buffer_info->dma,
 484                                         rx_buffer_info->skb);
 485
 486                                 if (netif_msg_pktdata(adapter)) {
 487                                         print_hex_dump(KERN_INFO, "",
 488                                            DUMP_PREFIX_ADDRESS, 16, 1,
 489                                            phys_to_virt(rx_buffer_info->dma),
 490                                            rx_ring->rx_buf_len, true);
 491
 492                                         if (rx_ring->rx_buf_len
 493                                                 < IXGBE_RXBUFFER_2048)
 494                                                 print_hex_dump(KERN_INFO, "",
 495                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 496                                                   phys_to_virt(
 497                                                     rx_buffer_info->page_dma +
 498                                                     rx_buffer_info->page_offset
 499                                                   ),
 500                                                   PAGE_SIZE/2, true);
 501                                 }
 502                         }
 503
 504                         if (i == rx_ring->next_to_use)
 505                                 pr_cont(" NTU\n");
 506                         else if (i == rx_ring->next_to_clean)
 507                                 pr_cont(" NTC\n");
 508                         else
 509                                 pr_cont("\n");
 510
 511                 }
 512         }
 513
 514 exit:
 515         return;
 516 }
 517
 518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 519 {
 520         u32 ctrl_ext;
 521
 522         /* Let firmware take over control of h/w */
 523         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 524         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 525                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 526 }
 527
 528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 529 {
 530         u32 ctrl_ext;
 531
 532         /* Let firmware know the driver has taken over */
 533         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 534         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 535                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 536 }
 537
 538 /*
 539  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 540  * @adapter: pointer to adapter struct
 541  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 542  * @queue: queue to map the corresponding interrupt to
 543  * @msix_vector: the vector to map to the corresponding queue
 544  *
 545  */
 546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 547                            u8 queue, u8 msix_vector)
 548 {
 549         u32 ivar, index;
 550         struct ixgbe_hw *hw = &adapter->hw;
 551         switch (hw->mac.type) {
 552         case ixgbe_mac_82598EB:
 553                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 554                 if (direction == -1)
 555                         direction = 0;
 556                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 557                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 558                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 559                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 560                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 561                 break;
 562         case ixgbe_mac_82599EB:
 563                 if (direction == -1) {
 564                         /* other causes */
 565                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 566                         index = ((queue & 1) * 8);
 567                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 568                         ivar &= ~(0xFF << index);
 569                         ivar |= (msix_vector << index);
 570                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 571                         break;
 572                 } else {
 573                         /* tx or rx causes */
 574                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 575                         index = ((16 * (queue & 1)) + (8 * direction));
 576                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 577                         ivar &= ~(0xFF << index);
 578                         ivar |= (msix_vector << index);
 579                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 580                         break;
 581                 }
 582         default:
 583                 break;
 584         }
 585 }
 586
 587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 588                                           u64 qmask)
 589 {
 590         u32 mask;
 591
 592         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 593                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 594                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 595         } else {
 596                 mask = (qmask & 0xFFFFFFFF);
 597                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 598                 mask = (qmask >> 32);
 599                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 600         }
 601 }
 602
 603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 604                                       struct ixgbe_tx_buffer *tx_buffer_info)
 605 {
 606         if (tx_buffer_info->dma) {
 607                 if (tx_buffer_info->mapped_as_page)
 608                         dma_unmap_page(tx_ring->dev,
 609                                        tx_buffer_info->dma,
 610                                        tx_buffer_info->length,
 611                                        DMA_TO_DEVICE);
 612                 else
 613                         dma_unmap_single(tx_ring->dev,
 614                                          tx_buffer_info->dma,
 615                                          tx_buffer_info->length,
 616                                          DMA_TO_DEVICE);
 617                 tx_buffer_info->dma = 0;
 618         }
 619         if (tx_buffer_info->skb) {
 620                 dev_kfree_skb_any(tx_buffer_info->skb);
 621                 tx_buffer_info->skb = NULL;
 622         }
 623         tx_buffer_info->time_stamp = 0;
 624         /* tx_buffer_info must be completely set up in the transmit path */
 625 }
 626
 627 /**
 628  * ixgbe_tx_xon_state - check the tx ring xon state
 629  * @adapter: the ixgbe adapter
 630  * @tx_ring: the corresponding tx_ring
 631  *
 632  * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
 633  * corresponding TC of this tx_ring when checking TFCS.
 634  *
 635  * Returns : true if in xon state (currently not paused)
 636  */
 637 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
 638                                       struct ixgbe_ring *tx_ring)
 639 {
 640         u32 txoff = IXGBE_TFCS_TXOFF;
 641
 642 #ifdef CONFIG_IXGBE_DCB
 643         if (adapter->dcb_cfg.pfc_mode_enable) {
 644                 int tc;
 645                 int reg_idx = tx_ring->reg_idx;
 646                 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
 647
 648                 switch (adapter->hw.mac.type) {
 649                 case ixgbe_mac_82598EB:
 650                         tc = reg_idx >> 2;
 651                         txoff = IXGBE_TFCS_TXOFF0;
 652                         break;
 653                 case ixgbe_mac_82599EB:
 654                         tc = 0;
 655                         txoff = IXGBE_TFCS_TXOFF;
 656                         if (dcb_i == 8) {
 657                                 /* TC0, TC1 */
 658                                 tc = reg_idx >> 5;
 659                                 if (tc == 2) /* TC2, TC3 */
 660                                         tc += (reg_idx - 64) >> 4;
 661                                 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
 662                                         tc += 1 + ((reg_idx - 96) >> 3);
 663                         } else if (dcb_i == 4) {
 664                                 /* TC0, TC1 */
 665                                 tc = reg_idx >> 6;
 666                                 if (tc == 1) {
 667                                         tc += (reg_idx - 64) >> 5;
 668                                         if (tc == 2) /* TC2, TC3 */
 669                                                 tc += (reg_idx - 96) >> 4;
 670                                 }
 671                         }
 672                         break;
 673                 default:
 674                         tc = 0;
 675                 }
 676                 txoff <<= tc;
 677         }
 678 #endif
 679         return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
 680 }
 681
 682 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 683                                        struct ixgbe_ring *tx_ring,
 684                                        unsigned int eop)
 685 {
 686         struct ixgbe_hw *hw = &adapter->hw;
 687
 688         /* Detect a transmit hang in hardware, this serializes the
 689          * check with the clearing of time_stamp and movement of eop */
 690         clear_check_for_tx_hang(tx_ring);
 691         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 692             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 693             ixgbe_tx_xon_state(adapter, tx_ring)) {
 694                 /* detected Tx unit hang */
 695                 union ixgbe_adv_tx_desc *tx_desc;
 696                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 697                 e_err(drv, "Detected Tx Unit Hang\n"
 698                       "  Tx Queue             <%d>\n"
 699                       "  TDH, TDT             <%x>, <%x>\n"
 700                       "  next_to_use          <%x>\n"
 701                       "  next_to_clean        <%x>\n"
 702                       "tx_buffer_info[next_to_clean]\n"
 703                       "  time_stamp           <%lx>\n"
 704                       "  jiffies              <%lx>\n",
 705                       tx_ring->queue_index,
 706                       IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 707                       IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 708                       tx_ring->next_to_use, eop,
 709                       tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 710                 return true;
 711         }
 712
 713         return false;
 714 }
 715
 716 #define IXGBE_MAX_TXD_PWR       14
 717 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 718
 719 /* Tx Descriptors needed, worst case */
 720 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 721                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 722 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 723         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 724
 725 static void ixgbe_tx_timeout(struct net_device *netdev);
 726
 727 /**
 728  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 729  * @q_vector: structure containing interrupt and ring information
 730  * @tx_ring: tx ring to clean
 731  **/
 732 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 733                                struct ixgbe_ring *tx_ring)
 734 {
 735         struct ixgbe_adapter *adapter = q_vector->adapter;
 736         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 737         struct ixgbe_tx_buffer *tx_buffer_info;
 738         unsigned int i, eop, count = 0;
 739         unsigned int total_bytes = 0, total_packets = 0;
 740
 741         i = tx_ring->next_to_clean;
 742         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 743         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 744
 745         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 746                (count < tx_ring->work_limit)) {
 747                 bool cleaned = false;
 748                 rmb(); /* read buffer_info after eop_desc */
 749                 for ( ; !cleaned; count++) {
 750                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 751                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 752
 753                         tx_desc->wb.status = 0;
 754                         cleaned = (i == eop);
 755
 756                         i++;
 757                         if (i == tx_ring->count)
 758                                 i = 0;
 759
 760                         if (cleaned && tx_buffer_info->skb) {
 761                                 total_bytes += tx_buffer_info->bytecount;
 762                                 total_packets += tx_buffer_info->gso_segs;
 763                         }
 764
 765                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 766                                                          tx_buffer_info);
 767                 }
 768
 769                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 770                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 771         }
 772
 773         tx_ring->next_to_clean = i;
 774
 775 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 776         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 777                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 778                 /* Make sure that anybody stopping the queue after this
 779                  * sees the new next_to_clean.
 780                  */
 781                 smp_mb();
 782                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 783                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 784                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 785                         ++tx_ring->tx_stats.restart_queue;
 786                 }
 787         }
 788
 789         if (check_for_tx_hang(tx_ring) &&
 790             ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 791                 /* schedule immediate reset if we believe we hung */
 792                 e_info(probe, "tx hang %d detected, resetting "
 793                        "adapter\n", adapter->tx_timeout_count + 1);
 794                 ixgbe_tx_timeout(adapter->netdev);
 795         }
 796
 797         /* re-arm the interrupt */
 798         if (count >= tx_ring->work_limit)
 799                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 800
 801         tx_ring->total_bytes += total_bytes;
 802         tx_ring->total_packets += total_packets;
 803         u64_stats_update_begin(&tx_ring->syncp);
 804         tx_ring->stats.packets += total_packets;
 805         tx_ring->stats.bytes += total_bytes;
 806         u64_stats_update_end(&tx_ring->syncp);
 807         return count < tx_ring->work_limit;
 808 }
 809
 810 #ifdef CONFIG_IXGBE_DCA
 811 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 812                                 struct ixgbe_ring *rx_ring,
 813                                 int cpu)
 814 {
 815         struct ixgbe_hw *hw = &adapter->hw;
 816         u32 rxctrl;
 817         u8 reg_idx = rx_ring->reg_idx;
 818
 819         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 820         switch (hw->mac.type) {
 821         case ixgbe_mac_82598EB:
 822                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 823                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 824                 break;
 825         case ixgbe_mac_82599EB:
 826                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 827                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 828                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 829                 break;
 830         default:
 831                 break;
 832         }
 833         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 834         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 835         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 836         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 837                     IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 838         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 839 }
 840
 841 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 842                                 struct ixgbe_ring *tx_ring,
 843                                 int cpu)
 844 {
 845         struct ixgbe_hw *hw = &adapter->hw;
 846         u32 txctrl;
 847         u8 reg_idx = tx_ring->reg_idx;
 848
 849         switch (hw->mac.type) {
 850         case ixgbe_mac_82598EB:
 851                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 852                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 853                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 854                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 855                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 856                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 857                 break;
 858         case ixgbe_mac_82599EB:
 859                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 860                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 861                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 862                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 863                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 864                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
 865                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 866                 break;
 867         default:
 868                 break;
 869         }
 870 }
 871
 872 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 873 {
 874         struct ixgbe_adapter *adapter = q_vector->adapter;
 875         int cpu = get_cpu();
 876         long r_idx;
 877         int i;
 878
 879         if (q_vector->cpu == cpu)
 880                 goto out_no_update;
 881
 882         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 883         for (i = 0; i < q_vector->txr_count; i++) {
 884                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 885                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 886                                       r_idx + 1);
 887         }
 888
 889         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 890         for (i = 0; i < q_vector->rxr_count; i++) {
 891                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 892                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 893                                       r_idx + 1);
 894         }
 895
 896         q_vector->cpu = cpu;
 897 out_no_update:
 898         put_cpu();
 899 }
 900
 901 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 902 {
 903         int num_q_vectors;
 904         int i;
 905
 906         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 907                 return;
 908
 909         /* always use CB2 mode, difference is masked in the CB driver */
 910         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 911
 912         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
 913                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 914         else
 915                 num_q_vectors = 1;
 916
 917         for (i = 0; i < num_q_vectors; i++) {
 918                 adapter->q_vector[i]->cpu = -1;
 919                 ixgbe_update_dca(adapter->q_vector[i]);
 920         }
 921 }
 922
 923 static int __ixgbe_notify_dca(struct device *dev, void *data)
 924 {
 925         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
 926         unsigned long event = *(unsigned long *)data;
 927
 928         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 929                 return 0;
 930
 931         switch (event) {
 932         case DCA_PROVIDER_ADD:
 933                 /* if we're already enabled, don't do it again */
 934                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 935                         break;
 936                 if (dca_add_requester(dev) == 0) {
 937                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 938                         ixgbe_setup_dca(adapter);
 939                         break;
 940                 }
 941                 /* Fall Through since DCA is disabled. */
 942         case DCA_PROVIDER_REMOVE:
 943                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 944                         dca_remove_requester(dev);
 945                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 946                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 947                 }
 948                 break;
 949         }
 950
 951         return 0;
 952 }
 953
 954 #endif /* CONFIG_IXGBE_DCA */
 955 /**
 956  * ixgbe_receive_skb - Send a completed packet up the stack
 957  * @adapter: board private structure
 958  * @skb: packet to send up
 959  * @status: hardware indication of status of receive
 960  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 961  * @rx_desc: rx descriptor
 962  **/
 963 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 964                               struct sk_buff *skb, u8 status,
 965                               struct ixgbe_ring *ring,
 966                               union ixgbe_adv_rx_desc *rx_desc)
 967 {
 968         struct ixgbe_adapter *adapter = q_vector->adapter;
 969         struct napi_struct *napi = &q_vector->napi;
 970         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 971         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 972
 973         if (is_vlan && (tag & VLAN_VID_MASK))
 974                 __vlan_hwaccel_put_tag(skb, tag);
 975
 976         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
 977                 napi_gro_receive(napi, skb);
 978         else
 979                 netif_rx(skb);
 980 }
 981
 982 /**
 983  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 984  * @adapter: address of board private structure
 985  * @status_err: hardware indication of status of receive
 986  * @skb: skb currently being received and modified
 987  **/
 988 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 989                                      union ixgbe_adv_rx_desc *rx_desc,
 990                                      struct sk_buff *skb)
 991 {
 992         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 993
 994         skb_checksum_none_assert(skb);
 995
 996         /* Rx csum disabled */
 997         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 998                 return;
 999
1000         /* if IP and error */
1001         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1002             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1003                 adapter->hw_csum_rx_error++;
1004                 return;
1005         }
1006
1007         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1008                 return;
1009
1010         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1011                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1012
1013                 /*
1014                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1015                  * checksum errors.
1016                  */
1017                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1018                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1019                         return;
1020
1021                 adapter->hw_csum_rx_error++;
1022                 return;
1023         }
1024
1025         /* It must be a TCP or UDP packet with a valid checksum */
1026         skb->ip_summed = CHECKSUM_UNNECESSARY;
1027 }
1028
1029 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1030 {
1031         /*
1032          * Force memory writes to complete before letting h/w
1033          * know there are new descriptors to fetch.  (Only
1034          * applicable for weak-ordered memory model archs,
1035          * such as IA-64).
1036          */
1037         wmb();
1038         writel(val, rx_ring->tail);
1039 }
1040
1041 /**
1042  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1043  * @rx_ring: ring to place buffers on
1044  * @cleaned_count: number of buffers to replace
1045  **/
1046 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1047 {
1048         union ixgbe_adv_rx_desc *rx_desc;
1049         struct ixgbe_rx_buffer *bi;
1050         struct sk_buff *skb;
1051         u16 i = rx_ring->next_to_use;
1052
1053         /* do nothing if no valid netdev defined */
1054         if (!rx_ring->netdev)
1055                 return;
1056
1057         while (cleaned_count--) {
1058                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1059                 bi = &rx_ring->rx_buffer_info[i];
1060                 skb = bi->skb;
1061
1062                 if (!skb) {
1063                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1064                                                         rx_ring->rx_buf_len);
1065                         if (!skb) {
1066                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1067                                 goto no_buffers;
1068                         }
1069                         /* initialize queue mapping */
1070                         skb_record_rx_queue(skb, rx_ring->queue_index);
1071                         bi->skb = skb;
1072                 }
1073
1074                 if (!bi->dma) {
1075                         bi->dma = dma_map_single(rx_ring->dev,
1076                                                  skb->data,
1077                                                  rx_ring->rx_buf_len,
1078                                                  DMA_FROM_DEVICE);
1079                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1080                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1081                                 bi->dma = 0;
1082                                 goto no_buffers;
1083                         }
1084                 }
1085
1086                 if (ring_is_ps_enabled(rx_ring)) {
1087                         if (!bi->page) {
1088                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1089                                 if (!bi->page) {
1090                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1091                                         goto no_buffers;
1092                                 }
1093                         }
1094
1095                         if (!bi->page_dma) {
1096                                 /* use a half page if we're re-using */
1097                                 bi->page_offset ^= PAGE_SIZE / 2;
1098                                 bi->page_dma = dma_map_page(rx_ring->dev,
1099                                                             bi->page,
1100                                                             bi->page_offset,
1101                                                             PAGE_SIZE / 2,
1102                                                             DMA_FROM_DEVICE);
1103                                 if (dma_mapping_error(rx_ring->dev,
1104                                                       bi->page_dma)) {
1105                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1106                                         bi->page_dma = 0;
1107                                         goto no_buffers;
1108                                 }
1109                         }
1110
1111                         /* Refresh the desc even if buffer_addrs didn't change
1112                          * because each write-back erases this info. */
1113                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1114                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1115                 } else {
1116                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1117                         rx_desc->read.hdr_addr = 0;
1118                 }
1119
1120                 i++;
1121                 if (i == rx_ring->count)
1122                         i = 0;
1123         }
1124
1125 no_buffers:
1126         if (rx_ring->next_to_use != i) {
1127                 rx_ring->next_to_use = i;
1128                 ixgbe_release_rx_desc(rx_ring, i);
1129         }
1130 }
1131
1132 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1133 {
1134         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1135 }
1136
1137 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1138 {
1139         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1140 }
1141
1142 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1143 {
1144         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1145                 IXGBE_RXDADV_RSCCNT_MASK) >>
1146                 IXGBE_RXDADV_RSCCNT_SHIFT;
1147 }
1148
1149 /**
1150  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1151  * @skb: pointer to the last skb in the rsc queue
1152  * @count: pointer to number of packets coalesced in this context
1153  *
1154  * This function changes a queue full of hw rsc buffers into a completed
1155  * packet.  It uses the ->prev pointers to find the first packet and then
1156  * turns it into the frag list owner.
1157  **/
1158 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1159                                                         u64 *count)
1160 {
1161         unsigned int frag_list_size = 0;
1162
1163         while (skb->prev) {
1164                 struct sk_buff *prev = skb->prev;
1165                 frag_list_size += skb->len;
1166                 skb->prev = NULL;
1167                 skb = prev;
1168                 *count += 1;
1169         }
1170
1171         skb_shinfo(skb)->frag_list = skb->next;
1172         skb->next = NULL;
1173         skb->len += frag_list_size;
1174         skb->data_len += frag_list_size;
1175         skb->truesize += frag_list_size;
1176         return skb;
1177 }
1178
1179 struct ixgbe_rsc_cb {
1180         dma_addr_t dma;
1181         bool delay_unmap;
1182 };
1183
1184 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1185
1186 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1187                                struct ixgbe_ring *rx_ring,
1188                                int *work_done, int work_to_do)
1189 {
1190         struct ixgbe_adapter *adapter = q_vector->adapter;
1191         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1192         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1193         struct sk_buff *skb;
1194         unsigned int i, rsc_count = 0;
1195         u32 len, staterr;
1196         u16 hdr_info;
1197         bool cleaned = false;
1198         int cleaned_count = 0;
1199         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1200 #ifdef IXGBE_FCOE
1201         int ddp_bytes = 0;
1202 #endif /* IXGBE_FCOE */
1203
1204         i = rx_ring->next_to_clean;
1205         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1206         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1207         rx_buffer_info = &rx_ring->rx_buffer_info[i];
1208
1209         while (staterr & IXGBE_RXD_STAT_DD) {
1210                 u32 upper_len = 0;
1211                 if (*work_done >= work_to_do)
1212                         break;
1213                 (*work_done)++;
1214
1215                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1216                 if (ring_is_ps_enabled(rx_ring)) {
1217                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1218                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1219                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1220                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1221                         if ((len > IXGBE_RX_HDR_SIZE) ||
1222                             (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1223                                 len = IXGBE_RX_HDR_SIZE;
1224                 } else {
1225                         len = le16_to_cpu(rx_desc->wb.upper.length);
1226                 }
1227
1228                 cleaned = true;
1229                 skb = rx_buffer_info->skb;
1230                 prefetch(skb->data);
1231                 rx_buffer_info->skb = NULL;
1232
1233                 if (rx_buffer_info->dma) {
1234                         if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1235                             (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1236                                  (!(skb->prev))) {
1237                                 /*
1238                                  * When HWRSC is enabled, delay unmapping
1239                                  * of the first packet. It carries the
1240                                  * header information, HW may still
1241                                  * access the header after the writeback.
1242                                  * Only unmap it when EOP is reached
1243                                  */
1244                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1245                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1246                         } else {
1247                                 dma_unmap_single(rx_ring->dev,
1248                                                  rx_buffer_info->dma,
1249                                                  rx_ring->rx_buf_len,
1250                                                  DMA_FROM_DEVICE);
1251                         }
1252                         rx_buffer_info->dma = 0;
1253                         skb_put(skb, len);
1254                 }
1255
1256                 if (upper_len) {
1257                         dma_unmap_page(rx_ring->dev,
1258                                        rx_buffer_info->page_dma,
1259                                        PAGE_SIZE / 2,
1260                                        DMA_FROM_DEVICE);
1261                         rx_buffer_info->page_dma = 0;
1262                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1263                                            rx_buffer_info->page,
1264                                            rx_buffer_info->page_offset,
1265                                            upper_len);
1266
1267                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1268                             (page_count(rx_buffer_info->page) != 1))
1269                                 rx_buffer_info->page = NULL;
1270                         else
1271                                 get_page(rx_buffer_info->page);
1272
1273                         skb->len += upper_len;
1274                         skb->data_len += upper_len;
1275                         skb->truesize += upper_len;
1276                 }
1277
1278                 i++;
1279                 if (i == rx_ring->count)
1280                         i = 0;
1281
1282                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1283                 prefetch(next_rxd);
1284                 cleaned_count++;
1285
1286                 if (ring_is_rsc_enabled(rx_ring))
1287                         rsc_count = ixgbe_get_rsc_count(rx_desc);
1288
1289                 if (rsc_count) {
1290                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1291                                      IXGBE_RXDADV_NEXTP_SHIFT;
1292                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1293                 } else {
1294                         next_buffer = &rx_ring->rx_buffer_info[i];
1295                 }
1296
1297                 if (staterr & IXGBE_RXD_STAT_EOP) {
1298                         if (skb->prev)
1299                                 skb = ixgbe_transform_rsc_queue(skb,
1300                                                 &(rx_ring->rx_stats.rsc_count));
1301                         if (ring_is_rsc_enabled(rx_ring)) {
1302                                 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1303                                         dma_unmap_single(rx_ring->dev,
1304                                                          IXGBE_RSC_CB(skb)->dma,
1305                                                          rx_ring->rx_buf_len,
1306                                                          DMA_FROM_DEVICE);
1307                                         IXGBE_RSC_CB(skb)->dma = 0;
1308                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
1309                                 }
1310                                 if (ring_is_ps_enabled(rx_ring))
1311                                         rx_ring->rx_stats.rsc_count +=
1312                                                  skb_shinfo(skb)->nr_frags;
1313                                 else
1314                                         rx_ring->rx_stats.rsc_count++;
1315                                 rx_ring->rx_stats.rsc_flush++;
1316                         }
1317                         u64_stats_update_begin(&rx_ring->syncp);
1318                         rx_ring->stats.packets++;
1319                         rx_ring->stats.bytes += skb->len;
1320                         u64_stats_update_end(&rx_ring->syncp);
1321                 } else {
1322                         if (ring_is_ps_enabled(rx_ring)) {
1323                                 rx_buffer_info->skb = next_buffer->skb;
1324                                 rx_buffer_info->dma = next_buffer->dma;
1325                                 next_buffer->skb = skb;
1326                                 next_buffer->dma = 0;
1327                         } else {
1328                                 skb->next = next_buffer->skb;
1329                                 skb->next->prev = skb;
1330                         }
1331                         rx_ring->rx_stats.non_eop_descs++;
1332                         goto next_desc;
1333                 }
1334
1335                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1336                         dev_kfree_skb_irq(skb);
1337                         goto next_desc;
1338                 }
1339
1340                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1341
1342                 /* probably a little skewed due to removing CRC */
1343                 total_rx_bytes += skb->len;
1344                 total_rx_packets++;
1345
1346                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1347 #ifdef IXGBE_FCOE
1348                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1349                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1350                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1351                         if (!ddp_bytes)
1352                                 goto next_desc;
1353                 }
1354 #endif /* IXGBE_FCOE */
1355                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1356
1357 next_desc:
1358                 rx_desc->wb.upper.status_error = 0;
1359
1360                 /* return some buffers to hardware, one at a time is too slow */
1361                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1362                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1363                         cleaned_count = 0;
1364                 }
1365
1366                 /* use prefetched values */
1367                 rx_desc = next_rxd;
1368                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1369
1370                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1371         }
1372
1373         rx_ring->next_to_clean = i;
1374         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1375
1376         if (cleaned_count)
1377                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1378
1379 #ifdef IXGBE_FCOE
1380         /* include DDPed FCoE data */
1381         if (ddp_bytes > 0) {
1382                 unsigned int mss;
1383
1384                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1385                         sizeof(struct fc_frame_header) -
1386                         sizeof(struct fcoe_crc_eof);
1387                 if (mss > 512)
1388                         mss &= ~511;
1389                 total_rx_bytes += ddp_bytes;
1390                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1391         }
1392 #endif /* IXGBE_FCOE */
1393
1394         rx_ring->total_packets += total_rx_packets;
1395         rx_ring->total_bytes += total_rx_bytes;
1396
1397         return cleaned;
1398 }
1399
1400 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1401 /**
1402  * ixgbe_configure_msix - Configure MSI-X hardware
1403  * @adapter: board private structure
1404  *
1405  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1406  * interrupts.
1407  **/
1408 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1409 {
1410         struct ixgbe_q_vector *q_vector;
1411         int i, j, q_vectors, v_idx, r_idx;
1412         u32 mask;
1413
1414         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1415
1416         /*
1417          * Populate the IVAR table and set the ITR values to the
1418          * corresponding register.
1419          */
1420         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1421                 q_vector = adapter->q_vector[v_idx];
1422                 /* XXX for_each_set_bit(...) */
1423                 r_idx = find_first_bit(q_vector->rxr_idx,
1424                                        adapter->num_rx_queues);
1425
1426                 for (i = 0; i < q_vector->rxr_count; i++) {
1427                         j = adapter->rx_ring[r_idx]->reg_idx;
1428                         ixgbe_set_ivar(adapter, 0, j, v_idx);
1429                         r_idx = find_next_bit(q_vector->rxr_idx,
1430                                               adapter->num_rx_queues,
1431                                               r_idx + 1);
1432                 }
1433                 r_idx = find_first_bit(q_vector->txr_idx,
1434                                        adapter->num_tx_queues);
1435
1436                 for (i = 0; i < q_vector->txr_count; i++) {
1437                         j = adapter->tx_ring[r_idx]->reg_idx;
1438                         ixgbe_set_ivar(adapter, 1, j, v_idx);
1439                         r_idx = find_next_bit(q_vector->txr_idx,
1440                                               adapter->num_tx_queues,
1441                                               r_idx + 1);
1442                 }
1443
1444                 if (q_vector->txr_count && !q_vector->rxr_count)
1445                         /* tx only */
1446                         q_vector->eitr = adapter->tx_eitr_param;
1447                 else if (q_vector->rxr_count)
1448                         /* rx or mixed */
1449                         q_vector->eitr = adapter->rx_eitr_param;
1450
1451                 ixgbe_write_eitr(q_vector);
1452                 /* If Flow Director is enabled, set interrupt affinity */
1453                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1454                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1455                         /*
1456                          * Allocate the affinity_hint cpumask, assign the mask
1457                          * for this vector, and set our affinity_hint for
1458                          * this irq.
1459                          */
1460                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1461                                                GFP_KERNEL))
1462                                 return;
1463                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1464                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1465                                               q_vector->affinity_mask);
1466                 }
1467         }
1468
1469         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1470                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1471                                v_idx);
1472         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1473                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1474         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1475
1476         /* set up to autoclear timer, and the vectors */
1477         mask = IXGBE_EIMS_ENABLE_MASK;
1478         if (adapter->num_vfs)
1479                 mask &= ~(IXGBE_EIMS_OTHER |
1480                           IXGBE_EIMS_MAILBOX |
1481                           IXGBE_EIMS_LSC);
1482         else
1483                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1484         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1485 }
1486
1487 enum latency_range {
1488         lowest_latency = 0,
1489         low_latency = 1,
1490         bulk_latency = 2,
1491         latency_invalid = 255
1492 };
1493
1494 /**
1495  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1496  * @adapter: pointer to adapter
1497  * @eitr: eitr setting (ints per sec) to give last timeslice
1498  * @itr_setting: current throttle rate in ints/second
1499  * @packets: the number of packets during this measurement interval
1500  * @bytes: the number of bytes during this measurement interval
1501  *
1502  *      Stores a new ITR value based on packets and byte
1503  *      counts during the last interrupt.  The advantage of per interrupt
1504  *      computation is faster updates and more accurate ITR for the current
1505  *      traffic pattern.  Constants in this function were computed
1506  *      based on theoretical maximum wire speed and thresholds were set based
1507  *      on testing data as well as attempting to minimize response time
1508  *      while increasing bulk throughput.
1509  *      this functionality is controlled by the InterruptThrottleRate module
1510  *      parameter (see ixgbe_param.c)
1511  **/
1512 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1513                            u32 eitr, u8 itr_setting,
1514                            int packets, int bytes)
1515 {
1516         unsigned int retval = itr_setting;
1517         u32 timepassed_us;
1518         u64 bytes_perint;
1519
1520         if (packets == 0)
1521                 goto update_itr_done;
1522
1523
1524         /* simple throttlerate management
1525          *    0-20MB/s lowest (100000 ints/s)
1526          *   20-100MB/s low   (20000 ints/s)
1527          *  100-1249MB/s bulk (8000 ints/s)
1528          */
1529         /* what was last interrupt timeslice? */
1530         timepassed_us = 1000000/eitr;
1531         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1532
1533         switch (itr_setting) {
1534         case lowest_latency:
1535                 if (bytes_perint > adapter->eitr_low)
1536                         retval = low_latency;
1537                 break;
1538         case low_latency:
1539                 if (bytes_perint > adapter->eitr_high)
1540                         retval = bulk_latency;
1541                 else if (bytes_perint <= adapter->eitr_low)
1542                         retval = lowest_latency;
1543                 break;
1544         case bulk_latency:
1545                 if (bytes_perint <= adapter->eitr_high)
1546                         retval = low_latency;
1547                 break;
1548         }
1549
1550 update_itr_done:
1551         return retval;
1552 }
1553
1554 /**
1555  * ixgbe_write_eitr - write EITR register in hardware specific way
1556  * @q_vector: structure containing interrupt and ring information
1557  *
1558  * This function is made to be called by ethtool and by the driver
1559  * when it needs to update EITR registers at runtime.  Hardware
1560  * specific quirks/differences are taken care of here.
1561  */
1562 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1563 {
1564         struct ixgbe_adapter *adapter = q_vector->adapter;
1565         struct ixgbe_hw *hw = &adapter->hw;
1566         int v_idx = q_vector->v_idx;
1567         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1568
1569         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1570                 /* must write high and low 16 bits to reset counter */
1571                 itr_reg |= (itr_reg << 16);
1572         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1573                 /*
1574                  * 82599 can support a value of zero, so allow it for
1575                  * max interrupt rate, but there is an errata where it can
1576                  * not be zero with RSC
1577                  */
1578                 if (itr_reg == 8 &&
1579                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1580                         itr_reg = 0;
1581
1582                 /*
1583                  * set the WDIS bit to not clear the timer bits and cause an
1584                  * immediate assertion of the interrupt
1585                  */
1586                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1587         }
1588         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1589 }
1590
1591 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1592 {
1593         struct ixgbe_adapter *adapter = q_vector->adapter;
1594         u32 new_itr;
1595         u8 current_itr, ret_itr;
1596         int i, r_idx;
1597         struct ixgbe_ring *rx_ring, *tx_ring;
1598
1599         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1600         for (i = 0; i < q_vector->txr_count; i++) {
1601                 tx_ring = adapter->tx_ring[r_idx];
1602                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1603                                            q_vector->tx_itr,
1604                                            tx_ring->total_packets,
1605                                            tx_ring->total_bytes);
1606                 /* if the result for this queue would decrease interrupt
1607                  * rate for this vector then use that result */
1608                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1609                                     q_vector->tx_itr - 1 : ret_itr);
1610                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1611                                       r_idx + 1);
1612         }
1613
1614         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1615         for (i = 0; i < q_vector->rxr_count; i++) {
1616                 rx_ring = adapter->rx_ring[r_idx];
1617                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1618                                            q_vector->rx_itr,
1619                                            rx_ring->total_packets,
1620                                            rx_ring->total_bytes);
1621                 /* if the result for this queue would decrease interrupt
1622                  * rate for this vector then use that result */
1623                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1624                                     q_vector->rx_itr - 1 : ret_itr);
1625                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1626                                       r_idx + 1);
1627         }
1628
1629         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1630
1631         switch (current_itr) {
1632         /* counts and packets in update_itr are dependent on these numbers */
1633         case lowest_latency:
1634                 new_itr = 100000;
1635                 break;
1636         case low_latency:
1637                 new_itr = 20000; /* aka hwitr = ~200 */
1638                 break;
1639         case bulk_latency:
1640         default:
1641                 new_itr = 8000;
1642                 break;
1643         }
1644
1645         if (new_itr != q_vector->eitr) {
1646                 /* do an exponential smoothing */
1647                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1648
1649                 /* save the algorithm value here, not the smoothed one */
1650                 q_vector->eitr = new_itr;
1651
1652                 ixgbe_write_eitr(q_vector);
1653         }
1654 }
1655
1656 /**
1657  * ixgbe_check_overtemp_task - worker thread to check over tempurature
1658  * @work: pointer to work_struct containing our data
1659  **/
1660 static void ixgbe_check_overtemp_task(struct work_struct *work)
1661 {
1662         struct ixgbe_adapter *adapter = container_of(work,
1663                                                      struct ixgbe_adapter,
1664                                                      check_overtemp_task);
1665         struct ixgbe_hw *hw = &adapter->hw;
1666         u32 eicr = adapter->interrupt_event;
1667
1668         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1669                 return;
1670
1671         switch (hw->device_id) {
1672         case IXGBE_DEV_ID_82599_T3_LOM: {
1673                 u32 autoneg;
1674                 bool link_up = false;
1675
1676                 if (hw->mac.ops.check_link)
1677                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1678
1679                 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1680                     (eicr & IXGBE_EICR_LSC))
1681                         /* Check if this is due to overtemp */
1682                         if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1683                                 break;
1684                 return;
1685         }
1686         default:
1687                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1688                         return;
1689                 break;
1690         }
1691         e_crit(drv,
1692                "Network adapter has been stopped because it has over heated. "
1693                "Restart the computer. If the problem persists, "
1694                "power off the system and replace the adapter\n");
1695         /* write to clear the interrupt */
1696         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1697 }
1698
1699 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1700 {
1701         struct ixgbe_hw *hw = &adapter->hw;
1702
1703         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1704             (eicr & IXGBE_EICR_GPI_SDP1)) {
1705                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1706                 /* write to clear the interrupt */
1707                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1708         }
1709 }
1710
1711 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1712 {
1713         struct ixgbe_hw *hw = &adapter->hw;
1714
1715         if (eicr & IXGBE_EICR_GPI_SDP2) {
1716                 /* Clear the interrupt */
1717                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1718                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1719                         schedule_work(&adapter->sfp_config_module_task);
1720         }
1721
1722         if (eicr & IXGBE_EICR_GPI_SDP1) {
1723                 /* Clear the interrupt */
1724                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1725                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1726                         schedule_work(&adapter->multispeed_fiber_task);
1727         }
1728 }
1729
1730 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1731 {
1732         struct ixgbe_hw *hw = &adapter->hw;
1733
1734         adapter->lsc_int++;
1735         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1736         adapter->link_check_timeout = jiffies;
1737         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1738                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1739                 IXGBE_WRITE_FLUSH(hw);
1740                 schedule_work(&adapter->watchdog_task);
1741         }
1742 }
1743
1744 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1745 {
1746         struct net_device *netdev = data;
1747         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1748         struct ixgbe_hw *hw = &adapter->hw;
1749         u32 eicr;
1750
1751         /*
1752          * Workaround for Silicon errata.  Use clear-by-write instead
1753          * of clear-by-read.  Reading with EICS will return the
1754          * interrupt causes without clearing, which later be done
1755          * with the write to EICR.
1756          */
1757         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1758         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1759
1760         if (eicr & IXGBE_EICR_LSC)
1761                 ixgbe_check_lsc(adapter);
1762
1763         if (eicr & IXGBE_EICR_MAILBOX)
1764                 ixgbe_msg_task(adapter);
1765
1766         if (hw->mac.type == ixgbe_mac_82598EB)
1767                 ixgbe_check_fan_failure(adapter, eicr);
1768
1769         if (hw->mac.type == ixgbe_mac_82599EB) {
1770                 ixgbe_check_sfp_event(adapter, eicr);
1771                 adapter->interrupt_event = eicr;
1772                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1773                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1774                         schedule_work(&adapter->check_overtemp_task);
1775
1776                 /* Handle Flow Director Full threshold interrupt */
1777                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1778                         int i;
1779                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1780                         /* Disable transmits before FDIR Re-initialization */
1781                         netif_tx_stop_all_queues(netdev);
1782                         for (i = 0; i < adapter->num_tx_queues; i++) {
1783                                 struct ixgbe_ring *tx_ring =
1784                                                             adapter->tx_ring[i];
1785                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1786                                                        &tx_ring->state))
1787                                         schedule_work(&adapter->fdir_reinit_task);
1788                         }
1789                 }
1790         }
1791         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1792                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1793
1794         return IRQ_HANDLED;
1795 }
1796
1797 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1798                                            u64 qmask)
1799 {
1800         u32 mask;
1801
1802         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1803                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1804                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1805         } else {
1806                 mask = (qmask & 0xFFFFFFFF);
1807                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1808                 mask = (qmask >> 32);
1809                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1810         }
1811         /* skip the flush */
1812 }
1813
1814 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1815                                             u64 qmask)
1816 {
1817         u32 mask;
1818
1819         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1820                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1821                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1822         } else {
1823                 mask = (qmask & 0xFFFFFFFF);
1824                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1825                 mask = (qmask >> 32);
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1827         }
1828         /* skip the flush */
1829 }
1830
1831 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1832 {
1833         struct ixgbe_q_vector *q_vector = data;
1834         struct ixgbe_adapter  *adapter = q_vector->adapter;
1835         struct ixgbe_ring     *tx_ring;
1836         int i, r_idx;
1837
1838         if (!q_vector->txr_count)
1839                 return IRQ_HANDLED;
1840
1841         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1842         for (i = 0; i < q_vector->txr_count; i++) {
1843                 tx_ring = adapter->tx_ring[r_idx];
1844                 tx_ring->total_bytes = 0;
1845                 tx_ring->total_packets = 0;
1846                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1847                                       r_idx + 1);
1848         }
1849
1850         /* EIAM disabled interrupts (on this vector) for us */
1851         napi_schedule(&q_vector->napi);
1852
1853         return IRQ_HANDLED;
1854 }
1855
1856 /**
1857  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1858  * @irq: unused
1859  * @data: pointer to our q_vector struct for this interrupt vector
1860  **/
1861 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1862 {
1863         struct ixgbe_q_vector *q_vector = data;
1864         struct ixgbe_adapter  *adapter = q_vector->adapter;
1865         struct ixgbe_ring  *rx_ring;
1866         int r_idx;
1867         int i;
1868
1869 #ifdef CONFIG_IXGBE_DCA
1870         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1871                 ixgbe_update_dca(q_vector);
1872 #endif
1873
1874         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1875         for (i = 0; i < q_vector->rxr_count; i++) {
1876                 rx_ring = adapter->rx_ring[r_idx];
1877                 rx_ring->total_bytes = 0;
1878                 rx_ring->total_packets = 0;
1879                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1880                                       r_idx + 1);
1881         }
1882
1883         if (!q_vector->rxr_count)
1884                 return IRQ_HANDLED;
1885
1886         /* EIAM disabled interrupts (on this vector) for us */
1887         napi_schedule(&q_vector->napi);
1888
1889         return IRQ_HANDLED;
1890 }
1891
1892 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1893 {
1894         struct ixgbe_q_vector *q_vector = data;
1895         struct ixgbe_adapter  *adapter = q_vector->adapter;
1896         struct ixgbe_ring  *ring;
1897         int r_idx;
1898         int i;
1899
1900         if (!q_vector->txr_count && !q_vector->rxr_count)
1901                 return IRQ_HANDLED;
1902
1903         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1904         for (i = 0; i < q_vector->txr_count; i++) {
1905                 ring = adapter->tx_ring[r_idx];
1906                 ring->total_bytes = 0;
1907                 ring->total_packets = 0;
1908                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1909                                       r_idx + 1);
1910         }
1911
1912         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1913         for (i = 0; i < q_vector->rxr_count; i++) {
1914                 ring = adapter->rx_ring[r_idx];
1915                 ring->total_bytes = 0;
1916                 ring->total_packets = 0;
1917                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1918                                       r_idx + 1);
1919         }
1920
1921         /* EIAM disabled interrupts (on this vector) for us */
1922         napi_schedule(&q_vector->napi);
1923
1924         return IRQ_HANDLED;
1925 }
1926
1927 /**
1928  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1929  * @napi: napi struct with our devices info in it
1930  * @budget: amount of work driver is allowed to do this pass, in packets
1931  *
1932  * This function is optimized for cleaning one queue only on a single
1933  * q_vector!!!
1934  **/
1935 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1936 {
1937         struct ixgbe_q_vector *q_vector =
1938                                container_of(napi, struct ixgbe_q_vector, napi);
1939         struct ixgbe_adapter *adapter = q_vector->adapter;
1940         struct ixgbe_ring *rx_ring = NULL;
1941         int work_done = 0;
1942         long r_idx;
1943
1944 #ifdef CONFIG_IXGBE_DCA
1945         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1946                 ixgbe_update_dca(q_vector);
1947 #endif
1948
1949         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1950         rx_ring = adapter->rx_ring[r_idx];
1951
1952         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1953
1954         /* If all Rx work done, exit the polling mode */
1955         if (work_done < budget) {
1956                 napi_complete(napi);
1957                 if (adapter->rx_itr_setting & 1)
1958                         ixgbe_set_itr_msix(q_vector);
1959                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1960                         ixgbe_irq_enable_queues(adapter,
1961                                                 ((u64)1 << q_vector->v_idx));
1962         }
1963
1964         return work_done;
1965 }
1966
1967 /**
1968  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1969  * @napi: napi struct with our devices info in it
1970  * @budget: amount of work driver is allowed to do this pass, in packets
1971  *
1972  * This function will clean more than one rx queue associated with a
1973  * q_vector.
1974  **/
1975 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1976 {
1977         struct ixgbe_q_vector *q_vector =
1978                                container_of(napi, struct ixgbe_q_vector, napi);
1979         struct ixgbe_adapter *adapter = q_vector->adapter;
1980         struct ixgbe_ring *ring = NULL;
1981         int work_done = 0, i;
1982         long r_idx;
1983         bool tx_clean_complete = true;
1984
1985 #ifdef CONFIG_IXGBE_DCA
1986         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1987                 ixgbe_update_dca(q_vector);
1988 #endif
1989
1990         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1991         for (i = 0; i < q_vector->txr_count; i++) {
1992                 ring = adapter->tx_ring[r_idx];
1993                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1994                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1995                                       r_idx + 1);
1996         }
1997
1998         /* attempt to distribute budget to each queue fairly, but don't allow
1999          * the budget to go below 1 because we'll exit polling */
2000         budget /= (q_vector->rxr_count ?: 1);
2001         budget = max(budget, 1);
2002         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2003         for (i = 0; i < q_vector->rxr_count; i++) {
2004                 ring = adapter->rx_ring[r_idx];
2005                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2006                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2007                                       r_idx + 1);
2008         }
2009
2010         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2011         ring = adapter->rx_ring[r_idx];
2012         /* If all Rx work done, exit the polling mode */
2013         if (work_done < budget) {
2014                 napi_complete(napi);
2015                 if (adapter->rx_itr_setting & 1)
2016                         ixgbe_set_itr_msix(q_vector);
2017                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2018                         ixgbe_irq_enable_queues(adapter,
2019                                                 ((u64)1 << q_vector->v_idx));
2020                 return 0;
2021         }
2022
2023         return work_done;
2024 }
2025
2026 /**
2027  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2028  * @napi: napi struct with our devices info in it
2029  * @budget: amount of work driver is allowed to do this pass, in packets
2030  *
2031  * This function is optimized for cleaning one queue only on a single
2032  * q_vector!!!
2033  **/
2034 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2035 {
2036         struct ixgbe_q_vector *q_vector =
2037                                container_of(napi, struct ixgbe_q_vector, napi);
2038         struct ixgbe_adapter *adapter = q_vector->adapter;
2039         struct ixgbe_ring *tx_ring = NULL;
2040         int work_done = 0;
2041         long r_idx;
2042
2043 #ifdef CONFIG_IXGBE_DCA
2044         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2045                 ixgbe_update_dca(q_vector);
2046 #endif
2047
2048         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2049         tx_ring = adapter->tx_ring[r_idx];
2050
2051         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2052                 work_done = budget;
2053
2054         /* If all Tx work done, exit the polling mode */
2055         if (work_done < budget) {
2056                 napi_complete(napi);
2057                 if (adapter->tx_itr_setting & 1)
2058                         ixgbe_set_itr_msix(q_vector);
2059                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2060                         ixgbe_irq_enable_queues(adapter,
2061                                                 ((u64)1 << q_vector->v_idx));
2062         }
2063
2064         return work_done;
2065 }
2066
2067 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2068                                      int r_idx)
2069 {
2070         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2071
2072         set_bit(r_idx, q_vector->rxr_idx);
2073         q_vector->rxr_count++;
2074 }
2075
2076 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2077                                      int t_idx)
2078 {
2079         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2080
2081         set_bit(t_idx, q_vector->txr_idx);
2082         q_vector->txr_count++;
2083 }
2084
2085 /**
2086  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2087  * @adapter: board private structure to initialize
2088  * @vectors: allotted vector count for descriptor rings
2089  *
2090  * This function maps descriptor rings to the queue-specific vectors
2091  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2092  * one vector per ring/queue, but on a constrained vector budget, we
2093  * group the rings as "efficiently" as possible.  You would add new
2094  * mapping configurations in here.
2095  **/
2096 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2097                                       int vectors)
2098 {
2099         int v_start = 0;
2100         int rxr_idx = 0, txr_idx = 0;
2101         int rxr_remaining = adapter->num_rx_queues;
2102         int txr_remaining = adapter->num_tx_queues;
2103         int i, j;
2104         int rqpv, tqpv;
2105         int err = 0;
2106
2107         /* No mapping required if MSI-X is disabled. */
2108         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2109                 goto out;
2110
2111         /*
2112          * The ideal configuration...
2113          * We have enough vectors to map one per queue.
2114          */
2115         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2116                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2117                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2118
2119                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2120                         map_vector_to_txq(adapter, v_start, txr_idx);
2121
2122                 goto out;
2123         }
2124
2125         /*
2126          * If we don't have enough vectors for a 1-to-1
2127          * mapping, we'll have to group them so there are
2128          * multiple queues per vector.
2129          */
2130         /* Re-adjusting *qpv takes care of the remainder. */
2131         for (i = v_start; i < vectors; i++) {
2132                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2133                 for (j = 0; j < rqpv; j++) {
2134                         map_vector_to_rxq(adapter, i, rxr_idx);
2135                         rxr_idx++;
2136                         rxr_remaining--;
2137                 }
2138         }
2139         for (i = v_start; i < vectors; i++) {
2140                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2141                 for (j = 0; j < tqpv; j++) {
2142                         map_vector_to_txq(adapter, i, txr_idx);
2143                         txr_idx++;
2144                         txr_remaining--;
2145                 }
2146         }
2147
2148 out:
2149         return err;
2150 }
2151
2152 /**
2153  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2154  * @adapter: board private structure
2155  *
2156  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2157  * interrupts from the kernel.
2158  **/
2159 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2160 {
2161         struct net_device *netdev = adapter->netdev;
2162         irqreturn_t (*handler)(int, void *);
2163         int i, vector, q_vectors, err;
2164         int ri = 0, ti = 0;
2165
2166         /* Decrement for Other and TCP Timer vectors */
2167         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2168
2169         /* Map the Tx/Rx rings to the vectors we were allotted. */
2170         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2171         if (err)
2172                 goto out;
2173
2174 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2175                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2176                          &ixgbe_msix_clean_many)
2177         for (vector = 0; vector < q_vectors; vector++) {
2178                 handler = SET_HANDLER(adapter->q_vector[vector]);
2179
2180                 if (handler == &ixgbe_msix_clean_rx) {
2181                         sprintf(adapter->name[vector], "%s-%s-%d",
2182                                 netdev->name, "rx", ri++);
2183                 } else if (handler == &ixgbe_msix_clean_tx) {
2184                         sprintf(adapter->name[vector], "%s-%s-%d",
2185                                 netdev->name, "tx", ti++);
2186                 } else
2187                         sprintf(adapter->name[vector], "%s-%s-%d",
2188                                 netdev->name, "TxRx", vector);
2189
2190                 err = request_irq(adapter->msix_entries[vector].vector,
2191                                   handler, 0, adapter->name[vector],
2192                                   adapter->q_vector[vector]);
2193                 if (err) {
2194                         e_err(probe, "request_irq failed for MSIX interrupt "
2195                               "Error: %d\n", err);
2196                         goto free_queue_irqs;
2197                 }
2198         }
2199
2200         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2201         err = request_irq(adapter->msix_entries[vector].vector,
2202                           ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2203         if (err) {
2204                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2205                 goto free_queue_irqs;
2206         }
2207
2208         return 0;
2209
2210 free_queue_irqs:
2211         for (i = vector - 1; i >= 0; i--)
2212                 free_irq(adapter->msix_entries[--vector].vector,
2213                          adapter->q_vector[i]);
2214         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2215         pci_disable_msix(adapter->pdev);
2216         kfree(adapter->msix_entries);
2217         adapter->msix_entries = NULL;
2218 out:
2219         return err;
2220 }
2221
2222 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2223 {
2224         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2225         u8 current_itr;
2226         u32 new_itr = q_vector->eitr;
2227         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2228         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2229
2230         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2231                                             q_vector->tx_itr,
2232                                             tx_ring->total_packets,
2233                                             tx_ring->total_bytes);
2234         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2235                                             q_vector->rx_itr,
2236                                             rx_ring->total_packets,
2237                                             rx_ring->total_bytes);
2238
2239         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2240
2241         switch (current_itr) {
2242         /* counts and packets in update_itr are dependent on these numbers */
2243         case lowest_latency:
2244                 new_itr = 100000;
2245                 break;
2246         case low_latency:
2247                 new_itr = 20000; /* aka hwitr = ~200 */
2248                 break;
2249         case bulk_latency:
2250                 new_itr = 8000;
2251                 break;
2252         default:
2253                 break;
2254         }
2255
2256         if (new_itr != q_vector->eitr) {
2257                 /* do an exponential smoothing */
2258                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2259
2260                 /* save the algorithm value here, not the smoothed one */
2261                 q_vector->eitr = new_itr;
2262
2263                 ixgbe_write_eitr(q_vector);
2264         }
2265 }
2266
2267 /**
2268  * ixgbe_irq_enable - Enable default interrupt generation settings
2269  * @adapter: board private structure
2270  **/
2271 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2272                                     bool flush)
2273 {
2274         u32 mask;
2275
2276         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2277         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2278                 mask |= IXGBE_EIMS_GPI_SDP0;
2279         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2280                 mask |= IXGBE_EIMS_GPI_SDP1;
2281         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2282                 mask |= IXGBE_EIMS_ECC;
2283                 mask |= IXGBE_EIMS_GPI_SDP1;
2284                 mask |= IXGBE_EIMS_GPI_SDP2;
2285                 if (adapter->num_vfs)
2286                         mask |= IXGBE_EIMS_MAILBOX;
2287         }
2288         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2289             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2290                 mask |= IXGBE_EIMS_FLOW_DIR;
2291
2292         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2293         if (queues)
2294                 ixgbe_irq_enable_queues(adapter, ~0);
2295         if (flush)
2296                 IXGBE_WRITE_FLUSH(&adapter->hw);
2297
2298         if (adapter->num_vfs > 32) {
2299                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2300                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2301         }
2302 }
2303
2304 /**
2305  * ixgbe_intr - legacy mode Interrupt Handler
2306  * @irq: interrupt number
2307  * @data: pointer to a network interface device structure
2308  **/
2309 static irqreturn_t ixgbe_intr(int irq, void *data)
2310 {
2311         struct net_device *netdev = data;
2312         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2313         struct ixgbe_hw *hw = &adapter->hw;
2314         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2315         u32 eicr;
2316
2317         /*
2318          * Workaround for silicon errata on 82598.  Mask the interrupts
2319          * before the read of EICR.
2320          */
2321         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2322
2323         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2324          * therefore no explict interrupt disable is necessary */
2325         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2326         if (!eicr) {
2327                 /*
2328                  * shared interrupt alert!
2329                  * make sure interrupts are enabled because the read will
2330                  * have disabled interrupts due to EIAM
2331                  * finish the workaround of silicon errata on 82598.  Unmask
2332                  * the interrupt that we masked before the EICR read.
2333                  */
2334                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2335                         ixgbe_irq_enable(adapter, true, true);
2336                 return IRQ_NONE;        /* Not our interrupt */
2337         }
2338
2339         if (eicr & IXGBE_EICR_LSC)
2340                 ixgbe_check_lsc(adapter);
2341
2342         if (hw->mac.type == ixgbe_mac_82599EB)
2343                 ixgbe_check_sfp_event(adapter, eicr);
2344
2345         ixgbe_check_fan_failure(adapter, eicr);
2346         if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2347             ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2348                 schedule_work(&adapter->check_overtemp_task);
2349
2350         if (napi_schedule_prep(&(q_vector->napi))) {
2351                 adapter->tx_ring[0]->total_packets = 0;
2352                 adapter->tx_ring[0]->total_bytes = 0;
2353                 adapter->rx_ring[0]->total_packets = 0;
2354                 adapter->rx_ring[0]->total_bytes = 0;
2355                 /* would disable interrupts here but EIAM disabled it */
2356                 __napi_schedule(&(q_vector->napi));
2357         }
2358
2359         /*
2360          * re-enable link(maybe) and non-queue interrupts, no flush.
2361          * ixgbe_poll will re-enable the queue interrupts
2362          */
2363
2364         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2365                 ixgbe_irq_enable(adapter, false, false);
2366
2367         return IRQ_HANDLED;
2368 }
2369
2370 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2371 {
2372         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2373
2374         for (i = 0; i < q_vectors; i++) {
2375                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2376                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2377                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2378                 q_vector->rxr_count = 0;
2379                 q_vector->txr_count = 0;
2380         }
2381 }
2382
2383 /**
2384  * ixgbe_request_irq - initialize interrupts
2385  * @adapter: board private structure
2386  *
2387  * Attempts to configure interrupts using the best available
2388  * capabilities of the hardware and kernel.
2389  **/
2390 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2391 {
2392         struct net_device *netdev = adapter->netdev;
2393         int err;
2394
2395         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2396                 err = ixgbe_request_msix_irqs(adapter);
2397         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2398                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2399                                   netdev->name, netdev);
2400         } else {
2401                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2402                                   netdev->name, netdev);
2403         }
2404
2405         if (err)
2406                 e_err(probe, "request_irq failed, Error %d\n", err);
2407
2408         return err;
2409 }
2410
2411 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2412 {
2413         struct net_device *netdev = adapter->netdev;
2414
2415         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2416                 int i, q_vectors;
2417
2418                 q_vectors = adapter->num_msix_vectors;
2419
2420                 i = q_vectors - 1;
2421                 free_irq(adapter->msix_entries[i].vector, netdev);
2422
2423                 i--;
2424                 for (; i >= 0; i--) {
2425                         free_irq(adapter->msix_entries[i].vector,
2426                                  adapter->q_vector[i]);
2427                 }
2428
2429                 ixgbe_reset_q_vectors(adapter);
2430         } else {
2431                 free_irq(adapter->pdev->irq, netdev);
2432         }
2433 }
2434
2435 /**
2436  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2437  * @adapter: board private structure
2438  **/
2439 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2440 {
2441         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2442                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2443         } else {
2444                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2445                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2446                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2447                 if (adapter->num_vfs > 32)
2448                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2449         }
2450         IXGBE_WRITE_FLUSH(&adapter->hw);
2451         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2452                 int i;
2453                 for (i = 0; i < adapter->num_msix_vectors; i++)
2454                         synchronize_irq(adapter->msix_entries[i].vector);
2455         } else {
2456                 synchronize_irq(adapter->pdev->irq);
2457         }
2458 }
2459
2460 /**
2461  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2462  *
2463  **/
2464 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2465 {
2466         struct ixgbe_hw *hw = &adapter->hw;
2467
2468         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2469                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2470
2471         ixgbe_set_ivar(adapter, 0, 0, 0);
2472         ixgbe_set_ivar(adapter, 1, 0, 0);
2473
2474         map_vector_to_rxq(adapter, 0, 0);
2475         map_vector_to_txq(adapter, 0, 0);
2476
2477         e_info(hw, "Legacy interrupt IVAR setup done\n");
2478 }
2479
2480 /**
2481  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2482  * @adapter: board private structure
2483  * @ring: structure containing ring specific data
2484  *
2485  * Configure the Tx descriptor ring after a reset.
2486  **/
2487 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2488                              struct ixgbe_ring *ring)
2489 {
2490         struct ixgbe_hw *hw = &adapter->hw;
2491         u64 tdba = ring->dma;
2492         int wait_loop = 10;
2493         u32 txdctl;
2494         u16 reg_idx = ring->reg_idx;
2495
2496         /* disable queue to avoid issues while updating state */
2497         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2498         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2499                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2500         IXGBE_WRITE_FLUSH(hw);
2501
2502         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2503                         (tdba & DMA_BIT_MASK(32)));
2504         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2505         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2506                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2507         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2508         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2509         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2510
2511         /* configure fetching thresholds */
2512         if (adapter->rx_itr_setting == 0) {
2513                 /* cannot set wthresh when itr==0 */
2514                 txdctl &= ~0x007F0000;
2515         } else {
2516                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2517                 txdctl |= (8 << 16);
2518         }
2519         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2520                 /* PThresh workaround for Tx hang with DFP enabled. */
2521                 txdctl |= 32;
2522         }
2523
2524         /* reinitialize flowdirector state */
2525         set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2526
2527         /* enable queue */
2528         txdctl |= IXGBE_TXDCTL_ENABLE;
2529         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2530
2531         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2532         if (hw->mac.type == ixgbe_mac_82598EB &&
2533             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2534                 return;
2535
2536         /* poll to verify queue is enabled */
2537         do {
2538                 msleep(1);
2539                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2540         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2541         if (!wait_loop)
2542                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2543 }
2544
2545 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2546 {
2547         struct ixgbe_hw *hw = &adapter->hw;
2548         u32 rttdcs;
2549         u32 mask;
2550
2551         if (hw->mac.type == ixgbe_mac_82598EB)
2552                 return;
2553
2554         /* disable the arbiter while setting MTQC */
2555         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2556         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2557         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2558
2559         /* set transmit pool layout */
2560         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2561         switch (adapter->flags & mask) {
2562
2563         case (IXGBE_FLAG_SRIOV_ENABLED):
2564                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2565                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2566                 break;
2567
2568         case (IXGBE_FLAG_DCB_ENABLED):
2569                 /* We enable 8 traffic classes, DCB only */
2570                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2571                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2572                 break;
2573
2574         default:
2575                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2576                 break;
2577         }
2578
2579         /* re-enable the arbiter */
2580         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2581         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2582 }
2583
2584 /**
2585  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2586  * @adapter: board private structure
2587  *
2588  * Configure the Tx unit of the MAC after a reset.
2589  **/
2590 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2591 {
2592         struct ixgbe_hw *hw = &adapter->hw;
2593         u32 dmatxctl;
2594         u32 i;
2595
2596         ixgbe_setup_mtqc(adapter);
2597
2598         if (hw->mac.type != ixgbe_mac_82598EB) {
2599                 /* DMATXCTL.EN must be before Tx queues are enabled */
2600                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2601                 dmatxctl |= IXGBE_DMATXCTL_TE;
2602                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2603         }
2604
2605         /* Setup the HW Tx Head and Tail descriptor pointers */
2606         for (i = 0; i < adapter->num_tx_queues; i++)
2607                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2608 }
2609
2610 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2611
2612 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2613                                    struct ixgbe_ring *rx_ring)
2614 {
2615         u32 srrctl;
2616         int index;
2617         struct ixgbe_ring_feature *feature = adapter->ring_feature;
2618
2619         index = rx_ring->reg_idx;
2620         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2621                 unsigned long mask;
2622                 mask = (unsigned long) feature[RING_F_RSS].mask;
2623                 index = index & mask;
2624         }
2625         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2626
2627         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2628         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2629         if (adapter->num_vfs)
2630                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2631
2632         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2633                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2634
2635         if (ring_is_ps_enabled(rx_ring)) {
2636 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2637                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2638 #else
2639                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2640 #endif
2641                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2642         } else {
2643                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2644                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2645                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2646         }
2647
2648         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2649 }
2650
2651 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2652 {
2653         struct ixgbe_hw *hw = &adapter->hw;
2654         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2655                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2656                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2657         u32 mrqc = 0, reta = 0;
2658         u32 rxcsum;
2659         int i, j;
2660         int mask;
2661
2662         /* Fill out hash function seeds */
2663         for (i = 0; i < 10; i++)
2664                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2665
2666         /* Fill out redirection table */
2667         for (i = 0, j = 0; i < 128; i++, j++) {
2668                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2669                         j = 0;
2670                 /* reta = 4-byte sliding window of
2671                  * 0x00..(indices-1)(indices-1)00..etc. */
2672                 reta = (reta << 8) | (j * 0x11);
2673                 if ((i & 3) == 3)
2674                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2675         }
2676
2677         /* Disable indicating checksum in descriptor, enables RSS hash */
2678         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2679         rxcsum |= IXGBE_RXCSUM_PCSD;
2680         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2681
2682         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2683                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2684         else
2685                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2686 #ifdef CONFIG_IXGBE_DCB
2687                                          | IXGBE_FLAG_DCB_ENABLED
2688 #endif
2689                                          | IXGBE_FLAG_SRIOV_ENABLED
2690                                         );
2691
2692         switch (mask) {
2693         case (IXGBE_FLAG_RSS_ENABLED):
2694                 mrqc = IXGBE_MRQC_RSSEN;
2695                 break;
2696         case (IXGBE_FLAG_SRIOV_ENABLED):
2697                 mrqc = IXGBE_MRQC_VMDQEN;
2698                 break;
2699 #ifdef CONFIG_IXGBE_DCB
2700         case (IXGBE_FLAG_DCB_ENABLED):
2701                 mrqc = IXGBE_MRQC_RT8TCEN;
2702                 break;
2703 #endif /* CONFIG_IXGBE_DCB */
2704         default:
2705                 break;
2706         }
2707
2708         /* Perform hash on these packet types */
2709         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2710               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2711               | IXGBE_MRQC_RSS_FIELD_IPV6
2712               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2713
2714         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2715 }
2716
2717 /**
2718  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2719  * @adapter:    address of board private structure
2720  * @index:      index of ring to set
2721  **/
2722 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2723                                    struct ixgbe_ring *ring)
2724 {
2725         struct ixgbe_hw *hw = &adapter->hw;
2726         u32 rscctrl;
2727         int rx_buf_len;
2728         u16 reg_idx = ring->reg_idx;
2729
2730         if (!ring_is_rsc_enabled(ring))
2731                 return;
2732
2733         rx_buf_len = ring->rx_buf_len;
2734         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2735         rscctrl |= IXGBE_RSCCTL_RSCEN;
2736         /*
2737          * we must limit the number of descriptors so that the
2738          * total size of max desc * buf_len is not greater
2739          * than 65535
2740          */
2741         if (ring_is_ps_enabled(ring)) {
2742 #if (MAX_SKB_FRAGS > 16)
2743                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2744 #elif (MAX_SKB_FRAGS > 8)
2745                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2746 #elif (MAX_SKB_FRAGS > 4)
2747                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2748 #else
2749                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2750 #endif
2751         } else {
2752                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2753                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2754                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2755                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2756                 else
2757                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2758         }
2759         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2760 }
2761
2762 /**
2763  *  ixgbe_set_uta - Set unicast filter table address
2764  *  @adapter: board private structure
2765  *
2766  *  The unicast table address is a register array of 32-bit registers.
2767  *  The table is meant to be used in a way similar to how the MTA is used
2768  *  however due to certain limitations in the hardware it is necessary to
2769  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2770  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
2771  **/
2772 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2773 {
2774         struct ixgbe_hw *hw = &adapter->hw;
2775         int i;
2776
2777         /* The UTA table only exists on 82599 hardware and newer */
2778         if (hw->mac.type < ixgbe_mac_82599EB)
2779                 return;
2780
2781         /* we only need to do this if VMDq is enabled */
2782         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2783                 return;
2784
2785         for (i = 0; i < 128; i++)
2786                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2787 }
2788
2789 #define IXGBE_MAX_RX_DESC_POLL 10
2790 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2791                                        struct ixgbe_ring *ring)
2792 {
2793         struct ixgbe_hw *hw = &adapter->hw;
2794         int reg_idx = ring->reg_idx;
2795         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2796         u32 rxdctl;
2797
2798         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2799         if (hw->mac.type == ixgbe_mac_82598EB &&
2800             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2801                 return;
2802
2803         do {
2804                 msleep(1);
2805                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2806         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2807
2808         if (!wait_loop) {
2809                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2810                       "the polling period\n", reg_idx);
2811         }
2812 }
2813
2814 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2815                              struct ixgbe_ring *ring)
2816 {
2817         struct ixgbe_hw *hw = &adapter->hw;
2818         u64 rdba = ring->dma;
2819         u32 rxdctl;
2820         u16 reg_idx = ring->reg_idx;
2821
2822         /* disable queue to avoid issues while updating state */
2823         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2824         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2825                         rxdctl & ~IXGBE_RXDCTL_ENABLE);
2826         IXGBE_WRITE_FLUSH(hw);
2827
2828         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2829         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2830         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2831                         ring->count * sizeof(union ixgbe_adv_rx_desc));
2832         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2833         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2834         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
2835
2836         ixgbe_configure_srrctl(adapter, ring);
2837         ixgbe_configure_rscctl(adapter, ring);
2838
2839         if (hw->mac.type == ixgbe_mac_82598EB) {
2840                 /*
2841                  * enable cache line friendly hardware writes:
2842                  * PTHRESH=32 descriptors (half the internal cache),
2843                  * this also removes ugly rx_no_buffer_count increment
2844                  * HTHRESH=4 descriptors (to minimize latency on fetch)
2845                  * WTHRESH=8 burst writeback up to two cache lines
2846                  */
2847                 rxdctl &= ~0x3FFFFF;
2848                 rxdctl |=  0x080420;
2849         }
2850
2851         /* enable receive descriptor ring */
2852         rxdctl |= IXGBE_RXDCTL_ENABLE;
2853         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2854
2855         ixgbe_rx_desc_queue_enable(adapter, ring);
2856         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
2857 }
2858
2859 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2860 {
2861         struct ixgbe_hw *hw = &adapter->hw;
2862         int p;
2863
2864         /* PSRTYPE must be initialized in non 82598 adapters */
2865         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2866                       IXGBE_PSRTYPE_UDPHDR |
2867                       IXGBE_PSRTYPE_IPV4HDR |
2868                       IXGBE_PSRTYPE_L2HDR |
2869                       IXGBE_PSRTYPE_IPV6HDR;
2870
2871         if (hw->mac.type == ixgbe_mac_82598EB)
2872                 return;
2873
2874         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2875                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2876
2877         for (p = 0; p < adapter->num_rx_pools; p++)
2878                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2879                                 psrtype);
2880 }
2881
2882 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2883 {
2884         struct ixgbe_hw *hw = &adapter->hw;
2885         u32 gcr_ext;
2886         u32 vt_reg_bits;
2887         u32 reg_offset, vf_shift;
2888         u32 vmdctl;
2889
2890         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2891                 return;
2892
2893         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2894         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2895         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2896         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2897
2898         vf_shift = adapter->num_vfs % 32;
2899         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2900
2901         /* Enable only the PF's pool for Tx/Rx */
2902         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2903         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2904         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2905         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2906         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2907
2908         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2909         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2910
2911         /*
2912          * Set up VF register offsets for selected VT Mode,
2913          * i.e. 32 or 64 VFs for SR-IOV
2914          */
2915         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2916         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2917         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2918         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2919
2920         /* enable Tx loopback for VF/PF communication */
2921         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2922 }
2923
2924 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2925 {
2926         struct ixgbe_hw *hw = &adapter->hw;
2927         struct net_device *netdev = adapter->netdev;
2928         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2929         int rx_buf_len;
2930         struct ixgbe_ring *rx_ring;
2931         int i;
2932         u32 mhadd, hlreg0;
2933
2934         /* Decide whether to use packet split mode or not */
2935         /* Do not use packet split if we're in SR-IOV Mode */
2936         if (!adapter->num_vfs)
2937                 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2938
2939         /* Set the RX buffer length according to the mode */
2940         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2941                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2942         } else {
2943                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2944                     (netdev->mtu <= ETH_DATA_LEN))
2945                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2946                 else
2947                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2948         }
2949
2950 #ifdef IXGBE_FCOE
2951         /* adjust max frame to be able to do baby jumbo for FCoE */
2952         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2953             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2954                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2955
2956 #endif /* IXGBE_FCOE */
2957         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2958         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2959                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2960                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2961
2962                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2963         }
2964
2965         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2966         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2967         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2968         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2969
2970         /*
2971          * Setup the HW Rx Head and Tail Descriptor Pointers and
2972          * the Base and Length of the Rx Descriptor Ring
2973          */
2974         for (i = 0; i < adapter->num_rx_queues; i++) {
2975                 rx_ring = adapter->rx_ring[i];
2976                 rx_ring->rx_buf_len = rx_buf_len;
2977
2978                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2979                         set_ring_ps_enabled(rx_ring);
2980                 else
2981                         clear_ring_ps_enabled(rx_ring);
2982
2983                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2984                         set_ring_rsc_enabled(rx_ring);
2985                 else
2986                         clear_ring_rsc_enabled(rx_ring);
2987
2988 #ifdef IXGBE_FCOE
2989                 if (netdev->features & NETIF_F_FCOE_MTU) {
2990                         struct ixgbe_ring_feature *f;
2991                         f = &adapter->ring_feature[RING_F_FCOE];
2992                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2993                                 clear_ring_ps_enabled(rx_ring);
2994                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2995                                         rx_ring->rx_buf_len =
2996                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2997                         } else if (!ring_is_rsc_enabled(rx_ring) &&
2998                                    !ring_is_ps_enabled(rx_ring)) {
2999                                 rx_ring->rx_buf_len =
3000                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3001                         }
3002                 }
3003 #endif /* IXGBE_FCOE */
3004         }
3005
3006 }
3007
3008 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3009 {
3010         struct ixgbe_hw *hw = &adapter->hw;
3011         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3012
3013         switch (hw->mac.type) {
3014         case ixgbe_mac_82598EB:
3015                 /*
3016                  * For VMDq support of different descriptor types or
3017                  * buffer sizes through the use of multiple SRRCTL
3018                  * registers, RDRXCTL.MVMEN must be set to 1
3019                  *
3020                  * also, the manual doesn't mention it clearly but DCA hints
3021                  * will only use queue 0's tags unless this bit is set.  Side
3022                  * effects of setting this bit are only that SRRCTL must be
3023                  * fully programmed [0..15]
3024                  */
3025                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3026                 break;
3027         case ixgbe_mac_82599EB:
3028                 /* Disable RSC for ACK packets */
3029                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3030                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3031                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3032                 /* hardware requires some bits to be set by default */
3033                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3034                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3035                 break;
3036         default:
3037                 /* We should do nothing since we don't know this hardware */
3038                 return;
3039         }
3040
3041         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3042 }
3043
3044 /**
3045  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3046  * @adapter: board private structure
3047  *
3048  * Configure the Rx unit of the MAC after a reset.
3049  **/
3050 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3051 {
3052         struct ixgbe_hw *hw = &adapter->hw;
3053         int i;
3054         u32 rxctrl;
3055
3056         /* disable receives while setting up the descriptors */
3057         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3058         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3059
3060         ixgbe_setup_psrtype(adapter);
3061         ixgbe_setup_rdrxctl(adapter);
3062
3063         /* Program registers for the distribution of queues */
3064         ixgbe_setup_mrqc(adapter);
3065
3066         ixgbe_set_uta(adapter);
3067
3068         /* set_rx_buffer_len must be called before ring initialization */
3069         ixgbe_set_rx_buffer_len(adapter);
3070
3071         /*
3072          * Setup the HW Rx Head and Tail Descriptor Pointers and
3073          * the Base and Length of the Rx Descriptor Ring
3074          */
3075         for (i = 0; i < adapter->num_rx_queues; i++)
3076                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3077
3078         /* disable drop enable for 82598 parts */
3079         if (hw->mac.type == ixgbe_mac_82598EB)
3080                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3081
3082         /* enable all receives */
3083         rxctrl |= IXGBE_RXCTRL_RXEN;
3084         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3085 }
3086
3087 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3088 {
3089         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3090         struct ixgbe_hw *hw = &adapter->hw;
3091         int pool_ndx = adapter->num_vfs;
3092
3093         /* add VID to filter table */
3094         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3095         set_bit(vid, adapter->active_vlans);
3096 }
3097
3098 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3099 {
3100         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3101         struct ixgbe_hw *hw = &adapter->hw;
3102         int pool_ndx = adapter->num_vfs;
3103
3104         /* remove VID from filter table */
3105         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3106         clear_bit(vid, adapter->active_vlans);
3107 }
3108
3109 /**
3110  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3111  * @adapter: driver data
3112  */
3113 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3114 {
3115         struct ixgbe_hw *hw = &adapter->hw;
3116         u32 vlnctrl;
3117
3118         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3119         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3120         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3121 }
3122
3123 /**
3124  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3125  * @adapter: driver data
3126  */
3127 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3128 {
3129         struct ixgbe_hw *hw = &adapter->hw;
3130         u32 vlnctrl;
3131
3132         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3133         vlnctrl |= IXGBE_VLNCTRL_VFE;
3134         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3135         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3136 }
3137
3138 /**
3139  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3140  * @adapter: driver data
3141  */
3142 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3143 {
3144         struct ixgbe_hw *hw = &adapter->hw;
3145         u32 vlnctrl;
3146         int i, j;
3147
3148         switch (hw->mac.type) {
3149         case ixgbe_mac_82598EB:
3150                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3151                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3152                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3153                 break;
3154         case ixgbe_mac_82599EB:
3155                 for (i = 0; i < adapter->num_rx_queues; i++) {
3156                         j = adapter->rx_ring[i]->reg_idx;
3157                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3158                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3159                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3160                 }
3161                 break;
3162         default:
3163                 break;
3164         }
3165 }
3166
3167 /**
3168  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3169  * @adapter: driver data
3170  */
3171 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3172 {
3173         struct ixgbe_hw *hw = &adapter->hw;
3174         u32 vlnctrl;
3175         int i, j;
3176
3177         switch (hw->mac.type) {
3178         case ixgbe_mac_82598EB:
3179                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3180                 vlnctrl |= IXGBE_VLNCTRL_VME;
3181                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3182                 break;
3183         case ixgbe_mac_82599EB:
3184                 for (i = 0; i < adapter->num_rx_queues; i++) {
3185                         j = adapter->rx_ring[i]->reg_idx;
3186                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3187                         vlnctrl |= IXGBE_RXDCTL_VME;
3188                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3189                 }
3190                 break;
3191         default:
3192                 break;
3193         }
3194 }
3195
3196 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3197 {
3198         u16 vid;
3199
3200         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3201
3202         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3203                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3204 }
3205
3206 /**
3207  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3208  * @netdev: network interface device structure
3209  *
3210  * Writes unicast address list to the RAR table.
3211  * Returns: -ENOMEM on failure/insufficient address space
3212  *                0 on no addresses written
3213  *                X on writing X addresses to the RAR table
3214  **/
3215 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3216 {
3217         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3218         struct ixgbe_hw *hw = &adapter->hw;
3219         unsigned int vfn = adapter->num_vfs;
3220         unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3221         int count = 0;
3222
3223         /* return ENOMEM indicating insufficient memory for addresses */
3224         if (netdev_uc_count(netdev) > rar_entries)
3225                 return -ENOMEM;
3226
3227         if (!netdev_uc_empty(netdev) && rar_entries) {
3228                 struct netdev_hw_addr *ha;
3229                 /* return error if we do not support writing to RAR table */
3230                 if (!hw->mac.ops.set_rar)
3231                         return -ENOMEM;
3232
3233                 netdev_for_each_uc_addr(ha, netdev) {
3234                         if (!rar_entries)
3235                                 break;
3236                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3237                                             vfn, IXGBE_RAH_AV);
3238                         count++;
3239                 }
3240         }
3241         /* write the addresses in reverse order to avoid write combining */
3242         for (; rar_entries > 0 ; rar_entries--)
3243                 hw->mac.ops.clear_rar(hw, rar_entries);
3244
3245         return count;
3246 }
3247
3248 /**
3249  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3250  * @netdev: network interface device structure
3251  *
3252  * The set_rx_method entry point is called whenever the unicast/multicast
3253  * address list or the network interface flags are updated.  This routine is
3254  * responsible for configuring the hardware for proper unicast, multicast and
3255  * promiscuous mode.
3256  **/
3257 void ixgbe_set_rx_mode(struct net_device *netdev)
3258 {
3259         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3260         struct ixgbe_hw *hw = &adapter->hw;
3261         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3262         int count;
3263
3264         /* Check for Promiscuous and All Multicast modes */
3265
3266         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3267
3268         /* set all bits that we expect to always be set */
3269         fctrl |= IXGBE_FCTRL_BAM;
3270         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3271         fctrl |= IXGBE_FCTRL_PMCF;
3272
3273         /* clear the bits we are changing the status of */
3274         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3275
3276         if (netdev->flags & IFF_PROMISC) {
3277                 hw->addr_ctrl.user_set_promisc = true;
3278                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3279                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3280                 /* don't hardware filter vlans in promisc mode */
3281                 ixgbe_vlan_filter_disable(adapter);
3282         } else {
3283                 if (netdev->flags & IFF_ALLMULTI) {
3284                         fctrl |= IXGBE_FCTRL_MPE;
3285                         vmolr |= IXGBE_VMOLR_MPE;
3286                 } else {
3287                         /*
3288                          * Write addresses to the MTA, if the attempt fails
3289                          * then we should just turn on promiscous mode so
3290                          * that we can at least receive multicast traffic
3291                          */
3292                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3293                         vmolr |= IXGBE_VMOLR_ROMPE;
3294                 }
3295                 ixgbe_vlan_filter_enable(adapter);
3296                 hw->addr_ctrl.user_set_promisc = false;
3297                 /*
3298                  * Write addresses to available RAR registers, if there is not
3299                  * sufficient space to store all the addresses then enable
3300                  * unicast promiscous mode
3301                  */
3302                 count = ixgbe_write_uc_addr_list(netdev);
3303                 if (count < 0) {
3304                         fctrl |= IXGBE_FCTRL_UPE;
3305                         vmolr |= IXGBE_VMOLR_ROPE;
3306                 }
3307         }
3308
3309         if (adapter->num_vfs) {
3310                 ixgbe_restore_vf_multicasts(adapter);
3311                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3312                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3313                            IXGBE_VMOLR_ROPE);
3314                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3315         }
3316
3317         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3318
3319         if (netdev->features & NETIF_F_HW_VLAN_RX)
3320                 ixgbe_vlan_strip_enable(adapter);
3321         else
3322                 ixgbe_vlan_strip_disable(adapter);
3323 }
3324
3325 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3326 {
3327         int q_idx;
3328         struct ixgbe_q_vector *q_vector;
3329         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3330
3331         /* legacy and MSI only use one vector */
3332         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3333                 q_vectors = 1;
3334
3335         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3336                 struct napi_struct *napi;
3337                 q_vector = adapter->q_vector[q_idx];
3338                 napi = &q_vector->napi;
3339                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3340                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3341                                 if (q_vector->txr_count == 1)
3342                                         napi->poll = &ixgbe_clean_txonly;
3343                                 else if (q_vector->rxr_count == 1)
3344                                         napi->poll = &ixgbe_clean_rxonly;
3345                         }
3346                 }
3347
3348                 napi_enable(napi);
3349         }
3350 }
3351
3352 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3353 {
3354         int q_idx;
3355         struct ixgbe_q_vector *q_vector;
3356         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3357
3358         /* legacy and MSI only use one vector */
3359         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3360                 q_vectors = 1;
3361
3362         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3363                 q_vector = adapter->q_vector[q_idx];
3364                 napi_disable(&q_vector->napi);
3365         }
3366 }
3367
3368 #ifdef CONFIG_IXGBE_DCB
3369 /*
3370  * ixgbe_configure_dcb - Configure DCB hardware
3371  * @adapter: ixgbe adapter struct
3372  *
3373  * This is called by the driver on open to configure the DCB hardware.
3374  * This is also called by the gennetlink interface when reconfiguring
3375  * the DCB state.
3376  */
3377 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3378 {
3379         struct ixgbe_hw *hw = &adapter->hw;
3380         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3381
3382         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3383                 if (hw->mac.type == ixgbe_mac_82598EB)
3384                         netif_set_gso_max_size(adapter->netdev, 65536);
3385                 return;
3386         }
3387
3388         if (hw->mac.type == ixgbe_mac_82598EB)
3389                 netif_set_gso_max_size(adapter->netdev, 32768);
3390
3391 #ifdef CONFIG_FCOE
3392         if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3393                 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3394 #endif
3395
3396         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3397                                         DCB_TX_CONFIG);
3398         ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3399                                         DCB_RX_CONFIG);
3400
3401         /* Enable VLAN tag insert/strip */
3402         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3403
3404         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3405
3406         /* reconfigure the hardware */
3407         ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3408 }
3409
3410 #endif
3411 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3412 {
3413         struct net_device *netdev = adapter->netdev;
3414         struct ixgbe_hw *hw = &adapter->hw;
3415         int i;
3416
3417 #ifdef CONFIG_IXGBE_DCB
3418         ixgbe_configure_dcb(adapter);
3419 #endif
3420
3421         ixgbe_set_rx_mode(netdev);
3422         ixgbe_restore_vlan(adapter);
3423
3424 #ifdef IXGBE_FCOE
3425         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3426                 ixgbe_configure_fcoe(adapter);
3427
3428 #endif /* IXGBE_FCOE */
3429         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3430                 for (i = 0; i < adapter->num_tx_queues; i++)
3431                         adapter->tx_ring[i]->atr_sample_rate =
3432                                                        adapter->atr_sample_rate;
3433                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3434         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3435                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3436         }
3437         ixgbe_configure_virtualization(adapter);
3438
3439         ixgbe_configure_tx(adapter);
3440         ixgbe_configure_rx(adapter);
3441 }
3442
3443 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3444 {
3445         switch (hw->phy.type) {
3446         case ixgbe_phy_sfp_avago:
3447         case ixgbe_phy_sfp_ftl:
3448         case ixgbe_phy_sfp_intel:
3449         case ixgbe_phy_sfp_unknown:
3450         case ixgbe_phy_sfp_passive_tyco:
3451         case ixgbe_phy_sfp_passive_unknown:
3452         case ixgbe_phy_sfp_active_unknown:
3453         case ixgbe_phy_sfp_ftl_active:
3454                 return true;
3455         default:
3456                 return false;
3457         }
3458 }
3459
3460 /**
3461  * ixgbe_sfp_link_config - set up SFP+ link
3462  * @adapter: pointer to private adapter struct
3463  **/
3464 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3465 {
3466         struct ixgbe_hw *hw = &adapter->hw;
3467
3468                 if (hw->phy.multispeed_fiber) {
3469                         /*
3470                          * In multispeed fiber setups, the device may not have
3471                          * had a physical connection when the driver loaded.
3472                          * If that's the case, the initial link configuration
3473                          * couldn't get the MAC into 10G or 1G mode, so we'll
3474                          * never have a link status change interrupt fire.
3475                          * We need to try and force an autonegotiation
3476                          * session, then bring up link.
3477                          */
3478                         hw->mac.ops.setup_sfp(hw);
3479                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3480                                 schedule_work(&adapter->multispeed_fiber_task);
3481                 } else {
3482                         /*
3483                          * Direct Attach Cu and non-multispeed fiber modules
3484                          * still need to be configured properly prior to
3485                          * attempting link.
3486                          */
3487                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3488                                 schedule_work(&adapter->sfp_config_module_task);
3489                 }
3490 }
3491
3492 /**
3493  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3494  * @hw: pointer to private hardware struct
3495  *
3496  * Returns 0 on success, negative on failure
3497  **/
3498 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3499 {
3500         u32 autoneg;
3501         bool negotiation, link_up = false;
3502         u32 ret = IXGBE_ERR_LINK_SETUP;
3503
3504         if (hw->mac.ops.check_link)
3505                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3506
3507         if (ret)
3508                 goto link_cfg_out;
3509
3510         if (hw->mac.ops.get_link_capabilities)
3511                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3512                                                         &negotiation);
3513         if (ret)
3514                 goto link_cfg_out;
3515
3516         if (hw->mac.ops.setup_link)
3517                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3518 link_cfg_out:
3519         return ret;
3520 }
3521
3522 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3523 {
3524         struct ixgbe_hw *hw = &adapter->hw;
3525         u32 gpie = 0;
3526
3527         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3528                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3529                        IXGBE_GPIE_OCD;
3530                 gpie |= IXGBE_GPIE_EIAME;
3531                 /*
3532                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3533                  * this saves a register write for every interrupt
3534                  */
3535                 switch (hw->mac.type) {
3536                 case ixgbe_mac_82598EB:
3537                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3538                         break;
3539                 default:
3540                 case ixgbe_mac_82599EB:
3541                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3542                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3543                         break;
3544                 }
3545         } else {
3546                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3547                  * specifically only auto mask tx and rx interrupts */
3548                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3549         }
3550
3551         /* XXX: to interrupt immediately for EICS writes, enable this */
3552         /* gpie |= IXGBE_GPIE_EIMEN; */
3553
3554         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3555                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3556                 gpie |= IXGBE_GPIE_VTMODE_64;
3557         }
3558
3559         /* Enable fan failure interrupt */
3560         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3561                 gpie |= IXGBE_SDP1_GPIEN;
3562
3563         if (hw->mac.type == ixgbe_mac_82599EB)
3564                 gpie |= IXGBE_SDP1_GPIEN;
3565                 gpie |= IXGBE_SDP2_GPIEN;
3566
3567         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3568 }
3569
3570 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3571 {
3572         struct ixgbe_hw *hw = &adapter->hw;
3573         int err;
3574         u32 ctrl_ext;
3575
3576         ixgbe_get_hw_control(adapter);
3577         ixgbe_setup_gpie(adapter);
3578
3579         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3580                 ixgbe_configure_msix(adapter);
3581         else
3582                 ixgbe_configure_msi_and_legacy(adapter);
3583
3584         /* enable the optics */
3585         if (hw->phy.multispeed_fiber)
3586                 hw->mac.ops.enable_tx_laser(hw);
3587
3588         clear_bit(__IXGBE_DOWN, &adapter->state);
3589         ixgbe_napi_enable_all(adapter);
3590
3591         if (ixgbe_is_sfp(hw)) {
3592                 ixgbe_sfp_link_config(adapter);
3593         } else {
3594                 err = ixgbe_non_sfp_link_config(hw);
3595                 if (err)
3596                         e_err(probe, "link_config FAILED %d\n", err);
3597         }
3598
3599         /* clear any pending interrupts, may auto mask */
3600         IXGBE_READ_REG(hw, IXGBE_EICR);
3601         ixgbe_irq_enable(adapter, true, true);
3602
3603         /*
3604          * If this adapter has a fan, check to see if we had a failure
3605          * before we enabled the interrupt.
3606          */
3607         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3608                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3609                 if (esdp & IXGBE_ESDP_SDP1)
3610                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3611         }
3612
3613         /*
3614          * For hot-pluggable SFP+ devices, a new SFP+ module may have
3615          * arrived before interrupts were enabled but after probe.  Such
3616          * devices wouldn't have their type identified yet. We need to
3617          * kick off the SFP+ module setup first, then try to bring up link.
3618          * If we're not hot-pluggable SFP+, we just need to configure link
3619          * and bring it up.
3620          */
3621         if (hw->phy.type == ixgbe_phy_unknown)
3622                 schedule_work(&adapter->sfp_config_module_task);
3623
3624         /* enable transmits */
3625         netif_tx_start_all_queues(adapter->netdev);
3626
3627         /* bring the link up in the watchdog, this could race with our first
3628          * link up interrupt but shouldn't be a problem */
3629         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3630         adapter->link_check_timeout = jiffies;
3631         mod_timer(&adapter->watchdog_timer, jiffies);
3632
3633         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3634         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3635         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3636         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3637
3638         return 0;
3639 }
3640
3641 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3642 {
3643         WARN_ON(in_interrupt());
3644         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3645                 msleep(1);
3646         ixgbe_down(adapter);
3647         /*
3648          * If SR-IOV enabled then wait a bit before bringing the adapter
3649          * back up to give the VFs time to respond to the reset.  The
3650          * two second wait is based upon the watchdog timer cycle in
3651          * the VF driver.
3652          */
3653         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3654                 msleep(2000);
3655         ixgbe_up(adapter);
3656         clear_bit(__IXGBE_RESETTING, &adapter->state);
3657 }
3658
3659 int ixgbe_up(struct ixgbe_adapter *adapter)
3660 {
3661         /* hardware has been reset, we need to reload some things */
3662         ixgbe_configure(adapter);
3663
3664         return ixgbe_up_complete(adapter);
3665 }
3666
3667 void ixgbe_reset(struct ixgbe_adapter *adapter)
3668 {
3669         struct ixgbe_hw *hw = &adapter->hw;
3670         int err;
3671
3672         err = hw->mac.ops.init_hw(hw);
3673         switch (err) {
3674         case 0:
3675         case IXGBE_ERR_SFP_NOT_PRESENT:
3676                 break;
3677         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3678                 e_dev_err("master disable timed out\n");
3679                 break;
3680         case IXGBE_ERR_EEPROM_VERSION:
3681                 /* We are running on a pre-production device, log a warning */
3682                 e_dev_warn("This device is a pre-production adapter/LOM. "
3683                            "Please be aware there may be issuesassociated with "
3684                            "your hardware.  If you are experiencing problems "
3685                            "please contact your Intel or hardware "
3686                            "representative who provided you with this "
3687                            "hardware.\n");
3688                 break;
3689         default:
3690                 e_dev_err("Hardware Error: %d\n", err);
3691         }
3692
3693         /* reprogram the RAR[0] in case user changed it. */
3694         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3695                             IXGBE_RAH_AV);
3696 }
3697
3698 /**
3699  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3700  * @rx_ring: ring to free buffers from
3701  **/
3702 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
3703 {
3704         struct device *dev = rx_ring->dev;
3705         unsigned long size;
3706         u16 i;
3707
3708         /* ring already cleared, nothing to do */
3709         if (!rx_ring->rx_buffer_info)
3710                 return;
3711
3712         /* Free all the Rx ring sk_buffs */
3713         for (i = 0; i < rx_ring->count; i++) {
3714                 struct ixgbe_rx_buffer *rx_buffer_info;
3715
3716                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3717                 if (rx_buffer_info->dma) {
3718                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
3719                                          rx_ring->rx_buf_len,
3720                                          DMA_FROM_DEVICE);
3721                         rx_buffer_info->dma = 0;
3722                 }
3723                 if (rx_buffer_info->skb) {
3724                         struct sk_buff *skb = rx_buffer_info->skb;
3725                         rx_buffer_info->skb = NULL;
3726                         do {
3727                                 struct sk_buff *this = skb;
3728                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
3729                                         dma_unmap_single(dev,
3730                                                          IXGBE_RSC_CB(this)->dma,
3731                                                          rx_ring->rx_buf_len,
3732                                                          DMA_FROM_DEVICE);
3733                                         IXGBE_RSC_CB(this)->dma = 0;
3734                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
3735                                 }
3736                                 skb = skb->prev;
3737                                 dev_kfree_skb(this);
3738                         } while (skb);
3739                 }
3740                 if (!rx_buffer_info->page)
3741                         continue;
3742                 if (rx_buffer_info->page_dma) {
3743                         dma_unmap_page(dev, rx_buffer_info->page_dma,
3744                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
3745                         rx_buffer_info->page_dma = 0;
3746                 }
3747                 put_page(rx_buffer_info->page);
3748                 rx_buffer_info->page = NULL;
3749                 rx_buffer_info->page_offset = 0;
3750         }
3751
3752         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3753         memset(rx_ring->rx_buffer_info, 0, size);
3754
3755         /* Zero out the descriptor ring */
3756         memset(rx_ring->desc, 0, rx_ring->size);
3757
3758         rx_ring->next_to_clean = 0;
3759         rx_ring->next_to_use = 0;
3760 }
3761
3762 /**
3763  * ixgbe_clean_tx_ring - Free Tx Buffers
3764  * @tx_ring: ring to be cleaned
3765  **/
3766 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
3767 {
3768         struct ixgbe_tx_buffer *tx_buffer_info;
3769         unsigned long size;
3770         u16 i;
3771
3772         /* ring already cleared, nothing to do */
3773         if (!tx_ring->tx_buffer_info)
3774                 return;
3775
3776         /* Free all the Tx ring sk_buffs */
3777         for (i = 0; i < tx_ring->count; i++) {
3778                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3779                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
3780         }
3781
3782         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3783         memset(tx_ring->tx_buffer_info, 0, size);
3784
3785         /* Zero out the descriptor ring */
3786         memset(tx_ring->desc, 0, tx_ring->size);
3787
3788         tx_ring->next_to_use = 0;
3789         tx_ring->next_to_clean = 0;
3790 }
3791
3792 /**
3793  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3794  * @adapter: board private structure
3795  **/
3796 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3797 {
3798         int i;
3799
3800         for (i = 0; i < adapter->num_rx_queues; i++)
3801                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
3802 }
3803
3804 /**
3805  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3806  * @adapter: board private structure
3807  **/
3808 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3809 {
3810         int i;
3811
3812         for (i = 0; i < adapter->num_tx_queues; i++)
3813                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
3814 }
3815
3816 void ixgbe_down(struct ixgbe_adapter *adapter)
3817 {
3818         struct net_device *netdev = adapter->netdev;
3819         struct ixgbe_hw *hw = &adapter->hw;
3820         u32 rxctrl;
3821         u32 txdctl;
3822         int i, j;
3823         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3824
3825         /* signal that we are down to the interrupt handler */
3826         set_bit(__IXGBE_DOWN, &adapter->state);
3827
3828         /* disable receive for all VFs and wait one second */
3829         if (adapter->num_vfs) {
3830                 /* ping all the active vfs to let them know we are going down */
3831                 ixgbe_ping_all_vfs(adapter);
3832
3833                 /* Disable all VFTE/VFRE TX/RX */
3834                 ixgbe_disable_tx_rx(adapter);
3835
3836                 /* Mark all the VFs as inactive */
3837                 for (i = 0 ; i < adapter->num_vfs; i++)
3838                         adapter->vfinfo[i].clear_to_send = 0;
3839         }
3840
3841         /* disable receives */
3842         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3843         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3844
3845         IXGBE_WRITE_FLUSH(hw);
3846         msleep(10);
3847
3848         netif_tx_stop_all_queues(netdev);
3849
3850         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3851         del_timer_sync(&adapter->sfp_timer);
3852         del_timer_sync(&adapter->watchdog_timer);
3853         cancel_work_sync(&adapter->watchdog_task);
3854
3855         netif_carrier_off(netdev);
3856         netif_tx_disable(netdev);
3857
3858         ixgbe_irq_disable(adapter);
3859
3860         ixgbe_napi_disable_all(adapter);
3861
3862         /* Cleanup the affinity_hint CPU mask memory and callback */
3863         for (i = 0; i < num_q_vectors; i++) {
3864                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3865                 /* clear the affinity_mask in the IRQ descriptor */
3866                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3867                 /* release the CPU mask memory */
3868                 free_cpumask_var(q_vector->affinity_mask);
3869         }
3870
3871         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3872             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3873                 cancel_work_sync(&adapter->fdir_reinit_task);
3874
3875         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3876                 cancel_work_sync(&adapter->check_overtemp_task);
3877
3878         /* disable transmits in the hardware now that interrupts are off */
3879         for (i = 0; i < adapter->num_tx_queues; i++) {
3880                 j = adapter->tx_ring[i]->reg_idx;
3881                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3882                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3883                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3884         }
3885         /* Disable the Tx DMA engine on 82599 */
3886         if (hw->mac.type == ixgbe_mac_82599EB)
3887                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3888                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3889                                  ~IXGBE_DMATXCTL_TE));
3890
3891         /* power down the optics */
3892         if (hw->phy.multispeed_fiber)
3893                 hw->mac.ops.disable_tx_laser(hw);
3894
3895         /* clear n-tuple filters that are cached */
3896         ethtool_ntuple_flush(netdev);
3897
3898         if (!pci_channel_offline(adapter->pdev))
3899                 ixgbe_reset(adapter);
3900         ixgbe_clean_all_tx_rings(adapter);
3901         ixgbe_clean_all_rx_rings(adapter);
3902
3903 #ifdef CONFIG_IXGBE_DCA
3904         /* since we reset the hardware DCA settings were cleared */
3905         ixgbe_setup_dca(adapter);
3906 #endif
3907 }
3908
3909 /**
3910  * ixgbe_poll - NAPI Rx polling callback
3911  * @napi: structure for representing this polling device
3912  * @budget: how many packets driver is allowed to clean
3913  *
3914  * This function is used for legacy and MSI, NAPI mode
3915  **/
3916 static int ixgbe_poll(struct napi_struct *napi, int budget)
3917 {
3918         struct ixgbe_q_vector *q_vector =
3919                                 container_of(napi, struct ixgbe_q_vector, napi);
3920         struct ixgbe_adapter *adapter = q_vector->adapter;
3921         int tx_clean_complete, work_done = 0;
3922
3923 #ifdef CONFIG_IXGBE_DCA
3924         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3925                 ixgbe_update_dca(q_vector);
3926 #endif
3927
3928         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3929         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3930
3931         if (!tx_clean_complete)
3932                 work_done = budget;
3933
3934         /* If budget not fully consumed, exit the polling mode */
3935         if (work_done < budget) {
3936                 napi_complete(napi);
3937                 if (adapter->rx_itr_setting & 1)
3938                         ixgbe_set_itr(adapter);
3939                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3940                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3941         }
3942         return work_done;
3943 }
3944
3945 /**
3946  * ixgbe_tx_timeout - Respond to a Tx Hang
3947  * @netdev: network interface device structure
3948  **/
3949 static void ixgbe_tx_timeout(struct net_device *netdev)
3950 {
3951         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3952
3953         /* Do the reset outside of interrupt context */
3954         schedule_work(&adapter->reset_task);
3955 }
3956
3957 static void ixgbe_reset_task(struct work_struct *work)
3958 {
3959         struct ixgbe_adapter *adapter;
3960         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3961
3962         /* If we're already down or resetting, just bail */
3963         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3964             test_bit(__IXGBE_RESETTING, &adapter->state))
3965                 return;
3966
3967         adapter->tx_timeout_count++;
3968
3969         ixgbe_dump(adapter);
3970         netdev_err(adapter->netdev, "Reset adapter\n");
3971         ixgbe_reinit_locked(adapter);
3972 }
3973
3974 #ifdef CONFIG_IXGBE_DCB
3975 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3976 {
3977         bool ret = false;
3978         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3979
3980         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3981                 return ret;
3982
3983         f->mask = 0x7 << 3;
3984         adapter->num_rx_queues = f->indices;
3985         adapter->num_tx_queues = f->indices;
3986         ret = true;
3987
3988         return ret;
3989 }
3990 #endif
3991
3992 /**
3993  * ixgbe_set_rss_queues: Allocate queues for RSS
3994  * @adapter: board private structure to initialize
3995  *
3996  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3997  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3998  *
3999  **/
4000 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4001 {
4002         bool ret = false;
4003         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4004
4005         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4006                 f->mask = 0xF;
4007                 adapter->num_rx_queues = f->indices;
4008                 adapter->num_tx_queues = f->indices;
4009                 ret = true;
4010         } else {
4011                 ret = false;
4012         }
4013
4014         return ret;
4015 }
4016
4017 /**
4018  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4019  * @adapter: board private structure to initialize
4020  *
4021  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4022  * to the original CPU that initiated the Tx session.  This runs in addition
4023  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4024  * Rx load across CPUs using RSS.
4025  *
4026  **/
4027 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4028 {
4029         bool ret = false;
4030         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4031
4032         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4033         f_fdir->mask = 0;
4034
4035         /* Flow Director must have RSS enabled */
4036         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4037             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4038              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4039                 adapter->num_tx_queues = f_fdir->indices;
4040                 adapter->num_rx_queues = f_fdir->indices;
4041                 ret = true;
4042         } else {
4043                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4044                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4045         }
4046         return ret;
4047 }
4048
4049 #ifdef IXGBE_FCOE
4050 /**
4051  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4052  * @adapter: board private structure to initialize
4053  *
4054  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4055  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4056  * rx queues out of the max number of rx queues, instead, it is used as the
4057  * index of the first rx queue used by FCoE.
4058  *
4059  **/
4060 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4061 {
4062         bool ret = false;
4063         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4064
4065         f->indices = min((int)num_online_cpus(), f->indices);
4066         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4067                 adapter->num_rx_queues = 1;
4068                 adapter->num_tx_queues = 1;
4069 #ifdef CONFIG_IXGBE_DCB
4070                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4071                         e_info(probe, "FCoE enabled with DCB\n");
4072                         ixgbe_set_dcb_queues(adapter);
4073                 }
4074 #endif
4075                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4076                         e_info(probe, "FCoE enabled with RSS\n");
4077                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4078                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4079                                 ixgbe_set_fdir_queues(adapter);
4080                         else
4081                                 ixgbe_set_rss_queues(adapter);
4082                 }
4083                 /* adding FCoE rx rings to the end */
4084                 f->mask = adapter->num_rx_queues;
4085                 adapter->num_rx_queues += f->indices;
4086                 adapter->num_tx_queues += f->indices;
4087
4088                 ret = true;
4089         }
4090
4091         return ret;
4092 }
4093
4094 #endif /* IXGBE_FCOE */
4095 /**
4096  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4097  * @adapter: board private structure to initialize
4098  *
4099  * IOV doesn't actually use anything, so just NAK the
4100  * request for now and let the other queue routines
4101  * figure out what to do.
4102  */
4103 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4104 {
4105         return false;
4106 }
4107
4108 /*
4109  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4110  * @adapter: board private structure to initialize
4111  *
4112  * This is the top level queue allocation routine.  The order here is very
4113  * important, starting with the "most" number of features turned on at once,
4114  * and ending with the smallest set of features.  This way large combinations
4115  * can be allocated if they're turned on, and smaller combinations are the
4116  * fallthrough conditions.
4117  *
4118  **/
4119 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4120 {
4121         /* Start with base case */
4122         adapter->num_rx_queues = 1;
4123         adapter->num_tx_queues = 1;
4124         adapter->num_rx_pools = adapter->num_rx_queues;
4125         adapter->num_rx_queues_per_pool = 1;
4126
4127         if (ixgbe_set_sriov_queues(adapter))
4128                 goto done;
4129
4130 #ifdef IXGBE_FCOE
4131         if (ixgbe_set_fcoe_queues(adapter))
4132                 goto done;
4133
4134 #endif /* IXGBE_FCOE */
4135 #ifdef CONFIG_IXGBE_DCB
4136         if (ixgbe_set_dcb_queues(adapter))
4137                 goto done;
4138
4139 #endif
4140         if (ixgbe_set_fdir_queues(adapter))
4141                 goto done;
4142
4143         if (ixgbe_set_rss_queues(adapter))
4144                 goto done;
4145
4146         /* fallback to base case */
4147         adapter->num_rx_queues = 1;
4148         adapter->num_tx_queues = 1;
4149
4150 done:
4151         /* Notify the stack of the (possibly) reduced queue counts. */
4152         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4153         return netif_set_real_num_rx_queues(adapter->netdev,
4154                                             adapter->num_rx_queues);
4155 }
4156
4157 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4158                                        int vectors)
4159 {
4160         int err, vector_threshold;
4161
4162         /* We'll want at least 3 (vector_threshold):
4163          * 1) TxQ[0] Cleanup
4164          * 2) RxQ[0] Cleanup
4165          * 3) Other (Link Status Change, etc.)
4166          * 4) TCP Timer (optional)
4167          */
4168         vector_threshold = MIN_MSIX_COUNT;
4169
4170         /* The more we get, the more we will assign to Tx/Rx Cleanup
4171          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4172          * Right now, we simply care about how many we'll get; we'll
4173          * set them up later while requesting irq's.
4174          */
4175         while (vectors >= vector_threshold) {
4176                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4177                                       vectors);
4178                 if (!err) /* Success in acquiring all requested vectors. */
4179                         break;
4180                 else if (err < 0)
4181                         vectors = 0; /* Nasty failure, quit now */
4182                 else /* err == number of vectors we should try again with */
4183                         vectors = err;
4184         }
4185
4186         if (vectors < vector_threshold) {
4187                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4188                  * This just means we'll go with either a single MSI
4189                  * vector or fall back to legacy interrupts.
4190                  */
4191                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4192                              "Unable to allocate MSI-X interrupts\n");
4193                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4194                 kfree(adapter->msix_entries);
4195                 adapter->msix_entries = NULL;
4196         } else {
4197                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4198                 /*
4199                  * Adjust for only the vectors we'll use, which is minimum
4200                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4201                  * vectors we were allocated.
4202                  */
4203                 adapter->num_msix_vectors = min(vectors,
4204                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4205         }
4206 }
4207
4208 /**
4209  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4210  * @adapter: board private structure to initialize
4211  *
4212  * Cache the descriptor ring offsets for RSS to the assigned rings.
4213  *
4214  **/
4215 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4216 {
4217         int i;
4218         bool ret = false;
4219
4220         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4221                 for (i = 0; i < adapter->num_rx_queues; i++)
4222                         adapter->rx_ring[i]->reg_idx = i;
4223                 for (i = 0; i < adapter->num_tx_queues; i++)
4224                         adapter->tx_ring[i]->reg_idx = i;
4225                 ret = true;
4226         } else {
4227                 ret = false;
4228         }
4229
4230         return ret;
4231 }
4232
4233 #ifdef CONFIG_IXGBE_DCB
4234 /**
4235  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4236  * @adapter: board private structure to initialize
4237  *
4238  * Cache the descriptor ring offsets for DCB to the assigned rings.
4239  *
4240  **/
4241 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4242 {
4243         int i;
4244         bool ret = false;
4245         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4246
4247         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4248                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4249                         /* the number of queues is assumed to be symmetric */
4250                         for (i = 0; i < dcb_i; i++) {
4251                                 adapter->rx_ring[i]->reg_idx = i << 3;
4252                                 adapter->tx_ring[i]->reg_idx = i << 2;
4253                         }
4254                         ret = true;
4255                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4256                         if (dcb_i == 8) {
4257                                 /*
4258                                  * Tx TC0 starts at: descriptor queue 0
4259                                  * Tx TC1 starts at: descriptor queue 32
4260                                  * Tx TC2 starts at: descriptor queue 64
4261                                  * Tx TC3 starts at: descriptor queue 80
4262                                  * Tx TC4 starts at: descriptor queue 96
4263                                  * Tx TC5 starts at: descriptor queue 104
4264                                  * Tx TC6 starts at: descriptor queue 112
4265                                  * Tx TC7 starts at: descriptor queue 120
4266                                  *
4267                                  * Rx TC0-TC7 are offset by 16 queues each
4268                                  */
4269                                 for (i = 0; i < 3; i++) {
4270                                         adapter->tx_ring[i]->reg_idx = i << 5;
4271                                         adapter->rx_ring[i]->reg_idx = i << 4;
4272                                 }
4273                                 for ( ; i < 5; i++) {
4274                                         adapter->tx_ring[i]->reg_idx =
4275                                                                  ((i + 2) << 4);
4276                                         adapter->rx_ring[i]->reg_idx = i << 4;
4277                                 }
4278                                 for ( ; i < dcb_i; i++) {
4279                                         adapter->tx_ring[i]->reg_idx =
4280                                                                  ((i + 8) << 3);
4281                                         adapter->rx_ring[i]->reg_idx = i << 4;
4282                                 }
4283
4284                                 ret = true;
4285                         } else if (dcb_i == 4) {
4286                                 /*
4287                                  * Tx TC0 starts at: descriptor queue 0
4288                                  * Tx TC1 starts at: descriptor queue 64
4289                                  * Tx TC2 starts at: descriptor queue 96
4290                                  * Tx TC3 starts at: descriptor queue 112
4291                                  *
4292                                  * Rx TC0-TC3 are offset by 32 queues each
4293                                  */
4294                                 adapter->tx_ring[0]->reg_idx = 0;
4295                                 adapter->tx_ring[1]->reg_idx = 64;
4296                                 adapter->tx_ring[2]->reg_idx = 96;
4297                                 adapter->tx_ring[3]->reg_idx = 112;
4298                                 for (i = 0 ; i < dcb_i; i++)
4299                                         adapter->rx_ring[i]->reg_idx = i << 5;
4300
4301                                 ret = true;
4302                         } else {
4303                                 ret = false;
4304                         }
4305                 } else {
4306                         ret = false;
4307                 }
4308         } else {
4309                 ret = false;
4310         }
4311
4312         return ret;
4313 }
4314 #endif
4315
4316 /**
4317  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4318  * @adapter: board private structure to initialize
4319  *
4320  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4321  *
4322  **/
4323 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4324 {
4325         int i;
4326         bool ret = false;
4327
4328         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4329             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4330              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4331                 for (i = 0; i < adapter->num_rx_queues; i++)
4332                         adapter->rx_ring[i]->reg_idx = i;
4333                 for (i = 0; i < adapter->num_tx_queues; i++)
4334                         adapter->tx_ring[i]->reg_idx = i;
4335                 ret = true;
4336         }
4337
4338         return ret;
4339 }
4340
4341 #ifdef IXGBE_FCOE
4342 /**
4343  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4344  * @adapter: board private structure to initialize
4345  *
4346  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4347  *
4348  */
4349 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4350 {
4351         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4352         bool ret = false;
4353         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4354
4355         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4356 #ifdef CONFIG_IXGBE_DCB
4357                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4358                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4359
4360                         ixgbe_cache_ring_dcb(adapter);
4361                         /* find out queues in TC for FCoE */
4362                         fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4363                         fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4364                         /*
4365                          * In 82599, the number of Tx queues for each traffic
4366                          * class for both 8-TC and 4-TC modes are:
4367                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4368                          * 8 TCs:  32  32  16  16   8   8   8   8
4369                          * 4 TCs:  64  64  32  32
4370                          * We have max 8 queues for FCoE, where 8 the is
4371                          * FCoE redirection table size. If TC for FCoE is
4372                          * less than or equal to TC3, we have enough queues
4373                          * to add max of 8 queues for FCoE, so we start FCoE
4374                          * tx descriptor from the next one, i.e., reg_idx + 1.
4375                          * If TC for FCoE is above TC3, implying 8 TC mode,
4376                          * and we need 8 for FCoE, we have to take all queues
4377                          * in that traffic class for FCoE.
4378                          */
4379                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4380                                 fcoe_tx_i--;
4381                 }
4382 #endif /* CONFIG_IXGBE_DCB */
4383                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4384                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4385                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4386                                 ixgbe_cache_ring_fdir(adapter);
4387                         else
4388                                 ixgbe_cache_ring_rss(adapter);
4389
4390                         fcoe_rx_i = f->mask;
4391                         fcoe_tx_i = f->mask;
4392                 }
4393                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4394                         adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4395                         adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4396                 }
4397                 ret = true;
4398         }
4399         return ret;
4400 }
4401
4402 #endif /* IXGBE_FCOE */
4403 /**
4404  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4405  * @adapter: board private structure to initialize
4406  *
4407  * SR-IOV doesn't use any descriptor rings but changes the default if
4408  * no other mapping is used.
4409  *
4410  */
4411 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4412 {
4413         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4414         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4415         if (adapter->num_vfs)
4416                 return true;
4417         else
4418                 return false;
4419 }
4420
4421 /**
4422  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4423  * @adapter: board private structure to initialize
4424  *
4425  * Once we know the feature-set enabled for the device, we'll cache
4426  * the register offset the descriptor ring is assigned to.
4427  *
4428  * Note, the order the various feature calls is important.  It must start with
4429  * the "most" features enabled at the same time, then trickle down to the
4430  * least amount of features turned on at once.
4431  **/
4432 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4433 {
4434         /* start with default case */
4435         adapter->rx_ring[0]->reg_idx = 0;
4436         adapter->tx_ring[0]->reg_idx = 0;
4437
4438         if (ixgbe_cache_ring_sriov(adapter))
4439                 return;
4440
4441 #ifdef IXGBE_FCOE
4442         if (ixgbe_cache_ring_fcoe(adapter))
4443                 return;
4444
4445 #endif /* IXGBE_FCOE */
4446 #ifdef CONFIG_IXGBE_DCB
4447         if (ixgbe_cache_ring_dcb(adapter))
4448                 return;
4449
4450 #endif
4451         if (ixgbe_cache_ring_fdir(adapter))
4452                 return;
4453
4454         if (ixgbe_cache_ring_rss(adapter))
4455                 return;
4456 }
4457
4458 /**
4459  * ixgbe_alloc_queues - Allocate memory for all rings
4460  * @adapter: board private structure to initialize
4461  *
4462  * We allocate one ring per queue at run-time since we don't know the
4463  * number of queues at compile-time.  The polling_netdev array is
4464  * intended for Multiqueue, but should work fine with a single queue.
4465  **/
4466 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4467 {
4468         int i;
4469         int rx_count;
4470         int orig_node = adapter->node;
4471
4472         for (i = 0; i < adapter->num_tx_queues; i++) {
4473                 struct ixgbe_ring *ring = adapter->tx_ring[i];
4474                 if (orig_node == -1) {
4475                         int cur_node = next_online_node(adapter->node);
4476                         if (cur_node == MAX_NUMNODES)
4477                                 cur_node = first_online_node;
4478                         adapter->node = cur_node;
4479                 }
4480                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4481                                     adapter->node);
4482                 if (!ring)
4483                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4484                 if (!ring)
4485                         goto err_tx_ring_allocation;
4486                 ring->count = adapter->tx_ring_count;
4487                 ring->queue_index = i;
4488                 ring->dev = &adapter->pdev->dev;
4489                 ring->netdev = adapter->netdev;
4490                 ring->numa_node = adapter->node;
4491
4492                 adapter->tx_ring[i] = ring;
4493         }
4494
4495         /* Restore the adapter's original node */
4496         adapter->node = orig_node;
4497
4498         rx_count = adapter->rx_ring_count;
4499         for (i = 0; i < adapter->num_rx_queues; i++) {
4500                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4501                 if (orig_node == -1) {
4502                         int cur_node = next_online_node(adapter->node);
4503                         if (cur_node == MAX_NUMNODES)
4504                                 cur_node = first_online_node;
4505                         adapter->node = cur_node;
4506                 }
4507                 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4508                                     adapter->node);
4509                 if (!ring)
4510                         ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4511                 if (!ring)
4512                         goto err_rx_ring_allocation;
4513                 ring->count = rx_count;
4514                 ring->queue_index = i;
4515                 ring->dev = &adapter->pdev->dev;
4516                 ring->netdev = adapter->netdev;
4517                 ring->numa_node = adapter->node;
4518
4519                 adapter->rx_ring[i] = ring;
4520         }
4521
4522         /* Restore the adapter's original node */
4523         adapter->node = orig_node;
4524
4525         ixgbe_cache_ring_register(adapter);
4526
4527         return 0;
4528
4529 err_rx_ring_allocation:
4530         for (i = 0; i < adapter->num_tx_queues; i++)
4531                 kfree(adapter->tx_ring[i]);
4532 err_tx_ring_allocation:
4533         return -ENOMEM;
4534 }
4535
4536 /**
4537  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4538  * @adapter: board private structure to initialize
4539  *
4540  * Attempt to configure the interrupts using the best available
4541  * capabilities of the hardware and the kernel.
4542  **/
4543 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4544 {
4545         struct ixgbe_hw *hw = &adapter->hw;
4546         int err = 0;
4547         int vector, v_budget;
4548
4549         /*
4550          * It's easy to be greedy for MSI-X vectors, but it really
4551          * doesn't do us much good if we have a lot more vectors
4552          * than CPU's.  So let's be conservative and only ask for
4553          * (roughly) the same number of vectors as there are CPU's.
4554          */
4555         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4556                        (int)num_online_cpus()) + NON_Q_VECTORS;
4557
4558         /*
4559          * At the same time, hardware can only support a maximum of
4560          * hw.mac->max_msix_vectors vectors.  With features
4561          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4562          * descriptor queues supported by our device.  Thus, we cap it off in
4563          * those rare cases where the cpu count also exceeds our vector limit.
4564          */
4565         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4566
4567         /* A failure in MSI-X entry allocation isn't fatal, but it does
4568          * mean we disable MSI-X capabilities of the adapter. */
4569         adapter->msix_entries = kcalloc(v_budget,
4570                                         sizeof(struct msix_entry), GFP_KERNEL);
4571         if (adapter->msix_entries) {
4572                 for (vector = 0; vector < v_budget; vector++)
4573                         adapter->msix_entries[vector].entry = vector;
4574
4575                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4576
4577                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4578                         goto out;
4579         }
4580
4581         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4582         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4583         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4584         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4585         adapter->atr_sample_rate = 0;
4586         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4587                 ixgbe_disable_sriov(adapter);
4588
4589         err = ixgbe_set_num_queues(adapter);
4590         if (err)
4591                 return err;
4592
4593         err = pci_enable_msi(adapter->pdev);
4594         if (!err) {
4595                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4596         } else {
4597                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4598                              "Unable to allocate MSI interrupt, "
4599                              "falling back to legacy.  Error: %d\n", err);
4600                 /* reset err */
4601                 err = 0;
4602         }
4603
4604 out:
4605         return err;
4606 }
4607
4608 /**
4609  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4610  * @adapter: board private structure to initialize
4611  *
4612  * We allocate one q_vector per queue interrupt.  If allocation fails we
4613  * return -ENOMEM.
4614  **/
4615 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4616 {
4617         int q_idx, num_q_vectors;
4618         struct ixgbe_q_vector *q_vector;
4619         int napi_vectors;
4620         int (*poll)(struct napi_struct *, int);
4621
4622         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4623                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4624                 napi_vectors = adapter->num_rx_queues;
4625                 poll = &ixgbe_clean_rxtx_many;
4626         } else {
4627                 num_q_vectors = 1;
4628                 napi_vectors = 1;
4629                 poll = &ixgbe_poll;
4630         }
4631
4632         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4633                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4634                                         GFP_KERNEL, adapter->node);
4635                 if (!q_vector)
4636                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4637                                            GFP_KERNEL);
4638                 if (!q_vector)
4639                         goto err_out;
4640                 q_vector->adapter = adapter;
4641                 if (q_vector->txr_count && !q_vector->rxr_count)
4642                         q_vector->eitr = adapter->tx_eitr_param;
4643                 else
4644                         q_vector->eitr = adapter->rx_eitr_param;
4645                 q_vector->v_idx = q_idx;
4646                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4647                 adapter->q_vector[q_idx] = q_vector;
4648         }
4649
4650         return 0;
4651
4652 err_out:
4653         while (q_idx) {
4654                 q_idx--;
4655                 q_vector = adapter->q_vector[q_idx];
4656                 netif_napi_del(&q_vector->napi);
4657                 kfree(q_vector);
4658                 adapter->q_vector[q_idx] = NULL;
4659         }
4660         return -ENOMEM;
4661 }
4662
4663 /**
4664  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4665  * @adapter: board private structure to initialize
4666  *
4667  * This function frees the memory allocated to the q_vectors.  In addition if
4668  * NAPI is enabled it will delete any references to the NAPI struct prior
4669  * to freeing the q_vector.
4670  **/
4671 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4672 {
4673         int q_idx, num_q_vectors;
4674
4675         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4676                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4677         else
4678                 num_q_vectors = 1;
4679
4680         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4681                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4682                 adapter->q_vector[q_idx] = NULL;
4683                 netif_napi_del(&q_vector->napi);
4684                 kfree(q_vector);
4685         }
4686 }
4687
4688 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4689 {
4690         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4691                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4692                 pci_disable_msix(adapter->pdev);
4693                 kfree(adapter->msix_entries);
4694                 adapter->msix_entries = NULL;
4695         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4696                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4697                 pci_disable_msi(adapter->pdev);
4698         }
4699 }
4700
4701 /**
4702  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4703  * @adapter: board private structure to initialize
4704  *
4705  * We determine which interrupt scheme to use based on...
4706  * - Kernel support (MSI, MSI-X)
4707  *   - which can be user-defined (via MODULE_PARAM)
4708  * - Hardware queue count (num_*_queues)
4709  *   - defined by miscellaneous hardware support/features (RSS, etc.)
4710  **/
4711 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4712 {
4713         int err;
4714
4715         /* Number of supported queues */
4716         err = ixgbe_set_num_queues(adapter);
4717         if (err)
4718                 return err;
4719
4720         err = ixgbe_set_interrupt_capability(adapter);
4721         if (err) {
4722                 e_dev_err("Unable to setup interrupt capabilities\n");
4723                 goto err_set_interrupt;
4724         }
4725
4726         err = ixgbe_alloc_q_vectors(adapter);
4727         if (err) {
4728                 e_dev_err("Unable to allocate memory for queue vectors\n");
4729                 goto err_alloc_q_vectors;
4730         }
4731
4732         err = ixgbe_alloc_queues(adapter);
4733         if (err) {
4734                 e_dev_err("Unable to allocate memory for queues\n");
4735                 goto err_alloc_queues;
4736         }
4737
4738         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4739                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4740                    adapter->num_rx_queues, adapter->num_tx_queues);
4741
4742         set_bit(__IXGBE_DOWN, &adapter->state);
4743
4744         return 0;
4745
4746 err_alloc_queues:
4747         ixgbe_free_q_vectors(adapter);
4748 err_alloc_q_vectors:
4749         ixgbe_reset_interrupt_capability(adapter);
4750 err_set_interrupt:
4751         return err;
4752 }
4753
4754 static void ring_free_rcu(struct rcu_head *head)
4755 {
4756         kfree(container_of(head, struct ixgbe_ring, rcu));
4757 }
4758
4759 /**
4760  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4761  * @adapter: board private structure to clear interrupt scheme on
4762  *
4763  * We go through and clear interrupt specific resources and reset the structure
4764  * to pre-load conditions
4765  **/
4766 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4767 {
4768         int i;
4769
4770         for (i = 0; i < adapter->num_tx_queues; i++) {
4771                 kfree(adapter->tx_ring[i]);
4772                 adapter->tx_ring[i] = NULL;
4773         }
4774         for (i = 0; i < adapter->num_rx_queues; i++) {
4775                 struct ixgbe_ring *ring = adapter->rx_ring[i];
4776
4777                 /* ixgbe_get_stats64() might access this ring, we must wait
4778                  * a grace period before freeing it.
4779                  */
4780                 call_rcu(&ring->rcu, ring_free_rcu);
4781                 adapter->rx_ring[i] = NULL;
4782         }
4783
4784         ixgbe_free_q_vectors(adapter);
4785         ixgbe_reset_interrupt_capability(adapter);
4786 }
4787
4788 /**
4789  * ixgbe_sfp_timer - worker thread to find a missing module
4790  * @data: pointer to our adapter struct
4791  **/
4792 static void ixgbe_sfp_timer(unsigned long data)
4793 {
4794         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4795
4796         /*
4797          * Do the sfp_timer outside of interrupt context due to the
4798          * delays that sfp+ detection requires
4799          */
4800         schedule_work(&adapter->sfp_task);
4801 }
4802
4803 /**
4804  * ixgbe_sfp_task - worker thread to find a missing module
4805  * @work: pointer to work_struct containing our data
4806  **/
4807 static void ixgbe_sfp_task(struct work_struct *work)
4808 {
4809         struct ixgbe_adapter *adapter = container_of(work,
4810                                                      struct ixgbe_adapter,
4811                                                      sfp_task);
4812         struct ixgbe_hw *hw = &adapter->hw;
4813
4814         if ((hw->phy.type == ixgbe_phy_nl) &&
4815             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4816                 s32 ret = hw->phy.ops.identify_sfp(hw);
4817                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4818                         goto reschedule;
4819                 ret = hw->phy.ops.reset(hw);
4820                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4821                         e_dev_err("failed to initialize because an unsupported "
4822                                   "SFP+ module type was detected.\n");
4823                         e_dev_err("Reload the driver after installing a "
4824                                   "supported module.\n");
4825                         unregister_netdev(adapter->netdev);
4826                 } else {
4827                         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4828                 }
4829                 /* don't need this routine any more */
4830                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4831         }
4832         return;
4833 reschedule:
4834         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4835                 mod_timer(&adapter->sfp_timer,
4836                           round_jiffies(jiffies + (2 * HZ)));
4837 }
4838
4839 /**
4840  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4841  * @adapter: board private structure to initialize
4842  *
4843  * ixgbe_sw_init initializes the Adapter private data structure.
4844  * Fields are initialized based on PCI device information and
4845  * OS network device settings (MTU size).
4846  **/
4847 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4848 {
4849         struct ixgbe_hw *hw = &adapter->hw;
4850         struct pci_dev *pdev = adapter->pdev;
4851         struct net_device *dev = adapter->netdev;
4852         unsigned int rss;
4853 #ifdef CONFIG_IXGBE_DCB
4854         int j;
4855         struct tc_configuration *tc;
4856 #endif
4857         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4858
4859         /* PCI config space info */
4860
4861         hw->vendor_id = pdev->vendor;
4862         hw->device_id = pdev->device;
4863         hw->revision_id = pdev->revision;
4864         hw->subsystem_vendor_id = pdev->subsystem_vendor;
4865         hw->subsystem_device_id = pdev->subsystem_device;
4866
4867         /* Set capability flags */
4868         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4869         adapter->ring_feature[RING_F_RSS].indices = rss;
4870         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4871         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4872         if (hw->mac.type == ixgbe_mac_82598EB) {
4873                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4874                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4875                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4876         } else if (hw->mac.type == ixgbe_mac_82599EB) {
4877                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4878                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4879                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4880                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4881                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4882                 if (dev->features & NETIF_F_NTUPLE) {
4883                         /* Flow Director perfect filter enabled */
4884                         adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4885                         adapter->atr_sample_rate = 0;
4886                         spin_lock_init(&adapter->fdir_perfect_lock);
4887                 } else {
4888                         /* Flow Director hash filters enabled */
4889                         adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4890                         adapter->atr_sample_rate = 20;
4891                 }
4892                 adapter->ring_feature[RING_F_FDIR].indices =
4893                                                          IXGBE_MAX_FDIR_INDICES;
4894                 adapter->fdir_pballoc = 0;
4895 #ifdef IXGBE_FCOE
4896                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4897                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4898                 adapter->ring_feature[RING_F_FCOE].indices = 0;
4899 #ifdef CONFIG_IXGBE_DCB
4900                 /* Default traffic class to use for FCoE */
4901                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4902                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4903 #endif
4904 #endif /* IXGBE_FCOE */
4905         }
4906
4907 #ifdef CONFIG_IXGBE_DCB
4908         /* Configure DCB traffic classes */
4909         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4910                 tc = &adapter->dcb_cfg.tc_config[j];
4911                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4912                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4913                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4914                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4915                 tc->dcb_pfc = pfc_disabled;
4916         }
4917         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4918         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4919         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4920         adapter->dcb_cfg.pfc_mode_enable = false;
4921         adapter->dcb_cfg.round_robin_enable = false;
4922         adapter->dcb_set_bitmap = 0x00;
4923         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4924                            adapter->ring_feature[RING_F_DCB].indices);
4925
4926 #endif
4927
4928         /* default flow control settings */
4929         hw->fc.requested_mode = ixgbe_fc_full;
4930         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
4931 #ifdef CONFIG_DCB
4932         adapter->last_lfc_mode = hw->fc.current_mode;
4933 #endif
4934         hw->fc.high_water = FC_HIGH_WATER(max_frame);
4935         hw->fc.low_water = FC_LOW_WATER(max_frame);
4936         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4937         hw->fc.send_xon = true;
4938         hw->fc.disable_fc_autoneg = false;
4939
4940         /* enable itr by default in dynamic mode */
4941         adapter->rx_itr_setting = 1;
4942         adapter->rx_eitr_param = 20000;
4943         adapter->tx_itr_setting = 1;
4944         adapter->tx_eitr_param = 10000;
4945
4946         /* set defaults for eitr in MegaBytes */
4947         adapter->eitr_low = 10;
4948         adapter->eitr_high = 20;
4949
4950         /* set default ring sizes */
4951         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4952         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4953
4954         /* initialize eeprom parameters */
4955         if (ixgbe_init_eeprom_params_generic(hw)) {
4956                 e_dev_err("EEPROM initialization failed\n");
4957                 return -EIO;
4958         }
4959
4960         /* enable rx csum by default */
4961         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4962
4963         /* get assigned NUMA node */
4964         adapter->node = dev_to_node(&pdev->dev);
4965
4966         set_bit(__IXGBE_DOWN, &adapter->state);
4967
4968         return 0;
4969 }
4970
4971 /**
4972  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4973  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
4974  *
4975  * Return 0 on success, negative on failure
4976  **/
4977 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
4978 {
4979         struct device *dev = tx_ring->dev;
4980         int size;
4981
4982         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4983         tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4984         if (!tx_ring->tx_buffer_info)
4985                 tx_ring->tx_buffer_info = vmalloc(size);
4986         if (!tx_ring->tx_buffer_info)
4987                 goto err;
4988         memset(tx_ring->tx_buffer_info, 0, size);
4989
4990         /* round up to nearest 4K */
4991         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4992         tx_ring->size = ALIGN(tx_ring->size, 4096);
4993
4994         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4995                                            &tx_ring->dma, GFP_KERNEL);
4996         if (!tx_ring->desc)
4997                 goto err;
4998
4999         tx_ring->next_to_use = 0;
5000         tx_ring->next_to_clean = 0;
5001         tx_ring->work_limit = tx_ring->count;
5002         return 0;
5003
5004 err:
5005         vfree(tx_ring->tx_buffer_info);
5006         tx_ring->tx_buffer_info = NULL;
5007         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5008         return -ENOMEM;
5009 }
5010
5011 /**
5012  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5013  * @adapter: board private structure
5014  *
5015  * If this function returns with an error, then it's possible one or
5016  * more of the rings is populated (while the rest are not).  It is the
5017  * callers duty to clean those orphaned rings.
5018  *
5019  * Return 0 on success, negative on failure
5020  **/
5021 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5022 {
5023         int i, err = 0;
5024
5025         for (i = 0; i < adapter->num_tx_queues; i++) {
5026                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5027                 if (!err)
5028                         continue;
5029                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5030                 break;
5031         }
5032
5033         return err;
5034 }
5035
5036 /**
5037  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5038  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5039  *
5040  * Returns 0 on success, negative on failure
5041  **/
5042 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5043 {
5044         struct device *dev = rx_ring->dev;
5045         int size;
5046
5047         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5048         rx_ring->rx_buffer_info = vmalloc_node(size, rx_ring->numa_node);
5049         if (!rx_ring->rx_buffer_info)
5050                 rx_ring->rx_buffer_info = vmalloc(size);
5051         if (!rx_ring->rx_buffer_info)
5052                 goto err;
5053         memset(rx_ring->rx_buffer_info, 0, size);
5054
5055         /* Round up to nearest 4K */
5056         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5057         rx_ring->size = ALIGN(rx_ring->size, 4096);
5058
5059         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5060                                            &rx_ring->dma, GFP_KERNEL);
5061
5062         if (!rx_ring->desc)
5063                 goto err;
5064
5065         rx_ring->next_to_clean = 0;
5066         rx_ring->next_to_use = 0;
5067
5068         return 0;
5069 err:
5070         vfree(rx_ring->rx_buffer_info);
5071         rx_ring->rx_buffer_info = NULL;
5072         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5073         return -ENOMEM;
5074 }
5075
5076 /**
5077  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5078  * @adapter: board private structure
5079  *
5080  * If this function returns with an error, then it's possible one or
5081  * more of the rings is populated (while the rest are not).  It is the
5082  * callers duty to clean those orphaned rings.
5083  *
5084  * Return 0 on success, negative on failure
5085  **/
5086 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5087 {
5088         int i, err = 0;
5089
5090         for (i = 0; i < adapter->num_rx_queues; i++) {
5091                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5092                 if (!err)
5093                         continue;
5094                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5095                 break;
5096         }
5097
5098         return err;
5099 }
5100
5101 /**
5102  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5103  * @tx_ring: Tx descriptor ring for a specific queue
5104  *
5105  * Free all transmit software resources
5106  **/
5107 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5108 {
5109         ixgbe_clean_tx_ring(tx_ring);
5110
5111         vfree(tx_ring->tx_buffer_info);
5112         tx_ring->tx_buffer_info = NULL;
5113
5114         /* if not set, then don't free */
5115         if (!tx_ring->desc)
5116                 return;
5117
5118         dma_free_coherent(tx_ring->dev, tx_ring->size,
5119                           tx_ring->desc, tx_ring->dma);
5120
5121         tx_ring->desc = NULL;
5122 }
5123
5124 /**
5125  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5126  * @adapter: board private structure
5127  *
5128  * Free all transmit software resources
5129  **/
5130 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5131 {
5132         int i;
5133
5134         for (i = 0; i < adapter->num_tx_queues; i++)
5135                 if (adapter->tx_ring[i]->desc)
5136                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5137 }
5138
5139 /**
5140  * ixgbe_free_rx_resources - Free Rx Resources
5141  * @rx_ring: ring to clean the resources from
5142  *
5143  * Free all receive software resources
5144  **/
5145 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5146 {
5147         ixgbe_clean_rx_ring(rx_ring);
5148
5149         vfree(rx_ring->rx_buffer_info);
5150         rx_ring->rx_buffer_info = NULL;
5151
5152         /* if not set, then don't free */
5153         if (!rx_ring->desc)
5154                 return;
5155
5156         dma_free_coherent(rx_ring->dev, rx_ring->size,
5157                           rx_ring->desc, rx_ring->dma);
5158
5159         rx_ring->desc = NULL;
5160 }
5161
5162 /**
5163  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5164  * @adapter: board private structure
5165  *
5166  * Free all receive software resources
5167  **/
5168 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5169 {
5170         int i;
5171
5172         for (i = 0; i < adapter->num_rx_queues; i++)
5173                 if (adapter->rx_ring[i]->desc)
5174                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5175 }
5176
5177 /**
5178  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5179  * @netdev: network interface device structure
5180  * @new_mtu: new value for maximum frame size
5181  *
5182  * Returns 0 on success, negative on failure
5183  **/
5184 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5185 {
5186         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5187         struct ixgbe_hw *hw = &adapter->hw;
5188         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5189
5190         /* MTU < 68 is an error and causes problems on some kernels */
5191         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5192                 return -EINVAL;
5193
5194         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5195         /* must set new MTU before calling down or up */
5196         netdev->mtu = new_mtu;
5197
5198         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5199         hw->fc.low_water = FC_LOW_WATER(max_frame);
5200
5201         if (netif_running(netdev))
5202                 ixgbe_reinit_locked(adapter);
5203
5204         return 0;
5205 }
5206
5207 /**
5208  * ixgbe_open - Called when a network interface is made active
5209  * @netdev: network interface device structure
5210  *
5211  * Returns 0 on success, negative value on failure
5212  *
5213  * The open entry point is called when a network interface is made
5214  * active by the system (IFF_UP).  At this point all resources needed
5215  * for transmit and receive operations are allocated, the interrupt
5216  * handler is registered with the OS, the watchdog timer is started,
5217  * and the stack is notified that the interface is ready.
5218  **/
5219 static int ixgbe_open(struct net_device *netdev)
5220 {
5221         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5222         int err;
5223
5224         /* disallow open during test */
5225         if (test_bit(__IXGBE_TESTING, &adapter->state))
5226                 return -EBUSY;
5227
5228         netif_carrier_off(netdev);
5229
5230         /* allocate transmit descriptors */
5231         err = ixgbe_setup_all_tx_resources(adapter);
5232         if (err)
5233                 goto err_setup_tx;
5234
5235         /* allocate receive descriptors */
5236         err = ixgbe_setup_all_rx_resources(adapter);
5237         if (err)
5238                 goto err_setup_rx;
5239
5240         ixgbe_configure(adapter);
5241
5242         err = ixgbe_request_irq(adapter);
5243         if (err)
5244                 goto err_req_irq;
5245
5246         err = ixgbe_up_complete(adapter);
5247         if (err)
5248                 goto err_up;
5249
5250         netif_tx_start_all_queues(netdev);
5251
5252         return 0;
5253
5254 err_up:
5255         ixgbe_release_hw_control(adapter);
5256         ixgbe_free_irq(adapter);
5257 err_req_irq:
5258 err_setup_rx:
5259         ixgbe_free_all_rx_resources(adapter);
5260 err_setup_tx:
5261         ixgbe_free_all_tx_resources(adapter);
5262         ixgbe_reset(adapter);
5263
5264         return err;
5265 }
5266
5267 /**
5268  * ixgbe_close - Disables a network interface
5269  * @netdev: network interface device structure
5270  *
5271  * Returns 0, this is not allowed to fail
5272  *
5273  * The close entry point is called when an interface is de-activated
5274  * by the OS.  The hardware is still under the drivers control, but
5275  * needs to be disabled.  A global MAC reset is issued to stop the
5276  * hardware, and all transmit and receive resources are freed.
5277  **/
5278 static int ixgbe_close(struct net_device *netdev)
5279 {
5280         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5281
5282         ixgbe_down(adapter);
5283         ixgbe_free_irq(adapter);
5284
5285         ixgbe_free_all_tx_resources(adapter);
5286         ixgbe_free_all_rx_resources(adapter);
5287
5288         ixgbe_release_hw_control(adapter);
5289
5290         return 0;
5291 }
5292
5293 #ifdef CONFIG_PM
5294 static int ixgbe_resume(struct pci_dev *pdev)
5295 {
5296         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5297         struct net_device *netdev = adapter->netdev;
5298         u32 err;
5299
5300         pci_set_power_state(pdev, PCI_D0);
5301         pci_restore_state(pdev);
5302         /*
5303          * pci_restore_state clears dev->state_saved so call
5304          * pci_save_state to restore it.
5305          */
5306         pci_save_state(pdev);
5307
5308         err = pci_enable_device_mem(pdev);
5309         if (err) {
5310                 e_dev_err("Cannot enable PCI device from suspend\n");
5311                 return err;
5312         }
5313         pci_set_master(pdev);
5314
5315         pci_wake_from_d3(pdev, false);
5316
5317         err = ixgbe_init_interrupt_scheme(adapter);
5318         if (err) {
5319                 e_dev_err("Cannot initialize interrupts for device\n");
5320                 return err;
5321         }
5322
5323         ixgbe_reset(adapter);
5324
5325         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5326
5327         if (netif_running(netdev)) {
5328                 err = ixgbe_open(netdev);
5329                 if (err)
5330                         return err;
5331         }
5332
5333         netif_device_attach(netdev);
5334
5335         return 0;
5336 }
5337 #endif /* CONFIG_PM */
5338
5339 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5340 {
5341         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5342         struct net_device *netdev = adapter->netdev;
5343         struct ixgbe_hw *hw = &adapter->hw;
5344         u32 ctrl, fctrl;
5345         u32 wufc = adapter->wol;
5346 #ifdef CONFIG_PM
5347         int retval = 0;
5348 #endif
5349
5350         netif_device_detach(netdev);
5351
5352         if (netif_running(netdev)) {
5353                 ixgbe_down(adapter);
5354                 ixgbe_free_irq(adapter);
5355                 ixgbe_free_all_tx_resources(adapter);
5356                 ixgbe_free_all_rx_resources(adapter);
5357         }
5358
5359         ixgbe_clear_interrupt_scheme(adapter);
5360
5361 #ifdef CONFIG_PM
5362         retval = pci_save_state(pdev);
5363         if (retval)
5364                 return retval;
5365
5366 #endif
5367         if (wufc) {
5368                 ixgbe_set_rx_mode(netdev);
5369
5370                 /* turn on all-multi mode if wake on multicast is enabled */
5371                 if (wufc & IXGBE_WUFC_MC) {
5372                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5373                         fctrl |= IXGBE_FCTRL_MPE;
5374                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5375                 }
5376
5377                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5378                 ctrl |= IXGBE_CTRL_GIO_DIS;
5379                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5380
5381                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5382         } else {
5383                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5384                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5385         }
5386
5387         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5388                 pci_wake_from_d3(pdev, true);
5389         else
5390                 pci_wake_from_d3(pdev, false);
5391
5392         *enable_wake = !!wufc;
5393
5394         ixgbe_release_hw_control(adapter);
5395
5396         pci_disable_device(pdev);
5397
5398         return 0;
5399 }
5400
5401 #ifdef CONFIG_PM
5402 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5403 {
5404         int retval;
5405         bool wake;
5406
5407         retval = __ixgbe_shutdown(pdev, &wake);
5408         if (retval)
5409                 return retval;
5410
5411         if (wake) {
5412                 pci_prepare_to_sleep(pdev);
5413         } else {
5414                 pci_wake_from_d3(pdev, false);
5415                 pci_set_power_state(pdev, PCI_D3hot);
5416         }
5417
5418         return 0;
5419 }
5420 #endif /* CONFIG_PM */
5421
5422 static void ixgbe_shutdown(struct pci_dev *pdev)
5423 {
5424         bool wake;
5425
5426         __ixgbe_shutdown(pdev, &wake);
5427
5428         if (system_state == SYSTEM_POWER_OFF) {
5429                 pci_wake_from_d3(pdev, wake);
5430                 pci_set_power_state(pdev, PCI_D3hot);
5431         }
5432 }
5433
5434 /**
5435  * ixgbe_update_stats - Update the board statistics counters.
5436  * @adapter: board private structure
5437  **/
5438 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5439 {
5440         struct net_device *netdev = adapter->netdev;
5441         struct ixgbe_hw *hw = &adapter->hw;
5442         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5443         u64 total_mpc = 0;
5444         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5445         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5446         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5447         u64 bytes = 0, packets = 0;
5448
5449         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5450             test_bit(__IXGBE_RESETTING, &adapter->state))
5451                 return;
5452
5453         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5454                 u64 rsc_count = 0;
5455                 u64 rsc_flush = 0;
5456                 for (i = 0; i < 16; i++)
5457                         adapter->hw_rx_no_dma_resources +=
5458                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5459                 for (i = 0; i < adapter->num_rx_queues; i++) {
5460                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5461                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5462                 }
5463                 adapter->rsc_total_count = rsc_count;
5464                 adapter->rsc_total_flush = rsc_flush;
5465         }
5466
5467         for (i = 0; i < adapter->num_rx_queues; i++) {
5468                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5469                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5470                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5471                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5472                 bytes += rx_ring->stats.bytes;
5473                 packets += rx_ring->stats.packets;
5474         }
5475         adapter->non_eop_descs = non_eop_descs;
5476         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5477         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5478         netdev->stats.rx_bytes = bytes;
5479         netdev->stats.rx_packets = packets;
5480
5481         bytes = 0;
5482         packets = 0;
5483         /* gather some stats to the adapter struct that are per queue */
5484         for (i = 0; i < adapter->num_tx_queues; i++) {
5485                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5486                 restart_queue += tx_ring->tx_stats.restart_queue;
5487                 tx_busy += tx_ring->tx_stats.tx_busy;
5488                 bytes += tx_ring->stats.bytes;
5489                 packets += tx_ring->stats.packets;
5490         }
5491         adapter->restart_queue = restart_queue;
5492         adapter->tx_busy = tx_busy;
5493         netdev->stats.tx_bytes = bytes;
5494         netdev->stats.tx_packets = packets;
5495
5496         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5497         for (i = 0; i < 8; i++) {
5498                 /* for packet buffers not used, the register should read 0 */
5499                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5500                 missed_rx += mpc;
5501                 hwstats->mpc[i] += mpc;
5502                 total_mpc += hwstats->mpc[i];
5503                 if (hw->mac.type == ixgbe_mac_82598EB)
5504                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5505                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5506                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5507                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5508                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5509                 if (hw->mac.type == ixgbe_mac_82599EB) {
5510                         hwstats->pxonrxc[i] +=
5511                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5512                         hwstats->pxoffrxc[i] +=
5513                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5514                         hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5515                 } else {
5516                         hwstats->pxonrxc[i] +=
5517                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5518                         hwstats->pxoffrxc[i] +=
5519                                 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5520                 }
5521                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5522                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5523         }
5524         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5525         /* work around hardware counting issue */
5526         hwstats->gprc -= missed_rx;
5527
5528         /* 82598 hardware only has a 32 bit counter in the high register */
5529         if (hw->mac.type == ixgbe_mac_82599EB) {
5530                 u64 tmp;
5531                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5532                 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5533                                                 /* 4 high bits of GORC */
5534                 hwstats->gorc += (tmp << 32);
5535                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5536                 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5537                                                 /* 4 high bits of GOTC */
5538                 hwstats->gotc += (tmp << 32);
5539                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5540                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5541                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5542                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5543                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5544                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5545 #ifdef IXGBE_FCOE
5546                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5547                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5548                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5549                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5550                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5551                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5552 #endif /* IXGBE_FCOE */
5553         } else {
5554                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5555                 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5556                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5557                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5558                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5559         }
5560         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5561         hwstats->bprc += bprc;
5562         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5563         if (hw->mac.type == ixgbe_mac_82598EB)
5564                 hwstats->mprc -= bprc;
5565         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5566         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5567         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5568         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5569         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5570         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5571         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5572         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5573         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5574         hwstats->lxontxc += lxon;
5575         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5576         hwstats->lxofftxc += lxoff;
5577         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5578         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5579         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5580         /*
5581          * 82598 errata - tx of flow control packets is included in tx counters
5582          */
5583         xon_off_tot = lxon + lxoff;
5584         hwstats->gptc -= xon_off_tot;
5585         hwstats->mptc -= xon_off_tot;
5586         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5587         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5588         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5589         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5590         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5591         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5592         hwstats->ptc64 -= xon_off_tot;
5593         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5594         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5595         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5596         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5597         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5598         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5599
5600         /* Fill out the OS statistics structure */
5601         netdev->stats.multicast = hwstats->mprc;
5602
5603         /* Rx Errors */
5604         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5605         netdev->stats.rx_dropped = 0;
5606         netdev->stats.rx_length_errors = hwstats->rlec;
5607         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5608         netdev->stats.rx_missed_errors = total_mpc;
5609 }
5610
5611 /**
5612  * ixgbe_watchdog - Timer Call-back
5613  * @data: pointer to adapter cast into an unsigned long
5614  **/
5615 static void ixgbe_watchdog(unsigned long data)
5616 {
5617         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5618         struct ixgbe_hw *hw = &adapter->hw;
5619         u64 eics = 0;
5620         int i;
5621
5622         /*
5623          *  Do the watchdog outside of interrupt context due to the lovely
5624          * delays that some of the newer hardware requires
5625          */
5626
5627         if (test_bit(__IXGBE_DOWN, &adapter->state))
5628                 goto watchdog_short_circuit;
5629
5630         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5631                 /*
5632                  * for legacy and MSI interrupts don't set any bits
5633                  * that are enabled for EIAM, because this operation
5634                  * would set *both* EIMS and EICS for any bit in EIAM
5635                  */
5636                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5637                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5638                 goto watchdog_reschedule;
5639         }
5640
5641         /* get one bit for every active tx/rx interrupt vector */
5642         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5643                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5644                 if (qv->rxr_count || qv->txr_count)
5645                         eics |= ((u64)1 << i);
5646         }
5647
5648         /* Cause software interrupt to ensure rx rings are cleaned */
5649         ixgbe_irq_rearm_queues(adapter, eics);
5650
5651 watchdog_reschedule:
5652         /* Reset the timer */
5653         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5654
5655 watchdog_short_circuit:
5656         schedule_work(&adapter->watchdog_task);
5657 }
5658
5659 /**
5660  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5661  * @work: pointer to work_struct containing our data
5662  **/
5663 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5664 {
5665         struct ixgbe_adapter *adapter = container_of(work,
5666                                                      struct ixgbe_adapter,
5667                                                      multispeed_fiber_task);
5668         struct ixgbe_hw *hw = &adapter->hw;
5669         u32 autoneg;
5670         bool negotiation;
5671
5672         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5673         autoneg = hw->phy.autoneg_advertised;
5674         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5675                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5676         hw->mac.autotry_restart = false;
5677         if (hw->mac.ops.setup_link)
5678                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5679         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5680         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5681 }
5682
5683 /**
5684  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5685  * @work: pointer to work_struct containing our data
5686  **/
5687 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5688 {
5689         struct ixgbe_adapter *adapter = container_of(work,
5690                                                      struct ixgbe_adapter,
5691                                                      sfp_config_module_task);
5692         struct ixgbe_hw *hw = &adapter->hw;
5693         u32 err;
5694
5695         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5696
5697         /* Time for electrical oscillations to settle down */
5698         msleep(100);
5699         err = hw->phy.ops.identify_sfp(hw);
5700
5701         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5702                 e_dev_err("failed to initialize because an unsupported SFP+ "
5703                           "module type was detected.\n");
5704                 e_dev_err("Reload the driver after installing a supported "
5705                           "module.\n");
5706                 unregister_netdev(adapter->netdev);
5707                 return;
5708         }
5709         hw->mac.ops.setup_sfp(hw);
5710
5711         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5712                 /* This will also work for DA Twinax connections */
5713                 schedule_work(&adapter->multispeed_fiber_task);
5714         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5715 }
5716
5717 /**
5718  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5719  * @work: pointer to work_struct containing our data
5720  **/
5721 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5722 {
5723         struct ixgbe_adapter *adapter = container_of(work,
5724                                                      struct ixgbe_adapter,
5725                                                      fdir_reinit_task);
5726         struct ixgbe_hw *hw = &adapter->hw;
5727         int i;
5728
5729         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5730                 for (i = 0; i < adapter->num_tx_queues; i++)
5731                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5732                                 &(adapter->tx_ring[i]->state));
5733         } else {
5734                 e_err(probe, "failed to finish FDIR re-initialization, "
5735                       "ignored adding FDIR ATR filters\n");
5736         }
5737         /* Done FDIR Re-initialization, enable transmits */
5738         netif_tx_start_all_queues(adapter->netdev);
5739 }
5740
5741 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5742
5743 /**
5744  * ixgbe_watchdog_task - worker thread to bring link up
5745  * @work: pointer to work_struct containing our data
5746  **/
5747 static void ixgbe_watchdog_task(struct work_struct *work)
5748 {
5749         struct ixgbe_adapter *adapter = container_of(work,
5750                                                      struct ixgbe_adapter,
5751                                                      watchdog_task);
5752         struct net_device *netdev = adapter->netdev;
5753         struct ixgbe_hw *hw = &adapter->hw;
5754         u32 link_speed;
5755         bool link_up;
5756         int i;
5757         struct ixgbe_ring *tx_ring;
5758         int some_tx_pending = 0;
5759
5760         mutex_lock(&ixgbe_watchdog_lock);
5761
5762         link_up = adapter->link_up;
5763         link_speed = adapter->link_speed;
5764
5765         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5766                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5767                 if (link_up) {
5768 #ifdef CONFIG_DCB
5769                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5770                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5771                                         hw->mac.ops.fc_enable(hw, i);
5772                         } else {
5773                                 hw->mac.ops.fc_enable(hw, 0);
5774                         }
5775 #else
5776                         hw->mac.ops.fc_enable(hw, 0);
5777 #endif
5778                 }
5779
5780                 if (link_up ||
5781                     time_after(jiffies, (adapter->link_check_timeout +
5782                                          IXGBE_TRY_LINK_TIMEOUT))) {
5783                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5784                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5785                 }
5786                 adapter->link_up = link_up;
5787                 adapter->link_speed = link_speed;
5788         }
5789
5790         if (link_up) {
5791                 if (!netif_carrier_ok(netdev)) {
5792                         bool flow_rx, flow_tx;
5793
5794                         if (hw->mac.type == ixgbe_mac_82599EB) {
5795                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5796                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5797                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5798                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5799                         } else {
5800                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5801                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5802                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5803                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5804                         }
5805
5806                         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5807                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5808                                "10 Gbps" :
5809                                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5810                                "1 Gbps" : "unknown speed")),
5811                                ((flow_rx && flow_tx) ? "RX/TX" :
5812                                (flow_rx ? "RX" :
5813                                (flow_tx ? "TX" : "None"))));
5814
5815                         netif_carrier_on(netdev);
5816                 } else {
5817                         /* Force detection of hung controller */
5818                         for (i = 0; i < adapter->num_tx_queues; i++) {
5819                                 tx_ring = adapter->tx_ring[i];
5820                                 set_check_for_tx_hang(tx_ring);
5821                         }
5822                 }
5823         } else {
5824                 adapter->link_up = false;
5825                 adapter->link_speed = 0;
5826                 if (netif_carrier_ok(netdev)) {
5827                         e_info(drv, "NIC Link is Down\n");
5828                         netif_carrier_off(netdev);
5829                 }
5830         }
5831
5832         if (!netif_carrier_ok(netdev)) {
5833                 for (i = 0; i < adapter->num_tx_queues; i++) {
5834                         tx_ring = adapter->tx_ring[i];
5835                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5836                                 some_tx_pending = 1;
5837                                 break;
5838                         }
5839                 }
5840
5841                 if (some_tx_pending) {
5842                         /* We've lost link, so the controller stops DMA,
5843                          * but we've got queued Tx work that's never going
5844                          * to get done, so reset controller to flush Tx.
5845                          * (Do the reset outside of interrupt context).
5846                          */
5847                          schedule_work(&adapter->reset_task);
5848                 }
5849         }
5850
5851         ixgbe_update_stats(adapter);
5852         mutex_unlock(&ixgbe_watchdog_lock);
5853 }
5854
5855 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5856                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5857                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
5858 {
5859         struct ixgbe_adv_tx_context_desc *context_desc;
5860         unsigned int i;
5861         int err;
5862         struct ixgbe_tx_buffer *tx_buffer_info;
5863         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5864         u32 mss_l4len_idx, l4len;
5865
5866         if (skb_is_gso(skb)) {
5867                 if (skb_header_cloned(skb)) {
5868                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5869                         if (err)
5870                                 return err;
5871                 }
5872                 l4len = tcp_hdrlen(skb);
5873                 *hdr_len += l4len;
5874
5875                 if (protocol == htons(ETH_P_IP)) {
5876                         struct iphdr *iph = ip_hdr(skb);
5877                         iph->tot_len = 0;
5878                         iph->check = 0;
5879                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5880                                                                  iph->daddr, 0,
5881                                                                  IPPROTO_TCP,
5882                                                                  0);
5883                 } else if (skb_is_gso_v6(skb)) {
5884                         ipv6_hdr(skb)->payload_len = 0;
5885                         tcp_hdr(skb)->check =
5886                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5887                                              &ipv6_hdr(skb)->daddr,
5888                                              0, IPPROTO_TCP, 0);
5889                 }
5890
5891                 i = tx_ring->next_to_use;
5892
5893                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5894                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5895
5896                 /* VLAN MACLEN IPLEN */
5897                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5898                         vlan_macip_lens |=
5899                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5900                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5901                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5902                 *hdr_len += skb_network_offset(skb);
5903                 vlan_macip_lens |=
5904                     (skb_transport_header(skb) - skb_network_header(skb));
5905                 *hdr_len +=
5906                     (skb_transport_header(skb) - skb_network_header(skb));
5907                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5908                 context_desc->seqnum_seed = 0;
5909
5910                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5911                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5912                                    IXGBE_ADVTXD_DTYP_CTXT);
5913
5914                 if (protocol == htons(ETH_P_IP))
5915                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5916                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5917                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5918
5919                 /* MSS L4LEN IDX */
5920                 mss_l4len_idx =
5921                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5922                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5923                 /* use index 1 for TSO */
5924                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5925                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5926
5927                 tx_buffer_info->time_stamp = jiffies;
5928                 tx_buffer_info->next_to_watch = i;
5929
5930                 i++;
5931                 if (i == tx_ring->count)
5932                         i = 0;
5933                 tx_ring->next_to_use = i;
5934
5935                 return true;
5936         }
5937         return false;
5938 }
5939
5940 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5941                       __be16 protocol)
5942 {
5943         u32 rtn = 0;
5944
5945         switch (protocol) {
5946         case cpu_to_be16(ETH_P_IP):
5947                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5948                 switch (ip_hdr(skb)->protocol) {
5949                 case IPPROTO_TCP:
5950                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5951                         break;
5952                 case IPPROTO_SCTP:
5953                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5954                         break;
5955                 }
5956                 break;
5957         case cpu_to_be16(ETH_P_IPV6):
5958                 /* XXX what about other V6 headers?? */
5959                 switch (ipv6_hdr(skb)->nexthdr) {
5960                 case IPPROTO_TCP:
5961                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5962                         break;
5963                 case IPPROTO_SCTP:
5964                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5965                         break;
5966                 }
5967                 break;
5968         default:
5969                 if (unlikely(net_ratelimit()))
5970                         e_warn(probe, "partial checksum but proto=%x!\n",
5971                                protocol);
5972                 break;
5973         }
5974
5975         return rtn;
5976 }
5977
5978 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5979                           struct ixgbe_ring *tx_ring,
5980                           struct sk_buff *skb, u32 tx_flags,
5981                           __be16 protocol)
5982 {
5983         struct ixgbe_adv_tx_context_desc *context_desc;
5984         unsigned int i;
5985         struct ixgbe_tx_buffer *tx_buffer_info;
5986         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5987
5988         if (skb->ip_summed == CHECKSUM_PARTIAL ||
5989             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5990                 i = tx_ring->next_to_use;
5991                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5992                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5993
5994                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5995                         vlan_macip_lens |=
5996                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5997                 vlan_macip_lens |= (skb_network_offset(skb) <<
5998                                     IXGBE_ADVTXD_MACLEN_SHIFT);
5999                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6000                         vlan_macip_lens |= (skb_transport_header(skb) -
6001                                             skb_network_header(skb));
6002
6003                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6004                 context_desc->seqnum_seed = 0;
6005
6006                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6007                                     IXGBE_ADVTXD_DTYP_CTXT);
6008
6009                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6010                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6011
6012                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6013                 /* use index zero for tx checksum offload */
6014                 context_desc->mss_l4len_idx = 0;
6015
6016                 tx_buffer_info->time_stamp = jiffies;
6017                 tx_buffer_info->next_to_watch = i;
6018
6019                 i++;
6020                 if (i == tx_ring->count)
6021                         i = 0;
6022                 tx_ring->next_to_use = i;
6023
6024                 return true;
6025         }
6026
6027         return false;
6028 }
6029
6030 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6031                         struct ixgbe_ring *tx_ring,
6032                         struct sk_buff *skb, u32 tx_flags,
6033                         unsigned int first, const u8 hdr_len)
6034 {
6035         struct device *dev = tx_ring->dev;
6036         struct ixgbe_tx_buffer *tx_buffer_info;
6037         unsigned int len;
6038         unsigned int total = skb->len;
6039         unsigned int offset = 0, size, count = 0, i;
6040         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6041         unsigned int f;
6042         unsigned int bytecount = skb->len;
6043         u16 gso_segs = 1;
6044
6045         i = tx_ring->next_to_use;
6046
6047         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6048                 /* excluding fcoe_crc_eof for FCoE */
6049                 total -= sizeof(struct fcoe_crc_eof);
6050
6051         len = min(skb_headlen(skb), total);
6052         while (len) {
6053                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6054                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6055
6056                 tx_buffer_info->length = size;
6057                 tx_buffer_info->mapped_as_page = false;
6058                 tx_buffer_info->dma = dma_map_single(dev,
6059                                                      skb->data + offset,
6060                                                      size, DMA_TO_DEVICE);
6061                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6062                         goto dma_error;
6063                 tx_buffer_info->time_stamp = jiffies;
6064                 tx_buffer_info->next_to_watch = i;
6065
6066                 len -= size;
6067                 total -= size;
6068                 offset += size;
6069                 count++;
6070
6071                 if (len) {
6072                         i++;
6073                         if (i == tx_ring->count)
6074                                 i = 0;
6075                 }
6076         }
6077
6078         for (f = 0; f < nr_frags; f++) {
6079                 struct skb_frag_struct *frag;
6080
6081                 frag = &skb_shinfo(skb)->frags[f];
6082                 len = min((unsigned int)frag->size, total);
6083                 offset = frag->page_offset;
6084
6085                 while (len) {
6086                         i++;
6087                         if (i == tx_ring->count)
6088                                 i = 0;
6089
6090                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6091                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6092
6093                         tx_buffer_info->length = size;
6094                         tx_buffer_info->dma = dma_map_page(dev,
6095                                                            frag->page,
6096                                                            offset, size,
6097                                                            DMA_TO_DEVICE);
6098                         tx_buffer_info->mapped_as_page = true;
6099                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6100                                 goto dma_error;
6101                         tx_buffer_info->time_stamp = jiffies;
6102                         tx_buffer_info->next_to_watch = i;
6103
6104                         len -= size;
6105                         total -= size;
6106                         offset += size;
6107                         count++;
6108                 }
6109                 if (total == 0)
6110                         break;
6111         }
6112
6113         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6114                 gso_segs = skb_shinfo(skb)->gso_segs;
6115 #ifdef IXGBE_FCOE
6116         /* adjust for FCoE Sequence Offload */
6117         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6118                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6119                                         skb_shinfo(skb)->gso_size);
6120 #endif /* IXGBE_FCOE */
6121         bytecount += (gso_segs - 1) * hdr_len;
6122
6123         /* multiply data chunks by size of headers */
6124         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6125         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6126         tx_ring->tx_buffer_info[i].skb = skb;
6127         tx_ring->tx_buffer_info[first].next_to_watch = i;
6128
6129         return count;
6130
6131 dma_error:
6132         e_dev_err("TX DMA map failed\n");
6133
6134         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6135         tx_buffer_info->dma = 0;
6136         tx_buffer_info->time_stamp = 0;
6137         tx_buffer_info->next_to_watch = 0;
6138         if (count)
6139                 count--;
6140
6141         /* clear timestamp and dma mappings for remaining portion of packet */
6142         while (count--) {
6143                 if (i == 0)
6144                         i += tx_ring->count;
6145                 i--;
6146                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6147                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6148         }
6149
6150         return 0;
6151 }
6152
6153 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6154                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6155 {
6156         union ixgbe_adv_tx_desc *tx_desc = NULL;
6157         struct ixgbe_tx_buffer *tx_buffer_info;
6158         u32 olinfo_status = 0, cmd_type_len = 0;
6159         unsigned int i;
6160         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6161
6162         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6163
6164         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6165
6166         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6167                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6168
6169         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6170                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6171
6172                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6173                                  IXGBE_ADVTXD_POPTS_SHIFT;
6174
6175                 /* use index 1 context for tso */
6176                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6177                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6178                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6179                                          IXGBE_ADVTXD_POPTS_SHIFT;
6180
6181         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6182                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6183                                  IXGBE_ADVTXD_POPTS_SHIFT;
6184
6185         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6186                 olinfo_status |= IXGBE_ADVTXD_CC;
6187                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6188                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6189                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6190         }
6191
6192         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6193
6194         i = tx_ring->next_to_use;
6195         while (count--) {
6196                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6197                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6198                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6199                 tx_desc->read.cmd_type_len =
6200                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6201                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6202                 i++;
6203                 if (i == tx_ring->count)
6204                         i = 0;
6205         }
6206
6207         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6208
6209         /*
6210          * Force memory writes to complete before letting h/w
6211          * know there are new descriptors to fetch.  (Only
6212          * applicable for weak-ordered memory model archs,
6213          * such as IA-64).
6214          */
6215         wmb();
6216
6217         tx_ring->next_to_use = i;
6218         writel(i, tx_ring->tail);
6219 }
6220
6221 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6222                       int queue, u32 tx_flags, __be16 protocol)
6223 {
6224         struct ixgbe_atr_input atr_input;
6225         struct tcphdr *th;
6226         struct iphdr *iph = ip_hdr(skb);
6227         struct ethhdr *eth = (struct ethhdr *)skb->data;
6228         u16 vlan_id, src_port, dst_port, flex_bytes;
6229         u32 src_ipv4_addr, dst_ipv4_addr;
6230         u8 l4type = 0;
6231
6232         /* Right now, we support IPv4 only */
6233         if (protocol != htons(ETH_P_IP))
6234                 return;
6235         /* check if we're UDP or TCP */
6236         if (iph->protocol == IPPROTO_TCP) {
6237                 th = tcp_hdr(skb);
6238                 src_port = th->source;
6239                 dst_port = th->dest;
6240                 l4type |= IXGBE_ATR_L4TYPE_TCP;
6241                 /* l4type IPv4 type is 0, no need to assign */
6242         } else {
6243                 /* Unsupported L4 header, just bail here */
6244                 return;
6245         }
6246
6247         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6248
6249         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6250                    IXGBE_TX_FLAGS_VLAN_SHIFT;
6251         src_ipv4_addr = iph->saddr;
6252         dst_ipv4_addr = iph->daddr;
6253         flex_bytes = eth->h_proto;
6254
6255         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6256         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6257         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6258         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6259         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6260         /* src and dst are inverted, think how the receiver sees them */
6261         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6262         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6263
6264         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6265         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6266 }
6267
6268 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6269 {
6270         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6271         /* Herbert's original patch had:
6272          *  smp_mb__after_netif_stop_queue();
6273          * but since that doesn't exist yet, just open code it. */
6274         smp_mb();
6275
6276         /* We need to check again in a case another CPU has just
6277          * made room available. */
6278         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6279                 return -EBUSY;
6280
6281         /* A reprieve! - use start_queue because it doesn't call schedule */
6282         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6283         ++tx_ring->tx_stats.restart_queue;
6284         return 0;
6285 }
6286
6287 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6288 {
6289         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6290                 return 0;
6291         return __ixgbe_maybe_stop_tx(tx_ring, size);
6292 }
6293
6294 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6295 {
6296         struct ixgbe_adapter *adapter = netdev_priv(dev);
6297         int txq = smp_processor_id();
6298 #ifdef IXGBE_FCOE
6299         __be16 protocol;
6300
6301         protocol = vlan_get_protocol(skb);
6302
6303         if ((protocol == htons(ETH_P_FCOE)) ||
6304             (protocol == htons(ETH_P_FIP))) {
6305                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6306                         txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6307                         txq += adapter->ring_feature[RING_F_FCOE].mask;
6308                         return txq;
6309 #ifdef CONFIG_IXGBE_DCB
6310                 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6311                         txq = adapter->fcoe.up;
6312                         return txq;
6313 #endif
6314                 }
6315         }
6316 #endif
6317
6318         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6319                 while (unlikely(txq >= dev->real_num_tx_queues))
6320                         txq -= dev->real_num_tx_queues;
6321                 return txq;
6322         }
6323
6324         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6325                 if (skb->priority == TC_PRIO_CONTROL)
6326                         txq = adapter->ring_feature[RING_F_DCB].indices-1;
6327                 else
6328                         txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6329                                >> 13;
6330                 return txq;
6331         }
6332
6333         return skb_tx_hash(dev, skb);
6334 }
6335
6336 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6337                           struct ixgbe_adapter *adapter,
6338                           struct ixgbe_ring *tx_ring)
6339 {
6340         struct net_device *netdev = tx_ring->netdev;
6341         struct netdev_queue *txq;
6342         unsigned int first;
6343         unsigned int tx_flags = 0;
6344         u8 hdr_len = 0;
6345         int tso;
6346         int count = 0;
6347         unsigned int f;
6348         __be16 protocol;
6349
6350         protocol = vlan_get_protocol(skb);
6351
6352         if (vlan_tx_tag_present(skb)) {
6353                 tx_flags |= vlan_tx_tag_get(skb);
6354                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6355                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6356                         tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6357                 }
6358                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6359                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6360         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6361                    skb->priority != TC_PRIO_CONTROL) {
6362                 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6363                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6364                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6365         }
6366
6367 #ifdef IXGBE_FCOE
6368         /* for FCoE with DCB, we force the priority to what
6369          * was specified by the switch */
6370         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6371             (protocol == htons(ETH_P_FCOE) ||
6372              protocol == htons(ETH_P_FIP))) {
6373 #ifdef CONFIG_IXGBE_DCB
6374                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6375                         tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6376                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6377                         tx_flags |= ((adapter->fcoe.up << 13)
6378                                       << IXGBE_TX_FLAGS_VLAN_SHIFT);
6379                 }
6380 #endif
6381                 /* flag for FCoE offloads */
6382                 if (protocol == htons(ETH_P_FCOE))
6383                         tx_flags |= IXGBE_TX_FLAGS_FCOE;
6384         }
6385 #endif
6386
6387         /* four things can cause us to need a context descriptor */
6388         if (skb_is_gso(skb) ||
6389             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6390             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6391             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6392                 count++;
6393
6394         count += TXD_USE_COUNT(skb_headlen(skb));
6395         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6396                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6397
6398         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6399                 tx_ring->tx_stats.tx_busy++;
6400                 return NETDEV_TX_BUSY;
6401         }
6402
6403         first = tx_ring->next_to_use;
6404         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6405 #ifdef IXGBE_FCOE
6406                 /* setup tx offload for FCoE */
6407                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6408                 if (tso < 0) {
6409                         dev_kfree_skb_any(skb);
6410                         return NETDEV_TX_OK;
6411                 }
6412                 if (tso)
6413                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6414 #endif /* IXGBE_FCOE */
6415         } else {
6416                 if (protocol == htons(ETH_P_IP))
6417                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6418                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6419                                 protocol);
6420                 if (tso < 0) {
6421                         dev_kfree_skb_any(skb);
6422                         return NETDEV_TX_OK;
6423                 }
6424
6425                 if (tso)
6426                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6427                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6428                                        protocol) &&
6429                          (skb->ip_summed == CHECKSUM_PARTIAL))
6430                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6431         }
6432
6433         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6434         if (count) {
6435                 /* add the ATR filter if ATR is on */
6436                 if (tx_ring->atr_sample_rate) {
6437                         ++tx_ring->atr_count;
6438                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6439                              test_bit(__IXGBE_TX_FDIR_INIT_DONE,
6440                                       &tx_ring->state)) {
6441                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6442                                           tx_flags, protocol);
6443                                 tx_ring->atr_count = 0;
6444                         }
6445                 }
6446                 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6447                 txq->tx_bytes += skb->len;
6448                 txq->tx_packets++;
6449                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6450                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6451
6452         } else {
6453                 dev_kfree_skb_any(skb);
6454                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6455                 tx_ring->next_to_use = first;
6456         }
6457
6458         return NETDEV_TX_OK;
6459 }
6460
6461 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6462 {
6463         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6464         struct ixgbe_ring *tx_ring;
6465
6466         tx_ring = adapter->tx_ring[skb->queue_mapping];
6467         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6468 }
6469
6470 /**
6471  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6472  * @netdev: network interface device structure
6473  * @p: pointer to an address structure
6474  *
6475  * Returns 0 on success, negative on failure
6476  **/
6477 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6478 {
6479         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6480         struct ixgbe_hw *hw = &adapter->hw;
6481         struct sockaddr *addr = p;
6482
6483         if (!is_valid_ether_addr(addr->sa_data))
6484                 return -EADDRNOTAVAIL;
6485
6486         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6487         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6488
6489         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6490                             IXGBE_RAH_AV);
6491
6492         return 0;
6493 }
6494
6495 static int
6496 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6497 {
6498         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6499         struct ixgbe_hw *hw = &adapter->hw;
6500         u16 value;
6501         int rc;
6502
6503         if (prtad != hw->phy.mdio.prtad)
6504                 return -EINVAL;
6505         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6506         if (!rc)
6507                 rc = value;
6508         return rc;
6509 }
6510
6511 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6512                             u16 addr, u16 value)
6513 {
6514         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6515         struct ixgbe_hw *hw = &adapter->hw;
6516
6517         if (prtad != hw->phy.mdio.prtad)
6518                 return -EINVAL;
6519         return hw->phy.ops.write_reg(hw, addr, devad, value);
6520 }
6521
6522 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6523 {
6524         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6525
6526         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6527 }
6528
6529 /**
6530  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6531  * netdev->dev_addrs
6532  * @netdev: network interface device structure
6533  *
6534  * Returns non-zero on failure
6535  **/
6536 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6537 {
6538         int err = 0;
6539         struct ixgbe_adapter *adapter = netdev_priv(dev);
6540         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6541
6542         if (is_valid_ether_addr(mac->san_addr)) {
6543                 rtnl_lock();
6544                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6545                 rtnl_unlock();
6546         }
6547         return err;
6548 }
6549
6550 /**
6551  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6552  * netdev->dev_addrs
6553  * @netdev: network interface device structure
6554  *
6555  * Returns non-zero on failure
6556  **/
6557 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6558 {
6559         int err = 0;
6560         struct ixgbe_adapter *adapter = netdev_priv(dev);
6561         struct ixgbe_mac_info *mac = &adapter->hw.mac;
6562
6563         if (is_valid_ether_addr(mac->san_addr)) {
6564                 rtnl_lock();
6565                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6566                 rtnl_unlock();
6567         }
6568         return err;
6569 }
6570
6571 #ifdef CONFIG_NET_POLL_CONTROLLER
6572 /*
6573  * Polling 'interrupt' - used by things like netconsole to send skbs
6574  * without having to re-enable interrupts. It's not called while
6575  * the interrupt routine is executing.
6576  */
6577 static void ixgbe_netpoll(struct net_device *netdev)
6578 {
6579         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6580         int i;
6581
6582         /* if interface is down do nothing */
6583         if (test_bit(__IXGBE_DOWN, &adapter->state))
6584                 return;
6585
6586         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6587         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6588                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6589                 for (i = 0; i < num_q_vectors; i++) {
6590                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6591                         ixgbe_msix_clean_many(0, q_vector);
6592                 }
6593         } else {
6594                 ixgbe_intr(adapter->pdev->irq, netdev);
6595         }
6596         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6597 }
6598 #endif
6599
6600 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6601                                                    struct rtnl_link_stats64 *stats)
6602 {
6603         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6604         int i;
6605
6606         /* accurate rx/tx bytes/packets stats */
6607         dev_txq_stats_fold(netdev, stats);
6608         rcu_read_lock();
6609         for (i = 0; i < adapter->num_rx_queues; i++) {
6610                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
6611                 u64 bytes, packets;
6612                 unsigned int start;
6613
6614                 if (ring) {
6615                         do {
6616                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
6617                                 packets = ring->stats.packets;
6618                                 bytes   = ring->stats.bytes;
6619                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6620                         stats->rx_packets += packets;
6621                         stats->rx_bytes   += bytes;
6622                 }
6623         }
6624         rcu_read_unlock();
6625         /* following stats updated by ixgbe_watchdog_task() */
6626         stats->multicast        = netdev->stats.multicast;
6627         stats->rx_errors        = netdev->stats.rx_errors;
6628         stats->rx_length_errors = netdev->stats.rx_length_errors;
6629         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
6630         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6631         return stats;
6632 }
6633
6634
6635 static const struct net_device_ops ixgbe_netdev_ops = {
6636         .ndo_open               = ixgbe_open,
6637         .ndo_stop               = ixgbe_close,
6638         .ndo_start_xmit         = ixgbe_xmit_frame,
6639         .ndo_select_queue       = ixgbe_select_queue,
6640         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
6641         .ndo_set_multicast_list = ixgbe_set_rx_mode,
6642         .ndo_validate_addr      = eth_validate_addr,
6643         .ndo_set_mac_address    = ixgbe_set_mac,
6644         .ndo_change_mtu         = ixgbe_change_mtu,
6645         .ndo_tx_timeout         = ixgbe_tx_timeout,
6646         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
6647         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
6648         .ndo_do_ioctl           = ixgbe_ioctl,
6649         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
6650         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
6651         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
6652         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
6653         .ndo_get_stats64        = ixgbe_get_stats64,
6654 #ifdef CONFIG_NET_POLL_CONTROLLER
6655         .ndo_poll_controller    = ixgbe_netpoll,
6656 #endif
6657 #ifdef IXGBE_FCOE
6658         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6659         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6660         .ndo_fcoe_enable = ixgbe_fcoe_enable,
6661         .ndo_fcoe_disable = ixgbe_fcoe_disable,
6662         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6663 #endif /* IXGBE_FCOE */
6664 };
6665
6666 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6667                            const struct ixgbe_info *ii)
6668 {
6669 #ifdef CONFIG_PCI_IOV
6670         struct ixgbe_hw *hw = &adapter->hw;
6671         int err;
6672
6673         if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6674                 return;
6675
6676         /* The 82599 supports up to 64 VFs per physical function
6677          * but this implementation limits allocation to 63 so that
6678          * basic networking resources are still available to the
6679          * physical function
6680          */
6681         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6682         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6683         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6684         if (err) {
6685                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6686                 goto err_novfs;
6687         }
6688         /* If call to enable VFs succeeded then allocate memory
6689          * for per VF control structures.
6690          */
6691         adapter->vfinfo =
6692                 kcalloc(adapter->num_vfs,
6693                         sizeof(struct vf_data_storage), GFP_KERNEL);
6694         if (adapter->vfinfo) {
6695                 /* Now that we're sure SR-IOV is enabled
6696                  * and memory allocated set up the mailbox parameters
6697                  */
6698                 ixgbe_init_mbx_params_pf(hw);
6699                 memcpy(&hw->mbx.ops, ii->mbx_ops,
6700                        sizeof(hw->mbx.ops));
6701
6702                 /* Disable RSC when in SR-IOV mode */
6703                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6704                                      IXGBE_FLAG2_RSC_ENABLED);
6705                 return;
6706         }
6707
6708         /* Oh oh */
6709         e_err(probe, "Unable to allocate memory for VF Data Storage - "
6710               "SRIOV disabled\n");
6711         pci_disable_sriov(adapter->pdev);
6712
6713 err_novfs:
6714         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6715         adapter->num_vfs = 0;
6716 #endif /* CONFIG_PCI_IOV */
6717 }
6718
6719 /**
6720  * ixgbe_probe - Device Initialization Routine
6721  * @pdev: PCI device information struct
6722  * @ent: entry in ixgbe_pci_tbl
6723  *
6724  * Returns 0 on success, negative on failure
6725  *
6726  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6727  * The OS initialization, configuring of the adapter private structure,
6728  * and a hardware reset occur.
6729  **/
6730 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6731                                  const struct pci_device_id *ent)
6732 {
6733         struct net_device *netdev;
6734         struct ixgbe_adapter *adapter = NULL;
6735         struct ixgbe_hw *hw;
6736         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6737         static int cards_found;
6738         int i, err, pci_using_dac;
6739         unsigned int indices = num_possible_cpus();
6740 #ifdef IXGBE_FCOE
6741         u16 device_caps;
6742 #endif
6743         u32 part_num, eec;
6744
6745         /* Catch broken hardware that put the wrong VF device ID in
6746          * the PCIe SR-IOV capability.
6747          */
6748         if (pdev->is_virtfn) {
6749                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6750                      pci_name(pdev), pdev->vendor, pdev->device);
6751                 return -EINVAL;
6752         }
6753
6754         err = pci_enable_device_mem(pdev);
6755         if (err)
6756                 return err;
6757
6758         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6759             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6760                 pci_using_dac = 1;
6761         } else {
6762                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6763                 if (err) {
6764                         err = dma_set_coherent_mask(&pdev->dev,
6765                                                     DMA_BIT_MASK(32));
6766                         if (err) {
6767                                 dev_err(&pdev->dev,
6768                                         "No usable DMA configuration, aborting\n");
6769                                 goto err_dma;
6770                         }
6771                 }
6772                 pci_using_dac = 0;
6773         }
6774
6775         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6776                                            IORESOURCE_MEM), ixgbe_driver_name);
6777         if (err) {
6778                 dev_err(&pdev->dev,
6779                         "pci_request_selected_regions failed 0x%x\n", err);
6780                 goto err_pci_reg;
6781         }
6782
6783         pci_enable_pcie_error_reporting(pdev);
6784
6785         pci_set_master(pdev);
6786         pci_save_state(pdev);
6787
6788         if (ii->mac == ixgbe_mac_82598EB)
6789                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6790         else
6791                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6792
6793         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6794 #ifdef IXGBE_FCOE
6795         indices += min_t(unsigned int, num_possible_cpus(),
6796                          IXGBE_MAX_FCOE_INDICES);
6797 #endif
6798         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6799         if (!netdev) {
6800                 err = -ENOMEM;
6801                 goto err_alloc_etherdev;
6802         }
6803
6804         SET_NETDEV_DEV(netdev, &pdev->dev);
6805
6806         adapter = netdev_priv(netdev);
6807         pci_set_drvdata(pdev, adapter);
6808
6809         adapter->netdev = netdev;
6810         adapter->pdev = pdev;
6811         hw = &adapter->hw;
6812         hw->back = adapter;
6813         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6814
6815         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6816                               pci_resource_len(pdev, 0));
6817         if (!hw->hw_addr) {
6818                 err = -EIO;
6819                 goto err_ioremap;
6820         }
6821
6822         for (i = 1; i <= 5; i++) {
6823                 if (pci_resource_len(pdev, i) == 0)
6824                         continue;
6825         }
6826
6827         netdev->netdev_ops = &ixgbe_netdev_ops;
6828         ixgbe_set_ethtool_ops(netdev);
6829         netdev->watchdog_timeo = 5 * HZ;
6830         strcpy(netdev->name, pci_name(pdev));
6831
6832         adapter->bd_number = cards_found;
6833
6834         /* Setup hw api */
6835         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6836         hw->mac.type  = ii->mac;
6837
6838         /* EEPROM */
6839         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6840         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6841         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6842         if (!(eec & (1 << 8)))
6843                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6844
6845         /* PHY */
6846         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6847         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6848         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6849         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6850         hw->phy.mdio.mmds = 0;
6851         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6852         hw->phy.mdio.dev = netdev;
6853         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6854         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6855
6856         /* set up this timer and work struct before calling get_invariants
6857          * which might start the timer
6858          */
6859         init_timer(&adapter->sfp_timer);
6860         adapter->sfp_timer.function = ixgbe_sfp_timer;
6861         adapter->sfp_timer.data = (unsigned long) adapter;
6862
6863         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6864
6865         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6866         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6867
6868         /* a new SFP+ module arrival, called from GPI SDP2 context */
6869         INIT_WORK(&adapter->sfp_config_module_task,
6870                   ixgbe_sfp_config_module_task);
6871
6872         ii->get_invariants(hw);
6873
6874         /* setup the private structure */
6875         err = ixgbe_sw_init(adapter);
6876         if (err)
6877                 goto err_sw_init;
6878
6879         /* Make it possible the adapter to be woken up via WOL */
6880         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6881                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6882
6883         /*
6884          * If there is a fan on this device and it has failed log the
6885          * failure.
6886          */
6887         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6888                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6889                 if (esdp & IXGBE_ESDP_SDP1)
6890                         e_crit(probe, "Fan has stopped, replace the adapter\n");
6891         }
6892
6893         /* reset_hw fills in the perm_addr as well */
6894         hw->phy.reset_if_overtemp = true;
6895         err = hw->mac.ops.reset_hw(hw);
6896         hw->phy.reset_if_overtemp = false;
6897         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6898             hw->mac.type == ixgbe_mac_82598EB) {
6899                 /*
6900                  * Start a kernel thread to watch for a module to arrive.
6901                  * Only do this for 82598, since 82599 will generate
6902                  * interrupts on module arrival.
6903                  */
6904                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6905                 mod_timer(&adapter->sfp_timer,
6906                           round_jiffies(jiffies + (2 * HZ)));
6907                 err = 0;
6908         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6909                 e_dev_err("failed to initialize because an unsupported SFP+ "
6910                           "module type was detected.\n");
6911                 e_dev_err("Reload the driver after installing a supported "
6912                           "module.\n");
6913                 goto err_sw_init;
6914         } else if (err) {
6915                 e_dev_err("HW Init failed: %d\n", err);
6916                 goto err_sw_init;
6917         }
6918
6919         ixgbe_probe_vf(adapter, ii);
6920
6921         netdev->features = NETIF_F_SG |
6922                            NETIF_F_IP_CSUM |
6923                            NETIF_F_HW_VLAN_TX |
6924                            NETIF_F_HW_VLAN_RX |
6925                            NETIF_F_HW_VLAN_FILTER;
6926
6927         netdev->features |= NETIF_F_IPV6_CSUM;
6928         netdev->features |= NETIF_F_TSO;
6929         netdev->features |= NETIF_F_TSO6;
6930         netdev->features |= NETIF_F_GRO;
6931
6932         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6933                 netdev->features |= NETIF_F_SCTP_CSUM;
6934
6935         netdev->vlan_features |= NETIF_F_TSO;
6936         netdev->vlan_features |= NETIF_F_TSO6;
6937         netdev->vlan_features |= NETIF_F_IP_CSUM;
6938         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6939         netdev->vlan_features |= NETIF_F_SG;
6940
6941         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6942                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6943                                     IXGBE_FLAG_DCB_ENABLED);
6944         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6945                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6946
6947 #ifdef CONFIG_IXGBE_DCB
6948         netdev->dcbnl_ops = &dcbnl_ops;
6949 #endif
6950
6951 #ifdef IXGBE_FCOE
6952         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6953                 if (hw->mac.ops.get_device_caps) {
6954                         hw->mac.ops.get_device_caps(hw, &device_caps);
6955                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6956                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6957                 }
6958         }
6959         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6960                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6961                 netdev->vlan_features |= NETIF_F_FSO;
6962                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6963         }
6964 #endif /* IXGBE_FCOE */
6965         if (pci_using_dac) {
6966                 netdev->features |= NETIF_F_HIGHDMA;
6967                 netdev->vlan_features |= NETIF_F_HIGHDMA;
6968         }
6969
6970         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6971                 netdev->features |= NETIF_F_LRO;
6972
6973         /* make sure the EEPROM is good */
6974         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6975                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6976                 err = -EIO;
6977                 goto err_eeprom;
6978         }
6979
6980         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6981         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6982
6983         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6984                 e_dev_err("invalid MAC address\n");
6985                 err = -EIO;
6986                 goto err_eeprom;
6987         }
6988
6989         /* power down the optics */
6990         if (hw->phy.multispeed_fiber)
6991                 hw->mac.ops.disable_tx_laser(hw);
6992
6993         init_timer(&adapter->watchdog_timer);
6994         adapter->watchdog_timer.function = ixgbe_watchdog;
6995         adapter->watchdog_timer.data = (unsigned long)adapter;
6996
6997         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6998         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6999
7000         err = ixgbe_init_interrupt_scheme(adapter);
7001         if (err)
7002                 goto err_sw_init;
7003
7004         switch (pdev->device) {
7005         case IXGBE_DEV_ID_82599_KX4:
7006                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7007                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7008                 break;
7009         default:
7010                 adapter->wol = 0;
7011                 break;
7012         }
7013         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7014
7015         /* pick up the PCI bus settings for reporting later */
7016         hw->mac.ops.get_bus_info(hw);
7017
7018         /* print bus type/speed/width info */
7019         e_dev_info("(PCI Express:%s:%s) %pM\n",
7020                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
7021                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
7022                     "Unknown"),
7023                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7024                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7025                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7026                     "Unknown"),
7027                    netdev->dev_addr);
7028         ixgbe_read_pba_num_generic(hw, &part_num);
7029         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7030                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7031                            "PBA No: %06x-%03x\n",
7032                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7033                            (part_num >> 8), (part_num & 0xff));
7034         else
7035                 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7036                            hw->mac.type, hw->phy.type,
7037                            (part_num >> 8), (part_num & 0xff));
7038
7039         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7040                 e_dev_warn("PCI-Express bandwidth available for this card is "
7041                            "not sufficient for optimal performance.\n");
7042                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7043                            "is required.\n");
7044         }
7045
7046         /* save off EEPROM version number */
7047         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7048
7049         /* reset the hardware with the new settings */
7050         err = hw->mac.ops.start_hw(hw);
7051
7052         if (err == IXGBE_ERR_EEPROM_VERSION) {
7053                 /* We are running on a pre-production device, log a warning */
7054                 e_dev_warn("This device is a pre-production adapter/LOM. "
7055                            "Please be aware there may be issues associated "
7056                            "with your hardware.  If you are experiencing "
7057                            "problems please contact your Intel or hardware "
7058                            "representative who provided you with this "
7059                            "hardware.\n");
7060         }
7061         strcpy(netdev->name, "eth%d");
7062         err = register_netdev(netdev);
7063         if (err)
7064                 goto err_register;
7065
7066         /* carrier off reporting is important to ethtool even BEFORE open */
7067         netif_carrier_off(netdev);
7068
7069         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7070             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7071                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7072
7073         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7074                 INIT_WORK(&adapter->check_overtemp_task,
7075                           ixgbe_check_overtemp_task);
7076 #ifdef CONFIG_IXGBE_DCA
7077         if (dca_add_requester(&pdev->dev) == 0) {
7078                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7079                 ixgbe_setup_dca(adapter);
7080         }
7081 #endif
7082         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7083                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7084                 for (i = 0; i < adapter->num_vfs; i++)
7085                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7086         }
7087
7088         /* add san mac addr to netdev */
7089         ixgbe_add_sanmac_netdev(netdev);
7090
7091         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7092         cards_found++;
7093         return 0;
7094
7095 err_register:
7096         ixgbe_release_hw_control(adapter);
7097         ixgbe_clear_interrupt_scheme(adapter);
7098 err_sw_init:
7099 err_eeprom:
7100         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7101                 ixgbe_disable_sriov(adapter);
7102         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7103         del_timer_sync(&adapter->sfp_timer);
7104         cancel_work_sync(&adapter->sfp_task);
7105         cancel_work_sync(&adapter->multispeed_fiber_task);
7106         cancel_work_sync(&adapter->sfp_config_module_task);
7107         iounmap(hw->hw_addr);
7108 err_ioremap:
7109         free_netdev(netdev);
7110 err_alloc_etherdev:
7111         pci_release_selected_regions(pdev,
7112                                      pci_select_bars(pdev, IORESOURCE_MEM));
7113 err_pci_reg:
7114 err_dma:
7115         pci_disable_device(pdev);
7116         return err;
7117 }
7118
7119 /**
7120  * ixgbe_remove - Device Removal Routine
7121  * @pdev: PCI device information struct
7122  *
7123  * ixgbe_remove is called by the PCI subsystem to alert the driver
7124  * that it should release a PCI device.  The could be caused by a
7125  * Hot-Plug event, or because the driver is going to be removed from
7126  * memory.
7127  **/
7128 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7129 {
7130         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7131         struct net_device *netdev = adapter->netdev;
7132
7133         set_bit(__IXGBE_DOWN, &adapter->state);
7134         /* clear the module not found bit to make sure the worker won't
7135          * reschedule
7136          */
7137         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7138         del_timer_sync(&adapter->watchdog_timer);
7139
7140         del_timer_sync(&adapter->sfp_timer);
7141         cancel_work_sync(&adapter->watchdog_task);
7142         cancel_work_sync(&adapter->sfp_task);
7143         cancel_work_sync(&adapter->multispeed_fiber_task);
7144         cancel_work_sync(&adapter->sfp_config_module_task);
7145         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7146             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7147                 cancel_work_sync(&adapter->fdir_reinit_task);
7148         flush_scheduled_work();
7149
7150 #ifdef CONFIG_IXGBE_DCA
7151         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7152                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7153                 dca_remove_requester(&pdev->dev);
7154                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7155         }
7156
7157 #endif
7158 #ifdef IXGBE_FCOE
7159         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7160                 ixgbe_cleanup_fcoe(adapter);
7161
7162 #endif /* IXGBE_FCOE */
7163
7164         /* remove the added san mac */
7165         ixgbe_del_sanmac_netdev(netdev);
7166
7167         if (netdev->reg_state == NETREG_REGISTERED)
7168                 unregister_netdev(netdev);
7169
7170         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7171                 ixgbe_disable_sriov(adapter);
7172
7173         ixgbe_clear_interrupt_scheme(adapter);
7174
7175         ixgbe_release_hw_control(adapter);
7176
7177         iounmap(adapter->hw.hw_addr);
7178         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7179                                      IORESOURCE_MEM));
7180
7181         e_dev_info("complete\n");
7182
7183         free_netdev(netdev);
7184
7185         pci_disable_pcie_error_reporting(pdev);
7186
7187         pci_disable_device(pdev);
7188 }
7189
7190 /**
7191  * ixgbe_io_error_detected - called when PCI error is detected
7192  * @pdev: Pointer to PCI device
7193  * @state: The current pci connection state
7194  *
7195  * This function is called after a PCI bus error affecting
7196  * this device has been detected.
7197  */
7198 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7199                                                 pci_channel_state_t state)
7200 {
7201         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7202         struct net_device *netdev = adapter->netdev;
7203
7204         netif_device_detach(netdev);
7205
7206         if (state == pci_channel_io_perm_failure)
7207                 return PCI_ERS_RESULT_DISCONNECT;
7208
7209         if (netif_running(netdev))
7210                 ixgbe_down(adapter);
7211         pci_disable_device(pdev);
7212
7213         /* Request a slot reset. */
7214         return PCI_ERS_RESULT_NEED_RESET;
7215 }
7216
7217 /**
7218  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7219  * @pdev: Pointer to PCI device
7220  *
7221  * Restart the card from scratch, as if from a cold-boot.
7222  */
7223 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7224 {
7225         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7226         pci_ers_result_t result;
7227         int err;
7228
7229         if (pci_enable_device_mem(pdev)) {
7230                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7231                 result = PCI_ERS_RESULT_DISCONNECT;
7232         } else {
7233                 pci_set_master(pdev);
7234                 pci_restore_state(pdev);
7235                 pci_save_state(pdev);
7236
7237                 pci_wake_from_d3(pdev, false);
7238
7239                 ixgbe_reset(adapter);
7240                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7241                 result = PCI_ERS_RESULT_RECOVERED;
7242         }
7243
7244         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7245         if (err) {
7246                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7247                           "failed 0x%0x\n", err);
7248                 /* non-fatal, continue */
7249         }
7250
7251         return result;
7252 }
7253
7254 /**
7255  * ixgbe_io_resume - called when traffic can start flowing again.
7256  * @pdev: Pointer to PCI device
7257  *
7258  * This callback is called when the error recovery driver tells us that
7259  * its OK to resume normal operation.
7260  */
7261 static void ixgbe_io_resume(struct pci_dev *pdev)
7262 {
7263         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7264         struct net_device *netdev = adapter->netdev;
7265
7266         if (netif_running(netdev)) {
7267                 if (ixgbe_up(adapter)) {
7268                         e_info(probe, "ixgbe_up failed after reset\n");
7269                         return;
7270                 }
7271         }
7272
7273         netif_device_attach(netdev);
7274 }
7275
7276 static struct pci_error_handlers ixgbe_err_handler = {
7277         .error_detected = ixgbe_io_error_detected,
7278         .slot_reset = ixgbe_io_slot_reset,
7279         .resume = ixgbe_io_resume,
7280 };
7281
7282 static struct pci_driver ixgbe_driver = {
7283         .name     = ixgbe_driver_name,
7284         .id_table = ixgbe_pci_tbl,
7285         .probe    = ixgbe_probe,
7286         .remove   = __devexit_p(ixgbe_remove),
7287 #ifdef CONFIG_PM
7288         .suspend  = ixgbe_suspend,
7289         .resume   = ixgbe_resume,
7290 #endif
7291         .shutdown = ixgbe_shutdown,
7292         .err_handler = &ixgbe_err_handler
7293 };
7294
7295 /**
7296  * ixgbe_init_module - Driver Registration Routine
7297  *
7298  * ixgbe_init_module is the first routine called when the driver is
7299  * loaded. All it does is register with the PCI subsystem.
7300  **/
7301 static int __init ixgbe_init_module(void)
7302 {
7303         int ret;
7304         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7305         pr_info("%s\n", ixgbe_copyright);
7306
7307 #ifdef CONFIG_IXGBE_DCA
7308         dca_register_notify(&dca_notifier);
7309 #endif
7310
7311         ret = pci_register_driver(&ixgbe_driver);
7312         return ret;
7313 }
7314
7315 module_init(ixgbe_init_module);
7316
7317 /**
7318  * ixgbe_exit_module - Driver Exit Cleanup Routine
7319  *
7320  * ixgbe_exit_module is called just before the driver is removed
7321  * from memory.
7322  **/
7323 static void __exit ixgbe_exit_module(void)
7324 {
7325 #ifdef CONFIG_IXGBE_DCA
7326         dca_unregister_notify(&dca_notifier);
7327 #endif
7328         pci_unregister_driver(&ixgbe_driver);
7329         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7330 }
7331
7332 #ifdef CONFIG_IXGBE_DCA
7333 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7334                             void *p)
7335 {
7336         int ret_val;
7337
7338         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7339                                          __ixgbe_notify_dca);
7340
7341         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7342 }
7343
7344 #endif /* CONFIG_IXGBE_DCA */
7345
7346 /**
7347  * ixgbe_get_hw_dev return device
7348  * used by hardware layer to print debugging information
7349  **/
7350 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7351 {
7352         struct ixgbe_adapter *adapter = hw->back;
7353         return adapter->netdev;
7354 }
7355
7356 module_exit(ixgbe_exit_module);
7357
7358 /* ixgbe_main.c */