1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
45 ixgbe_link_speed speed,
47 bool autoneg_wait_to_complete);
48 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
52 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
53 * @hw: pointer to the HW structure
55 * The defaults for 82598 should be in the range of 50us to 50ms,
56 * however the hardware default for these parts is 500us to 1ms which is less
57 * than the 10ms recommended by the pci-e spec. To address this we need to
58 * increase the value to either 10ms to 250ms for capability version 1 config,
59 * or 16ms to 55ms for version 2.
61 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
63 struct ixgbe_adapter *adapter = hw->back;
64 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
67 /* only take action if timeout value is defaulted to 0 */
68 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
72 * if capababilities version is type 1 we can write the
73 * timeout of 10ms to 250ms through the GCR register
75 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
76 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
81 * for version 2 capabilities we need to write the config space
82 * directly in order to set the completion timeout value for
85 pci_read_config_word(adapter->pdev,
86 IXGBE_PCI_DEVICE_CONTROL2, &pcie_devctl2);
87 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
88 pci_write_config_word(adapter->pdev,
89 IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
91 /* disable completion timeout resend */
92 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
93 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
97 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
98 * @hw: pointer to hardware structure
100 * Read PCIe configuration space, and get the MSI-X vector count from
101 * the capabilities table.
103 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
105 struct ixgbe_adapter *adapter = hw->back;
107 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
109 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
111 /* MSI-X count is zero-based in HW, so increment to give proper value */
119 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
121 struct ixgbe_mac_info *mac = &hw->mac;
123 /* Call PHY identify routine to get the phy type */
124 ixgbe_identify_phy_generic(hw);
126 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
127 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
128 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
129 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
130 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
131 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
137 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
138 * @hw: pointer to hardware structure
140 * Initialize any function pointers that were not able to be
141 * set during get_invariants because the PHY/SFP type was
142 * not known. Perform the SFP init if necessary.
145 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
147 struct ixgbe_mac_info *mac = &hw->mac;
148 struct ixgbe_phy_info *phy = &hw->phy;
150 u16 list_offset, data_offset;
152 /* Identify the PHY */
153 phy->ops.identify(hw);
155 /* Overwrite the link function pointers if copper PHY */
156 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
157 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
158 mac->ops.get_link_capabilities =
159 &ixgbe_get_copper_link_capabilities_82598;
162 switch (hw->phy.type) {
164 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
165 phy->ops.get_firmware_version =
166 &ixgbe_get_phy_firmware_version_tnx;
169 phy->ops.reset = &ixgbe_reset_phy_nl;
171 /* Call SFP+ identify routine to get the SFP+ module type */
172 ret_val = phy->ops.identify_sfp(hw);
175 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
176 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
180 /* Check to see if SFP+ module is supported */
181 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
185 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
198 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
199 * @hw: pointer to hardware structure
201 * Starts the hardware using the generic start_hw function.
202 * Then set pcie completion timeout
204 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
208 ret_val = ixgbe_start_hw_generic(hw);
210 /* set the completion timeout for interface */
212 ixgbe_set_pcie_completion_timeout(hw);
218 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
219 * @hw: pointer to hardware structure
220 * @speed: pointer to link speed
221 * @autoneg: boolean auto-negotiation value
223 * Determines the link capabilities by reading the AUTOC register.
225 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
226 ixgbe_link_speed *speed,
233 * Determine link capabilities based on the stored value of AUTOC,
234 * which represents EEPROM defaults. If AUTOC value has not been
235 * stored, use the current register value.
237 if (hw->mac.orig_link_settings_stored)
238 autoc = hw->mac.orig_autoc;
240 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
242 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
243 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
244 *speed = IXGBE_LINK_SPEED_1GB_FULL;
248 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
249 *speed = IXGBE_LINK_SPEED_10GB_FULL;
253 case IXGBE_AUTOC_LMS_1G_AN:
254 *speed = IXGBE_LINK_SPEED_1GB_FULL;
258 case IXGBE_AUTOC_LMS_KX4_AN:
259 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
260 *speed = IXGBE_LINK_SPEED_UNKNOWN;
261 if (autoc & IXGBE_AUTOC_KX4_SUPP)
262 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
263 if (autoc & IXGBE_AUTOC_KX_SUPP)
264 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
269 status = IXGBE_ERR_LINK_SETUP;
277 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
278 * @hw: pointer to hardware structure
279 * @speed: pointer to link speed
280 * @autoneg: boolean auto-negotiation value
282 * Determines the link capabilities by reading the AUTOC register.
284 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
285 ixgbe_link_speed *speed,
288 s32 status = IXGBE_ERR_LINK_SETUP;
294 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
298 if (speed_ability & MDIO_SPEED_10G)
299 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
300 if (speed_ability & MDIO_PMA_SPEED_1000)
301 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
308 * ixgbe_get_media_type_82598 - Determines media type
309 * @hw: pointer to hardware structure
311 * Returns the media type (fiber, copper, backplane)
313 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
315 enum ixgbe_media_type media_type;
317 /* Media type for I82598 is based on device ID */
318 switch (hw->device_id) {
319 case IXGBE_DEV_ID_82598:
320 case IXGBE_DEV_ID_82598_BX:
321 media_type = ixgbe_media_type_backplane;
323 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
324 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
325 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
326 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
327 case IXGBE_DEV_ID_82598EB_XF_LR:
328 case IXGBE_DEV_ID_82598EB_SFP_LOM:
329 media_type = ixgbe_media_type_fiber;
331 case IXGBE_DEV_ID_82598EB_CX4:
332 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
333 media_type = ixgbe_media_type_cx4;
335 case IXGBE_DEV_ID_82598AT:
336 case IXGBE_DEV_ID_82598AT2:
337 media_type = ixgbe_media_type_copper;
340 media_type = ixgbe_media_type_unknown;
348 * ixgbe_fc_enable_82598 - Enable flow control
349 * @hw: pointer to hardware structure
350 * @packetbuf_num: packet buffer number (0-7)
352 * Enable flow control according to the current settings.
354 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
365 if (hw->fc.requested_mode == ixgbe_fc_pfc)
368 #endif /* CONFIG_DCB */
370 * On 82598 having Rx FC on causes resets while doing 1G
371 * so if it's on turn it off once we know link_speed. For
372 * more details see 82598 Specification update.
374 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
375 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
376 switch (hw->fc.requested_mode) {
378 hw->fc.requested_mode = ixgbe_fc_tx_pause;
380 case ixgbe_fc_rx_pause:
381 hw->fc.requested_mode = ixgbe_fc_none;
389 /* Negotiate the fc mode to use */
390 ret_val = ixgbe_fc_autoneg(hw);
394 /* Disable any previous flow control settings */
395 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
396 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
398 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
399 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
402 * The possible values of fc.current_mode are:
403 * 0: Flow control is completely disabled
404 * 1: Rx flow control is enabled (we can receive pause frames,
405 * but not send pause frames).
406 * 2: Tx flow control is enabled (we can send pause frames but
407 * we do not support receiving pause frames).
408 * 3: Both Rx and Tx flow control (symmetric) are enabled.
411 * 4: Priority Flow Control is enabled.
414 switch (hw->fc.current_mode) {
417 * Flow control is disabled by software override or autoneg.
418 * The code below will actually disable it in the HW.
421 case ixgbe_fc_rx_pause:
423 * Rx Flow control is enabled and Tx Flow control is
424 * disabled by software override. Since there really
425 * isn't a way to advertise that we are capable of RX
426 * Pause ONLY, we will advertise that we support both
427 * symmetric and asymmetric Rx PAUSE. Later, we will
428 * disable the adapter's ability to send PAUSE frames.
430 fctrl_reg |= IXGBE_FCTRL_RFCE;
432 case ixgbe_fc_tx_pause:
434 * Tx Flow control is enabled, and Rx Flow control is
435 * disabled by software override.
437 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
440 /* Flow control (both Rx and Tx) is enabled by SW override. */
441 fctrl_reg |= IXGBE_FCTRL_RFCE;
442 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
448 #endif /* CONFIG_DCB */
450 hw_dbg(hw, "Flow control param set incorrectly\n");
451 ret_val = IXGBE_ERR_CONFIG;
456 /* Set 802.3x based flow control settings. */
457 fctrl_reg |= IXGBE_FCTRL_DPF;
458 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
459 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
461 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
462 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
463 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
464 rx_pba_size >>= IXGBE_RXPBSIZE_SHIFT;
466 reg = (rx_pba_size - hw->fc.low_water) << 6;
468 reg |= IXGBE_FCRTL_XONE;
469 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num), reg);
471 reg = (rx_pba_size - hw->fc.high_water) << 10;
472 reg |= IXGBE_FCRTH_FCEN;
474 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num), reg);
477 /* Configure pause time (2 TCs per register) */
478 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
479 if ((packetbuf_num & 1) == 0)
480 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
482 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
483 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
485 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
492 * ixgbe_start_mac_link_82598 - Configures MAC link settings
493 * @hw: pointer to hardware structure
495 * Configures link settings based on values in the ixgbe_hw struct.
496 * Restarts the link. Performs autonegotiation if needed.
498 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
499 bool autoneg_wait_to_complete)
507 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
508 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
509 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
511 /* Only poll for autoneg to complete if specified to do so */
512 if (autoneg_wait_to_complete) {
513 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
514 IXGBE_AUTOC_LMS_KX4_AN ||
515 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
516 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
517 links_reg = 0; /* Just in case Autoneg time = 0 */
518 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
519 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
520 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
524 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
525 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
526 hw_dbg(hw, "Autonegotiation did not complete.\n");
531 /* Add delay to filter out noises during initial link setup */
538 * ixgbe_validate_link_ready - Function looks for phy link
539 * @hw: pointer to hardware structure
541 * Function indicates success when phy link is available. If phy is not ready
542 * within 5 seconds of MAC indicating link, the function returns error.
544 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
549 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
553 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
554 hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
556 if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
557 (an_reg & MDIO_STAT1_LSTATUS))
563 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
564 hw_dbg(hw, "Link was indicated but link is down\n");
565 return IXGBE_ERR_LINK_SETUP;
572 * ixgbe_check_mac_link_82598 - Get link/speed status
573 * @hw: pointer to hardware structure
574 * @speed: pointer to link speed
575 * @link_up: true is link is up, false otherwise
576 * @link_up_wait_to_complete: bool used to wait for link up or not
578 * Reads the links register to determine if link is up and the current speed
580 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
581 ixgbe_link_speed *speed, bool *link_up,
582 bool link_up_wait_to_complete)
586 u16 link_reg, adapt_comp_reg;
589 * SERDES PHY requires us to read link status from register 0xC79F.
590 * Bit 0 set indicates link is up/ready; clear indicates link down.
591 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
592 * clear indicates active; set indicates inactive.
594 if (hw->phy.type == ixgbe_phy_nl) {
595 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
596 hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
597 hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
599 if (link_up_wait_to_complete) {
600 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
601 if ((link_reg & 1) &&
602 ((adapt_comp_reg & 1) == 0)) {
609 hw->phy.ops.read_reg(hw, 0xC79F,
612 hw->phy.ops.read_reg(hw, 0xC00C,
617 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
623 if (*link_up == false)
627 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
628 if (link_up_wait_to_complete) {
629 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
630 if (links_reg & IXGBE_LINKS_UP) {
637 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
640 if (links_reg & IXGBE_LINKS_UP)
646 if (links_reg & IXGBE_LINKS_SPEED)
647 *speed = IXGBE_LINK_SPEED_10GB_FULL;
649 *speed = IXGBE_LINK_SPEED_1GB_FULL;
651 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
652 (ixgbe_validate_link_ready(hw) != 0))
655 /* if link is down, zero out the current_mode */
656 if (*link_up == false) {
657 hw->fc.current_mode = ixgbe_fc_none;
658 hw->fc.fc_was_autonegged = false;
666 * ixgbe_setup_mac_link_82598 - Set MAC link speed
667 * @hw: pointer to hardware structure
668 * @speed: new link speed
669 * @autoneg: true if auto-negotiation enabled
670 * @autoneg_wait_to_complete: true if waiting is needed to complete
672 * Set the link speed in the AUTOC register and restarts link.
674 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
675 ixgbe_link_speed speed, bool autoneg,
676 bool autoneg_wait_to_complete)
679 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
680 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
681 u32 autoc = curr_autoc;
682 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
684 /* Check to see if speed passed in is supported. */
685 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
686 speed &= link_capabilities;
688 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
689 status = IXGBE_ERR_LINK_SETUP;
691 /* Set KX4/KX support according to speed requested */
692 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
693 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
694 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
695 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
696 autoc |= IXGBE_AUTOC_KX4_SUPP;
697 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
698 autoc |= IXGBE_AUTOC_KX_SUPP;
699 if (autoc != curr_autoc)
700 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
705 * Setup and restart the link based on the new values in
706 * ixgbe_hw This will write the AUTOC register based on the new
709 status = ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
717 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
718 * @hw: pointer to hardware structure
719 * @speed: new link speed
720 * @autoneg: true if autonegotiation enabled
721 * @autoneg_wait_to_complete: true if waiting is needed to complete
723 * Sets the link speed in the AUTOC register in the MAC and restarts link.
725 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
726 ixgbe_link_speed speed,
728 bool autoneg_wait_to_complete)
732 /* Setup the PHY according to input speed */
733 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
734 autoneg_wait_to_complete);
737 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
743 * ixgbe_reset_hw_82598 - Performs hardware reset
744 * @hw: pointer to hardware structure
746 * Resets the hardware by resetting the transmit and receive units, masks and
747 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
750 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
760 /* Call adapter stop to disable tx/rx and clear interrupts */
761 hw->mac.ops.stop_adapter(hw);
764 * Power up the Atlas Tx lanes if they are currently powered down.
765 * Atlas Tx lanes are powered down for MAC loopback tests, but
766 * they are not automatically restored on reset.
768 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
769 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
770 /* Enable Tx Atlas so packets can be transmitted again */
771 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
773 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
774 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
777 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
779 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
780 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
783 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
785 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
786 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
789 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
791 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
792 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
797 if (hw->phy.reset_disable == false) {
798 /* PHY ops must be identified and initialized prior to reset */
800 /* Init PHY and function pointers, perform SFP setup */
801 phy_status = hw->phy.ops.init(hw);
802 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
804 else if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
808 hw->phy.ops.reset(hw);
813 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
814 * access and verify no pending requests before reset
816 status = ixgbe_disable_pcie_master(hw);
818 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
819 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
823 * Issue global reset to the MAC. This needs to be a SW reset.
824 * If link reset is used, it might reset the MAC when mng is using it
826 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
827 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
828 IXGBE_WRITE_FLUSH(hw);
830 /* Poll for reset bit to self-clear indicating reset is complete */
831 for (i = 0; i < 10; i++) {
833 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
834 if (!(ctrl & IXGBE_CTRL_RST))
837 if (ctrl & IXGBE_CTRL_RST) {
838 status = IXGBE_ERR_RESET_FAILED;
839 hw_dbg(hw, "Reset polling failed to complete.\n");
844 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
845 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
846 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
849 * Store the original AUTOC value if it has not been
850 * stored off yet. Otherwise restore the stored original
851 * AUTOC value since the reset operation sets back to deaults.
853 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
854 if (hw->mac.orig_link_settings_stored == false) {
855 hw->mac.orig_autoc = autoc;
856 hw->mac.orig_link_settings_stored = true;
857 } else if (autoc != hw->mac.orig_autoc) {
858 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
862 * Store MAC address from RAR0, clear receive address registers, and
863 * clear the multicast table
865 hw->mac.ops.init_rx_addrs(hw);
867 /* Store the permanent mac address */
868 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
878 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
879 * @hw: pointer to hardware struct
880 * @rar: receive address register index to associate with a VMDq index
881 * @vmdq: VMDq set index
883 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
887 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
888 rar_high &= ~IXGBE_RAH_VIND_MASK;
889 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
890 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
895 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
896 * @hw: pointer to hardware struct
897 * @rar: receive address register index to associate with a VMDq index
898 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
900 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
903 u32 rar_entries = hw->mac.num_rar_entries;
905 if (rar < rar_entries) {
906 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
907 if (rar_high & IXGBE_RAH_VIND_MASK) {
908 rar_high &= ~IXGBE_RAH_VIND_MASK;
909 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
912 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
919 * ixgbe_set_vfta_82598 - Set VLAN filter table
920 * @hw: pointer to hardware structure
921 * @vlan: VLAN id to write to VLAN filter
922 * @vind: VMDq output index that maps queue to VLAN id in VFTA
923 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
925 * Turn on/off specified VLAN in the VLAN filter table.
927 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
936 return IXGBE_ERR_PARAM;
938 /* Determine 32-bit word position in array */
939 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
941 /* Determine the location of the (VMD) queue index */
942 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
943 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
945 /* Set the nibble for VMD queue index */
946 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
947 bits &= (~(0x0F << bitindex));
948 bits |= (vind << bitindex);
949 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
951 /* Determine the location of the bit for this VLAN id */
952 bitindex = vlan & 0x1F; /* lower five bits */
954 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
956 /* Turn on this VLAN id */
957 bits |= (1 << bitindex);
959 /* Turn off this VLAN id */
960 bits &= ~(1 << bitindex);
961 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
967 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
968 * @hw: pointer to hardware structure
970 * Clears the VLAN filer table, and the VMDq index associated with the filter
972 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
977 for (offset = 0; offset < hw->mac.vft_size; offset++)
978 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
980 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
981 for (offset = 0; offset < hw->mac.vft_size; offset++)
982 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
989 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
990 * @hw: pointer to hardware structure
991 * @reg: analog register to read
994 * Performs read operation to Atlas analog register specified.
996 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1000 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1001 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1002 IXGBE_WRITE_FLUSH(hw);
1004 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1005 *val = (u8)atlas_ctl;
1011 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1012 * @hw: pointer to hardware structure
1013 * @reg: atlas register to write
1014 * @val: value to write
1016 * Performs write operation to Atlas analog register specified.
1018 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1022 atlas_ctl = (reg << 8) | val;
1023 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1024 IXGBE_WRITE_FLUSH(hw);
1031 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
1032 * over I2C interface through an intermediate phy.
1033 * @hw: pointer to hardware structure
1034 * @byte_offset: EEPROM byte offset to read
1035 * @eeprom_data: value read
1037 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1039 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1048 if (hw->phy.type == ixgbe_phy_nl) {
1050 * phy SDA/SCL registers are at addresses 0xC30A to
1051 * 0xC30D. These registers are used to talk to the SFP+
1052 * module's EEPROM through the SDA/SCL (I2C) interface.
1054 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1055 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1056 hw->phy.ops.write_reg(hw,
1057 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1062 for (i = 0; i < 100; i++) {
1063 hw->phy.ops.read_reg(hw,
1064 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1067 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1068 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1073 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1074 hw_dbg(hw, "EEPROM read did not pass.\n");
1075 status = IXGBE_ERR_SFP_NOT_PRESENT;
1080 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1081 MDIO_MMD_PMAPMD, &sfp_data);
1083 *eeprom_data = (u8)(sfp_data >> 8);
1085 status = IXGBE_ERR_PHY;
1094 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1095 * @hw: pointer to hardware structure
1097 * Determines physical layer capabilities of the current configuration.
1099 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1101 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1102 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1103 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1104 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1105 u16 ext_ability = 0;
1107 hw->phy.ops.identify(hw);
1109 /* Copper PHY must be checked before AUTOC LMS to determine correct
1110 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1111 if (hw->phy.type == ixgbe_phy_tn ||
1112 hw->phy.type == ixgbe_phy_cu_unknown) {
1113 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1115 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1116 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1117 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1118 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1119 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1120 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1124 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1125 case IXGBE_AUTOC_LMS_1G_AN:
1126 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1127 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1128 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1130 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1132 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1133 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1134 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1135 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1136 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1138 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1140 case IXGBE_AUTOC_LMS_KX4_AN:
1141 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1142 if (autoc & IXGBE_AUTOC_KX_SUPP)
1143 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1144 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1145 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1151 if (hw->phy.type == ixgbe_phy_nl) {
1152 hw->phy.ops.identify_sfp(hw);
1154 switch (hw->phy.sfp_type) {
1155 case ixgbe_sfp_type_da_cu:
1156 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1158 case ixgbe_sfp_type_sr:
1159 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1161 case ixgbe_sfp_type_lr:
1162 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1165 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1170 switch (hw->device_id) {
1171 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1172 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1174 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1175 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1176 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1177 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1179 case IXGBE_DEV_ID_82598EB_XF_LR:
1180 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1187 return physical_layer;
1190 static struct ixgbe_mac_operations mac_ops_82598 = {
1191 .init_hw = &ixgbe_init_hw_generic,
1192 .reset_hw = &ixgbe_reset_hw_82598,
1193 .start_hw = &ixgbe_start_hw_82598,
1194 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1195 .get_media_type = &ixgbe_get_media_type_82598,
1196 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1197 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1198 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1199 .stop_adapter = &ixgbe_stop_adapter_generic,
1200 .get_bus_info = &ixgbe_get_bus_info_generic,
1201 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1202 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1203 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1204 .setup_link = &ixgbe_setup_mac_link_82598,
1205 .check_link = &ixgbe_check_mac_link_82598,
1206 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1207 .led_on = &ixgbe_led_on_generic,
1208 .led_off = &ixgbe_led_off_generic,
1209 .blink_led_start = &ixgbe_blink_led_start_generic,
1210 .blink_led_stop = &ixgbe_blink_led_stop_generic,
1211 .set_rar = &ixgbe_set_rar_generic,
1212 .clear_rar = &ixgbe_clear_rar_generic,
1213 .set_vmdq = &ixgbe_set_vmdq_82598,
1214 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1215 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1216 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1217 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1218 .enable_mc = &ixgbe_enable_mc_generic,
1219 .disable_mc = &ixgbe_disable_mc_generic,
1220 .clear_vfta = &ixgbe_clear_vfta_82598,
1221 .set_vfta = &ixgbe_set_vfta_82598,
1222 .fc_enable = &ixgbe_fc_enable_82598,
1225 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1226 .init_params = &ixgbe_init_eeprom_params_generic,
1227 .read = &ixgbe_read_eerd_generic,
1228 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1229 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1232 static struct ixgbe_phy_operations phy_ops_82598 = {
1233 .identify = &ixgbe_identify_phy_generic,
1234 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1235 .init = &ixgbe_init_phy_ops_82598,
1236 .reset = &ixgbe_reset_phy_generic,
1237 .read_reg = &ixgbe_read_phy_reg_generic,
1238 .write_reg = &ixgbe_write_phy_reg_generic,
1239 .setup_link = &ixgbe_setup_phy_link_generic,
1240 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1241 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1242 .check_overtemp = &ixgbe_tn_check_overtemp,
1245 struct ixgbe_info ixgbe_82598_info = {
1246 .mac = ixgbe_mac_82598EB,
1247 .get_invariants = &ixgbe_get_invariants_82598,
1248 .mac_ops = &mac_ops_82598,
1249 .eeprom_ops = &eeprom_ops_82598,
1250 .phy_ops = &phy_ops_82598,