1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
31 #include <linux/bitops.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/cpumask.h>
36 #include <linux/aer.h>
37 #include <linux/if_vlan.h>
39 #include "ixgbe_type.h"
40 #include "ixgbe_common.h"
41 #include "ixgbe_dcb.h"
42 #if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
44 #include "ixgbe_fcoe.h"
45 #endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
46 #ifdef CONFIG_IXGBE_DCA
47 #include <linux/dca.h>
50 /* common prefix used by pr_<> macros */
52 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 /* TX/RX descriptor defines */
55 #define IXGBE_DEFAULT_TXD 512
56 #define IXGBE_MAX_TXD 4096
57 #define IXGBE_MIN_TXD 64
59 #define IXGBE_DEFAULT_RXD 512
60 #define IXGBE_MAX_RXD 4096
61 #define IXGBE_MIN_RXD 64
64 #define IXGBE_MIN_FCRTL 0x40
65 #define IXGBE_MAX_FCRTL 0x7FF80
66 #define IXGBE_MIN_FCRTH 0x600
67 #define IXGBE_MAX_FCRTH 0x7FFF0
68 #define IXGBE_DEFAULT_FCPAUSE 0xFFFF
69 #define IXGBE_MIN_FCPAUSE 0
70 #define IXGBE_MAX_FCPAUSE 0xFFFF
72 /* Supported Rx Buffer Sizes */
73 #define IXGBE_RXBUFFER_512 512 /* Used for packet split */
74 #define IXGBE_RXBUFFER_2048 2048
75 #define IXGBE_RXBUFFER_4096 4096
76 #define IXGBE_RXBUFFER_8192 8192
77 #define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
86 #define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
88 #define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
90 /* How many Rx Buffers do we bundle into one write to the hardware ? */
91 #define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
93 #define IXGBE_TX_FLAGS_CSUM (u32)(1)
94 #define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95 #define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96 #define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
97 #define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98 #define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
99 #define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
100 #define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
101 #define IXGBE_TX_FLAGS_VLAN_SHIFT 16
103 #define IXGBE_MAX_RSC_INT_RATE 162760
105 #define IXGBE_MAX_VF_MC_ENTRIES 30
106 #define IXGBE_MAX_VF_FUNCTIONS 64
107 #define IXGBE_MAX_VFTA_ENTRIES 128
108 #define MAX_EMULATION_MAC_ADDRS 16
109 #define VMDQ_P(p) ((p) + adapter->num_vfs)
111 struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
123 /* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125 struct ixgbe_tx_buffer {
128 unsigned long time_stamp;
134 struct ixgbe_rx_buffer {
139 unsigned int page_offset;
142 struct ixgbe_queue_stats {
148 void *desc; /* descriptor ring memory */
150 struct ixgbe_tx_buffer *tx_buffer_info;
151 struct ixgbe_rx_buffer *rx_buffer_info;
155 u16 count; /* amount of descriptors */
160 u8 queue_index; /* needed for multiqueue queue management */
162 #define IXGBE_RING_RX_PS_ENABLED (u8)(1)
163 u8 flags; /* per ring feature flags */
167 unsigned int total_bytes;
168 unsigned int total_packets;
170 #ifdef CONFIG_IXGBE_DCA
171 /* cpu for tx queue */
175 u16 work_limit; /* max work per interrupt */
176 u16 reg_idx; /* holds the special value that gets
177 * the hardware register offset
178 * associated with this ring, which is
179 * different for DCB and RSS modes
182 struct ixgbe_queue_stats stats;
183 struct u64_stats_sync syncp;
185 unsigned long reinit_state;
186 u64 rsc_count; /* stat for coalesced packets */
187 u64 rsc_flush; /* stats for flushed packets */
188 u32 restart_queue; /* track tx queue restarts */
189 u32 non_eop_descs; /* track hardware descriptor chaining */
191 unsigned int size; /* length in bytes */
192 dma_addr_t dma; /* phys. address of descriptor ring */
194 } ____cacheline_internodealigned_in_smp;
196 enum ixgbe_ring_f_enum {
199 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
204 #endif /* IXGBE_FCOE */
206 RING_F_ARRAY_SIZE /* must be last in enum set */
209 #define IXGBE_MAX_DCB_INDICES 8
210 #define IXGBE_MAX_RSS_INDICES 16
211 #define IXGBE_MAX_VMDQ_INDICES 64
212 #define IXGBE_MAX_FDIR_INDICES 64
214 #define IXGBE_MAX_FCOE_INDICES 8
215 #define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
216 #define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
218 #define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
219 #define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
220 #endif /* IXGBE_FCOE */
221 struct ixgbe_ring_feature {
224 } ____cacheline_internodealigned_in_smp;
227 #define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
229 #define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
231 /* MAX_MSIX_Q_VECTORS of these are allocated,
232 * but we only use one per queue-specific vector.
234 struct ixgbe_q_vector {
235 struct ixgbe_adapter *adapter;
236 unsigned int v_idx; /* index of q_vector within array, also used for
237 * finding the bit in EICR and friends that
238 * represents the vector for this ring */
239 struct napi_struct napi;
240 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
241 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
242 u8 rxr_count; /* Rx ring count assigned to this vector */
243 u8 txr_count; /* Tx ring count assigned to this vector */
247 cpumask_var_t affinity_mask;
250 /* Helper macros to switch between ints/sec and what the register uses.
251 * And yes, it's the same math going both ways. The lowest value
252 * supported by all of the ixgbe hardware is 8.
254 #define EITR_INTS_PER_SEC_TO_REG(_eitr) \
255 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
256 #define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
258 #define IXGBE_DESC_UNUSED(R) \
259 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
260 (R)->next_to_clean - (R)->next_to_use - 1)
262 #define IXGBE_RX_DESC_ADV(R, i) \
263 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
264 #define IXGBE_TX_DESC_ADV(R, i) \
265 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
266 #define IXGBE_TX_CTXTDESC_ADV(R, i) \
267 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
269 #define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
271 /* Use 3K as the baby jumbo frame size for FCoE */
272 #define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
273 #endif /* IXGBE_FCOE */
275 #define OTHER_VECTOR 1
276 #define NON_Q_VECTORS (OTHER_VECTOR)
278 #define MAX_MSIX_VECTORS_82599 64
279 #define MAX_MSIX_Q_VECTORS_82599 64
280 #define MAX_MSIX_VECTORS_82598 18
281 #define MAX_MSIX_Q_VECTORS_82598 16
283 #define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
284 #define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
286 #define MIN_MSIX_Q_VECTORS 2
287 #define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
289 /* board specific private data structure */
290 struct ixgbe_adapter {
291 struct timer_list watchdog_timer;
292 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
294 struct work_struct reset_task;
295 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
296 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
297 struct ixgbe_dcb_config dcb_cfg;
298 struct ixgbe_dcb_config temp_dcb_cfg;
300 enum ixgbe_fc_mode last_lfc_mode;
302 /* Interrupt Throttle Rate */
309 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
311 u32 tx_timeout_count;
318 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
320 int num_rx_pools; /* == num_rx_queues in 82598 */
321 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
322 u64 hw_csum_rx_error;
323 u64 hw_rx_no_dma_resources;
325 int num_msix_vectors;
326 int max_msix_q_vectors; /* true count of q_vectors for device */
327 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
328 struct msix_entry *msix_entries;
330 u32 alloc_rx_page_failed;
331 u32 alloc_rx_buff_failed;
333 /* Some features need tri-state capability,
334 * thus the additional *_CAPABLE flags.
337 #define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
338 #define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
339 #define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
340 #define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
341 #define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
342 #define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
343 #define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
344 #define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
345 #define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
346 #define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
347 #define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
348 #define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
349 #define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
350 #define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
351 #define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
352 #define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
353 #define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
354 #define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
355 #define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
356 #define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
357 #define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
358 #define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
359 #define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
360 #define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
361 #define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
362 #define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
363 #define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
364 #define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
367 #define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
368 #define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
369 #define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
370 /* default to trying for four seconds */
371 #define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
373 /* OS defined structs */
374 struct net_device *netdev;
375 struct pci_dev *pdev;
378 struct ixgbe_ring test_tx_ring;
379 struct ixgbe_ring test_rx_ring;
381 /* structs defined in ixgbe_hw.h */
384 struct ixgbe_hw_stats stats;
386 /* Interrupt Throttle Rate */
392 unsigned int tx_ring_count;
393 unsigned int rx_ring_count;
397 unsigned long link_check_timeout;
399 struct work_struct watchdog_task;
400 struct work_struct sfp_task;
401 struct timer_list sfp_timer;
402 struct work_struct multispeed_fiber_task;
403 struct work_struct sfp_config_module_task;
406 spinlock_t fdir_perfect_lock;
407 struct work_struct fdir_reinit_task;
409 struct ixgbe_fcoe fcoe;
410 #endif /* IXGBE_FCOE */
417 struct work_struct check_overtemp_task;
421 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
422 unsigned int num_vfs;
423 struct vf_data_storage *vfinfo;
430 __IXGBE_FDIR_INIT_DONE,
431 __IXGBE_SFP_MODULE_NOT_FOUND
439 extern struct ixgbe_info ixgbe_82598_info;
440 extern struct ixgbe_info ixgbe_82599_info;
441 #ifdef CONFIG_IXGBE_DCB
442 extern const struct dcbnl_rtnl_ops dcbnl_ops;
443 extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
444 struct ixgbe_dcb_config *dst_dcb_cfg,
448 extern char ixgbe_driver_name[];
449 extern const char ixgbe_driver_version[];
451 extern int ixgbe_up(struct ixgbe_adapter *adapter);
452 extern void ixgbe_down(struct ixgbe_adapter *adapter);
453 extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
454 extern void ixgbe_reset(struct ixgbe_adapter *adapter);
455 extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
456 extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
457 extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
458 extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
459 extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
460 extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
461 extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
462 extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
463 extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
464 extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
465 extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
467 struct ixgbe_adapter *,
468 struct ixgbe_ring *);
469 extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
470 struct ixgbe_tx_buffer *);
471 extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
472 struct ixgbe_ring *rx_ring,
474 extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
475 extern int ethtool_ioctl(struct ifreq *ifr);
476 extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
477 extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
478 extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
479 extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
480 struct ixgbe_atr_input *input,
482 extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
483 struct ixgbe_atr_input *input,
484 struct ixgbe_atr_input_masks *input_masks,
485 u16 soft_id, u8 queue);
486 extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
488 extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
490 extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
492 extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
494 extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
496 extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
498 extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
500 extern void ixgbe_set_rx_mode(struct net_device *netdev);
502 extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
503 extern int ixgbe_fso(struct ixgbe_adapter *adapter,
504 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
505 u32 tx_flags, u8 *hdr_len);
506 extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
507 extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
508 union ixgbe_adv_rx_desc *rx_desc,
509 struct sk_buff *skb);
510 extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
511 struct scatterlist *sgl, unsigned int sgc);
512 extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
513 extern int ixgbe_fcoe_enable(struct net_device *netdev);
514 extern int ixgbe_fcoe_disable(struct net_device *netdev);
515 #ifdef CONFIG_IXGBE_DCB
516 extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
517 extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
518 #endif /* CONFIG_IXGBE_DCB */
519 extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
520 #endif /* IXGBE_FCOE */
522 #endif /* _IXGBE_H_ */