drivers/net/can/pch_can.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/sched.h>
  24 #include <linux/pci.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/can.h>
  32 #include <linux/can/dev.h>
  33 #include <linux/can/error.h>
  34
  35 #define PCH_MAX_MSG_OBJ         32
  36 #define PCH_MSG_OBJ_RX          0 /* The receive message object flag. */
  37 #define PCH_MSG_OBJ_TX          1 /* The transmit message object flag. */
  38
  39 #define PCH_ENABLE              1 /* The enable flag */
  40 #define PCH_DISABLE             0 /* The disable flag */
  41 #define PCH_CTRL_INIT           BIT(0) /* The INIT bit of CANCONT register. */
  42 #define PCH_CTRL_IE             BIT(1) /* The IE bit of CAN control register */
  43 #define PCH_CTRL_IE_SIE_EIE     (BIT(3) | BIT(2) | BIT(1))
  44 #define PCH_CTRL_CCE            BIT(6)
  45 #define PCH_CTRL_OPT            BIT(7) /* The OPT bit of CANCONT register. */
  46 #define PCH_OPT_SILENT          BIT(3) /* The Silent bit of CANOPT reg. */
  47 #define PCH_OPT_LBACK           BIT(4) /* The LoopBack bit of CANOPT reg. */
  48
  49 #define PCH_CMASK_RX_TX_SET     0x00f3
  50 #define PCH_CMASK_RX_TX_GET     0x0073
  51 #define PCH_CMASK_ALL           0xff
  52 #define PCH_CMASK_NEWDAT        BIT(2)
  53 #define PCH_CMASK_CLRINTPND     BIT(3)
  54 #define PCH_CMASK_CTRL          BIT(4)
  55 #define PCH_CMASK_ARB           BIT(5)
  56 #define PCH_CMASK_MASK          BIT(6)
  57 #define PCH_CMASK_RDWR          BIT(7)
  58 #define PCH_IF_MCONT_NEWDAT     BIT(15)
  59 #define PCH_IF_MCONT_MSGLOST    BIT(14)
  60 #define PCH_IF_MCONT_INTPND     BIT(13)
  61 #define PCH_IF_MCONT_UMASK      BIT(12)
  62 #define PCH_IF_MCONT_TXIE       BIT(11)
  63 #define PCH_IF_MCONT_RXIE       BIT(10)
  64 #define PCH_IF_MCONT_RMTEN      BIT(9)
  65 #define PCH_IF_MCONT_TXRQXT     BIT(8)
  66 #define PCH_IF_MCONT_EOB        BIT(7)
  67 #define PCH_IF_MCONT_DLC        (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  68 #define PCH_MASK2_MDIR_MXTD     (BIT(14) | BIT(15))
  69 #define PCH_ID2_DIR             BIT(13)
  70 #define PCH_ID2_XTD             BIT(14)
  71 #define PCH_ID_MSGVAL           BIT(15)
  72 #define PCH_IF_CREQ_BUSY        BIT(15)
  73
  74 #define PCH_STATUS_INT          0x8000
  75 #define PCH_REC                 0x00007f00
  76 #define PCH_TEC                 0x000000ff
  77
  78 #define PCH_TX_OK               BIT(3)
  79 #define PCH_RX_OK               BIT(4)
  80 #define PCH_EPASSIV             BIT(5)
  81 #define PCH_EWARN               BIT(6)
  82 #define PCH_BUS_OFF             BIT(7)
  83 #define PCH_LEC0                BIT(0)
  84 #define PCH_LEC1                BIT(1)
  85 #define PCH_LEC2                BIT(2)
  86 #define PCH_LEC_ALL             (PCH_LEC0 | PCH_LEC1 | PCH_LEC2)
  87 #define PCH_STUF_ERR            PCH_LEC0
  88 #define PCH_FORM_ERR            PCH_LEC1
  89 #define PCH_ACK_ERR             (PCH_LEC0 | PCH_LEC1)
  90 #define PCH_BIT1_ERR            PCH_LEC2
  91 #define PCH_BIT0_ERR            (PCH_LEC0 | PCH_LEC2)
  92 #define PCH_CRC_ERR             (PCH_LEC1 | PCH_LEC2)
  93
  94 /* bit position of certain controller bits. */
  95 #define PCH_BIT_BRP             0
  96 #define PCH_BIT_SJW             6
  97 #define PCH_BIT_TSEG1           8
  98 #define PCH_BIT_TSEG2           12
  99 #define PCH_BIT_BRPE_BRPE       6
 100 #define PCH_MSK_BITT_BRP        0x3f
 101 #define PCH_MSK_BRPE_BRPE       0x3c0
 102 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
 103 #define PCH_COUNTER_LIMIT       10
 104
 105 #define PCH_CAN_CLK             50000000        /* 50MHz */
 106
 107 /* Define the number of message object.
 108  * PCH CAN communications are done via Message RAM.
 109  * The Message RAM consists of 32 message objects. */
 110 #define PCH_RX_OBJ_NUM          26  /* 1~ PCH_RX_OBJ_NUM is Rx*/
 111 #define PCH_TX_OBJ_NUM          6  /* PCH_RX_OBJ_NUM is RX ~ Tx*/
 112 #define PCH_OBJ_NUM             (PCH_TX_OBJ_NUM + PCH_RX_OBJ_NUM)
 113
 114 #define PCH_FIFO_THRESH         16
 115
 116 enum pch_can_mode {
 117         PCH_CAN_ENABLE,
 118         PCH_CAN_DISABLE,
 119         PCH_CAN_ALL,
 120         PCH_CAN_NONE,
 121         PCH_CAN_STOP,
 122         PCH_CAN_RUN
 123 };
 124
 125 struct pch_can_regs {
 126         u32 cont;
 127         u32 stat;
 128         u32 errc;
 129         u32 bitt;
 130         u32 intr;
 131         u32 opt;
 132         u32 brpe;
 133         u32 reserve1;
 134         u32 if1_creq;
 135         u32 if1_cmask;
 136         u32 if1_mask1;
 137         u32 if1_mask2;
 138         u32 if1_id1;
 139         u32 if1_id2;
 140         u32 if1_mcont;
 141         u32 if1_dataa1;
 142         u32 if1_dataa2;
 143         u32 if1_datab1;
 144         u32 if1_datab2;
 145         u32 reserve2;
 146         u32 reserve3[12];
 147         u32 if2_creq;
 148         u32 if2_cmask;
 149         u32 if2_mask1;
 150         u32 if2_mask2;
 151         u32 if2_id1;
 152         u32 if2_id2;
 153         u32 if2_mcont;
 154         u32 if2_dataa1;
 155         u32 if2_dataa2;
 156         u32 if2_datab1;
 157         u32 if2_datab2;
 158         u32 reserve4;
 159         u32 reserve5[20];
 160         u32 treq1;
 161         u32 treq2;
 162         u32 reserve6[2];
 163         u32 reserve7[56];
 164         u32 reserve8[3];
 165         u32 srst;
 166 };
 167
 168 struct pch_can_priv {
 169         struct can_priv can;
 170         unsigned int can_num;
 171         struct pci_dev *dev;
 172         unsigned int tx_enable[PCH_MAX_MSG_OBJ];
 173         unsigned int rx_enable[PCH_MAX_MSG_OBJ];
 174         unsigned int rx_link[PCH_MAX_MSG_OBJ];
 175         unsigned int int_enables;
 176         unsigned int int_stat;
 177         struct net_device *ndev;
 178         spinlock_t msgif_reg_lock; /* Message Interface Registers Access Lock*/
 179         unsigned int msg_obj[PCH_MAX_MSG_OBJ];
 180         struct pch_can_regs __iomem *regs;
 181         struct napi_struct napi;
 182         unsigned int tx_obj;    /* Point next Tx Obj index */
 183         unsigned int use_msi;
 184 };
 185
 186 static struct can_bittiming_const pch_can_bittiming_const = {
 187         .name = KBUILD_MODNAME,
 188         .tseg1_min = 1,
 189         .tseg1_max = 16,
 190         .tseg2_min = 1,
 191         .tseg2_max = 8,
 192         .sjw_max = 4,
 193         .brp_min = 1,
 194         .brp_max = 1024, /* 6bit + extended 4bit */
 195         .brp_inc = 1,
 196 };
 197
 198 static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
 199         {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
 200         {0,}
 201 };
 202 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
 203
 204 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
 205 {
 206         iowrite32(ioread32(addr) | mask, addr);
 207 }
 208
 209 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
 210 {
 211         iowrite32(ioread32(addr) & ~mask, addr);
 212 }
 213
 214 static void pch_can_set_run_mode(struct pch_can_priv *priv,
 215                                  enum pch_can_mode mode)
 216 {
 217         switch (mode) {
 218         case PCH_CAN_RUN:
 219                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
 220                 break;
 221
 222         case PCH_CAN_STOP:
 223                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
 224                 break;
 225
 226         default:
 227                 dev_err(&priv->ndev->dev, "%s -> Invalid Mode.\n", __func__);
 228                 break;
 229         }
 230 }
 231
 232 static void pch_can_set_optmode(struct pch_can_priv *priv)
 233 {
 234         u32 reg_val = ioread32(&priv->regs->opt);
 235
 236         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 237                 reg_val |= PCH_OPT_SILENT;
 238
 239         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 240                 reg_val |= PCH_OPT_LBACK;
 241
 242         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
 243         iowrite32(reg_val, &priv->regs->opt);
 244 }
 245
 246 static void pch_can_set_int_custom(struct pch_can_priv *priv)
 247 {
 248         /* Clearing the IE, SIE and EIE bits of Can control register. */
 249         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 250
 251         /* Appropriately setting them. */
 252         pch_can_bit_set(&priv->regs->cont,
 253                         ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
 254 }
 255
 256 /* This function retrieves interrupt enabled for the CAN device. */
 257 static void pch_can_get_int_enables(struct pch_can_priv *priv, u32 *enables)
 258 {
 259         /* Obtaining the status of IE, SIE and EIE interrupt bits. */
 260         *enables = ((ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1);
 261 }
 262
 263 static void pch_can_set_int_enables(struct pch_can_priv *priv,
 264                                     enum pch_can_mode interrupt_no)
 265 {
 266         switch (interrupt_no) {
 267         case PCH_CAN_ENABLE:
 268                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE);
 269                 break;
 270
 271         case PCH_CAN_DISABLE:
 272                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
 273                 break;
 274
 275         case PCH_CAN_ALL:
 276                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 277                 break;
 278
 279         case PCH_CAN_NONE:
 280                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 281                 break;
 282
 283         default:
 284                 dev_err(&priv->ndev->dev, "Invalid interrupt number.\n");
 285                 break;
 286         }
 287 }
 288
 289 static void pch_can_check_if_busy(u32 __iomem *creq_addr, u32 num)
 290 {
 291         u32 counter = PCH_COUNTER_LIMIT;
 292         u32 ifx_creq;
 293
 294         iowrite32(num, creq_addr);
 295         while (counter) {
 296                 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
 297                 if (!ifx_creq)
 298                         break;
 299                 counter--;
 300                 udelay(1);
 301         }
 302         if (!counter)
 303                 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
 304 }
 305
 306 static void pch_can_set_rx_enable(struct pch_can_priv *priv, u32 buff_num,
 307                                   u32 set)
 308 {
 309         unsigned long flags;
 310
 311         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 312         /* Reading the receive buffer data from RAM to Interface1 registers */
 313         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 314         pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
 315
 316         /* Setting the IF1MASK1 register to access MsgVal and RxIE bits */
 317         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
 318                   &priv->regs->if1_cmask);
 319
 320         if (set == PCH_ENABLE) {
 321                 /* Setting the MsgVal and RxIE bits */
 322                 pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
 323                 pch_can_bit_set(&priv->regs->if1_id2, PCH_ID_MSGVAL);
 324
 325         } else if (set == PCH_DISABLE) {
 326                 /* Resetting the MsgVal and RxIE bits */
 327                 pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_RXIE);
 328                 pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID_MSGVAL);
 329         }
 330
 331         pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
 332         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 333 }
 334
 335 static void pch_can_rx_enable_all(struct pch_can_priv *priv)
 336 {
 337         int i;
 338
 339         /* Traversing to obtain the object configured as receivers. */
 340         for (i = 0; i < PCH_OBJ_NUM; i++) {
 341                 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
 342                         pch_can_set_rx_enable(priv, i + 1, PCH_ENABLE);
 343         }
 344 }
 345
 346 static void pch_can_rx_disable_all(struct pch_can_priv *priv)
 347 {
 348         int i;
 349
 350         /* Traversing to obtain the object configured as receivers. */
 351         for (i = 0; i < PCH_OBJ_NUM; i++) {
 352                 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX)
 353                         pch_can_set_rx_enable(priv, i + 1, PCH_DISABLE);
 354         }
 355 }
 356
 357 static void pch_can_set_tx_enable(struct pch_can_priv *priv, u32 buff_num,
 358                                  u32 set)
 359 {
 360         unsigned long flags;
 361
 362         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 363         /* Reading the Msg buffer from Message RAM to Interface2 registers. */
 364         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
 365         pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
 366
 367         /* Setting the IF2CMASK register for accessing the
 368                 MsgVal and TxIE bits */
 369         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
 370                  &priv->regs->if2_cmask);
 371
 372         if (set == PCH_ENABLE) {
 373                 /* Setting the MsgVal and TxIE bits */
 374                 pch_can_bit_set(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
 375                 pch_can_bit_set(&priv->regs->if2_id2, PCH_ID_MSGVAL);
 376         } else if (set == PCH_DISABLE) {
 377                 /* Resetting the MsgVal and TxIE bits. */
 378                 pch_can_bit_clear(&priv->regs->if2_mcont, PCH_IF_MCONT_TXIE);
 379                 pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID_MSGVAL);
 380         }
 381
 382         pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
 383         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 384 }
 385
 386 static void pch_can_tx_enable_all(struct pch_can_priv *priv)
 387 {
 388         int i;
 389
 390         /* Traversing to obtain the object configured as transmit object. */
 391         for (i = 0; i < PCH_OBJ_NUM; i++) {
 392                 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
 393                         pch_can_set_tx_enable(priv, i + 1, PCH_ENABLE);
 394         }
 395 }
 396
 397 static void pch_can_tx_disable_all(struct pch_can_priv *priv)
 398 {
 399         int i;
 400
 401         /* Traversing to obtain the object configured as transmit object. */
 402         for (i = 0; i < PCH_OBJ_NUM; i++) {
 403                 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
 404                         pch_can_set_tx_enable(priv, i + 1, PCH_DISABLE);
 405         }
 406 }
 407
 408 static void pch_can_get_rx_enable(struct pch_can_priv *priv, u32 buff_num,
 409                                  u32 *enable)
 410 {
 411         unsigned long flags;
 412
 413         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 414         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 415         pch_can_check_if_busy(&priv->regs->if1_creq, buff_num);
 416
 417         if (((ioread32(&priv->regs->if1_id2)) & PCH_ID_MSGVAL) &&
 418                         ((ioread32(&priv->regs->if1_mcont)) &
 419                         PCH_IF_MCONT_RXIE))
 420                 *enable = PCH_ENABLE;
 421         else
 422                 *enable = PCH_DISABLE;
 423         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 424 }
 425
 426 static void pch_can_get_tx_enable(struct pch_can_priv *priv, u32 buff_num,
 427                                  u32 *enable)
 428 {
 429         unsigned long flags;
 430
 431         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 432         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
 433         pch_can_check_if_busy(&priv->regs->if2_creq, buff_num);
 434
 435         if (((ioread32(&priv->regs->if2_id2)) & PCH_ID_MSGVAL) &&
 436                         ((ioread32(&priv->regs->if2_mcont)) &
 437                         PCH_IF_MCONT_TXIE)) {
 438                 *enable = PCH_ENABLE;
 439         } else {
 440                 *enable = PCH_DISABLE;
 441         }
 442         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 443 }
 444
 445 static int pch_can_int_pending(struct pch_can_priv *priv)
 446 {
 447         return ioread32(&priv->regs->intr) & 0xffff;
 448 }
 449
 450 static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
 451                                        u32 buffer_num, u32 set)
 452 {
 453         unsigned long flags;
 454
 455         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 456         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 457         pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
 458         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL, &priv->regs->if1_cmask);
 459         if (set == PCH_ENABLE)
 460                 pch_can_bit_clear(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
 461         else
 462                 pch_can_bit_set(&priv->regs->if1_mcont, PCH_IF_MCONT_EOB);
 463
 464         pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
 465         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 466 }
 467
 468 static void pch_can_get_rx_buffer_link(struct pch_can_priv *priv,
 469                                        u32 buffer_num, u32 *link)
 470 {
 471         unsigned long flags;
 472
 473         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 474         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 475         pch_can_check_if_busy(&priv->regs->if1_creq, buffer_num);
 476
 477         if (ioread32(&priv->regs->if1_mcont) & PCH_IF_MCONT_EOB)
 478                 *link = PCH_DISABLE;
 479         else
 480                 *link = PCH_ENABLE;
 481         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 482 }
 483
 484 static void pch_can_clear_buffers(struct pch_can_priv *priv)
 485 {
 486         int i;
 487
 488         for (i = 0; i < PCH_RX_OBJ_NUM; i++) {
 489                 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if1_cmask);
 490                 iowrite32(0xffff, &priv->regs->if1_mask1);
 491                 iowrite32(0xffff, &priv->regs->if1_mask2);
 492                 iowrite32(0x0, &priv->regs->if1_id1);
 493                 iowrite32(0x0, &priv->regs->if1_id2);
 494                 iowrite32(0x0, &priv->regs->if1_mcont);
 495                 iowrite32(0x0, &priv->regs->if1_dataa1);
 496                 iowrite32(0x0, &priv->regs->if1_dataa2);
 497                 iowrite32(0x0, &priv->regs->if1_datab1);
 498                 iowrite32(0x0, &priv->regs->if1_datab2);
 499                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
 500                           PCH_CMASK_ARB | PCH_CMASK_CTRL,
 501                           &priv->regs->if1_cmask);
 502                 pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
 503         }
 504
 505         for (i = i;  i < PCH_OBJ_NUM; i++) {
 506                 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->if2_cmask);
 507                 iowrite32(0xffff, &priv->regs->if2_mask1);
 508                 iowrite32(0xffff, &priv->regs->if2_mask2);
 509                 iowrite32(0x0, &priv->regs->if2_id1);
 510                 iowrite32(0x0, &priv->regs->if2_id2);
 511                 iowrite32(0x0, &priv->regs->if2_mcont);
 512                 iowrite32(0x0, &priv->regs->if2_dataa1);
 513                 iowrite32(0x0, &priv->regs->if2_dataa2);
 514                 iowrite32(0x0, &priv->regs->if2_datab1);
 515                 iowrite32(0x0, &priv->regs->if2_datab2);
 516                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
 517                           PCH_CMASK_ARB | PCH_CMASK_CTRL,
 518                           &priv->regs->if2_cmask);
 519                 pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
 520         }
 521 }
 522
 523 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
 524 {
 525         int i;
 526         unsigned long flags;
 527
 528         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 529
 530         for (i = 0; i < PCH_OBJ_NUM; i++) {
 531                 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
 532                         iowrite32(PCH_CMASK_RX_TX_GET,
 533                                 &priv->regs->if1_cmask);
 534                         pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
 535
 536                         iowrite32(0x0, &priv->regs->if1_id1);
 537                         iowrite32(0x0, &priv->regs->if1_id2);
 538
 539                         pch_can_bit_set(&priv->regs->if1_mcont,
 540                                         PCH_IF_MCONT_UMASK);
 541
 542                         /* Set FIFO mode set to 0 except last Rx Obj*/
 543                         pch_can_bit_clear(&priv->regs->if1_mcont,
 544                                           PCH_IF_MCONT_EOB);
 545                         /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
 546                         if (i == (PCH_RX_OBJ_NUM - 1))
 547                                 pch_can_bit_set(&priv->regs->if1_mcont,
 548                                                   PCH_IF_MCONT_EOB);
 549
 550                         iowrite32(0, &priv->regs->if1_mask1);
 551                         pch_can_bit_clear(&priv->regs->if1_mask2,
 552                                           0x1fff | PCH_MASK2_MDIR_MXTD);
 553
 554                         /* Setting CMASK for writing */
 555                         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
 556                                   PCH_CMASK_ARB | PCH_CMASK_CTRL,
 557                                   &priv->regs->if1_cmask);
 558
 559                         pch_can_check_if_busy(&priv->regs->if1_creq, i+1);
 560                 } else if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
 561                         iowrite32(PCH_CMASK_RX_TX_GET,
 562                                 &priv->regs->if2_cmask);
 563                         pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
 564
 565                         /* Resetting DIR bit for reception */
 566                         iowrite32(0x0, &priv->regs->if2_id1);
 567                         iowrite32(0x0, &priv->regs->if2_id2);
 568                         pch_can_bit_set(&priv->regs->if2_id2, PCH_ID2_DIR);
 569
 570                         /* Setting EOB bit for transmitter */
 571                         iowrite32(PCH_IF_MCONT_EOB, &priv->regs->if2_mcont);
 572
 573                         pch_can_bit_set(&priv->regs->if2_mcont,
 574                                         PCH_IF_MCONT_UMASK);
 575
 576                         iowrite32(0, &priv->regs->if2_mask1);
 577                         pch_can_bit_clear(&priv->regs->if2_mask2, 0x1fff);
 578
 579                         /* Setting CMASK for writing */
 580                         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
 581                                   PCH_CMASK_ARB | PCH_CMASK_CTRL,
 582                                   &priv->regs->if2_cmask);
 583
 584                         pch_can_check_if_busy(&priv->regs->if2_creq, i+1);
 585                 }
 586         }
 587         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 588 }
 589
 590 static void pch_can_init(struct pch_can_priv *priv)
 591 {
 592         /* Stopping the Can device. */
 593         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 594
 595         /* Clearing all the message object buffers. */
 596         pch_can_clear_buffers(priv);
 597
 598         /* Configuring the respective message object as either rx/tx object. */
 599         pch_can_config_rx_tx_buffers(priv);
 600
 601         /* Enabling the interrupts. */
 602         pch_can_set_int_enables(priv, PCH_CAN_ALL);
 603 }
 604
 605 static void pch_can_release(struct pch_can_priv *priv)
 606 {
 607         /* Stooping the CAN device. */
 608         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 609
 610         /* Disabling the interrupts. */
 611         pch_can_set_int_enables(priv, PCH_CAN_NONE);
 612
 613         /* Disabling all the receive object. */
 614         pch_can_rx_disable_all(priv);
 615
 616         /* Disabling all the transmit object. */
 617         pch_can_tx_disable_all(priv);
 618 }
 619
 620 /* This function clears interrupt(s) from the CAN device. */
 621 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
 622 {
 623         if (mask == PCH_STATUS_INT) {
 624                 ioread32(&priv->regs->stat);
 625                 return;
 626         }
 627
 628         /* Clear interrupt for transmit object */
 629         if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_TX) {
 630                 /* Setting CMASK for clearing interrupts for
 631                                          frame transmission. */
 632                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
 633                           &priv->regs->if2_cmask);
 634
 635                 /* Resetting the ID registers. */
 636                 pch_can_bit_set(&priv->regs->if2_id2,
 637                                PCH_ID2_DIR | (0x7ff << 2));
 638                 iowrite32(0x0, &priv->regs->if2_id1);
 639
 640                 /* Claring NewDat, TxRqst & IntPnd */
 641                 pch_can_bit_clear(&priv->regs->if2_mcont,
 642                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
 643                                   PCH_IF_MCONT_TXRQXT);
 644                 pch_can_check_if_busy(&priv->regs->if2_creq, mask);
 645         } else if (priv->msg_obj[mask - 1] == PCH_MSG_OBJ_RX) {
 646                 /* Setting CMASK for clearing the reception interrupts. */
 647                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
 648                           &priv->regs->if1_cmask);
 649
 650                 /* Clearing the Dir bit. */
 651                 pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
 652
 653                 /* Clearing NewDat & IntPnd */
 654                 pch_can_bit_clear(&priv->regs->if1_mcont,
 655                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
 656
 657                 pch_can_check_if_busy(&priv->regs->if1_creq, mask);
 658         }
 659 }
 660
 661 static int pch_can_get_buffer_status(struct pch_can_priv *priv)
 662 {
 663         return (ioread32(&priv->regs->treq1) & 0xffff) |
 664                ((ioread32(&priv->regs->treq2) & 0xffff) << 16);
 665 }
 666
 667 static void pch_can_reset(struct pch_can_priv *priv)
 668 {
 669         /* write to sw reset register */
 670         iowrite32(1, &priv->regs->srst);
 671         iowrite32(0, &priv->regs->srst);
 672 }
 673
 674 static void pch_can_error(struct net_device *ndev, u32 status)
 675 {
 676         struct sk_buff *skb;
 677         struct pch_can_priv *priv = netdev_priv(ndev);
 678         struct can_frame *cf;
 679         u32 errc;
 680         struct net_device_stats *stats = &(priv->ndev->stats);
 681         enum can_state state = priv->can.state;
 682
 683         skb = alloc_can_err_skb(ndev, &cf);
 684         if (!skb)
 685                 return;
 686
 687         if (status & PCH_BUS_OFF) {
 688                 pch_can_tx_disable_all(priv);
 689                 pch_can_rx_disable_all(priv);
 690                 state = CAN_STATE_BUS_OFF;
 691                 cf->can_id |= CAN_ERR_BUSOFF;
 692                 can_bus_off(ndev);
 693                 pch_can_set_run_mode(priv, PCH_CAN_RUN);
 694                 dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__);
 695         }
 696
 697         /* Warning interrupt. */
 698         if (status & PCH_EWARN) {
 699                 state = CAN_STATE_ERROR_WARNING;
 700                 priv->can.can_stats.error_warning++;
 701                 cf->can_id |= CAN_ERR_CRTL;
 702                 errc = ioread32(&priv->regs->errc);
 703                 if (((errc & PCH_REC) >> 8) > 96)
 704                         cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
 705                 if ((errc & PCH_TEC) > 96)
 706                         cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
 707                 dev_warn(&ndev->dev,
 708                         "%s -> Error Counter is more than 96.\n", __func__);
 709         }
 710         /* Error passive interrupt. */
 711         if (status & PCH_EPASSIV) {
 712                 priv->can.can_stats.error_passive++;
 713                 state = CAN_STATE_ERROR_PASSIVE;
 714                 cf->can_id |= CAN_ERR_CRTL;
 715                 errc = ioread32(&priv->regs->errc);
 716                 if (((errc & PCH_REC) >> 8) > 127)
 717                         cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 718                 if ((errc & PCH_TEC) > 127)
 719                         cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 720                 dev_err(&ndev->dev,
 721                         "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
 722         }
 723
 724         if (status & PCH_LEC_ALL) {
 725                 priv->can.can_stats.bus_error++;
 726                 stats->rx_errors++;
 727                 switch (status & PCH_LEC_ALL) {
 728                 case PCH_STUF_ERR:
 729                         cf->data[2] |= CAN_ERR_PROT_STUFF;
 730                         break;
 731                 case PCH_FORM_ERR:
 732                         cf->data[2] |= CAN_ERR_PROT_FORM;
 733                         break;
 734                 case PCH_ACK_ERR:
 735                         cf->data[2] |= CAN_ERR_PROT_LOC_ACK |
 736                                        CAN_ERR_PROT_LOC_ACK_DEL;
 737                         break;
 738                 case PCH_BIT1_ERR:
 739                 case PCH_BIT0_ERR:
 740                         cf->data[2] |= CAN_ERR_PROT_BIT;
 741                         break;
 742                 case PCH_CRC_ERR:
 743                         cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
 744                                        CAN_ERR_PROT_LOC_CRC_DEL;
 745                         break;
 746                 default:
 747                         iowrite32(status | PCH_LEC_ALL, &priv->regs->stat);
 748                         break;
 749                 }
 750
 751         }
 752
 753         priv->can.state = state;
 754         netif_rx(skb);
 755
 756         stats->rx_packets++;
 757         stats->rx_bytes += cf->can_dlc;
 758 }
 759
 760 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
 761 {
 762         struct net_device *ndev = (struct net_device *)dev_id;
 763         struct pch_can_priv *priv = netdev_priv(ndev);
 764
 765         pch_can_set_int_enables(priv, PCH_CAN_NONE);
 766
 767         napi_schedule(&priv->napi);
 768
 769         return IRQ_HANDLED;
 770 }
 771
 772 static int pch_can_rx_normal(struct net_device *ndev, u32 int_stat)
 773 {
 774         u32 reg;
 775         canid_t id;
 776         u32 ide;
 777         u32 rtr;
 778         int i, j, k;
 779         int rcv_pkts = 0;
 780         struct sk_buff *skb;
 781         struct can_frame *cf;
 782         struct pch_can_priv *priv = netdev_priv(ndev);
 783         struct net_device_stats *stats = &(priv->ndev->stats);
 784
 785         /* Reading the messsage object from the Message RAM */
 786         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 787         pch_can_check_if_busy(&priv->regs->if1_creq, int_stat);
 788
 789         /* Reading the MCONT register. */
 790         reg = ioread32(&priv->regs->if1_mcont);
 791         reg &= 0xffff;
 792
 793         for (k = int_stat; !(reg & PCH_IF_MCONT_EOB); k++) {
 794                 /* If MsgLost bit set. */
 795                 if (reg & PCH_IF_MCONT_MSGLOST) {
 796                         dev_err(&priv->ndev->dev, "Msg Obj is overwritten.\n");
 797                         pch_can_bit_clear(&priv->regs->if1_mcont,
 798                                           PCH_IF_MCONT_MSGLOST);
 799                         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
 800                                   &priv->regs->if1_cmask);
 801                         pch_can_check_if_busy(&priv->regs->if1_creq, k);
 802
 803                         skb = alloc_can_err_skb(ndev, &cf);
 804                         if (!skb)
 805                                 return -ENOMEM;
 806
 807                         priv->can.can_stats.error_passive++;
 808                         priv->can.state = CAN_STATE_ERROR_PASSIVE;
 809                         cf->can_id |= CAN_ERR_CRTL;
 810                         cf->data[1] |= CAN_ERR_CRTL_RX_OVERFLOW;
 811                         cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
 812                         stats->rx_packets++;
 813                         stats->rx_bytes += cf->can_dlc;
 814
 815                         netif_receive_skb(skb);
 816                         rcv_pkts++;
 817                         goto RX_NEXT;
 818                 }
 819                 if (!(reg & PCH_IF_MCONT_NEWDAT))
 820                         goto RX_NEXT;
 821
 822                 skb = alloc_can_skb(priv->ndev, &cf);
 823                 if (!skb)
 824                         return -ENOMEM;
 825
 826                 /* Get Received data */
 827                 ide = ((ioread32(&priv->regs->if1_id2)) & PCH_ID2_XTD) >> 14;
 828                 if (ide) {
 829                         id = (ioread32(&priv->regs->if1_id1) & 0xffff);
 830                         id |= (((ioread32(&priv->regs->if1_id2)) &
 831                                             0x1fff) << 16);
 832                         cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
 833                 } else {
 834                         id = (((ioread32(&priv->regs->if1_id2)) &
 835                                           (CAN_SFF_MASK << 2)) >> 2);
 836                         cf->can_id = (id & CAN_SFF_MASK);
 837                 }
 838
 839                 rtr = (ioread32(&priv->regs->if1_id2) &  PCH_ID2_DIR);
 840                 if (rtr) {
 841                         cf->can_dlc = 0;
 842                         cf->can_id |= CAN_RTR_FLAG;
 843                 } else {
 844                         cf->can_dlc = ((ioread32(&priv->regs->if1_mcont)) &
 845                                                    0x0f);
 846                 }
 847
 848                 for (i = 0, j = 0; i < cf->can_dlc; j++) {
 849                         reg = ioread32(&priv->regs->if1_dataa1 + j*4);
 850                         cf->data[i++] = cpu_to_le32(reg & 0xff);
 851                         if (i == cf->can_dlc)
 852                                 break;
 853                         cf->data[i++] = cpu_to_le32((reg >> 8) & 0xff);
 854                 }
 855
 856                 netif_receive_skb(skb);
 857                 rcv_pkts++;
 858                 stats->rx_packets++;
 859                 stats->rx_bytes += cf->can_dlc;
 860
 861                 if (k < PCH_FIFO_THRESH) {
 862                         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
 863                                   PCH_CMASK_ARB, &priv->regs->if1_cmask);
 864
 865                         /* Clearing the Dir bit. */
 866                         pch_can_bit_clear(&priv->regs->if1_id2, PCH_ID2_DIR);
 867
 868                         /* Clearing NewDat & IntPnd */
 869                         pch_can_bit_clear(&priv->regs->if1_mcont,
 870                                           PCH_IF_MCONT_INTPND);
 871                         pch_can_check_if_busy(&priv->regs->if1_creq, k);
 872                 } else if (k > PCH_FIFO_THRESH) {
 873                         pch_can_int_clr(priv, k);
 874                 } else if (k == PCH_FIFO_THRESH) {
 875                         int cnt;
 876                         for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
 877                                 pch_can_int_clr(priv, cnt+1);
 878                 }
 879 RX_NEXT:
 880                 /* Reading the messsage object from the Message RAM */
 881                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if1_cmask);
 882                 pch_can_check_if_busy(&priv->regs->if1_creq, k + 1);
 883                 reg = ioread32(&priv->regs->if1_mcont);
 884         }
 885
 886         return rcv_pkts;
 887 }
 888 static int pch_can_rx_poll(struct napi_struct *napi, int quota)
 889 {
 890         struct net_device *ndev = napi->dev;
 891         struct pch_can_priv *priv = netdev_priv(ndev);
 892         struct net_device_stats *stats = &(priv->ndev->stats);
 893         u32 dlc;
 894         u32 int_stat;
 895         int rcv_pkts = 0;
 896         u32 reg_stat;
 897         unsigned long flags;
 898
 899         int_stat = pch_can_int_pending(priv);
 900         if (!int_stat)
 901                 return 0;
 902
 903 INT_STAT:
 904         if (int_stat == PCH_STATUS_INT) {
 905                 reg_stat = ioread32(&priv->regs->stat);
 906                 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
 907                         if ((reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL)
 908                                 pch_can_error(ndev, reg_stat);
 909                 }
 910
 911                 if (reg_stat & PCH_TX_OK) {
 912                         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 913                         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
 914                         pch_can_check_if_busy(&priv->regs->if2_creq,
 915                                                ioread32(&priv->regs->intr));
 916                         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 917                         pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
 918                 }
 919
 920                 if (reg_stat & PCH_RX_OK)
 921                         pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
 922
 923                 int_stat = pch_can_int_pending(priv);
 924                 if (int_stat == PCH_STATUS_INT)
 925                         goto INT_STAT;
 926         }
 927
 928 MSG_OBJ:
 929         if ((int_stat >= 1) && (int_stat <= PCH_RX_OBJ_NUM)) {
 930                 spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 931                 rcv_pkts = pch_can_rx_normal(ndev, int_stat);
 932                 spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 933                 if (rcv_pkts < 0)
 934                         return 0;
 935         } else if ((int_stat > PCH_RX_OBJ_NUM) && (int_stat <= PCH_OBJ_NUM)) {
 936                 if (priv->msg_obj[int_stat - 1] == PCH_MSG_OBJ_TX) {
 937                         /* Handle transmission interrupt */
 938                         can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_NUM - 1);
 939                         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
 940                         iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
 941                                   &priv->regs->if2_cmask);
 942                         dlc = ioread32(&priv->regs->if2_mcont) &
 943                                        PCH_IF_MCONT_DLC;
 944                         pch_can_check_if_busy(&priv->regs->if2_creq, int_stat);
 945                         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
 946                         if (dlc > 8)
 947                                 dlc = 8;
 948                         stats->tx_bytes += dlc;
 949                         stats->tx_packets++;
 950                 }
 951         }
 952
 953         int_stat = pch_can_int_pending(priv);
 954         if (int_stat == PCH_STATUS_INT)
 955                 goto INT_STAT;
 956         else if (int_stat >= 1 && int_stat <= 32)
 957                 goto MSG_OBJ;
 958
 959         napi_complete(napi);
 960         pch_can_set_int_enables(priv, PCH_CAN_ALL);
 961
 962         return rcv_pkts;
 963 }
 964
 965 static int pch_set_bittiming(struct net_device *ndev)
 966 {
 967         struct pch_can_priv *priv = netdev_priv(ndev);
 968         const struct can_bittiming *bt = &priv->can.bittiming;
 969         u32 canbit;
 970         u32 bepe;
 971         u32 brp;
 972
 973         /* Setting the CCE bit for accessing the Can Timing register. */
 974         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
 975
 976         brp = (bt->tq) / (1000000000/PCH_CAN_CLK) - 1;
 977         canbit = brp & PCH_MSK_BITT_BRP;
 978         canbit |= (bt->sjw - 1) << PCH_BIT_SJW;
 979         canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1;
 980         canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2;
 981         bepe = (brp & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE;
 982         iowrite32(canbit, &priv->regs->bitt);
 983         iowrite32(bepe, &priv->regs->brpe);
 984         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
 985
 986         return 0;
 987 }
 988
 989 static void pch_can_start(struct net_device *ndev)
 990 {
 991         struct pch_can_priv *priv = netdev_priv(ndev);
 992
 993         if (priv->can.state != CAN_STATE_STOPPED)
 994                 pch_can_reset(priv);
 995
 996         pch_set_bittiming(ndev);
 997         pch_can_set_optmode(priv);
 998
 999         pch_can_tx_enable_all(priv);
1000         pch_can_rx_enable_all(priv);
1001
1002         /* Setting the CAN to run mode. */
1003         pch_can_set_run_mode(priv, PCH_CAN_RUN);
1004
1005         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1006
1007         return;
1008 }
1009
1010 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
1011 {
1012         int ret = 0;
1013
1014         switch (mode) {
1015         case CAN_MODE_START:
1016                 pch_can_start(ndev);
1017                 netif_wake_queue(ndev);
1018                 break;
1019         default:
1020                 ret = -EOPNOTSUPP;
1021                 break;
1022         }
1023
1024         return ret;
1025 }
1026
1027 static int pch_can_open(struct net_device *ndev)
1028 {
1029         struct pch_can_priv *priv = netdev_priv(ndev);
1030         int retval;
1031
1032         retval = pci_enable_msi(priv->dev);
1033         if (retval) {
1034                 dev_info(&ndev->dev, "PCH CAN opened without MSI\n");
1035                 priv->use_msi = 0;
1036         } else {
1037                 dev_info(&ndev->dev, "PCH CAN opened with MSI\n");
1038                 priv->use_msi = 1;
1039         }
1040
1041         /* Regsitering the interrupt. */
1042         retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
1043                              ndev->name, ndev);
1044         if (retval) {
1045                 dev_err(&ndev->dev, "request_irq failed.\n");
1046                 goto req_irq_err;
1047         }
1048
1049         /* Open common can device */
1050         retval = open_candev(ndev);
1051         if (retval) {
1052                 dev_err(ndev->dev.parent, "open_candev() failed %d\n", retval);
1053                 goto err_open_candev;
1054         }
1055
1056         pch_can_init(priv);
1057         pch_can_start(ndev);
1058         napi_enable(&priv->napi);
1059         netif_start_queue(ndev);
1060
1061         return 0;
1062
1063 err_open_candev:
1064         free_irq(priv->dev->irq, ndev);
1065 req_irq_err:
1066         if (priv->use_msi)
1067                 pci_disable_msi(priv->dev);
1068
1069         pch_can_release(priv);
1070
1071         return retval;
1072 }
1073
1074 static int pch_close(struct net_device *ndev)
1075 {
1076         struct pch_can_priv *priv = netdev_priv(ndev);
1077
1078         netif_stop_queue(ndev);
1079         napi_disable(&priv->napi);
1080         pch_can_release(priv);
1081         free_irq(priv->dev->irq, ndev);
1082         if (priv->use_msi)
1083                 pci_disable_msi(priv->dev);
1084         close_candev(ndev);
1085         priv->can.state = CAN_STATE_STOPPED;
1086         return 0;
1087 }
1088
1089 static int pch_get_msg_obj_sts(struct net_device *ndev, u32 obj_id)
1090 {
1091         u32 buffer_status = 0;
1092         struct pch_can_priv *priv = netdev_priv(ndev);
1093
1094         /* Getting the message object status. */
1095         buffer_status = (u32) pch_can_get_buffer_status(priv);
1096
1097         return buffer_status & obj_id;
1098 }
1099
1100
1101 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
1102 {
1103         int i, j;
1104         unsigned long flags;
1105         struct pch_can_priv *priv = netdev_priv(ndev);
1106         struct can_frame *cf = (struct can_frame *)skb->data;
1107         int tx_buffer_avail = 0;
1108
1109         if (can_dropped_invalid_skb(ndev, skb))
1110                 return NETDEV_TX_OK;
1111
1112         if (priv->tx_obj == (PCH_OBJ_NUM + 1)) { /* Point tail Obj */
1113                 while (pch_get_msg_obj_sts(ndev, (((1 << PCH_TX_OBJ_NUM)-1) <<
1114                                            PCH_RX_OBJ_NUM)))
1115                         udelay(500);
1116
1117                 priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj ID */
1118                 tx_buffer_avail = priv->tx_obj; /* Point Tail of Tx Obj */
1119         } else {
1120                 tx_buffer_avail = priv->tx_obj;
1121         }
1122         priv->tx_obj++;
1123
1124         /* Attaining the lock. */
1125         spin_lock_irqsave(&priv->msgif_reg_lock, flags);
1126
1127         /* Reading the Msg Obj from the Msg RAM to the Interface register. */
1128         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->if2_cmask);
1129         pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
1130
1131         /* Setting the CMASK register. */
1132         pch_can_bit_set(&priv->regs->if2_cmask, PCH_CMASK_ALL);
1133
1134         /* If ID extended is set. */
1135         pch_can_bit_clear(&priv->regs->if2_id1, 0xffff);
1136         pch_can_bit_clear(&priv->regs->if2_id2, 0x1fff | PCH_ID2_XTD);
1137         if (cf->can_id & CAN_EFF_FLAG) {
1138                 pch_can_bit_set(&priv->regs->if2_id1, cf->can_id & 0xffff);
1139                 pch_can_bit_set(&priv->regs->if2_id2,
1140                                 ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD);
1141         } else {
1142                 pch_can_bit_set(&priv->regs->if2_id1, 0);
1143                 pch_can_bit_set(&priv->regs->if2_id2,
1144                                 (cf->can_id & CAN_SFF_MASK) << 2);
1145         }
1146
1147         /* If remote frame has to be transmitted.. */
1148         if (cf->can_id & CAN_RTR_FLAG)
1149                 pch_can_bit_clear(&priv->regs->if2_id2, PCH_ID2_DIR);
1150
1151         for (i = 0, j = 0; i < cf->can_dlc; j++) {
1152                 iowrite32(le32_to_cpu(cf->data[i++]),
1153                          (&priv->regs->if2_dataa1) + j*4);
1154                 if (i == cf->can_dlc)
1155                         break;
1156                 iowrite32(le32_to_cpu(cf->data[i++] << 8),
1157                          (&priv->regs->if2_dataa1) + j*4);
1158         }
1159
1160         can_put_echo_skb(skb, ndev, tx_buffer_avail - PCH_RX_OBJ_NUM - 1);
1161
1162         /* Updating the size of the data. */
1163         pch_can_bit_clear(&priv->regs->if2_mcont, 0x0f);
1164         pch_can_bit_set(&priv->regs->if2_mcont, cf->can_dlc);
1165
1166         /* Clearing IntPend, NewDat & TxRqst */
1167         pch_can_bit_clear(&priv->regs->if2_mcont,
1168                           PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
1169                           PCH_IF_MCONT_TXRQXT);
1170
1171         /* Setting NewDat, TxRqst bits */
1172         pch_can_bit_set(&priv->regs->if2_mcont,
1173                         PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT);
1174
1175         pch_can_check_if_busy(&priv->regs->if2_creq, tx_buffer_avail);
1176
1177         spin_unlock_irqrestore(&priv->msgif_reg_lock, flags);
1178
1179         return NETDEV_TX_OK;
1180 }
1181
1182 static const struct net_device_ops pch_can_netdev_ops = {
1183         .ndo_open               = pch_can_open,
1184         .ndo_stop               = pch_close,
1185         .ndo_start_xmit         = pch_xmit,
1186 };
1187
1188 static void __devexit pch_can_remove(struct pci_dev *pdev)
1189 {
1190         struct net_device *ndev = pci_get_drvdata(pdev);
1191         struct pch_can_priv *priv = netdev_priv(ndev);
1192
1193         unregister_candev(priv->ndev);
1194         free_candev(priv->ndev);
1195         pci_iounmap(pdev, priv->regs);
1196         pci_release_regions(pdev);
1197         pci_disable_device(pdev);
1198         pci_set_drvdata(pdev, NULL);
1199         pch_can_reset(priv);
1200 }
1201
1202 #ifdef CONFIG_PM
1203 static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1204 {
1205         int i;                  /* Counter variable. */
1206         int retval;             /* Return value. */
1207         u32 buf_stat;   /* Variable for reading the transmit buffer status. */
1208         u32 counter = 0xFFFFFF;
1209
1210         struct net_device *dev = pci_get_drvdata(pdev);
1211         struct pch_can_priv *priv = netdev_priv(dev);
1212
1213         /* Stop the CAN controller */
1214         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1215
1216         /* Indicate that we are aboutto/in suspend */
1217         priv->can.state = CAN_STATE_SLEEPING;
1218
1219         /* Waiting for all transmission to complete. */
1220         while (counter) {
1221                 buf_stat = pch_can_get_buffer_status(priv);
1222                 if (!buf_stat)
1223                         break;
1224                 counter--;
1225                 udelay(1);
1226         }
1227         if (!counter)
1228                 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1229
1230         /* Save interrupt configuration and then disable them */
1231         pch_can_get_int_enables(priv, &(priv->int_enables));
1232         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1233
1234         /* Save Tx buffer enable state */
1235         for (i = 0; i < PCH_OBJ_NUM; i++) {
1236                 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX)
1237                         pch_can_get_tx_enable(priv, i + 1,
1238                                               &(priv->tx_enable[i]));
1239         }
1240
1241         /* Disable all Transmit buffers */
1242         pch_can_tx_disable_all(priv);
1243
1244         /* Save Rx buffer enable state */
1245         for (i = 0; i < PCH_OBJ_NUM; i++) {
1246                 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
1247                         pch_can_get_rx_enable(priv, i + 1,
1248                                                 &(priv->rx_enable[i]));
1249                         pch_can_get_rx_buffer_link(priv, i + 1,
1250                                                 &(priv->rx_link[i]));
1251                 }
1252         }
1253
1254         /* Disable all Receive buffers */
1255         pch_can_rx_disable_all(priv);
1256         retval = pci_save_state(pdev);
1257         if (retval) {
1258                 dev_err(&pdev->dev, "pci_save_state failed.\n");
1259         } else {
1260                 pci_enable_wake(pdev, PCI_D3hot, 0);
1261                 pci_disable_device(pdev);
1262                 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1263         }
1264
1265         return retval;
1266 }
1267
1268 static int pch_can_resume(struct pci_dev *pdev)
1269 {
1270         int i;                  /* Counter variable. */
1271         int retval;             /* Return variable. */
1272         struct net_device *dev = pci_get_drvdata(pdev);
1273         struct pch_can_priv *priv = netdev_priv(dev);
1274
1275         pci_set_power_state(pdev, PCI_D0);
1276         pci_restore_state(pdev);
1277         retval = pci_enable_device(pdev);
1278         if (retval) {
1279                 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1280                 return retval;
1281         }
1282
1283         pci_enable_wake(pdev, PCI_D3hot, 0);
1284
1285         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1286
1287         /* Disabling all interrupts. */
1288         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1289
1290         /* Setting the CAN device in Stop Mode. */
1291         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1292
1293         /* Configuring the transmit and receive buffers. */
1294         pch_can_config_rx_tx_buffers(priv);
1295
1296         /* Restore the CAN state */
1297         pch_set_bittiming(dev);
1298
1299         /* Listen/Active */
1300         pch_can_set_optmode(priv);
1301
1302         /* Enabling the transmit buffer. */
1303         for (i = 0; i < PCH_OBJ_NUM; i++) {
1304                 if (priv->msg_obj[i] == PCH_MSG_OBJ_TX) {
1305                         pch_can_set_tx_enable(priv, i + 1,
1306                                               priv->tx_enable[i]);
1307                 }
1308         }
1309
1310         /* Configuring the receive buffer and enabling them. */
1311         for (i = 0; i < PCH_OBJ_NUM; i++) {
1312                 if (priv->msg_obj[i] == PCH_MSG_OBJ_RX) {
1313                         /* Restore buffer link */
1314                         pch_can_set_rx_buffer_link(priv, i + 1,
1315                                                    priv->rx_link[i]);
1316
1317                         /* Restore buffer enables */
1318                         pch_can_set_rx_enable(priv, i + 1, priv->rx_enable[i]);
1319                 }
1320         }
1321
1322         /* Enable CAN Interrupts */
1323         pch_can_set_int_custom(priv);
1324
1325         /* Restore Run Mode */
1326         pch_can_set_run_mode(priv, PCH_CAN_RUN);
1327
1328         return retval;
1329 }
1330 #else
1331 #define pch_can_suspend NULL
1332 #define pch_can_resume NULL
1333 #endif
1334
1335 static int pch_can_get_berr_counter(const struct net_device *dev,
1336                                     struct can_berr_counter *bec)
1337 {
1338         struct pch_can_priv *priv = netdev_priv(dev);
1339
1340         bec->txerr = ioread32(&priv->regs->errc) & PCH_TEC;
1341         bec->rxerr = (ioread32(&priv->regs->errc) & PCH_REC) >> 8;
1342
1343         return 0;
1344 }
1345
1346 static int __devinit pch_can_probe(struct pci_dev *pdev,
1347                                    const struct pci_device_id *id)
1348 {
1349         struct net_device *ndev;
1350         struct pch_can_priv *priv;
1351         int rc;
1352         int index;
1353         void __iomem *addr;
1354
1355         rc = pci_enable_device(pdev);
1356         if (rc) {
1357                 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1358                 goto probe_exit_endev;
1359         }
1360
1361         rc = pci_request_regions(pdev, KBUILD_MODNAME);
1362         if (rc) {
1363                 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1364                 goto probe_exit_pcireq;
1365         }
1366
1367         addr = pci_iomap(pdev, 1, 0);
1368         if (!addr) {
1369                 rc = -EIO;
1370                 dev_err(&pdev->dev, "Failed pci_iomap\n");
1371                 goto probe_exit_ipmap;
1372         }
1373
1374         ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_NUM);
1375         if (!ndev) {
1376                 rc = -ENOMEM;
1377                 dev_err(&pdev->dev, "Failed alloc_candev\n");
1378                 goto probe_exit_alloc_candev;
1379         }
1380
1381         priv = netdev_priv(ndev);
1382         priv->ndev = ndev;
1383         priv->regs = addr;
1384         priv->dev = pdev;
1385         priv->can.bittiming_const = &pch_can_bittiming_const;
1386         priv->can.do_set_mode = pch_can_do_set_mode;
1387         priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1388         priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1389                                        CAN_CTRLMODE_LOOPBACK;
1390         priv->tx_obj = PCH_RX_OBJ_NUM + 1; /* Point head of Tx Obj */
1391
1392         ndev->irq = pdev->irq;
1393         ndev->flags |= IFF_ECHO;
1394
1395         pci_set_drvdata(pdev, ndev);
1396         SET_NETDEV_DEV(ndev, &pdev->dev);
1397         ndev->netdev_ops = &pch_can_netdev_ops;
1398
1399         priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1400         for (index = 0; index < PCH_RX_OBJ_NUM;)
1401                 priv->msg_obj[index++] = PCH_MSG_OBJ_RX;
1402
1403         for (index = index;  index < PCH_OBJ_NUM;)
1404                 priv->msg_obj[index++] = PCH_MSG_OBJ_TX;
1405
1406         netif_napi_add(ndev, &priv->napi, pch_can_rx_poll, PCH_RX_OBJ_NUM);
1407
1408         rc = register_candev(ndev);
1409         if (rc) {
1410                 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1411                 goto probe_exit_reg_candev;
1412         }
1413
1414         return 0;
1415
1416 probe_exit_reg_candev:
1417         free_candev(ndev);
1418 probe_exit_alloc_candev:
1419         pci_iounmap(pdev, addr);
1420 probe_exit_ipmap:
1421         pci_release_regions(pdev);
1422 probe_exit_pcireq:
1423         pci_disable_device(pdev);
1424 probe_exit_endev:
1425         return rc;
1426 }
1427
1428 static struct pci_driver pch_can_pci_driver = {
1429         .name = "pch_can",
1430         .id_table = pch_pci_tbl,
1431         .probe = pch_can_probe,
1432         .remove = __devexit_p(pch_can_remove),
1433         .suspend = pch_can_suspend,
1434         .resume = pch_can_resume,
1435 };
1436
1437 static int __init pch_can_pci_init(void)
1438 {
1439         return pci_register_driver(&pch_can_pci_driver);
1440 }
1441 module_init(pch_can_pci_init);
1442
1443 static void __exit pch_can_pci_exit(void)
1444 {
1445         pci_unregister_driver(&pch_can_pci_driver);
1446 }
1447 module_exit(pch_can_pci_exit);
1448
1449 MODULE_DESCRIPTION("Controller Area Network Driver");
1450 MODULE_LICENSE("GPL v2");
1451 MODULE_VERSION("0.94");