2 * Definitions of consts/structs to drive the Freescale MSCAN.
4 * Copyright (C) 2005-2006 Andrey Volkov <avolkov@varma-el.com>,
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the version 2 of the GNU General Public License
9 * as published by the Free Software Foundation
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/types.h>
26 /* MSCAN control register 0 (CANCTL0) bits */
27 #define MSCAN_RXFRM 0x80
28 #define MSCAN_RXACT 0x40
29 #define MSCAN_CSWAI 0x20
30 #define MSCAN_SYNCH 0x10
31 #define MSCAN_TIME 0x08
32 #define MSCAN_WUPE 0x04
33 #define MSCAN_SLPRQ 0x02
34 #define MSCAN_INITRQ 0x01
36 /* MSCAN control register 1 (CANCTL1) bits */
37 #define MSCAN_CANE 0x80
38 #define MSCAN_CLKSRC 0x40
39 #define MSCAN_LOOPB 0x20
40 #define MSCAN_LISTEN 0x10
41 #define MSCAN_WUPM 0x04
42 #define MSCAN_SLPAK 0x02
43 #define MSCAN_INITAK 0x01
45 /* Use the MPC5200 MSCAN variant? */
47 #define MSCAN_FOR_MPC5200
50 #ifdef MSCAN_FOR_MPC5200
51 #define MSCAN_CLKSRC_BUS 0
52 #define MSCAN_CLKSRC_XTAL MSCAN_CLKSRC
54 #define MSCAN_CLKSRC_BUS MSCAN_CLKSRC
55 #define MSCAN_CLKSRC_XTAL 0
58 /* MSCAN receiver flag register (CANRFLG) bits */
59 #define MSCAN_WUPIF 0x80
60 #define MSCAN_CSCIF 0x40
61 #define MSCAN_RSTAT1 0x20
62 #define MSCAN_RSTAT0 0x10
63 #define MSCAN_TSTAT1 0x08
64 #define MSCAN_TSTAT0 0x04
65 #define MSCAN_OVRIF 0x02
66 #define MSCAN_RXF 0x01
67 #define MSCAN_ERR_IF (MSCAN_OVRIF | MSCAN_CSCIF)
68 #define MSCAN_RSTAT_MSK (MSCAN_RSTAT1 | MSCAN_RSTAT0)
69 #define MSCAN_TSTAT_MSK (MSCAN_TSTAT1 | MSCAN_TSTAT0)
70 #define MSCAN_STAT_MSK (MSCAN_RSTAT_MSK | MSCAN_TSTAT_MSK)
72 #define MSCAN_STATE_BUS_OFF (MSCAN_RSTAT1 | MSCAN_RSTAT0 | \
73 MSCAN_TSTAT1 | MSCAN_TSTAT0)
74 #define MSCAN_STATE_TX(canrflg) (((canrflg)&MSCAN_TSTAT_MSK)>>2)
75 #define MSCAN_STATE_RX(canrflg) (((canrflg)&MSCAN_RSTAT_MSK)>>4)
76 #define MSCAN_STATE_ACTIVE 0
77 #define MSCAN_STATE_WARNING 1
78 #define MSCAN_STATE_PASSIVE 2
79 #define MSCAN_STATE_BUSOFF 3
81 /* MSCAN receiver interrupt enable register (CANRIER) bits */
82 #define MSCAN_WUPIE 0x80
83 #define MSCAN_CSCIE 0x40
84 #define MSCAN_RSTATE1 0x20
85 #define MSCAN_RSTATE0 0x10
86 #define MSCAN_TSTATE1 0x08
87 #define MSCAN_TSTATE0 0x04
88 #define MSCAN_OVRIE 0x02
89 #define MSCAN_RXFIE 0x01
91 /* MSCAN transmitter flag register (CANTFLG) bits */
92 #define MSCAN_TXE2 0x04
93 #define MSCAN_TXE1 0x02
94 #define MSCAN_TXE0 0x01
95 #define MSCAN_TXE (MSCAN_TXE2 | MSCAN_TXE1 | MSCAN_TXE0)
97 /* MSCAN transmitter interrupt enable register (CANTIER) bits */
98 #define MSCAN_TXIE2 0x04
99 #define MSCAN_TXIE1 0x02
100 #define MSCAN_TXIE0 0x01
101 #define MSCAN_TXIE (MSCAN_TXIE2 | MSCAN_TXIE1 | MSCAN_TXIE0)
103 /* MSCAN transmitter message abort request (CANTARQ) bits */
104 #define MSCAN_ABTRQ2 0x04
105 #define MSCAN_ABTRQ1 0x02
106 #define MSCAN_ABTRQ0 0x01
108 /* MSCAN transmitter message abort ack (CANTAAK) bits */
109 #define MSCAN_ABTAK2 0x04
110 #define MSCAN_ABTAK1 0x02
111 #define MSCAN_ABTAK0 0x01
113 /* MSCAN transmit buffer selection (CANTBSEL) bits */
114 #define MSCAN_TX2 0x04
115 #define MSCAN_TX1 0x02
116 #define MSCAN_TX0 0x01
118 /* MSCAN ID acceptance control register (CANIDAC) bits */
119 #define MSCAN_IDAM1 0x20
120 #define MSCAN_IDAM0 0x10
121 #define MSCAN_IDHIT2 0x04
122 #define MSCAN_IDHIT1 0x02
123 #define MSCAN_IDHIT0 0x01
125 #define MSCAN_AF_32BIT 0x00
126 #define MSCAN_AF_16BIT MSCAN_IDAM0
127 #define MSCAN_AF_8BIT MSCAN_IDAM1
128 #define MSCAN_AF_CLOSED (MSCAN_IDAM0|MSCAN_IDAM1)
129 #define MSCAN_AF_MASK (~(MSCAN_IDAM0|MSCAN_IDAM1))
131 /* MSCAN Miscellaneous Register (CANMISC) bits */
132 #define MSCAN_BOHOLD 0x01
134 /* MSCAN Identifier Register (IDR) bits */
135 #define MSCAN_SFF_RTR_SHIFT 4
136 #define MSCAN_EFF_RTR_SHIFT 0
137 #define MSCAN_EFF_FLAGS 0x18 /* IDE + SRR */
139 #ifdef MSCAN_FOR_MPC5200
140 #define _MSCAN_RESERVED_(n, num) u8 _res##n[num]
141 #define _MSCAN_RESERVED_DSR_SIZE 2
143 #define _MSCAN_RESERVED_(n, num)
144 #define _MSCAN_RESERVED_DSR_SIZE 0
147 /* Structure of the hardware registers */
149 /* (see doc S12MSCANV3/D) MPC5200 MSCAN */
150 u8 canctl0; /* + 0x00 0x00 */
151 u8 canctl1; /* + 0x01 0x01 */
152 _MSCAN_RESERVED_(1, 2); /* + 0x02 */
153 u8 canbtr0; /* + 0x04 0x02 */
154 u8 canbtr1; /* + 0x05 0x03 */
155 _MSCAN_RESERVED_(2, 2); /* + 0x06 */
156 u8 canrflg; /* + 0x08 0x04 */
157 u8 canrier; /* + 0x09 0x05 */
158 _MSCAN_RESERVED_(3, 2); /* + 0x0a */
159 u8 cantflg; /* + 0x0c 0x06 */
160 u8 cantier; /* + 0x0d 0x07 */
161 _MSCAN_RESERVED_(4, 2); /* + 0x0e */
162 u8 cantarq; /* + 0x10 0x08 */
163 u8 cantaak; /* + 0x11 0x09 */
164 _MSCAN_RESERVED_(5, 2); /* + 0x12 */
165 u8 cantbsel; /* + 0x14 0x0a */
166 u8 canidac; /* + 0x15 0x0b */
167 u8 reserved; /* + 0x16 0x0c */
168 _MSCAN_RESERVED_(6, 5); /* + 0x17 */
169 #ifndef MSCAN_FOR_MPC5200
170 u8 canmisc; /* 0x0d */
172 u8 canrxerr; /* + 0x1c 0x0e */
173 u8 cantxerr; /* + 0x1d 0x0f */
174 _MSCAN_RESERVED_(7, 2); /* + 0x1e */
175 u16 canidar1_0; /* + 0x20 0x10 */
176 _MSCAN_RESERVED_(8, 2); /* + 0x22 */
177 u16 canidar3_2; /* + 0x24 0x12 */
178 _MSCAN_RESERVED_(9, 2); /* + 0x26 */
179 u16 canidmr1_0; /* + 0x28 0x14 */
180 _MSCAN_RESERVED_(10, 2); /* + 0x2a */
181 u16 canidmr3_2; /* + 0x2c 0x16 */
182 _MSCAN_RESERVED_(11, 2); /* + 0x2e */
183 u16 canidar5_4; /* + 0x30 0x18 */
184 _MSCAN_RESERVED_(12, 2); /* + 0x32 */
185 u16 canidar7_6; /* + 0x34 0x1a */
186 _MSCAN_RESERVED_(13, 2); /* + 0x36 */
187 u16 canidmr5_4; /* + 0x38 0x1c */
188 _MSCAN_RESERVED_(14, 2); /* + 0x3a */
189 u16 canidmr7_6; /* + 0x3c 0x1e */
190 _MSCAN_RESERVED_(15, 2); /* + 0x3e */
192 u16 idr1_0; /* + 0x40 0x20 */
193 _MSCAN_RESERVED_(16, 2); /* + 0x42 */
194 u16 idr3_2; /* + 0x44 0x22 */
195 _MSCAN_RESERVED_(17, 2); /* + 0x46 */
196 u16 dsr1_0; /* + 0x48 0x24 */
197 _MSCAN_RESERVED_(18, 2); /* + 0x4a */
198 u16 dsr3_2; /* + 0x4c 0x26 */
199 _MSCAN_RESERVED_(19, 2); /* + 0x4e */
200 u16 dsr5_4; /* + 0x50 0x28 */
201 _MSCAN_RESERVED_(20, 2); /* + 0x52 */
202 u16 dsr7_6; /* + 0x54 0x2a */
203 _MSCAN_RESERVED_(21, 2); /* + 0x56 */
204 u8 dlr; /* + 0x58 0x2c */
205 u8:8; /* + 0x59 0x2d */
206 _MSCAN_RESERVED_(22, 2); /* + 0x5a */
207 u16 time; /* + 0x5c 0x2e */
209 _MSCAN_RESERVED_(23, 2); /* + 0x5e */
211 u16 idr1_0; /* + 0x60 0x30 */
212 _MSCAN_RESERVED_(24, 2); /* + 0x62 */
213 u16 idr3_2; /* + 0x64 0x32 */
214 _MSCAN_RESERVED_(25, 2); /* + 0x66 */
215 u16 dsr1_0; /* + 0x68 0x34 */
216 _MSCAN_RESERVED_(26, 2); /* + 0x6a */
217 u16 dsr3_2; /* + 0x6c 0x36 */
218 _MSCAN_RESERVED_(27, 2); /* + 0x6e */
219 u16 dsr5_4; /* + 0x70 0x38 */
220 _MSCAN_RESERVED_(28, 2); /* + 0x72 */
221 u16 dsr7_6; /* + 0x74 0x3a */
222 _MSCAN_RESERVED_(29, 2); /* + 0x76 */
223 u8 dlr; /* + 0x78 0x3c */
224 u8 tbpr; /* + 0x79 0x3d */
225 _MSCAN_RESERVED_(30, 2); /* + 0x7a */
226 u16 time; /* + 0x7c 0x3e */
228 _MSCAN_RESERVED_(31, 2); /* + 0x7e */
229 } __attribute__ ((packed));
231 #undef _MSCAN_RESERVED_
232 #define MSCAN_REGION sizeof(struct mscan)
234 #define MSCAN_NORMAL_MODE 0
235 #define MSCAN_SLEEP_MODE MSCAN_SLPRQ
236 #define MSCAN_INIT_MODE (MSCAN_INITRQ | MSCAN_SLPRQ)
237 #define MSCAN_POWEROFF_MODE (MSCAN_CSWAI | MSCAN_SLPRQ)
238 #define MSCAN_SET_MODE_RETRIES 255
239 #define MSCAN_ECHO_SKB_MAX 3
241 #define BTR0_BRP_MASK 0x3f
242 #define BTR0_SJW_SHIFT 6
243 #define BTR0_SJW_MASK (0x3 << BTR0_SJW_SHIFT)
245 #define BTR1_TSEG1_MASK 0xf
246 #define BTR1_TSEG2_SHIFT 4
247 #define BTR1_TSEG2_MASK (0x7 << BTR1_TSEG2_SHIFT)
248 #define BTR1_SAM_SHIFT 7
250 #define BTR0_SET_BRP(brp) (((brp) - 1) & BTR0_BRP_MASK)
251 #define BTR0_SET_SJW(sjw) ((((sjw) - 1) << BTR0_SJW_SHIFT) & \
254 #define BTR1_SET_TSEG1(tseg1) (((tseg1) - 1) & BTR1_TSEG1_MASK)
255 #define BTR1_SET_TSEG2(tseg2) ((((tseg2) - 1) << BTR1_TSEG2_SHIFT) & \
257 #define BTR1_SET_SAM(sam) ((sam) ? 1 << BTR1_SAM_SHIFT : 0)
259 #define F_RX_PROGRESS 0
260 #define F_TX_PROGRESS 1
261 #define F_TX_WAIT_ALL 2
263 #define TX_QUEUE_SIZE 3
265 struct tx_queue_entry {
266 struct list_head list;
272 struct can_priv can; /* must be the first member */
275 void __iomem *reg_base; /* ioremap'ed address to registers */
282 struct list_head tx_head;
283 struct tx_queue_entry tx_queue[TX_QUEUE_SIZE];
284 struct napi_struct napi;
287 extern struct net_device *alloc_mscandev(void);
290 * 1 = The MSCAN clock source is the onchip Bus Clock.
291 * 0 = The MSCAN clock source is the chip Oscillator Clock.
293 extern int register_mscandev(struct net_device *dev, int clock_src);
294 extern void unregister_mscandev(struct net_device *dev);
296 #endif /* __MSCAN_H__ */