2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
20 #include <asm/div64.h>
22 MODULE_VERSION(DRV_VER);
23 MODULE_DEVICE_TABLE(pci, be_dev_ids);
24 MODULE_DESCRIPTION(DRV_DESC " " DRV_VER);
25 MODULE_AUTHOR("ServerEngines Corporation");
26 MODULE_LICENSE("GPL");
28 static unsigned int rx_frag_size = 2048;
29 static unsigned int num_vfs;
30 module_param(rx_frag_size, uint, S_IRUGO);
31 module_param(num_vfs, uint, S_IRUGO);
32 MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data.");
33 MODULE_PARM_DESC(num_vfs, "Number of PCI VFs to initialize");
35 static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
36 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
37 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
38 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
39 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
42 MODULE_DEVICE_TABLE(pci, be_dev_ids);
44 static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
46 struct be_dma_mem *mem = &q->dma_mem;
48 pci_free_consistent(adapter->pdev, mem->size,
52 static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q,
53 u16 len, u16 entry_size)
55 struct be_dma_mem *mem = &q->dma_mem;
57 memset(q, 0, sizeof(*q));
59 q->entry_size = entry_size;
60 mem->size = len * entry_size;
61 mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma);
64 memset(mem->va, 0, mem->size);
68 static void be_intr_set(struct be_adapter *adapter, bool enable)
70 u8 __iomem *addr = adapter->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
71 u32 reg = ioread32(addr);
72 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
77 if (!enabled && enable)
78 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
79 else if (enabled && !enable)
80 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
87 static void be_rxq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
90 val |= qid & DB_RQ_RING_ID_MASK;
91 val |= posted << DB_RQ_NUM_POSTED_SHIFT;
92 iowrite32(val, adapter->db + DB_RQ_OFFSET);
95 static void be_txq_notify(struct be_adapter *adapter, u16 qid, u16 posted)
98 val |= qid & DB_TXULP_RING_ID_MASK;
99 val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT;
100 iowrite32(val, adapter->db + DB_TXULP1_OFFSET);
103 static void be_eq_notify(struct be_adapter *adapter, u16 qid,
104 bool arm, bool clear_int, u16 num_popped)
107 val |= qid & DB_EQ_RING_ID_MASK;
109 if (adapter->eeh_err)
113 val |= 1 << DB_EQ_REARM_SHIFT;
115 val |= 1 << DB_EQ_CLR_SHIFT;
116 val |= 1 << DB_EQ_EVNT_SHIFT;
117 val |= num_popped << DB_EQ_NUM_POPPED_SHIFT;
118 iowrite32(val, adapter->db + DB_EQ_OFFSET);
121 void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped)
124 val |= qid & DB_CQ_RING_ID_MASK;
126 if (adapter->eeh_err)
130 val |= 1 << DB_CQ_REARM_SHIFT;
131 val |= num_popped << DB_CQ_NUM_POPPED_SHIFT;
132 iowrite32(val, adapter->db + DB_CQ_OFFSET);
135 static int be_mac_addr_set(struct net_device *netdev, void *p)
137 struct be_adapter *adapter = netdev_priv(netdev);
138 struct sockaddr *addr = p;
141 if (!is_valid_ether_addr(addr->sa_data))
142 return -EADDRNOTAVAIL;
144 /* MAC addr configuration will be done in hardware for VFs
145 * by their corresponding PFs. Just copy to netdev addr here
147 if (!be_physfn(adapter))
150 status = be_cmd_pmac_del(adapter, adapter->if_handle, adapter->pmac_id);
154 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
155 adapter->if_handle, &adapter->pmac_id);
158 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
163 void netdev_stats_update(struct be_adapter *adapter)
165 struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va);
166 struct be_rxf_stats *rxf_stats = &hw_stats->rxf;
167 struct be_port_rxf_stats *port_stats =
168 &rxf_stats->port[adapter->port_num];
169 struct net_device_stats *dev_stats = &adapter->netdev->stats;
170 struct be_erx_stats *erx_stats = &hw_stats->erx;
172 dev_stats->rx_packets = drvr_stats(adapter)->be_rx_pkts;
173 dev_stats->tx_packets = drvr_stats(adapter)->be_tx_pkts;
174 dev_stats->rx_bytes = drvr_stats(adapter)->be_rx_bytes;
175 dev_stats->tx_bytes = drvr_stats(adapter)->be_tx_bytes;
177 /* bad pkts received */
178 dev_stats->rx_errors = port_stats->rx_crc_errors +
179 port_stats->rx_alignment_symbol_errors +
180 port_stats->rx_in_range_errors +
181 port_stats->rx_out_range_errors +
182 port_stats->rx_frame_too_long +
183 port_stats->rx_dropped_too_small +
184 port_stats->rx_dropped_too_short +
185 port_stats->rx_dropped_header_too_small +
186 port_stats->rx_dropped_tcp_length +
187 port_stats->rx_dropped_runt +
188 port_stats->rx_tcp_checksum_errs +
189 port_stats->rx_ip_checksum_errs +
190 port_stats->rx_udp_checksum_errs;
192 /* no space in linux buffers: best possible approximation */
193 dev_stats->rx_dropped =
194 erx_stats->rx_drops_no_fragments[adapter->rx_obj.q.id];
196 /* detailed rx errors */
197 dev_stats->rx_length_errors = port_stats->rx_in_range_errors +
198 port_stats->rx_out_range_errors +
199 port_stats->rx_frame_too_long;
201 /* receive ring buffer overflow */
202 dev_stats->rx_over_errors = 0;
204 dev_stats->rx_crc_errors = port_stats->rx_crc_errors;
206 /* frame alignment errors */
207 dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors;
209 /* receiver fifo overrun */
210 /* drops_no_pbuf is no per i/f, it's per BE card */
211 dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow +
212 port_stats->rx_input_fifo_overflow +
213 rxf_stats->rx_drops_no_pbuf;
214 /* receiver missed packetd */
215 dev_stats->rx_missed_errors = 0;
217 /* packet transmit problems */
218 dev_stats->tx_errors = 0;
220 /* no space available in linux */
221 dev_stats->tx_dropped = 0;
223 dev_stats->multicast = port_stats->rx_multicast_frames;
224 dev_stats->collisions = 0;
226 /* detailed tx_errors */
227 dev_stats->tx_aborted_errors = 0;
228 dev_stats->tx_carrier_errors = 0;
229 dev_stats->tx_fifo_errors = 0;
230 dev_stats->tx_heartbeat_errors = 0;
231 dev_stats->tx_window_errors = 0;
234 void be_link_status_update(struct be_adapter *adapter, bool link_up)
236 struct net_device *netdev = adapter->netdev;
238 /* If link came up or went down */
239 if (adapter->link_up != link_up) {
240 adapter->link_speed = -1;
242 netif_start_queue(netdev);
243 netif_carrier_on(netdev);
244 printk(KERN_INFO "%s: Link up\n", netdev->name);
246 netif_stop_queue(netdev);
247 netif_carrier_off(netdev);
248 printk(KERN_INFO "%s: Link down\n", netdev->name);
250 adapter->link_up = link_up;
254 /* Update the EQ delay n BE based on the RX frags consumed / sec */
255 static void be_rx_eqd_update(struct be_adapter *adapter)
257 struct be_eq_obj *rx_eq = &adapter->rx_eq;
258 struct be_drvr_stats *stats = &adapter->stats.drvr_stats;
262 if (!rx_eq->enable_aic)
266 if (time_before(now, stats->rx_fps_jiffies)) {
267 stats->rx_fps_jiffies = now;
271 /* Update once a second */
272 if ((now - stats->rx_fps_jiffies) < HZ)
275 stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) /
276 ((now - stats->rx_fps_jiffies) / HZ);
278 stats->rx_fps_jiffies = now;
279 stats->be_prev_rx_frags = stats->be_rx_frags;
280 eqd = stats->be_rx_fps / 110000;
282 if (eqd > rx_eq->max_eqd)
283 eqd = rx_eq->max_eqd;
284 if (eqd < rx_eq->min_eqd)
285 eqd = rx_eq->min_eqd;
288 if (eqd != rx_eq->cur_eqd)
289 be_cmd_modify_eqd(adapter, rx_eq->q.id, eqd);
291 rx_eq->cur_eqd = eqd;
294 static struct net_device_stats *be_get_stats(struct net_device *dev)
299 static u32 be_calc_rate(u64 bytes, unsigned long ticks)
303 do_div(rate, ticks / HZ);
304 rate <<= 3; /* bytes/sec -> bits/sec */
305 do_div(rate, 1000000ul); /* MB/Sec */
310 static void be_tx_rate_update(struct be_adapter *adapter)
312 struct be_drvr_stats *stats = drvr_stats(adapter);
315 /* Wrapped around? */
316 if (time_before(now, stats->be_tx_jiffies)) {
317 stats->be_tx_jiffies = now;
321 /* Update tx rate once in two seconds */
322 if ((now - stats->be_tx_jiffies) > 2 * HZ) {
323 stats->be_tx_rate = be_calc_rate(stats->be_tx_bytes
324 - stats->be_tx_bytes_prev,
325 now - stats->be_tx_jiffies);
326 stats->be_tx_jiffies = now;
327 stats->be_tx_bytes_prev = stats->be_tx_bytes;
331 static void be_tx_stats_update(struct be_adapter *adapter,
332 u32 wrb_cnt, u32 copied, u32 gso_segs, bool stopped)
334 struct be_drvr_stats *stats = drvr_stats(adapter);
336 stats->be_tx_wrbs += wrb_cnt;
337 stats->be_tx_bytes += copied;
338 stats->be_tx_pkts += (gso_segs ? gso_segs : 1);
340 stats->be_tx_stops++;
343 /* Determine number of WRB entries needed to xmit data in an skb */
344 static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy)
346 int cnt = (skb->len > skb->data_len);
348 cnt += skb_shinfo(skb)->nr_frags;
350 /* to account for hdr wrb */
353 /* add a dummy to make it an even num */
358 BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT);
362 static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len)
364 wrb->frag_pa_hi = upper_32_bits(addr);
365 wrb->frag_pa_lo = addr & 0xFFFFFFFF;
366 wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK;
369 static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb,
370 bool vlan, u32 wrb_cnt, u32 len)
372 memset(hdr, 0, sizeof(*hdr));
374 AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
376 if (skb_is_gso(skb)) {
377 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
378 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
379 hdr, skb_shinfo(skb)->gso_size);
380 if (skb_is_gso_v6(skb))
381 AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
382 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
384 AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
385 else if (is_udp_pkt(skb))
386 AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
389 if (vlan && vlan_tx_tag_present(skb)) {
390 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
391 AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag,
392 hdr, vlan_tx_tag_get(skb));
395 AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
396 AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1);
397 AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
398 AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
401 static void unmap_tx_frag(struct pci_dev *pdev, struct be_eth_wrb *wrb,
406 be_dws_le_to_cpu(wrb, sizeof(*wrb));
408 dma = (u64)wrb->frag_pa_hi << 32 | (u64)wrb->frag_pa_lo;
411 pci_unmap_single(pdev, dma, wrb->frag_len,
414 pci_unmap_page(pdev, dma, wrb->frag_len,
419 static int make_tx_wrbs(struct be_adapter *adapter,
420 struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb)
424 struct pci_dev *pdev = adapter->pdev;
425 struct sk_buff *first_skb = skb;
426 struct be_queue_info *txq = &adapter->tx_obj.q;
427 struct be_eth_wrb *wrb;
428 struct be_eth_hdr_wrb *hdr;
429 bool map_single = false;
432 hdr = queue_head_node(txq);
434 map_head = txq->head;
436 if (skb->len > skb->data_len) {
437 int len = skb_headlen(skb);
438 busaddr = pci_map_single(pdev, skb->data, len,
440 if (pci_dma_mapping_error(pdev, busaddr))
443 wrb = queue_head_node(txq);
444 wrb_fill(wrb, busaddr, len);
445 be_dws_cpu_to_le(wrb, sizeof(*wrb));
450 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
451 struct skb_frag_struct *frag =
452 &skb_shinfo(skb)->frags[i];
453 busaddr = pci_map_page(pdev, frag->page,
455 frag->size, PCI_DMA_TODEVICE);
456 if (pci_dma_mapping_error(pdev, busaddr))
458 wrb = queue_head_node(txq);
459 wrb_fill(wrb, busaddr, frag->size);
460 be_dws_cpu_to_le(wrb, sizeof(*wrb));
462 copied += frag->size;
466 wrb = queue_head_node(txq);
468 be_dws_cpu_to_le(wrb, sizeof(*wrb));
472 wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false,
474 be_dws_cpu_to_le(hdr, sizeof(*hdr));
478 txq->head = map_head;
480 wrb = queue_head_node(txq);
481 unmap_tx_frag(pdev, wrb, map_single);
483 copied -= wrb->frag_len;
489 static netdev_tx_t be_xmit(struct sk_buff *skb,
490 struct net_device *netdev)
492 struct be_adapter *adapter = netdev_priv(netdev);
493 struct be_tx_obj *tx_obj = &adapter->tx_obj;
494 struct be_queue_info *txq = &tx_obj->q;
495 u32 wrb_cnt = 0, copied = 0;
496 u32 start = txq->head;
497 bool dummy_wrb, stopped = false;
499 wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb);
501 copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb);
503 /* record the sent skb in the sent_skb table */
504 BUG_ON(tx_obj->sent_skb_list[start]);
505 tx_obj->sent_skb_list[start] = skb;
507 /* Ensure txq has space for the next skb; Else stop the queue
508 * *BEFORE* ringing the tx doorbell, so that we serialze the
509 * tx compls of the current transmit which'll wake up the queue
511 atomic_add(wrb_cnt, &txq->used);
512 if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >=
514 netif_stop_queue(netdev);
518 be_txq_notify(adapter, txq->id, wrb_cnt);
520 be_tx_stats_update(adapter, wrb_cnt, copied,
521 skb_shinfo(skb)->gso_segs, stopped);
524 dev_kfree_skb_any(skb);
529 static int be_change_mtu(struct net_device *netdev, int new_mtu)
531 struct be_adapter *adapter = netdev_priv(netdev);
532 if (new_mtu < BE_MIN_MTU ||
533 new_mtu > (BE_MAX_JUMBO_FRAME_SIZE -
534 (ETH_HLEN + ETH_FCS_LEN))) {
535 dev_info(&adapter->pdev->dev,
536 "MTU must be between %d and %d bytes\n",
538 (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
541 dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
542 netdev->mtu, new_mtu);
543 netdev->mtu = new_mtu;
548 * A max of 64 (BE_NUM_VLANS_SUPPORTED) vlans can be configured in BE.
549 * If the user configures more, place BE in vlan promiscuous mode.
551 static int be_vid_config(struct be_adapter *adapter)
553 u16 vtag[BE_NUM_VLANS_SUPPORTED];
557 if (adapter->vlans_added <= adapter->max_vlans) {
558 /* Construct VLAN Table to give to HW */
559 for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) {
560 if (adapter->vlan_tag[i]) {
561 vtag[ntags] = cpu_to_le16(i);
565 status = be_cmd_vlan_config(adapter, adapter->if_handle,
568 status = be_cmd_vlan_config(adapter, adapter->if_handle,
574 static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp)
576 struct be_adapter *adapter = netdev_priv(netdev);
577 struct be_eq_obj *rx_eq = &adapter->rx_eq;
578 struct be_eq_obj *tx_eq = &adapter->tx_eq;
580 be_eq_notify(adapter, rx_eq->q.id, false, false, 0);
581 be_eq_notify(adapter, tx_eq->q.id, false, false, 0);
582 adapter->vlan_grp = grp;
583 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
584 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
587 static void be_vlan_add_vid(struct net_device *netdev, u16 vid)
589 struct be_adapter *adapter = netdev_priv(netdev);
591 if (!be_physfn(adapter))
594 adapter->vlan_tag[vid] = 1;
595 adapter->vlans_added++;
596 if (adapter->vlans_added <= (adapter->max_vlans + 1))
597 be_vid_config(adapter);
600 static void be_vlan_rem_vid(struct net_device *netdev, u16 vid)
602 struct be_adapter *adapter = netdev_priv(netdev);
604 if (!be_physfn(adapter))
607 adapter->vlan_tag[vid] = 0;
608 vlan_group_set_device(adapter->vlan_grp, vid, NULL);
609 adapter->vlans_added--;
610 if (adapter->vlans_added <= adapter->max_vlans)
611 be_vid_config(adapter);
614 static void be_set_multicast_list(struct net_device *netdev)
616 struct be_adapter *adapter = netdev_priv(netdev);
618 if (netdev->flags & IFF_PROMISC) {
619 be_cmd_promiscuous_config(adapter, adapter->port_num, 1);
620 adapter->promiscuous = true;
624 /* BE was previously in promiscous mode; disable it */
625 if (adapter->promiscuous) {
626 adapter->promiscuous = false;
627 be_cmd_promiscuous_config(adapter, adapter->port_num, 0);
630 /* Enable multicast promisc if num configured exceeds what we support */
631 if (netdev->flags & IFF_ALLMULTI ||
632 netdev_mc_count(netdev) > BE_MAX_MC) {
633 be_cmd_multicast_set(adapter, adapter->if_handle, NULL,
634 &adapter->mc_cmd_mem);
638 be_cmd_multicast_set(adapter, adapter->if_handle, netdev,
639 &adapter->mc_cmd_mem);
644 static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
646 struct be_adapter *adapter = netdev_priv(netdev);
649 if (!adapter->sriov_enabled)
652 if (!is_valid_ether_addr(mac) || (vf >= num_vfs))
655 status = be_cmd_pmac_del(adapter, adapter->vf_if_handle[vf],
656 adapter->vf_pmac_id[vf]);
658 status = be_cmd_pmac_add(adapter, mac, adapter->vf_if_handle[vf],
659 &adapter->vf_pmac_id[vf]);
661 dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n",
666 static void be_rx_rate_update(struct be_adapter *adapter)
668 struct be_drvr_stats *stats = drvr_stats(adapter);
672 if (time_before(now, stats->be_rx_jiffies)) {
673 stats->be_rx_jiffies = now;
677 /* Update the rate once in two seconds */
678 if ((now - stats->be_rx_jiffies) < 2 * HZ)
681 stats->be_rx_rate = be_calc_rate(stats->be_rx_bytes
682 - stats->be_rx_bytes_prev,
683 now - stats->be_rx_jiffies);
684 stats->be_rx_jiffies = now;
685 stats->be_rx_bytes_prev = stats->be_rx_bytes;
688 static void be_rx_stats_update(struct be_adapter *adapter,
689 u32 pktsize, u16 numfrags)
691 struct be_drvr_stats *stats = drvr_stats(adapter);
693 stats->be_rx_compl++;
694 stats->be_rx_frags += numfrags;
695 stats->be_rx_bytes += pktsize;
699 static inline bool do_pkt_csum(struct be_eth_rx_compl *rxcp, bool cso)
701 u8 l4_cksm, ip_version, ipcksm, tcpf = 0, udpf = 0, ipv6_chk;
703 l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp);
704 ipcksm = AMAP_GET_BITS(struct amap_eth_rx_compl, ipcksm, rxcp);
705 ip_version = AMAP_GET_BITS(struct amap_eth_rx_compl, ip_version, rxcp);
707 tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
708 udpf = AMAP_GET_BITS(struct amap_eth_rx_compl, udpf, rxcp);
710 ipv6_chk = (ip_version && (tcpf || udpf));
712 return ((l4_cksm && ipv6_chk && ipcksm) && cso) ? false : true;
715 static struct be_rx_page_info *
716 get_rx_page_info(struct be_adapter *adapter, u16 frag_idx)
718 struct be_rx_page_info *rx_page_info;
719 struct be_queue_info *rxq = &adapter->rx_obj.q;
721 rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx];
722 BUG_ON(!rx_page_info->page);
724 if (rx_page_info->last_page_user) {
725 pci_unmap_page(adapter->pdev, dma_unmap_addr(rx_page_info, bus),
726 adapter->big_page_size, PCI_DMA_FROMDEVICE);
727 rx_page_info->last_page_user = false;
730 atomic_dec(&rxq->used);
734 /* Throwaway the data in the Rx completion */
735 static void be_rx_compl_discard(struct be_adapter *adapter,
736 struct be_eth_rx_compl *rxcp)
738 struct be_queue_info *rxq = &adapter->rx_obj.q;
739 struct be_rx_page_info *page_info;
740 u16 rxq_idx, i, num_rcvd;
742 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
743 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
745 for (i = 0; i < num_rcvd; i++) {
746 page_info = get_rx_page_info(adapter, rxq_idx);
747 put_page(page_info->page);
748 memset(page_info, 0, sizeof(*page_info));
749 index_inc(&rxq_idx, rxq->len);
754 * skb_fill_rx_data forms a complete skb for an ether frame
757 static void skb_fill_rx_data(struct be_adapter *adapter,
758 struct sk_buff *skb, struct be_eth_rx_compl *rxcp,
761 struct be_queue_info *rxq = &adapter->rx_obj.q;
762 struct be_rx_page_info *page_info;
764 u32 pktsize, hdr_len, curr_frag_len, size;
767 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
768 pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
770 page_info = get_rx_page_info(adapter, rxq_idx);
772 start = page_address(page_info->page) + page_info->page_offset;
775 /* Copy data in the first descriptor of this completion */
776 curr_frag_len = min(pktsize, rx_frag_size);
778 /* Copy the header portion into skb_data */
779 hdr_len = min((u32)BE_HDR_LEN, curr_frag_len);
780 memcpy(skb->data, start, hdr_len);
781 skb->len = curr_frag_len;
782 if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */
783 /* Complete packet has now been moved to data */
784 put_page(page_info->page);
786 skb->tail += curr_frag_len;
788 skb_shinfo(skb)->nr_frags = 1;
789 skb_shinfo(skb)->frags[0].page = page_info->page;
790 skb_shinfo(skb)->frags[0].page_offset =
791 page_info->page_offset + hdr_len;
792 skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len;
793 skb->data_len = curr_frag_len - hdr_len;
794 skb->tail += hdr_len;
796 page_info->page = NULL;
798 if (pktsize <= rx_frag_size) {
799 BUG_ON(num_rcvd != 1);
803 /* More frags present for this completion */
805 for (i = 1, j = 0; i < num_rcvd; i++) {
806 size -= curr_frag_len;
807 index_inc(&rxq_idx, rxq->len);
808 page_info = get_rx_page_info(adapter, rxq_idx);
810 curr_frag_len = min(size, rx_frag_size);
812 /* Coalesce all frags from the same physical page in one slot */
813 if (page_info->page_offset == 0) {
816 skb_shinfo(skb)->frags[j].page = page_info->page;
817 skb_shinfo(skb)->frags[j].page_offset =
818 page_info->page_offset;
819 skb_shinfo(skb)->frags[j].size = 0;
820 skb_shinfo(skb)->nr_frags++;
822 put_page(page_info->page);
825 skb_shinfo(skb)->frags[j].size += curr_frag_len;
826 skb->len += curr_frag_len;
827 skb->data_len += curr_frag_len;
829 page_info->page = NULL;
831 BUG_ON(j > MAX_SKB_FRAGS);
834 be_rx_stats_update(adapter, pktsize, num_rcvd);
837 /* Process the RX completion indicated by rxcp when GRO is disabled */
838 static void be_rx_compl_process(struct be_adapter *adapter,
839 struct be_eth_rx_compl *rxcp)
846 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
847 /* Is it a flush compl that has no data */
848 if (unlikely(num_rcvd == 0))
851 skb = netdev_alloc_skb_ip_align(adapter->netdev, BE_HDR_LEN);
852 if (unlikely(!skb)) {
854 dev_warn(&adapter->pdev->dev, "skb alloc failed\n");
855 be_rx_compl_discard(adapter, rxcp);
859 skb_fill_rx_data(adapter, skb, rxcp, num_rcvd);
861 if (do_pkt_csum(rxcp, adapter->rx_csum))
862 skb->ip_summed = CHECKSUM_NONE;
864 skb->ip_summed = CHECKSUM_UNNECESSARY;
866 skb->truesize = skb->len + sizeof(struct sk_buff);
867 skb->protocol = eth_type_trans(skb, adapter->netdev);
869 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
870 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
872 /* vlanf could be wrongly set in some cards.
873 * ignore if vtm is not set */
874 if ((adapter->cap & 0x400) && !vtm)
877 if (unlikely(vlanf)) {
878 if (!adapter->vlan_grp || adapter->vlans_added == 0) {
882 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
884 vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid);
886 netif_receive_skb(skb);
890 /* Process the RX completion indicated by rxcp when GRO is enabled */
891 static void be_rx_compl_process_gro(struct be_adapter *adapter,
892 struct be_eth_rx_compl *rxcp)
894 struct be_rx_page_info *page_info;
895 struct sk_buff *skb = NULL;
896 struct be_queue_info *rxq = &adapter->rx_obj.q;
897 struct be_eq_obj *eq_obj = &adapter->rx_eq;
898 u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len;
899 u16 i, rxq_idx = 0, vid, j;
902 num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp);
903 /* Is it a flush compl that has no data */
904 if (unlikely(num_rcvd == 0))
907 pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp);
908 vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp);
909 rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp);
910 vtm = AMAP_GET_BITS(struct amap_eth_rx_compl, vtm, rxcp);
912 /* vlanf could be wrongly set in some cards.
913 * ignore if vtm is not set */
914 if ((adapter->cap & 0x400) && !vtm)
917 skb = napi_get_frags(&eq_obj->napi);
919 be_rx_compl_discard(adapter, rxcp);
923 remaining = pkt_size;
924 for (i = 0, j = -1; i < num_rcvd; i++) {
925 page_info = get_rx_page_info(adapter, rxq_idx);
927 curr_frag_len = min(remaining, rx_frag_size);
929 /* Coalesce all frags from the same physical page in one slot */
930 if (i == 0 || page_info->page_offset == 0) {
931 /* First frag or Fresh page */
933 skb_shinfo(skb)->frags[j].page = page_info->page;
934 skb_shinfo(skb)->frags[j].page_offset =
935 page_info->page_offset;
936 skb_shinfo(skb)->frags[j].size = 0;
938 put_page(page_info->page);
940 skb_shinfo(skb)->frags[j].size += curr_frag_len;
942 remaining -= curr_frag_len;
943 index_inc(&rxq_idx, rxq->len);
944 memset(page_info, 0, sizeof(*page_info));
946 BUG_ON(j > MAX_SKB_FRAGS);
948 skb_shinfo(skb)->nr_frags = j + 1;
950 skb->data_len = pkt_size;
951 skb->truesize += pkt_size;
952 skb->ip_summed = CHECKSUM_UNNECESSARY;
954 if (likely(!vlanf)) {
955 napi_gro_frags(&eq_obj->napi);
957 vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp);
960 if (!adapter->vlan_grp || adapter->vlans_added == 0)
963 vlan_gro_frags(&eq_obj->napi, adapter->vlan_grp, vid);
966 be_rx_stats_update(adapter, pkt_size, num_rcvd);
969 static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter)
971 struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq);
973 if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0)
976 be_dws_le_to_cpu(rxcp, sizeof(*rxcp));
978 queue_tail_inc(&adapter->rx_obj.cq);
982 /* To reset the valid bit, we need to reset the whole word as
983 * when walking the queue the valid entries are little-endian
984 * and invalid entries are host endian
986 static inline void be_rx_compl_reset(struct be_eth_rx_compl *rxcp)
988 rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0;
991 static inline struct page *be_alloc_pages(u32 size)
993 gfp_t alloc_flags = GFP_ATOMIC;
994 u32 order = get_order(size);
996 alloc_flags |= __GFP_COMP;
997 return alloc_pages(alloc_flags, order);
1001 * Allocate a page, split it to fragments of size rx_frag_size and post as
1002 * receive buffers to BE
1004 static void be_post_rx_frags(struct be_adapter *adapter)
1006 struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl;
1007 struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL;
1008 struct be_queue_info *rxq = &adapter->rx_obj.q;
1009 struct page *pagep = NULL;
1010 struct be_eth_rx_d *rxd;
1011 u64 page_dmaaddr = 0, frag_dmaaddr;
1012 u32 posted, page_offset = 0;
1014 page_info = &page_info_tbl[rxq->head];
1015 for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) {
1017 pagep = be_alloc_pages(adapter->big_page_size);
1018 if (unlikely(!pagep)) {
1019 drvr_stats(adapter)->be_ethrx_post_fail++;
1022 page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0,
1023 adapter->big_page_size,
1024 PCI_DMA_FROMDEVICE);
1025 page_info->page_offset = 0;
1028 page_info->page_offset = page_offset + rx_frag_size;
1030 page_offset = page_info->page_offset;
1031 page_info->page = pagep;
1032 dma_unmap_addr_set(page_info, bus, page_dmaaddr);
1033 frag_dmaaddr = page_dmaaddr + page_info->page_offset;
1035 rxd = queue_head_node(rxq);
1036 rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF);
1037 rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr));
1039 /* Any space left in the current big page for another frag? */
1040 if ((page_offset + rx_frag_size + rx_frag_size) >
1041 adapter->big_page_size) {
1043 page_info->last_page_user = true;
1046 prev_page_info = page_info;
1047 queue_head_inc(rxq);
1048 page_info = &page_info_tbl[rxq->head];
1051 prev_page_info->last_page_user = true;
1054 atomic_add(posted, &rxq->used);
1055 be_rxq_notify(adapter, rxq->id, posted);
1056 } else if (atomic_read(&rxq->used) == 0) {
1057 /* Let be_worker replenish when memory is available */
1058 adapter->rx_post_starved = true;
1062 static struct be_eth_tx_compl *be_tx_compl_get(struct be_queue_info *tx_cq)
1064 struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq);
1066 if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0)
1069 be_dws_le_to_cpu(txcp, sizeof(*txcp));
1071 txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0;
1073 queue_tail_inc(tx_cq);
1077 static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index)
1079 struct be_queue_info *txq = &adapter->tx_obj.q;
1080 struct be_eth_wrb *wrb;
1081 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1082 struct sk_buff *sent_skb;
1083 u16 cur_index, num_wrbs = 1; /* account for hdr wrb */
1084 bool unmap_skb_hdr = true;
1086 sent_skb = sent_skbs[txq->tail];
1088 sent_skbs[txq->tail] = NULL;
1090 /* skip header wrb */
1091 queue_tail_inc(txq);
1094 cur_index = txq->tail;
1095 wrb = queue_tail_node(txq);
1096 unmap_tx_frag(adapter->pdev, wrb, (unmap_skb_hdr &&
1097 skb_headlen(sent_skb)));
1098 unmap_skb_hdr = false;
1101 queue_tail_inc(txq);
1102 } while (cur_index != last_index);
1104 atomic_sub(num_wrbs, &txq->used);
1106 kfree_skb(sent_skb);
1109 static inline struct be_eq_entry *event_get(struct be_eq_obj *eq_obj)
1111 struct be_eq_entry *eqe = queue_tail_node(&eq_obj->q);
1116 eqe->evt = le32_to_cpu(eqe->evt);
1117 queue_tail_inc(&eq_obj->q);
1121 static int event_handle(struct be_adapter *adapter,
1122 struct be_eq_obj *eq_obj)
1124 struct be_eq_entry *eqe;
1127 while ((eqe = event_get(eq_obj)) != NULL) {
1132 /* Deal with any spurious interrupts that come
1135 be_eq_notify(adapter, eq_obj->q.id, true, true, num);
1137 napi_schedule(&eq_obj->napi);
1142 /* Just read and notify events without processing them.
1143 * Used at the time of destroying event queues */
1144 static void be_eq_clean(struct be_adapter *adapter,
1145 struct be_eq_obj *eq_obj)
1147 struct be_eq_entry *eqe;
1150 while ((eqe = event_get(eq_obj)) != NULL) {
1156 be_eq_notify(adapter, eq_obj->q.id, false, true, num);
1159 static void be_rx_q_clean(struct be_adapter *adapter)
1161 struct be_rx_page_info *page_info;
1162 struct be_queue_info *rxq = &adapter->rx_obj.q;
1163 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1164 struct be_eth_rx_compl *rxcp;
1167 /* First cleanup pending rx completions */
1168 while ((rxcp = be_rx_compl_get(adapter)) != NULL) {
1169 be_rx_compl_discard(adapter, rxcp);
1170 be_rx_compl_reset(rxcp);
1171 be_cq_notify(adapter, rx_cq->id, true, 1);
1174 /* Then free posted rx buffer that were not used */
1175 tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len;
1176 for (; atomic_read(&rxq->used) > 0; index_inc(&tail, rxq->len)) {
1177 page_info = get_rx_page_info(adapter, tail);
1178 put_page(page_info->page);
1179 memset(page_info, 0, sizeof(*page_info));
1181 BUG_ON(atomic_read(&rxq->used));
1184 static void be_tx_compl_clean(struct be_adapter *adapter)
1186 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
1187 struct be_queue_info *txq = &adapter->tx_obj.q;
1188 struct be_eth_tx_compl *txcp;
1189 u16 end_idx, cmpl = 0, timeo = 0;
1190 struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list;
1191 struct sk_buff *sent_skb;
1194 /* Wait for a max of 200ms for all the tx-completions to arrive. */
1196 while ((txcp = be_tx_compl_get(tx_cq))) {
1197 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1199 be_tx_compl_process(adapter, end_idx);
1203 be_cq_notify(adapter, tx_cq->id, false, cmpl);
1207 if (atomic_read(&txq->used) == 0 || ++timeo > 200)
1213 if (atomic_read(&txq->used))
1214 dev_err(&adapter->pdev->dev, "%d pending tx-completions\n",
1215 atomic_read(&txq->used));
1217 /* free posted tx for which compls will never arrive */
1218 while (atomic_read(&txq->used)) {
1219 sent_skb = sent_skbs[txq->tail];
1220 end_idx = txq->tail;
1222 wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len);
1223 be_tx_compl_process(adapter, end_idx);
1227 static void be_mcc_queues_destroy(struct be_adapter *adapter)
1229 struct be_queue_info *q;
1231 q = &adapter->mcc_obj.q;
1233 be_cmd_q_destroy(adapter, q, QTYPE_MCCQ);
1234 be_queue_free(adapter, q);
1236 q = &adapter->mcc_obj.cq;
1238 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1239 be_queue_free(adapter, q);
1242 /* Must be called only after TX qs are created as MCC shares TX EQ */
1243 static int be_mcc_queues_create(struct be_adapter *adapter)
1245 struct be_queue_info *q, *cq;
1247 /* Alloc MCC compl queue */
1248 cq = &adapter->mcc_obj.cq;
1249 if (be_queue_alloc(adapter, cq, MCC_CQ_LEN,
1250 sizeof(struct be_mcc_compl)))
1253 /* Ask BE to create MCC compl queue; share TX's eq */
1254 if (be_cmd_cq_create(adapter, cq, &adapter->tx_eq.q, false, true, 0))
1257 /* Alloc MCC queue */
1258 q = &adapter->mcc_obj.q;
1259 if (be_queue_alloc(adapter, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
1260 goto mcc_cq_destroy;
1262 /* Ask BE to create MCC queue */
1263 if (be_cmd_mccq_create(adapter, q, cq))
1269 be_queue_free(adapter, q);
1271 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
1273 be_queue_free(adapter, cq);
1278 static void be_tx_queues_destroy(struct be_adapter *adapter)
1280 struct be_queue_info *q;
1282 q = &adapter->tx_obj.q;
1284 be_cmd_q_destroy(adapter, q, QTYPE_TXQ);
1285 be_queue_free(adapter, q);
1287 q = &adapter->tx_obj.cq;
1289 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1290 be_queue_free(adapter, q);
1292 /* Clear any residual events */
1293 be_eq_clean(adapter, &adapter->tx_eq);
1295 q = &adapter->tx_eq.q;
1297 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1298 be_queue_free(adapter, q);
1301 static int be_tx_queues_create(struct be_adapter *adapter)
1303 struct be_queue_info *eq, *q, *cq;
1305 adapter->tx_eq.max_eqd = 0;
1306 adapter->tx_eq.min_eqd = 0;
1307 adapter->tx_eq.cur_eqd = 96;
1308 adapter->tx_eq.enable_aic = false;
1309 /* Alloc Tx Event queue */
1310 eq = &adapter->tx_eq.q;
1311 if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry)))
1314 /* Ask BE to create Tx Event queue */
1315 if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd))
1317 adapter->base_eq_id = adapter->tx_eq.q.id;
1319 /* Alloc TX eth compl queue */
1320 cq = &adapter->tx_obj.cq;
1321 if (be_queue_alloc(adapter, cq, TX_CQ_LEN,
1322 sizeof(struct be_eth_tx_compl)))
1325 /* Ask BE to create Tx eth compl queue */
1326 if (be_cmd_cq_create(adapter, cq, eq, false, false, 3))
1329 /* Alloc TX eth queue */
1330 q = &adapter->tx_obj.q;
1331 if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb)))
1334 /* Ask BE to create Tx eth queue */
1335 if (be_cmd_txq_create(adapter, q, cq))
1340 be_queue_free(adapter, q);
1342 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
1344 be_queue_free(adapter, cq);
1346 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
1348 be_queue_free(adapter, eq);
1352 static void be_rx_queues_destroy(struct be_adapter *adapter)
1354 struct be_queue_info *q;
1356 q = &adapter->rx_obj.q;
1358 be_cmd_q_destroy(adapter, q, QTYPE_RXQ);
1360 /* After the rxq is invalidated, wait for a grace time
1361 * of 1ms for all dma to end and the flush compl to arrive
1364 be_rx_q_clean(adapter);
1366 be_queue_free(adapter, q);
1368 q = &adapter->rx_obj.cq;
1370 be_cmd_q_destroy(adapter, q, QTYPE_CQ);
1371 be_queue_free(adapter, q);
1373 /* Clear any residual events */
1374 be_eq_clean(adapter, &adapter->rx_eq);
1376 q = &adapter->rx_eq.q;
1378 be_cmd_q_destroy(adapter, q, QTYPE_EQ);
1379 be_queue_free(adapter, q);
1382 static int be_rx_queues_create(struct be_adapter *adapter)
1384 struct be_queue_info *eq, *q, *cq;
1387 adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE;
1388 adapter->rx_eq.max_eqd = BE_MAX_EQD;
1389 adapter->rx_eq.min_eqd = 0;
1390 adapter->rx_eq.cur_eqd = 0;
1391 adapter->rx_eq.enable_aic = true;
1393 /* Alloc Rx Event queue */
1394 eq = &adapter->rx_eq.q;
1395 rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN,
1396 sizeof(struct be_eq_entry));
1400 /* Ask BE to create Rx Event queue */
1401 rc = be_cmd_eq_create(adapter, eq, adapter->rx_eq.cur_eqd);
1405 /* Alloc RX eth compl queue */
1406 cq = &adapter->rx_obj.cq;
1407 rc = be_queue_alloc(adapter, cq, RX_CQ_LEN,
1408 sizeof(struct be_eth_rx_compl));
1412 /* Ask BE to create Rx eth compl queue */
1413 rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3);
1417 /* Alloc RX eth queue */
1418 q = &adapter->rx_obj.q;
1419 rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d));
1423 /* Ask BE to create Rx eth queue */
1424 rc = be_cmd_rxq_create(adapter, q, cq->id, rx_frag_size,
1425 BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false);
1431 be_queue_free(adapter, q);
1433 be_cmd_q_destroy(adapter, cq, QTYPE_CQ);
1435 be_queue_free(adapter, cq);
1437 be_cmd_q_destroy(adapter, eq, QTYPE_EQ);
1439 be_queue_free(adapter, eq);
1443 /* There are 8 evt ids per func. Retruns the evt id's bit number */
1444 static inline int be_evt_bit_get(struct be_adapter *adapter, u32 eq_id)
1446 return eq_id - adapter->base_eq_id;
1449 static irqreturn_t be_intx(int irq, void *dev)
1451 struct be_adapter *adapter = dev;
1454 isr = ioread32(adapter->csr + CEV_ISR0_OFFSET +
1455 (adapter->tx_eq.q.id/ 8) * CEV_ISR_SIZE);
1459 event_handle(adapter, &adapter->tx_eq);
1460 event_handle(adapter, &adapter->rx_eq);
1465 static irqreturn_t be_msix_rx(int irq, void *dev)
1467 struct be_adapter *adapter = dev;
1469 event_handle(adapter, &adapter->rx_eq);
1474 static irqreturn_t be_msix_tx_mcc(int irq, void *dev)
1476 struct be_adapter *adapter = dev;
1478 event_handle(adapter, &adapter->tx_eq);
1483 static inline bool do_gro(struct be_adapter *adapter,
1484 struct be_eth_rx_compl *rxcp)
1486 int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp);
1487 int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp);
1490 drvr_stats(adapter)->be_rxcp_err++;
1492 return (tcp_frame && !err) ? true : false;
1495 int be_poll_rx(struct napi_struct *napi, int budget)
1497 struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi);
1498 struct be_adapter *adapter =
1499 container_of(rx_eq, struct be_adapter, rx_eq);
1500 struct be_queue_info *rx_cq = &adapter->rx_obj.cq;
1501 struct be_eth_rx_compl *rxcp;
1504 adapter->stats.drvr_stats.be_rx_polls++;
1505 for (work_done = 0; work_done < budget; work_done++) {
1506 rxcp = be_rx_compl_get(adapter);
1510 if (do_gro(adapter, rxcp))
1511 be_rx_compl_process_gro(adapter, rxcp);
1513 be_rx_compl_process(adapter, rxcp);
1515 be_rx_compl_reset(rxcp);
1518 /* Refill the queue */
1519 if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM)
1520 be_post_rx_frags(adapter);
1523 if (work_done < budget) {
1524 napi_complete(napi);
1525 be_cq_notify(adapter, rx_cq->id, true, work_done);
1527 /* More to be consumed; continue with interrupts disabled */
1528 be_cq_notify(adapter, rx_cq->id, false, work_done);
1533 /* As TX and MCC share the same EQ check for both TX and MCC completions.
1534 * For TX/MCC we don't honour budget; consume everything
1536 static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
1538 struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi);
1539 struct be_adapter *adapter =
1540 container_of(tx_eq, struct be_adapter, tx_eq);
1541 struct be_queue_info *txq = &adapter->tx_obj.q;
1542 struct be_queue_info *tx_cq = &adapter->tx_obj.cq;
1543 struct be_eth_tx_compl *txcp;
1544 int tx_compl = 0, mcc_compl, status = 0;
1547 while ((txcp = be_tx_compl_get(tx_cq))) {
1548 end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl,
1550 be_tx_compl_process(adapter, end_idx);
1554 mcc_compl = be_process_mcc(adapter, &status);
1556 napi_complete(napi);
1559 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
1560 be_cq_notify(adapter, mcc_obj->cq.id, true, mcc_compl);
1564 be_cq_notify(adapter, adapter->tx_obj.cq.id, true, tx_compl);
1566 /* As Tx wrbs have been freed up, wake up netdev queue if
1567 * it was stopped due to lack of tx wrbs.
1569 if (netif_queue_stopped(adapter->netdev) &&
1570 atomic_read(&txq->used) < txq->len / 2) {
1571 netif_wake_queue(adapter->netdev);
1574 drvr_stats(adapter)->be_tx_events++;
1575 drvr_stats(adapter)->be_tx_compl += tx_compl;
1581 static void be_worker(struct work_struct *work)
1583 struct be_adapter *adapter =
1584 container_of(work, struct be_adapter, work.work);
1586 be_cmd_get_stats(adapter, &adapter->stats.cmd);
1589 be_rx_eqd_update(adapter);
1591 be_tx_rate_update(adapter);
1592 be_rx_rate_update(adapter);
1594 if (adapter->rx_post_starved) {
1595 adapter->rx_post_starved = false;
1596 be_post_rx_frags(adapter);
1599 schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
1602 static void be_msix_disable(struct be_adapter *adapter)
1604 if (adapter->msix_enabled) {
1605 pci_disable_msix(adapter->pdev);
1606 adapter->msix_enabled = false;
1610 static void be_msix_enable(struct be_adapter *adapter)
1614 for (i = 0; i < BE_NUM_MSIX_VECTORS; i++)
1615 adapter->msix_entries[i].entry = i;
1617 status = pci_enable_msix(adapter->pdev, adapter->msix_entries,
1618 BE_NUM_MSIX_VECTORS);
1620 adapter->msix_enabled = true;
1623 static void be_sriov_enable(struct be_adapter *adapter)
1625 #ifdef CONFIG_PCI_IOV
1627 if (be_physfn(adapter) && num_vfs) {
1628 status = pci_enable_sriov(adapter->pdev, num_vfs);
1629 adapter->sriov_enabled = status ? false : true;
1634 static void be_sriov_disable(struct be_adapter *adapter)
1636 #ifdef CONFIG_PCI_IOV
1637 if (adapter->sriov_enabled) {
1638 pci_disable_sriov(adapter->pdev);
1639 adapter->sriov_enabled = false;
1644 static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id)
1646 return adapter->msix_entries[
1647 be_evt_bit_get(adapter, eq_id)].vector;
1650 static int be_request_irq(struct be_adapter *adapter,
1651 struct be_eq_obj *eq_obj,
1652 void *handler, char *desc)
1654 struct net_device *netdev = adapter->netdev;
1657 sprintf(eq_obj->desc, "%s-%s", netdev->name, desc);
1658 vec = be_msix_vec_get(adapter, eq_obj->q.id);
1659 return request_irq(vec, handler, 0, eq_obj->desc, adapter);
1662 static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj)
1664 int vec = be_msix_vec_get(adapter, eq_obj->q.id);
1665 free_irq(vec, adapter);
1668 static int be_msix_register(struct be_adapter *adapter)
1672 status = be_request_irq(adapter, &adapter->tx_eq, be_msix_tx_mcc, "tx");
1676 status = be_request_irq(adapter, &adapter->rx_eq, be_msix_rx, "rx");
1683 be_free_irq(adapter, &adapter->tx_eq);
1685 dev_warn(&adapter->pdev->dev,
1686 "MSIX Request IRQ failed - err %d\n", status);
1687 pci_disable_msix(adapter->pdev);
1688 adapter->msix_enabled = false;
1692 static int be_irq_register(struct be_adapter *adapter)
1694 struct net_device *netdev = adapter->netdev;
1697 if (adapter->msix_enabled) {
1698 status = be_msix_register(adapter);
1701 /* INTx is not supported for VF */
1702 if (!be_physfn(adapter))
1707 netdev->irq = adapter->pdev->irq;
1708 status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name,
1711 dev_err(&adapter->pdev->dev,
1712 "INTx request IRQ failed - err %d\n", status);
1716 adapter->isr_registered = true;
1720 static void be_irq_unregister(struct be_adapter *adapter)
1722 struct net_device *netdev = adapter->netdev;
1724 if (!adapter->isr_registered)
1728 if (!adapter->msix_enabled) {
1729 free_irq(netdev->irq, adapter);
1734 be_free_irq(adapter, &adapter->tx_eq);
1735 be_free_irq(adapter, &adapter->rx_eq);
1737 adapter->isr_registered = false;
1740 static int be_close(struct net_device *netdev)
1742 struct be_adapter *adapter = netdev_priv(netdev);
1743 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1744 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1747 cancel_delayed_work_sync(&adapter->work);
1749 be_async_mcc_disable(adapter);
1751 netif_stop_queue(netdev);
1752 netif_carrier_off(netdev);
1753 adapter->link_up = false;
1755 be_intr_set(adapter, false);
1757 if (adapter->msix_enabled) {
1758 vec = be_msix_vec_get(adapter, tx_eq->q.id);
1759 synchronize_irq(vec);
1760 vec = be_msix_vec_get(adapter, rx_eq->q.id);
1761 synchronize_irq(vec);
1763 synchronize_irq(netdev->irq);
1765 be_irq_unregister(adapter);
1767 napi_disable(&rx_eq->napi);
1768 napi_disable(&tx_eq->napi);
1770 /* Wait for all pending tx completions to arrive so that
1771 * all tx skbs are freed.
1773 be_tx_compl_clean(adapter);
1778 static int be_open(struct net_device *netdev)
1780 struct be_adapter *adapter = netdev_priv(netdev);
1781 struct be_eq_obj *rx_eq = &adapter->rx_eq;
1782 struct be_eq_obj *tx_eq = &adapter->tx_eq;
1788 /* First time posting */
1789 be_post_rx_frags(adapter);
1791 napi_enable(&rx_eq->napi);
1792 napi_enable(&tx_eq->napi);
1794 be_irq_register(adapter);
1796 be_intr_set(adapter, true);
1798 /* The evt queues are created in unarmed state; arm them */
1799 be_eq_notify(adapter, rx_eq->q.id, true, false, 0);
1800 be_eq_notify(adapter, tx_eq->q.id, true, false, 0);
1802 /* Rx compl queue may be in unarmed state; rearm it */
1803 be_cq_notify(adapter, adapter->rx_obj.cq.id, true, 0);
1805 /* Now that interrupts are on we can process async mcc */
1806 be_async_mcc_enable(adapter);
1808 schedule_delayed_work(&adapter->work, msecs_to_jiffies(100));
1810 status = be_cmd_link_status_query(adapter, &link_up, &mac_speed,
1814 be_link_status_update(adapter, link_up);
1816 if (be_physfn(adapter)) {
1817 status = be_vid_config(adapter);
1821 status = be_cmd_set_flow_control(adapter,
1822 adapter->tx_fc, adapter->rx_fc);
1829 be_close(adapter->netdev);
1833 static int be_setup_wol(struct be_adapter *adapter, bool enable)
1835 struct be_dma_mem cmd;
1839 memset(mac, 0, ETH_ALEN);
1841 cmd.size = sizeof(struct be_cmd_req_acpi_wol_magic_config);
1842 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size, &cmd.dma);
1845 memset(cmd.va, 0, cmd.size);
1848 status = pci_write_config_dword(adapter->pdev,
1849 PCICFG_PM_CONTROL_OFFSET, PCICFG_PM_CONTROL_MASK);
1851 dev_err(&adapter->pdev->dev,
1852 "Could not enable Wake-on-lan\n");
1853 pci_free_consistent(adapter->pdev, cmd.size, cmd.va,
1857 status = be_cmd_enable_magic_wol(adapter,
1858 adapter->netdev->dev_addr, &cmd);
1859 pci_enable_wake(adapter->pdev, PCI_D3hot, 1);
1860 pci_enable_wake(adapter->pdev, PCI_D3cold, 1);
1862 status = be_cmd_enable_magic_wol(adapter, mac, &cmd);
1863 pci_enable_wake(adapter->pdev, PCI_D3hot, 0);
1864 pci_enable_wake(adapter->pdev, PCI_D3cold, 0);
1867 pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma);
1871 static int be_setup(struct be_adapter *adapter)
1873 struct net_device *netdev = adapter->netdev;
1874 u32 cap_flags, en_flags, vf = 0;
1878 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST;
1880 if (be_physfn(adapter)) {
1881 cap_flags |= BE_IF_FLAGS_MCAST_PROMISCUOUS |
1882 BE_IF_FLAGS_PROMISCUOUS |
1883 BE_IF_FLAGS_PASS_L3L4_ERRORS;
1884 en_flags |= BE_IF_FLAGS_PASS_L3L4_ERRORS;
1887 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1888 netdev->dev_addr, false/* pmac_invalid */,
1889 &adapter->if_handle, &adapter->pmac_id, 0);
1893 if (be_physfn(adapter)) {
1894 while (vf < num_vfs) {
1895 cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED
1896 | BE_IF_FLAGS_BROADCAST;
1897 status = be_cmd_if_create(adapter, cap_flags, en_flags,
1898 mac, true, &adapter->vf_if_handle[vf],
1901 dev_err(&adapter->pdev->dev,
1902 "Interface Create failed for VF %d\n", vf);
1907 } else if (!be_physfn(adapter)) {
1908 status = be_cmd_mac_addr_query(adapter, mac,
1909 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
1911 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
1912 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
1916 status = be_tx_queues_create(adapter);
1920 status = be_rx_queues_create(adapter);
1924 status = be_mcc_queues_create(adapter);
1928 adapter->link_speed = -1;
1933 be_rx_queues_destroy(adapter);
1935 be_tx_queues_destroy(adapter);
1937 for (vf = 0; vf < num_vfs; vf++)
1938 if (adapter->vf_if_handle[vf])
1939 be_cmd_if_destroy(adapter, adapter->vf_if_handle[vf]);
1940 be_cmd_if_destroy(adapter, adapter->if_handle);
1945 static int be_clear(struct be_adapter *adapter)
1947 be_mcc_queues_destroy(adapter);
1948 be_rx_queues_destroy(adapter);
1949 be_tx_queues_destroy(adapter);
1951 be_cmd_if_destroy(adapter, adapter->if_handle);
1953 /* tell fw we're done with firing cmds */
1954 be_cmd_fw_clean(adapter);
1959 #define FW_FILE_HDR_SIGN "ServerEngines Corp. "
1960 char flash_cookie[2][16] = {"*** SE FLAS",
1961 "H DIRECTORY *** "};
1963 static bool be_flash_redboot(struct be_adapter *adapter,
1964 const u8 *p, u32 img_start, int image_size,
1971 crc_offset = hdr_size + img_start + image_size - 4;
1975 status = be_cmd_get_flash_crc(adapter, flashed_crc,
1978 dev_err(&adapter->pdev->dev,
1979 "could not get crc from flash, not flashing redboot\n");
1983 /*update redboot only if crc does not match*/
1984 if (!memcmp(flashed_crc, p, 4))
1990 static int be_flash_data(struct be_adapter *adapter,
1991 const struct firmware *fw,
1992 struct be_dma_mem *flash_cmd, int num_of_images)
1995 int status = 0, i, filehdr_size = 0;
1996 u32 total_bytes = 0, flash_op;
1998 const u8 *p = fw->data;
1999 struct be_cmd_write_flashrom *req = flash_cmd->va;
2000 struct flash_comp *pflashcomp;
2003 struct flash_comp gen3_flash_types[9] = {
2004 { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE,
2005 FLASH_IMAGE_MAX_SIZE_g3},
2006 { FLASH_REDBOOT_START_g3, IMG_TYPE_REDBOOT,
2007 FLASH_REDBOOT_IMAGE_MAX_SIZE_g3},
2008 { FLASH_iSCSI_BIOS_START_g3, IMG_TYPE_BIOS,
2009 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2010 { FLASH_PXE_BIOS_START_g3, IMG_TYPE_PXE_BIOS,
2011 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2012 { FLASH_FCoE_BIOS_START_g3, IMG_TYPE_FCOE_BIOS,
2013 FLASH_BIOS_IMAGE_MAX_SIZE_g3},
2014 { FLASH_iSCSI_BACKUP_IMAGE_START_g3, IMG_TYPE_ISCSI_BACKUP,
2015 FLASH_IMAGE_MAX_SIZE_g3},
2016 { FLASH_FCoE_PRIMARY_IMAGE_START_g3, IMG_TYPE_FCOE_FW_ACTIVE,
2017 FLASH_IMAGE_MAX_SIZE_g3},
2018 { FLASH_FCoE_BACKUP_IMAGE_START_g3, IMG_TYPE_FCOE_FW_BACKUP,
2019 FLASH_IMAGE_MAX_SIZE_g3},
2020 { FLASH_NCSI_START_g3, IMG_TYPE_NCSI_FW,
2021 FLASH_NCSI_IMAGE_MAX_SIZE_g3}
2023 struct flash_comp gen2_flash_types[8] = {
2024 { FLASH_iSCSI_PRIMARY_IMAGE_START_g2, IMG_TYPE_ISCSI_ACTIVE,
2025 FLASH_IMAGE_MAX_SIZE_g2},
2026 { FLASH_REDBOOT_START_g2, IMG_TYPE_REDBOOT,
2027 FLASH_REDBOOT_IMAGE_MAX_SIZE_g2},
2028 { FLASH_iSCSI_BIOS_START_g2, IMG_TYPE_BIOS,
2029 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2030 { FLASH_PXE_BIOS_START_g2, IMG_TYPE_PXE_BIOS,
2031 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2032 { FLASH_FCoE_BIOS_START_g2, IMG_TYPE_FCOE_BIOS,
2033 FLASH_BIOS_IMAGE_MAX_SIZE_g2},
2034 { FLASH_iSCSI_BACKUP_IMAGE_START_g2, IMG_TYPE_ISCSI_BACKUP,
2035 FLASH_IMAGE_MAX_SIZE_g2},
2036 { FLASH_FCoE_PRIMARY_IMAGE_START_g2, IMG_TYPE_FCOE_FW_ACTIVE,
2037 FLASH_IMAGE_MAX_SIZE_g2},
2038 { FLASH_FCoE_BACKUP_IMAGE_START_g2, IMG_TYPE_FCOE_FW_BACKUP,
2039 FLASH_IMAGE_MAX_SIZE_g2}
2042 if (adapter->generation == BE_GEN3) {
2043 pflashcomp = gen3_flash_types;
2044 filehdr_size = sizeof(struct flash_file_hdr_g3);
2047 pflashcomp = gen2_flash_types;
2048 filehdr_size = sizeof(struct flash_file_hdr_g2);
2051 for (i = 0; i < num_comp; i++) {
2052 if ((pflashcomp[i].optype == IMG_TYPE_NCSI_FW) &&
2053 memcmp(adapter->fw_ver, "3.102.148.0", 11) < 0)
2055 if ((pflashcomp[i].optype == IMG_TYPE_REDBOOT) &&
2056 (!be_flash_redboot(adapter, fw->data,
2057 pflashcomp[i].offset, pflashcomp[i].size,
2061 p += filehdr_size + pflashcomp[i].offset
2062 + (num_of_images * sizeof(struct image_hdr));
2063 if (p + pflashcomp[i].size > fw->data + fw->size)
2065 total_bytes = pflashcomp[i].size;
2066 while (total_bytes) {
2067 if (total_bytes > 32*1024)
2068 num_bytes = 32*1024;
2070 num_bytes = total_bytes;
2071 total_bytes -= num_bytes;
2074 flash_op = FLASHROM_OPER_FLASH;
2076 flash_op = FLASHROM_OPER_SAVE;
2077 memcpy(req->params.data_buf, p, num_bytes);
2079 status = be_cmd_write_flashrom(adapter, flash_cmd,
2080 pflashcomp[i].optype, flash_op, num_bytes);
2082 dev_err(&adapter->pdev->dev,
2083 "cmd to write to flash rom failed.\n");
2092 static int get_ufigen_type(struct flash_file_hdr_g2 *fhdr)
2096 if (fhdr->build[0] == '3')
2098 else if (fhdr->build[0] == '2')
2104 int be_load_fw(struct be_adapter *adapter, u8 *func)
2106 char fw_file[ETHTOOL_FLASH_MAX_FILENAME];
2107 const struct firmware *fw;
2108 struct flash_file_hdr_g2 *fhdr;
2109 struct flash_file_hdr_g3 *fhdr3;
2110 struct image_hdr *img_hdr_ptr = NULL;
2111 struct be_dma_mem flash_cmd;
2112 int status, i = 0, num_imgs = 0;
2115 strcpy(fw_file, func);
2117 status = request_firmware(&fw, fw_file, &adapter->pdev->dev);
2122 fhdr = (struct flash_file_hdr_g2 *) p;
2123 dev_info(&adapter->pdev->dev, "Flashing firmware file %s\n", fw_file);
2125 flash_cmd.size = sizeof(struct be_cmd_write_flashrom) + 32*1024;
2126 flash_cmd.va = pci_alloc_consistent(adapter->pdev, flash_cmd.size,
2128 if (!flash_cmd.va) {
2130 dev_err(&adapter->pdev->dev,
2131 "Memory allocation failure while flashing\n");
2135 if ((adapter->generation == BE_GEN3) &&
2136 (get_ufigen_type(fhdr) == BE_GEN3)) {
2137 fhdr3 = (struct flash_file_hdr_g3 *) fw->data;
2138 num_imgs = le32_to_cpu(fhdr3->num_imgs);
2139 for (i = 0; i < num_imgs; i++) {
2140 img_hdr_ptr = (struct image_hdr *) (fw->data +
2141 (sizeof(struct flash_file_hdr_g3) +
2142 i * sizeof(struct image_hdr)));
2143 if (le32_to_cpu(img_hdr_ptr->imageid) == 1)
2144 status = be_flash_data(adapter, fw, &flash_cmd,
2147 } else if ((adapter->generation == BE_GEN2) &&
2148 (get_ufigen_type(fhdr) == BE_GEN2)) {
2149 status = be_flash_data(adapter, fw, &flash_cmd, 0);
2151 dev_err(&adapter->pdev->dev,
2152 "UFI and Interface are not compatible for flashing\n");
2156 pci_free_consistent(adapter->pdev, flash_cmd.size, flash_cmd.va,
2159 dev_err(&adapter->pdev->dev, "Firmware load error\n");
2163 dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
2166 release_firmware(fw);
2170 static struct net_device_ops be_netdev_ops = {
2171 .ndo_open = be_open,
2172 .ndo_stop = be_close,
2173 .ndo_start_xmit = be_xmit,
2174 .ndo_get_stats = be_get_stats,
2175 .ndo_set_rx_mode = be_set_multicast_list,
2176 .ndo_set_mac_address = be_mac_addr_set,
2177 .ndo_change_mtu = be_change_mtu,
2178 .ndo_validate_addr = eth_validate_addr,
2179 .ndo_vlan_rx_register = be_vlan_register,
2180 .ndo_vlan_rx_add_vid = be_vlan_add_vid,
2181 .ndo_vlan_rx_kill_vid = be_vlan_rem_vid,
2182 .ndo_set_vf_mac = be_set_vf_mac
2185 static void be_netdev_init(struct net_device *netdev)
2187 struct be_adapter *adapter = netdev_priv(netdev);
2189 netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO |
2190 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_HW_CSUM |
2191 NETIF_F_GRO | NETIF_F_TSO6;
2193 netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_HW_CSUM;
2195 netdev->flags |= IFF_MULTICAST;
2197 adapter->rx_csum = true;
2199 /* Default settings for Rx and Tx flow control */
2200 adapter->rx_fc = true;
2201 adapter->tx_fc = true;
2203 netif_set_gso_max_size(netdev, 65535);
2205 BE_SET_NETDEV_OPS(netdev, &be_netdev_ops);
2207 SET_ETHTOOL_OPS(netdev, &be_ethtool_ops);
2209 netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx,
2211 netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx_mcc,
2214 netif_carrier_off(netdev);
2215 netif_stop_queue(netdev);
2218 static void be_unmap_pci_bars(struct be_adapter *adapter)
2221 iounmap(adapter->csr);
2223 iounmap(adapter->db);
2224 if (adapter->pcicfg && be_physfn(adapter))
2225 iounmap(adapter->pcicfg);
2228 static int be_map_pci_bars(struct be_adapter *adapter)
2231 int pcicfg_reg, db_reg;
2233 if (be_physfn(adapter)) {
2234 addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2),
2235 pci_resource_len(adapter->pdev, 2));
2238 adapter->csr = addr;
2241 if (adapter->generation == BE_GEN2) {
2246 if (be_physfn(adapter))
2251 addr = ioremap_nocache(pci_resource_start(adapter->pdev, db_reg),
2252 pci_resource_len(adapter->pdev, db_reg));
2257 if (be_physfn(adapter)) {
2258 addr = ioremap_nocache(
2259 pci_resource_start(adapter->pdev, pcicfg_reg),
2260 pci_resource_len(adapter->pdev, pcicfg_reg));
2263 adapter->pcicfg = addr;
2265 adapter->pcicfg = adapter->db + SRIOV_VF_PCICFG_OFFSET;
2269 be_unmap_pci_bars(adapter);
2274 static void be_ctrl_cleanup(struct be_adapter *adapter)
2276 struct be_dma_mem *mem = &adapter->mbox_mem_alloced;
2278 be_unmap_pci_bars(adapter);
2281 pci_free_consistent(adapter->pdev, mem->size,
2284 mem = &adapter->mc_cmd_mem;
2286 pci_free_consistent(adapter->pdev, mem->size,
2290 static int be_ctrl_init(struct be_adapter *adapter)
2292 struct be_dma_mem *mbox_mem_alloc = &adapter->mbox_mem_alloced;
2293 struct be_dma_mem *mbox_mem_align = &adapter->mbox_mem;
2294 struct be_dma_mem *mc_cmd_mem = &adapter->mc_cmd_mem;
2297 status = be_map_pci_bars(adapter);
2301 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
2302 mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev,
2303 mbox_mem_alloc->size, &mbox_mem_alloc->dma);
2304 if (!mbox_mem_alloc->va) {
2306 goto unmap_pci_bars;
2309 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
2310 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
2311 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
2312 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
2314 mc_cmd_mem->size = sizeof(struct be_cmd_req_mcast_mac_config);
2315 mc_cmd_mem->va = pci_alloc_consistent(adapter->pdev, mc_cmd_mem->size,
2317 if (mc_cmd_mem->va == NULL) {
2321 memset(mc_cmd_mem->va, 0, mc_cmd_mem->size);
2323 spin_lock_init(&adapter->mbox_lock);
2324 spin_lock_init(&adapter->mcc_lock);
2325 spin_lock_init(&adapter->mcc_cq_lock);
2327 init_completion(&adapter->flash_compl);
2328 pci_save_state(adapter->pdev);
2332 pci_free_consistent(adapter->pdev, mbox_mem_alloc->size,
2333 mbox_mem_alloc->va, mbox_mem_alloc->dma);
2336 be_unmap_pci_bars(adapter);
2342 static void be_stats_cleanup(struct be_adapter *adapter)
2344 struct be_stats_obj *stats = &adapter->stats;
2345 struct be_dma_mem *cmd = &stats->cmd;
2348 pci_free_consistent(adapter->pdev, cmd->size,
2352 static int be_stats_init(struct be_adapter *adapter)
2354 struct be_stats_obj *stats = &adapter->stats;
2355 struct be_dma_mem *cmd = &stats->cmd;
2357 cmd->size = sizeof(struct be_cmd_req_get_stats);
2358 cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma);
2359 if (cmd->va == NULL)
2361 memset(cmd->va, 0, cmd->size);
2365 static void __devexit be_remove(struct pci_dev *pdev)
2367 struct be_adapter *adapter = pci_get_drvdata(pdev);
2372 unregister_netdev(adapter->netdev);
2376 be_stats_cleanup(adapter);
2378 be_ctrl_cleanup(adapter);
2380 be_sriov_disable(adapter);
2382 be_msix_disable(adapter);
2384 pci_set_drvdata(pdev, NULL);
2385 pci_release_regions(pdev);
2386 pci_disable_device(pdev);
2388 free_netdev(adapter->netdev);
2391 static int be_get_config(struct be_adapter *adapter)
2396 status = be_cmd_get_fw_ver(adapter, adapter->fw_ver);
2400 status = be_cmd_query_fw_cfg(adapter,
2401 &adapter->port_num, &adapter->cap);
2405 memset(mac, 0, ETH_ALEN);
2407 if (be_physfn(adapter)) {
2408 status = be_cmd_mac_addr_query(adapter, mac,
2409 MAC_ADDRESS_TYPE_NETWORK, true /*permanent */, 0);
2414 if (!is_valid_ether_addr(mac))
2415 return -EADDRNOTAVAIL;
2417 memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN);
2418 memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN);
2421 if (adapter->cap & 0x400)
2422 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED/4;
2424 adapter->max_vlans = BE_NUM_VLANS_SUPPORTED;
2429 static int __devinit be_probe(struct pci_dev *pdev,
2430 const struct pci_device_id *pdev_id)
2433 struct be_adapter *adapter;
2434 struct net_device *netdev;
2437 status = pci_enable_device(pdev);
2441 status = pci_request_regions(pdev, DRV_NAME);
2444 pci_set_master(pdev);
2446 netdev = alloc_etherdev(sizeof(struct be_adapter));
2447 if (netdev == NULL) {
2451 adapter = netdev_priv(netdev);
2453 switch (pdev->device) {
2456 adapter->generation = BE_GEN2;
2460 adapter->generation = BE_GEN3;
2463 adapter->generation = 0;
2466 adapter->pdev = pdev;
2467 pci_set_drvdata(pdev, adapter);
2468 adapter->netdev = netdev;
2469 be_netdev_init(netdev);
2470 SET_NETDEV_DEV(netdev, &pdev->dev);
2472 be_msix_enable(adapter);
2474 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2476 netdev->features |= NETIF_F_HIGHDMA;
2478 status = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2480 dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
2485 be_sriov_enable(adapter);
2487 status = be_ctrl_init(adapter);
2491 /* sync up with fw's ready state */
2492 if (be_physfn(adapter)) {
2493 status = be_cmd_POST(adapter);
2498 /* tell fw we're ready to fire cmds */
2499 status = be_cmd_fw_init(adapter);
2503 if (be_physfn(adapter)) {
2504 status = be_cmd_reset_function(adapter);
2509 status = be_stats_init(adapter);
2513 status = be_get_config(adapter);
2517 INIT_DELAYED_WORK(&adapter->work, be_worker);
2519 status = be_setup(adapter);
2523 status = register_netdev(netdev);
2527 dev_info(&pdev->dev, "%s port %d\n", nic_name(pdev), adapter->port_num);
2533 be_stats_cleanup(adapter);
2535 be_ctrl_cleanup(adapter);
2537 be_msix_disable(adapter);
2538 be_sriov_disable(adapter);
2539 free_netdev(adapter->netdev);
2540 pci_set_drvdata(pdev, NULL);
2542 pci_release_regions(pdev);
2544 pci_disable_device(pdev);
2546 dev_err(&pdev->dev, "%s initialization failed\n", nic_name(pdev));
2550 static int be_suspend(struct pci_dev *pdev, pm_message_t state)
2552 struct be_adapter *adapter = pci_get_drvdata(pdev);
2553 struct net_device *netdev = adapter->netdev;
2556 be_setup_wol(adapter, true);
2558 netif_device_detach(netdev);
2559 if (netif_running(netdev)) {
2564 be_cmd_get_flow_control(adapter, &adapter->tx_fc, &adapter->rx_fc);
2567 pci_save_state(pdev);
2568 pci_disable_device(pdev);
2569 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2573 static int be_resume(struct pci_dev *pdev)
2576 struct be_adapter *adapter = pci_get_drvdata(pdev);
2577 struct net_device *netdev = adapter->netdev;
2579 netif_device_detach(netdev);
2581 status = pci_enable_device(pdev);
2585 pci_set_power_state(pdev, 0);
2586 pci_restore_state(pdev);
2588 /* tell fw we're ready to fire cmds */
2589 status = be_cmd_fw_init(adapter);
2594 if (netif_running(netdev)) {
2599 netif_device_attach(netdev);
2602 be_setup_wol(adapter, false);
2607 * An FLR will stop BE from DMAing any data.
2609 static void be_shutdown(struct pci_dev *pdev)
2611 struct be_adapter *adapter = pci_get_drvdata(pdev);
2612 struct net_device *netdev = adapter->netdev;
2614 netif_device_detach(netdev);
2616 be_cmd_reset_function(adapter);
2619 be_setup_wol(adapter, true);
2621 pci_disable_device(pdev);
2624 static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
2625 pci_channel_state_t state)
2627 struct be_adapter *adapter = pci_get_drvdata(pdev);
2628 struct net_device *netdev = adapter->netdev;
2630 dev_err(&adapter->pdev->dev, "EEH error detected\n");
2632 adapter->eeh_err = true;
2634 netif_device_detach(netdev);
2636 if (netif_running(netdev)) {
2643 if (state == pci_channel_io_perm_failure)
2644 return PCI_ERS_RESULT_DISCONNECT;
2646 pci_disable_device(pdev);
2648 return PCI_ERS_RESULT_NEED_RESET;
2651 static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
2653 struct be_adapter *adapter = pci_get_drvdata(pdev);
2656 dev_info(&adapter->pdev->dev, "EEH reset\n");
2657 adapter->eeh_err = false;
2659 status = pci_enable_device(pdev);
2661 return PCI_ERS_RESULT_DISCONNECT;
2663 pci_set_master(pdev);
2664 pci_set_power_state(pdev, 0);
2665 pci_restore_state(pdev);
2667 /* Check if card is ok and fw is ready */
2668 status = be_cmd_POST(adapter);
2670 return PCI_ERS_RESULT_DISCONNECT;
2672 return PCI_ERS_RESULT_RECOVERED;
2675 static void be_eeh_resume(struct pci_dev *pdev)
2678 struct be_adapter *adapter = pci_get_drvdata(pdev);
2679 struct net_device *netdev = adapter->netdev;
2681 dev_info(&adapter->pdev->dev, "EEH resume\n");
2683 pci_save_state(pdev);
2685 /* tell fw we're ready to fire cmds */
2686 status = be_cmd_fw_init(adapter);
2690 status = be_setup(adapter);
2694 if (netif_running(netdev)) {
2695 status = be_open(netdev);
2699 netif_device_attach(netdev);
2702 dev_err(&adapter->pdev->dev, "EEH resume failed\n");
2705 static struct pci_error_handlers be_eeh_handlers = {
2706 .error_detected = be_eeh_err_detected,
2707 .slot_reset = be_eeh_reset,
2708 .resume = be_eeh_resume,
2711 static struct pci_driver be_driver = {
2713 .id_table = be_dev_ids,
2715 .remove = be_remove,
2716 .suspend = be_suspend,
2717 .resume = be_resume,
2718 .shutdown = be_shutdown,
2719 .err_handler = &be_eeh_handlers
2722 static int __init be_init_module(void)
2724 if (rx_frag_size != 8192 && rx_frag_size != 4096 &&
2725 rx_frag_size != 2048) {
2726 printk(KERN_WARNING DRV_NAME
2727 " : Module param rx_frag_size must be 2048/4096/8192."
2729 rx_frag_size = 2048;
2733 printk(KERN_WARNING DRV_NAME
2734 " : Module param num_vfs must not be greater than 32."
2739 return pci_register_driver(&be_driver);
2741 module_init(be_init_module);
2743 static void __exit be_exit_module(void)
2745 pci_unregister_driver(&be_driver);
2747 module_exit(be_exit_module);