drivers/net/benet/be_cmds.h

   1 /*
   2  * Copyright (C) 2005 - 2009 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 /*
  19  * The driver sends configuration and managements command requests to the
  20  * firmware in the BE. These requests are communicated to the processor
  21  * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one
  22  * WRB inside a MAILBOX.
  23  * The commands are serviced by the ARM processor in the BladeEngine's MPU.
  24  */
  25
  26 struct be_sge {
  27         u32 pa_lo;
  28         u32 pa_hi;
  29         u32 len;
  30 };
  31
  32 #define MCC_WRB_EMBEDDED_MASK   1       /* bit 0 of dword 0*/
  33 #define MCC_WRB_SGE_CNT_SHIFT   3       /* bits 3 - 7 of dword 0 */
  34 #define MCC_WRB_SGE_CNT_MASK    0x1F    /* bits 3 - 7 of dword 0 */
  35 struct be_mcc_wrb {
  36         u32 embedded;           /* dword 0 */
  37         u32 payload_length;     /* dword 1 */
  38         u32 tag0;               /* dword 2 */
  39         u32 tag1;               /* dword 3 */
  40         u32 rsvd;               /* dword 4 */
  41         union {
  42                 u8 embedded_payload[236]; /* used by embedded cmds */
  43                 struct be_sge sgl[19];    /* used by non-embedded cmds */
  44         } payload;
  45 };
  46
  47 #define CQE_FLAGS_VALID_MASK            (1 << 31)
  48 #define CQE_FLAGS_ASYNC_MASK            (1 << 30)
  49 #define CQE_FLAGS_COMPLETED_MASK        (1 << 28)
  50 #define CQE_FLAGS_CONSUMED_MASK         (1 << 27)
  51
  52 /* Completion Status */
  53 enum {
  54         MCC_STATUS_SUCCESS = 0x0,
  55 /* The client does not have sufficient privileges to execute the command */
  56         MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1,
  57 /* A parameter in the command was invalid. */
  58         MCC_STATUS_INVALID_PARAMETER = 0x2,
  59 /* There are insufficient chip resources to execute the command */
  60         MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3,
  61 /* The command is completing because the queue was getting flushed */
  62         MCC_STATUS_QUEUE_FLUSHING = 0x4,
  63 /* The command is completing with a DMA error */
  64         MCC_STATUS_DMA_FAILED = 0x5,
  65         MCC_STATUS_NOT_SUPPORTED = 66
  66 };
  67
  68 #define CQE_STATUS_COMPL_MASK           0xFFFF
  69 #define CQE_STATUS_COMPL_SHIFT          0       /* bits 0 - 15 */
  70 #define CQE_STATUS_EXTD_MASK            0xFFFF
  71 #define CQE_STATUS_EXTD_SHIFT           16      /* bits 16 - 31 */
  72
  73 struct be_mcc_compl {
  74         u32 status;             /* dword 0 */
  75         u32 tag0;               /* dword 1 */
  76         u32 tag1;               /* dword 2 */
  77         u32 flags;              /* dword 3 */
  78 };
  79
  80 /* When the async bit of mcc_compl is set, the last 4 bytes of
  81  * mcc_compl is interpreted as follows:
  82  */
  83 #define ASYNC_TRAILER_EVENT_CODE_SHIFT  8       /* bits 8 - 15 */
  84 #define ASYNC_TRAILER_EVENT_CODE_MASK   0xFF
  85 #define ASYNC_EVENT_CODE_LINK_STATE     0x1
  86 struct be_async_event_trailer {
  87         u32 code;
  88 };
  89
  90 enum {
  91         ASYNC_EVENT_LINK_DOWN   = 0x0,
  92         ASYNC_EVENT_LINK_UP     = 0x1
  93 };
  94
  95 /* When the event code of an async trailer is link-state, the mcc_compl
  96  * must be interpreted as follows
  97  */
  98 struct be_async_event_link_state {
  99         u8 physical_port;
 100         u8 port_link_status;
 101         u8 port_duplex;
 102         u8 port_speed;
 103         u8 port_fault;
 104         u8 rsvd0[7];
 105         struct be_async_event_trailer trailer;
 106 } __packed;
 107
 108 struct be_mcc_mailbox {
 109         struct be_mcc_wrb wrb;
 110         struct be_mcc_compl compl;
 111 };
 112
 113 #define CMD_SUBSYSTEM_COMMON    0x1
 114 #define CMD_SUBSYSTEM_ETH       0x3
 115 #define CMD_SUBSYSTEM_LOWLEVEL  0xb
 116
 117 #define OPCODE_COMMON_NTWK_MAC_QUERY                    1
 118 #define OPCODE_COMMON_NTWK_MAC_SET                      2
 119 #define OPCODE_COMMON_NTWK_MULTICAST_SET                3
 120 #define OPCODE_COMMON_NTWK_VLAN_CONFIG                  4
 121 #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY            5
 122 #define OPCODE_COMMON_READ_FLASHROM                     6
 123 #define OPCODE_COMMON_WRITE_FLASHROM                    7
 124 #define OPCODE_COMMON_CQ_CREATE                         12
 125 #define OPCODE_COMMON_EQ_CREATE                         13
 126 #define OPCODE_COMMON_MCC_CREATE                        21
 127 #define OPCODE_COMMON_NTWK_RX_FILTER                    34
 128 #define OPCODE_COMMON_GET_FW_VERSION                    35
 129 #define OPCODE_COMMON_SET_FLOW_CONTROL                  36
 130 #define OPCODE_COMMON_GET_FLOW_CONTROL                  37
 131 #define OPCODE_COMMON_SET_FRAME_SIZE                    39
 132 #define OPCODE_COMMON_MODIFY_EQ_DELAY                   41
 133 #define OPCODE_COMMON_FIRMWARE_CONFIG                   42
 134 #define OPCODE_COMMON_NTWK_INTERFACE_CREATE             50
 135 #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY            51
 136 #define OPCODE_COMMON_MCC_DESTROY                       53
 137 #define OPCODE_COMMON_CQ_DESTROY                        54
 138 #define OPCODE_COMMON_EQ_DESTROY                        55
 139 #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG             58
 140 #define OPCODE_COMMON_NTWK_PMAC_ADD                     59
 141 #define OPCODE_COMMON_NTWK_PMAC_DEL                     60
 142 #define OPCODE_COMMON_FUNCTION_RESET                    61
 143 #define OPCODE_COMMON_ENABLE_DISABLE_BEACON             69
 144 #define OPCODE_COMMON_GET_BEACON_STATE                  70
 145 #define OPCODE_COMMON_READ_TRANSRECV_DATA               73
 146
 147 #define OPCODE_ETH_ACPI_CONFIG                          2
 148 #define OPCODE_ETH_PROMISCUOUS                          3
 149 #define OPCODE_ETH_GET_STATISTICS                       4
 150 #define OPCODE_ETH_TX_CREATE                            7
 151 #define OPCODE_ETH_RX_CREATE                            8
 152 #define OPCODE_ETH_TX_DESTROY                           9
 153 #define OPCODE_ETH_RX_DESTROY                           10
 154 #define OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG                12
 155
 156 #define OPCODE_LOWLEVEL_HOST_DDR_DMA                    17
 157 #define OPCODE_LOWLEVEL_LOOPBACK_TEST                   18
 158
 159 struct be_cmd_req_hdr {
 160         u8 opcode;              /* dword 0 */
 161         u8 subsystem;           /* dword 0 */
 162         u8 port_number;         /* dword 0 */
 163         u8 domain;              /* dword 0 */
 164         u32 timeout;            /* dword 1 */
 165         u32 request_length;     /* dword 2 */
 166         u32 rsvd;               /* dword 3 */
 167 };
 168
 169 #define RESP_HDR_INFO_OPCODE_SHIFT      0       /* bits 0 - 7 */
 170 #define RESP_HDR_INFO_SUBSYS_SHIFT      8       /* bits 8 - 15 */
 171 struct be_cmd_resp_hdr {
 172         u32 info;               /* dword 0 */
 173         u32 status;             /* dword 1 */
 174         u32 response_length;    /* dword 2 */
 175         u32 actual_resp_len;    /* dword 3 */
 176 };
 177
 178 struct phys_addr {
 179         u32 lo;
 180         u32 hi;
 181 };
 182
 183 /**************************
 184  * BE Command definitions *
 185  **************************/
 186
 187 /* Pseudo amap definition in which each bit of the actual structure is defined
 188  * as a byte: used to calculate offset/shift/mask of each field */
 189 struct amap_eq_context {
 190         u8 cidx[13];            /* dword 0*/
 191         u8 rsvd0[3];            /* dword 0*/
 192         u8 epidx[13];           /* dword 0*/
 193         u8 valid;               /* dword 0*/
 194         u8 rsvd1;               /* dword 0*/
 195         u8 size;                /* dword 0*/
 196         u8 pidx[13];            /* dword 1*/
 197         u8 rsvd2[3];            /* dword 1*/
 198         u8 pd[10];              /* dword 1*/
 199         u8 count[3];            /* dword 1*/
 200         u8 solevent;            /* dword 1*/
 201         u8 stalled;             /* dword 1*/
 202         u8 armed;               /* dword 1*/
 203         u8 rsvd3[4];            /* dword 2*/
 204         u8 func[8];             /* dword 2*/
 205         u8 rsvd4;               /* dword 2*/
 206         u8 delaymult[10];       /* dword 2*/
 207         u8 rsvd5[2];            /* dword 2*/
 208         u8 phase[2];            /* dword 2*/
 209         u8 nodelay;             /* dword 2*/
 210         u8 rsvd6[4];            /* dword 2*/
 211         u8 rsvd7[32];           /* dword 3*/
 212 } __packed;
 213
 214 struct be_cmd_req_eq_create {
 215         struct be_cmd_req_hdr hdr;
 216         u16 num_pages;          /* sword */
 217         u16 rsvd0;              /* sword */
 218         u8 context[sizeof(struct amap_eq_context) / 8];
 219         struct phys_addr pages[8];
 220 } __packed;
 221
 222 struct be_cmd_resp_eq_create {
 223         struct be_cmd_resp_hdr resp_hdr;
 224         u16 eq_id;              /* sword */
 225         u16 rsvd0;              /* sword */
 226 } __packed;
 227
 228 /******************** Mac query ***************************/
 229 enum {
 230         MAC_ADDRESS_TYPE_STORAGE = 0x0,
 231         MAC_ADDRESS_TYPE_NETWORK = 0x1,
 232         MAC_ADDRESS_TYPE_PD = 0x2,
 233         MAC_ADDRESS_TYPE_MANAGEMENT = 0x3
 234 };
 235
 236 struct mac_addr {
 237         u16 size_of_struct;
 238         u8 addr[ETH_ALEN];
 239 } __packed;
 240
 241 struct be_cmd_req_mac_query {
 242         struct be_cmd_req_hdr hdr;
 243         u8 type;
 244         u8 permanent;
 245         u16 if_id;
 246 } __packed;
 247
 248 struct be_cmd_resp_mac_query {
 249         struct be_cmd_resp_hdr hdr;
 250         struct mac_addr mac;
 251 };
 252
 253 /******************** PMac Add ***************************/
 254 struct be_cmd_req_pmac_add {
 255         struct be_cmd_req_hdr hdr;
 256         u32 if_id;
 257         u8 mac_address[ETH_ALEN];
 258         u8 rsvd0[2];
 259 } __packed;
 260
 261 struct be_cmd_resp_pmac_add {
 262         struct be_cmd_resp_hdr hdr;
 263         u32 pmac_id;
 264 };
 265
 266 /******************** PMac Del ***************************/
 267 struct be_cmd_req_pmac_del {
 268         struct be_cmd_req_hdr hdr;
 269         u32 if_id;
 270         u32 pmac_id;
 271 };
 272
 273 /******************** Create CQ ***************************/
 274 /* Pseudo amap definition in which each bit of the actual structure is defined
 275  * as a byte: used to calculate offset/shift/mask of each field */
 276 struct amap_cq_context {
 277         u8 cidx[11];            /* dword 0*/
 278         u8 rsvd0;               /* dword 0*/
 279         u8 coalescwm[2];        /* dword 0*/
 280         u8 nodelay;             /* dword 0*/
 281         u8 epidx[11];           /* dword 0*/
 282         u8 rsvd1;               /* dword 0*/
 283         u8 count[2];            /* dword 0*/
 284         u8 valid;               /* dword 0*/
 285         u8 solevent;            /* dword 0*/
 286         u8 eventable;           /* dword 0*/
 287         u8 pidx[11];            /* dword 1*/
 288         u8 rsvd2;               /* dword 1*/
 289         u8 pd[10];              /* dword 1*/
 290         u8 eqid[8];             /* dword 1*/
 291         u8 stalled;             /* dword 1*/
 292         u8 armed;               /* dword 1*/
 293         u8 rsvd3[4];            /* dword 2*/
 294         u8 func[8];             /* dword 2*/
 295         u8 rsvd4[20];           /* dword 2*/
 296         u8 rsvd5[32];           /* dword 3*/
 297 } __packed;
 298
 299 struct be_cmd_req_cq_create {
 300         struct be_cmd_req_hdr hdr;
 301         u16 num_pages;
 302         u16 rsvd0;
 303         u8 context[sizeof(struct amap_cq_context) / 8];
 304         struct phys_addr pages[8];
 305 } __packed;
 306
 307 struct be_cmd_resp_cq_create {
 308         struct be_cmd_resp_hdr hdr;
 309         u16 cq_id;
 310         u16 rsvd0;
 311 } __packed;
 312
 313 /******************** Create MCCQ ***************************/
 314 /* Pseudo amap definition in which each bit of the actual structure is defined
 315  * as a byte: used to calculate offset/shift/mask of each field */
 316 struct amap_mcc_context {
 317         u8 con_index[14];
 318         u8 rsvd0[2];
 319         u8 ring_size[4];
 320         u8 fetch_wrb;
 321         u8 fetch_r2t;
 322         u8 cq_id[10];
 323         u8 prod_index[14];
 324         u8 fid[8];
 325         u8 pdid[9];
 326         u8 valid;
 327         u8 rsvd1[32];
 328         u8 rsvd2[32];
 329 } __packed;
 330
 331 struct be_cmd_req_mcc_create {
 332         struct be_cmd_req_hdr hdr;
 333         u16 num_pages;
 334         u16 rsvd0;
 335         u8 context[sizeof(struct amap_mcc_context) / 8];
 336         struct phys_addr pages[8];
 337 } __packed;
 338
 339 struct be_cmd_resp_mcc_create {
 340         struct be_cmd_resp_hdr hdr;
 341         u16 id;
 342         u16 rsvd0;
 343 } __packed;
 344
 345 /******************** Create TxQ ***************************/
 346 #define BE_ETH_TX_RING_TYPE_STANDARD            2
 347 #define BE_ULP1_NUM                             1
 348
 349 /* Pseudo amap definition in which each bit of the actual structure is defined
 350  * as a byte: used to calculate offset/shift/mask of each field */
 351 struct amap_tx_context {
 352         u8 rsvd0[16];           /* dword 0 */
 353         u8 tx_ring_size[4];     /* dword 0 */
 354         u8 rsvd1[26];           /* dword 0 */
 355         u8 pci_func_id[8];      /* dword 1 */
 356         u8 rsvd2[9];            /* dword 1 */
 357         u8 ctx_valid;           /* dword 1 */
 358         u8 cq_id_send[16];      /* dword 2 */
 359         u8 rsvd3[16];           /* dword 2 */
 360         u8 rsvd4[32];           /* dword 3 */
 361         u8 rsvd5[32];           /* dword 4 */
 362         u8 rsvd6[32];           /* dword 5 */
 363         u8 rsvd7[32];           /* dword 6 */
 364         u8 rsvd8[32];           /* dword 7 */
 365         u8 rsvd9[32];           /* dword 8 */
 366         u8 rsvd10[32];          /* dword 9 */
 367         u8 rsvd11[32];          /* dword 10 */
 368         u8 rsvd12[32];          /* dword 11 */
 369         u8 rsvd13[32];          /* dword 12 */
 370         u8 rsvd14[32];          /* dword 13 */
 371         u8 rsvd15[32];          /* dword 14 */
 372         u8 rsvd16[32];          /* dword 15 */
 373 } __packed;
 374
 375 struct be_cmd_req_eth_tx_create {
 376         struct be_cmd_req_hdr hdr;
 377         u8 num_pages;
 378         u8 ulp_num;
 379         u8 type;
 380         u8 bound_port;
 381         u8 context[sizeof(struct amap_tx_context) / 8];
 382         struct phys_addr pages[8];
 383 } __packed;
 384
 385 struct be_cmd_resp_eth_tx_create {
 386         struct be_cmd_resp_hdr hdr;
 387         u16 cid;
 388         u16 rsvd0;
 389 } __packed;
 390
 391 /******************** Create RxQ ***************************/
 392 struct be_cmd_req_eth_rx_create {
 393         struct be_cmd_req_hdr hdr;
 394         u16 cq_id;
 395         u8 frag_size;
 396         u8 num_pages;
 397         struct phys_addr pages[2];
 398         u32 interface_id;
 399         u16 max_frame_size;
 400         u16 rsvd0;
 401         u32 rss_queue;
 402 } __packed;
 403
 404 struct be_cmd_resp_eth_rx_create {
 405         struct be_cmd_resp_hdr hdr;
 406         u16 id;
 407         u8 cpu_id;
 408         u8 rsvd0;
 409 } __packed;
 410
 411 /******************** Q Destroy  ***************************/
 412 /* Type of Queue to be destroyed */
 413 enum {
 414         QTYPE_EQ = 1,
 415         QTYPE_CQ,
 416         QTYPE_TXQ,
 417         QTYPE_RXQ,
 418         QTYPE_MCCQ
 419 };
 420
 421 struct be_cmd_req_q_destroy {
 422         struct be_cmd_req_hdr hdr;
 423         u16 id;
 424         u16 bypass_flush;       /* valid only for rx q destroy */
 425 } __packed;
 426
 427 /************ I/f Create (it's actually I/f Config Create)**********/
 428
 429 /* Capability flags for the i/f */
 430 enum be_if_flags {
 431         BE_IF_FLAGS_RSS = 0x4,
 432         BE_IF_FLAGS_PROMISCUOUS = 0x8,
 433         BE_IF_FLAGS_BROADCAST = 0x10,
 434         BE_IF_FLAGS_UNTAGGED = 0x20,
 435         BE_IF_FLAGS_ULP = 0x40,
 436         BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80,
 437         BE_IF_FLAGS_VLAN = 0x100,
 438         BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200,
 439         BE_IF_FLAGS_PASS_L2_ERRORS = 0x400,
 440         BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800
 441 };
 442
 443 /* An RX interface is an object with one or more MAC addresses and
 444  * filtering capabilities. */
 445 struct be_cmd_req_if_create {
 446         struct be_cmd_req_hdr hdr;
 447         u32 version;            /* ignore currently */
 448         u32 capability_flags;
 449         u32 enable_flags;
 450         u8 mac_addr[ETH_ALEN];
 451         u8 rsvd0;
 452         u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */
 453         u32 vlan_tag;    /* not used currently */
 454 } __packed;
 455
 456 struct be_cmd_resp_if_create {
 457         struct be_cmd_resp_hdr hdr;
 458         u32 interface_id;
 459         u32 pmac_id;
 460 };
 461
 462 /****** I/f Destroy(it's actually I/f Config Destroy )**********/
 463 struct be_cmd_req_if_destroy {
 464         struct be_cmd_req_hdr hdr;
 465         u32 interface_id;
 466 };
 467
 468 /*************** HW Stats Get **********************************/
 469 struct be_port_rxf_stats {
 470         u32 rx_bytes_lsd;       /* dword 0*/
 471         u32 rx_bytes_msd;       /* dword 1*/
 472         u32 rx_total_frames;    /* dword 2*/
 473         u32 rx_unicast_frames;  /* dword 3*/
 474         u32 rx_multicast_frames;        /* dword 4*/
 475         u32 rx_broadcast_frames;        /* dword 5*/
 476         u32 rx_crc_errors;      /* dword 6*/
 477         u32 rx_alignment_symbol_errors; /* dword 7*/
 478         u32 rx_pause_frames;    /* dword 8*/
 479         u32 rx_control_frames;  /* dword 9*/
 480         u32 rx_in_range_errors; /* dword 10*/
 481         u32 rx_out_range_errors;        /* dword 11*/
 482         u32 rx_frame_too_long;  /* dword 12*/
 483         u32 rx_address_match_errors;    /* dword 13*/
 484         u32 rx_vlan_mismatch;   /* dword 14*/
 485         u32 rx_dropped_too_small;       /* dword 15*/
 486         u32 rx_dropped_too_short;       /* dword 16*/
 487         u32 rx_dropped_header_too_small;        /* dword 17*/
 488         u32 rx_dropped_tcp_length;      /* dword 18*/
 489         u32 rx_dropped_runt;    /* dword 19*/
 490         u32 rx_64_byte_packets; /* dword 20*/
 491         u32 rx_65_127_byte_packets;     /* dword 21*/
 492         u32 rx_128_256_byte_packets;    /* dword 22*/
 493         u32 rx_256_511_byte_packets;    /* dword 23*/
 494         u32 rx_512_1023_byte_packets;   /* dword 24*/
 495         u32 rx_1024_1518_byte_packets;  /* dword 25*/
 496         u32 rx_1519_2047_byte_packets;  /* dword 26*/
 497         u32 rx_2048_4095_byte_packets;  /* dword 27*/
 498         u32 rx_4096_8191_byte_packets;  /* dword 28*/
 499         u32 rx_8192_9216_byte_packets;  /* dword 29*/
 500         u32 rx_ip_checksum_errs;        /* dword 30*/
 501         u32 rx_tcp_checksum_errs;       /* dword 31*/
 502         u32 rx_udp_checksum_errs;       /* dword 32*/
 503         u32 rx_non_rss_packets; /* dword 33*/
 504         u32 rx_ipv4_packets;    /* dword 34*/
 505         u32 rx_ipv6_packets;    /* dword 35*/
 506         u32 rx_ipv4_bytes_lsd;  /* dword 36*/
 507         u32 rx_ipv4_bytes_msd;  /* dword 37*/
 508         u32 rx_ipv6_bytes_lsd;  /* dword 38*/
 509         u32 rx_ipv6_bytes_msd;  /* dword 39*/
 510         u32 rx_chute1_packets;  /* dword 40*/
 511         u32 rx_chute2_packets;  /* dword 41*/
 512         u32 rx_chute3_packets;  /* dword 42*/
 513         u32 rx_management_packets;      /* dword 43*/
 514         u32 rx_switched_unicast_packets;        /* dword 44*/
 515         u32 rx_switched_multicast_packets;      /* dword 45*/
 516         u32 rx_switched_broadcast_packets;      /* dword 46*/
 517         u32 tx_bytes_lsd;       /* dword 47*/
 518         u32 tx_bytes_msd;       /* dword 48*/
 519         u32 tx_unicastframes;   /* dword 49*/
 520         u32 tx_multicastframes; /* dword 50*/
 521         u32 tx_broadcastframes; /* dword 51*/
 522         u32 tx_pauseframes;     /* dword 52*/
 523         u32 tx_controlframes;   /* dword 53*/
 524         u32 tx_64_byte_packets; /* dword 54*/
 525         u32 tx_65_127_byte_packets;     /* dword 55*/
 526         u32 tx_128_256_byte_packets;    /* dword 56*/
 527         u32 tx_256_511_byte_packets;    /* dword 57*/
 528         u32 tx_512_1023_byte_packets;   /* dword 58*/
 529         u32 tx_1024_1518_byte_packets;  /* dword 59*/
 530         u32 tx_1519_2047_byte_packets;  /* dword 60*/
 531         u32 tx_2048_4095_byte_packets;  /* dword 61*/
 532         u32 tx_4096_8191_byte_packets;  /* dword 62*/
 533         u32 tx_8192_9216_byte_packets;  /* dword 63*/
 534         u32 rx_fifo_overflow;   /* dword 64*/
 535         u32 rx_input_fifo_overflow;     /* dword 65*/
 536 };
 537
 538 struct be_rxf_stats {
 539         struct be_port_rxf_stats port[2];
 540         u32 rx_drops_no_pbuf;   /* dword 132*/
 541         u32 rx_drops_no_txpb;   /* dword 133*/
 542         u32 rx_drops_no_erx_descr;      /* dword 134*/
 543         u32 rx_drops_no_tpre_descr;     /* dword 135*/
 544         u32 management_rx_port_packets; /* dword 136*/
 545         u32 management_rx_port_bytes;   /* dword 137*/
 546         u32 management_rx_port_pause_frames;    /* dword 138*/
 547         u32 management_rx_port_errors;  /* dword 139*/
 548         u32 management_tx_port_packets; /* dword 140*/
 549         u32 management_tx_port_bytes;   /* dword 141*/
 550         u32 management_tx_port_pause;   /* dword 142*/
 551         u32 management_rx_port_rxfifo_overflow; /* dword 143*/
 552         u32 rx_drops_too_many_frags;    /* dword 144*/
 553         u32 rx_drops_invalid_ring;      /* dword 145*/
 554         u32 forwarded_packets;  /* dword 146*/
 555         u32 rx_drops_mtu;       /* dword 147*/
 556         u32 rsvd0[15];
 557 };
 558
 559 struct be_erx_stats {
 560         u32 rx_drops_no_fragments[44];     /* dwordS 0 to 43*/
 561         u32 debug_wdma_sent_hold;          /* dword 44*/
 562         u32 debug_wdma_pbfree_sent_hold;   /* dword 45*/
 563         u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/
 564         u32 debug_pmem_pbuf_dealloc;       /* dword 47*/
 565 };
 566
 567 struct be_hw_stats {
 568         struct be_rxf_stats rxf;
 569         u32 rsvd[48];
 570         struct be_erx_stats erx;
 571 };
 572
 573 struct be_cmd_req_get_stats {
 574         struct be_cmd_req_hdr hdr;
 575         u8 rsvd[sizeof(struct be_hw_stats)];
 576 };
 577
 578 struct be_cmd_resp_get_stats {
 579         struct be_cmd_resp_hdr hdr;
 580         struct be_hw_stats hw_stats;
 581 };
 582
 583 struct be_cmd_req_vlan_config {
 584         struct be_cmd_req_hdr hdr;
 585         u8 interface_id;
 586         u8 promiscuous;
 587         u8 untagged;
 588         u8 num_vlan;
 589         u16 normal_vlan[64];
 590 } __packed;
 591
 592 struct be_cmd_req_promiscuous_config {
 593         struct be_cmd_req_hdr hdr;
 594         u8 port0_promiscuous;
 595         u8 port1_promiscuous;
 596         u16 rsvd0;
 597 } __packed;
 598
 599 /******************** Multicast MAC Config *******************/
 600 #define BE_MAX_MC               64 /* set mcast promisc if > 64 */
 601 struct macaddr {
 602         u8 byte[ETH_ALEN];
 603 };
 604
 605 struct be_cmd_req_mcast_mac_config {
 606         struct be_cmd_req_hdr hdr;
 607         u16 num_mac;
 608         u8 promiscuous;
 609         u8 interface_id;
 610         struct macaddr mac[BE_MAX_MC];
 611 } __packed;
 612
 613 static inline struct be_hw_stats *
 614 hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd)
 615 {
 616         return &cmd->hw_stats;
 617 }
 618
 619 /******************** Link Status Query *******************/
 620 struct be_cmd_req_link_status {
 621         struct be_cmd_req_hdr hdr;
 622         u32 rsvd;
 623 };
 624
 625 enum {
 626         PHY_LINK_DUPLEX_NONE = 0x0,
 627         PHY_LINK_DUPLEX_HALF = 0x1,
 628         PHY_LINK_DUPLEX_FULL = 0x2
 629 };
 630
 631 enum {
 632         PHY_LINK_SPEED_ZERO = 0x0,      /* => No link */
 633         PHY_LINK_SPEED_10MBPS = 0x1,
 634         PHY_LINK_SPEED_100MBPS = 0x2,
 635         PHY_LINK_SPEED_1GBPS = 0x3,
 636         PHY_LINK_SPEED_10GBPS = 0x4
 637 };
 638
 639 struct be_cmd_resp_link_status {
 640         struct be_cmd_resp_hdr hdr;
 641         u8 physical_port;
 642         u8 mac_duplex;
 643         u8 mac_speed;
 644         u8 mac_fault;
 645         u8 mgmt_mac_duplex;
 646         u8 mgmt_mac_speed;
 647         u16 link_speed;
 648         u32 rsvd0;
 649 } __packed;
 650
 651 /******************** Port Identification ***************************/
 652 /*    Identifies the type of port attached to NIC     */
 653 struct be_cmd_req_port_type {
 654         struct be_cmd_req_hdr hdr;
 655         u32 page_num;
 656         u32 port;
 657 };
 658
 659 enum {
 660         TR_PAGE_A0 = 0xa0,
 661         TR_PAGE_A2 = 0xa2
 662 };
 663
 664 struct be_cmd_resp_port_type {
 665         struct be_cmd_resp_hdr hdr;
 666         u32 page_num;
 667         u32 port;
 668         struct data {
 669                 u8 identifier;
 670                 u8 identifier_ext;
 671                 u8 connector;
 672                 u8 transceiver[8];
 673                 u8 rsvd0[3];
 674                 u8 length_km;
 675                 u8 length_hm;
 676                 u8 length_om1;
 677                 u8 length_om2;
 678                 u8 length_cu;
 679                 u8 length_cu_m;
 680                 u8 vendor_name[16];
 681                 u8 rsvd;
 682                 u8 vendor_oui[3];
 683                 u8 vendor_pn[16];
 684                 u8 vendor_rev[4];
 685         } data;
 686 };
 687
 688 /******************** Get FW Version *******************/
 689 struct be_cmd_req_get_fw_version {
 690         struct be_cmd_req_hdr hdr;
 691         u8 rsvd0[FW_VER_LEN];
 692         u8 rsvd1[FW_VER_LEN];
 693 } __packed;
 694
 695 struct be_cmd_resp_get_fw_version {
 696         struct be_cmd_resp_hdr hdr;
 697         u8 firmware_version_string[FW_VER_LEN];
 698         u8 fw_on_flash_version_string[FW_VER_LEN];
 699 } __packed;
 700
 701 /******************** Set Flow Contrl *******************/
 702 struct be_cmd_req_set_flow_control {
 703         struct be_cmd_req_hdr hdr;
 704         u16 tx_flow_control;
 705         u16 rx_flow_control;
 706 } __packed;
 707
 708 /******************** Get Flow Contrl *******************/
 709 struct be_cmd_req_get_flow_control {
 710         struct be_cmd_req_hdr hdr;
 711         u32 rsvd;
 712 };
 713
 714 struct be_cmd_resp_get_flow_control {
 715         struct be_cmd_resp_hdr hdr;
 716         u16 tx_flow_control;
 717         u16 rx_flow_control;
 718 } __packed;
 719
 720 /******************** Modify EQ Delay *******************/
 721 struct be_cmd_req_modify_eq_delay {
 722         struct be_cmd_req_hdr hdr;
 723         u32 num_eq;
 724         struct {
 725                 u32 eq_id;
 726                 u32 phase;
 727                 u32 delay_multiplier;
 728         } delay[8];
 729 } __packed;
 730
 731 struct be_cmd_resp_modify_eq_delay {
 732         struct be_cmd_resp_hdr hdr;
 733         u32 rsvd0;
 734 } __packed;
 735
 736 /******************** Get FW Config *******************/
 737 struct be_cmd_req_query_fw_cfg {
 738         struct be_cmd_req_hdr hdr;
 739         u32 rsvd[30];
 740 };
 741
 742 struct be_cmd_resp_query_fw_cfg {
 743         struct be_cmd_resp_hdr hdr;
 744         u32 be_config_number;
 745         u32 asic_revision;
 746         u32 phys_port;
 747         u32 function_cap;
 748         u32 rsvd[26];
 749 };
 750
 751 /******************** Port Beacon ***************************/
 752
 753 #define BEACON_STATE_ENABLED            0x1
 754 #define BEACON_STATE_DISABLED           0x0
 755
 756 struct be_cmd_req_enable_disable_beacon {
 757         struct be_cmd_req_hdr hdr;
 758         u8  port_num;
 759         u8  beacon_state;
 760         u8  beacon_duration;
 761         u8  status_duration;
 762 } __packed;
 763
 764 struct be_cmd_resp_enable_disable_beacon {
 765         struct be_cmd_resp_hdr resp_hdr;
 766         u32 rsvd0;
 767 } __packed;
 768
 769 struct be_cmd_req_get_beacon_state {
 770         struct be_cmd_req_hdr hdr;
 771         u8  port_num;
 772         u8  rsvd0;
 773         u16 rsvd1;
 774 } __packed;
 775
 776 struct be_cmd_resp_get_beacon_state {
 777         struct be_cmd_resp_hdr resp_hdr;
 778         u8 beacon_state;
 779         u8 rsvd0[3];
 780 } __packed;
 781
 782 /****************** Firmware Flash ******************/
 783 struct flashrom_params {
 784         u32 op_code;
 785         u32 op_type;
 786         u32 data_buf_size;
 787         u32 offset;
 788         u8 data_buf[4];
 789 };
 790
 791 struct be_cmd_write_flashrom {
 792         struct be_cmd_req_hdr hdr;
 793         struct flashrom_params params;
 794 };
 795
 796 /************************ WOL *******************************/
 797 struct be_cmd_req_acpi_wol_magic_config{
 798         struct be_cmd_req_hdr hdr;
 799         u32 rsvd0[145];
 800         u8 magic_mac[6];
 801         u8 rsvd2[2];
 802 } __packed;
 803
 804 /********************** LoopBack test *********************/
 805 struct be_cmd_req_loopback_test {
 806         struct be_cmd_req_hdr hdr;
 807         u32 loopback_type;
 808         u32 num_pkts;
 809         u64 pattern;
 810         u32 src_port;
 811         u32 dest_port;
 812         u32 pkt_size;
 813 };
 814
 815 struct be_cmd_resp_loopback_test {
 816         struct be_cmd_resp_hdr resp_hdr;
 817         u32    status;
 818         u32    num_txfer;
 819         u32    num_rx;
 820         u32    miscomp_off;
 821         u32    ticks_compl;
 822 };
 823
 824 /********************** DDR DMA test *********************/
 825 struct be_cmd_req_ddrdma_test {
 826         struct be_cmd_req_hdr hdr;
 827         u64 pattern;
 828         u32 byte_count;
 829         u32 rsvd0;
 830         u8  snd_buff[4096];
 831         u8  rsvd1[4096];
 832 };
 833
 834 struct be_cmd_resp_ddrdma_test {
 835         struct be_cmd_resp_hdr hdr;
 836         u64 pattern;
 837         u32 byte_cnt;
 838         u32 snd_err;
 839         u8  rsvd0[4096];
 840         u8  rcv_buff[4096];
 841 };
 842
 843 extern int be_pci_fnum_get(struct be_adapter *adapter);
 844 extern int be_cmd_POST(struct be_adapter *adapter);
 845 extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
 846                         u8 type, bool permanent, u32 if_handle);
 847 extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
 848                         u32 if_id, u32 *pmac_id);
 849 extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id);
 850 extern int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags,
 851                         u32 en_flags, u8 *mac, bool pmac_invalid,
 852                         u32 *if_handle, u32 *pmac_id);
 853 extern int be_cmd_if_destroy(struct be_adapter *adapter, u32 if_handle);
 854 extern int be_cmd_eq_create(struct be_adapter *adapter,
 855                         struct be_queue_info *eq, int eq_delay);
 856 extern int be_cmd_cq_create(struct be_adapter *adapter,
 857                         struct be_queue_info *cq, struct be_queue_info *eq,
 858                         bool sol_evts, bool no_delay,
 859                         int num_cqe_dma_coalesce);
 860 extern int be_cmd_mccq_create(struct be_adapter *adapter,
 861                         struct be_queue_info *mccq,
 862                         struct be_queue_info *cq);
 863 extern int be_cmd_txq_create(struct be_adapter *adapter,
 864                         struct be_queue_info *txq,
 865                         struct be_queue_info *cq);
 866 extern int be_cmd_rxq_create(struct be_adapter *adapter,
 867                         struct be_queue_info *rxq, u16 cq_id,
 868                         u16 frag_size, u16 max_frame_size, u32 if_id,
 869                         u32 rss);
 870 extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
 871                         int type);
 872 extern int be_cmd_link_status_query(struct be_adapter *adapter,
 873                         bool *link_up, u8 *mac_speed, u16 *link_speed);
 874 extern int be_cmd_reset(struct be_adapter *adapter);
 875 extern int be_cmd_get_stats(struct be_adapter *adapter,
 876                         struct be_dma_mem *nonemb_cmd);
 877 extern int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver);
 878
 879 extern int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd);
 880 extern int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id,
 881                         u16 *vtag_array, u32 num, bool untagged,
 882                         bool promiscuous);
 883 extern int be_cmd_promiscuous_config(struct be_adapter *adapter,
 884                         u8 port_num, bool en);
 885 extern int be_cmd_multicast_set(struct be_adapter *adapter, u32 if_id,
 886                         struct dev_mc_list *mc_list, u32 mc_count,
 887                         struct be_dma_mem *mem);
 888 extern int be_cmd_set_flow_control(struct be_adapter *adapter,
 889                         u32 tx_fc, u32 rx_fc);
 890 extern int be_cmd_get_flow_control(struct be_adapter *adapter,
 891                         u32 *tx_fc, u32 *rx_fc);
 892 extern int be_cmd_query_fw_cfg(struct be_adapter *adapter,
 893                         u32 *port_num, u32 *cap);
 894 extern int be_cmd_reset_function(struct be_adapter *adapter);
 895 extern int be_process_mcc(struct be_adapter *adapter);
 896 extern int be_cmd_set_beacon_state(struct be_adapter *adapter,
 897                         u8 port_num, u8 beacon, u8 status, u8 state);
 898 extern int be_cmd_get_beacon_state(struct be_adapter *adapter,
 899                         u8 port_num, u32 *state);
 900 extern int be_cmd_read_port_type(struct be_adapter *adapter, u32 port,
 901                                         u8 *connector);
 902 extern int be_cmd_write_flashrom(struct be_adapter *adapter,
 903                         struct be_dma_mem *cmd, u32 flash_oper,
 904                         u32 flash_opcode, u32 buf_size);
 905 extern int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc);
 906 extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
 907                                 struct be_dma_mem *nonemb_cmd);
 908 extern int be_cmd_fw_init(struct be_adapter *adapter);
 909 extern int be_cmd_fw_clean(struct be_adapter *adapter);
 910 extern int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
 911                                 u32 loopback_type, u32 pkt_size,
 912                                 u32 num_pkts, u64 pattern);
 913 extern int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
 914                         u32 byte_cnt, struct be_dma_mem *cmd);