2 * Copyright (C) 2005 - 2010 ServerEngines
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@serverengines.com
14 * 209 N. Fair Oaks Ave
21 #include <linux/pci.h>
22 #include <linux/etherdevice.h>
23 #include <linux/version.h>
24 #include <linux/delay.h>
28 #include <linux/if_vlan.h>
29 #include <linux/workqueue.h>
30 #include <linux/interrupt.h>
31 #include <linux/firmware.h>
35 #define DRV_VER "2.102.147u"
36 #define DRV_NAME "be2net"
37 #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC"
38 #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC"
39 #define OC_NAME "Emulex OneConnect 10Gbps NIC"
40 #define OC_NAME1 "Emulex OneConnect 10Gbps NIC (be3)"
41 #define DRV_DESC "ServerEngines BladeEngine 10Gbps NIC Driver"
43 #define BE_VENDOR_ID 0x19a2
44 #define BE_DEVICE_ID1 0x211
45 #define BE_DEVICE_ID2 0x221
46 #define OC_DEVICE_ID1 0x700
47 #define OC_DEVICE_ID2 0x710
49 static inline char *nic_name(struct pci_dev *pdev)
51 switch (pdev->device) {
63 /* Number of bytes of an RX frame that are copied to skb->data */
65 #define BE_MAX_JUMBO_FRAME_SIZE 9018
66 #define BE_MIN_MTU 256
68 #define BE_NUM_VLANS_SUPPORTED 64
70 #define BE_MAX_TX_FRAG_COUNT 30
72 #define EVNT_Q_LEN 1024
74 #define TX_CQ_LEN 1024
75 #define RX_Q_LEN 1024 /* Does not support any other value */
76 #define RX_CQ_LEN 1024
77 #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */
78 #define MCC_CQ_LEN 256
80 #define BE_NAPI_WEIGHT 64
81 #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */
82 #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST)
94 struct be_queue_info {
95 struct be_dma_mem dma_mem;
97 u16 entry_size; /* Size of an element in the queue */
101 atomic_t used; /* Number of valid elements in the queue */
104 static inline u32 MODULO(u16 val, u16 limit)
106 BUG_ON(limit & (limit - 1));
107 return val & (limit - 1);
110 static inline void index_adv(u16 *index, u16 val, u16 limit)
112 *index = MODULO((*index + val), limit);
115 static inline void index_inc(u16 *index, u16 limit)
117 *index = MODULO((*index + 1), limit);
120 static inline void *queue_head_node(struct be_queue_info *q)
122 return q->dma_mem.va + q->head * q->entry_size;
125 static inline void *queue_tail_node(struct be_queue_info *q)
127 return q->dma_mem.va + q->tail * q->entry_size;
130 static inline void queue_head_inc(struct be_queue_info *q)
132 index_inc(&q->head, q->len);
135 static inline void queue_tail_inc(struct be_queue_info *q)
137 index_inc(&q->tail, q->len);
141 struct be_queue_info q;
144 /* Adaptive interrupt coalescing (AIC) info */
146 u16 min_eqd; /* in usecs */
147 u16 max_eqd; /* in usecs */
148 u16 cur_eqd; /* in usecs */
150 struct napi_struct napi;
154 struct be_queue_info q;
155 struct be_queue_info cq;
159 struct be_drvr_stats {
160 u32 be_tx_reqs; /* number of TX requests initiated */
161 u32 be_tx_stops; /* number of times TX Q was stopped */
162 u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */
163 u32 be_tx_wrbs; /* number of tx WRBs used */
164 u32 be_tx_events; /* number of tx completion events */
165 u32 be_tx_compl; /* number of tx completion entries processed */
168 u64 be_tx_bytes_prev;
172 u32 cache_barrier[16];
174 u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
175 u32 be_rx_polls; /* number of times NAPI called poll function */
176 u32 be_rx_events; /* number of ucast rx completion events */
177 u32 be_rx_compl; /* number of rx completion entries processed */
180 u64 be_rx_bytes_prev;
183 /* number of non ether type II frames dropped where
184 * frame len > length field of Mac Hdr */
185 u32 be_802_3_dropped_frames;
186 /* number of non ether type II frames malformed where
187 * in frame len < length field of Mac Hdr */
188 u32 be_802_3_malformed_frames;
189 u32 be_rxcp_err; /* Num rx completion entries w/ err set. */
190 ulong rx_fps_jiffies; /* jiffies at last FPS calc */
192 u32 be_prev_rx_frags;
193 u32 be_rx_fps; /* Rx frags per second */
196 struct be_stats_obj {
197 struct be_drvr_stats drvr_stats;
198 struct be_dma_mem cmd;
202 struct be_queue_info q;
203 struct be_queue_info cq;
204 /* Remember the skbs that were transmitted */
205 struct sk_buff *sent_skb_list[TX_Q_LEN];
208 /* Struct to remember the pages posted for rx frags */
209 struct be_rx_page_info {
217 struct be_queue_info q;
218 struct be_queue_info cq;
219 struct be_rx_page_info page_info_tbl[RX_Q_LEN];
222 #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */
224 struct pci_dev *pdev;
225 struct net_device *netdev;
228 u8 __iomem *db; /* Door Bell */
229 u8 __iomem *pcicfg; /* PCI config space */
231 spinlock_t mbox_lock; /* For serializing mbox cmds to BE card */
232 struct be_dma_mem mbox_mem;
233 /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
234 * is stored for freeing purpose */
235 struct be_dma_mem mbox_mem_alloced;
237 struct be_mcc_obj mcc_obj;
238 spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */
239 spinlock_t mcc_cq_lock;
241 struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
246 struct be_eq_obj tx_eq;
247 struct be_tx_obj tx_obj;
249 u32 cache_line_break[8];
252 struct be_eq_obj rx_eq;
253 struct be_rx_obj rx_obj;
254 u32 big_page_size; /* Compounded page size shared by rx wrbs */
255 bool rx_post_starved; /* Zero rx frags have been posted to BE */
257 struct vlan_group *vlan_grp;
259 u16 max_vlans; /* Number of vlans supported */
260 u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
261 struct be_dma_mem mc_cmd_mem;
263 struct be_stats_obj stats;
264 /* Work queue used to perform periodic tasks like getting statistics */
265 struct delayed_work work;
267 /* Ethtool knobs and info */
268 bool rx_csum; /* BE card must perform rx-checksumming */
269 char fw_ver[FW_VER_LEN];
270 u32 if_handle; /* Used to configure filtering */
271 u32 pmac_id; /* MAC addr handle used by BE card */
279 u32 rx_fc; /* Rx flow control */
280 u32 tx_fc; /* Tx flow control */
284 u8 generation; /* BladeEngine ASIC generation */
287 u32 vf_if_handle[BE_MAX_VF];
288 u32 vf_pmac_id[BE_MAX_VF];
292 #define be_physfn(adapter) (!adapter->pdev->is_virtfn)
294 /* BladeEngine Generation numbers */
298 extern const struct ethtool_ops be_ethtool_ops;
300 #define drvr_stats(adapter) (&adapter->stats.drvr_stats)
302 #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops)
304 #define PAGE_SHIFT_4K 12
305 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)
307 /* Returns number of pages spanned by the data starting at the given addr */
308 #define PAGES_4K_SPANNED(_address, size) \
309 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
310 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
312 /* Byte offset into the page corresponding to given address */
313 #define OFFSET_IN_PAGE(addr) \
314 ((size_t)(addr) & (PAGE_SIZE_4K-1))
316 /* Returns bit offset within a DWORD of a bitfield */
317 #define AMAP_BIT_OFFSET(_struct, field) \
318 (((size_t)&(((_struct *)0)->field))%32)
320 /* Returns the bit mask of the field that is NOT shifted into location. */
321 static inline u32 amap_mask(u32 bitsize)
323 return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
327 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
329 u32 *dw = (u32 *) ptr + dw_offset;
330 *dw &= ~(mask << offset);
331 *dw |= (mask & value) << offset;
334 #define AMAP_SET_BITS(_struct, field, ptr, val) \
336 offsetof(_struct, field)/32, \
337 amap_mask(sizeof(((_struct *)0)->field)), \
338 AMAP_BIT_OFFSET(_struct, field), \
341 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
343 u32 *dw = (u32 *) ptr;
344 return mask & (*(dw + dw_offset) >> offset);
347 #define AMAP_GET_BITS(_struct, field, ptr) \
349 offsetof(_struct, field)/32, \
350 amap_mask(sizeof(((_struct *)0)->field)), \
351 AMAP_BIT_OFFSET(_struct, field))
353 #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len)
354 #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len)
355 static inline void swap_dws(void *wrb, int len)
361 *dw = cpu_to_le32(*dw);
365 #endif /* __BIG_ENDIAN */
368 static inline u8 is_tcp_pkt(struct sk_buff *skb)
372 if (ip_hdr(skb)->version == 4)
373 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
374 else if (ip_hdr(skb)->version == 6)
375 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
380 static inline u8 is_udp_pkt(struct sk_buff *skb)
384 if (ip_hdr(skb)->version == 4)
385 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
386 else if (ip_hdr(skb)->version == 6)
387 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
392 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
394 extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
395 extern void netdev_stats_update(struct be_adapter *adapter);
396 extern int be_load_fw(struct be_adapter *adapter, u8 *func);