drivers/gpu/drm/nouveau/nv17_tv.c

   1 /*
   2  * Copyright (C) 2009 Francisco Jerez.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29 #include "nouveau_drv.h"
  30 #include "nouveau_encoder.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_crtc.h"
  33 #include "nouveau_hw.h"
  34 #include "nv17_tv.h"
  35
  36 static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder)
  37 {
  38         struct drm_device *dev = encoder->dev;
  39         struct drm_nouveau_private *dev_priv = dev->dev_private;
  40         struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
  41         uint32_t testval, regoffset = nv04_dac_output_offset(encoder);
  42         uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end,
  43                 fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c;
  44         uint32_t sample = 0;
  45         int head;
  46
  47 #define RGB_TEST_DATA(r, g, b) (r << 0 | g << 10 | b << 20)
  48         testval = RGB_TEST_DATA(0x82, 0xeb, 0x82);
  49         if (dev_priv->vbios.tvdactestval)
  50                 testval = dev_priv->vbios.tvdactestval;
  51
  52         dacclk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset);
  53         head = (dacclk & 0x100) >> 8;
  54
  55         /* Save the previous state. */
  56         gpio1 = gpio->get(dev, DCB_GPIO_TVDAC1);
  57         gpio0 = gpio->get(dev, DCB_GPIO_TVDAC0);
  58         fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL);
  59         fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START);
  60         fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END);
  61         fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
  62         test_ctrl = NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset);
  63         ctv_1c = NVReadRAMDAC(dev, head, 0x680c1c);
  64         ctv_14 = NVReadRAMDAC(dev, head, 0x680c14);
  65         ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c);
  66
  67         /* Prepare the DAC for load detection.  */
  68         gpio->set(dev, DCB_GPIO_TVDAC1, true);
  69         gpio->set(dev, DCB_GPIO_TVDAC0, true);
  70
  71         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343);
  72         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047);
  73         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, 1183);
  74         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL,
  75                       NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
  76                       NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12 |
  77                       NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
  78                       NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS |
  79                       NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS);
  80
  81         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, 0);
  82
  83         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  84                       (dacclk & ~0xff) | 0x22);
  85         msleep(1);
  86         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset,
  87                       (dacclk & ~0xff) | 0x21);
  88
  89         NVWriteRAMDAC(dev, head, 0x680c1c, 1 << 20);
  90         NVWriteRAMDAC(dev, head, 0x680c14, 4 << 16);
  91
  92         /* Sample pin 0x4 (usually S-video luma). */
  93         NVWriteRAMDAC(dev, head, 0x680c6c, testval >> 10 & 0x3ff);
  94         msleep(20);
  95         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
  96                 & 0x4 << 28;
  97
  98         /* Sample the remaining pins. */
  99         NVWriteRAMDAC(dev, head, 0x680c6c, testval & 0x3ff);
 100         msleep(20);
 101         sample |= NVReadRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset)
 102                 & 0xa << 28;
 103
 104         /* Restore the previous state. */
 105         NVWriteRAMDAC(dev, head, 0x680c1c, ctv_1c);
 106         NVWriteRAMDAC(dev, head, 0x680c14, ctv_14);
 107         NVWriteRAMDAC(dev, head, 0x680c6c, ctv_6c);
 108         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK + regoffset, dacclk);
 109         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + regoffset, test_ctrl);
 110         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, fp_control);
 111         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end);
 112         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start);
 113         NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal);
 114         gpio->set(dev, DCB_GPIO_TVDAC1, gpio1);
 115         gpio->set(dev, DCB_GPIO_TVDAC0, gpio0);
 116
 117         return sample;
 118 }
 119
 120 static bool
 121 get_tv_detect_quirks(struct drm_device *dev, uint32_t *pin_mask)
 122 {
 123         /* Zotac FX5200 */
 124         if (dev->pdev->device == 0x0322 &&
 125             dev->pdev->subsystem_vendor == 0x19da &&
 126             (dev->pdev->subsystem_device == 0x1035 ||
 127              dev->pdev->subsystem_device == 0x2035)) {
 128                 *pin_mask = 0xc;
 129                 return false;
 130         }
 131
 132         /* MSI nForce2 IGP */
 133         if (dev->pdev->device == 0x01f0 &&
 134             dev->pdev->subsystem_vendor == 0x1462 &&
 135             dev->pdev->subsystem_device == 0x5710) {
 136                 *pin_mask = 0xc;
 137                 return false;
 138         }
 139
 140         return true;
 141 }
 142
 143 static enum drm_connector_status
 144 nv17_tv_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 145 {
 146         struct drm_device *dev = encoder->dev;
 147         struct drm_nouveau_private *dev_priv = dev->dev_private;
 148         struct drm_mode_config *conf = &dev->mode_config;
 149         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 150         struct dcb_entry *dcb = tv_enc->base.dcb;
 151         bool reliable = get_tv_detect_quirks(dev, &tv_enc->pin_mask);
 152
 153         if (nv04_dac_in_use(encoder))
 154                 return connector_status_disconnected;
 155
 156         if (reliable) {
 157                 if (dev_priv->chipset == 0x42 ||
 158                     dev_priv->chipset == 0x43)
 159                         tv_enc->pin_mask =
 160                                 nv42_tv_sample_load(encoder) >> 28 & 0xe;
 161                 else
 162                         tv_enc->pin_mask =
 163                                 nv17_dac_sample_load(encoder) >> 28 & 0xe;
 164         }
 165
 166         switch (tv_enc->pin_mask) {
 167         case 0x2:
 168         case 0x4:
 169                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Composite;
 170                 break;
 171         case 0xc:
 172                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SVIDEO;
 173                 break;
 174         case 0xe:
 175                 if (dcb->tvconf.has_component_output)
 176                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Component;
 177                 else
 178                         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_SCART;
 179                 break;
 180         default:
 181                 tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 182                 break;
 183         }
 184
 185         drm_connector_property_set_value(connector,
 186                                          conf->tv_subconnector_property,
 187                                          tv_enc->subconnector);
 188
 189         if (!reliable) {
 190                 return connector_status_unknown;
 191         } else if (tv_enc->subconnector) {
 192                 NV_INFO(dev, "Load detected on output %c\n",
 193                         '@' + ffs(dcb->or));
 194                 return connector_status_connected;
 195         } else {
 196                 return connector_status_disconnected;
 197         }
 198 }
 199
 200 static const struct {
 201         int hdisplay;
 202         int vdisplay;
 203 } modes[] = {
 204         { 640, 400 },
 205         { 640, 480 },
 206         { 720, 480 },
 207         { 720, 576 },
 208         { 800, 600 },
 209         { 1024, 768 },
 210         { 1280, 720 },
 211         { 1280, 1024 },
 212         { 1920, 1080 }
 213 };
 214
 215 static int nv17_tv_get_modes(struct drm_encoder *encoder,
 216                              struct drm_connector *connector)
 217 {
 218         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 219         struct drm_display_mode *mode;
 220         struct drm_display_mode *output_mode;
 221         int n = 0;
 222         int i;
 223
 224         if (tv_norm->kind != CTV_ENC_MODE) {
 225                 struct drm_display_mode *tv_mode;
 226
 227                 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) {
 228                         mode = drm_mode_duplicate(encoder->dev, tv_mode);
 229
 230                         mode->clock = tv_norm->tv_enc_mode.vrefresh *
 231                                                 mode->htotal / 1000 *
 232                                                 mode->vtotal / 1000;
 233
 234                         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 235                                 mode->clock *= 2;
 236
 237                         if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay &&
 238                             mode->vdisplay == tv_norm->tv_enc_mode.vdisplay)
 239                                 mode->type |= DRM_MODE_TYPE_PREFERRED;
 240
 241                         drm_mode_probed_add(connector, mode);
 242                         n++;
 243                 }
 244                 return n;
 245         }
 246
 247         /* tv_norm->kind == CTV_ENC_MODE */
 248         output_mode = &tv_norm->ctv_enc_mode.mode;
 249         for (i = 0; i < ARRAY_SIZE(modes); i++) {
 250                 if (modes[i].hdisplay > output_mode->hdisplay ||
 251                     modes[i].vdisplay > output_mode->vdisplay)
 252                         continue;
 253
 254                 if (modes[i].hdisplay == output_mode->hdisplay &&
 255                     modes[i].vdisplay == output_mode->vdisplay) {
 256                         mode = drm_mode_duplicate(encoder->dev, output_mode);
 257                         mode->type |= DRM_MODE_TYPE_PREFERRED;
 258                 } else {
 259                         mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay,
 260                                 modes[i].vdisplay, 60, false,
 261                                 output_mode->flags & DRM_MODE_FLAG_INTERLACE,
 262                                 false);
 263                 }
 264
 265                 /* CVT modes are sometimes unsuitable... */
 266                 if (output_mode->hdisplay <= 720
 267                     || output_mode->hdisplay >= 1920) {
 268                         mode->htotal = output_mode->htotal;
 269                         mode->hsync_start = (mode->hdisplay + (mode->htotal
 270                                              - mode->hdisplay) * 9 / 10) & ~7;
 271                         mode->hsync_end = mode->hsync_start + 8;
 272                 }
 273                 if (output_mode->vdisplay >= 1024) {
 274                         mode->vtotal = output_mode->vtotal;
 275                         mode->vsync_start = output_mode->vsync_start;
 276                         mode->vsync_end = output_mode->vsync_end;
 277                 }
 278
 279                 mode->type |= DRM_MODE_TYPE_DRIVER;
 280                 drm_mode_probed_add(connector, mode);
 281                 n++;
 282         }
 283         return n;
 284 }
 285
 286 static int nv17_tv_mode_valid(struct drm_encoder *encoder,
 287                               struct drm_display_mode *mode)
 288 {
 289         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 290
 291         if (tv_norm->kind == CTV_ENC_MODE) {
 292                 struct drm_display_mode *output_mode =
 293                                                 &tv_norm->ctv_enc_mode.mode;
 294
 295                 if (mode->clock > 400000)
 296                         return MODE_CLOCK_HIGH;
 297
 298                 if (mode->hdisplay > output_mode->hdisplay ||
 299                     mode->vdisplay > output_mode->vdisplay)
 300                         return MODE_BAD;
 301
 302                 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) !=
 303                     (output_mode->flags & DRM_MODE_FLAG_INTERLACE))
 304                         return MODE_NO_INTERLACE;
 305
 306                 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 307                         return MODE_NO_DBLESCAN;
 308
 309         } else {
 310                 const int vsync_tolerance = 600;
 311
 312                 if (mode->clock > 70000)
 313                         return MODE_CLOCK_HIGH;
 314
 315                 if (abs(drm_mode_vrefresh(mode) * 1000 -
 316                         tv_norm->tv_enc_mode.vrefresh) > vsync_tolerance)
 317                         return MODE_VSYNC;
 318
 319                 /* The encoder takes care of the actual interlacing */
 320                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 321                         return MODE_NO_INTERLACE;
 322         }
 323
 324         return MODE_OK;
 325 }
 326
 327 static bool nv17_tv_mode_fixup(struct drm_encoder *encoder,
 328                                struct drm_display_mode *mode,
 329                                struct drm_display_mode *adjusted_mode)
 330 {
 331         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 332
 333         if (nv04_dac_in_use(encoder))
 334                 return false;
 335
 336         if (tv_norm->kind == CTV_ENC_MODE)
 337                 adjusted_mode->clock = tv_norm->ctv_enc_mode.mode.clock;
 338         else
 339                 adjusted_mode->clock = 90000;
 340
 341         return true;
 342 }
 343
 344 static void  nv17_tv_dpms(struct drm_encoder *encoder, int mode)
 345 {
 346         struct drm_device *dev = encoder->dev;
 347         struct drm_nouveau_private *dev_priv = dev->dev_private;
 348         struct nouveau_gpio_engine *gpio = &dev_priv->engine.gpio;
 349         struct nv17_tv_state *regs = &to_tv_enc(encoder)->state;
 350         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 351
 352         if (nouveau_encoder(encoder)->last_dpms == mode)
 353                 return;
 354         nouveau_encoder(encoder)->last_dpms = mode;
 355
 356         NV_INFO(dev, "Setting dpms mode %d on TV encoder (output %d)\n",
 357                  mode, nouveau_encoder(encoder)->dcb->index);
 358
 359         regs->ptv_200 &= ~1;
 360
 361         if (tv_norm->kind == CTV_ENC_MODE) {
 362                 nv04_dfp_update_fp_control(encoder, mode);
 363
 364         } else {
 365                 nv04_dfp_update_fp_control(encoder, DRM_MODE_DPMS_OFF);
 366
 367                 if (mode == DRM_MODE_DPMS_ON)
 368                         regs->ptv_200 |= 1;
 369         }
 370
 371         nv_load_ptv(dev, regs, 200);
 372
 373         gpio->set(dev, DCB_GPIO_TVDAC1, mode == DRM_MODE_DPMS_ON);
 374         gpio->set(dev, DCB_GPIO_TVDAC0, mode == DRM_MODE_DPMS_ON);
 375
 376         nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON);
 377 }
 378
 379 static void nv17_tv_prepare(struct drm_encoder *encoder)
 380 {
 381         struct drm_device *dev = encoder->dev;
 382         struct drm_nouveau_private *dev_priv = dev->dev_private;
 383         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 384         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 385         int head = nouveau_crtc(encoder->crtc)->index;
 386         uint8_t *cr_lcd = &dev_priv->mode_reg.crtc_reg[head].CRTC[
 387                                                         NV_CIO_CRE_LCD__INDEX];
 388         uint32_t dacclk_off = NV_PRAMDAC_DACCLK +
 389                                         nv04_dac_output_offset(encoder);
 390         uint32_t dacclk;
 391
 392         helper->dpms(encoder, DRM_MODE_DPMS_OFF);
 393
 394         nv04_dfp_disable(dev, head);
 395
 396         /* Unbind any FP encoders from this head if we need the FP
 397          * stuff enabled. */
 398         if (tv_norm->kind == CTV_ENC_MODE) {
 399                 struct drm_encoder *enc;
 400
 401                 list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
 402                         struct dcb_entry *dcb = nouveau_encoder(enc)->dcb;
 403
 404                         if ((dcb->type == OUTPUT_TMDS ||
 405                              dcb->type == OUTPUT_LVDS) &&
 406                              !enc->crtc &&
 407                              nv04_dfp_get_bound_head(dev, dcb) == head) {
 408                                 nv04_dfp_bind_head(dev, dcb, head ^ 1,
 409                                                 dev_priv->vbios.fp.dual_link);
 410                         }
 411                 }
 412
 413         }
 414
 415         /* Some NV4x have unknown values (0x3f, 0x50, 0x54, 0x6b, 0x79, 0x7f)
 416          * at LCD__INDEX which we don't alter
 417          */
 418         if (!(*cr_lcd & 0x44)) {
 419                 if (tv_norm->kind == CTV_ENC_MODE)
 420                         *cr_lcd = 0x1 | (head ? 0x0 : 0x8);
 421                 else
 422                         *cr_lcd = 0;
 423         }
 424
 425         /* Set the DACCLK register */
 426         dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
 427
 428         if (dev_priv->card_type == NV_40)
 429                 dacclk |= 0x1a << 16;
 430
 431         if (tv_norm->kind == CTV_ENC_MODE) {
 432                 dacclk |=  0x20;
 433
 434                 if (head)
 435                         dacclk |= 0x100;
 436                 else
 437                         dacclk &= ~0x100;
 438
 439         } else {
 440                 dacclk |= 0x10;
 441
 442         }
 443
 444         NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
 445 }
 446
 447 static void nv17_tv_mode_set(struct drm_encoder *encoder,
 448                              struct drm_display_mode *drm_mode,
 449                              struct drm_display_mode *adjusted_mode)
 450 {
 451         struct drm_device *dev = encoder->dev;
 452         struct drm_nouveau_private *dev_priv = dev->dev_private;
 453         int head = nouveau_crtc(encoder->crtc)->index;
 454         struct nv04_crtc_reg *regs = &dev_priv->mode_reg.crtc_reg[head];
 455         struct nv17_tv_state *tv_regs = &to_tv_enc(encoder)->state;
 456         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 457         int i;
 458
 459         regs->CRTC[NV_CIO_CRE_53] = 0x40; /* FP_HTIMING */
 460         regs->CRTC[NV_CIO_CRE_54] = 0; /* FP_VTIMING */
 461         regs->ramdac_630 = 0x2; /* turn off green mode (tv test pattern?) */
 462         regs->tv_setup = 1;
 463         regs->ramdac_8c0 = 0x0;
 464
 465         if (tv_norm->kind == TV_ENC_MODE) {
 466                 tv_regs->ptv_200 = 0x13111100;
 467                 if (head)
 468                         tv_regs->ptv_200 |= 0x10;
 469
 470                 tv_regs->ptv_20c = 0x808010;
 471                 tv_regs->ptv_304 = 0x2d00000;
 472                 tv_regs->ptv_600 = 0x0;
 473                 tv_regs->ptv_60c = 0x0;
 474                 tv_regs->ptv_610 = 0x1e00000;
 475
 476                 if (tv_norm->tv_enc_mode.vdisplay == 576) {
 477                         tv_regs->ptv_508 = 0x1200000;
 478                         tv_regs->ptv_614 = 0x33;
 479
 480                 } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 481                         tv_regs->ptv_508 = 0xf00000;
 482                         tv_regs->ptv_614 = 0x13;
 483                 }
 484
 485                 if (dev_priv->card_type >= NV_30) {
 486                         tv_regs->ptv_500 = 0xe8e0;
 487                         tv_regs->ptv_504 = 0x1710;
 488                         tv_regs->ptv_604 = 0x0;
 489                         tv_regs->ptv_608 = 0x0;
 490                 } else {
 491                         if (tv_norm->tv_enc_mode.vdisplay == 576) {
 492                                 tv_regs->ptv_604 = 0x20;
 493                                 tv_regs->ptv_608 = 0x10;
 494                                 tv_regs->ptv_500 = 0x19710;
 495                                 tv_regs->ptv_504 = 0x68f0;
 496
 497                         } else if (tv_norm->tv_enc_mode.vdisplay == 480) {
 498                                 tv_regs->ptv_604 = 0x10;
 499                                 tv_regs->ptv_608 = 0x20;
 500                                 tv_regs->ptv_500 = 0x4b90;
 501                                 tv_regs->ptv_504 = 0x1b480;
 502                         }
 503                 }
 504
 505                 for (i = 0; i < 0x40; i++)
 506                         tv_regs->tv_enc[i] = tv_norm->tv_enc_mode.tv_enc[i];
 507
 508         } else {
 509                 struct drm_display_mode *output_mode =
 510                                                 &tv_norm->ctv_enc_mode.mode;
 511
 512                 /* The registers in PRAMDAC+0xc00 control some timings and CSC
 513                  * parameters for the CTV encoder (It's only used for "HD" TV
 514                  * modes, I don't think I have enough working to guess what
 515                  * they exactly mean...), it's probably connected at the
 516                  * output of the FP encoder, but it also needs the analog
 517                  * encoder in its OR enabled and routed to the head it's
 518                  * using. It's enabled with the DACCLK register, bits [5:4].
 519                  */
 520                 for (i = 0; i < 38; i++)
 521                         regs->ctv_regs[i] = tv_norm->ctv_enc_mode.ctv_regs[i];
 522
 523                 regs->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1;
 524                 regs->fp_horiz_regs[FP_TOTAL] = output_mode->htotal - 1;
 525                 regs->fp_horiz_regs[FP_SYNC_START] =
 526                                                 output_mode->hsync_start - 1;
 527                 regs->fp_horiz_regs[FP_SYNC_END] = output_mode->hsync_end - 1;
 528                 regs->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay +
 529                         max((output_mode->hdisplay-600)/40 - 1, 1);
 530
 531                 regs->fp_vert_regs[FP_DISPLAY_END] = output_mode->vdisplay - 1;
 532                 regs->fp_vert_regs[FP_TOTAL] = output_mode->vtotal - 1;
 533                 regs->fp_vert_regs[FP_SYNC_START] =
 534                                                 output_mode->vsync_start - 1;
 535                 regs->fp_vert_regs[FP_SYNC_END] = output_mode->vsync_end - 1;
 536                 regs->fp_vert_regs[FP_CRTC] = output_mode->vdisplay - 1;
 537
 538                 regs->fp_control = NV_PRAMDAC_FP_TG_CONTROL_DISPEN_POS |
 539                         NV_PRAMDAC_FP_TG_CONTROL_READ_PROG |
 540                         NV_PRAMDAC_FP_TG_CONTROL_WIDTH_12;
 541
 542                 if (output_mode->flags & DRM_MODE_FLAG_PVSYNC)
 543                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_VSYNC_POS;
 544                 if (output_mode->flags & DRM_MODE_FLAG_PHSYNC)
 545                         regs->fp_control |= NV_PRAMDAC_FP_TG_CONTROL_HSYNC_POS;
 546
 547                 regs->fp_debug_0 = NV_PRAMDAC_FP_DEBUG_0_YWEIGHT_ROUND |
 548                         NV_PRAMDAC_FP_DEBUG_0_XWEIGHT_ROUND |
 549                         NV_PRAMDAC_FP_DEBUG_0_YINTERP_BILINEAR |
 550                         NV_PRAMDAC_FP_DEBUG_0_XINTERP_BILINEAR |
 551                         NV_RAMDAC_FP_DEBUG_0_TMDS_ENABLED |
 552                         NV_PRAMDAC_FP_DEBUG_0_YSCALE_ENABLE |
 553                         NV_PRAMDAC_FP_DEBUG_0_XSCALE_ENABLE;
 554
 555                 regs->fp_debug_2 = 0;
 556
 557                 regs->fp_margin_color = 0x801080;
 558
 559         }
 560 }
 561
 562 static void nv17_tv_commit(struct drm_encoder *encoder)
 563 {
 564         struct drm_device *dev = encoder->dev;
 565         struct drm_nouveau_private *dev_priv = dev->dev_private;
 566         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 567         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 568         struct drm_encoder_helper_funcs *helper = encoder->helper_private;
 569
 570         if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
 571                 nv17_tv_update_rescaler(encoder);
 572                 nv17_tv_update_properties(encoder);
 573         } else {
 574                 nv17_ctv_update_rescaler(encoder);
 575         }
 576
 577         nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
 578
 579         /* This could use refinement for flatpanels, but it should work */
 580         if (dev_priv->chipset < 0x44)
 581                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 582                                         nv04_dac_output_offset(encoder),
 583                                         0xf0000000);
 584         else
 585                 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL +
 586                                         nv04_dac_output_offset(encoder),
 587                                         0x00100000);
 588
 589         helper->dpms(encoder, DRM_MODE_DPMS_ON);
 590
 591         NV_INFO(dev, "Output %s is running on CRTC %d using output %c\n",
 592                 drm_get_connector_name(
 593                         &nouveau_encoder_connector_get(nv_encoder)->base),
 594                 nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 595 }
 596
 597 static void nv17_tv_save(struct drm_encoder *encoder)
 598 {
 599         struct drm_device *dev = encoder->dev;
 600         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 601
 602         nouveau_encoder(encoder)->restore.output =
 603                                         NVReadRAMDAC(dev, 0,
 604                                         NV_PRAMDAC_DACCLK +
 605                                         nv04_dac_output_offset(encoder));
 606
 607         nv17_tv_state_save(dev, &tv_enc->saved_state);
 608
 609         tv_enc->state.ptv_200 = tv_enc->saved_state.ptv_200;
 610 }
 611
 612 static void nv17_tv_restore(struct drm_encoder *encoder)
 613 {
 614         struct drm_device *dev = encoder->dev;
 615
 616         NVWriteRAMDAC(dev, 0, NV_PRAMDAC_DACCLK +
 617                                 nv04_dac_output_offset(encoder),
 618                                 nouveau_encoder(encoder)->restore.output);
 619
 620         nv17_tv_state_load(dev, &to_tv_enc(encoder)->saved_state);
 621
 622         nouveau_encoder(encoder)->last_dpms = NV_DPMS_CLEARED;
 623 }
 624
 625 static int nv17_tv_create_resources(struct drm_encoder *encoder,
 626                                     struct drm_connector *connector)
 627 {
 628         struct drm_device *dev = encoder->dev;
 629         struct drm_mode_config *conf = &dev->mode_config;
 630         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 631         struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb;
 632         int num_tv_norms = dcb->tvconf.has_component_output ? NUM_TV_NORMS :
 633                                                         NUM_LD_TV_NORMS;
 634         int i;
 635
 636         if (nouveau_tv_norm) {
 637                 for (i = 0; i < num_tv_norms; i++) {
 638                         if (!strcmp(nv17_tv_norm_names[i], nouveau_tv_norm)) {
 639                                 tv_enc->tv_norm = i;
 640                                 break;
 641                         }
 642                 }
 643
 644                 if (i == num_tv_norms)
 645                         NV_WARN(dev, "Invalid TV norm setting \"%s\"\n",
 646                                 nouveau_tv_norm);
 647         }
 648
 649         drm_mode_create_tv_properties(dev, num_tv_norms, nv17_tv_norm_names);
 650
 651         drm_connector_attach_property(connector,
 652                                         conf->tv_select_subconnector_property,
 653                                         tv_enc->select_subconnector);
 654         drm_connector_attach_property(connector,
 655                                         conf->tv_subconnector_property,
 656                                         tv_enc->subconnector);
 657         drm_connector_attach_property(connector,
 658                                         conf->tv_mode_property,
 659                                         tv_enc->tv_norm);
 660         drm_connector_attach_property(connector,
 661                                         conf->tv_flicker_reduction_property,
 662                                         tv_enc->flicker);
 663         drm_connector_attach_property(connector,
 664                                         conf->tv_saturation_property,
 665                                         tv_enc->saturation);
 666         drm_connector_attach_property(connector,
 667                                         conf->tv_hue_property,
 668                                         tv_enc->hue);
 669         drm_connector_attach_property(connector,
 670                                         conf->tv_overscan_property,
 671                                         tv_enc->overscan);
 672
 673         return 0;
 674 }
 675
 676 static int nv17_tv_set_property(struct drm_encoder *encoder,
 677                                 struct drm_connector *connector,
 678                                 struct drm_property *property,
 679                                 uint64_t val)
 680 {
 681         struct drm_mode_config *conf = &encoder->dev->mode_config;
 682         struct drm_crtc *crtc = encoder->crtc;
 683         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 684         struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
 685         bool modes_changed = false;
 686
 687         if (property == conf->tv_overscan_property) {
 688                 tv_enc->overscan = val;
 689                 if (encoder->crtc) {
 690                         if (tv_norm->kind == CTV_ENC_MODE)
 691                                 nv17_ctv_update_rescaler(encoder);
 692                         else
 693                                 nv17_tv_update_rescaler(encoder);
 694                 }
 695
 696         } else if (property == conf->tv_saturation_property) {
 697                 if (tv_norm->kind != TV_ENC_MODE)
 698                         return -EINVAL;
 699
 700                 tv_enc->saturation = val;
 701                 nv17_tv_update_properties(encoder);
 702
 703         } else if (property == conf->tv_hue_property) {
 704                 if (tv_norm->kind != TV_ENC_MODE)
 705                         return -EINVAL;
 706
 707                 tv_enc->hue = val;
 708                 nv17_tv_update_properties(encoder);
 709
 710         } else if (property == conf->tv_flicker_reduction_property) {
 711                 if (tv_norm->kind != TV_ENC_MODE)
 712                         return -EINVAL;
 713
 714                 tv_enc->flicker = val;
 715                 if (encoder->crtc)
 716                         nv17_tv_update_rescaler(encoder);
 717
 718         } else if (property == conf->tv_mode_property) {
 719                 if (connector->dpms != DRM_MODE_DPMS_OFF)
 720                         return -EINVAL;
 721
 722                 tv_enc->tv_norm = val;
 723
 724                 modes_changed = true;
 725
 726         } else if (property == conf->tv_select_subconnector_property) {
 727                 if (tv_norm->kind != TV_ENC_MODE)
 728                         return -EINVAL;
 729
 730                 tv_enc->select_subconnector = val;
 731                 nv17_tv_update_properties(encoder);
 732
 733         } else {
 734                 return -EINVAL;
 735         }
 736
 737         if (modes_changed) {
 738                 drm_helper_probe_single_connector_modes(connector, 0, 0);
 739
 740                 /* Disable the crtc to ensure a full modeset is
 741                  * performed whenever it's turned on again. */
 742                 if (crtc) {
 743                         struct drm_mode_set modeset = {
 744                                 .crtc = crtc,
 745                         };
 746
 747                         crtc->funcs->set_config(&modeset);
 748                 }
 749         }
 750
 751         return 0;
 752 }
 753
 754 static void nv17_tv_destroy(struct drm_encoder *encoder)
 755 {
 756         struct nv17_tv_encoder *tv_enc = to_tv_enc(encoder);
 757
 758         NV_DEBUG_KMS(encoder->dev, "\n");
 759
 760         drm_encoder_cleanup(encoder);
 761         kfree(tv_enc);
 762 }
 763
 764 static struct drm_encoder_helper_funcs nv17_tv_helper_funcs = {
 765         .dpms = nv17_tv_dpms,
 766         .save = nv17_tv_save,
 767         .restore = nv17_tv_restore,
 768         .mode_fixup = nv17_tv_mode_fixup,
 769         .prepare = nv17_tv_prepare,
 770         .commit = nv17_tv_commit,
 771         .mode_set = nv17_tv_mode_set,
 772         .detect = nv17_tv_detect,
 773 };
 774
 775 static struct drm_encoder_slave_funcs nv17_tv_slave_funcs = {
 776         .get_modes = nv17_tv_get_modes,
 777         .mode_valid = nv17_tv_mode_valid,
 778         .create_resources = nv17_tv_create_resources,
 779         .set_property = nv17_tv_set_property,
 780 };
 781
 782 static struct drm_encoder_funcs nv17_tv_funcs = {
 783         .destroy = nv17_tv_destroy,
 784 };
 785
 786 int
 787 nv17_tv_create(struct drm_connector *connector, struct dcb_entry *entry)
 788 {
 789         struct drm_device *dev = connector->dev;
 790         struct drm_encoder *encoder;
 791         struct nv17_tv_encoder *tv_enc = NULL;
 792
 793         tv_enc = kzalloc(sizeof(*tv_enc), GFP_KERNEL);
 794         if (!tv_enc)
 795                 return -ENOMEM;
 796
 797         tv_enc->overscan = 50;
 798         tv_enc->flicker = 50;
 799         tv_enc->saturation = 50;
 800         tv_enc->hue = 0;
 801         tv_enc->tv_norm = TV_NORM_PAL;
 802         tv_enc->subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
 803         tv_enc->select_subconnector = DRM_MODE_SUBCONNECTOR_Automatic;
 804         tv_enc->pin_mask = 0;
 805
 806         encoder = to_drm_encoder(&tv_enc->base);
 807
 808         tv_enc->base.dcb = entry;
 809         tv_enc->base.or = ffs(entry->or) - 1;
 810
 811         drm_encoder_init(dev, encoder, &nv17_tv_funcs, DRM_MODE_ENCODER_TVDAC);
 812         drm_encoder_helper_add(encoder, &nv17_tv_helper_funcs);
 813         to_encoder_slave(encoder)->slave_funcs = &nv17_tv_slave_funcs;
 814
 815         encoder->possible_crtcs = entry->heads;
 816         encoder->possible_clones = 0;
 817
 818         nv17_tv_create_resources(encoder, connector);
 819         drm_mode_connector_attach_encoder(connector, encoder);
 820         return 0;
 821 }