drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
  46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
  47
  48 struct intel_dp {
  49         struct intel_encoder base;
  50         uint32_t output_reg;
  51         uint32_t DP;
  52         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  53         bool has_audio;
  54         int dpms_mode;
  55         uint8_t link_bw;
  56         uint8_t lane_count;
  57         uint8_t dpcd[4];
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         bool is_pch_edp;
  61 };
  62
  63 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
  64 {
  65         return container_of(enc_to_intel_encoder(encoder), struct intel_dp, base);
  66 }
  67
  68 static void intel_dp_link_train(struct intel_dp *intel_dp);
  69 static void intel_dp_link_down(struct intel_dp *intel_dp);
  70
  71 void
  72 intel_edp_link_config (struct intel_encoder *intel_encoder,
  73                        int *lane_num, int *link_bw)
  74 {
  75         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
  76
  77         *lane_num = intel_dp->lane_count;
  78         if (intel_dp->link_bw == DP_LINK_BW_1_62)
  79                 *link_bw = 162000;
  80         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
  81                 *link_bw = 270000;
  82 }
  83
  84 static int
  85 intel_dp_max_lane_count(struct intel_dp *intel_dp)
  86 {
  87         int max_lane_count = 4;
  88
  89         if (intel_dp->dpcd[0] >= 0x11) {
  90                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
  91                 switch (max_lane_count) {
  92                 case 1: case 2: case 4:
  93                         break;
  94                 default:
  95                         max_lane_count = 4;
  96                 }
  97         }
  98         return max_lane_count;
  99 }
 100
 101 static int
 102 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 103 {
 104         int max_link_bw = intel_dp->dpcd[1];
 105
 106         switch (max_link_bw) {
 107         case DP_LINK_BW_1_62:
 108         case DP_LINK_BW_2_7:
 109                 break;
 110         default:
 111                 max_link_bw = DP_LINK_BW_1_62;
 112                 break;
 113         }
 114         return max_link_bw;
 115 }
 116
 117 static int
 118 intel_dp_link_clock(uint8_t link_bw)
 119 {
 120         if (link_bw == DP_LINK_BW_2_7)
 121                 return 270000;
 122         else
 123                 return 162000;
 124 }
 125
 126 /* I think this is a fiction */
 127 static int
 128 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
 129 {
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131
 132         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 133                 return (pixel_clock * dev_priv->edp_bpp) / 8;
 134         else
 135                 return pixel_clock * 3;
 136 }
 137
 138 static int
 139 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 140 {
 141         return (max_link_clock * max_lanes * 8) / 10;
 142 }
 143
 144 static int
 145 intel_dp_mode_valid(struct drm_connector *connector,
 146                     struct drm_display_mode *mode)
 147 {
 148         struct drm_encoder *encoder = intel_attached_encoder(connector);
 149         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 150         struct drm_device *dev = connector->dev;
 151         struct drm_i915_private *dev_priv = dev->dev_private;
 152         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 153         int max_lanes = intel_dp_max_lane_count(intel_dp);
 154
 155         if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
 156             dev_priv->panel_fixed_mode) {
 157                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 158                         return MODE_PANEL;
 159
 160                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 161                         return MODE_PANEL;
 162         }
 163
 164         /* only refuse the mode on non eDP since we have seen some wierd eDP panels
 165            which are outside spec tolerances but somehow work by magic */
 166         if (!IS_eDP(intel_dp) &&
 167             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
 168              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
 169                 return MODE_CLOCK_HIGH;
 170
 171         if (mode->clock < 10000)
 172                 return MODE_CLOCK_LOW;
 173
 174         return MODE_OK;
 175 }
 176
 177 static uint32_t
 178 pack_aux(uint8_t *src, int src_bytes)
 179 {
 180         int     i;
 181         uint32_t v = 0;
 182
 183         if (src_bytes > 4)
 184                 src_bytes = 4;
 185         for (i = 0; i < src_bytes; i++)
 186                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 187         return v;
 188 }
 189
 190 static void
 191 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 192 {
 193         int i;
 194         if (dst_bytes > 4)
 195                 dst_bytes = 4;
 196         for (i = 0; i < dst_bytes; i++)
 197                 dst[i] = src >> ((3-i) * 8);
 198 }
 199
 200 /* hrawclock is 1/4 the FSB frequency */
 201 static int
 202 intel_hrawclk(struct drm_device *dev)
 203 {
 204         struct drm_i915_private *dev_priv = dev->dev_private;
 205         uint32_t clkcfg;
 206
 207         clkcfg = I915_READ(CLKCFG);
 208         switch (clkcfg & CLKCFG_FSB_MASK) {
 209         case CLKCFG_FSB_400:
 210                 return 100;
 211         case CLKCFG_FSB_533:
 212                 return 133;
 213         case CLKCFG_FSB_667:
 214                 return 166;
 215         case CLKCFG_FSB_800:
 216                 return 200;
 217         case CLKCFG_FSB_1067:
 218                 return 266;
 219         case CLKCFG_FSB_1333:
 220                 return 333;
 221         /* these two are just a guess; one of them might be right */
 222         case CLKCFG_FSB_1600:
 223         case CLKCFG_FSB_1600_ALT:
 224                 return 400;
 225         default:
 226                 return 133;
 227         }
 228 }
 229
 230 static int
 231 intel_dp_aux_ch(struct intel_dp *intel_dp,
 232                 uint8_t *send, int send_bytes,
 233                 uint8_t *recv, int recv_size)
 234 {
 235         uint32_t output_reg = intel_dp->output_reg;
 236         struct drm_device *dev = intel_dp->base.enc.dev;
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         uint32_t ch_ctl = output_reg + 0x10;
 239         uint32_t ch_data = ch_ctl + 4;
 240         int i;
 241         int recv_bytes;
 242         uint32_t ctl;
 243         uint32_t status;
 244         uint32_t aux_clock_divider;
 245         int try, precharge;
 246
 247         /* The clock divider is based off the hrawclk,
 248          * and would like to run at 2MHz. So, take the
 249          * hrawclk value and divide by 2 and use that
 250          */
 251         if (IS_eDP(intel_dp)) {
 252                 if (IS_GEN6(dev))
 253                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
 254                 else
 255                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 256         } else if (HAS_PCH_SPLIT(dev))
 257                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
 258         else
 259                 aux_clock_divider = intel_hrawclk(dev) / 2;
 260
 261         if (IS_GEN6(dev))
 262                 precharge = 3;
 263         else
 264                 precharge = 5;
 265
 266         /* Must try at least 3 times according to DP spec */
 267         for (try = 0; try < 5; try++) {
 268                 /* Load the send data into the aux channel data registers */
 269                 for (i = 0; i < send_bytes; i += 4) {
 270                         uint32_t    d = pack_aux(send + i, send_bytes - i);
 271
 272                         I915_WRITE(ch_data + i, d);
 273                 }
 274
 275                 ctl = (DP_AUX_CH_CTL_SEND_BUSY |
 276                        DP_AUX_CH_CTL_TIME_OUT_400us |
 277                        (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 278                        (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 279                        (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 280                        DP_AUX_CH_CTL_DONE |
 281                        DP_AUX_CH_CTL_TIME_OUT_ERROR |
 282                        DP_AUX_CH_CTL_RECEIVE_ERROR);
 283
 284                 /* Send the command and wait for it to complete */
 285                 I915_WRITE(ch_ctl, ctl);
 286                 (void) I915_READ(ch_ctl);
 287                 for (;;) {
 288                         udelay(100);
 289                         status = I915_READ(ch_ctl);
 290                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 291                                 break;
 292                 }
 293
 294                 /* Clear done status and any errors */
 295                 I915_WRITE(ch_ctl, (status |
 296                                 DP_AUX_CH_CTL_DONE |
 297                                 DP_AUX_CH_CTL_TIME_OUT_ERROR |
 298                                 DP_AUX_CH_CTL_RECEIVE_ERROR));
 299                 (void) I915_READ(ch_ctl);
 300                 if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
 301                         break;
 302         }
 303
 304         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 305                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 306                 return -EBUSY;
 307         }
 308
 309         /* Check for timeout or receive error.
 310          * Timeouts occur when the sink is not connected
 311          */
 312         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 313                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 314                 return -EIO;
 315         }
 316
 317         /* Timeouts occur when the device isn't connected, so they're
 318          * "normal" -- don't fill the kernel log with these */
 319         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 320                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 321                 return -ETIMEDOUT;
 322         }
 323
 324         /* Unload any bytes sent back from the other side */
 325         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 326                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 327
 328         if (recv_bytes > recv_size)
 329                 recv_bytes = recv_size;
 330
 331         for (i = 0; i < recv_bytes; i += 4) {
 332                 uint32_t    d = I915_READ(ch_data + i);
 333
 334                 unpack_aux(d, recv + i, recv_bytes - i);
 335         }
 336
 337         return recv_bytes;
 338 }
 339
 340 /* Write data to the aux channel in native mode */
 341 static int
 342 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 343                           uint16_t address, uint8_t *send, int send_bytes)
 344 {
 345         int ret;
 346         uint8_t msg[20];
 347         int msg_bytes;
 348         uint8_t ack;
 349
 350         if (send_bytes > 16)
 351                 return -1;
 352         msg[0] = AUX_NATIVE_WRITE << 4;
 353         msg[1] = address >> 8;
 354         msg[2] = address & 0xff;
 355         msg[3] = send_bytes - 1;
 356         memcpy(&msg[4], send, send_bytes);
 357         msg_bytes = send_bytes + 4;
 358         for (;;) {
 359                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 360                 if (ret < 0)
 361                         return ret;
 362                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 363                         break;
 364                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 365                         udelay(100);
 366                 else
 367                         return -EIO;
 368         }
 369         return send_bytes;
 370 }
 371
 372 /* Write a single byte to the aux channel in native mode */
 373 static int
 374 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 375                             uint16_t address, uint8_t byte)
 376 {
 377         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 378 }
 379
 380 /* read bytes from a native aux channel */
 381 static int
 382 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 383                          uint16_t address, uint8_t *recv, int recv_bytes)
 384 {
 385         uint8_t msg[4];
 386         int msg_bytes;
 387         uint8_t reply[20];
 388         int reply_bytes;
 389         uint8_t ack;
 390         int ret;
 391
 392         msg[0] = AUX_NATIVE_READ << 4;
 393         msg[1] = address >> 8;
 394         msg[2] = address & 0xff;
 395         msg[3] = recv_bytes - 1;
 396
 397         msg_bytes = 4;
 398         reply_bytes = recv_bytes + 1;
 399
 400         for (;;) {
 401                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 402                                       reply, reply_bytes);
 403                 if (ret == 0)
 404                         return -EPROTO;
 405                 if (ret < 0)
 406                         return ret;
 407                 ack = reply[0];
 408                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 409                         memcpy(recv, reply + 1, ret - 1);
 410                         return ret - 1;
 411                 }
 412                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 413                         udelay(100);
 414                 else
 415                         return -EIO;
 416         }
 417 }
 418
 419 static int
 420 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 421                     uint8_t write_byte, uint8_t *read_byte)
 422 {
 423         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 424         struct intel_dp *intel_dp = container_of(adapter,
 425                                                 struct intel_dp,
 426                                                 adapter);
 427         uint16_t address = algo_data->address;
 428         uint8_t msg[5];
 429         uint8_t reply[2];
 430         int msg_bytes;
 431         int reply_bytes;
 432         int ret;
 433
 434         /* Set up the command byte */
 435         if (mode & MODE_I2C_READ)
 436                 msg[0] = AUX_I2C_READ << 4;
 437         else
 438                 msg[0] = AUX_I2C_WRITE << 4;
 439
 440         if (!(mode & MODE_I2C_STOP))
 441                 msg[0] |= AUX_I2C_MOT << 4;
 442
 443         msg[1] = address >> 8;
 444         msg[2] = address;
 445
 446         switch (mode) {
 447         case MODE_I2C_WRITE:
 448                 msg[3] = 0;
 449                 msg[4] = write_byte;
 450                 msg_bytes = 5;
 451                 reply_bytes = 1;
 452                 break;
 453         case MODE_I2C_READ:
 454                 msg[3] = 0;
 455                 msg_bytes = 4;
 456                 reply_bytes = 2;
 457                 break;
 458         default:
 459                 msg_bytes = 3;
 460                 reply_bytes = 1;
 461                 break;
 462         }
 463
 464         for (;;) {
 465           ret = intel_dp_aux_ch(intel_dp,
 466                                 msg, msg_bytes,
 467                                 reply, reply_bytes);
 468                 if (ret < 0) {
 469                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 470                         return ret;
 471                 }
 472                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 473                 case AUX_I2C_REPLY_ACK:
 474                         if (mode == MODE_I2C_READ) {
 475                                 *read_byte = reply[1];
 476                         }
 477                         return reply_bytes - 1;
 478                 case AUX_I2C_REPLY_NACK:
 479                         DRM_DEBUG_KMS("aux_ch nack\n");
 480                         return -EREMOTEIO;
 481                 case AUX_I2C_REPLY_DEFER:
 482                         DRM_DEBUG_KMS("aux_ch defer\n");
 483                         udelay(100);
 484                         break;
 485                 default:
 486                         DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply[0]);
 487                         return -EREMOTEIO;
 488                 }
 489         }
 490 }
 491
 492 static int
 493 intel_dp_i2c_init(struct intel_dp *intel_dp,
 494                   struct intel_connector *intel_connector, const char *name)
 495 {
 496         DRM_DEBUG_KMS("i2c_init %s\n", name);
 497         intel_dp->algo.running = false;
 498         intel_dp->algo.address = 0;
 499         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 500
 501         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 502         intel_dp->adapter.owner = THIS_MODULE;
 503         intel_dp->adapter.class = I2C_CLASS_DDC;
 504         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 505         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 506         intel_dp->adapter.algo_data = &intel_dp->algo;
 507         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 508
 509         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 510 }
 511
 512 static bool
 513 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 514                     struct drm_display_mode *adjusted_mode)
 515 {
 516         struct drm_device *dev = encoder->dev;
 517         struct drm_i915_private *dev_priv = dev->dev_private;
 518         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 519         int lane_count, clock;
 520         int max_lane_count = intel_dp_max_lane_count(intel_dp);
 521         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 522         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 523
 524         if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
 525             dev_priv->panel_fixed_mode) {
 526                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
 527                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
 528                                         mode, adjusted_mode);
 529                 /*
 530                  * the mode->clock is used to calculate the Data&Link M/N
 531                  * of the pipe. For the eDP the fixed clock should be used.
 532                  */
 533                 mode->clock = dev_priv->panel_fixed_mode->clock;
 534         }
 535
 536         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 537                 for (clock = 0; clock <= max_clock; clock++) {
 538                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 539
 540                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
 541                                         <= link_avail) {
 542                                 intel_dp->link_bw = bws[clock];
 543                                 intel_dp->lane_count = lane_count;
 544                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 545                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 546                                                 "count %d clock %d\n",
 547                                        intel_dp->link_bw, intel_dp->lane_count,
 548                                        adjusted_mode->clock);
 549                                 return true;
 550                         }
 551                 }
 552         }
 553
 554         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
 555                 /* okay we failed just pick the highest */
 556                 intel_dp->lane_count = max_lane_count;
 557                 intel_dp->link_bw = bws[max_clock];
 558                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 559                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
 560                               "count %d clock %d\n",
 561                               intel_dp->link_bw, intel_dp->lane_count,
 562                               adjusted_mode->clock);
 563
 564                 return true;
 565         }
 566
 567         return false;
 568 }
 569
 570 struct intel_dp_m_n {
 571         uint32_t        tu;
 572         uint32_t        gmch_m;
 573         uint32_t        gmch_n;
 574         uint32_t        link_m;
 575         uint32_t        link_n;
 576 };
 577
 578 static void
 579 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 580 {
 581         while (*num > 0xffffff || *den > 0xffffff) {
 582                 *num >>= 1;
 583                 *den >>= 1;
 584         }
 585 }
 586
 587 static void
 588 intel_dp_compute_m_n(int bpp,
 589                      int nlanes,
 590                      int pixel_clock,
 591                      int link_clock,
 592                      struct intel_dp_m_n *m_n)
 593 {
 594         m_n->tu = 64;
 595         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 596         m_n->gmch_n = link_clock * nlanes;
 597         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 598         m_n->link_m = pixel_clock;
 599         m_n->link_n = link_clock;
 600         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 601 }
 602
 603 bool intel_pch_has_edp(struct drm_crtc *crtc)
 604 {
 605         struct drm_device *dev = crtc->dev;
 606         struct drm_mode_config *mode_config = &dev->mode_config;
 607         struct drm_encoder *encoder;
 608
 609         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 610                 struct intel_dp *intel_dp;
 611
 612                 if (encoder->crtc != crtc)
 613                         continue;
 614
 615                 intel_dp = enc_to_intel_dp(encoder);
 616                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
 617                         return intel_dp->is_pch_edp;
 618         }
 619         return false;
 620 }
 621
 622 void
 623 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 624                  struct drm_display_mode *adjusted_mode)
 625 {
 626         struct drm_device *dev = crtc->dev;
 627         struct drm_mode_config *mode_config = &dev->mode_config;
 628         struct drm_encoder *encoder;
 629         struct drm_i915_private *dev_priv = dev->dev_private;
 630         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 631         int lane_count = 4, bpp = 24;
 632         struct intel_dp_m_n m_n;
 633
 634         /*
 635          * Find the lane count in the intel_encoder private
 636          */
 637         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 638                 struct intel_dp *intel_dp;
 639
 640                 if (encoder->crtc != crtc)
 641                         continue;
 642
 643                 intel_dp = enc_to_intel_dp(encoder);
 644                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
 645                         lane_count = intel_dp->lane_count;
 646                         if (IS_PCH_eDP(intel_dp))
 647                                 bpp = dev_priv->edp_bpp;
 648                         break;
 649                 }
 650         }
 651
 652         /*
 653          * Compute the GMCH and Link ratios. The '3' here is
 654          * the number of bytes_per_pixel post-LUT, which we always
 655          * set up for 8-bits of R/G/B, or 3 bytes total.
 656          */
 657         intel_dp_compute_m_n(bpp, lane_count,
 658                              mode->clock, adjusted_mode->clock, &m_n);
 659
 660         if (HAS_PCH_SPLIT(dev)) {
 661                 if (intel_crtc->pipe == 0) {
 662                         I915_WRITE(TRANSA_DATA_M1,
 663                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 664                                    m_n.gmch_m);
 665                         I915_WRITE(TRANSA_DATA_N1, m_n.gmch_n);
 666                         I915_WRITE(TRANSA_DP_LINK_M1, m_n.link_m);
 667                         I915_WRITE(TRANSA_DP_LINK_N1, m_n.link_n);
 668                 } else {
 669                         I915_WRITE(TRANSB_DATA_M1,
 670                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 671                                    m_n.gmch_m);
 672                         I915_WRITE(TRANSB_DATA_N1, m_n.gmch_n);
 673                         I915_WRITE(TRANSB_DP_LINK_M1, m_n.link_m);
 674                         I915_WRITE(TRANSB_DP_LINK_N1, m_n.link_n);
 675                 }
 676         } else {
 677                 if (intel_crtc->pipe == 0) {
 678                         I915_WRITE(PIPEA_GMCH_DATA_M,
 679                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 680                                    m_n.gmch_m);
 681                         I915_WRITE(PIPEA_GMCH_DATA_N,
 682                                    m_n.gmch_n);
 683                         I915_WRITE(PIPEA_DP_LINK_M, m_n.link_m);
 684                         I915_WRITE(PIPEA_DP_LINK_N, m_n.link_n);
 685                 } else {
 686                         I915_WRITE(PIPEB_GMCH_DATA_M,
 687                                    ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 688                                    m_n.gmch_m);
 689                         I915_WRITE(PIPEB_GMCH_DATA_N,
 690                                         m_n.gmch_n);
 691                         I915_WRITE(PIPEB_DP_LINK_M, m_n.link_m);
 692                         I915_WRITE(PIPEB_DP_LINK_N, m_n.link_n);
 693                 }
 694         }
 695 }
 696
 697 static void
 698 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 699                   struct drm_display_mode *adjusted_mode)
 700 {
 701         struct drm_device *dev = encoder->dev;
 702         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 703         struct drm_crtc *crtc = intel_dp->base.enc.crtc;
 704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 705
 706         intel_dp->DP = (DP_VOLTAGE_0_4 |
 707                        DP_PRE_EMPHASIS_0);
 708
 709         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 710                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 711         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 712                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 713
 714         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
 715                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 716         else
 717                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 718
 719         switch (intel_dp->lane_count) {
 720         case 1:
 721                 intel_dp->DP |= DP_PORT_WIDTH_1;
 722                 break;
 723         case 2:
 724                 intel_dp->DP |= DP_PORT_WIDTH_2;
 725                 break;
 726         case 4:
 727                 intel_dp->DP |= DP_PORT_WIDTH_4;
 728                 break;
 729         }
 730         if (intel_dp->has_audio)
 731                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 732
 733         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 734         intel_dp->link_configuration[0] = intel_dp->link_bw;
 735         intel_dp->link_configuration[1] = intel_dp->lane_count;
 736
 737         /*
 738          * Check for DPCD version > 1.1 and enhanced framing support
 739          */
 740         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
 741                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 742                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 743         }
 744
 745         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 746         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
 747                 intel_dp->DP |= DP_PIPEB_SELECT;
 748
 749         if (IS_eDP(intel_dp)) {
 750                 /* don't miss out required setting for eDP */
 751                 intel_dp->DP |= DP_PLL_ENABLE;
 752                 if (adjusted_mode->clock < 200000)
 753                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 754                 else
 755                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 756         }
 757 }
 758
 759 static void ironlake_edp_panel_on (struct drm_device *dev)
 760 {
 761         struct drm_i915_private *dev_priv = dev->dev_private;
 762         u32 pp;
 763
 764         if (I915_READ(PCH_PP_STATUS) & PP_ON)
 765                 return;
 766
 767         pp = I915_READ(PCH_PP_CONTROL);
 768
 769         /* ILK workaround: disable reset around power sequence */
 770         pp &= ~PANEL_POWER_RESET;
 771         I915_WRITE(PCH_PP_CONTROL, pp);
 772         POSTING_READ(PCH_PP_CONTROL);
 773
 774         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
 775         I915_WRITE(PCH_PP_CONTROL, pp);
 776
 777         if (wait_for(I915_READ(PCH_PP_STATUS) & PP_ON, 5000, 10))
 778                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
 779                           I915_READ(PCH_PP_STATUS));
 780
 781         pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
 782         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
 783         I915_WRITE(PCH_PP_CONTROL, pp);
 784         POSTING_READ(PCH_PP_CONTROL);
 785 }
 786
 787 static void ironlake_edp_panel_off (struct drm_device *dev)
 788 {
 789         struct drm_i915_private *dev_priv = dev->dev_private;
 790         u32 pp;
 791
 792         pp = I915_READ(PCH_PP_CONTROL);
 793
 794         /* ILK workaround: disable reset around power sequence */
 795         pp &= ~PANEL_POWER_RESET;
 796         I915_WRITE(PCH_PP_CONTROL, pp);
 797         POSTING_READ(PCH_PP_CONTROL);
 798
 799         pp &= ~POWER_TARGET_ON;
 800         I915_WRITE(PCH_PP_CONTROL, pp);
 801
 802         if (wait_for((I915_READ(PCH_PP_STATUS) & PP_ON) == 0, 5000, 10))
 803                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
 804                           I915_READ(PCH_PP_STATUS));
 805
 806         /* Make sure VDD is enabled so DP AUX will work */
 807         pp |= EDP_FORCE_VDD | PANEL_POWER_RESET; /* restore panel reset bit */
 808         I915_WRITE(PCH_PP_CONTROL, pp);
 809         POSTING_READ(PCH_PP_CONTROL);
 810 }
 811
 812 static void ironlake_edp_backlight_on (struct drm_device *dev)
 813 {
 814         struct drm_i915_private *dev_priv = dev->dev_private;
 815         u32 pp;
 816
 817         DRM_DEBUG_KMS("\n");
 818         pp = I915_READ(PCH_PP_CONTROL);
 819         pp |= EDP_BLC_ENABLE;
 820         I915_WRITE(PCH_PP_CONTROL, pp);
 821 }
 822
 823 static void ironlake_edp_backlight_off (struct drm_device *dev)
 824 {
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         u32 pp;
 827
 828         DRM_DEBUG_KMS("\n");
 829         pp = I915_READ(PCH_PP_CONTROL);
 830         pp &= ~EDP_BLC_ENABLE;
 831         I915_WRITE(PCH_PP_CONTROL, pp);
 832 }
 833
 834 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
 835 {
 836         struct drm_device *dev = encoder->dev;
 837         struct drm_i915_private *dev_priv = dev->dev_private;
 838         u32 dpa_ctl;
 839
 840         DRM_DEBUG_KMS("\n");
 841         dpa_ctl = I915_READ(DP_A);
 842         dpa_ctl &= ~DP_PLL_ENABLE;
 843         I915_WRITE(DP_A, dpa_ctl);
 844 }
 845
 846 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
 847 {
 848         struct drm_device *dev = encoder->dev;
 849         struct drm_i915_private *dev_priv = dev->dev_private;
 850         u32 dpa_ctl;
 851
 852         dpa_ctl = I915_READ(DP_A);
 853         dpa_ctl |= DP_PLL_ENABLE;
 854         I915_WRITE(DP_A, dpa_ctl);
 855         udelay(200);
 856 }
 857
 858 static void intel_dp_prepare(struct drm_encoder *encoder)
 859 {
 860         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 861         struct drm_device *dev = encoder->dev;
 862         struct drm_i915_private *dev_priv = dev->dev_private;
 863         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 864
 865         if (IS_eDP(intel_dp)) {
 866                 ironlake_edp_backlight_off(dev);
 867                 ironlake_edp_panel_on(dev);
 868                 ironlake_edp_pll_on(encoder);
 869         }
 870         if (dp_reg & DP_PORT_EN)
 871                 intel_dp_link_down(intel_dp);
 872 }
 873
 874 static void intel_dp_commit(struct drm_encoder *encoder)
 875 {
 876         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 877         struct drm_device *dev = encoder->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 880
 881         if (!(dp_reg & DP_PORT_EN)) {
 882                 intel_dp_link_train(intel_dp);
 883         }
 884         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 885                 ironlake_edp_backlight_on(dev);
 886 }
 887
 888 static void
 889 intel_dp_dpms(struct drm_encoder *encoder, int mode)
 890 {
 891         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 892         struct drm_device *dev = encoder->dev;
 893         struct drm_i915_private *dev_priv = dev->dev_private;
 894         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
 895
 896         if (mode != DRM_MODE_DPMS_ON) {
 897                 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
 898                         ironlake_edp_backlight_off(dev);
 899                         ironlake_edp_panel_off(dev);
 900                 }
 901                 if (dp_reg & DP_PORT_EN)
 902                         intel_dp_link_down(intel_dp);
 903                 if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 904                         ironlake_edp_pll_off(encoder);
 905         } else {
 906                 if (!(dp_reg & DP_PORT_EN)) {
 907                         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 908                                 ironlake_edp_panel_on(dev);
 909                         intel_dp_link_train(intel_dp);
 910                         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp))
 911                                 ironlake_edp_backlight_on(dev);
 912                 }
 913         }
 914         intel_dp->dpms_mode = mode;
 915 }
 916
 917 /*
 918  * Fetch AUX CH registers 0x202 - 0x207 which contain
 919  * link status information
 920  */
 921 static bool
 922 intel_dp_get_link_status(struct intel_dp *intel_dp,
 923                          uint8_t link_status[DP_LINK_STATUS_SIZE])
 924 {
 925         int ret;
 926
 927         ret = intel_dp_aux_native_read(intel_dp,
 928                                        DP_LANE0_1_STATUS,
 929                                        link_status, DP_LINK_STATUS_SIZE);
 930         if (ret != DP_LINK_STATUS_SIZE)
 931                 return false;
 932         return true;
 933 }
 934
 935 static uint8_t
 936 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 937                      int r)
 938 {
 939         return link_status[r - DP_LANE0_1_STATUS];
 940 }
 941
 942 static uint8_t
 943 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 944                                  int lane)
 945 {
 946         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 947         int         s = ((lane & 1) ?
 948                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 949                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 950         uint8_t l = intel_dp_link_status(link_status, i);
 951
 952         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 953 }
 954
 955 static uint8_t
 956 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 957                                       int lane)
 958 {
 959         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 960         int         s = ((lane & 1) ?
 961                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 962                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 963         uint8_t l = intel_dp_link_status(link_status, i);
 964
 965         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 966 }
 967
 968
 969 #if 0
 970 static char     *voltage_names[] = {
 971         "0.4V", "0.6V", "0.8V", "1.2V"
 972 };
 973 static char     *pre_emph_names[] = {
 974         "0dB", "3.5dB", "6dB", "9.5dB"
 975 };
 976 static char     *link_train_names[] = {
 977         "pattern 1", "pattern 2", "idle", "off"
 978 };
 979 #endif
 980
 981 /*
 982  * These are source-specific values; current Intel hardware supports
 983  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 984  */
 985 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
 986
 987 static uint8_t
 988 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 989 {
 990         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 991         case DP_TRAIN_VOLTAGE_SWING_400:
 992                 return DP_TRAIN_PRE_EMPHASIS_6;
 993         case DP_TRAIN_VOLTAGE_SWING_600:
 994                 return DP_TRAIN_PRE_EMPHASIS_6;
 995         case DP_TRAIN_VOLTAGE_SWING_800:
 996                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 997         case DP_TRAIN_VOLTAGE_SWING_1200:
 998         default:
 999                 return DP_TRAIN_PRE_EMPHASIS_0;
1000         }
1001 }
1002
1003 static void
1004 intel_get_adjust_train(struct intel_dp *intel_dp,
1005                        uint8_t link_status[DP_LINK_STATUS_SIZE],
1006                        int lane_count,
1007                        uint8_t train_set[4])
1008 {
1009         uint8_t v = 0;
1010         uint8_t p = 0;
1011         int lane;
1012
1013         for (lane = 0; lane < lane_count; lane++) {
1014                 uint8_t this_v = intel_get_adjust_request_voltage(link_status, lane);
1015                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(link_status, lane);
1016
1017                 if (this_v > v)
1018                         v = this_v;
1019                 if (this_p > p)
1020                         p = this_p;
1021         }
1022
1023         if (v >= I830_DP_VOLTAGE_MAX)
1024                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1025
1026         if (p >= intel_dp_pre_emphasis_max(v))
1027                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1028
1029         for (lane = 0; lane < 4; lane++)
1030                 train_set[lane] = v | p;
1031 }
1032
1033 static uint32_t
1034 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1035 {
1036         uint32_t        signal_levels = 0;
1037
1038         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1039         case DP_TRAIN_VOLTAGE_SWING_400:
1040         default:
1041                 signal_levels |= DP_VOLTAGE_0_4;
1042                 break;
1043         case DP_TRAIN_VOLTAGE_SWING_600:
1044                 signal_levels |= DP_VOLTAGE_0_6;
1045                 break;
1046         case DP_TRAIN_VOLTAGE_SWING_800:
1047                 signal_levels |= DP_VOLTAGE_0_8;
1048                 break;
1049         case DP_TRAIN_VOLTAGE_SWING_1200:
1050                 signal_levels |= DP_VOLTAGE_1_2;
1051                 break;
1052         }
1053         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1054         case DP_TRAIN_PRE_EMPHASIS_0:
1055         default:
1056                 signal_levels |= DP_PRE_EMPHASIS_0;
1057                 break;
1058         case DP_TRAIN_PRE_EMPHASIS_3_5:
1059                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1060                 break;
1061         case DP_TRAIN_PRE_EMPHASIS_6:
1062                 signal_levels |= DP_PRE_EMPHASIS_6;
1063                 break;
1064         case DP_TRAIN_PRE_EMPHASIS_9_5:
1065                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1066                 break;
1067         }
1068         return signal_levels;
1069 }
1070
1071 /* Gen6's DP voltage swing and pre-emphasis control */
1072 static uint32_t
1073 intel_gen6_edp_signal_levels(uint8_t train_set)
1074 {
1075         switch (train_set & (DP_TRAIN_VOLTAGE_SWING_MASK|DP_TRAIN_PRE_EMPHASIS_MASK)) {
1076         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1077                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1078         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1079                 return EDP_LINK_TRAIN_400MV_6DB_SNB_B;
1080         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1081                 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B;
1082         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1083                 return EDP_LINK_TRAIN_800MV_0DB_SNB_B;
1084         default:
1085                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1086                 return EDP_LINK_TRAIN_400MV_0DB_SNB_B;
1087         }
1088 }
1089
1090 static uint8_t
1091 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1092                       int lane)
1093 {
1094         int i = DP_LANE0_1_STATUS + (lane >> 1);
1095         int s = (lane & 1) * 4;
1096         uint8_t l = intel_dp_link_status(link_status, i);
1097
1098         return (l >> s) & 0xf;
1099 }
1100
1101 /* Check for clock recovery is done on all channels */
1102 static bool
1103 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1104 {
1105         int lane;
1106         uint8_t lane_status;
1107
1108         for (lane = 0; lane < lane_count; lane++) {
1109                 lane_status = intel_get_lane_status(link_status, lane);
1110                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1111                         return false;
1112         }
1113         return true;
1114 }
1115
1116 /* Check to see if channel eq is done on all channels */
1117 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1118                          DP_LANE_CHANNEL_EQ_DONE|\
1119                          DP_LANE_SYMBOL_LOCKED)
1120 static bool
1121 intel_channel_eq_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1122 {
1123         uint8_t lane_align;
1124         uint8_t lane_status;
1125         int lane;
1126
1127         lane_align = intel_dp_link_status(link_status,
1128                                           DP_LANE_ALIGN_STATUS_UPDATED);
1129         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1130                 return false;
1131         for (lane = 0; lane < lane_count; lane++) {
1132                 lane_status = intel_get_lane_status(link_status, lane);
1133                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1134                         return false;
1135         }
1136         return true;
1137 }
1138
1139 static bool
1140 intel_dp_set_link_train(struct intel_dp *intel_dp,
1141                         uint32_t dp_reg_value,
1142                         uint8_t dp_train_pat,
1143                         uint8_t train_set[4],
1144                         bool first)
1145 {
1146         struct drm_device *dev = intel_dp->base.enc.dev;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148         int ret;
1149
1150         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1151         POSTING_READ(intel_dp->output_reg);
1152         if (first)
1153                 intel_wait_for_vblank(dev);
1154
1155         intel_dp_aux_native_write_1(intel_dp,
1156                                     DP_TRAINING_PATTERN_SET,
1157                                     dp_train_pat);
1158
1159         ret = intel_dp_aux_native_write(intel_dp,
1160                                         DP_TRAINING_LANE0_SET, train_set, 4);
1161         if (ret != 4)
1162                 return false;
1163
1164         return true;
1165 }
1166
1167 static void
1168 intel_dp_link_train(struct intel_dp *intel_dp)
1169 {
1170         struct drm_device *dev = intel_dp->base.enc.dev;
1171         struct drm_i915_private *dev_priv = dev->dev_private;
1172         uint8_t train_set[4];
1173         uint8_t link_status[DP_LINK_STATUS_SIZE];
1174         int i;
1175         uint8_t voltage;
1176         bool clock_recovery = false;
1177         bool channel_eq = false;
1178         bool first = true;
1179         int tries;
1180         u32 reg;
1181         uint32_t DP = intel_dp->DP;
1182
1183         /* Write the link configuration data */
1184         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1185                                   intel_dp->link_configuration,
1186                                   DP_LINK_CONFIGURATION_SIZE);
1187
1188         DP |= DP_PORT_EN;
1189         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1190                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1191         else
1192                 DP &= ~DP_LINK_TRAIN_MASK;
1193         memset(train_set, 0, 4);
1194         voltage = 0xff;
1195         tries = 0;
1196         clock_recovery = false;
1197         for (;;) {
1198                 /* Use train_set[0] to set the voltage and pre emphasis values */
1199                 uint32_t    signal_levels;
1200                 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1201                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1202                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1203                 } else {
1204                         signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1205                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1206                 }
1207
1208                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1209                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1210                 else
1211                         reg = DP | DP_LINK_TRAIN_PAT_1;
1212
1213                 if (!intel_dp_set_link_train(intel_dp, reg,
1214                                              DP_TRAINING_PATTERN_1, train_set, first))
1215                         break;
1216                 first = false;
1217                 /* Set training pattern 1 */
1218
1219                 udelay(100);
1220                 if (!intel_dp_get_link_status(intel_dp, link_status))
1221                         break;
1222
1223                 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1224                         clock_recovery = true;
1225                         break;
1226                 }
1227
1228                 /* Check to see if we've tried the max voltage */
1229                 for (i = 0; i < intel_dp->lane_count; i++)
1230                         if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1231                                 break;
1232                 if (i == intel_dp->lane_count)
1233                         break;
1234
1235                 /* Check to see if we've tried the same voltage 5 times */
1236                 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1237                         ++tries;
1238                         if (tries == 5)
1239                                 break;
1240                 } else
1241                         tries = 0;
1242                 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1243
1244                 /* Compute new train_set as requested by target */
1245                 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1246         }
1247
1248         /* channel equalization */
1249         tries = 0;
1250         channel_eq = false;
1251         for (;;) {
1252                 /* Use train_set[0] to set the voltage and pre emphasis values */
1253                 uint32_t    signal_levels;
1254
1255                 if (IS_GEN6(dev) && IS_eDP(intel_dp)) {
1256                         signal_levels = intel_gen6_edp_signal_levels(train_set[0]);
1257                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1258                 } else {
1259                         signal_levels = intel_dp_signal_levels(train_set[0], intel_dp->lane_count);
1260                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1261                 }
1262
1263                 if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1264                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1265                 else
1266                         reg = DP | DP_LINK_TRAIN_PAT_2;
1267
1268                 /* channel eq pattern */
1269                 if (!intel_dp_set_link_train(intel_dp, reg,
1270                                              DP_TRAINING_PATTERN_2, train_set,
1271                                              false))
1272                         break;
1273
1274                 udelay(400);
1275                 if (!intel_dp_get_link_status(intel_dp, link_status))
1276                         break;
1277
1278                 if (intel_channel_eq_ok(link_status, intel_dp->lane_count)) {
1279                         channel_eq = true;
1280                         break;
1281                 }
1282
1283                 /* Try 5 times */
1284                 if (tries > 5)
1285                         break;
1286
1287                 /* Compute new train_set as requested by target */
1288                 intel_get_adjust_train(intel_dp, link_status, intel_dp->lane_count, train_set);
1289                 ++tries;
1290         }
1291
1292         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp))
1293                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1294         else
1295                 reg = DP | DP_LINK_TRAIN_OFF;
1296
1297         I915_WRITE(intel_dp->output_reg, reg);
1298         POSTING_READ(intel_dp->output_reg);
1299         intel_dp_aux_native_write_1(intel_dp,
1300                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1301 }
1302
1303 static void
1304 intel_dp_link_down(struct intel_dp *intel_dp)
1305 {
1306         struct drm_device *dev = intel_dp->base.enc.dev;
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         uint32_t DP = intel_dp->DP;
1309
1310         DRM_DEBUG_KMS("\n");
1311
1312         if (IS_eDP(intel_dp)) {
1313                 DP &= ~DP_PLL_ENABLE;
1314                 I915_WRITE(intel_dp->output_reg, DP);
1315                 POSTING_READ(intel_dp->output_reg);
1316                 udelay(100);
1317         }
1318
1319         if (HAS_PCH_CPT(dev) && !IS_eDP(intel_dp)) {
1320                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1321                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1322                 POSTING_READ(intel_dp->output_reg);
1323         } else {
1324                 DP &= ~DP_LINK_TRAIN_MASK;
1325                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1326                 POSTING_READ(intel_dp->output_reg);
1327         }
1328
1329         udelay(17000);
1330
1331         if (IS_eDP(intel_dp))
1332                 DP |= DP_LINK_TRAIN_OFF;
1333         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1334         POSTING_READ(intel_dp->output_reg);
1335 }
1336
1337 /*
1338  * According to DP spec
1339  * 5.1.2:
1340  *  1. Read DPCD
1341  *  2. Configure link according to Receiver Capabilities
1342  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1343  *  4. Check link status on receipt of hot-plug interrupt
1344  */
1345
1346 static void
1347 intel_dp_check_link_status(struct intel_dp *intel_dp)
1348 {
1349         uint8_t link_status[DP_LINK_STATUS_SIZE];
1350
1351         if (!intel_dp->base.enc.crtc)
1352                 return;
1353
1354         if (!intel_dp_get_link_status(intel_dp, link_status)) {
1355                 intel_dp_link_down(intel_dp);
1356                 return;
1357         }
1358
1359         if (!intel_channel_eq_ok(link_status, intel_dp->lane_count))
1360                 intel_dp_link_train(intel_dp);
1361 }
1362
1363 static enum drm_connector_status
1364 ironlake_dp_detect(struct drm_connector *connector)
1365 {
1366         struct drm_encoder *encoder = intel_attached_encoder(connector);
1367         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1368         enum drm_connector_status status;
1369
1370         status = connector_status_disconnected;
1371         if (intel_dp_aux_native_read(intel_dp,
1372                                      0x000, intel_dp->dpcd,
1373                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1374         {
1375                 if (intel_dp->dpcd[0] != 0)
1376                         status = connector_status_connected;
1377         }
1378         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1379                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1380         return status;
1381 }
1382
1383 /**
1384  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1385  *
1386  * \return true if DP port is connected.
1387  * \return false if DP port is disconnected.
1388  */
1389 static enum drm_connector_status
1390 intel_dp_detect(struct drm_connector *connector)
1391 {
1392         struct drm_encoder *encoder = intel_attached_encoder(connector);
1393         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1394         struct drm_device *dev = intel_dp->base.enc.dev;
1395         struct drm_i915_private *dev_priv = dev->dev_private;
1396         uint32_t temp, bit;
1397         enum drm_connector_status status;
1398
1399         intel_dp->has_audio = false;
1400
1401         if (HAS_PCH_SPLIT(dev))
1402                 return ironlake_dp_detect(connector);
1403
1404         switch (intel_dp->output_reg) {
1405         case DP_B:
1406                 bit = DPB_HOTPLUG_INT_STATUS;
1407                 break;
1408         case DP_C:
1409                 bit = DPC_HOTPLUG_INT_STATUS;
1410                 break;
1411         case DP_D:
1412                 bit = DPD_HOTPLUG_INT_STATUS;
1413                 break;
1414         default:
1415                 return connector_status_unknown;
1416         }
1417
1418         temp = I915_READ(PORT_HOTPLUG_STAT);
1419
1420         if ((temp & bit) == 0)
1421                 return connector_status_disconnected;
1422
1423         status = connector_status_disconnected;
1424         if (intel_dp_aux_native_read(intel_dp,
1425                                      0x000, intel_dp->dpcd,
1426                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1427         {
1428                 if (intel_dp->dpcd[0] != 0)
1429                         status = connector_status_connected;
1430         }
1431         return status;
1432 }
1433
1434 static int intel_dp_get_modes(struct drm_connector *connector)
1435 {
1436         struct drm_encoder *encoder = intel_attached_encoder(connector);
1437         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1438         struct drm_device *dev = intel_dp->base.enc.dev;
1439         struct drm_i915_private *dev_priv = dev->dev_private;
1440         int ret;
1441
1442         /* We should parse the EDID data and find out if it has an audio sink
1443          */
1444
1445         ret = intel_ddc_get_modes(connector, intel_dp->base.ddc_bus);
1446         if (ret) {
1447                 if ((IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) &&
1448                     !dev_priv->panel_fixed_mode) {
1449                         struct drm_display_mode *newmode;
1450                         list_for_each_entry(newmode, &connector->probed_modes,
1451                                             head) {
1452                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1453                                         dev_priv->panel_fixed_mode =
1454                                                 drm_mode_duplicate(dev, newmode);
1455                                         break;
1456                                 }
1457                         }
1458                 }
1459
1460                 return ret;
1461         }
1462
1463         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1464         if (IS_eDP(intel_dp) || IS_PCH_eDP(intel_dp)) {
1465                 if (dev_priv->panel_fixed_mode != NULL) {
1466                         struct drm_display_mode *mode;
1467                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1468                         drm_mode_probed_add(connector, mode);
1469                         return 1;
1470                 }
1471         }
1472         return 0;
1473 }
1474
1475 static void
1476 intel_dp_destroy (struct drm_connector *connector)
1477 {
1478         drm_sysfs_connector_remove(connector);
1479         drm_connector_cleanup(connector);
1480         kfree(connector);
1481 }
1482
1483 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1484         .dpms = intel_dp_dpms,
1485         .mode_fixup = intel_dp_mode_fixup,
1486         .prepare = intel_dp_prepare,
1487         .mode_set = intel_dp_mode_set,
1488         .commit = intel_dp_commit,
1489 };
1490
1491 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1492         .dpms = drm_helper_connector_dpms,
1493         .detect = intel_dp_detect,
1494         .fill_modes = drm_helper_probe_single_connector_modes,
1495         .destroy = intel_dp_destroy,
1496 };
1497
1498 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1499         .get_modes = intel_dp_get_modes,
1500         .mode_valid = intel_dp_mode_valid,
1501         .best_encoder = intel_attached_encoder,
1502 };
1503
1504 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1505         .destroy = intel_encoder_destroy,
1506 };
1507
1508 void
1509 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1510 {
1511         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1512
1513         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1514                 intel_dp_check_link_status(intel_dp);
1515 }
1516
1517 /* Return which DP Port should be selected for Transcoder DP control */
1518 int
1519 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1520 {
1521         struct drm_device *dev = crtc->dev;
1522         struct drm_mode_config *mode_config = &dev->mode_config;
1523         struct drm_encoder *encoder;
1524
1525         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1526                 struct intel_dp *intel_dp;
1527
1528                 if (encoder->crtc != crtc)
1529                         continue;
1530
1531                 intel_dp = enc_to_intel_dp(encoder);
1532                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1533                         return intel_dp->output_reg;
1534         }
1535
1536         return -1;
1537 }
1538
1539 /* check the VBT to see whether the eDP is on DP-D port */
1540 bool intel_dpd_is_edp(struct drm_device *dev)
1541 {
1542         struct drm_i915_private *dev_priv = dev->dev_private;
1543         struct child_device_config *p_child;
1544         int i;
1545
1546         if (!dev_priv->child_dev_num)
1547                 return false;
1548
1549         for (i = 0; i < dev_priv->child_dev_num; i++) {
1550                 p_child = dev_priv->child_dev + i;
1551
1552                 if (p_child->dvo_port == PORT_IDPD &&
1553                     p_child->device_type == DEVICE_TYPE_eDP)
1554                         return true;
1555         }
1556         return false;
1557 }
1558
1559 void
1560 intel_dp_init(struct drm_device *dev, int output_reg)
1561 {
1562         struct drm_i915_private *dev_priv = dev->dev_private;
1563         struct drm_connector *connector;
1564         struct intel_dp *intel_dp;
1565         struct intel_encoder *intel_encoder;
1566         struct intel_connector *intel_connector;
1567         const char *name = NULL;
1568         int type;
1569
1570         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1571         if (!intel_dp)
1572                 return;
1573
1574         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1575         if (!intel_connector) {
1576                 kfree(intel_dp);
1577                 return;
1578         }
1579         intel_encoder = &intel_dp->base;
1580
1581         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1582                 if (intel_dpd_is_edp(dev))
1583                         intel_dp->is_pch_edp = true;
1584
1585         if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1586                 type = DRM_MODE_CONNECTOR_eDP;
1587                 intel_encoder->type = INTEL_OUTPUT_EDP;
1588         } else {
1589                 type = DRM_MODE_CONNECTOR_DisplayPort;
1590                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1591         }
1592
1593         connector = &intel_connector->base;
1594         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1595         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1596
1597         connector->polled = DRM_CONNECTOR_POLL_HPD;
1598
1599         if (output_reg == DP_B || output_reg == PCH_DP_B)
1600                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1601         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1602                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1603         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1604                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1605
1606         if (IS_eDP(intel_dp))
1607                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1608
1609         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1610         connector->interlace_allowed = true;
1611         connector->doublescan_allowed = 0;
1612
1613         intel_dp->output_reg = output_reg;
1614         intel_dp->has_audio = false;
1615         intel_dp->dpms_mode = DRM_MODE_DPMS_ON;
1616
1617         drm_encoder_init(dev, &intel_encoder->enc, &intel_dp_enc_funcs,
1618                          DRM_MODE_ENCODER_TMDS);
1619         drm_encoder_helper_add(&intel_encoder->enc, &intel_dp_helper_funcs);
1620
1621         drm_mode_connector_attach_encoder(&intel_connector->base,
1622                                           &intel_encoder->enc);
1623         drm_sysfs_connector_add(connector);
1624
1625         /* Set up the DDC bus. */
1626         switch (output_reg) {
1627                 case DP_A:
1628                         name = "DPDDC-A";
1629                         break;
1630                 case DP_B:
1631                 case PCH_DP_B:
1632                         dev_priv->hotplug_supported_mask |=
1633                                 HDMIB_HOTPLUG_INT_STATUS;
1634                         name = "DPDDC-B";
1635                         break;
1636                 case DP_C:
1637                 case PCH_DP_C:
1638                         dev_priv->hotplug_supported_mask |=
1639                                 HDMIC_HOTPLUG_INT_STATUS;
1640                         name = "DPDDC-C";
1641                         break;
1642                 case DP_D:
1643                 case PCH_DP_D:
1644                         dev_priv->hotplug_supported_mask |=
1645                                 HDMID_HOTPLUG_INT_STATUS;
1646                         name = "DPDDC-D";
1647                         break;
1648         }
1649
1650         intel_dp_i2c_init(intel_dp, intel_connector, name);
1651
1652         intel_encoder->ddc_bus = &intel_dp->adapter;
1653         intel_encoder->hot_plug = intel_dp_hot_plug;
1654
1655         if (output_reg == DP_A || IS_PCH_eDP(intel_dp)) {
1656                 /* initialize panel mode from VBT if available for eDP */
1657                 if (dev_priv->lfp_lvds_vbt_mode) {
1658                         dev_priv->panel_fixed_mode =
1659                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1660                         if (dev_priv->panel_fixed_mode) {
1661                                 dev_priv->panel_fixed_mode->type |=
1662                                         DRM_MODE_TYPE_PREFERRED;
1663                         }
1664                 }
1665         }
1666
1667         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1668          * 0xd.  Failure to do so will result in spurious interrupts being
1669          * generated on the port when a cable is not attached.
1670          */
1671         if (IS_G4X(dev) && !IS_GM45(dev)) {
1672                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1673                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1674         }
1675 }