drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      I915_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              I915_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u8 new_delay = dev_priv->cur_delay;
 282
 283         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 284         busy_up = I915_READ(RCPREVBSYTUPAVG);
 285         busy_down = I915_READ(RCPREVBSYTDNAVG);
 286         max_avg = I915_READ(RCBMAXAVG);
 287         min_avg = I915_READ(RCBMINAVG);
 288
 289         /* Handle RCS change request from hw */
 290         if (busy_up > max_avg) {
 291                 if (dev_priv->cur_delay != dev_priv->max_delay)
 292                         new_delay = dev_priv->cur_delay - 1;
 293                 if (new_delay < dev_priv->max_delay)
 294                         new_delay = dev_priv->max_delay;
 295         } else if (busy_down < min_avg) {
 296                 if (dev_priv->cur_delay != dev_priv->min_delay)
 297                         new_delay = dev_priv->cur_delay + 1;
 298                 if (new_delay > dev_priv->min_delay)
 299                         new_delay = dev_priv->min_delay;
 300         }
 301
 302         if (ironlake_set_drps(dev, new_delay))
 303                 dev_priv->cur_delay = new_delay;
 304
 305         return;
 306 }
 307
 308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 309 {
 310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 311         int ret = IRQ_NONE;
 312         u32 de_iir, gt_iir, de_ier, pch_iir;
 313         struct drm_i915_master_private *master_priv;
 314         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 315
 316         /* disable master interrupt before clearing iir  */
 317         de_ier = I915_READ(DEIER);
 318         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 319         (void)I915_READ(DEIER);
 320
 321         de_iir = I915_READ(DEIIR);
 322         gt_iir = I915_READ(GTIIR);
 323         pch_iir = I915_READ(SDEIIR);
 324
 325         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 326                 goto done;
 327
 328         ret = IRQ_HANDLED;
 329
 330         if (dev->primary->master) {
 331                 master_priv = dev->primary->master->driver_priv;
 332                 if (master_priv->sarea_priv)
 333                         master_priv->sarea_priv->last_dispatch =
 334                                 READ_BREADCRUMB(dev_priv);
 335         }
 336
 337         if (gt_iir & GT_PIPE_NOTIFY) {
 338                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 339                 render_ring->irq_gem_seqno = seqno;
 340                 trace_i915_gem_request_complete(dev, seqno);
 341                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 344         }
 345         if (gt_iir & GT_BSD_USER_INTERRUPT)
 346                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 347
 348
 349         if (de_iir & DE_GSE)
 350                 ironlake_opregion_gse_intr(dev);
 351
 352         if (de_iir & DE_PLANEA_FLIP_DONE) {
 353                 intel_prepare_page_flip(dev, 0);
 354                 intel_finish_page_flip(dev, 0);
 355         }
 356
 357         if (de_iir & DE_PLANEB_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 1);
 359                 intel_finish_page_flip(dev, 1);
 360         }
 361
 362         if (de_iir & DE_PIPEA_VBLANK)
 363                 drm_handle_vblank(dev, 0);
 364
 365         if (de_iir & DE_PIPEB_VBLANK)
 366                 drm_handle_vblank(dev, 1);
 367
 368         /* check event from PCH */
 369         if ((de_iir & DE_PCH_EVENT) &&
 370             (pch_iir & SDE_HOTPLUG_MASK)) {
 371                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 372         }
 373
 374         if (de_iir & DE_PCU_EVENT) {
 375                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 376                 i915_handle_rps_change(dev);
 377         }
 378
 379         /* should clear PCH hotplug event before clear CPU irq */
 380         I915_WRITE(SDEIIR, pch_iir);
 381         I915_WRITE(GTIIR, gt_iir);
 382         I915_WRITE(DEIIR, de_iir);
 383
 384 done:
 385         I915_WRITE(DEIER, de_ier);
 386         (void)I915_READ(DEIER);
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * i915_error_work_func - do process context error handling work
 393  * @work: work struct
 394  *
 395  * Fire an error uevent so userspace can see that a hang or error
 396  * was detected.
 397  */
 398 static void i915_error_work_func(struct work_struct *work)
 399 {
 400         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 401                                                     error_work);
 402         struct drm_device *dev = dev_priv->dev;
 403         char *error_event[] = { "ERROR=1", NULL };
 404         char *reset_event[] = { "RESET=1", NULL };
 405         char *reset_done_event[] = { "ERROR=0", NULL };
 406
 407         DRM_DEBUG_DRIVER("generating error event\n");
 408         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 409
 410         if (atomic_read(&dev_priv->mm.wedged)) {
 411                 if (IS_I965G(dev)) {
 412                         DRM_DEBUG_DRIVER("resetting chip\n");
 413                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 414                         if (!i965_reset(dev, GDRST_RENDER)) {
 415                                 atomic_set(&dev_priv->mm.wedged, 0);
 416                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 417                         }
 418                 } else {
 419                         DRM_DEBUG_DRIVER("reboot required\n");
 420                 }
 421         }
 422 }
 423
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         struct drm_i915_error_object *dst;
 429         struct drm_i915_gem_object *src_priv;
 430         int page, page_count;
 431
 432         if (src == NULL)
 433                 return NULL;
 434
 435         src_priv = to_intel_bo(src);
 436         if (src_priv->pages == NULL)
 437                 return NULL;
 438
 439         page_count = src->size / PAGE_SIZE;
 440
 441         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 442         if (dst == NULL)
 443                 return NULL;
 444
 445         for (page = 0; page < page_count; page++) {
 446                 void *s, *d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 447                 unsigned long flags;
 448
 449                 if (d == NULL)
 450                         goto unwind;
 451                 local_irq_save(flags);
 452                 s = kmap_atomic(src_priv->pages[page], KM_IRQ0);
 453                 memcpy(d, s, PAGE_SIZE);
 454                 kunmap_atomic(s, KM_IRQ0);
 455                 local_irq_restore(flags);
 456                 dst->pages[page] = d;
 457         }
 458         dst->page_count = page_count;
 459         dst->gtt_offset = src_priv->gtt_offset;
 460
 461         return dst;
 462
 463 unwind:
 464         while (page--)
 465                 kfree(dst->pages[page]);
 466         kfree(dst);
 467         return NULL;
 468 }
 469
 470 static void
 471 i915_error_object_free(struct drm_i915_error_object *obj)
 472 {
 473         int page;
 474
 475         if (obj == NULL)
 476                 return;
 477
 478         for (page = 0; page < obj->page_count; page++)
 479                 kfree(obj->pages[page]);
 480
 481         kfree(obj);
 482 }
 483
 484 static void
 485 i915_error_state_free(struct drm_device *dev,
 486                       struct drm_i915_error_state *error)
 487 {
 488         i915_error_object_free(error->batchbuffer[0]);
 489         i915_error_object_free(error->batchbuffer[1]);
 490         i915_error_object_free(error->ringbuffer);
 491         kfree(error->active_bo);
 492         kfree(error);
 493 }
 494
 495 static u32
 496 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 497 {
 498         u32 cmd;
 499
 500         if (IS_I830(dev) || IS_845G(dev))
 501                 cmd = MI_BATCH_BUFFER;
 502         else if (IS_I965G(dev))
 503                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 504                        MI_BATCH_NON_SECURE_I965);
 505         else
 506                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 507
 508         return ring[0] == cmd ? ring[1] : 0;
 509 }
 510
 511 static u32
 512 i915_ringbuffer_last_batch(struct drm_device *dev)
 513 {
 514         struct drm_i915_private *dev_priv = dev->dev_private;
 515         u32 head, bbaddr;
 516         u32 *ring;
 517
 518         /* Locate the current position in the ringbuffer and walk back
 519          * to find the most recently dispatched batch buffer.
 520          */
 521         bbaddr = 0;
 522         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 523         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 524
 525         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 526                 bbaddr = i915_get_bbaddr(dev, ring);
 527                 if (bbaddr)
 528                         break;
 529         }
 530
 531         if (bbaddr == 0) {
 532                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 533                                 + dev_priv->render_ring.size);
 534                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 535                         bbaddr = i915_get_bbaddr(dev, ring);
 536                         if (bbaddr)
 537                                 break;
 538                 }
 539         }
 540
 541         return bbaddr;
 542 }
 543
 544 /**
 545  * i915_capture_error_state - capture an error record for later analysis
 546  * @dev: drm device
 547  *
 548  * Should be called when an error is detected (either a hang or an error
 549  * interrupt) to capture error state from the time of the error.  Fills
 550  * out a structure which becomes available in debugfs for user level tools
 551  * to pick up.
 552  */
 553 static void i915_capture_error_state(struct drm_device *dev)
 554 {
 555         struct drm_i915_private *dev_priv = dev->dev_private;
 556         struct drm_i915_gem_object *obj_priv;
 557         struct drm_i915_error_state *error;
 558         struct drm_gem_object *batchbuffer[2];
 559         unsigned long flags;
 560         u32 bbaddr;
 561         int count;
 562
 563         spin_lock_irqsave(&dev_priv->error_lock, flags);
 564         error = dev_priv->first_error;
 565         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 566         if (error)
 567                 return;
 568
 569         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 570         if (!error) {
 571                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 572                 return;
 573         }
 574
 575         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 576         error->eir = I915_READ(EIR);
 577         error->pgtbl_er = I915_READ(PGTBL_ER);
 578         error->pipeastat = I915_READ(PIPEASTAT);
 579         error->pipebstat = I915_READ(PIPEBSTAT);
 580         error->instpm = I915_READ(INSTPM);
 581         if (!IS_I965G(dev)) {
 582                 error->ipeir = I915_READ(IPEIR);
 583                 error->ipehr = I915_READ(IPEHR);
 584                 error->instdone = I915_READ(INSTDONE);
 585                 error->acthd = I915_READ(ACTHD);
 586                 error->bbaddr = 0;
 587         } else {
 588                 error->ipeir = I915_READ(IPEIR_I965);
 589                 error->ipehr = I915_READ(IPEHR_I965);
 590                 error->instdone = I915_READ(INSTDONE_I965);
 591                 error->instps = I915_READ(INSTPS);
 592                 error->instdone1 = I915_READ(INSTDONE1);
 593                 error->acthd = I915_READ(ACTHD_I965);
 594                 error->bbaddr = I915_READ64(BB_ADDR);
 595         }
 596
 597         bbaddr = i915_ringbuffer_last_batch(dev);
 598
 599         /* Grab the current batchbuffer, most likely to have crashed. */
 600         batchbuffer[0] = NULL;
 601         batchbuffer[1] = NULL;
 602         count = 0;
 603         list_for_each_entry(obj_priv,
 604                         &dev_priv->render_ring.active_list, list) {
 605
 606                 struct drm_gem_object *obj = &obj_priv->base;
 607
 608                 if (batchbuffer[0] == NULL &&
 609                     bbaddr >= obj_priv->gtt_offset &&
 610                     bbaddr < obj_priv->gtt_offset + obj->size)
 611                         batchbuffer[0] = obj;
 612
 613                 if (batchbuffer[1] == NULL &&
 614                     error->acthd >= obj_priv->gtt_offset &&
 615                     error->acthd < obj_priv->gtt_offset + obj->size &&
 616                     batchbuffer[0] != obj)
 617                         batchbuffer[1] = obj;
 618
 619                 count++;
 620         }
 621
 622         /* We need to copy these to an anonymous buffer as the simplest
 623          * method to avoid being overwritten by userpace.
 624          */
 625         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 626         error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 627
 628         /* Record the ringbuffer */
 629         error->ringbuffer = i915_error_object_create(dev,
 630                         dev_priv->render_ring.gem_object);
 631
 632         /* Record buffers on the active list. */
 633         error->active_bo = NULL;
 634         error->active_bo_count = 0;
 635
 636         if (count)
 637                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 638                                            GFP_ATOMIC);
 639
 640         if (error->active_bo) {
 641                 int i = 0;
 642                 list_for_each_entry(obj_priv,
 643                                 &dev_priv->render_ring.active_list, list) {
 644                         struct drm_gem_object *obj = &obj_priv->base;
 645
 646                         error->active_bo[i].size = obj->size;
 647                         error->active_bo[i].name = obj->name;
 648                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 649                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 650                         error->active_bo[i].read_domains = obj->read_domains;
 651                         error->active_bo[i].write_domain = obj->write_domain;
 652                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 653                         error->active_bo[i].pinned = 0;
 654                         if (obj_priv->pin_count > 0)
 655                                 error->active_bo[i].pinned = 1;
 656                         if (obj_priv->user_pin_count > 0)
 657                                 error->active_bo[i].pinned = -1;
 658                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 659                         error->active_bo[i].dirty = obj_priv->dirty;
 660                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 661
 662                         if (++i == count)
 663                                 break;
 664                 }
 665                 error->active_bo_count = i;
 666         }
 667
 668         do_gettimeofday(&error->time);
 669
 670         spin_lock_irqsave(&dev_priv->error_lock, flags);
 671         if (dev_priv->first_error == NULL) {
 672                 dev_priv->first_error = error;
 673                 error = NULL;
 674         }
 675         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 676
 677         if (error)
 678                 i915_error_state_free(dev, error);
 679 }
 680
 681 void i915_destroy_error_state(struct drm_device *dev)
 682 {
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         struct drm_i915_error_state *error;
 685
 686         spin_lock(&dev_priv->error_lock);
 687         error = dev_priv->first_error;
 688         dev_priv->first_error = NULL;
 689         spin_unlock(&dev_priv->error_lock);
 690
 691         if (error)
 692                 i915_error_state_free(dev, error);
 693 }
 694
 695 static void i915_report_and_clear_eir(struct drm_device *dev)
 696 {
 697         struct drm_i915_private *dev_priv = dev->dev_private;
 698         u32 eir = I915_READ(EIR);
 699
 700         if (!eir)
 701                 return;
 702
 703         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 704                eir);
 705
 706         if (IS_G4X(dev)) {
 707                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 708                         u32 ipeir = I915_READ(IPEIR_I965);
 709
 710                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 711                                I915_READ(IPEIR_I965));
 712                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 713                                I915_READ(IPEHR_I965));
 714                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 715                                I915_READ(INSTDONE_I965));
 716                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 717                                I915_READ(INSTPS));
 718                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 719                                I915_READ(INSTDONE1));
 720                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 721                                I915_READ(ACTHD_I965));
 722                         I915_WRITE(IPEIR_I965, ipeir);
 723                         (void)I915_READ(IPEIR_I965);
 724                 }
 725                 if (eir & GM45_ERROR_PAGE_TABLE) {
 726                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 727                         printk(KERN_ERR "page table error\n");
 728                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 729                                pgtbl_err);
 730                         I915_WRITE(PGTBL_ER, pgtbl_err);
 731                         (void)I915_READ(PGTBL_ER);
 732                 }
 733         }
 734
 735         if (IS_I9XX(dev)) {
 736                 if (eir & I915_ERROR_PAGE_TABLE) {
 737                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 738                         printk(KERN_ERR "page table error\n");
 739                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 740                                pgtbl_err);
 741                         I915_WRITE(PGTBL_ER, pgtbl_err);
 742                         (void)I915_READ(PGTBL_ER);
 743                 }
 744         }
 745
 746         if (eir & I915_ERROR_MEMORY_REFRESH) {
 747                 u32 pipea_stats = I915_READ(PIPEASTAT);
 748                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 749
 750                 printk(KERN_ERR "memory refresh error\n");
 751                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 752                        pipea_stats);
 753                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 754                        pipeb_stats);
 755                 /* pipestat has already been acked */
 756         }
 757         if (eir & I915_ERROR_INSTRUCTION) {
 758                 printk(KERN_ERR "instruction error\n");
 759                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 760                        I915_READ(INSTPM));
 761                 if (!IS_I965G(dev)) {
 762                         u32 ipeir = I915_READ(IPEIR);
 763
 764                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 765                                I915_READ(IPEIR));
 766                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 767                                I915_READ(IPEHR));
 768                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 769                                I915_READ(INSTDONE));
 770                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 771                                I915_READ(ACTHD));
 772                         I915_WRITE(IPEIR, ipeir);
 773                         (void)I915_READ(IPEIR);
 774                 } else {
 775                         u32 ipeir = I915_READ(IPEIR_I965);
 776
 777                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 778                                I915_READ(IPEIR_I965));
 779                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 780                                I915_READ(IPEHR_I965));
 781                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 782                                I915_READ(INSTDONE_I965));
 783                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 784                                I915_READ(INSTPS));
 785                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 786                                I915_READ(INSTDONE1));
 787                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 788                                I915_READ(ACTHD_I965));
 789                         I915_WRITE(IPEIR_I965, ipeir);
 790                         (void)I915_READ(IPEIR_I965);
 791                 }
 792         }
 793
 794         I915_WRITE(EIR, eir);
 795         (void)I915_READ(EIR);
 796         eir = I915_READ(EIR);
 797         if (eir) {
 798                 /*
 799                  * some errors might have become stuck,
 800                  * mask them.
 801                  */
 802                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 803                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 804                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 805         }
 806 }
 807
 808 /**
 809  * i915_handle_error - handle an error interrupt
 810  * @dev: drm device
 811  *
 812  * Do some basic checking of regsiter state at error interrupt time and
 813  * dump it to the syslog.  Also call i915_capture_error_state() to make
 814  * sure we get a record and make it available in debugfs.  Fire a uevent
 815  * so userspace knows something bad happened (should trigger collection
 816  * of a ring dump etc.).
 817  */
 818 static void i915_handle_error(struct drm_device *dev, bool wedged)
 819 {
 820         struct drm_i915_private *dev_priv = dev->dev_private;
 821
 822         i915_capture_error_state(dev);
 823         i915_report_and_clear_eir(dev);
 824
 825         if (wedged) {
 826                 atomic_set(&dev_priv->mm.wedged, 1);
 827
 828                 /*
 829                  * Wakeup waiting processes so they don't hang
 830                  */
 831                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 832         }
 833
 834         queue_work(dev_priv->wq, &dev_priv->error_work);
 835 }
 836
 837 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 838 {
 839         struct drm_device *dev = (struct drm_device *) arg;
 840         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 841         struct drm_i915_master_private *master_priv;
 842         u32 iir, new_iir;
 843         u32 pipea_stats, pipeb_stats;
 844         u32 vblank_status;
 845         u32 vblank_enable;
 846         int vblank = 0;
 847         unsigned long irqflags;
 848         int irq_received;
 849         int ret = IRQ_NONE;
 850         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 851
 852         atomic_inc(&dev_priv->irq_received);
 853
 854         if (HAS_PCH_SPLIT(dev))
 855                 return ironlake_irq_handler(dev);
 856
 857         iir = I915_READ(IIR);
 858
 859         if (IS_I965G(dev)) {
 860                 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
 861                 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
 862         } else {
 863                 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
 864                 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
 865         }
 866
 867         for (;;) {
 868                 irq_received = iir != 0;
 869
 870                 /* Can't rely on pipestat interrupt bit in iir as it might
 871                  * have been cleared after the pipestat interrupt was received.
 872                  * It doesn't set the bit in iir again, but it still produces
 873                  * interrupts (for non-MSI).
 874                  */
 875                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 876                 pipea_stats = I915_READ(PIPEASTAT);
 877                 pipeb_stats = I915_READ(PIPEBSTAT);
 878
 879                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 880                         i915_handle_error(dev, false);
 881
 882                 /*
 883                  * Clear the PIPE(A|B)STAT regs before the IIR
 884                  */
 885                 if (pipea_stats & 0x8000ffff) {
 886                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 887                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 888                         I915_WRITE(PIPEASTAT, pipea_stats);
 889                         irq_received = 1;
 890                 }
 891
 892                 if (pipeb_stats & 0x8000ffff) {
 893                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 894                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 895                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 896                         irq_received = 1;
 897                 }
 898                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 899
 900                 if (!irq_received)
 901                         break;
 902
 903                 ret = IRQ_HANDLED;
 904
 905                 /* Consume port.  Then clear IIR or we'll miss events */
 906                 if ((I915_HAS_HOTPLUG(dev)) &&
 907                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 908                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 909
 910                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 911                                   hotplug_status);
 912                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 913                                 queue_work(dev_priv->wq,
 914                                            &dev_priv->hotplug_work);
 915
 916                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 917                         I915_READ(PORT_HOTPLUG_STAT);
 918                 }
 919
 920                 I915_WRITE(IIR, iir);
 921                 new_iir = I915_READ(IIR); /* Flush posted writes */
 922
 923                 if (dev->primary->master) {
 924                         master_priv = dev->primary->master->driver_priv;
 925                         if (master_priv->sarea_priv)
 926                                 master_priv->sarea_priv->last_dispatch =
 927                                         READ_BREADCRUMB(dev_priv);
 928                 }
 929
 930                 if (iir & I915_USER_INTERRUPT) {
 931                         u32 seqno =
 932                                 render_ring->get_gem_seqno(dev, render_ring);
 933                         render_ring->irq_gem_seqno = seqno;
 934                         trace_i915_gem_request_complete(dev, seqno);
 935                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 936                         dev_priv->hangcheck_count = 0;
 937                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 938                 }
 939
 940                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
 941                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 942
 943                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
 944                         intel_prepare_page_flip(dev, 0);
 945                         if (dev_priv->flip_pending_is_done)
 946                                 intel_finish_page_flip_plane(dev, 0);
 947                 }
 948
 949                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
 950                         if (dev_priv->flip_pending_is_done)
 951                                 intel_finish_page_flip_plane(dev, 1);
 952                         intel_prepare_page_flip(dev, 1);
 953                 }
 954
 955                 if (pipea_stats & vblank_status) {
 956                         vblank++;
 957                         drm_handle_vblank(dev, 0);
 958                         if (!dev_priv->flip_pending_is_done)
 959                                 intel_finish_page_flip(dev, 0);
 960                 }
 961
 962                 if (pipeb_stats & vblank_status) {
 963                         vblank++;
 964                         drm_handle_vblank(dev, 1);
 965                         if (!dev_priv->flip_pending_is_done)
 966                                 intel_finish_page_flip(dev, 1);
 967                 }
 968
 969                 if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 970                     (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 971                     (iir & I915_ASLE_INTERRUPT))
 972                         opregion_asle_intr(dev);
 973
 974                 /* With MSI, interrupts are only generated when iir
 975                  * transitions from zero to nonzero.  If another bit got
 976                  * set while we were handling the existing iir bits, then
 977                  * we would never get another interrupt.
 978                  *
 979                  * This is fine on non-MSI as well, as if we hit this path
 980                  * we avoid exiting the interrupt handler only to generate
 981                  * another one.
 982                  *
 983                  * Note that for MSI this could cause a stray interrupt report
 984                  * if an interrupt landed in the time between writing IIR and
 985                  * the posting read.  This should be rare enough to never
 986                  * trigger the 99% of 100,000 interrupts test for disabling
 987                  * stray interrupts.
 988                  */
 989                 iir = new_iir;
 990         }
 991
 992         return ret;
 993 }
 994
 995 static int i915_emit_irq(struct drm_device * dev)
 996 {
 997         drm_i915_private_t *dev_priv = dev->dev_private;
 998         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 999
1000         i915_kernel_lost_context(dev);
1001
1002         DRM_DEBUG_DRIVER("\n");
1003
1004         dev_priv->counter++;
1005         if (dev_priv->counter > 0x7FFFFFFFUL)
1006                 dev_priv->counter = 1;
1007         if (master_priv->sarea_priv)
1008                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1009
1010         BEGIN_LP_RING(4);
1011         OUT_RING(MI_STORE_DWORD_INDEX);
1012         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1013         OUT_RING(dev_priv->counter);
1014         OUT_RING(MI_USER_INTERRUPT);
1015         ADVANCE_LP_RING();
1016
1017         return dev_priv->counter;
1018 }
1019
1020 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1021 {
1022         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1023         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1024
1025         if (dev_priv->trace_irq_seqno == 0)
1026                 render_ring->user_irq_get(dev, render_ring);
1027
1028         dev_priv->trace_irq_seqno = seqno;
1029 }
1030
1031 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1032 {
1033         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1034         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1035         int ret = 0;
1036         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1037
1038         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1039                   READ_BREADCRUMB(dev_priv));
1040
1041         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1042                 if (master_priv->sarea_priv)
1043                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1044                 return 0;
1045         }
1046
1047         if (master_priv->sarea_priv)
1048                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1049
1050         render_ring->user_irq_get(dev, render_ring);
1051         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1052                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1053         render_ring->user_irq_put(dev, render_ring);
1054
1055         if (ret == -EBUSY) {
1056                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1057                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1058         }
1059
1060         return ret;
1061 }
1062
1063 /* Needs the lock as it touches the ring.
1064  */
1065 int i915_irq_emit(struct drm_device *dev, void *data,
1066                          struct drm_file *file_priv)
1067 {
1068         drm_i915_private_t *dev_priv = dev->dev_private;
1069         drm_i915_irq_emit_t *emit = data;
1070         int result;
1071
1072         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1073                 DRM_ERROR("called with no initialization\n");
1074                 return -EINVAL;
1075         }
1076
1077         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1078
1079         mutex_lock(&dev->struct_mutex);
1080         result = i915_emit_irq(dev);
1081         mutex_unlock(&dev->struct_mutex);
1082
1083         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1084                 DRM_ERROR("copy_to_user\n");
1085                 return -EFAULT;
1086         }
1087
1088         return 0;
1089 }
1090
1091 /* Doesn't need the hardware lock.
1092  */
1093 int i915_irq_wait(struct drm_device *dev, void *data,
1094                          struct drm_file *file_priv)
1095 {
1096         drm_i915_private_t *dev_priv = dev->dev_private;
1097         drm_i915_irq_wait_t *irqwait = data;
1098
1099         if (!dev_priv) {
1100                 DRM_ERROR("called with no initialization\n");
1101                 return -EINVAL;
1102         }
1103
1104         return i915_wait_irq(dev, irqwait->irq_seq);
1105 }
1106
1107 /* Called from drm generic code, passed 'crtc' which
1108  * we use as a pipe index
1109  */
1110 int i915_enable_vblank(struct drm_device *dev, int pipe)
1111 {
1112         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1113         unsigned long irqflags;
1114         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1115         u32 pipeconf;
1116
1117         pipeconf = I915_READ(pipeconf_reg);
1118         if (!(pipeconf & PIPEACONF_ENABLE))
1119                 return -EINVAL;
1120
1121         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1122         if (HAS_PCH_SPLIT(dev))
1123                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1124                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1125         else if (IS_I965G(dev))
1126                 i915_enable_pipestat(dev_priv, pipe,
1127                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1128         else
1129                 i915_enable_pipestat(dev_priv, pipe,
1130                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1131         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1132         return 0;
1133 }
1134
1135 /* Called from drm generic code, passed 'crtc' which
1136  * we use as a pipe index
1137  */
1138 void i915_disable_vblank(struct drm_device *dev, int pipe)
1139 {
1140         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1141         unsigned long irqflags;
1142
1143         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1144         if (HAS_PCH_SPLIT(dev))
1145                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1146                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1147         else
1148                 i915_disable_pipestat(dev_priv, pipe,
1149                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1150                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1151         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1152 }
1153
1154 void i915_enable_interrupt (struct drm_device *dev)
1155 {
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157
1158         if (!HAS_PCH_SPLIT(dev))
1159                 opregion_enable_asle(dev);
1160         dev_priv->irq_enabled = 1;
1161 }
1162
1163
1164 /* Set the vblank monitor pipe
1165  */
1166 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1167                          struct drm_file *file_priv)
1168 {
1169         drm_i915_private_t *dev_priv = dev->dev_private;
1170
1171         if (!dev_priv) {
1172                 DRM_ERROR("called with no initialization\n");
1173                 return -EINVAL;
1174         }
1175
1176         return 0;
1177 }
1178
1179 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1180                          struct drm_file *file_priv)
1181 {
1182         drm_i915_private_t *dev_priv = dev->dev_private;
1183         drm_i915_vblank_pipe_t *pipe = data;
1184
1185         if (!dev_priv) {
1186                 DRM_ERROR("called with no initialization\n");
1187                 return -EINVAL;
1188         }
1189
1190         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1191
1192         return 0;
1193 }
1194
1195 /**
1196  * Schedule buffer swap at given vertical blank.
1197  */
1198 int i915_vblank_swap(struct drm_device *dev, void *data,
1199                      struct drm_file *file_priv)
1200 {
1201         /* The delayed swap mechanism was fundamentally racy, and has been
1202          * removed.  The model was that the client requested a delayed flip/swap
1203          * from the kernel, then waited for vblank before continuing to perform
1204          * rendering.  The problem was that the kernel might wake the client
1205          * up before it dispatched the vblank swap (since the lock has to be
1206          * held while touching the ringbuffer), in which case the client would
1207          * clear and start the next frame before the swap occurred, and
1208          * flicker would occur in addition to likely missing the vblank.
1209          *
1210          * In the absence of this ioctl, userland falls back to a correct path
1211          * of waiting for a vblank, then dispatching the swap on its own.
1212          * Context switching to userland and back is plenty fast enough for
1213          * meeting the requirements of vblank swapping.
1214          */
1215         return -EINVAL;
1216 }
1217
1218 struct drm_i915_gem_request *
1219 i915_get_tail_request(struct drm_device *dev)
1220 {
1221         drm_i915_private_t *dev_priv = dev->dev_private;
1222         return list_entry(dev_priv->render_ring.request_list.prev,
1223                         struct drm_i915_gem_request, list);
1224 }
1225
1226 /**
1227  * This is called when the chip hasn't reported back with completed
1228  * batchbuffers in a long time. The first time this is called we simply record
1229  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1230  * again, we assume the chip is wedged and try to fix it.
1231  */
1232 void i915_hangcheck_elapsed(unsigned long data)
1233 {
1234         struct drm_device *dev = (struct drm_device *)data;
1235         drm_i915_private_t *dev_priv = dev->dev_private;
1236         uint32_t acthd;
1237
1238         /* No reset support on this chip yet. */
1239         if (IS_GEN6(dev))
1240                 return;
1241
1242         if (!IS_I965G(dev))
1243                 acthd = I915_READ(ACTHD);
1244         else
1245                 acthd = I915_READ(ACTHD_I965);
1246
1247         /* If all work is done then ACTHD clearly hasn't advanced. */
1248         if (list_empty(&dev_priv->render_ring.request_list) ||
1249                 i915_seqno_passed(i915_get_gem_seqno(dev,
1250                                 &dev_priv->render_ring),
1251                         i915_get_tail_request(dev)->seqno)) {
1252                 dev_priv->hangcheck_count = 0;
1253                 return;
1254         }
1255
1256         if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
1257                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1258                 i915_handle_error(dev, true);
1259                 return;
1260         }
1261
1262         /* Reset timer case chip hangs without another request being added */
1263         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1264
1265         if (acthd != dev_priv->last_acthd)
1266                 dev_priv->hangcheck_count = 0;
1267         else
1268                 dev_priv->hangcheck_count++;
1269
1270         dev_priv->last_acthd = acthd;
1271 }
1272
1273 /* drm_dma.h hooks
1274 */
1275 static void ironlake_irq_preinstall(struct drm_device *dev)
1276 {
1277         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1278
1279         I915_WRITE(HWSTAM, 0xeffe);
1280
1281         /* XXX hotplug from PCH */
1282
1283         I915_WRITE(DEIMR, 0xffffffff);
1284         I915_WRITE(DEIER, 0x0);
1285         (void) I915_READ(DEIER);
1286
1287         /* and GT */
1288         I915_WRITE(GTIMR, 0xffffffff);
1289         I915_WRITE(GTIER, 0x0);
1290         (void) I915_READ(GTIER);
1291
1292         /* south display irq */
1293         I915_WRITE(SDEIMR, 0xffffffff);
1294         I915_WRITE(SDEIER, 0x0);
1295         (void) I915_READ(SDEIER);
1296 }
1297
1298 static int ironlake_irq_postinstall(struct drm_device *dev)
1299 {
1300         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1301         /* enable kind of interrupts always enabled */
1302         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1303                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1304         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1305         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1306                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1307
1308         dev_priv->irq_mask_reg = ~display_mask;
1309         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1310
1311         /* should always can generate irq */
1312         I915_WRITE(DEIIR, I915_READ(DEIIR));
1313         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1314         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1315         (void) I915_READ(DEIER);
1316
1317         /* user interrupt should be enabled, but masked initial */
1318         dev_priv->gt_irq_mask_reg = ~render_mask;
1319         dev_priv->gt_irq_enable_reg = render_mask;
1320
1321         I915_WRITE(GTIIR, I915_READ(GTIIR));
1322         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1323         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1324         (void) I915_READ(GTIER);
1325
1326         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1327         dev_priv->pch_irq_enable_reg = hotplug_mask;
1328
1329         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1330         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1331         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1332         (void) I915_READ(SDEIER);
1333
1334         if (IS_IRONLAKE_M(dev)) {
1335                 /* Clear & enable PCU event interrupts */
1336                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1337                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1338                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1339         }
1340
1341         return 0;
1342 }
1343
1344 void i915_driver_irq_preinstall(struct drm_device * dev)
1345 {
1346         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1347
1348         atomic_set(&dev_priv->irq_received, 0);
1349
1350         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1351         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1352
1353         if (HAS_PCH_SPLIT(dev)) {
1354                 ironlake_irq_preinstall(dev);
1355                 return;
1356         }
1357
1358         if (I915_HAS_HOTPLUG(dev)) {
1359                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1360                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1361         }
1362
1363         I915_WRITE(HWSTAM, 0xeffe);
1364         I915_WRITE(PIPEASTAT, 0);
1365         I915_WRITE(PIPEBSTAT, 0);
1366         I915_WRITE(IMR, 0xffffffff);
1367         I915_WRITE(IER, 0x0);
1368         (void) I915_READ(IER);
1369 }
1370
1371 /*
1372  * Must be called after intel_modeset_init or hotplug interrupts won't be
1373  * enabled correctly.
1374  */
1375 int i915_driver_irq_postinstall(struct drm_device *dev)
1376 {
1377         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1378         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1379         u32 error_mask;
1380
1381         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1382
1383         if (HAS_BSD(dev))
1384                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1385
1386         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1387
1388         if (HAS_PCH_SPLIT(dev))
1389                 return ironlake_irq_postinstall(dev);
1390
1391         /* Unmask the interrupts that we always want on. */
1392         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1393
1394         dev_priv->pipestat[0] = 0;
1395         dev_priv->pipestat[1] = 0;
1396
1397         if (I915_HAS_HOTPLUG(dev)) {
1398                 /* Enable in IER... */
1399                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1400                 /* and unmask in IMR */
1401                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1402         }
1403
1404         /*
1405          * Enable some error detection, note the instruction error mask
1406          * bit is reserved, so we leave it masked.
1407          */
1408         if (IS_G4X(dev)) {
1409                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1410                                GM45_ERROR_MEM_PRIV |
1411                                GM45_ERROR_CP_PRIV |
1412                                I915_ERROR_MEMORY_REFRESH);
1413         } else {
1414                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1415                                I915_ERROR_MEMORY_REFRESH);
1416         }
1417         I915_WRITE(EMR, error_mask);
1418
1419         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1420         I915_WRITE(IER, enable_mask);
1421         (void) I915_READ(IER);
1422
1423         if (I915_HAS_HOTPLUG(dev)) {
1424                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1425
1426                 /* Note HDMI and DP share bits */
1427                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1428                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1429                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1430                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1431                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1432                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1433                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1434                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1435                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1436                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1437                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1438                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1439                 /* Ignore TV since it's buggy */
1440
1441                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1442         }
1443
1444         opregion_enable_asle(dev);
1445
1446         return 0;
1447 }
1448
1449 static void ironlake_irq_uninstall(struct drm_device *dev)
1450 {
1451         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1452         I915_WRITE(HWSTAM, 0xffffffff);
1453
1454         I915_WRITE(DEIMR, 0xffffffff);
1455         I915_WRITE(DEIER, 0x0);
1456         I915_WRITE(DEIIR, I915_READ(DEIIR));
1457
1458         I915_WRITE(GTIMR, 0xffffffff);
1459         I915_WRITE(GTIER, 0x0);
1460         I915_WRITE(GTIIR, I915_READ(GTIIR));
1461 }
1462
1463 void i915_driver_irq_uninstall(struct drm_device * dev)
1464 {
1465         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1466
1467         if (!dev_priv)
1468                 return;
1469
1470         dev_priv->vblank_pipe = 0;
1471
1472         if (HAS_PCH_SPLIT(dev)) {
1473                 ironlake_irq_uninstall(dev);
1474                 return;
1475         }
1476
1477         if (I915_HAS_HOTPLUG(dev)) {
1478                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1479                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1480         }
1481
1482         I915_WRITE(HWSTAM, 0xffffffff);
1483         I915_WRITE(PIPEASTAT, 0);
1484         I915_WRITE(PIPEBSTAT, 0);
1485         I915_WRITE(IMR, 0xffffffff);
1486         I915_WRITE(IER, 0x0);
1487
1488         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1489         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1490         I915_WRITE(IIR, I915_READ(IIR));
1491 }