drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/sysrq.h>
  30 #include <linux/slab.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #define MAX_NOPID ((u32)~0)
  39
  40 /**
  41  * Interrupts that are always left unmasked.
  42  *
  43  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  44  * we leave them always unmasked in IMR and then control enabling them through
  45  * PIPESTAT alone.
  46  */
  47 #define I915_INTERRUPT_ENABLE_FIX                       \
  48         (I915_ASLE_INTERRUPT |                          \
  49          I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |          \
  50          I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |          \
  51          I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |  \
  52          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |  \
  53          I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
  54
  55 /** Interrupts that we mask and unmask at runtime. */
  56 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
  57
  58 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
  59                                  PIPE_VBLANK_INTERRUPT_STATUS)
  60
  61 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
  62                                  PIPE_VBLANK_INTERRUPT_ENABLE)
  63
  64 #define DRM_I915_VBLANK_PIPE_ALL        (DRM_I915_VBLANK_PIPE_A | \
  65                                          DRM_I915_VBLANK_PIPE_B)
  66
  67 void
  68 ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  69 {
  70         if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
  71                 dev_priv->gt_irq_mask_reg &= ~mask;
  72                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  73                 (void) I915_READ(GTIMR);
  74         }
  75 }
  76
  77 void
  78 ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
  79 {
  80         if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
  81                 dev_priv->gt_irq_mask_reg |= mask;
  82                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
  83                 (void) I915_READ(GTIMR);
  84         }
  85 }
  86
  87 /* For display hotplug interrupt */
  88 void
  89 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  90 {
  91         if ((dev_priv->irq_mask_reg & mask) != 0) {
  92                 dev_priv->irq_mask_reg &= ~mask;
  93                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
  94                 (void) I915_READ(DEIMR);
  95         }
  96 }
  97
  98 static inline void
  99 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 100 {
 101         if ((dev_priv->irq_mask_reg & mask) != mask) {
 102                 dev_priv->irq_mask_reg |= mask;
 103                 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
 104                 (void) I915_READ(DEIMR);
 105         }
 106 }
 107
 108 void
 109 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
 110 {
 111         if ((dev_priv->irq_mask_reg & mask) != 0) {
 112                 dev_priv->irq_mask_reg &= ~mask;
 113                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 114                 (void) I915_READ(IMR);
 115         }
 116 }
 117
 118 void
 119 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
 120 {
 121         if ((dev_priv->irq_mask_reg & mask) != mask) {
 122                 dev_priv->irq_mask_reg |= mask;
 123                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 124                 (void) I915_READ(IMR);
 125         }
 126 }
 127
 128 static inline u32
 129 i915_pipestat(int pipe)
 130 {
 131         if (pipe == 0)
 132                 return PIPEASTAT;
 133         if (pipe == 1)
 134                 return PIPEBSTAT;
 135         BUG();
 136 }
 137
 138 void
 139 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 140 {
 141         if ((dev_priv->pipestat[pipe] & mask) != mask) {
 142                 u32 reg = i915_pipestat(pipe);
 143
 144                 dev_priv->pipestat[pipe] |= mask;
 145                 /* Enable the interrupt, clear any pending status */
 146                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
 147                 (void) I915_READ(reg);
 148         }
 149 }
 150
 151 void
 152 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 153 {
 154         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 155                 u32 reg = i915_pipestat(pipe);
 156
 157                 dev_priv->pipestat[pipe] &= ~mask;
 158                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 159                 (void) I915_READ(reg);
 160         }
 161 }
 162
 163 /**
 164  * intel_enable_asle - enable ASLE interrupt for OpRegion
 165  */
 166 void intel_enable_asle (struct drm_device *dev)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169
 170         if (HAS_PCH_SPLIT(dev))
 171                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 172         else {
 173                 i915_enable_pipestat(dev_priv, 1,
 174                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 175                 if (IS_I965G(dev))
 176                         i915_enable_pipestat(dev_priv, 0,
 177                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 178         }
 179 }
 180
 181 /**
 182  * i915_pipe_enabled - check if a pipe is enabled
 183  * @dev: DRM device
 184  * @pipe: pipe to check
 185  *
 186  * Reading certain registers when the pipe is disabled can hang the chip.
 187  * Use this routine to make sure the PLL is running and the pipe is active
 188  * before reading such registers if unsure.
 189  */
 190 static int
 191 i915_pipe_enabled(struct drm_device *dev, int pipe)
 192 {
 193         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 194         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 195
 196         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 197                 return 1;
 198
 199         return 0;
 200 }
 201
 202 /* Called from drm generic code, passed a 'crtc', which
 203  * we use as a pipe index
 204  */
 205 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 206 {
 207         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 208         unsigned long high_frame;
 209         unsigned long low_frame;
 210         u32 high1, high2, low, count;
 211
 212         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 213         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 214
 215         if (!i915_pipe_enabled(dev, pipe)) {
 216                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 217                                 "pipe %d\n", pipe);
 218                 return 0;
 219         }
 220
 221         /*
 222          * High & low register fields aren't synchronized, so make sure
 223          * we get a low value that's stable across two reads of the high
 224          * register.
 225          */
 226         do {
 227                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 228                          PIPE_FRAME_HIGH_SHIFT);
 229                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 230                         PIPE_FRAME_LOW_SHIFT);
 231                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 232                          PIPE_FRAME_HIGH_SHIFT);
 233         } while (high1 != high2);
 234
 235         count = (high1 << 8) | low;
 236
 237         return count;
 238 }
 239
 240 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
 244
 245         if (!i915_pipe_enabled(dev, pipe)) {
 246                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 247                                         "pipe %d\n", pipe);
 248                 return 0;
 249         }
 250
 251         return I915_READ(reg);
 252 }
 253
 254 /*
 255  * Handle hotplug events outside the interrupt handler proper.
 256  */
 257 static void i915_hotplug_work_func(struct work_struct *work)
 258 {
 259         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 260                                                     hotplug_work);
 261         struct drm_device *dev = dev_priv->dev;
 262         struct drm_mode_config *mode_config = &dev->mode_config;
 263         struct drm_encoder *encoder;
 264
 265         if (mode_config->num_encoder) {
 266                 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 267                         struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder);
 268
 269                         if (intel_encoder->hot_plug)
 270                                 (*intel_encoder->hot_plug) (intel_encoder);
 271                 }
 272         }
 273         /* Just fire off a uevent and let userspace tell us what to do */
 274         drm_helper_hpd_irq_event(dev);
 275 }
 276
 277 static void i915_handle_rps_change(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = dev->dev_private;
 280         u32 busy_up, busy_down, max_avg, min_avg;
 281         u8 new_delay = dev_priv->cur_delay;
 282
 283         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 284         busy_up = I915_READ(RCPREVBSYTUPAVG);
 285         busy_down = I915_READ(RCPREVBSYTDNAVG);
 286         max_avg = I915_READ(RCBMAXAVG);
 287         min_avg = I915_READ(RCBMINAVG);
 288
 289         /* Handle RCS change request from hw */
 290         if (busy_up > max_avg) {
 291                 if (dev_priv->cur_delay != dev_priv->max_delay)
 292                         new_delay = dev_priv->cur_delay - 1;
 293                 if (new_delay < dev_priv->max_delay)
 294                         new_delay = dev_priv->max_delay;
 295         } else if (busy_down < min_avg) {
 296                 if (dev_priv->cur_delay != dev_priv->min_delay)
 297                         new_delay = dev_priv->cur_delay + 1;
 298                 if (new_delay > dev_priv->min_delay)
 299                         new_delay = dev_priv->min_delay;
 300         }
 301
 302         if (ironlake_set_drps(dev, new_delay))
 303                 dev_priv->cur_delay = new_delay;
 304
 305         return;
 306 }
 307
 308 irqreturn_t ironlake_irq_handler(struct drm_device *dev)
 309 {
 310         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 311         int ret = IRQ_NONE;
 312         u32 de_iir, gt_iir, de_ier, pch_iir;
 313         struct drm_i915_master_private *master_priv;
 314         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 315
 316         /* disable master interrupt before clearing iir  */
 317         de_ier = I915_READ(DEIER);
 318         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 319         (void)I915_READ(DEIER);
 320
 321         de_iir = I915_READ(DEIIR);
 322         gt_iir = I915_READ(GTIIR);
 323         pch_iir = I915_READ(SDEIIR);
 324
 325         if (de_iir == 0 && gt_iir == 0 && pch_iir == 0)
 326                 goto done;
 327
 328         ret = IRQ_HANDLED;
 329
 330         if (dev->primary->master) {
 331                 master_priv = dev->primary->master->driver_priv;
 332                 if (master_priv->sarea_priv)
 333                         master_priv->sarea_priv->last_dispatch =
 334                                 READ_BREADCRUMB(dev_priv);
 335         }
 336
 337         if (gt_iir & GT_PIPE_NOTIFY) {
 338                 u32 seqno = render_ring->get_gem_seqno(dev, render_ring);
 339                 render_ring->irq_gem_seqno = seqno;
 340                 trace_i915_gem_request_complete(dev, seqno);
 341                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 342                 dev_priv->hangcheck_count = 0;
 343                 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 344         }
 345         if (gt_iir & GT_BSD_USER_INTERRUPT)
 346                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 347
 348
 349         if (de_iir & DE_GSE)
 350                 ironlake_opregion_gse_intr(dev);
 351
 352         if (de_iir & DE_PLANEA_FLIP_DONE) {
 353                 intel_prepare_page_flip(dev, 0);
 354                 intel_finish_page_flip(dev, 0);
 355         }
 356
 357         if (de_iir & DE_PLANEB_FLIP_DONE) {
 358                 intel_prepare_page_flip(dev, 1);
 359                 intel_finish_page_flip(dev, 1);
 360         }
 361
 362         if (de_iir & DE_PIPEA_VBLANK)
 363                 drm_handle_vblank(dev, 0);
 364
 365         if (de_iir & DE_PIPEB_VBLANK)
 366                 drm_handle_vblank(dev, 1);
 367
 368         /* check event from PCH */
 369         if ((de_iir & DE_PCH_EVENT) &&
 370             (pch_iir & SDE_HOTPLUG_MASK)) {
 371                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 372         }
 373
 374         if (de_iir & DE_PCU_EVENT) {
 375                 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 376                 i915_handle_rps_change(dev);
 377         }
 378
 379         /* should clear PCH hotplug event before clear CPU irq */
 380         I915_WRITE(SDEIIR, pch_iir);
 381         I915_WRITE(GTIIR, gt_iir);
 382         I915_WRITE(DEIIR, de_iir);
 383
 384 done:
 385         I915_WRITE(DEIER, de_ier);
 386         (void)I915_READ(DEIER);
 387
 388         return ret;
 389 }
 390
 391 /**
 392  * i915_error_work_func - do process context error handling work
 393  * @work: work struct
 394  *
 395  * Fire an error uevent so userspace can see that a hang or error
 396  * was detected.
 397  */
 398 static void i915_error_work_func(struct work_struct *work)
 399 {
 400         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 401                                                     error_work);
 402         struct drm_device *dev = dev_priv->dev;
 403         char *error_event[] = { "ERROR=1", NULL };
 404         char *reset_event[] = { "RESET=1", NULL };
 405         char *reset_done_event[] = { "ERROR=0", NULL };
 406
 407         DRM_DEBUG_DRIVER("generating error event\n");
 408         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 409
 410         if (atomic_read(&dev_priv->mm.wedged)) {
 411                 if (IS_I965G(dev)) {
 412                         DRM_DEBUG_DRIVER("resetting chip\n");
 413                         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
 414                         if (!i965_reset(dev, GDRST_RENDER)) {
 415                                 atomic_set(&dev_priv->mm.wedged, 0);
 416                                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
 417                         }
 418                 } else {
 419                         DRM_DEBUG_DRIVER("reboot required\n");
 420                 }
 421         }
 422 }
 423
 424 static struct drm_i915_error_object *
 425 i915_error_object_create(struct drm_device *dev,
 426                          struct drm_gem_object *src)
 427 {
 428         drm_i915_private_t *dev_priv = dev->dev_private;
 429         struct drm_i915_error_object *dst;
 430         struct drm_i915_gem_object *src_priv;
 431         int page, page_count;
 432         u32 reloc_offset;
 433
 434         if (src == NULL)
 435                 return NULL;
 436
 437         src_priv = to_intel_bo(src);
 438         if (src_priv->pages == NULL)
 439                 return NULL;
 440
 441         page_count = src->size / PAGE_SIZE;
 442
 443         dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
 444         if (dst == NULL)
 445                 return NULL;
 446
 447         reloc_offset = src_priv->gtt_offset;
 448         for (page = 0; page < page_count; page++) {
 449                 unsigned long flags;
 450                 void __iomem *s;
 451                 void *d;
 452
 453                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 454                 if (d == NULL)
 455                         goto unwind;
 456
 457                 local_irq_save(flags);
 458                 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
 459                                              reloc_offset,
 460                                              KM_IRQ0);
 461                 memcpy_fromio(d, s, PAGE_SIZE);
 462                 io_mapping_unmap_atomic(s, KM_IRQ0);
 463                 local_irq_restore(flags);
 464
 465                 dst->pages[page] = d;
 466
 467                 reloc_offset += PAGE_SIZE;
 468         }
 469         dst->page_count = page_count;
 470         dst->gtt_offset = src_priv->gtt_offset;
 471
 472         return dst;
 473
 474 unwind:
 475         while (page--)
 476                 kfree(dst->pages[page]);
 477         kfree(dst);
 478         return NULL;
 479 }
 480
 481 static void
 482 i915_error_object_free(struct drm_i915_error_object *obj)
 483 {
 484         int page;
 485
 486         if (obj == NULL)
 487                 return;
 488
 489         for (page = 0; page < obj->page_count; page++)
 490                 kfree(obj->pages[page]);
 491
 492         kfree(obj);
 493 }
 494
 495 static void
 496 i915_error_state_free(struct drm_device *dev,
 497                       struct drm_i915_error_state *error)
 498 {
 499         i915_error_object_free(error->batchbuffer[0]);
 500         i915_error_object_free(error->batchbuffer[1]);
 501         i915_error_object_free(error->ringbuffer);
 502         kfree(error->active_bo);
 503         kfree(error->overlay);
 504         kfree(error);
 505 }
 506
 507 static u32
 508 i915_get_bbaddr(struct drm_device *dev, u32 *ring)
 509 {
 510         u32 cmd;
 511
 512         if (IS_I830(dev) || IS_845G(dev))
 513                 cmd = MI_BATCH_BUFFER;
 514         else if (IS_I965G(dev))
 515                 cmd = (MI_BATCH_BUFFER_START | (2 << 6) |
 516                        MI_BATCH_NON_SECURE_I965);
 517         else
 518                 cmd = (MI_BATCH_BUFFER_START | (2 << 6));
 519
 520         return ring[0] == cmd ? ring[1] : 0;
 521 }
 522
 523 static u32
 524 i915_ringbuffer_last_batch(struct drm_device *dev)
 525 {
 526         struct drm_i915_private *dev_priv = dev->dev_private;
 527         u32 head, bbaddr;
 528         u32 *ring;
 529
 530         /* Locate the current position in the ringbuffer and walk back
 531          * to find the most recently dispatched batch buffer.
 532          */
 533         bbaddr = 0;
 534         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 535         ring = (u32 *)(dev_priv->render_ring.virtual_start + head);
 536
 537         while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 538                 bbaddr = i915_get_bbaddr(dev, ring);
 539                 if (bbaddr)
 540                         break;
 541         }
 542
 543         if (bbaddr == 0) {
 544                 ring = (u32 *)(dev_priv->render_ring.virtual_start
 545                                 + dev_priv->render_ring.size);
 546                 while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) {
 547                         bbaddr = i915_get_bbaddr(dev, ring);
 548                         if (bbaddr)
 549                                 break;
 550                 }
 551         }
 552
 553         return bbaddr;
 554 }
 555
 556 /**
 557  * i915_capture_error_state - capture an error record for later analysis
 558  * @dev: drm device
 559  *
 560  * Should be called when an error is detected (either a hang or an error
 561  * interrupt) to capture error state from the time of the error.  Fills
 562  * out a structure which becomes available in debugfs for user level tools
 563  * to pick up.
 564  */
 565 static void i915_capture_error_state(struct drm_device *dev)
 566 {
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct drm_i915_gem_object *obj_priv;
 569         struct drm_i915_error_state *error;
 570         struct drm_gem_object *batchbuffer[2];
 571         unsigned long flags;
 572         u32 bbaddr;
 573         int count;
 574
 575         spin_lock_irqsave(&dev_priv->error_lock, flags);
 576         error = dev_priv->first_error;
 577         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 578         if (error)
 579                 return;
 580
 581         error = kmalloc(sizeof(*error), GFP_ATOMIC);
 582         if (!error) {
 583                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
 584                 return;
 585         }
 586
 587         error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring);
 588         error->eir = I915_READ(EIR);
 589         error->pgtbl_er = I915_READ(PGTBL_ER);
 590         error->pipeastat = I915_READ(PIPEASTAT);
 591         error->pipebstat = I915_READ(PIPEBSTAT);
 592         error->instpm = I915_READ(INSTPM);
 593         if (!IS_I965G(dev)) {
 594                 error->ipeir = I915_READ(IPEIR);
 595                 error->ipehr = I915_READ(IPEHR);
 596                 error->instdone = I915_READ(INSTDONE);
 597                 error->acthd = I915_READ(ACTHD);
 598                 error->bbaddr = 0;
 599         } else {
 600                 error->ipeir = I915_READ(IPEIR_I965);
 601                 error->ipehr = I915_READ(IPEHR_I965);
 602                 error->instdone = I915_READ(INSTDONE_I965);
 603                 error->instps = I915_READ(INSTPS);
 604                 error->instdone1 = I915_READ(INSTDONE1);
 605                 error->acthd = I915_READ(ACTHD_I965);
 606                 error->bbaddr = I915_READ64(BB_ADDR);
 607         }
 608
 609         bbaddr = i915_ringbuffer_last_batch(dev);
 610
 611         /* Grab the current batchbuffer, most likely to have crashed. */
 612         batchbuffer[0] = NULL;
 613         batchbuffer[1] = NULL;
 614         count = 0;
 615         list_for_each_entry(obj_priv,
 616                         &dev_priv->render_ring.active_list, list) {
 617
 618                 struct drm_gem_object *obj = &obj_priv->base;
 619
 620                 if (batchbuffer[0] == NULL &&
 621                     bbaddr >= obj_priv->gtt_offset &&
 622                     bbaddr < obj_priv->gtt_offset + obj->size)
 623                         batchbuffer[0] = obj;
 624
 625                 if (batchbuffer[1] == NULL &&
 626                     error->acthd >= obj_priv->gtt_offset &&
 627                     error->acthd < obj_priv->gtt_offset + obj->size)
 628                         batchbuffer[1] = obj;
 629
 630                 count++;
 631         }
 632         /* Scan the other lists for completeness for those bizarre errors. */
 633         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 634                 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
 635                         struct drm_gem_object *obj = &obj_priv->base;
 636
 637                         if (batchbuffer[0] == NULL &&
 638                             bbaddr >= obj_priv->gtt_offset &&
 639                             bbaddr < obj_priv->gtt_offset + obj->size)
 640                                 batchbuffer[0] = obj;
 641
 642                         if (batchbuffer[1] == NULL &&
 643                             error->acthd >= obj_priv->gtt_offset &&
 644                             error->acthd < obj_priv->gtt_offset + obj->size)
 645                                 batchbuffer[1] = obj;
 646
 647                         if (batchbuffer[0] && batchbuffer[1])
 648                                 break;
 649                 }
 650         }
 651         if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) {
 652                 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 653                         struct drm_gem_object *obj = &obj_priv->base;
 654
 655                         if (batchbuffer[0] == NULL &&
 656                             bbaddr >= obj_priv->gtt_offset &&
 657                             bbaddr < obj_priv->gtt_offset + obj->size)
 658                                 batchbuffer[0] = obj;
 659
 660                         if (batchbuffer[1] == NULL &&
 661                             error->acthd >= obj_priv->gtt_offset &&
 662                             error->acthd < obj_priv->gtt_offset + obj->size)
 663                                 batchbuffer[1] = obj;
 664
 665                         if (batchbuffer[0] && batchbuffer[1])
 666                                 break;
 667                 }
 668         }
 669
 670         /* We need to copy these to an anonymous buffer as the simplest
 671          * method to avoid being overwritten by userpace.
 672          */
 673         error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]);
 674         if (batchbuffer[1] != batchbuffer[0])
 675                 error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]);
 676         else
 677                 error->batchbuffer[1] = NULL;
 678
 679         /* Record the ringbuffer */
 680         error->ringbuffer = i915_error_object_create(dev,
 681                         dev_priv->render_ring.gem_object);
 682
 683         /* Record buffers on the active list. */
 684         error->active_bo = NULL;
 685         error->active_bo_count = 0;
 686
 687         if (count)
 688                 error->active_bo = kmalloc(sizeof(*error->active_bo)*count,
 689                                            GFP_ATOMIC);
 690
 691         if (error->active_bo) {
 692                 int i = 0;
 693                 list_for_each_entry(obj_priv,
 694                                 &dev_priv->render_ring.active_list, list) {
 695                         struct drm_gem_object *obj = &obj_priv->base;
 696
 697                         error->active_bo[i].size = obj->size;
 698                         error->active_bo[i].name = obj->name;
 699                         error->active_bo[i].seqno = obj_priv->last_rendering_seqno;
 700                         error->active_bo[i].gtt_offset = obj_priv->gtt_offset;
 701                         error->active_bo[i].read_domains = obj->read_domains;
 702                         error->active_bo[i].write_domain = obj->write_domain;
 703                         error->active_bo[i].fence_reg = obj_priv->fence_reg;
 704                         error->active_bo[i].pinned = 0;
 705                         if (obj_priv->pin_count > 0)
 706                                 error->active_bo[i].pinned = 1;
 707                         if (obj_priv->user_pin_count > 0)
 708                                 error->active_bo[i].pinned = -1;
 709                         error->active_bo[i].tiling = obj_priv->tiling_mode;
 710                         error->active_bo[i].dirty = obj_priv->dirty;
 711                         error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED;
 712
 713                         if (++i == count)
 714                                 break;
 715                 }
 716                 error->active_bo_count = i;
 717         }
 718
 719         do_gettimeofday(&error->time);
 720
 721         error->overlay = intel_overlay_capture_error_state(dev);
 722
 723         spin_lock_irqsave(&dev_priv->error_lock, flags);
 724         if (dev_priv->first_error == NULL) {
 725                 dev_priv->first_error = error;
 726                 error = NULL;
 727         }
 728         spin_unlock_irqrestore(&dev_priv->error_lock, flags);
 729
 730         if (error)
 731                 i915_error_state_free(dev, error);
 732 }
 733
 734 void i915_destroy_error_state(struct drm_device *dev)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         struct drm_i915_error_state *error;
 738
 739         spin_lock(&dev_priv->error_lock);
 740         error = dev_priv->first_error;
 741         dev_priv->first_error = NULL;
 742         spin_unlock(&dev_priv->error_lock);
 743
 744         if (error)
 745                 i915_error_state_free(dev, error);
 746 }
 747
 748 static void i915_report_and_clear_eir(struct drm_device *dev)
 749 {
 750         struct drm_i915_private *dev_priv = dev->dev_private;
 751         u32 eir = I915_READ(EIR);
 752
 753         if (!eir)
 754                 return;
 755
 756         printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
 757                eir);
 758
 759         if (IS_G4X(dev)) {
 760                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
 761                         u32 ipeir = I915_READ(IPEIR_I965);
 762
 763                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 764                                I915_READ(IPEIR_I965));
 765                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 766                                I915_READ(IPEHR_I965));
 767                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 768                                I915_READ(INSTDONE_I965));
 769                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 770                                I915_READ(INSTPS));
 771                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 772                                I915_READ(INSTDONE1));
 773                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 774                                I915_READ(ACTHD_I965));
 775                         I915_WRITE(IPEIR_I965, ipeir);
 776                         (void)I915_READ(IPEIR_I965);
 777                 }
 778                 if (eir & GM45_ERROR_PAGE_TABLE) {
 779                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 780                         printk(KERN_ERR "page table error\n");
 781                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 782                                pgtbl_err);
 783                         I915_WRITE(PGTBL_ER, pgtbl_err);
 784                         (void)I915_READ(PGTBL_ER);
 785                 }
 786         }
 787
 788         if (IS_I9XX(dev)) {
 789                 if (eir & I915_ERROR_PAGE_TABLE) {
 790                         u32 pgtbl_err = I915_READ(PGTBL_ER);
 791                         printk(KERN_ERR "page table error\n");
 792                         printk(KERN_ERR "  PGTBL_ER: 0x%08x\n",
 793                                pgtbl_err);
 794                         I915_WRITE(PGTBL_ER, pgtbl_err);
 795                         (void)I915_READ(PGTBL_ER);
 796                 }
 797         }
 798
 799         if (eir & I915_ERROR_MEMORY_REFRESH) {
 800                 u32 pipea_stats = I915_READ(PIPEASTAT);
 801                 u32 pipeb_stats = I915_READ(PIPEBSTAT);
 802
 803                 printk(KERN_ERR "memory refresh error\n");
 804                 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
 805                        pipea_stats);
 806                 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
 807                        pipeb_stats);
 808                 /* pipestat has already been acked */
 809         }
 810         if (eir & I915_ERROR_INSTRUCTION) {
 811                 printk(KERN_ERR "instruction error\n");
 812                 printk(KERN_ERR "  INSTPM: 0x%08x\n",
 813                        I915_READ(INSTPM));
 814                 if (!IS_I965G(dev)) {
 815                         u32 ipeir = I915_READ(IPEIR);
 816
 817                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 818                                I915_READ(IPEIR));
 819                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 820                                I915_READ(IPEHR));
 821                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 822                                I915_READ(INSTDONE));
 823                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 824                                I915_READ(ACTHD));
 825                         I915_WRITE(IPEIR, ipeir);
 826                         (void)I915_READ(IPEIR);
 827                 } else {
 828                         u32 ipeir = I915_READ(IPEIR_I965);
 829
 830                         printk(KERN_ERR "  IPEIR: 0x%08x\n",
 831                                I915_READ(IPEIR_I965));
 832                         printk(KERN_ERR "  IPEHR: 0x%08x\n",
 833                                I915_READ(IPEHR_I965));
 834                         printk(KERN_ERR "  INSTDONE: 0x%08x\n",
 835                                I915_READ(INSTDONE_I965));
 836                         printk(KERN_ERR "  INSTPS: 0x%08x\n",
 837                                I915_READ(INSTPS));
 838                         printk(KERN_ERR "  INSTDONE1: 0x%08x\n",
 839                                I915_READ(INSTDONE1));
 840                         printk(KERN_ERR "  ACTHD: 0x%08x\n",
 841                                I915_READ(ACTHD_I965));
 842                         I915_WRITE(IPEIR_I965, ipeir);
 843                         (void)I915_READ(IPEIR_I965);
 844                 }
 845         }
 846
 847         I915_WRITE(EIR, eir);
 848         (void)I915_READ(EIR);
 849         eir = I915_READ(EIR);
 850         if (eir) {
 851                 /*
 852                  * some errors might have become stuck,
 853                  * mask them.
 854                  */
 855                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
 856                 I915_WRITE(EMR, I915_READ(EMR) | eir);
 857                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
 858         }
 859 }
 860
 861 /**
 862  * i915_handle_error - handle an error interrupt
 863  * @dev: drm device
 864  *
 865  * Do some basic checking of regsiter state at error interrupt time and
 866  * dump it to the syslog.  Also call i915_capture_error_state() to make
 867  * sure we get a record and make it available in debugfs.  Fire a uevent
 868  * so userspace knows something bad happened (should trigger collection
 869  * of a ring dump etc.).
 870  */
 871 static void i915_handle_error(struct drm_device *dev, bool wedged)
 872 {
 873         struct drm_i915_private *dev_priv = dev->dev_private;
 874
 875         i915_capture_error_state(dev);
 876         i915_report_and_clear_eir(dev);
 877
 878         if (wedged) {
 879                 atomic_set(&dev_priv->mm.wedged, 1);
 880
 881                 /*
 882                  * Wakeup waiting processes so they don't hang
 883                  */
 884                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 885         }
 886
 887         queue_work(dev_priv->wq, &dev_priv->error_work);
 888 }
 889
 890 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 891 {
 892         struct drm_device *dev = (struct drm_device *) arg;
 893         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 894         struct drm_i915_master_private *master_priv;
 895         u32 iir, new_iir;
 896         u32 pipea_stats, pipeb_stats;
 897         u32 vblank_status;
 898         int vblank = 0;
 899         unsigned long irqflags;
 900         int irq_received;
 901         int ret = IRQ_NONE;
 902         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
 903
 904         atomic_inc(&dev_priv->irq_received);
 905
 906         if (HAS_PCH_SPLIT(dev))
 907                 return ironlake_irq_handler(dev);
 908
 909         iir = I915_READ(IIR);
 910
 911         if (IS_I965G(dev))
 912                 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
 913         else
 914                 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
 915
 916         for (;;) {
 917                 irq_received = iir != 0;
 918
 919                 /* Can't rely on pipestat interrupt bit in iir as it might
 920                  * have been cleared after the pipestat interrupt was received.
 921                  * It doesn't set the bit in iir again, but it still produces
 922                  * interrupts (for non-MSI).
 923                  */
 924                 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 925                 pipea_stats = I915_READ(PIPEASTAT);
 926                 pipeb_stats = I915_READ(PIPEBSTAT);
 927
 928                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
 929                         i915_handle_error(dev, false);
 930
 931                 /*
 932                  * Clear the PIPE(A|B)STAT regs before the IIR
 933                  */
 934                 if (pipea_stats & 0x8000ffff) {
 935                         if (pipea_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 936                                 DRM_DEBUG_DRIVER("pipe a underrun\n");
 937                         I915_WRITE(PIPEASTAT, pipea_stats);
 938                         irq_received = 1;
 939                 }
 940
 941                 if (pipeb_stats & 0x8000ffff) {
 942                         if (pipeb_stats &  PIPE_FIFO_UNDERRUN_STATUS)
 943                                 DRM_DEBUG_DRIVER("pipe b underrun\n");
 944                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 945                         irq_received = 1;
 946                 }
 947                 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 948
 949                 if (!irq_received)
 950                         break;
 951
 952                 ret = IRQ_HANDLED;
 953
 954                 /* Consume port.  Then clear IIR or we'll miss events */
 955                 if ((I915_HAS_HOTPLUG(dev)) &&
 956                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
 957                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 958
 959                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 960                                   hotplug_status);
 961                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 962                                 queue_work(dev_priv->wq,
 963                                            &dev_priv->hotplug_work);
 964
 965                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 966                         I915_READ(PORT_HOTPLUG_STAT);
 967                 }
 968
 969                 I915_WRITE(IIR, iir);
 970                 new_iir = I915_READ(IIR); /* Flush posted writes */
 971
 972                 if (dev->primary->master) {
 973                         master_priv = dev->primary->master->driver_priv;
 974                         if (master_priv->sarea_priv)
 975                                 master_priv->sarea_priv->last_dispatch =
 976                                         READ_BREADCRUMB(dev_priv);
 977                 }
 978
 979                 if (iir & I915_USER_INTERRUPT) {
 980                         u32 seqno =
 981                                 render_ring->get_gem_seqno(dev, render_ring);
 982                         render_ring->irq_gem_seqno = seqno;
 983                         trace_i915_gem_request_complete(dev, seqno);
 984                         DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
 985                         dev_priv->hangcheck_count = 0;
 986                         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
 987                 }
 988
 989                 if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT))
 990                         DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
 991
 992                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
 993                         intel_prepare_page_flip(dev, 0);
 994                         if (dev_priv->flip_pending_is_done)
 995                                 intel_finish_page_flip_plane(dev, 0);
 996                 }
 997
 998                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
 999                         intel_prepare_page_flip(dev, 1);
1000                         if (dev_priv->flip_pending_is_done)
1001                                 intel_finish_page_flip_plane(dev, 1);
1002                 }
1003
1004                 if (pipea_stats & vblank_status) {
1005                         vblank++;
1006                         drm_handle_vblank(dev, 0);
1007                         if (!dev_priv->flip_pending_is_done)
1008                                 intel_finish_page_flip(dev, 0);
1009                 }
1010
1011                 if (pipeb_stats & vblank_status) {
1012                         vblank++;
1013                         drm_handle_vblank(dev, 1);
1014                         if (!dev_priv->flip_pending_is_done)
1015                                 intel_finish_page_flip(dev, 1);
1016                 }
1017
1018                 if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1019                     (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
1020                     (iir & I915_ASLE_INTERRUPT))
1021                         opregion_asle_intr(dev);
1022
1023                 /* With MSI, interrupts are only generated when iir
1024                  * transitions from zero to nonzero.  If another bit got
1025                  * set while we were handling the existing iir bits, then
1026                  * we would never get another interrupt.
1027                  *
1028                  * This is fine on non-MSI as well, as if we hit this path
1029                  * we avoid exiting the interrupt handler only to generate
1030                  * another one.
1031                  *
1032                  * Note that for MSI this could cause a stray interrupt report
1033                  * if an interrupt landed in the time between writing IIR and
1034                  * the posting read.  This should be rare enough to never
1035                  * trigger the 99% of 100,000 interrupts test for disabling
1036                  * stray interrupts.
1037                  */
1038                 iir = new_iir;
1039         }
1040
1041         return ret;
1042 }
1043
1044 static int i915_emit_irq(struct drm_device * dev)
1045 {
1046         drm_i915_private_t *dev_priv = dev->dev_private;
1047         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1048
1049         i915_kernel_lost_context(dev);
1050
1051         DRM_DEBUG_DRIVER("\n");
1052
1053         dev_priv->counter++;
1054         if (dev_priv->counter > 0x7FFFFFFFUL)
1055                 dev_priv->counter = 1;
1056         if (master_priv->sarea_priv)
1057                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
1058
1059         BEGIN_LP_RING(4);
1060         OUT_RING(MI_STORE_DWORD_INDEX);
1061         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1062         OUT_RING(dev_priv->counter);
1063         OUT_RING(MI_USER_INTERRUPT);
1064         ADVANCE_LP_RING();
1065
1066         return dev_priv->counter;
1067 }
1068
1069 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
1070 {
1071         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1072         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1073
1074         if (dev_priv->trace_irq_seqno == 0)
1075                 render_ring->user_irq_get(dev, render_ring);
1076
1077         dev_priv->trace_irq_seqno = seqno;
1078 }
1079
1080 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1081 {
1082         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1083         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1084         int ret = 0;
1085         struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
1086
1087         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1088                   READ_BREADCRUMB(dev_priv));
1089
1090         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
1091                 if (master_priv->sarea_priv)
1092                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1093                 return 0;
1094         }
1095
1096         if (master_priv->sarea_priv)
1097                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1098
1099         render_ring->user_irq_get(dev, render_ring);
1100         DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ,
1101                     READ_BREADCRUMB(dev_priv) >= irq_nr);
1102         render_ring->user_irq_put(dev, render_ring);
1103
1104         if (ret == -EBUSY) {
1105                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1106                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1107         }
1108
1109         return ret;
1110 }
1111
1112 /* Needs the lock as it touches the ring.
1113  */
1114 int i915_irq_emit(struct drm_device *dev, void *data,
1115                          struct drm_file *file_priv)
1116 {
1117         drm_i915_private_t *dev_priv = dev->dev_private;
1118         drm_i915_irq_emit_t *emit = data;
1119         int result;
1120
1121         if (!dev_priv || !dev_priv->render_ring.virtual_start) {
1122                 DRM_ERROR("called with no initialization\n");
1123                 return -EINVAL;
1124         }
1125
1126         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1127
1128         mutex_lock(&dev->struct_mutex);
1129         result = i915_emit_irq(dev);
1130         mutex_unlock(&dev->struct_mutex);
1131
1132         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1133                 DRM_ERROR("copy_to_user\n");
1134                 return -EFAULT;
1135         }
1136
1137         return 0;
1138 }
1139
1140 /* Doesn't need the hardware lock.
1141  */
1142 int i915_irq_wait(struct drm_device *dev, void *data,
1143                          struct drm_file *file_priv)
1144 {
1145         drm_i915_private_t *dev_priv = dev->dev_private;
1146         drm_i915_irq_wait_t *irqwait = data;
1147
1148         if (!dev_priv) {
1149                 DRM_ERROR("called with no initialization\n");
1150                 return -EINVAL;
1151         }
1152
1153         return i915_wait_irq(dev, irqwait->irq_seq);
1154 }
1155
1156 /* Called from drm generic code, passed 'crtc' which
1157  * we use as a pipe index
1158  */
1159 int i915_enable_vblank(struct drm_device *dev, int pipe)
1160 {
1161         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1162         unsigned long irqflags;
1163         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1164         u32 pipeconf;
1165
1166         pipeconf = I915_READ(pipeconf_reg);
1167         if (!(pipeconf & PIPEACONF_ENABLE))
1168                 return -EINVAL;
1169
1170         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1171         if (HAS_PCH_SPLIT(dev))
1172                 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1173                                             DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1174         else if (IS_I965G(dev))
1175                 i915_enable_pipestat(dev_priv, pipe,
1176                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1177         else
1178                 i915_enable_pipestat(dev_priv, pipe,
1179                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1180         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1181         return 0;
1182 }
1183
1184 /* Called from drm generic code, passed 'crtc' which
1185  * we use as a pipe index
1186  */
1187 void i915_disable_vblank(struct drm_device *dev, int pipe)
1188 {
1189         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1190         unsigned long irqflags;
1191
1192         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
1193         if (HAS_PCH_SPLIT(dev))
1194                 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1195                                              DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1196         else
1197                 i915_disable_pipestat(dev_priv, pipe,
1198                                       PIPE_VBLANK_INTERRUPT_ENABLE |
1199                                       PIPE_START_VBLANK_INTERRUPT_ENABLE);
1200         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
1201 }
1202
1203 void i915_enable_interrupt (struct drm_device *dev)
1204 {
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206
1207         if (!HAS_PCH_SPLIT(dev))
1208                 opregion_enable_asle(dev);
1209         dev_priv->irq_enabled = 1;
1210 }
1211
1212
1213 /* Set the vblank monitor pipe
1214  */
1215 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1216                          struct drm_file *file_priv)
1217 {
1218         drm_i915_private_t *dev_priv = dev->dev_private;
1219
1220         if (!dev_priv) {
1221                 DRM_ERROR("called with no initialization\n");
1222                 return -EINVAL;
1223         }
1224
1225         return 0;
1226 }
1227
1228 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1229                          struct drm_file *file_priv)
1230 {
1231         drm_i915_private_t *dev_priv = dev->dev_private;
1232         drm_i915_vblank_pipe_t *pipe = data;
1233
1234         if (!dev_priv) {
1235                 DRM_ERROR("called with no initialization\n");
1236                 return -EINVAL;
1237         }
1238
1239         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1240
1241         return 0;
1242 }
1243
1244 /**
1245  * Schedule buffer swap at given vertical blank.
1246  */
1247 int i915_vblank_swap(struct drm_device *dev, void *data,
1248                      struct drm_file *file_priv)
1249 {
1250         /* The delayed swap mechanism was fundamentally racy, and has been
1251          * removed.  The model was that the client requested a delayed flip/swap
1252          * from the kernel, then waited for vblank before continuing to perform
1253          * rendering.  The problem was that the kernel might wake the client
1254          * up before it dispatched the vblank swap (since the lock has to be
1255          * held while touching the ringbuffer), in which case the client would
1256          * clear and start the next frame before the swap occurred, and
1257          * flicker would occur in addition to likely missing the vblank.
1258          *
1259          * In the absence of this ioctl, userland falls back to a correct path
1260          * of waiting for a vblank, then dispatching the swap on its own.
1261          * Context switching to userland and back is plenty fast enough for
1262          * meeting the requirements of vblank swapping.
1263          */
1264         return -EINVAL;
1265 }
1266
1267 struct drm_i915_gem_request *
1268 i915_get_tail_request(struct drm_device *dev)
1269 {
1270         drm_i915_private_t *dev_priv = dev->dev_private;
1271         return list_entry(dev_priv->render_ring.request_list.prev,
1272                         struct drm_i915_gem_request, list);
1273 }
1274
1275 /**
1276  * This is called when the chip hasn't reported back with completed
1277  * batchbuffers in a long time. The first time this is called we simply record
1278  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1279  * again, we assume the chip is wedged and try to fix it.
1280  */
1281 void i915_hangcheck_elapsed(unsigned long data)
1282 {
1283         struct drm_device *dev = (struct drm_device *)data;
1284         drm_i915_private_t *dev_priv = dev->dev_private;
1285         uint32_t acthd, instdone, instdone1;
1286
1287         /* No reset support on this chip yet. */
1288         if (IS_GEN6(dev))
1289                 return;
1290
1291         if (!IS_I965G(dev)) {
1292                 acthd = I915_READ(ACTHD);
1293                 instdone = I915_READ(INSTDONE);
1294                 instdone1 = 0;
1295         } else {
1296                 acthd = I915_READ(ACTHD_I965);
1297                 instdone = I915_READ(INSTDONE_I965);
1298                 instdone1 = I915_READ(INSTDONE1);
1299         }
1300
1301         /* If all work is done then ACTHD clearly hasn't advanced. */
1302         if (list_empty(&dev_priv->render_ring.request_list) ||
1303                 i915_seqno_passed(i915_get_gem_seqno(dev,
1304                                 &dev_priv->render_ring),
1305                         i915_get_tail_request(dev)->seqno)) {
1306                 dev_priv->hangcheck_count = 0;
1307
1308                 /* Issue a wake-up to catch stuck h/w. */
1309                 if (dev_priv->render_ring.waiting_gem_seqno |
1310                     dev_priv->bsd_ring.waiting_gem_seqno) {
1311                         DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n");
1312                         if (dev_priv->render_ring.waiting_gem_seqno)
1313                                 DRM_WAKEUP(&dev_priv->render_ring.irq_queue);
1314                         if (dev_priv->bsd_ring.waiting_gem_seqno)
1315                                 DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue);
1316                 }
1317                 return;
1318         }
1319
1320         if (dev_priv->last_acthd == acthd &&
1321             dev_priv->last_instdone == instdone &&
1322             dev_priv->last_instdone1 == instdone1) {
1323                 if (dev_priv->hangcheck_count++ > 1) {
1324                         DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1325                         i915_handle_error(dev, true);
1326                         return;
1327                 }
1328         } else {
1329                 dev_priv->hangcheck_count = 0;
1330
1331                 dev_priv->last_acthd = acthd;
1332                 dev_priv->last_instdone = instdone;
1333                 dev_priv->last_instdone1 = instdone1;
1334         }
1335
1336         /* Reset timer case chip hangs without another request being added */
1337         mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1338 }
1339
1340 /* drm_dma.h hooks
1341 */
1342 static void ironlake_irq_preinstall(struct drm_device *dev)
1343 {
1344         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1345
1346         I915_WRITE(HWSTAM, 0xeffe);
1347
1348         /* XXX hotplug from PCH */
1349
1350         I915_WRITE(DEIMR, 0xffffffff);
1351         I915_WRITE(DEIER, 0x0);
1352         (void) I915_READ(DEIER);
1353
1354         /* and GT */
1355         I915_WRITE(GTIMR, 0xffffffff);
1356         I915_WRITE(GTIER, 0x0);
1357         (void) I915_READ(GTIER);
1358
1359         /* south display irq */
1360         I915_WRITE(SDEIMR, 0xffffffff);
1361         I915_WRITE(SDEIER, 0x0);
1362         (void) I915_READ(SDEIER);
1363 }
1364
1365 static int ironlake_irq_postinstall(struct drm_device *dev)
1366 {
1367         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1368         /* enable kind of interrupts always enabled */
1369         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1370                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1371         u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT;
1372         u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
1373                            SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
1374
1375         dev_priv->irq_mask_reg = ~display_mask;
1376         dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK;
1377
1378         /* should always can generate irq */
1379         I915_WRITE(DEIIR, I915_READ(DEIIR));
1380         I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1381         I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1382         (void) I915_READ(DEIER);
1383
1384         /* Gen6 only needs render pipe_control now */
1385         if (IS_GEN6(dev))
1386                 render_mask = GT_PIPE_NOTIFY;
1387
1388         dev_priv->gt_irq_mask_reg = ~render_mask;
1389         dev_priv->gt_irq_enable_reg = render_mask;
1390
1391         I915_WRITE(GTIIR, I915_READ(GTIIR));
1392         I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1393         if (IS_GEN6(dev))
1394                 I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT);
1395         I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1396         (void) I915_READ(GTIER);
1397
1398         dev_priv->pch_irq_mask_reg = ~hotplug_mask;
1399         dev_priv->pch_irq_enable_reg = hotplug_mask;
1400
1401         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1402         I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg);
1403         I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg);
1404         (void) I915_READ(SDEIER);
1405
1406         if (IS_IRONLAKE_M(dev)) {
1407                 /* Clear & enable PCU event interrupts */
1408                 I915_WRITE(DEIIR, DE_PCU_EVENT);
1409                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1410                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1411         }
1412
1413         return 0;
1414 }
1415
1416 void i915_driver_irq_preinstall(struct drm_device * dev)
1417 {
1418         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1419
1420         atomic_set(&dev_priv->irq_received, 0);
1421
1422         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1423         INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1424
1425         if (HAS_PCH_SPLIT(dev)) {
1426                 ironlake_irq_preinstall(dev);
1427                 return;
1428         }
1429
1430         if (I915_HAS_HOTPLUG(dev)) {
1431                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1432                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1433         }
1434
1435         I915_WRITE(HWSTAM, 0xeffe);
1436         I915_WRITE(PIPEASTAT, 0);
1437         I915_WRITE(PIPEBSTAT, 0);
1438         I915_WRITE(IMR, 0xffffffff);
1439         I915_WRITE(IER, 0x0);
1440         (void) I915_READ(IER);
1441 }
1442
1443 /*
1444  * Must be called after intel_modeset_init or hotplug interrupts won't be
1445  * enabled correctly.
1446  */
1447 int i915_driver_irq_postinstall(struct drm_device *dev)
1448 {
1449         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1450         u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1451         u32 error_mask;
1452
1453         DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue);
1454
1455         if (HAS_BSD(dev))
1456                 DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue);
1457
1458         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1459
1460         if (HAS_PCH_SPLIT(dev))
1461                 return ironlake_irq_postinstall(dev);
1462
1463         /* Unmask the interrupts that we always want on. */
1464         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1465
1466         dev_priv->pipestat[0] = 0;
1467         dev_priv->pipestat[1] = 0;
1468
1469         if (I915_HAS_HOTPLUG(dev)) {
1470                 /* Enable in IER... */
1471                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1472                 /* and unmask in IMR */
1473                 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
1474         }
1475
1476         /*
1477          * Enable some error detection, note the instruction error mask
1478          * bit is reserved, so we leave it masked.
1479          */
1480         if (IS_G4X(dev)) {
1481                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1482                                GM45_ERROR_MEM_PRIV |
1483                                GM45_ERROR_CP_PRIV |
1484                                I915_ERROR_MEMORY_REFRESH);
1485         } else {
1486                 error_mask = ~(I915_ERROR_PAGE_TABLE |
1487                                I915_ERROR_MEMORY_REFRESH);
1488         }
1489         I915_WRITE(EMR, error_mask);
1490
1491         I915_WRITE(IMR, dev_priv->irq_mask_reg);
1492         I915_WRITE(IER, enable_mask);
1493         (void) I915_READ(IER);
1494
1495         if (I915_HAS_HOTPLUG(dev)) {
1496                 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1497
1498                 /* Note HDMI and DP share bits */
1499                 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1500                         hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1501                 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1502                         hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1503                 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1504                         hotplug_en |= HDMID_HOTPLUG_INT_EN;
1505                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1506                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1507                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1508                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1509                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1510                         hotplug_en |= CRT_HOTPLUG_INT_EN;
1511
1512                         /* Programming the CRT detection parameters tends
1513                            to generate a spurious hotplug event about three
1514                            seconds later.  So just do it once.
1515                         */
1516                         if (IS_G4X(dev))
1517                                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1518                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1519                 }
1520
1521                 /* Ignore TV since it's buggy */
1522
1523                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1524         }
1525
1526         opregion_enable_asle(dev);
1527
1528         return 0;
1529 }
1530
1531 static void ironlake_irq_uninstall(struct drm_device *dev)
1532 {
1533         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1534         I915_WRITE(HWSTAM, 0xffffffff);
1535
1536         I915_WRITE(DEIMR, 0xffffffff);
1537         I915_WRITE(DEIER, 0x0);
1538         I915_WRITE(DEIIR, I915_READ(DEIIR));
1539
1540         I915_WRITE(GTIMR, 0xffffffff);
1541         I915_WRITE(GTIER, 0x0);
1542         I915_WRITE(GTIIR, I915_READ(GTIIR));
1543 }
1544
1545 void i915_driver_irq_uninstall(struct drm_device * dev)
1546 {
1547         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1548
1549         if (!dev_priv)
1550                 return;
1551
1552         dev_priv->vblank_pipe = 0;
1553
1554         if (HAS_PCH_SPLIT(dev)) {
1555                 ironlake_irq_uninstall(dev);
1556                 return;
1557         }
1558
1559         if (I915_HAS_HOTPLUG(dev)) {
1560                 I915_WRITE(PORT_HOTPLUG_EN, 0);
1561                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1562         }
1563
1564         I915_WRITE(HWSTAM, 0xffffffff);
1565         I915_WRITE(PIPEASTAT, 0);
1566         I915_WRITE(PIPEBSTAT, 0);
1567         I915_WRITE(IMR, 0xffffffff);
1568         I915_WRITE(IER, 0x0);
1569
1570         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1571         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1572         I915_WRITE(IIR, I915_READ(IIR));
1573 }