2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
39 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
52 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
53 struct drm_i915_gem_pwrite *args,
54 struct drm_file *file_priv);
55 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
57 static LIST_HEAD(shrink_list);
58 static DEFINE_SPINLOCK(shrink_list_lock);
61 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
63 return obj_priv->gtt_space &&
65 obj_priv->pin_count == 0;
68 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
71 drm_i915_private_t *dev_priv = dev->dev_private;
74 (start & (PAGE_SIZE - 1)) != 0 ||
75 (end & (PAGE_SIZE - 1)) != 0) {
79 drm_mm_init(&dev_priv->mm.gtt_space, start,
82 dev->gtt_total = (uint32_t) (end - start);
88 i915_gem_init_ioctl(struct drm_device *dev, void *data,
89 struct drm_file *file_priv)
91 struct drm_i915_gem_init *args = data;
94 mutex_lock(&dev->struct_mutex);
95 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
96 mutex_unlock(&dev->struct_mutex);
102 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
103 struct drm_file *file_priv)
105 struct drm_i915_gem_get_aperture *args = data;
107 if (!(dev->driver->driver_features & DRIVER_GEM))
110 args->aper_size = dev->gtt_total;
111 args->aper_available_size = (args->aper_size -
112 atomic_read(&dev->pin_memory));
119 * Creates a new mm object and returns a handle to it.
122 i915_gem_create_ioctl(struct drm_device *dev, void *data,
123 struct drm_file *file_priv)
125 struct drm_i915_gem_create *args = data;
126 struct drm_gem_object *obj;
130 args->size = roundup(args->size, PAGE_SIZE);
132 /* Allocate the new object */
133 obj = i915_gem_alloc_object(dev, args->size);
137 ret = drm_gem_handle_create(file_priv, obj, &handle);
138 drm_gem_object_unreference_unlocked(obj);
142 args->handle = handle;
148 fast_shmem_read(struct page **pages,
149 loff_t page_base, int page_offset,
156 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
159 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
160 kunmap_atomic(vaddr, KM_USER0);
168 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
170 drm_i915_private_t *dev_priv = obj->dev->dev_private;
171 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
173 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
174 obj_priv->tiling_mode != I915_TILING_NONE;
178 slow_shmem_copy(struct page *dst_page,
180 struct page *src_page,
184 char *dst_vaddr, *src_vaddr;
186 dst_vaddr = kmap(dst_page);
187 src_vaddr = kmap(src_page);
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
196 slow_shmem_bit17_copy(struct page *gpu_page,
198 struct page *cpu_page,
203 char *gpu_vaddr, *cpu_vaddr;
205 /* Use the unswizzled path if this page isn't affected. */
206 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
208 return slow_shmem_copy(cpu_page, cpu_offset,
209 gpu_page, gpu_offset, length);
211 return slow_shmem_copy(gpu_page, gpu_offset,
212 cpu_page, cpu_offset, length);
215 gpu_vaddr = kmap(gpu_page);
216 cpu_vaddr = kmap(cpu_page);
218 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
219 * XORing with the other bits (A9 for Y, A9 and A10 for X)
222 int cacheline_end = ALIGN(gpu_offset + 1, 64);
223 int this_length = min(cacheline_end - gpu_offset, length);
224 int swizzled_gpu_offset = gpu_offset ^ 64;
227 memcpy(cpu_vaddr + cpu_offset,
228 gpu_vaddr + swizzled_gpu_offset,
231 memcpy(gpu_vaddr + swizzled_gpu_offset,
232 cpu_vaddr + cpu_offset,
235 cpu_offset += this_length;
236 gpu_offset += this_length;
237 length -= this_length;
245 * This is the fast shmem pread path, which attempts to copy_from_user directly
246 * from the backing pages of the object to the user's address space. On a
247 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
250 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
251 struct drm_i915_gem_pread *args,
252 struct drm_file *file_priv)
254 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
256 loff_t offset, page_base;
257 char __user *user_data;
258 int page_offset, page_length;
261 user_data = (char __user *) (uintptr_t) args->data_ptr;
264 mutex_lock(&dev->struct_mutex);
266 ret = i915_gem_object_get_pages(obj, 0);
270 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
275 obj_priv = to_intel_bo(obj);
276 offset = args->offset;
279 /* Operation in this page
281 * page_base = page offset within aperture
282 * page_offset = offset within page
283 * page_length = bytes to copy for this page
285 page_base = (offset & ~(PAGE_SIZE-1));
286 page_offset = offset & (PAGE_SIZE-1);
287 page_length = remain;
288 if ((page_offset + remain) > PAGE_SIZE)
289 page_length = PAGE_SIZE - page_offset;
291 ret = fast_shmem_read(obj_priv->pages,
292 page_base, page_offset,
293 user_data, page_length);
297 remain -= page_length;
298 user_data += page_length;
299 offset += page_length;
303 i915_gem_object_put_pages(obj);
305 mutex_unlock(&dev->struct_mutex);
311 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
315 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
317 /* If we've insufficient memory to map in the pages, attempt
318 * to make some space by throwing out some old buffers.
320 if (ret == -ENOMEM) {
321 struct drm_device *dev = obj->dev;
323 ret = i915_gem_evict_something(dev, obj->size,
324 i915_gem_get_gtt_alignment(obj));
328 ret = i915_gem_object_get_pages(obj, 0);
335 * This is the fallback shmem pread path, which allocates temporary storage
336 * in kernel space to copy_to_user into outside of the struct_mutex, so we
337 * can copy out of the object's backing pages while holding the struct mutex
338 * and not take page faults.
341 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
342 struct drm_i915_gem_pread *args,
343 struct drm_file *file_priv)
345 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
346 struct mm_struct *mm = current->mm;
347 struct page **user_pages;
349 loff_t offset, pinned_pages, i;
350 loff_t first_data_page, last_data_page, num_pages;
351 int shmem_page_index, shmem_page_offset;
352 int data_page_index, data_page_offset;
355 uint64_t data_ptr = args->data_ptr;
356 int do_bit17_swizzling;
360 /* Pin the user pages containing the data. We can't fault while
361 * holding the struct mutex, yet we want to hold it while
362 * dereferencing the user data.
364 first_data_page = data_ptr / PAGE_SIZE;
365 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
366 num_pages = last_data_page - first_data_page + 1;
368 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
369 if (user_pages == NULL)
372 down_read(&mm->mmap_sem);
373 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
374 num_pages, 1, 0, user_pages, NULL);
375 up_read(&mm->mmap_sem);
376 if (pinned_pages < num_pages) {
378 goto fail_put_user_pages;
381 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
383 mutex_lock(&dev->struct_mutex);
385 ret = i915_gem_object_get_pages_or_evict(obj);
389 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
394 obj_priv = to_intel_bo(obj);
395 offset = args->offset;
398 /* Operation in this page
400 * shmem_page_index = page number within shmem file
401 * shmem_page_offset = offset within page in shmem file
402 * data_page_index = page number in get_user_pages return
403 * data_page_offset = offset with data_page_index page.
404 * page_length = bytes to copy for this page
406 shmem_page_index = offset / PAGE_SIZE;
407 shmem_page_offset = offset & ~PAGE_MASK;
408 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
409 data_page_offset = data_ptr & ~PAGE_MASK;
411 page_length = remain;
412 if ((shmem_page_offset + page_length) > PAGE_SIZE)
413 page_length = PAGE_SIZE - shmem_page_offset;
414 if ((data_page_offset + page_length) > PAGE_SIZE)
415 page_length = PAGE_SIZE - data_page_offset;
417 if (do_bit17_swizzling) {
418 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
420 user_pages[data_page_index],
425 slow_shmem_copy(user_pages[data_page_index],
427 obj_priv->pages[shmem_page_index],
432 remain -= page_length;
433 data_ptr += page_length;
434 offset += page_length;
438 i915_gem_object_put_pages(obj);
440 mutex_unlock(&dev->struct_mutex);
442 for (i = 0; i < pinned_pages; i++) {
443 SetPageDirty(user_pages[i]);
444 page_cache_release(user_pages[i]);
446 drm_free_large(user_pages);
452 * Reads data from the object referenced by handle.
454 * On error, the contents of *data are undefined.
457 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
458 struct drm_file *file_priv)
460 struct drm_i915_gem_pread *args = data;
461 struct drm_gem_object *obj;
462 struct drm_i915_gem_object *obj_priv;
465 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
468 obj_priv = to_intel_bo(obj);
470 /* Bounds check source.
472 * XXX: This could use review for overflow issues...
474 if (args->offset > obj->size || args->size > obj->size ||
475 args->offset + args->size > obj->size) {
476 drm_gem_object_unreference_unlocked(obj);
480 if (i915_gem_object_needs_bit17_swizzle(obj)) {
481 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
483 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
485 ret = i915_gem_shmem_pread_slow(dev, obj, args,
489 drm_gem_object_unreference_unlocked(obj);
494 /* This is the fast write path which cannot handle
495 * page faults in the source data
499 fast_user_write(struct io_mapping *mapping,
500 loff_t page_base, int page_offset,
501 char __user *user_data,
505 unsigned long unwritten;
507 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
508 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
510 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
516 /* Here's the write path which can sleep for
521 slow_kernel_write(struct io_mapping *mapping,
522 loff_t gtt_base, int gtt_offset,
523 struct page *user_page, int user_offset,
526 char __iomem *dst_vaddr;
529 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
530 src_vaddr = kmap(user_page);
532 memcpy_toio(dst_vaddr + gtt_offset,
533 src_vaddr + user_offset,
537 io_mapping_unmap(dst_vaddr);
541 fast_shmem_write(struct page **pages,
542 loff_t page_base, int page_offset,
547 unsigned long unwritten;
549 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
552 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
553 kunmap_atomic(vaddr, KM_USER0);
561 * This is the fast pwrite path, where we copy the data directly from the
562 * user into the GTT, uncached.
565 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
566 struct drm_i915_gem_pwrite *args,
567 struct drm_file *file_priv)
569 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
570 drm_i915_private_t *dev_priv = dev->dev_private;
572 loff_t offset, page_base;
573 char __user *user_data;
574 int page_offset, page_length;
577 user_data = (char __user *) (uintptr_t) args->data_ptr;
579 if (!access_ok(VERIFY_READ, user_data, remain))
583 mutex_lock(&dev->struct_mutex);
584 ret = i915_gem_object_pin(obj, 0);
586 mutex_unlock(&dev->struct_mutex);
589 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
593 obj_priv = to_intel_bo(obj);
594 offset = obj_priv->gtt_offset + args->offset;
597 /* Operation in this page
599 * page_base = page offset within aperture
600 * page_offset = offset within page
601 * page_length = bytes to copy for this page
603 page_base = (offset & ~(PAGE_SIZE-1));
604 page_offset = offset & (PAGE_SIZE-1);
605 page_length = remain;
606 if ((page_offset + remain) > PAGE_SIZE)
607 page_length = PAGE_SIZE - page_offset;
609 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
610 page_offset, user_data, page_length);
612 /* If we get a fault while copying data, then (presumably) our
613 * source page isn't available. Return the error and we'll
614 * retry in the slow path.
619 remain -= page_length;
620 user_data += page_length;
621 offset += page_length;
625 i915_gem_object_unpin(obj);
626 mutex_unlock(&dev->struct_mutex);
632 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
633 * the memory and maps it using kmap_atomic for copying.
635 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
636 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
639 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
640 struct drm_i915_gem_pwrite *args,
641 struct drm_file *file_priv)
643 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
644 drm_i915_private_t *dev_priv = dev->dev_private;
646 loff_t gtt_page_base, offset;
647 loff_t first_data_page, last_data_page, num_pages;
648 loff_t pinned_pages, i;
649 struct page **user_pages;
650 struct mm_struct *mm = current->mm;
651 int gtt_page_offset, data_page_offset, data_page_index, page_length;
653 uint64_t data_ptr = args->data_ptr;
657 /* Pin the user pages containing the data. We can't fault while
658 * holding the struct mutex, and all of the pwrite implementations
659 * want to hold it while dereferencing the user data.
661 first_data_page = data_ptr / PAGE_SIZE;
662 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
663 num_pages = last_data_page - first_data_page + 1;
665 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
666 if (user_pages == NULL)
669 down_read(&mm->mmap_sem);
670 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
671 num_pages, 0, 0, user_pages, NULL);
672 up_read(&mm->mmap_sem);
673 if (pinned_pages < num_pages) {
675 goto out_unpin_pages;
678 mutex_lock(&dev->struct_mutex);
679 ret = i915_gem_object_pin(obj, 0);
683 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
685 goto out_unpin_object;
687 obj_priv = to_intel_bo(obj);
688 offset = obj_priv->gtt_offset + args->offset;
691 /* Operation in this page
693 * gtt_page_base = page offset within aperture
694 * gtt_page_offset = offset within page in aperture
695 * data_page_index = page number in get_user_pages return
696 * data_page_offset = offset with data_page_index page.
697 * page_length = bytes to copy for this page
699 gtt_page_base = offset & PAGE_MASK;
700 gtt_page_offset = offset & ~PAGE_MASK;
701 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
702 data_page_offset = data_ptr & ~PAGE_MASK;
704 page_length = remain;
705 if ((gtt_page_offset + page_length) > PAGE_SIZE)
706 page_length = PAGE_SIZE - gtt_page_offset;
707 if ((data_page_offset + page_length) > PAGE_SIZE)
708 page_length = PAGE_SIZE - data_page_offset;
710 slow_kernel_write(dev_priv->mm.gtt_mapping,
711 gtt_page_base, gtt_page_offset,
712 user_pages[data_page_index],
716 remain -= page_length;
717 offset += page_length;
718 data_ptr += page_length;
722 i915_gem_object_unpin(obj);
724 mutex_unlock(&dev->struct_mutex);
726 for (i = 0; i < pinned_pages; i++)
727 page_cache_release(user_pages[i]);
728 drm_free_large(user_pages);
734 * This is the fast shmem pwrite path, which attempts to directly
735 * copy_from_user into the kmapped pages backing the object.
738 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
739 struct drm_i915_gem_pwrite *args,
740 struct drm_file *file_priv)
742 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
744 loff_t offset, page_base;
745 char __user *user_data;
746 int page_offset, page_length;
749 user_data = (char __user *) (uintptr_t) args->data_ptr;
752 mutex_lock(&dev->struct_mutex);
754 ret = i915_gem_object_get_pages(obj, 0);
758 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
762 obj_priv = to_intel_bo(obj);
763 offset = args->offset;
767 /* Operation in this page
769 * page_base = page offset within aperture
770 * page_offset = offset within page
771 * page_length = bytes to copy for this page
773 page_base = (offset & ~(PAGE_SIZE-1));
774 page_offset = offset & (PAGE_SIZE-1);
775 page_length = remain;
776 if ((page_offset + remain) > PAGE_SIZE)
777 page_length = PAGE_SIZE - page_offset;
779 ret = fast_shmem_write(obj_priv->pages,
780 page_base, page_offset,
781 user_data, page_length);
785 remain -= page_length;
786 user_data += page_length;
787 offset += page_length;
791 i915_gem_object_put_pages(obj);
793 mutex_unlock(&dev->struct_mutex);
799 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
800 * the memory and maps it using kmap_atomic for copying.
802 * This avoids taking mmap_sem for faulting on the user's address while the
803 * struct_mutex is held.
806 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
807 struct drm_i915_gem_pwrite *args,
808 struct drm_file *file_priv)
810 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
811 struct mm_struct *mm = current->mm;
812 struct page **user_pages;
814 loff_t offset, pinned_pages, i;
815 loff_t first_data_page, last_data_page, num_pages;
816 int shmem_page_index, shmem_page_offset;
817 int data_page_index, data_page_offset;
820 uint64_t data_ptr = args->data_ptr;
821 int do_bit17_swizzling;
825 /* Pin the user pages containing the data. We can't fault while
826 * holding the struct mutex, and all of the pwrite implementations
827 * want to hold it while dereferencing the user data.
829 first_data_page = data_ptr / PAGE_SIZE;
830 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
831 num_pages = last_data_page - first_data_page + 1;
833 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
834 if (user_pages == NULL)
837 down_read(&mm->mmap_sem);
838 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
839 num_pages, 0, 0, user_pages, NULL);
840 up_read(&mm->mmap_sem);
841 if (pinned_pages < num_pages) {
843 goto fail_put_user_pages;
846 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
848 mutex_lock(&dev->struct_mutex);
850 ret = i915_gem_object_get_pages_or_evict(obj);
854 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
858 obj_priv = to_intel_bo(obj);
859 offset = args->offset;
863 /* Operation in this page
865 * shmem_page_index = page number within shmem file
866 * shmem_page_offset = offset within page in shmem file
867 * data_page_index = page number in get_user_pages return
868 * data_page_offset = offset with data_page_index page.
869 * page_length = bytes to copy for this page
871 shmem_page_index = offset / PAGE_SIZE;
872 shmem_page_offset = offset & ~PAGE_MASK;
873 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
874 data_page_offset = data_ptr & ~PAGE_MASK;
876 page_length = remain;
877 if ((shmem_page_offset + page_length) > PAGE_SIZE)
878 page_length = PAGE_SIZE - shmem_page_offset;
879 if ((data_page_offset + page_length) > PAGE_SIZE)
880 page_length = PAGE_SIZE - data_page_offset;
882 if (do_bit17_swizzling) {
883 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
885 user_pages[data_page_index],
890 slow_shmem_copy(obj_priv->pages[shmem_page_index],
892 user_pages[data_page_index],
897 remain -= page_length;
898 data_ptr += page_length;
899 offset += page_length;
903 i915_gem_object_put_pages(obj);
905 mutex_unlock(&dev->struct_mutex);
907 for (i = 0; i < pinned_pages; i++)
908 page_cache_release(user_pages[i]);
909 drm_free_large(user_pages);
915 * Writes data to the object referenced by handle.
917 * On error, the contents of the buffer that were to be modified are undefined.
920 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
921 struct drm_file *file_priv)
923 struct drm_i915_gem_pwrite *args = data;
924 struct drm_gem_object *obj;
925 struct drm_i915_gem_object *obj_priv;
928 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
931 obj_priv = to_intel_bo(obj);
933 /* Bounds check destination.
935 * XXX: This could use review for overflow issues...
937 if (args->offset > obj->size || args->size > obj->size ||
938 args->offset + args->size > obj->size) {
939 drm_gem_object_unreference_unlocked(obj);
943 /* We can only do the GTT pwrite on untiled buffers, as otherwise
944 * it would end up going through the fenced access, and we'll get
945 * different detiling behavior between reading and writing.
946 * pread/pwrite currently are reading and writing from the CPU
947 * perspective, requiring manual detiling by the client.
949 if (obj_priv->phys_obj)
950 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
951 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
952 dev->gtt_total != 0 &&
953 obj->write_domain != I915_GEM_DOMAIN_CPU) {
954 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
955 if (ret == -EFAULT) {
956 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
959 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
960 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
962 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
963 if (ret == -EFAULT) {
964 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
971 DRM_INFO("pwrite failed %d\n", ret);
974 drm_gem_object_unreference_unlocked(obj);
980 * Called when user space prepares to use an object with the CPU, either
981 * through the mmap ioctl's mapping or a GTT mapping.
984 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *file_priv)
987 struct drm_i915_private *dev_priv = dev->dev_private;
988 struct drm_i915_gem_set_domain *args = data;
989 struct drm_gem_object *obj;
990 struct drm_i915_gem_object *obj_priv;
991 uint32_t read_domains = args->read_domains;
992 uint32_t write_domain = args->write_domain;
995 if (!(dev->driver->driver_features & DRIVER_GEM))
998 /* Only handle setting domains to types used by the CPU. */
999 if (write_domain & I915_GEM_GPU_DOMAINS)
1002 if (read_domains & I915_GEM_GPU_DOMAINS)
1005 /* Having something in the write domain implies it's in the read
1006 * domain, and only that read domain. Enforce that in the request.
1008 if (write_domain != 0 && read_domains != write_domain)
1011 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1014 obj_priv = to_intel_bo(obj);
1016 mutex_lock(&dev->struct_mutex);
1018 intel_mark_busy(dev, obj);
1021 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1022 obj, obj->size, read_domains, write_domain);
1024 if (read_domains & I915_GEM_DOMAIN_GTT) {
1025 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1027 /* Update the LRU on the fence for the CPU access that's
1030 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1031 struct drm_i915_fence_reg *reg =
1032 &dev_priv->fence_regs[obj_priv->fence_reg];
1033 list_move_tail(®->lru_list,
1034 &dev_priv->mm.fence_list);
1037 /* Silently promote "you're not bound, there was nothing to do"
1038 * to success, since the client was just asking us to
1039 * make sure everything was done.
1044 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1048 /* Maintain LRU order of "inactive" objects */
1049 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1050 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1052 drm_gem_object_unreference(obj);
1053 mutex_unlock(&dev->struct_mutex);
1058 * Called when user space has done writes to this buffer
1061 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1062 struct drm_file *file_priv)
1064 struct drm_i915_gem_sw_finish *args = data;
1065 struct drm_gem_object *obj;
1066 struct drm_i915_gem_object *obj_priv;
1069 if (!(dev->driver->driver_features & DRIVER_GEM))
1072 mutex_lock(&dev->struct_mutex);
1073 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1075 mutex_unlock(&dev->struct_mutex);
1080 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1081 __func__, args->handle, obj, obj->size);
1083 obj_priv = to_intel_bo(obj);
1085 /* Pinned buffers may be scanout, so flush the cache */
1086 if (obj_priv->pin_count)
1087 i915_gem_object_flush_cpu_write_domain(obj);
1089 drm_gem_object_unreference(obj);
1090 mutex_unlock(&dev->struct_mutex);
1095 * Maps the contents of an object, returning the address it is mapped
1098 * While the mapping holds a reference on the contents of the object, it doesn't
1099 * imply a ref on the object itself.
1102 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv)
1105 struct drm_i915_gem_mmap *args = data;
1106 struct drm_gem_object *obj;
1110 if (!(dev->driver->driver_features & DRIVER_GEM))
1113 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1117 offset = args->offset;
1119 down_write(¤t->mm->mmap_sem);
1120 addr = do_mmap(obj->filp, 0, args->size,
1121 PROT_READ | PROT_WRITE, MAP_SHARED,
1123 up_write(¤t->mm->mmap_sem);
1124 drm_gem_object_unreference_unlocked(obj);
1125 if (IS_ERR((void *)addr))
1128 args->addr_ptr = (uint64_t) addr;
1134 * i915_gem_fault - fault a page into the GTT
1135 * vma: VMA in question
1138 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1139 * from userspace. The fault handler takes care of binding the object to
1140 * the GTT (if needed), allocating and programming a fence register (again,
1141 * only if needed based on whether the old reg is still valid or the object
1142 * is tiled) and inserting a new PTE into the faulting process.
1144 * Note that the faulting process may involve evicting existing objects
1145 * from the GTT and/or fence registers to make room. So performance may
1146 * suffer if the GTT working set is large or there are few fence registers
1149 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1151 struct drm_gem_object *obj = vma->vm_private_data;
1152 struct drm_device *dev = obj->dev;
1153 drm_i915_private_t *dev_priv = dev->dev_private;
1154 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1155 pgoff_t page_offset;
1158 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1160 /* We don't use vmf->pgoff since that has the fake offset */
1161 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1164 /* Now bind it into the GTT if needed */
1165 mutex_lock(&dev->struct_mutex);
1166 if (!obj_priv->gtt_space) {
1167 ret = i915_gem_object_bind_to_gtt(obj, 0);
1171 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1176 /* Need a new fence register? */
1177 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1178 ret = i915_gem_object_get_fence_reg(obj);
1183 if (i915_gem_object_is_inactive(obj_priv))
1184 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1186 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1189 /* Finally, remap it using the new GTT offset */
1190 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1192 mutex_unlock(&dev->struct_mutex);
1197 return VM_FAULT_NOPAGE;
1200 return VM_FAULT_OOM;
1202 return VM_FAULT_SIGBUS;
1207 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1208 * @obj: obj in question
1210 * GEM memory mapping works by handing back to userspace a fake mmap offset
1211 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1212 * up the object based on the offset and sets up the various memory mapping
1215 * This routine allocates and attaches a fake offset for @obj.
1218 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1220 struct drm_device *dev = obj->dev;
1221 struct drm_gem_mm *mm = dev->mm_private;
1222 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1223 struct drm_map_list *list;
1224 struct drm_local_map *map;
1227 /* Set the object up for mmap'ing */
1228 list = &obj->map_list;
1229 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1234 map->type = _DRM_GEM;
1235 map->size = obj->size;
1238 /* Get a DRM GEM mmap offset allocated... */
1239 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1240 obj->size / PAGE_SIZE, 0, 0);
1241 if (!list->file_offset_node) {
1242 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1247 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1248 obj->size / PAGE_SIZE, 0);
1249 if (!list->file_offset_node) {
1254 list->hash.key = list->file_offset_node->start;
1255 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1256 DRM_ERROR("failed to add to map hash\n");
1261 /* By now we should be all set, any drm_mmap request on the offset
1262 * below will get to our mmap & fault handler */
1263 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1268 drm_mm_put_block(list->file_offset_node);
1276 * i915_gem_release_mmap - remove physical page mappings
1277 * @obj: obj in question
1279 * Preserve the reservation of the mmapping with the DRM core code, but
1280 * relinquish ownership of the pages back to the system.
1282 * It is vital that we remove the page mapping if we have mapped a tiled
1283 * object through the GTT and then lose the fence register due to
1284 * resource pressure. Similarly if the object has been moved out of the
1285 * aperture, than pages mapped into userspace must be revoked. Removing the
1286 * mapping will then trigger a page fault on the next user access, allowing
1287 * fixup by i915_gem_fault().
1290 i915_gem_release_mmap(struct drm_gem_object *obj)
1292 struct drm_device *dev = obj->dev;
1293 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1295 if (dev->dev_mapping)
1296 unmap_mapping_range(dev->dev_mapping,
1297 obj_priv->mmap_offset, obj->size, 1);
1301 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1303 struct drm_device *dev = obj->dev;
1304 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1305 struct drm_gem_mm *mm = dev->mm_private;
1306 struct drm_map_list *list;
1308 list = &obj->map_list;
1309 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1311 if (list->file_offset_node) {
1312 drm_mm_put_block(list->file_offset_node);
1313 list->file_offset_node = NULL;
1321 obj_priv->mmap_offset = 0;
1325 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1326 * @obj: object to check
1328 * Return the required GTT alignment for an object, taking into account
1329 * potential fence register mapping if needed.
1332 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1334 struct drm_device *dev = obj->dev;
1335 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1339 * Minimum alignment is 4k (GTT page size), but might be greater
1340 * if a fence register is needed for the object.
1342 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1346 * Previous chips need to be aligned to the size of the smallest
1347 * fence register that can contain the object.
1354 for (i = start; i < obj->size; i <<= 1)
1361 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1363 * @data: GTT mapping ioctl data
1364 * @file_priv: GEM object info
1366 * Simply returns the fake offset to userspace so it can mmap it.
1367 * The mmap call will end up in drm_gem_mmap(), which will set things
1368 * up so we can get faults in the handler above.
1370 * The fault handler will take care of binding the object into the GTT
1371 * (since it may have been evicted to make room for something), allocating
1372 * a fence register, and mapping the appropriate aperture address into
1376 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1377 struct drm_file *file_priv)
1379 struct drm_i915_gem_mmap_gtt *args = data;
1380 struct drm_gem_object *obj;
1381 struct drm_i915_gem_object *obj_priv;
1384 if (!(dev->driver->driver_features & DRIVER_GEM))
1387 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1391 mutex_lock(&dev->struct_mutex);
1393 obj_priv = to_intel_bo(obj);
1395 if (obj_priv->madv != I915_MADV_WILLNEED) {
1396 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1397 drm_gem_object_unreference(obj);
1398 mutex_unlock(&dev->struct_mutex);
1403 if (!obj_priv->mmap_offset) {
1404 ret = i915_gem_create_mmap_offset(obj);
1406 drm_gem_object_unreference(obj);
1407 mutex_unlock(&dev->struct_mutex);
1412 args->offset = obj_priv->mmap_offset;
1415 * Pull it into the GTT so that we have a page list (makes the
1416 * initial fault faster and any subsequent flushing possible).
1418 if (!obj_priv->agp_mem) {
1419 ret = i915_gem_object_bind_to_gtt(obj, 0);
1421 drm_gem_object_unreference(obj);
1422 mutex_unlock(&dev->struct_mutex);
1427 drm_gem_object_unreference(obj);
1428 mutex_unlock(&dev->struct_mutex);
1434 i915_gem_object_put_pages(struct drm_gem_object *obj)
1436 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1437 int page_count = obj->size / PAGE_SIZE;
1440 BUG_ON(obj_priv->pages_refcount == 0);
1441 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1443 if (--obj_priv->pages_refcount != 0)
1446 if (obj_priv->tiling_mode != I915_TILING_NONE)
1447 i915_gem_object_save_bit_17_swizzle(obj);
1449 if (obj_priv->madv == I915_MADV_DONTNEED)
1450 obj_priv->dirty = 0;
1452 for (i = 0; i < page_count; i++) {
1453 if (obj_priv->dirty)
1454 set_page_dirty(obj_priv->pages[i]);
1456 if (obj_priv->madv == I915_MADV_WILLNEED)
1457 mark_page_accessed(obj_priv->pages[i]);
1459 page_cache_release(obj_priv->pages[i]);
1461 obj_priv->dirty = 0;
1463 drm_free_large(obj_priv->pages);
1464 obj_priv->pages = NULL;
1468 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1469 struct intel_ring_buffer *ring)
1471 struct drm_device *dev = obj->dev;
1472 drm_i915_private_t *dev_priv = dev->dev_private;
1473 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1474 BUG_ON(ring == NULL);
1475 obj_priv->ring = ring;
1477 /* Add a reference if we're newly entering the active list. */
1478 if (!obj_priv->active) {
1479 drm_gem_object_reference(obj);
1480 obj_priv->active = 1;
1482 /* Move from whatever list we were on to the tail of execution. */
1483 spin_lock(&dev_priv->mm.active_list_lock);
1484 list_move_tail(&obj_priv->list, &ring->active_list);
1485 spin_unlock(&dev_priv->mm.active_list_lock);
1486 obj_priv->last_rendering_seqno = seqno;
1490 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1492 struct drm_device *dev = obj->dev;
1493 drm_i915_private_t *dev_priv = dev->dev_private;
1494 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1496 BUG_ON(!obj_priv->active);
1497 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1498 obj_priv->last_rendering_seqno = 0;
1501 /* Immediately discard the backing storage */
1503 i915_gem_object_truncate(struct drm_gem_object *obj)
1505 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1506 struct inode *inode;
1508 /* Our goal here is to return as much of the memory as
1509 * is possible back to the system as we are called from OOM.
1510 * To do this we must instruct the shmfs to drop all of its
1511 * backing pages, *now*. Here we mirror the actions taken
1512 * when by shmem_delete_inode() to release the backing store.
1514 inode = obj->filp->f_path.dentry->d_inode;
1515 truncate_inode_pages(inode->i_mapping, 0);
1516 if (inode->i_op->truncate_range)
1517 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1519 obj_priv->madv = __I915_MADV_PURGED;
1523 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1525 return obj_priv->madv == I915_MADV_DONTNEED;
1529 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1531 struct drm_device *dev = obj->dev;
1532 drm_i915_private_t *dev_priv = dev->dev_private;
1533 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1535 i915_verify_inactive(dev, __FILE__, __LINE__);
1536 if (obj_priv->pin_count != 0)
1537 list_del_init(&obj_priv->list);
1539 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1541 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1543 obj_priv->last_rendering_seqno = 0;
1544 obj_priv->ring = NULL;
1545 if (obj_priv->active) {
1546 obj_priv->active = 0;
1547 drm_gem_object_unreference(obj);
1549 i915_verify_inactive(dev, __FILE__, __LINE__);
1553 i915_gem_process_flushing_list(struct drm_device *dev,
1554 uint32_t flush_domains, uint32_t seqno,
1555 struct intel_ring_buffer *ring)
1557 drm_i915_private_t *dev_priv = dev->dev_private;
1558 struct drm_i915_gem_object *obj_priv, *next;
1560 list_for_each_entry_safe(obj_priv, next,
1561 &dev_priv->mm.gpu_write_list,
1563 struct drm_gem_object *obj = &obj_priv->base;
1565 if ((obj->write_domain & flush_domains) ==
1566 obj->write_domain &&
1567 obj_priv->ring->ring_flag == ring->ring_flag) {
1568 uint32_t old_write_domain = obj->write_domain;
1570 obj->write_domain = 0;
1571 list_del_init(&obj_priv->gpu_write_list);
1572 i915_gem_object_move_to_active(obj, seqno, ring);
1574 /* update the fence lru list */
1575 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1576 struct drm_i915_fence_reg *reg =
1577 &dev_priv->fence_regs[obj_priv->fence_reg];
1578 list_move_tail(®->lru_list,
1579 &dev_priv->mm.fence_list);
1582 trace_i915_gem_object_change_domain(obj,
1590 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1591 uint32_t flush_domains, struct intel_ring_buffer *ring)
1593 drm_i915_private_t *dev_priv = dev->dev_private;
1594 struct drm_i915_file_private *i915_file_priv = NULL;
1595 struct drm_i915_gem_request *request;
1599 if (file_priv != NULL)
1600 i915_file_priv = file_priv->driver_priv;
1602 request = kzalloc(sizeof(*request), GFP_KERNEL);
1603 if (request == NULL)
1606 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1608 request->seqno = seqno;
1609 request->ring = ring;
1610 request->emitted_jiffies = jiffies;
1611 was_empty = list_empty(&ring->request_list);
1612 list_add_tail(&request->list, &ring->request_list);
1614 if (i915_file_priv) {
1615 list_add_tail(&request->client_list,
1616 &i915_file_priv->mm.request_list);
1618 INIT_LIST_HEAD(&request->client_list);
1621 /* Associate any objects on the flushing list matching the write
1622 * domain we're flushing with our flush.
1624 if (flush_domains != 0)
1625 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1627 if (!dev_priv->mm.suspended) {
1628 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1630 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1636 * Command execution barrier
1638 * Ensures that all commands in the ring are finished
1639 * before signalling the CPU
1642 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1644 uint32_t flush_domains = 0;
1646 /* The sampler always gets flushed on i965 (sigh) */
1648 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1650 ring->flush(dev, ring,
1651 I915_GEM_DOMAIN_COMMAND, flush_domains);
1652 return flush_domains;
1656 * Moves buffers associated only with the given active seqno from the active
1657 * to inactive list, potentially freeing them.
1660 i915_gem_retire_request(struct drm_device *dev,
1661 struct drm_i915_gem_request *request)
1663 drm_i915_private_t *dev_priv = dev->dev_private;
1665 trace_i915_gem_request_retire(dev, request->seqno);
1667 /* Move any buffers on the active list that are no longer referenced
1668 * by the ringbuffer to the flushing/inactive lists as appropriate.
1670 spin_lock(&dev_priv->mm.active_list_lock);
1671 while (!list_empty(&request->ring->active_list)) {
1672 struct drm_gem_object *obj;
1673 struct drm_i915_gem_object *obj_priv;
1675 obj_priv = list_first_entry(&request->ring->active_list,
1676 struct drm_i915_gem_object,
1678 obj = &obj_priv->base;
1680 /* If the seqno being retired doesn't match the oldest in the
1681 * list, then the oldest in the list must still be newer than
1684 if (obj_priv->last_rendering_seqno != request->seqno)
1688 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1689 __func__, request->seqno, obj);
1692 if (obj->write_domain != 0)
1693 i915_gem_object_move_to_flushing(obj);
1695 /* Take a reference on the object so it won't be
1696 * freed while the spinlock is held. The list
1697 * protection for this spinlock is safe when breaking
1698 * the lock like this since the next thing we do
1699 * is just get the head of the list again.
1701 drm_gem_object_reference(obj);
1702 i915_gem_object_move_to_inactive(obj);
1703 spin_unlock(&dev_priv->mm.active_list_lock);
1704 drm_gem_object_unreference(obj);
1705 spin_lock(&dev_priv->mm.active_list_lock);
1709 spin_unlock(&dev_priv->mm.active_list_lock);
1713 * Returns true if seq1 is later than seq2.
1716 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1718 return (int32_t)(seq1 - seq2) >= 0;
1722 i915_get_gem_seqno(struct drm_device *dev,
1723 struct intel_ring_buffer *ring)
1725 return ring->get_gem_seqno(dev, ring);
1729 * This function clears the request list as sequence numbers are passed.
1732 i915_gem_retire_requests_ring(struct drm_device *dev,
1733 struct intel_ring_buffer *ring)
1735 drm_i915_private_t *dev_priv = dev->dev_private;
1738 if (!ring->status_page.page_addr
1739 || list_empty(&ring->request_list))
1742 seqno = i915_get_gem_seqno(dev, ring);
1744 while (!list_empty(&ring->request_list)) {
1745 struct drm_i915_gem_request *request;
1746 uint32_t retiring_seqno;
1748 request = list_first_entry(&ring->request_list,
1749 struct drm_i915_gem_request,
1751 retiring_seqno = request->seqno;
1753 if (i915_seqno_passed(seqno, retiring_seqno) ||
1754 atomic_read(&dev_priv->mm.wedged)) {
1755 i915_gem_retire_request(dev, request);
1757 list_del(&request->list);
1758 list_del(&request->client_list);
1764 if (unlikely (dev_priv->trace_irq_seqno &&
1765 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1767 ring->user_irq_put(dev, ring);
1768 dev_priv->trace_irq_seqno = 0;
1773 i915_gem_retire_requests(struct drm_device *dev)
1775 drm_i915_private_t *dev_priv = dev->dev_private;
1777 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1778 struct drm_i915_gem_object *obj_priv, *tmp;
1780 /* We must be careful that during unbind() we do not
1781 * accidentally infinitely recurse into retire requests.
1783 * retire -> free -> unbind -> wait -> retire_ring
1785 list_for_each_entry_safe(obj_priv, tmp,
1786 &dev_priv->mm.deferred_free_list,
1788 i915_gem_free_object_tail(&obj_priv->base);
1791 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1793 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1797 i915_gem_retire_work_handler(struct work_struct *work)
1799 drm_i915_private_t *dev_priv;
1800 struct drm_device *dev;
1802 dev_priv = container_of(work, drm_i915_private_t,
1803 mm.retire_work.work);
1804 dev = dev_priv->dev;
1806 mutex_lock(&dev->struct_mutex);
1807 i915_gem_retire_requests(dev);
1809 if (!dev_priv->mm.suspended &&
1810 (!list_empty(&dev_priv->render_ring.request_list) ||
1812 !list_empty(&dev_priv->bsd_ring.request_list))))
1813 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1814 mutex_unlock(&dev->struct_mutex);
1818 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1819 int interruptible, struct intel_ring_buffer *ring)
1821 drm_i915_private_t *dev_priv = dev->dev_private;
1827 if (atomic_read(&dev_priv->mm.wedged))
1830 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1831 if (HAS_PCH_SPLIT(dev))
1832 ier = I915_READ(DEIER) | I915_READ(GTIER);
1834 ier = I915_READ(IER);
1836 DRM_ERROR("something (likely vbetool) disabled "
1837 "interrupts, re-enabling\n");
1838 i915_driver_irq_preinstall(dev);
1839 i915_driver_irq_postinstall(dev);
1842 trace_i915_gem_request_wait_begin(dev, seqno);
1844 ring->waiting_gem_seqno = seqno;
1845 ring->user_irq_get(dev, ring);
1847 ret = wait_event_interruptible(ring->irq_queue,
1849 ring->get_gem_seqno(dev, ring), seqno)
1850 || atomic_read(&dev_priv->mm.wedged));
1852 wait_event(ring->irq_queue,
1854 ring->get_gem_seqno(dev, ring), seqno)
1855 || atomic_read(&dev_priv->mm.wedged));
1857 ring->user_irq_put(dev, ring);
1858 ring->waiting_gem_seqno = 0;
1860 trace_i915_gem_request_wait_end(dev, seqno);
1862 if (atomic_read(&dev_priv->mm.wedged))
1865 if (ret && ret != -ERESTARTSYS)
1866 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1867 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1869 /* Directly dispatch request retiring. While we have the work queue
1870 * to handle this, the waiter on a request often wants an associated
1871 * buffer to have made it to the inactive list, and we would need
1872 * a separate wait queue to handle that.
1875 i915_gem_retire_requests_ring(dev, ring);
1881 * Waits for a sequence number to be signaled, and cleans up the
1882 * request and object lists appropriately for that event.
1885 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1886 struct intel_ring_buffer *ring)
1888 return i915_do_wait_request(dev, seqno, 1, ring);
1892 i915_gem_flush(struct drm_device *dev,
1893 uint32_t invalidate_domains,
1894 uint32_t flush_domains)
1896 drm_i915_private_t *dev_priv = dev->dev_private;
1897 if (flush_domains & I915_GEM_DOMAIN_CPU)
1898 drm_agp_chipset_flush(dev);
1899 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1904 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1910 * Ensures that all rendering to the object has completed and the object is
1911 * safe to unbind from the GTT or access from the CPU.
1914 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1916 struct drm_device *dev = obj->dev;
1917 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1920 /* This function only exists to support waiting for existing rendering,
1921 * not for emitting required flushes.
1923 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1925 /* If there is rendering queued on the buffer being evicted, wait for
1928 if (obj_priv->active) {
1930 DRM_INFO("%s: object %p wait for seqno %08x\n",
1931 __func__, obj, obj_priv->last_rendering_seqno);
1933 ret = i915_wait_request(dev,
1934 obj_priv->last_rendering_seqno, obj_priv->ring);
1943 * Unbinds an object from the GTT aperture.
1946 i915_gem_object_unbind(struct drm_gem_object *obj)
1948 struct drm_device *dev = obj->dev;
1949 drm_i915_private_t *dev_priv = dev->dev_private;
1950 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1954 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1955 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1957 if (obj_priv->gtt_space == NULL)
1960 if (obj_priv->pin_count != 0) {
1961 DRM_ERROR("Attempting to unbind pinned buffer\n");
1965 /* blow away mappings if mapped through GTT */
1966 i915_gem_release_mmap(obj);
1968 /* Move the object to the CPU domain to ensure that
1969 * any possible CPU writes while it's not in the GTT
1970 * are flushed when we go to remap it. This will
1971 * also ensure that all pending GPU writes are finished
1974 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1975 if (ret == -ERESTARTSYS)
1977 /* Continue on if we fail due to EIO, the GPU is hung so we
1978 * should be safe and we need to cleanup or else we might
1979 * cause memory corruption through use-after-free.
1982 BUG_ON(obj_priv->active);
1984 /* release the fence reg _after_ flushing */
1985 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1986 i915_gem_clear_fence_reg(obj);
1988 if (obj_priv->agp_mem != NULL) {
1989 drm_unbind_agp(obj_priv->agp_mem);
1990 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1991 obj_priv->agp_mem = NULL;
1994 i915_gem_object_put_pages(obj);
1995 BUG_ON(obj_priv->pages_refcount);
1997 if (obj_priv->gtt_space) {
1998 atomic_dec(&dev->gtt_count);
1999 atomic_sub(obj->size, &dev->gtt_memory);
2001 drm_mm_put_block(obj_priv->gtt_space);
2002 obj_priv->gtt_space = NULL;
2005 /* Remove ourselves from the LRU list if present. */
2006 spin_lock(&dev_priv->mm.active_list_lock);
2007 if (!list_empty(&obj_priv->list))
2008 list_del_init(&obj_priv->list);
2009 spin_unlock(&dev_priv->mm.active_list_lock);
2011 if (i915_gem_object_is_purgeable(obj_priv))
2012 i915_gem_object_truncate(obj);
2014 trace_i915_gem_object_unbind(obj);
2020 i915_gpu_idle(struct drm_device *dev)
2022 drm_i915_private_t *dev_priv = dev->dev_private;
2024 uint32_t seqno1, seqno2;
2027 spin_lock(&dev_priv->mm.active_list_lock);
2028 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2029 list_empty(&dev_priv->render_ring.active_list) &&
2031 list_empty(&dev_priv->bsd_ring.active_list)));
2032 spin_unlock(&dev_priv->mm.active_list_lock);
2037 /* Flush everything onto the inactive list. */
2038 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2039 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2040 &dev_priv->render_ring);
2043 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2046 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2047 &dev_priv->bsd_ring);
2051 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2061 i915_gem_object_get_pages(struct drm_gem_object *obj,
2064 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2066 struct address_space *mapping;
2067 struct inode *inode;
2070 BUG_ON(obj_priv->pages_refcount
2071 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2073 if (obj_priv->pages_refcount++ != 0)
2076 /* Get the list of pages out of our struct file. They'll be pinned
2077 * at this point until we release them.
2079 page_count = obj->size / PAGE_SIZE;
2080 BUG_ON(obj_priv->pages != NULL);
2081 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2082 if (obj_priv->pages == NULL) {
2083 obj_priv->pages_refcount--;
2087 inode = obj->filp->f_path.dentry->d_inode;
2088 mapping = inode->i_mapping;
2089 for (i = 0; i < page_count; i++) {
2090 page = read_cache_page_gfp(mapping, i,
2098 obj_priv->pages[i] = page;
2101 if (obj_priv->tiling_mode != I915_TILING_NONE)
2102 i915_gem_object_do_bit_17_swizzle(obj);
2108 page_cache_release(obj_priv->pages[i]);
2110 drm_free_large(obj_priv->pages);
2111 obj_priv->pages = NULL;
2112 obj_priv->pages_refcount--;
2113 return PTR_ERR(page);
2116 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2118 struct drm_gem_object *obj = reg->obj;
2119 struct drm_device *dev = obj->dev;
2120 drm_i915_private_t *dev_priv = dev->dev_private;
2121 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2122 int regnum = obj_priv->fence_reg;
2125 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2127 val |= obj_priv->gtt_offset & 0xfffff000;
2128 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2129 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2131 if (obj_priv->tiling_mode == I915_TILING_Y)
2132 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2133 val |= I965_FENCE_REG_VALID;
2135 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2138 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2140 struct drm_gem_object *obj = reg->obj;
2141 struct drm_device *dev = obj->dev;
2142 drm_i915_private_t *dev_priv = dev->dev_private;
2143 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2144 int regnum = obj_priv->fence_reg;
2147 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2149 val |= obj_priv->gtt_offset & 0xfffff000;
2150 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2151 if (obj_priv->tiling_mode == I915_TILING_Y)
2152 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2153 val |= I965_FENCE_REG_VALID;
2155 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2158 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2160 struct drm_gem_object *obj = reg->obj;
2161 struct drm_device *dev = obj->dev;
2162 drm_i915_private_t *dev_priv = dev->dev_private;
2163 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2164 int regnum = obj_priv->fence_reg;
2166 uint32_t fence_reg, val;
2169 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2170 (obj_priv->gtt_offset & (obj->size - 1))) {
2171 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2172 __func__, obj_priv->gtt_offset, obj->size);
2176 if (obj_priv->tiling_mode == I915_TILING_Y &&
2177 HAS_128_BYTE_Y_TILING(dev))
2182 /* Note: pitch better be a power of two tile widths */
2183 pitch_val = obj_priv->stride / tile_width;
2184 pitch_val = ffs(pitch_val) - 1;
2186 if (obj_priv->tiling_mode == I915_TILING_Y &&
2187 HAS_128_BYTE_Y_TILING(dev))
2188 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2190 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2192 val = obj_priv->gtt_offset;
2193 if (obj_priv->tiling_mode == I915_TILING_Y)
2194 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2195 val |= I915_FENCE_SIZE_BITS(obj->size);
2196 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2197 val |= I830_FENCE_REG_VALID;
2200 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2202 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2203 I915_WRITE(fence_reg, val);
2206 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2208 struct drm_gem_object *obj = reg->obj;
2209 struct drm_device *dev = obj->dev;
2210 drm_i915_private_t *dev_priv = dev->dev_private;
2211 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2212 int regnum = obj_priv->fence_reg;
2215 uint32_t fence_size_bits;
2217 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2218 (obj_priv->gtt_offset & (obj->size - 1))) {
2219 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2220 __func__, obj_priv->gtt_offset);
2224 pitch_val = obj_priv->stride / 128;
2225 pitch_val = ffs(pitch_val) - 1;
2226 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2228 val = obj_priv->gtt_offset;
2229 if (obj_priv->tiling_mode == I915_TILING_Y)
2230 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2231 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2232 WARN_ON(fence_size_bits & ~0x00000f00);
2233 val |= fence_size_bits;
2234 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2235 val |= I830_FENCE_REG_VALID;
2237 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2240 static int i915_find_fence_reg(struct drm_device *dev)
2242 struct drm_i915_fence_reg *reg = NULL;
2243 struct drm_i915_gem_object *obj_priv = NULL;
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245 struct drm_gem_object *obj = NULL;
2248 /* First try to find a free reg */
2250 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2251 reg = &dev_priv->fence_regs[i];
2255 obj_priv = to_intel_bo(reg->obj);
2256 if (!obj_priv->pin_count)
2263 /* None available, try to steal one or wait for a user to finish */
2264 i = I915_FENCE_REG_NONE;
2265 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2268 obj_priv = to_intel_bo(obj);
2270 if (obj_priv->pin_count)
2274 i = obj_priv->fence_reg;
2278 BUG_ON(i == I915_FENCE_REG_NONE);
2280 /* We only have a reference on obj from the active list. put_fence_reg
2281 * might drop that one, causing a use-after-free in it. So hold a
2282 * private reference to obj like the other callers of put_fence_reg
2283 * (set_tiling ioctl) do. */
2284 drm_gem_object_reference(obj);
2285 ret = i915_gem_object_put_fence_reg(obj);
2286 drm_gem_object_unreference(obj);
2294 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2295 * @obj: object to map through a fence reg
2297 * When mapping objects through the GTT, userspace wants to be able to write
2298 * to them without having to worry about swizzling if the object is tiled.
2300 * This function walks the fence regs looking for a free one for @obj,
2301 * stealing one if it can't find any.
2303 * It then sets up the reg based on the object's properties: address, pitch
2304 * and tiling format.
2307 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2309 struct drm_device *dev = obj->dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2312 struct drm_i915_fence_reg *reg = NULL;
2315 /* Just update our place in the LRU if our fence is getting used. */
2316 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2317 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2318 list_move_tail(®->lru_list, &dev_priv->mm.fence_list);
2322 switch (obj_priv->tiling_mode) {
2323 case I915_TILING_NONE:
2324 WARN(1, "allocating a fence for non-tiled object?\n");
2327 if (!obj_priv->stride)
2329 WARN((obj_priv->stride & (512 - 1)),
2330 "object 0x%08x is X tiled but has non-512B pitch\n",
2331 obj_priv->gtt_offset);
2334 if (!obj_priv->stride)
2336 WARN((obj_priv->stride & (128 - 1)),
2337 "object 0x%08x is Y tiled but has non-128B pitch\n",
2338 obj_priv->gtt_offset);
2342 ret = i915_find_fence_reg(dev);
2346 obj_priv->fence_reg = ret;
2347 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2348 list_add_tail(®->lru_list, &dev_priv->mm.fence_list);
2353 sandybridge_write_fence_reg(reg);
2354 else if (IS_I965G(dev))
2355 i965_write_fence_reg(reg);
2356 else if (IS_I9XX(dev))
2357 i915_write_fence_reg(reg);
2359 i830_write_fence_reg(reg);
2361 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2362 obj_priv->tiling_mode);
2368 * i915_gem_clear_fence_reg - clear out fence register info
2369 * @obj: object to clear
2371 * Zeroes out the fence register itself and clears out the associated
2372 * data structures in dev_priv and obj_priv.
2375 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2377 struct drm_device *dev = obj->dev;
2378 drm_i915_private_t *dev_priv = dev->dev_private;
2379 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2380 struct drm_i915_fence_reg *reg =
2381 &dev_priv->fence_regs[obj_priv->fence_reg];
2384 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2385 (obj_priv->fence_reg * 8), 0);
2386 } else if (IS_I965G(dev)) {
2387 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2391 if (obj_priv->fence_reg < 8)
2392 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2394 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2397 I915_WRITE(fence_reg, 0);
2401 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2402 list_del_init(®->lru_list);
2406 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2407 * to the buffer to finish, and then resets the fence register.
2408 * @obj: tiled object holding a fence register.
2410 * Zeroes out the fence register itself and clears out the associated
2411 * data structures in dev_priv and obj_priv.
2414 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2416 struct drm_device *dev = obj->dev;
2417 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2419 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2422 /* If we've changed tiling, GTT-mappings of the object
2423 * need to re-fault to ensure that the correct fence register
2424 * setup is in place.
2426 i915_gem_release_mmap(obj);
2428 /* On the i915, GPU access to tiled buffers is via a fence,
2429 * therefore we must wait for any outstanding access to complete
2430 * before clearing the fence.
2432 if (!IS_I965G(dev)) {
2435 ret = i915_gem_object_flush_gpu_write_domain(obj);
2439 ret = i915_gem_object_wait_rendering(obj);
2444 i915_gem_object_flush_gtt_write_domain(obj);
2445 i915_gem_clear_fence_reg (obj);
2451 * Finds free space in the GTT aperture and binds the object there.
2454 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2456 struct drm_device *dev = obj->dev;
2457 drm_i915_private_t *dev_priv = dev->dev_private;
2458 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2459 struct drm_mm_node *free_space;
2460 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2463 if (obj_priv->madv != I915_MADV_WILLNEED) {
2464 DRM_ERROR("Attempting to bind a purgeable object\n");
2469 alignment = i915_gem_get_gtt_alignment(obj);
2470 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2471 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2475 /* If the object is bigger than the entire aperture, reject it early
2476 * before evicting everything in a vain attempt to find space.
2478 if (obj->size > dev->gtt_total) {
2479 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2484 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2485 obj->size, alignment, 0);
2486 if (free_space != NULL) {
2487 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2489 if (obj_priv->gtt_space != NULL)
2490 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2492 if (obj_priv->gtt_space == NULL) {
2493 /* If the gtt is empty and we're still having trouble
2494 * fitting our object in, we're out of memory.
2497 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2499 ret = i915_gem_evict_something(dev, obj->size, alignment);
2507 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2508 obj->size, obj_priv->gtt_offset);
2510 ret = i915_gem_object_get_pages(obj, gfpmask);
2512 drm_mm_put_block(obj_priv->gtt_space);
2513 obj_priv->gtt_space = NULL;
2515 if (ret == -ENOMEM) {
2516 /* first try to clear up some space from the GTT */
2517 ret = i915_gem_evict_something(dev, obj->size,
2520 /* now try to shrink everyone else */
2535 /* Create an AGP memory structure pointing at our pages, and bind it
2538 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2540 obj->size >> PAGE_SHIFT,
2541 obj_priv->gtt_offset,
2542 obj_priv->agp_type);
2543 if (obj_priv->agp_mem == NULL) {
2544 i915_gem_object_put_pages(obj);
2545 drm_mm_put_block(obj_priv->gtt_space);
2546 obj_priv->gtt_space = NULL;
2548 ret = i915_gem_evict_something(dev, obj->size, alignment);
2554 atomic_inc(&dev->gtt_count);
2555 atomic_add(obj->size, &dev->gtt_memory);
2557 /* keep track of bounds object by adding it to the inactive list */
2558 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2560 /* Assert that the object is not currently in any GPU domain. As it
2561 * wasn't in the GTT, there shouldn't be any way it could have been in
2564 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2565 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2567 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2573 i915_gem_clflush_object(struct drm_gem_object *obj)
2575 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2577 /* If we don't have a page list set up, then we're not pinned
2578 * to GPU, and we can ignore the cache flush because it'll happen
2579 * again at bind time.
2581 if (obj_priv->pages == NULL)
2584 trace_i915_gem_object_clflush(obj);
2586 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2589 /** Flushes any GPU write domain for the object if it's dirty. */
2591 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2593 struct drm_device *dev = obj->dev;
2594 uint32_t old_write_domain;
2595 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2597 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2600 /* Queue the GPU write cache flushing we need. */
2601 old_write_domain = obj->write_domain;
2602 i915_gem_flush(dev, 0, obj->write_domain);
2603 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2606 trace_i915_gem_object_change_domain(obj,
2612 /** Flushes the GTT write domain for the object if it's dirty. */
2614 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2616 uint32_t old_write_domain;
2618 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2621 /* No actual flushing is required for the GTT write domain. Writes
2622 * to it immediately go to main memory as far as we know, so there's
2623 * no chipset flush. It also doesn't land in render cache.
2625 old_write_domain = obj->write_domain;
2626 obj->write_domain = 0;
2628 trace_i915_gem_object_change_domain(obj,
2633 /** Flushes the CPU write domain for the object if it's dirty. */
2635 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2637 struct drm_device *dev = obj->dev;
2638 uint32_t old_write_domain;
2640 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2643 i915_gem_clflush_object(obj);
2644 drm_agp_chipset_flush(dev);
2645 old_write_domain = obj->write_domain;
2646 obj->write_domain = 0;
2648 trace_i915_gem_object_change_domain(obj,
2654 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2658 switch (obj->write_domain) {
2659 case I915_GEM_DOMAIN_GTT:
2660 i915_gem_object_flush_gtt_write_domain(obj);
2662 case I915_GEM_DOMAIN_CPU:
2663 i915_gem_object_flush_cpu_write_domain(obj);
2666 ret = i915_gem_object_flush_gpu_write_domain(obj);
2674 * Moves a single object to the GTT read, and possibly write domain.
2676 * This function returns when the move is complete, including waiting on
2680 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2682 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2683 uint32_t old_write_domain, old_read_domains;
2686 /* Not valid to be called on unbound objects. */
2687 if (obj_priv->gtt_space == NULL)
2690 ret = i915_gem_object_flush_gpu_write_domain(obj);
2694 /* Wait on any GPU rendering and flushing to occur. */
2695 ret = i915_gem_object_wait_rendering(obj);
2699 old_write_domain = obj->write_domain;
2700 old_read_domains = obj->read_domains;
2702 /* If we're writing through the GTT domain, then CPU and GPU caches
2703 * will need to be invalidated at next use.
2706 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2708 i915_gem_object_flush_cpu_write_domain(obj);
2710 /* It should now be out of any other write domains, and we can update
2711 * the domain values for our changes.
2713 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2714 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2716 obj->write_domain = I915_GEM_DOMAIN_GTT;
2717 obj_priv->dirty = 1;
2720 trace_i915_gem_object_change_domain(obj,
2728 * Prepare buffer for display plane. Use uninterruptible for possible flush
2729 * wait, as in modesetting process we're not supposed to be interrupted.
2732 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2734 struct drm_device *dev = obj->dev;
2735 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2736 uint32_t old_write_domain, old_read_domains;
2739 /* Not valid to be called on unbound objects. */
2740 if (obj_priv->gtt_space == NULL)
2743 ret = i915_gem_object_flush_gpu_write_domain(obj);
2747 /* Wait on any GPU rendering and flushing to occur. */
2748 if (obj_priv->active) {
2750 DRM_INFO("%s: object %p wait for seqno %08x\n",
2751 __func__, obj, obj_priv->last_rendering_seqno);
2753 ret = i915_do_wait_request(dev,
2754 obj_priv->last_rendering_seqno,
2761 i915_gem_object_flush_cpu_write_domain(obj);
2763 old_write_domain = obj->write_domain;
2764 old_read_domains = obj->read_domains;
2766 /* It should now be out of any other write domains, and we can update
2767 * the domain values for our changes.
2769 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2770 obj->read_domains = I915_GEM_DOMAIN_GTT;
2771 obj->write_domain = I915_GEM_DOMAIN_GTT;
2772 obj_priv->dirty = 1;
2774 trace_i915_gem_object_change_domain(obj,
2782 * Moves a single object to the CPU read, and possibly write domain.
2784 * This function returns when the move is complete, including waiting on
2788 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2790 uint32_t old_write_domain, old_read_domains;
2793 ret = i915_gem_object_flush_gpu_write_domain(obj);
2797 /* Wait on any GPU rendering and flushing to occur. */
2798 ret = i915_gem_object_wait_rendering(obj);
2802 i915_gem_object_flush_gtt_write_domain(obj);
2804 /* If we have a partially-valid cache of the object in the CPU,
2805 * finish invalidating it and free the per-page flags.
2807 i915_gem_object_set_to_full_cpu_read_domain(obj);
2809 old_write_domain = obj->write_domain;
2810 old_read_domains = obj->read_domains;
2812 /* Flush the CPU cache if it's still invalid. */
2813 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2814 i915_gem_clflush_object(obj);
2816 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2819 /* It should now be out of any other write domains, and we can update
2820 * the domain values for our changes.
2822 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2824 /* If we're writing through the CPU, then the GPU read domains will
2825 * need to be invalidated at next use.
2828 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2829 obj->write_domain = I915_GEM_DOMAIN_CPU;
2832 trace_i915_gem_object_change_domain(obj,
2840 * Set the next domain for the specified object. This
2841 * may not actually perform the necessary flushing/invaliding though,
2842 * as that may want to be batched with other set_domain operations
2844 * This is (we hope) the only really tricky part of gem. The goal
2845 * is fairly simple -- track which caches hold bits of the object
2846 * and make sure they remain coherent. A few concrete examples may
2847 * help to explain how it works. For shorthand, we use the notation
2848 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2849 * a pair of read and write domain masks.
2851 * Case 1: the batch buffer
2857 * 5. Unmapped from GTT
2860 * Let's take these a step at a time
2863 * Pages allocated from the kernel may still have
2864 * cache contents, so we set them to (CPU, CPU) always.
2865 * 2. Written by CPU (using pwrite)
2866 * The pwrite function calls set_domain (CPU, CPU) and
2867 * this function does nothing (as nothing changes)
2869 * This function asserts that the object is not
2870 * currently in any GPU-based read or write domains
2872 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2873 * As write_domain is zero, this function adds in the
2874 * current read domains (CPU+COMMAND, 0).
2875 * flush_domains is set to CPU.
2876 * invalidate_domains is set to COMMAND
2877 * clflush is run to get data out of the CPU caches
2878 * then i915_dev_set_domain calls i915_gem_flush to
2879 * emit an MI_FLUSH and drm_agp_chipset_flush
2880 * 5. Unmapped from GTT
2881 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2882 * flush_domains and invalidate_domains end up both zero
2883 * so no flushing/invalidating happens
2887 * Case 2: The shared render buffer
2891 * 3. Read/written by GPU
2892 * 4. set_domain to (CPU,CPU)
2893 * 5. Read/written by CPU
2894 * 6. Read/written by GPU
2897 * Same as last example, (CPU, CPU)
2899 * Nothing changes (assertions find that it is not in the GPU)
2900 * 3. Read/written by GPU
2901 * execbuffer calls set_domain (RENDER, RENDER)
2902 * flush_domains gets CPU
2903 * invalidate_domains gets GPU
2905 * MI_FLUSH and drm_agp_chipset_flush
2906 * 4. set_domain (CPU, CPU)
2907 * flush_domains gets GPU
2908 * invalidate_domains gets CPU
2909 * wait_rendering (obj) to make sure all drawing is complete.
2910 * This will include an MI_FLUSH to get the data from GPU
2912 * clflush (obj) to invalidate the CPU cache
2913 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2914 * 5. Read/written by CPU
2915 * cache lines are loaded and dirtied
2916 * 6. Read written by GPU
2917 * Same as last GPU access
2919 * Case 3: The constant buffer
2924 * 4. Updated (written) by CPU again
2933 * flush_domains = CPU
2934 * invalidate_domains = RENDER
2937 * drm_agp_chipset_flush
2938 * 4. Updated (written) by CPU again
2940 * flush_domains = 0 (no previous write domain)
2941 * invalidate_domains = 0 (no new read domains)
2944 * flush_domains = CPU
2945 * invalidate_domains = RENDER
2948 * drm_agp_chipset_flush
2951 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2953 struct drm_device *dev = obj->dev;
2954 drm_i915_private_t *dev_priv = dev->dev_private;
2955 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2956 uint32_t invalidate_domains = 0;
2957 uint32_t flush_domains = 0;
2958 uint32_t old_read_domains;
2960 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2961 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2963 intel_mark_busy(dev, obj);
2966 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2968 obj->read_domains, obj->pending_read_domains,
2969 obj->write_domain, obj->pending_write_domain);
2972 * If the object isn't moving to a new write domain,
2973 * let the object stay in multiple read domains
2975 if (obj->pending_write_domain == 0)
2976 obj->pending_read_domains |= obj->read_domains;
2978 obj_priv->dirty = 1;
2981 * Flush the current write domain if
2982 * the new read domains don't match. Invalidate
2983 * any read domains which differ from the old
2986 if (obj->write_domain &&
2987 obj->write_domain != obj->pending_read_domains) {
2988 flush_domains |= obj->write_domain;
2989 invalidate_domains |=
2990 obj->pending_read_domains & ~obj->write_domain;
2993 * Invalidate any read caches which may have
2994 * stale data. That is, any new read domains.
2996 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
2997 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
2999 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3000 __func__, flush_domains, invalidate_domains);
3002 i915_gem_clflush_object(obj);
3005 old_read_domains = obj->read_domains;
3007 /* The actual obj->write_domain will be updated with
3008 * pending_write_domain after we emit the accumulated flush for all
3009 * of our domain changes in execbuffers (which clears objects'
3010 * write_domains). So if we have a current write domain that we
3011 * aren't changing, set pending_write_domain to that.
3013 if (flush_domains == 0 && obj->pending_write_domain == 0)
3014 obj->pending_write_domain = obj->write_domain;
3015 obj->read_domains = obj->pending_read_domains;
3017 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3018 if (obj_priv->ring == &dev_priv->render_ring)
3019 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3020 else if (obj_priv->ring == &dev_priv->bsd_ring)
3021 dev_priv->flush_rings |= FLUSH_BSD_RING;
3024 dev->invalidate_domains |= invalidate_domains;
3025 dev->flush_domains |= flush_domains;
3027 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3029 obj->read_domains, obj->write_domain,
3030 dev->invalidate_domains, dev->flush_domains);
3033 trace_i915_gem_object_change_domain(obj,
3039 * Moves the object from a partially CPU read to a full one.
3041 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3042 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3045 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3047 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3049 if (!obj_priv->page_cpu_valid)
3052 /* If we're partially in the CPU read domain, finish moving it in.
3054 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3057 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3058 if (obj_priv->page_cpu_valid[i])
3060 drm_clflush_pages(obj_priv->pages + i, 1);
3064 /* Free the page_cpu_valid mappings which are now stale, whether
3065 * or not we've got I915_GEM_DOMAIN_CPU.
3067 kfree(obj_priv->page_cpu_valid);
3068 obj_priv->page_cpu_valid = NULL;
3072 * Set the CPU read domain on a range of the object.
3074 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3075 * not entirely valid. The page_cpu_valid member of the object flags which
3076 * pages have been flushed, and will be respected by
3077 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3078 * of the whole object.
3080 * This function returns when the move is complete, including waiting on
3084 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3085 uint64_t offset, uint64_t size)
3087 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3088 uint32_t old_read_domains;
3091 if (offset == 0 && size == obj->size)
3092 return i915_gem_object_set_to_cpu_domain(obj, 0);
3094 ret = i915_gem_object_flush_gpu_write_domain(obj);
3098 /* Wait on any GPU rendering and flushing to occur. */
3099 ret = i915_gem_object_wait_rendering(obj);
3102 i915_gem_object_flush_gtt_write_domain(obj);
3104 /* If we're already fully in the CPU read domain, we're done. */
3105 if (obj_priv->page_cpu_valid == NULL &&
3106 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3109 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3110 * newly adding I915_GEM_DOMAIN_CPU
3112 if (obj_priv->page_cpu_valid == NULL) {
3113 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3115 if (obj_priv->page_cpu_valid == NULL)
3117 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3118 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3120 /* Flush the cache on any pages that are still invalid from the CPU's
3123 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3125 if (obj_priv->page_cpu_valid[i])
3128 drm_clflush_pages(obj_priv->pages + i, 1);
3130 obj_priv->page_cpu_valid[i] = 1;
3133 /* It should now be out of any other write domains, and we can update
3134 * the domain values for our changes.
3136 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3138 old_read_domains = obj->read_domains;
3139 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3141 trace_i915_gem_object_change_domain(obj,
3149 * Pin an object to the GTT and evaluate the relocations landing in it.
3152 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3153 struct drm_file *file_priv,
3154 struct drm_i915_gem_exec_object2 *entry,
3155 struct drm_i915_gem_relocation_entry *relocs)
3157 struct drm_device *dev = obj->dev;
3158 drm_i915_private_t *dev_priv = dev->dev_private;
3159 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3161 void __iomem *reloc_page;
3164 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3165 obj_priv->tiling_mode != I915_TILING_NONE;
3167 /* Check fence reg constraints and rebind if necessary */
3169 !i915_gem_object_fence_offset_ok(obj,
3170 obj_priv->tiling_mode)) {
3171 ret = i915_gem_object_unbind(obj);
3176 /* Choose the GTT offset for our buffer and put it there. */
3177 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3182 * Pre-965 chips need a fence register set up in order to
3183 * properly handle blits to/from tiled surfaces.
3186 ret = i915_gem_object_get_fence_reg(obj);
3188 i915_gem_object_unpin(obj);
3193 entry->offset = obj_priv->gtt_offset;
3195 /* Apply the relocations, using the GTT aperture to avoid cache
3196 * flushing requirements.
3198 for (i = 0; i < entry->relocation_count; i++) {
3199 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3200 struct drm_gem_object *target_obj;
3201 struct drm_i915_gem_object *target_obj_priv;
3202 uint32_t reloc_val, reloc_offset;
3203 uint32_t __iomem *reloc_entry;
3205 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3206 reloc->target_handle);
3207 if (target_obj == NULL) {
3208 i915_gem_object_unpin(obj);
3211 target_obj_priv = to_intel_bo(target_obj);
3214 DRM_INFO("%s: obj %p offset %08x target %d "
3215 "read %08x write %08x gtt %08x "
3216 "presumed %08x delta %08x\n",
3219 (int) reloc->offset,
3220 (int) reloc->target_handle,
3221 (int) reloc->read_domains,
3222 (int) reloc->write_domain,
3223 (int) target_obj_priv->gtt_offset,
3224 (int) reloc->presumed_offset,
3228 /* The target buffer should have appeared before us in the
3229 * exec_object list, so it should have a GTT space bound by now.
3231 if (target_obj_priv->gtt_space == NULL) {
3232 DRM_ERROR("No GTT space found for object %d\n",
3233 reloc->target_handle);
3234 drm_gem_object_unreference(target_obj);
3235 i915_gem_object_unpin(obj);
3239 /* Validate that the target is in a valid r/w GPU domain */
3240 if (reloc->write_domain & (reloc->write_domain - 1)) {
3241 DRM_ERROR("reloc with multiple write domains: "
3242 "obj %p target %d offset %d "
3243 "read %08x write %08x",
3244 obj, reloc->target_handle,
3245 (int) reloc->offset,
3246 reloc->read_domains,
3247 reloc->write_domain);
3250 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3251 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3252 DRM_ERROR("reloc with read/write CPU domains: "
3253 "obj %p target %d offset %d "
3254 "read %08x write %08x",
3255 obj, reloc->target_handle,
3256 (int) reloc->offset,
3257 reloc->read_domains,
3258 reloc->write_domain);
3259 drm_gem_object_unreference(target_obj);
3260 i915_gem_object_unpin(obj);
3263 if (reloc->write_domain && target_obj->pending_write_domain &&
3264 reloc->write_domain != target_obj->pending_write_domain) {
3265 DRM_ERROR("Write domain conflict: "
3266 "obj %p target %d offset %d "
3267 "new %08x old %08x\n",
3268 obj, reloc->target_handle,
3269 (int) reloc->offset,
3270 reloc->write_domain,
3271 target_obj->pending_write_domain);
3272 drm_gem_object_unreference(target_obj);
3273 i915_gem_object_unpin(obj);
3277 target_obj->pending_read_domains |= reloc->read_domains;
3278 target_obj->pending_write_domain |= reloc->write_domain;
3280 /* If the relocation already has the right value in it, no
3281 * more work needs to be done.
3283 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3284 drm_gem_object_unreference(target_obj);
3288 /* Check that the relocation address is valid... */
3289 if (reloc->offset > obj->size - 4) {
3290 DRM_ERROR("Relocation beyond object bounds: "
3291 "obj %p target %d offset %d size %d.\n",
3292 obj, reloc->target_handle,
3293 (int) reloc->offset, (int) obj->size);
3294 drm_gem_object_unreference(target_obj);
3295 i915_gem_object_unpin(obj);
3298 if (reloc->offset & 3) {
3299 DRM_ERROR("Relocation not 4-byte aligned: "
3300 "obj %p target %d offset %d.\n",
3301 obj, reloc->target_handle,
3302 (int) reloc->offset);
3303 drm_gem_object_unreference(target_obj);
3304 i915_gem_object_unpin(obj);
3308 /* and points to somewhere within the target object. */
3309 if (reloc->delta >= target_obj->size) {
3310 DRM_ERROR("Relocation beyond target object bounds: "
3311 "obj %p target %d delta %d size %d.\n",
3312 obj, reloc->target_handle,
3313 (int) reloc->delta, (int) target_obj->size);
3314 drm_gem_object_unreference(target_obj);
3315 i915_gem_object_unpin(obj);
3319 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3321 drm_gem_object_unreference(target_obj);
3322 i915_gem_object_unpin(obj);
3326 /* Map the page containing the relocation we're going to
3329 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3330 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3334 reloc_entry = (uint32_t __iomem *)(reloc_page +
3335 (reloc_offset & (PAGE_SIZE - 1)));
3336 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3339 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3340 obj, (unsigned int) reloc->offset,
3341 readl(reloc_entry), reloc_val);
3343 writel(reloc_val, reloc_entry);
3344 io_mapping_unmap_atomic(reloc_page, KM_USER0);
3346 /* The updated presumed offset for this entry will be
3347 * copied back out to the user.
3349 reloc->presumed_offset = target_obj_priv->gtt_offset;
3351 drm_gem_object_unreference(target_obj);
3356 i915_gem_dump_object(obj, 128, __func__, ~0);
3361 /* Throttle our rendering by waiting until the ring has completed our requests
3362 * emitted over 20 msec ago.
3364 * Note that if we were to use the current jiffies each time around the loop,
3365 * we wouldn't escape the function with any frames outstanding if the time to
3366 * render a frame was over 20ms.
3368 * This should get us reasonable parallelism between CPU and GPU but also
3369 * relatively low latency when blocking on a particular request to finish.
3372 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3374 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3376 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3378 mutex_lock(&dev->struct_mutex);
3379 while (!list_empty(&i915_file_priv->mm.request_list)) {
3380 struct drm_i915_gem_request *request;
3382 request = list_first_entry(&i915_file_priv->mm.request_list,
3383 struct drm_i915_gem_request,
3386 if (time_after_eq(request->emitted_jiffies, recent_enough))
3389 ret = i915_wait_request(dev, request->seqno, request->ring);
3393 mutex_unlock(&dev->struct_mutex);
3399 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3400 uint32_t buffer_count,
3401 struct drm_i915_gem_relocation_entry **relocs)
3403 uint32_t reloc_count = 0, reloc_index = 0, i;
3407 for (i = 0; i < buffer_count; i++) {
3408 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3410 reloc_count += exec_list[i].relocation_count;
3413 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3414 if (*relocs == NULL) {
3415 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3419 for (i = 0; i < buffer_count; i++) {
3420 struct drm_i915_gem_relocation_entry __user *user_relocs;
3422 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3424 ret = copy_from_user(&(*relocs)[reloc_index],
3426 exec_list[i].relocation_count *
3429 drm_free_large(*relocs);
3434 reloc_index += exec_list[i].relocation_count;
3441 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3442 uint32_t buffer_count,
3443 struct drm_i915_gem_relocation_entry *relocs)
3445 uint32_t reloc_count = 0, i;
3451 for (i = 0; i < buffer_count; i++) {
3452 struct drm_i915_gem_relocation_entry __user *user_relocs;
3455 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3457 unwritten = copy_to_user(user_relocs,
3458 &relocs[reloc_count],
3459 exec_list[i].relocation_count *
3467 reloc_count += exec_list[i].relocation_count;
3471 drm_free_large(relocs);
3477 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3478 uint64_t exec_offset)
3480 uint32_t exec_start, exec_len;
3482 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3483 exec_len = (uint32_t) exec->batch_len;
3485 if ((exec_start | exec_len) & 0x7)
3495 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3496 struct drm_gem_object **object_list,
3499 drm_i915_private_t *dev_priv = dev->dev_private;
3500 struct drm_i915_gem_object *obj_priv;
3505 prepare_to_wait(&dev_priv->pending_flip_queue,
3506 &wait, TASK_INTERRUPTIBLE);
3507 for (i = 0; i < count; i++) {
3508 obj_priv = to_intel_bo(object_list[i]);
3509 if (atomic_read(&obj_priv->pending_flip) > 0)
3515 if (!signal_pending(current)) {
3516 mutex_unlock(&dev->struct_mutex);
3518 mutex_lock(&dev->struct_mutex);
3524 finish_wait(&dev_priv->pending_flip_queue, &wait);
3531 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3532 struct drm_file *file_priv,
3533 struct drm_i915_gem_execbuffer2 *args,
3534 struct drm_i915_gem_exec_object2 *exec_list)
3536 drm_i915_private_t *dev_priv = dev->dev_private;
3537 struct drm_gem_object **object_list = NULL;
3538 struct drm_gem_object *batch_obj;
3539 struct drm_i915_gem_object *obj_priv;
3540 struct drm_clip_rect *cliprects = NULL;
3541 struct drm_i915_gem_relocation_entry *relocs = NULL;
3542 int ret = 0, ret2, i, pinned = 0;
3543 uint64_t exec_offset;
3544 uint32_t seqno, flush_domains, reloc_index;
3545 int pin_tries, flips;
3547 struct intel_ring_buffer *ring = NULL;
3550 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3551 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3553 if (args->flags & I915_EXEC_BSD) {
3554 if (!HAS_BSD(dev)) {
3555 DRM_ERROR("execbuf with wrong flag\n");
3558 ring = &dev_priv->bsd_ring;
3560 ring = &dev_priv->render_ring;
3563 if (args->buffer_count < 1) {
3564 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3567 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3568 if (object_list == NULL) {
3569 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3570 args->buffer_count);
3575 if (args->num_cliprects != 0) {
3576 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3578 if (cliprects == NULL) {
3583 ret = copy_from_user(cliprects,
3584 (struct drm_clip_rect __user *)
3585 (uintptr_t) args->cliprects_ptr,
3586 sizeof(*cliprects) * args->num_cliprects);
3588 DRM_ERROR("copy %d cliprects failed: %d\n",
3589 args->num_cliprects, ret);
3594 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3599 mutex_lock(&dev->struct_mutex);
3601 i915_verify_inactive(dev, __FILE__, __LINE__);
3603 if (atomic_read(&dev_priv->mm.wedged)) {
3604 mutex_unlock(&dev->struct_mutex);
3609 if (dev_priv->mm.suspended) {
3610 mutex_unlock(&dev->struct_mutex);
3615 /* Look up object handles */
3617 for (i = 0; i < args->buffer_count; i++) {
3618 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3619 exec_list[i].handle);
3620 if (object_list[i] == NULL) {
3621 DRM_ERROR("Invalid object handle %d at index %d\n",
3622 exec_list[i].handle, i);
3623 /* prevent error path from reading uninitialized data */
3624 args->buffer_count = i + 1;
3629 obj_priv = to_intel_bo(object_list[i]);
3630 if (obj_priv->in_execbuffer) {
3631 DRM_ERROR("Object %p appears more than once in object list\n",
3633 /* prevent error path from reading uninitialized data */
3634 args->buffer_count = i + 1;
3638 obj_priv->in_execbuffer = true;
3639 flips += atomic_read(&obj_priv->pending_flip);
3643 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3644 args->buffer_count);
3649 /* Pin and relocate */
3650 for (pin_tries = 0; ; pin_tries++) {
3654 for (i = 0; i < args->buffer_count; i++) {
3655 object_list[i]->pending_read_domains = 0;
3656 object_list[i]->pending_write_domain = 0;
3657 ret = i915_gem_object_pin_and_relocate(object_list[i],
3660 &relocs[reloc_index]);
3664 reloc_index += exec_list[i].relocation_count;
3670 /* error other than GTT full, or we've already tried again */
3671 if (ret != -ENOSPC || pin_tries >= 1) {
3672 if (ret != -ERESTARTSYS) {
3673 unsigned long long total_size = 0;
3675 for (i = 0; i < args->buffer_count; i++) {
3676 obj_priv = to_intel_bo(object_list[i]);
3678 total_size += object_list[i]->size;
3680 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3681 obj_priv->tiling_mode != I915_TILING_NONE;
3683 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3684 pinned+1, args->buffer_count,
3685 total_size, num_fences,
3687 DRM_ERROR("%d objects [%d pinned], "
3688 "%d object bytes [%d pinned], "
3689 "%d/%d gtt bytes\n",
3690 atomic_read(&dev->object_count),
3691 atomic_read(&dev->pin_count),
3692 atomic_read(&dev->object_memory),
3693 atomic_read(&dev->pin_memory),
3694 atomic_read(&dev->gtt_memory),
3700 /* unpin all of our buffers */
3701 for (i = 0; i < pinned; i++)
3702 i915_gem_object_unpin(object_list[i]);
3705 /* evict everyone we can from the aperture */
3706 ret = i915_gem_evict_everything(dev);
3707 if (ret && ret != -ENOSPC)
3711 /* Set the pending read domains for the batch buffer to COMMAND */
3712 batch_obj = object_list[args->buffer_count-1];
3713 if (batch_obj->pending_write_domain) {
3714 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3718 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3720 /* Sanity check the batch buffer, prior to moving objects */
3721 exec_offset = exec_list[args->buffer_count - 1].offset;
3722 ret = i915_gem_check_execbuffer (args, exec_offset);
3724 DRM_ERROR("execbuf with invalid offset/length\n");
3728 i915_verify_inactive(dev, __FILE__, __LINE__);
3730 /* Zero the global flush/invalidate flags. These
3731 * will be modified as new domains are computed
3734 dev->invalidate_domains = 0;
3735 dev->flush_domains = 0;
3736 dev_priv->flush_rings = 0;
3738 for (i = 0; i < args->buffer_count; i++) {
3739 struct drm_gem_object *obj = object_list[i];
3741 /* Compute new gpu domains and update invalidate/flush */
3742 i915_gem_object_set_to_gpu_domain(obj);
3745 i915_verify_inactive(dev, __FILE__, __LINE__);
3747 if (dev->invalidate_domains | dev->flush_domains) {
3749 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3751 dev->invalidate_domains,
3752 dev->flush_domains);
3755 dev->invalidate_domains,
3756 dev->flush_domains);
3757 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3758 (void)i915_add_request(dev, file_priv,
3760 &dev_priv->render_ring);
3761 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3762 (void)i915_add_request(dev, file_priv,
3764 &dev_priv->bsd_ring);
3767 for (i = 0; i < args->buffer_count; i++) {
3768 struct drm_gem_object *obj = object_list[i];
3769 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3770 uint32_t old_write_domain = obj->write_domain;
3772 obj->write_domain = obj->pending_write_domain;
3773 if (obj->write_domain)
3774 list_move_tail(&obj_priv->gpu_write_list,
3775 &dev_priv->mm.gpu_write_list);
3777 list_del_init(&obj_priv->gpu_write_list);
3779 trace_i915_gem_object_change_domain(obj,
3784 i915_verify_inactive(dev, __FILE__, __LINE__);
3787 for (i = 0; i < args->buffer_count; i++) {
3788 i915_gem_object_check_coherency(object_list[i],
3789 exec_list[i].handle);
3794 i915_gem_dump_object(batch_obj,
3800 /* Exec the batchbuffer */
3801 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3802 cliprects, exec_offset);
3804 DRM_ERROR("dispatch failed %d\n", ret);
3809 * Ensure that the commands in the batch buffer are
3810 * finished before the interrupt fires
3812 flush_domains = i915_retire_commands(dev, ring);
3814 i915_verify_inactive(dev, __FILE__, __LINE__);
3817 * Get a seqno representing the execution of the current buffer,
3818 * which we can wait on. We would like to mitigate these interrupts,
3819 * likely by only creating seqnos occasionally (so that we have
3820 * *some* interrupts representing completion of buffers that we can
3821 * wait on when trying to clear up gtt space).
3823 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3825 for (i = 0; i < args->buffer_count; i++) {
3826 struct drm_gem_object *obj = object_list[i];
3827 obj_priv = to_intel_bo(obj);
3829 i915_gem_object_move_to_active(obj, seqno, ring);
3831 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3835 i915_dump_lru(dev, __func__);
3838 i915_verify_inactive(dev, __FILE__, __LINE__);
3841 for (i = 0; i < pinned; i++)
3842 i915_gem_object_unpin(object_list[i]);
3844 for (i = 0; i < args->buffer_count; i++) {
3845 if (object_list[i]) {
3846 obj_priv = to_intel_bo(object_list[i]);
3847 obj_priv->in_execbuffer = false;
3849 drm_gem_object_unreference(object_list[i]);
3852 mutex_unlock(&dev->struct_mutex);
3855 /* Copy the updated relocations out regardless of current error
3856 * state. Failure to update the relocs would mean that the next
3857 * time userland calls execbuf, it would do so with presumed offset
3858 * state that didn't match the actual object state.
3860 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3863 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3869 drm_free_large(object_list);
3876 * Legacy execbuffer just creates an exec2 list from the original exec object
3877 * list array and passes it to the real function.
3880 i915_gem_execbuffer(struct drm_device *dev, void *data,
3881 struct drm_file *file_priv)
3883 struct drm_i915_gem_execbuffer *args = data;
3884 struct drm_i915_gem_execbuffer2 exec2;
3885 struct drm_i915_gem_exec_object *exec_list = NULL;
3886 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3890 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3891 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3894 if (args->buffer_count < 1) {
3895 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3899 /* Copy in the exec list from userland */
3900 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3901 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3902 if (exec_list == NULL || exec2_list == NULL) {
3903 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3904 args->buffer_count);
3905 drm_free_large(exec_list);
3906 drm_free_large(exec2_list);
3909 ret = copy_from_user(exec_list,
3910 (struct drm_i915_relocation_entry __user *)
3911 (uintptr_t) args->buffers_ptr,
3912 sizeof(*exec_list) * args->buffer_count);
3914 DRM_ERROR("copy %d exec entries failed %d\n",
3915 args->buffer_count, ret);
3916 drm_free_large(exec_list);
3917 drm_free_large(exec2_list);
3921 for (i = 0; i < args->buffer_count; i++) {
3922 exec2_list[i].handle = exec_list[i].handle;
3923 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3924 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3925 exec2_list[i].alignment = exec_list[i].alignment;
3926 exec2_list[i].offset = exec_list[i].offset;
3928 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3930 exec2_list[i].flags = 0;
3933 exec2.buffers_ptr = args->buffers_ptr;
3934 exec2.buffer_count = args->buffer_count;
3935 exec2.batch_start_offset = args->batch_start_offset;
3936 exec2.batch_len = args->batch_len;
3937 exec2.DR1 = args->DR1;
3938 exec2.DR4 = args->DR4;
3939 exec2.num_cliprects = args->num_cliprects;
3940 exec2.cliprects_ptr = args->cliprects_ptr;
3941 exec2.flags = I915_EXEC_RENDER;
3943 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3945 /* Copy the new buffer offsets back to the user's exec list. */
3946 for (i = 0; i < args->buffer_count; i++)
3947 exec_list[i].offset = exec2_list[i].offset;
3948 /* ... and back out to userspace */
3949 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3950 (uintptr_t) args->buffers_ptr,
3952 sizeof(*exec_list) * args->buffer_count);
3955 DRM_ERROR("failed to copy %d exec entries "
3956 "back to user (%d)\n",
3957 args->buffer_count, ret);
3961 drm_free_large(exec_list);
3962 drm_free_large(exec2_list);
3967 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3968 struct drm_file *file_priv)
3970 struct drm_i915_gem_execbuffer2 *args = data;
3971 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3975 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3976 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3979 if (args->buffer_count < 1) {
3980 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3984 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3985 if (exec2_list == NULL) {
3986 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3987 args->buffer_count);
3990 ret = copy_from_user(exec2_list,
3991 (struct drm_i915_relocation_entry __user *)
3992 (uintptr_t) args->buffers_ptr,
3993 sizeof(*exec2_list) * args->buffer_count);
3995 DRM_ERROR("copy %d exec entries failed %d\n",
3996 args->buffer_count, ret);
3997 drm_free_large(exec2_list);
4001 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4003 /* Copy the new buffer offsets back to the user's exec list. */
4004 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4005 (uintptr_t) args->buffers_ptr,
4007 sizeof(*exec2_list) * args->buffer_count);
4010 DRM_ERROR("failed to copy %d exec entries "
4011 "back to user (%d)\n",
4012 args->buffer_count, ret);
4016 drm_free_large(exec2_list);
4021 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4023 struct drm_device *dev = obj->dev;
4024 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4027 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4029 i915_verify_inactive(dev, __FILE__, __LINE__);
4031 if (obj_priv->gtt_space != NULL) {
4033 alignment = i915_gem_get_gtt_alignment(obj);
4034 if (obj_priv->gtt_offset & (alignment - 1)) {
4035 WARN(obj_priv->pin_count,
4036 "bo is already pinned with incorrect alignment:"
4037 " offset=%x, req.alignment=%x\n",
4038 obj_priv->gtt_offset, alignment);
4039 ret = i915_gem_object_unbind(obj);
4045 if (obj_priv->gtt_space == NULL) {
4046 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4051 obj_priv->pin_count++;
4053 /* If the object is not active and not pending a flush,
4054 * remove it from the inactive list
4056 if (obj_priv->pin_count == 1) {
4057 atomic_inc(&dev->pin_count);
4058 atomic_add(obj->size, &dev->pin_memory);
4059 if (!obj_priv->active &&
4060 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4061 list_del_init(&obj_priv->list);
4063 i915_verify_inactive(dev, __FILE__, __LINE__);
4069 i915_gem_object_unpin(struct drm_gem_object *obj)
4071 struct drm_device *dev = obj->dev;
4072 drm_i915_private_t *dev_priv = dev->dev_private;
4073 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4075 i915_verify_inactive(dev, __FILE__, __LINE__);
4076 obj_priv->pin_count--;
4077 BUG_ON(obj_priv->pin_count < 0);
4078 BUG_ON(obj_priv->gtt_space == NULL);
4080 /* If the object is no longer pinned, and is
4081 * neither active nor being flushed, then stick it on
4084 if (obj_priv->pin_count == 0) {
4085 if (!obj_priv->active &&
4086 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4087 list_move_tail(&obj_priv->list,
4088 &dev_priv->mm.inactive_list);
4089 atomic_dec(&dev->pin_count);
4090 atomic_sub(obj->size, &dev->pin_memory);
4092 i915_verify_inactive(dev, __FILE__, __LINE__);
4096 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4097 struct drm_file *file_priv)
4099 struct drm_i915_gem_pin *args = data;
4100 struct drm_gem_object *obj;
4101 struct drm_i915_gem_object *obj_priv;
4104 mutex_lock(&dev->struct_mutex);
4106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4108 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4110 mutex_unlock(&dev->struct_mutex);
4113 obj_priv = to_intel_bo(obj);
4115 if (obj_priv->madv != I915_MADV_WILLNEED) {
4116 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4117 drm_gem_object_unreference(obj);
4118 mutex_unlock(&dev->struct_mutex);
4122 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4123 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4125 drm_gem_object_unreference(obj);
4126 mutex_unlock(&dev->struct_mutex);
4130 obj_priv->user_pin_count++;
4131 obj_priv->pin_filp = file_priv;
4132 if (obj_priv->user_pin_count == 1) {
4133 ret = i915_gem_object_pin(obj, args->alignment);
4135 drm_gem_object_unreference(obj);
4136 mutex_unlock(&dev->struct_mutex);
4141 /* XXX - flush the CPU caches for pinned objects
4142 * as the X server doesn't manage domains yet
4144 i915_gem_object_flush_cpu_write_domain(obj);
4145 args->offset = obj_priv->gtt_offset;
4146 drm_gem_object_unreference(obj);
4147 mutex_unlock(&dev->struct_mutex);
4153 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4154 struct drm_file *file_priv)
4156 struct drm_i915_gem_pin *args = data;
4157 struct drm_gem_object *obj;
4158 struct drm_i915_gem_object *obj_priv;
4160 mutex_lock(&dev->struct_mutex);
4162 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4164 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4166 mutex_unlock(&dev->struct_mutex);
4170 obj_priv = to_intel_bo(obj);
4171 if (obj_priv->pin_filp != file_priv) {
4172 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4174 drm_gem_object_unreference(obj);
4175 mutex_unlock(&dev->struct_mutex);
4178 obj_priv->user_pin_count--;
4179 if (obj_priv->user_pin_count == 0) {
4180 obj_priv->pin_filp = NULL;
4181 i915_gem_object_unpin(obj);
4184 drm_gem_object_unreference(obj);
4185 mutex_unlock(&dev->struct_mutex);
4190 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4191 struct drm_file *file_priv)
4193 struct drm_i915_gem_busy *args = data;
4194 struct drm_gem_object *obj;
4195 struct drm_i915_gem_object *obj_priv;
4197 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4199 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4204 mutex_lock(&dev->struct_mutex);
4206 /* Count all active objects as busy, even if they are currently not used
4207 * by the gpu. Users of this interface expect objects to eventually
4208 * become non-busy without any further actions, therefore emit any
4209 * necessary flushes here.
4211 obj_priv = to_intel_bo(obj);
4212 args->busy = obj_priv->active;
4214 /* Unconditionally flush objects, even when the gpu still uses this
4215 * object. Userspace calling this function indicates that it wants to
4216 * use this buffer rather sooner than later, so issuing the required
4217 * flush earlier is beneficial.
4219 if (obj->write_domain) {
4220 i915_gem_flush(dev, 0, obj->write_domain);
4221 (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4224 /* Update the active list for the hardware's current position.
4225 * Otherwise this only updates on a delayed timer or when irqs
4226 * are actually unmasked, and our working set ends up being
4227 * larger than required.
4229 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4231 args->busy = obj_priv->active;
4234 drm_gem_object_unreference(obj);
4235 mutex_unlock(&dev->struct_mutex);
4240 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4241 struct drm_file *file_priv)
4243 return i915_gem_ring_throttle(dev, file_priv);
4247 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4248 struct drm_file *file_priv)
4250 struct drm_i915_gem_madvise *args = data;
4251 struct drm_gem_object *obj;
4252 struct drm_i915_gem_object *obj_priv;
4254 switch (args->madv) {
4255 case I915_MADV_DONTNEED:
4256 case I915_MADV_WILLNEED:
4262 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4264 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4269 mutex_lock(&dev->struct_mutex);
4270 obj_priv = to_intel_bo(obj);
4272 if (obj_priv->pin_count) {
4273 drm_gem_object_unreference(obj);
4274 mutex_unlock(&dev->struct_mutex);
4276 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4280 if (obj_priv->madv != __I915_MADV_PURGED)
4281 obj_priv->madv = args->madv;
4283 /* if the object is no longer bound, discard its backing storage */
4284 if (i915_gem_object_is_purgeable(obj_priv) &&
4285 obj_priv->gtt_space == NULL)
4286 i915_gem_object_truncate(obj);
4288 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4290 drm_gem_object_unreference(obj);
4291 mutex_unlock(&dev->struct_mutex);
4296 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4299 struct drm_i915_gem_object *obj;
4301 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4305 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4310 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4311 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4313 obj->agp_type = AGP_USER_MEMORY;
4314 obj->base.driver_private = NULL;
4315 obj->fence_reg = I915_FENCE_REG_NONE;
4316 INIT_LIST_HEAD(&obj->list);
4317 INIT_LIST_HEAD(&obj->gpu_write_list);
4318 obj->madv = I915_MADV_WILLNEED;
4320 trace_i915_gem_object_create(&obj->base);
4325 int i915_gem_init_object(struct drm_gem_object *obj)
4332 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4334 struct drm_device *dev = obj->dev;
4335 drm_i915_private_t *dev_priv = dev->dev_private;
4336 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4339 ret = i915_gem_object_unbind(obj);
4340 if (ret == -ERESTARTSYS) {
4341 list_move(&obj_priv->list,
4342 &dev_priv->mm.deferred_free_list);
4346 if (obj_priv->mmap_offset)
4347 i915_gem_free_mmap_offset(obj);
4349 drm_gem_object_release(obj);
4351 kfree(obj_priv->page_cpu_valid);
4352 kfree(obj_priv->bit_17);
4356 void i915_gem_free_object(struct drm_gem_object *obj)
4358 struct drm_device *dev = obj->dev;
4359 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4361 trace_i915_gem_object_destroy(obj);
4363 while (obj_priv->pin_count > 0)
4364 i915_gem_object_unpin(obj);
4366 if (obj_priv->phys_obj)
4367 i915_gem_detach_phys_object(dev, obj);
4369 i915_gem_free_object_tail(obj);
4373 i915_gem_idle(struct drm_device *dev)
4375 drm_i915_private_t *dev_priv = dev->dev_private;
4378 mutex_lock(&dev->struct_mutex);
4380 if (dev_priv->mm.suspended ||
4381 (dev_priv->render_ring.gem_object == NULL) ||
4383 dev_priv->bsd_ring.gem_object == NULL)) {
4384 mutex_unlock(&dev->struct_mutex);
4388 ret = i915_gpu_idle(dev);
4390 mutex_unlock(&dev->struct_mutex);
4394 /* Under UMS, be paranoid and evict. */
4395 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4396 ret = i915_gem_evict_inactive(dev);
4398 mutex_unlock(&dev->struct_mutex);
4403 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4404 * We need to replace this with a semaphore, or something.
4405 * And not confound mm.suspended!
4407 dev_priv->mm.suspended = 1;
4408 del_timer(&dev_priv->hangcheck_timer);
4410 i915_kernel_lost_context(dev);
4411 i915_gem_cleanup_ringbuffer(dev);
4413 mutex_unlock(&dev->struct_mutex);
4415 /* Cancel the retire work handler, which should be idle now. */
4416 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4422 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4423 * over cache flushing.
4426 i915_gem_init_pipe_control(struct drm_device *dev)
4428 drm_i915_private_t *dev_priv = dev->dev_private;
4429 struct drm_gem_object *obj;
4430 struct drm_i915_gem_object *obj_priv;
4433 obj = i915_gem_alloc_object(dev, 4096);
4435 DRM_ERROR("Failed to allocate seqno page\n");
4439 obj_priv = to_intel_bo(obj);
4440 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4442 ret = i915_gem_object_pin(obj, 4096);
4446 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4447 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4448 if (dev_priv->seqno_page == NULL)
4451 dev_priv->seqno_obj = obj;
4452 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4457 i915_gem_object_unpin(obj);
4459 drm_gem_object_unreference(obj);
4466 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4468 drm_i915_private_t *dev_priv = dev->dev_private;
4469 struct drm_gem_object *obj;
4470 struct drm_i915_gem_object *obj_priv;
4472 obj = dev_priv->seqno_obj;
4473 obj_priv = to_intel_bo(obj);
4474 kunmap(obj_priv->pages[0]);
4475 i915_gem_object_unpin(obj);
4476 drm_gem_object_unreference(obj);
4477 dev_priv->seqno_obj = NULL;
4479 dev_priv->seqno_page = NULL;
4483 i915_gem_init_ringbuffer(struct drm_device *dev)
4485 drm_i915_private_t *dev_priv = dev->dev_private;
4488 dev_priv->render_ring = render_ring;
4490 if (!I915_NEED_GFX_HWS(dev)) {
4491 dev_priv->render_ring.status_page.page_addr
4492 = dev_priv->status_page_dmah->vaddr;
4493 memset(dev_priv->render_ring.status_page.page_addr,
4497 if (HAS_PIPE_CONTROL(dev)) {
4498 ret = i915_gem_init_pipe_control(dev);
4503 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4505 goto cleanup_pipe_control;
4508 dev_priv->bsd_ring = bsd_ring;
4509 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4511 goto cleanup_render_ring;
4514 dev_priv->next_seqno = 1;
4518 cleanup_render_ring:
4519 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4520 cleanup_pipe_control:
4521 if (HAS_PIPE_CONTROL(dev))
4522 i915_gem_cleanup_pipe_control(dev);
4527 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4529 drm_i915_private_t *dev_priv = dev->dev_private;
4531 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4533 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4534 if (HAS_PIPE_CONTROL(dev))
4535 i915_gem_cleanup_pipe_control(dev);
4539 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4540 struct drm_file *file_priv)
4542 drm_i915_private_t *dev_priv = dev->dev_private;
4545 if (drm_core_check_feature(dev, DRIVER_MODESET))
4548 if (atomic_read(&dev_priv->mm.wedged)) {
4549 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4550 atomic_set(&dev_priv->mm.wedged, 0);
4553 mutex_lock(&dev->struct_mutex);
4554 dev_priv->mm.suspended = 0;
4556 ret = i915_gem_init_ringbuffer(dev);
4558 mutex_unlock(&dev->struct_mutex);
4562 spin_lock(&dev_priv->mm.active_list_lock);
4563 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4564 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4565 spin_unlock(&dev_priv->mm.active_list_lock);
4567 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4568 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4569 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4570 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4571 mutex_unlock(&dev->struct_mutex);
4573 ret = drm_irq_install(dev);
4575 goto cleanup_ringbuffer;
4580 mutex_lock(&dev->struct_mutex);
4581 i915_gem_cleanup_ringbuffer(dev);
4582 dev_priv->mm.suspended = 1;
4583 mutex_unlock(&dev->struct_mutex);
4589 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4590 struct drm_file *file_priv)
4592 if (drm_core_check_feature(dev, DRIVER_MODESET))
4595 drm_irq_uninstall(dev);
4596 return i915_gem_idle(dev);
4600 i915_gem_lastclose(struct drm_device *dev)
4604 if (drm_core_check_feature(dev, DRIVER_MODESET))
4607 ret = i915_gem_idle(dev);
4609 DRM_ERROR("failed to idle hardware: %d\n", ret);
4613 i915_gem_load(struct drm_device *dev)
4616 drm_i915_private_t *dev_priv = dev->dev_private;
4618 spin_lock_init(&dev_priv->mm.active_list_lock);
4619 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4620 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4621 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4622 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4623 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4624 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4625 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4627 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4628 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4630 for (i = 0; i < 16; i++)
4631 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4632 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4633 i915_gem_retire_work_handler);
4634 spin_lock(&shrink_list_lock);
4635 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4636 spin_unlock(&shrink_list_lock);
4638 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4640 u32 tmp = I915_READ(MI_ARB_STATE);
4641 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4642 /* arb state is a masked write, so set bit + bit in mask */
4643 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4644 I915_WRITE(MI_ARB_STATE, tmp);
4648 /* Old X drivers will take 0-2 for front, back, depth buffers */
4649 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4650 dev_priv->fence_reg_start = 3;
4652 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4653 dev_priv->num_fence_regs = 16;
4655 dev_priv->num_fence_regs = 8;
4657 /* Initialize fence registers to zero */
4658 if (IS_I965G(dev)) {
4659 for (i = 0; i < 16; i++)
4660 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4662 for (i = 0; i < 8; i++)
4663 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4664 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4665 for (i = 0; i < 8; i++)
4666 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4668 i915_gem_detect_bit_6_swizzle(dev);
4669 init_waitqueue_head(&dev_priv->pending_flip_queue);
4673 * Create a physically contiguous memory object for this object
4674 * e.g. for cursor + overlay regs
4676 int i915_gem_init_phys_object(struct drm_device *dev,
4677 int id, int size, int align)
4679 drm_i915_private_t *dev_priv = dev->dev_private;
4680 struct drm_i915_gem_phys_object *phys_obj;
4683 if (dev_priv->mm.phys_objs[id - 1] || !size)
4686 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4692 phys_obj->handle = drm_pci_alloc(dev, size, align);
4693 if (!phys_obj->handle) {
4698 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4701 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4709 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4711 drm_i915_private_t *dev_priv = dev->dev_private;
4712 struct drm_i915_gem_phys_object *phys_obj;
4714 if (!dev_priv->mm.phys_objs[id - 1])
4717 phys_obj = dev_priv->mm.phys_objs[id - 1];
4718 if (phys_obj->cur_obj) {
4719 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4723 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4725 drm_pci_free(dev, phys_obj->handle);
4727 dev_priv->mm.phys_objs[id - 1] = NULL;
4730 void i915_gem_free_all_phys_object(struct drm_device *dev)
4734 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4735 i915_gem_free_phys_object(dev, i);
4738 void i915_gem_detach_phys_object(struct drm_device *dev,
4739 struct drm_gem_object *obj)
4741 struct drm_i915_gem_object *obj_priv;
4746 obj_priv = to_intel_bo(obj);
4747 if (!obj_priv->phys_obj)
4750 ret = i915_gem_object_get_pages(obj, 0);
4754 page_count = obj->size / PAGE_SIZE;
4756 for (i = 0; i < page_count; i++) {
4757 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
4758 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4760 memcpy(dst, src, PAGE_SIZE);
4761 kunmap_atomic(dst, KM_USER0);
4763 drm_clflush_pages(obj_priv->pages, page_count);
4764 drm_agp_chipset_flush(dev);
4766 i915_gem_object_put_pages(obj);
4768 obj_priv->phys_obj->cur_obj = NULL;
4769 obj_priv->phys_obj = NULL;
4773 i915_gem_attach_phys_object(struct drm_device *dev,
4774 struct drm_gem_object *obj,
4778 drm_i915_private_t *dev_priv = dev->dev_private;
4779 struct drm_i915_gem_object *obj_priv;
4784 if (id > I915_MAX_PHYS_OBJECT)
4787 obj_priv = to_intel_bo(obj);
4789 if (obj_priv->phys_obj) {
4790 if (obj_priv->phys_obj->id == id)
4792 i915_gem_detach_phys_object(dev, obj);
4795 /* create a new object */
4796 if (!dev_priv->mm.phys_objs[id - 1]) {
4797 ret = i915_gem_init_phys_object(dev, id,
4800 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4805 /* bind to the object */
4806 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4807 obj_priv->phys_obj->cur_obj = obj;
4809 ret = i915_gem_object_get_pages(obj, 0);
4811 DRM_ERROR("failed to get page list\n");
4815 page_count = obj->size / PAGE_SIZE;
4817 for (i = 0; i < page_count; i++) {
4818 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
4819 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4821 memcpy(dst, src, PAGE_SIZE);
4822 kunmap_atomic(src, KM_USER0);
4825 i915_gem_object_put_pages(obj);
4833 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4834 struct drm_i915_gem_pwrite *args,
4835 struct drm_file *file_priv)
4837 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4840 char __user *user_data;
4842 user_data = (char __user *) (uintptr_t) args->data_ptr;
4843 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4845 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4846 ret = copy_from_user(obj_addr, user_data, args->size);
4850 drm_agp_chipset_flush(dev);
4854 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4856 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4858 /* Clean up our request list when the client is going away, so that
4859 * later retire_requests won't dereference our soon-to-be-gone
4862 mutex_lock(&dev->struct_mutex);
4863 while (!list_empty(&i915_file_priv->mm.request_list))
4864 list_del_init(i915_file_priv->mm.request_list.next);
4865 mutex_unlock(&dev->struct_mutex);
4869 i915_gpu_is_active(struct drm_device *dev)
4871 drm_i915_private_t *dev_priv = dev->dev_private;
4874 spin_lock(&dev_priv->mm.active_list_lock);
4875 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4876 list_empty(&dev_priv->render_ring.active_list);
4878 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4879 spin_unlock(&dev_priv->mm.active_list_lock);
4881 return !lists_empty;
4885 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4887 drm_i915_private_t *dev_priv, *next_dev;
4888 struct drm_i915_gem_object *obj_priv, *next_obj;
4890 int would_deadlock = 1;
4892 /* "fast-path" to count number of available objects */
4893 if (nr_to_scan == 0) {
4894 spin_lock(&shrink_list_lock);
4895 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4896 struct drm_device *dev = dev_priv->dev;
4898 if (mutex_trylock(&dev->struct_mutex)) {
4899 list_for_each_entry(obj_priv,
4900 &dev_priv->mm.inactive_list,
4903 mutex_unlock(&dev->struct_mutex);
4906 spin_unlock(&shrink_list_lock);
4908 return (cnt / 100) * sysctl_vfs_cache_pressure;
4911 spin_lock(&shrink_list_lock);
4914 /* first scan for clean buffers */
4915 list_for_each_entry_safe(dev_priv, next_dev,
4916 &shrink_list, mm.shrink_list) {
4917 struct drm_device *dev = dev_priv->dev;
4919 if (! mutex_trylock(&dev->struct_mutex))
4922 spin_unlock(&shrink_list_lock);
4923 i915_gem_retire_requests(dev);
4925 list_for_each_entry_safe(obj_priv, next_obj,
4926 &dev_priv->mm.inactive_list,
4928 if (i915_gem_object_is_purgeable(obj_priv)) {
4929 i915_gem_object_unbind(&obj_priv->base);
4930 if (--nr_to_scan <= 0)
4935 spin_lock(&shrink_list_lock);
4936 mutex_unlock(&dev->struct_mutex);
4940 if (nr_to_scan <= 0)
4944 /* second pass, evict/count anything still on the inactive list */
4945 list_for_each_entry_safe(dev_priv, next_dev,
4946 &shrink_list, mm.shrink_list) {
4947 struct drm_device *dev = dev_priv->dev;
4949 if (! mutex_trylock(&dev->struct_mutex))
4952 spin_unlock(&shrink_list_lock);
4954 list_for_each_entry_safe(obj_priv, next_obj,
4955 &dev_priv->mm.inactive_list,
4957 if (nr_to_scan > 0) {
4958 i915_gem_object_unbind(&obj_priv->base);
4964 spin_lock(&shrink_list_lock);
4965 mutex_unlock(&dev->struct_mutex);
4974 * We are desperate for pages, so as a last resort, wait
4975 * for the GPU to finish and discard whatever we can.
4976 * This has a dramatic impact to reduce the number of
4977 * OOM-killer events whilst running the GPU aggressively.
4979 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4980 struct drm_device *dev = dev_priv->dev;
4982 if (!mutex_trylock(&dev->struct_mutex))
4985 spin_unlock(&shrink_list_lock);
4987 if (i915_gpu_is_active(dev)) {
4992 spin_lock(&shrink_list_lock);
4993 mutex_unlock(&dev->struct_mutex);
5000 spin_unlock(&shrink_list_lock);
5005 return (cnt / 100) * sysctl_vfs_cache_pressure;
5010 static struct shrinker shrinker = {
5011 .shrink = i915_gem_shrink,
5012 .seeks = DEFAULT_SEEKS,
5016 i915_gem_shrinker_init(void)
5018 register_shrinker(&shrinker);
5022 i915_gem_shrinker_exit(void)
5024 unregister_shrinker(&shrinker);