arch/x86/kernel/hpet.c

   1 #include <linux/clocksource.h>
   2 #include <linux/clockchips.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/sysdev.h>
   5 #include <linux/delay.h>
   6 #include <linux/errno.h>
   7 #include <linux/slab.h>
   8 #include <linux/hpet.h>
   9 #include <linux/init.h>
  10 #include <linux/cpu.h>
  11 #include <linux/pm.h>
  12 #include <linux/io.h>
  13
  14 #include <asm/fixmap.h>
  15 #include <asm/i8253.h>
  16 #include <asm/hpet.h>
  17
  18 #define HPET_MASK                       CLOCKSOURCE_MASK(32)
  19
  20 /* FSEC = 10^-15
  21    NSEC = 10^-9 */
  22 #define FSEC_PER_NSEC                   1000000L
  23
  24 #define HPET_DEV_USED_BIT               2
  25 #define HPET_DEV_USED                   (1 << HPET_DEV_USED_BIT)
  26 #define HPET_DEV_VALID                  0x8
  27 #define HPET_DEV_FSB_CAP                0x1000
  28 #define HPET_DEV_PERI_CAP               0x2000
  29
  30 #define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
  31
  32 /*
  33  * HPET address is set in acpi/boot.c, when an ACPI entry exists
  34  */
  35 unsigned long                           hpet_address;
  36 u8                                      hpet_blockid; /* OS timer block num */
  37 u8                                      hpet_msi_disable;
  38
  39 #ifdef CONFIG_PCI_MSI
  40 static unsigned long                    hpet_num_timers;
  41 #endif
  42 static void __iomem                     *hpet_virt_address;
  43
  44 struct hpet_dev {
  45         struct clock_event_device       evt;
  46         unsigned int                    num;
  47         int                             cpu;
  48         unsigned int                    irq;
  49         unsigned int                    flags;
  50         char                            name[10];
  51 };
  52
  53 inline unsigned int hpet_readl(unsigned int a)
  54 {
  55         return readl(hpet_virt_address + a);
  56 }
  57
  58 static inline void hpet_writel(unsigned int d, unsigned int a)
  59 {
  60         writel(d, hpet_virt_address + a);
  61 }
  62
  63 #ifdef CONFIG_X86_64
  64 #include <asm/pgtable.h>
  65 #endif
  66
  67 static inline void hpet_set_mapping(void)
  68 {
  69         hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
  70 #ifdef CONFIG_X86_64
  71         __set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
  72 #endif
  73 }
  74
  75 static inline void hpet_clear_mapping(void)
  76 {
  77         iounmap(hpet_virt_address);
  78         hpet_virt_address = NULL;
  79 }
  80
  81 /*
  82  * HPET command line enable / disable
  83  */
  84 static int boot_hpet_disable;
  85 int hpet_force_user;
  86 static int hpet_verbose;
  87
  88 static int __init hpet_setup(char *str)
  89 {
  90         if (str) {
  91                 if (!strncmp("disable", str, 7))
  92                         boot_hpet_disable = 1;
  93                 if (!strncmp("force", str, 5))
  94                         hpet_force_user = 1;
  95                 if (!strncmp("verbose", str, 7))
  96                         hpet_verbose = 1;
  97         }
  98         return 1;
  99 }
 100 __setup("hpet=", hpet_setup);
 101
 102 static int __init disable_hpet(char *str)
 103 {
 104         boot_hpet_disable = 1;
 105         return 1;
 106 }
 107 __setup("nohpet", disable_hpet);
 108
 109 static inline int is_hpet_capable(void)
 110 {
 111         return !boot_hpet_disable && hpet_address;
 112 }
 113
 114 /*
 115  * HPET timer interrupt enable / disable
 116  */
 117 static int hpet_legacy_int_enabled;
 118
 119 /**
 120  * is_hpet_enabled - check whether the hpet timer interrupt is enabled
 121  */
 122 int is_hpet_enabled(void)
 123 {
 124         return is_hpet_capable() && hpet_legacy_int_enabled;
 125 }
 126 EXPORT_SYMBOL_GPL(is_hpet_enabled);
 127
 128 static void _hpet_print_config(const char *function, int line)
 129 {
 130         u32 i, timers, l, h;
 131         printk(KERN_INFO "hpet: %s(%d):\n", function, line);
 132         l = hpet_readl(HPET_ID);
 133         h = hpet_readl(HPET_PERIOD);
 134         timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 135         printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
 136         l = hpet_readl(HPET_CFG);
 137         h = hpet_readl(HPET_STATUS);
 138         printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
 139         l = hpet_readl(HPET_COUNTER);
 140         h = hpet_readl(HPET_COUNTER+4);
 141         printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
 142
 143         for (i = 0; i < timers; i++) {
 144                 l = hpet_readl(HPET_Tn_CFG(i));
 145                 h = hpet_readl(HPET_Tn_CFG(i)+4);
 146                 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
 147                        i, l, h);
 148                 l = hpet_readl(HPET_Tn_CMP(i));
 149                 h = hpet_readl(HPET_Tn_CMP(i)+4);
 150                 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
 151                        i, l, h);
 152                 l = hpet_readl(HPET_Tn_ROUTE(i));
 153                 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
 154                 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
 155                        i, l, h);
 156         }
 157 }
 158
 159 #define hpet_print_config()                                     \
 160 do {                                                            \
 161         if (hpet_verbose)                                       \
 162                 _hpet_print_config(__FUNCTION__, __LINE__);     \
 163 } while (0)
 164
 165 /*
 166  * When the hpet driver (/dev/hpet) is enabled, we need to reserve
 167  * timer 0 and timer 1 in case of RTC emulation.
 168  */
 169 #ifdef CONFIG_HPET
 170
 171 static void hpet_reserve_msi_timers(struct hpet_data *hd);
 172
 173 static void hpet_reserve_platform_timers(unsigned int id)
 174 {
 175         struct hpet __iomem *hpet = hpet_virt_address;
 176         struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
 177         unsigned int nrtimers, i;
 178         struct hpet_data hd;
 179
 180         nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
 181
 182         memset(&hd, 0, sizeof(hd));
 183         hd.hd_phys_address      = hpet_address;
 184         hd.hd_address           = hpet;
 185         hd.hd_nirqs             = nrtimers;
 186         hpet_reserve_timer(&hd, 0);
 187
 188 #ifdef CONFIG_HPET_EMULATE_RTC
 189         hpet_reserve_timer(&hd, 1);
 190 #endif
 191
 192         /*
 193          * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
 194          * is wrong for i8259!) not the output IRQ.  Many BIOS writers
 195          * don't bother configuring *any* comparator interrupts.
 196          */
 197         hd.hd_irq[0] = HPET_LEGACY_8254;
 198         hd.hd_irq[1] = HPET_LEGACY_RTC;
 199
 200         for (i = 2; i < nrtimers; timer++, i++) {
 201                 hd.hd_irq[i] = (readl(&timer->hpet_config) &
 202                         Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
 203         }
 204
 205         hpet_reserve_msi_timers(&hd);
 206
 207         hpet_alloc(&hd);
 208
 209 }
 210 #else
 211 static void hpet_reserve_platform_timers(unsigned int id) { }
 212 #endif
 213
 214 /*
 215  * Common hpet info
 216  */
 217 static unsigned long hpet_period;
 218
 219 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 220                           struct clock_event_device *evt);
 221 static int hpet_legacy_next_event(unsigned long delta,
 222                            struct clock_event_device *evt);
 223
 224 /*
 225  * The hpet clock event device
 226  */
 227 static struct clock_event_device hpet_clockevent = {
 228         .name           = "hpet",
 229         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 230         .set_mode       = hpet_legacy_set_mode,
 231         .set_next_event = hpet_legacy_next_event,
 232         .shift          = 32,
 233         .irq            = 0,
 234         .rating         = 50,
 235 };
 236
 237 static void hpet_stop_counter(void)
 238 {
 239         unsigned long cfg = hpet_readl(HPET_CFG);
 240         cfg &= ~HPET_CFG_ENABLE;
 241         hpet_writel(cfg, HPET_CFG);
 242 }
 243
 244 static void hpet_reset_counter(void)
 245 {
 246         hpet_writel(0, HPET_COUNTER);
 247         hpet_writel(0, HPET_COUNTER + 4);
 248 }
 249
 250 static void hpet_start_counter(void)
 251 {
 252         unsigned int cfg = hpet_readl(HPET_CFG);
 253         cfg |= HPET_CFG_ENABLE;
 254         hpet_writel(cfg, HPET_CFG);
 255 }
 256
 257 static void hpet_restart_counter(void)
 258 {
 259         hpet_stop_counter();
 260         hpet_reset_counter();
 261         hpet_start_counter();
 262 }
 263
 264 static void hpet_resume_device(void)
 265 {
 266         force_hpet_resume();
 267 }
 268
 269 static void hpet_resume_counter(struct clocksource *cs)
 270 {
 271         hpet_resume_device();
 272         hpet_restart_counter();
 273 }
 274
 275 static void hpet_enable_legacy_int(void)
 276 {
 277         unsigned int cfg = hpet_readl(HPET_CFG);
 278
 279         cfg |= HPET_CFG_LEGACY;
 280         hpet_writel(cfg, HPET_CFG);
 281         hpet_legacy_int_enabled = 1;
 282 }
 283
 284 static void hpet_legacy_clockevent_register(void)
 285 {
 286         /* Start HPET legacy interrupts */
 287         hpet_enable_legacy_int();
 288
 289         /*
 290          * The mult factor is defined as (include/linux/clockchips.h)
 291          *  mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
 292          * hpet_period is in units of femtoseconds (per cycle), so
 293          *  mult/2^shift = cyc/ns = 10^6/hpet_period
 294          *  mult = (10^6 * 2^shift)/hpet_period
 295          *  mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
 296          */
 297         hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
 298                                       hpet_period, hpet_clockevent.shift);
 299         /* Calculate the min / max delta */
 300         hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
 301                                                            &hpet_clockevent);
 302         /* 5 usec minimum reprogramming delta. */
 303         hpet_clockevent.min_delta_ns = 5000;
 304
 305         /*
 306          * Start hpet with the boot cpu mask and make it
 307          * global after the IO_APIC has been initialized.
 308          */
 309         hpet_clockevent.cpumask = cpumask_of(smp_processor_id());
 310         clockevents_register_device(&hpet_clockevent);
 311         global_clock_event = &hpet_clockevent;
 312         printk(KERN_DEBUG "hpet clockevent registered\n");
 313 }
 314
 315 static int hpet_setup_msi_irq(unsigned int irq);
 316
 317 static void hpet_set_mode(enum clock_event_mode mode,
 318                           struct clock_event_device *evt, int timer)
 319 {
 320         unsigned int cfg, cmp, now;
 321         uint64_t delta;
 322
 323         switch (mode) {
 324         case CLOCK_EVT_MODE_PERIODIC:
 325                 hpet_stop_counter();
 326                 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
 327                 delta >>= evt->shift;
 328                 now = hpet_readl(HPET_COUNTER);
 329                 cmp = now + (unsigned int) delta;
 330                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 331                 /* Make sure we use edge triggered interrupts */
 332                 cfg &= ~HPET_TN_LEVEL;
 333                 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
 334                        HPET_TN_SETVAL | HPET_TN_32BIT;
 335                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 336                 hpet_writel(cmp, HPET_Tn_CMP(timer));
 337                 udelay(1);
 338                 /*
 339                  * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
 340                  * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
 341                  * bit is automatically cleared after the first write.
 342                  * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
 343                  * Publication # 24674)
 344                  */
 345                 hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
 346                 hpet_start_counter();
 347                 hpet_print_config();
 348                 break;
 349
 350         case CLOCK_EVT_MODE_ONESHOT:
 351                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 352                 cfg &= ~HPET_TN_PERIODIC;
 353                 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
 354                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 355                 break;
 356
 357         case CLOCK_EVT_MODE_UNUSED:
 358         case CLOCK_EVT_MODE_SHUTDOWN:
 359                 cfg = hpet_readl(HPET_Tn_CFG(timer));
 360                 cfg &= ~HPET_TN_ENABLE;
 361                 hpet_writel(cfg, HPET_Tn_CFG(timer));
 362                 break;
 363
 364         case CLOCK_EVT_MODE_RESUME:
 365                 if (timer == 0) {
 366                         hpet_enable_legacy_int();
 367                 } else {
 368                         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 369                         hpet_setup_msi_irq(hdev->irq);
 370                         disable_irq(hdev->irq);
 371                         irq_set_affinity(hdev->irq, cpumask_of(hdev->cpu));
 372                         enable_irq(hdev->irq);
 373                 }
 374                 hpet_print_config();
 375                 break;
 376         }
 377 }
 378
 379 static int hpet_next_event(unsigned long delta,
 380                            struct clock_event_device *evt, int timer)
 381 {
 382         u32 cnt;
 383
 384         cnt = hpet_readl(HPET_COUNTER);
 385         cnt += (u32) delta;
 386         hpet_writel(cnt, HPET_Tn_CMP(timer));
 387
 388         /*
 389          * We need to read back the CMP register on certain HPET
 390          * implementations (ATI chipsets) which seem to delay the
 391          * transfer of the compare register into the internal compare
 392          * logic. With small deltas this might actually be too late as
 393          * the counter could already be higher than the compare value
 394          * at that point and we would wait for the next hpet interrupt
 395          * forever. We found out that reading the CMP register back
 396          * forces the transfer so we can rely on the comparison with
 397          * the counter register below. If the read back from the
 398          * compare register does not match the value we programmed
 399          * then we might have a real hardware problem. We can not do
 400          * much about it here, but at least alert the user/admin with
 401          * a prominent warning.
 402          *
 403          * An erratum on some chipsets (ICH9,..), results in
 404          * comparator read immediately following a write returning old
 405          * value. Workaround for this is to read this value second
 406          * time, when first read returns old value.
 407          *
 408          * In fact the write to the comparator register is delayed up
 409          * to two HPET cycles so the workaround we tried to restrict
 410          * the readback to those known to be borked ATI chipsets
 411          * failed miserably. So we give up on optimizations forever
 412          * and penalize all HPET incarnations unconditionally.
 413          */
 414         if (unlikely((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt)) {
 415                 if (hpet_readl(HPET_Tn_CMP(timer)) != cnt)
 416                         printk_once(KERN_WARNING
 417                                 "hpet: compare register read back failed.\n");
 418         }
 419
 420         return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
 421 }
 422
 423 static void hpet_legacy_set_mode(enum clock_event_mode mode,
 424                         struct clock_event_device *evt)
 425 {
 426         hpet_set_mode(mode, evt, 0);
 427 }
 428
 429 static int hpet_legacy_next_event(unsigned long delta,
 430                         struct clock_event_device *evt)
 431 {
 432         return hpet_next_event(delta, evt, 0);
 433 }
 434
 435 /*
 436  * HPET MSI Support
 437  */
 438 #ifdef CONFIG_PCI_MSI
 439
 440 static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
 441 static struct hpet_dev  *hpet_devs;
 442
 443 void hpet_msi_unmask(unsigned int irq)
 444 {
 445         struct hpet_dev *hdev = get_irq_data(irq);
 446         unsigned int cfg;
 447
 448         /* unmask it */
 449         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 450         cfg |= HPET_TN_FSB;
 451         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 452 }
 453
 454 void hpet_msi_mask(unsigned int irq)
 455 {
 456         unsigned int cfg;
 457         struct hpet_dev *hdev = get_irq_data(irq);
 458
 459         /* mask it */
 460         cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
 461         cfg &= ~HPET_TN_FSB;
 462         hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
 463 }
 464
 465 void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
 466 {
 467         struct hpet_dev *hdev = get_irq_data(irq);
 468
 469         hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
 470         hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
 471 }
 472
 473 void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
 474 {
 475         struct hpet_dev *hdev = get_irq_data(irq);
 476
 477         msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
 478         msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
 479         msg->address_hi = 0;
 480 }
 481
 482 static void hpet_msi_set_mode(enum clock_event_mode mode,
 483                                 struct clock_event_device *evt)
 484 {
 485         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 486         hpet_set_mode(mode, evt, hdev->num);
 487 }
 488
 489 static int hpet_msi_next_event(unsigned long delta,
 490                                 struct clock_event_device *evt)
 491 {
 492         struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
 493         return hpet_next_event(delta, evt, hdev->num);
 494 }
 495
 496 static int hpet_setup_msi_irq(unsigned int irq)
 497 {
 498         if (arch_setup_hpet_msi(irq, hpet_blockid)) {
 499                 destroy_irq(irq);
 500                 return -EINVAL;
 501         }
 502         return 0;
 503 }
 504
 505 static int hpet_assign_irq(struct hpet_dev *dev)
 506 {
 507         unsigned int irq;
 508
 509         irq = create_irq();
 510         if (!irq)
 511                 return -EINVAL;
 512
 513         set_irq_data(irq, dev);
 514
 515         if (hpet_setup_msi_irq(irq))
 516                 return -EINVAL;
 517
 518         dev->irq = irq;
 519         return 0;
 520 }
 521
 522 static irqreturn_t hpet_interrupt_handler(int irq, void *data)
 523 {
 524         struct hpet_dev *dev = (struct hpet_dev *)data;
 525         struct clock_event_device *hevt = &dev->evt;
 526
 527         if (!hevt->event_handler) {
 528                 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
 529                                 dev->num);
 530                 return IRQ_HANDLED;
 531         }
 532
 533         hevt->event_handler(hevt);
 534         return IRQ_HANDLED;
 535 }
 536
 537 static int hpet_setup_irq(struct hpet_dev *dev)
 538 {
 539
 540         if (request_irq(dev->irq, hpet_interrupt_handler,
 541                         IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
 542                         dev->name, dev))
 543                 return -1;
 544
 545         disable_irq(dev->irq);
 546         irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
 547         enable_irq(dev->irq);
 548
 549         printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
 550                          dev->name, dev->irq);
 551
 552         return 0;
 553 }
 554
 555 /* This should be called in specific @cpu */
 556 static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
 557 {
 558         struct clock_event_device *evt = &hdev->evt;
 559         uint64_t hpet_freq;
 560
 561         WARN_ON(cpu != smp_processor_id());
 562         if (!(hdev->flags & HPET_DEV_VALID))
 563                 return;
 564
 565         if (hpet_setup_msi_irq(hdev->irq))
 566                 return;
 567
 568         hdev->cpu = cpu;
 569         per_cpu(cpu_hpet_dev, cpu) = hdev;
 570         evt->name = hdev->name;
 571         hpet_setup_irq(hdev);
 572         evt->irq = hdev->irq;
 573
 574         evt->rating = 110;
 575         evt->features = CLOCK_EVT_FEAT_ONESHOT;
 576         if (hdev->flags & HPET_DEV_PERI_CAP)
 577                 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
 578
 579         evt->set_mode = hpet_msi_set_mode;
 580         evt->set_next_event = hpet_msi_next_event;
 581         evt->shift = 32;
 582
 583         /*
 584          * The period is a femto seconds value. We need to calculate the
 585          * scaled math multiplication factor for nanosecond to hpet tick
 586          * conversion.
 587          */
 588         hpet_freq = FSEC_PER_SEC;
 589         do_div(hpet_freq, hpet_period);
 590         evt->mult = div_sc((unsigned long) hpet_freq,
 591                                       NSEC_PER_SEC, evt->shift);
 592         /* Calculate the max delta */
 593         evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
 594         /* 5 usec minimum reprogramming delta. */
 595         evt->min_delta_ns = 5000;
 596
 597         evt->cpumask = cpumask_of(hdev->cpu);
 598         clockevents_register_device(evt);
 599 }
 600
 601 #ifdef CONFIG_HPET
 602 /* Reserve at least one timer for userspace (/dev/hpet) */
 603 #define RESERVE_TIMERS 1
 604 #else
 605 #define RESERVE_TIMERS 0
 606 #endif
 607
 608 static void hpet_msi_capability_lookup(unsigned int start_timer)
 609 {
 610         unsigned int id;
 611         unsigned int num_timers;
 612         unsigned int num_timers_used = 0;
 613         int i;
 614
 615         if (hpet_msi_disable)
 616                 return;
 617
 618         if (boot_cpu_has(X86_FEATURE_ARAT))
 619                 return;
 620         id = hpet_readl(HPET_ID);
 621
 622         num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
 623         num_timers++; /* Value read out starts from 0 */
 624         hpet_print_config();
 625
 626         hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
 627         if (!hpet_devs)
 628                 return;
 629
 630         hpet_num_timers = num_timers;
 631
 632         for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
 633                 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
 634                 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
 635
 636                 /* Only consider HPET timer with MSI support */
 637                 if (!(cfg & HPET_TN_FSB_CAP))
 638                         continue;
 639
 640                 hdev->flags = 0;
 641                 if (cfg & HPET_TN_PERIODIC_CAP)
 642                         hdev->flags |= HPET_DEV_PERI_CAP;
 643                 hdev->num = i;
 644
 645                 sprintf(hdev->name, "hpet%d", i);
 646                 if (hpet_assign_irq(hdev))
 647                         continue;
 648
 649                 hdev->flags |= HPET_DEV_FSB_CAP;
 650                 hdev->flags |= HPET_DEV_VALID;
 651                 num_timers_used++;
 652                 if (num_timers_used == num_possible_cpus())
 653                         break;
 654         }
 655
 656         printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
 657                 num_timers, num_timers_used);
 658 }
 659
 660 #ifdef CONFIG_HPET
 661 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 662 {
 663         int i;
 664
 665         if (!hpet_devs)
 666                 return;
 667
 668         for (i = 0; i < hpet_num_timers; i++) {
 669                 struct hpet_dev *hdev = &hpet_devs[i];
 670
 671                 if (!(hdev->flags & HPET_DEV_VALID))
 672                         continue;
 673
 674                 hd->hd_irq[hdev->num] = hdev->irq;
 675                 hpet_reserve_timer(hd, hdev->num);
 676         }
 677 }
 678 #endif
 679
 680 static struct hpet_dev *hpet_get_unused_timer(void)
 681 {
 682         int i;
 683
 684         if (!hpet_devs)
 685                 return NULL;
 686
 687         for (i = 0; i < hpet_num_timers; i++) {
 688                 struct hpet_dev *hdev = &hpet_devs[i];
 689
 690                 if (!(hdev->flags & HPET_DEV_VALID))
 691                         continue;
 692                 if (test_and_set_bit(HPET_DEV_USED_BIT,
 693                         (unsigned long *)&hdev->flags))
 694                         continue;
 695                 return hdev;
 696         }
 697         return NULL;
 698 }
 699
 700 struct hpet_work_struct {
 701         struct delayed_work work;
 702         struct completion complete;
 703 };
 704
 705 static void hpet_work(struct work_struct *w)
 706 {
 707         struct hpet_dev *hdev;
 708         int cpu = smp_processor_id();
 709         struct hpet_work_struct *hpet_work;
 710
 711         hpet_work = container_of(w, struct hpet_work_struct, work.work);
 712
 713         hdev = hpet_get_unused_timer();
 714         if (hdev)
 715                 init_one_hpet_msi_clockevent(hdev, cpu);
 716
 717         complete(&hpet_work->complete);
 718 }
 719
 720 static int hpet_cpuhp_notify(struct notifier_block *n,
 721                 unsigned long action, void *hcpu)
 722 {
 723         unsigned long cpu = (unsigned long)hcpu;
 724         struct hpet_work_struct work;
 725         struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
 726
 727         switch (action & 0xf) {
 728         case CPU_ONLINE:
 729                 INIT_DELAYED_WORK_ON_STACK(&work.work, hpet_work);
 730                 init_completion(&work.complete);
 731                 /* FIXME: add schedule_work_on() */
 732                 schedule_delayed_work_on(cpu, &work.work, 0);
 733                 wait_for_completion(&work.complete);
 734                 destroy_timer_on_stack(&work.work.timer);
 735                 break;
 736         case CPU_DEAD:
 737                 if (hdev) {
 738                         free_irq(hdev->irq, hdev);
 739                         hdev->flags &= ~HPET_DEV_USED;
 740                         per_cpu(cpu_hpet_dev, cpu) = NULL;
 741                 }
 742                 break;
 743         }
 744         return NOTIFY_OK;
 745 }
 746 #else
 747
 748 static int hpet_setup_msi_irq(unsigned int irq)
 749 {
 750         return 0;
 751 }
 752 static void hpet_msi_capability_lookup(unsigned int start_timer)
 753 {
 754         return;
 755 }
 756
 757 #ifdef CONFIG_HPET
 758 static void hpet_reserve_msi_timers(struct hpet_data *hd)
 759 {
 760         return;
 761 }
 762 #endif
 763
 764 static int hpet_cpuhp_notify(struct notifier_block *n,
 765                 unsigned long action, void *hcpu)
 766 {
 767         return NOTIFY_OK;
 768 }
 769
 770 #endif
 771
 772 /*
 773  * Clock source related code
 774  */
 775 static cycle_t read_hpet(struct clocksource *cs)
 776 {
 777         return (cycle_t)hpet_readl(HPET_COUNTER);
 778 }
 779
 780 #ifdef CONFIG_X86_64
 781 static cycle_t __vsyscall_fn vread_hpet(void)
 782 {
 783         return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
 784 }
 785 #endif
 786
 787 static struct clocksource clocksource_hpet = {
 788         .name           = "hpet",
 789         .rating         = 250,
 790         .read           = read_hpet,
 791         .mask           = HPET_MASK,
 792         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 793         .resume         = hpet_resume_counter,
 794 #ifdef CONFIG_X86_64
 795         .vread          = vread_hpet,
 796 #endif
 797 };
 798
 799 static int hpet_clocksource_register(void)
 800 {
 801         u64 start, now;
 802         u64 hpet_freq;
 803         cycle_t t1;
 804
 805         /* Start the counter */
 806         hpet_restart_counter();
 807
 808         /* Verify whether hpet counter works */
 809         t1 = hpet_readl(HPET_COUNTER);
 810         rdtscll(start);
 811
 812         /*
 813          * We don't know the TSC frequency yet, but waiting for
 814          * 200000 TSC cycles is safe:
 815          * 4 GHz == 50us
 816          * 1 GHz == 200us
 817          */
 818         do {
 819                 rep_nop();
 820                 rdtscll(now);
 821         } while ((now - start) < 200000UL);
 822
 823         if (t1 == hpet_readl(HPET_COUNTER)) {
 824                 printk(KERN_WARNING
 825                        "HPET counter not counting. HPET disabled\n");
 826                 return -ENODEV;
 827         }
 828
 829         /*
 830          * The definition of mult is (include/linux/clocksource.h)
 831          * mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
 832          * so we first need to convert hpet_period to ns/cyc units:
 833          *  mult/2^shift = ns/cyc = hpet_period/10^6
 834          *  mult = (hpet_period * 2^shift)/10^6
 835          *  mult = (hpet_period << shift)/FSEC_PER_NSEC
 836          */
 837
 838         /* Need to convert hpet_period (fsec/cyc) to cyc/sec:
 839          *
 840          * cyc/sec = FSEC_PER_SEC/hpet_period(fsec/cyc)
 841          * cyc/sec = (FSEC_PER_NSEC * NSEC_PER_SEC)/hpet_period
 842          */
 843         hpet_freq = FSEC_PER_SEC;
 844         do_div(hpet_freq, hpet_period);
 845         clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
 846
 847         return 0;
 848 }
 849
 850 /**
 851  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
 852  */
 853 int __init hpet_enable(void)
 854 {
 855         unsigned int id;
 856         int i;
 857
 858         if (!is_hpet_capable())
 859                 return 0;
 860
 861         hpet_set_mapping();
 862
 863         /*
 864          * Read the period and check for a sane value:
 865          */
 866         hpet_period = hpet_readl(HPET_PERIOD);
 867
 868         /*
 869          * AMD SB700 based systems with spread spectrum enabled use a
 870          * SMM based HPET emulation to provide proper frequency
 871          * setting. The SMM code is initialized with the first HPET
 872          * register access and takes some time to complete. During
 873          * this time the config register reads 0xffffffff. We check
 874          * for max. 1000 loops whether the config register reads a non
 875          * 0xffffffff value to make sure that HPET is up and running
 876          * before we go further. A counting loop is safe, as the HPET
 877          * access takes thousands of CPU cycles. On non SB700 based
 878          * machines this check is only done once and has no side
 879          * effects.
 880          */
 881         for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
 882                 if (i == 1000) {
 883                         printk(KERN_WARNING
 884                                "HPET config register value = 0xFFFFFFFF. "
 885                                "Disabling HPET\n");
 886                         goto out_nohpet;
 887                 }
 888         }
 889
 890         if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
 891                 goto out_nohpet;
 892
 893         /*
 894          * Read the HPET ID register to retrieve the IRQ routing
 895          * information and the number of channels
 896          */
 897         id = hpet_readl(HPET_ID);
 898         hpet_print_config();
 899
 900 #ifdef CONFIG_HPET_EMULATE_RTC
 901         /*
 902          * The legacy routing mode needs at least two channels, tick timer
 903          * and the rtc emulation channel.
 904          */
 905         if (!(id & HPET_ID_NUMBER))
 906                 goto out_nohpet;
 907 #endif
 908
 909         if (hpet_clocksource_register())
 910                 goto out_nohpet;
 911
 912         if (id & HPET_ID_LEGSUP) {
 913                 hpet_legacy_clockevent_register();
 914                 return 1;
 915         }
 916         return 0;
 917
 918 out_nohpet:
 919         hpet_clear_mapping();
 920         hpet_address = 0;
 921         return 0;
 922 }
 923
 924 /*
 925  * Needs to be late, as the reserve_timer code calls kalloc !
 926  *
 927  * Not a problem on i386 as hpet_enable is called from late_time_init,
 928  * but on x86_64 it is necessary !
 929  */
 930 static __init int hpet_late_init(void)
 931 {
 932         int cpu;
 933
 934         if (boot_hpet_disable)
 935                 return -ENODEV;
 936
 937         if (!hpet_address) {
 938                 if (!force_hpet_address)
 939                         return -ENODEV;
 940
 941                 hpet_address = force_hpet_address;
 942                 hpet_enable();
 943         }
 944
 945         if (!hpet_virt_address)
 946                 return -ENODEV;
 947
 948         if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
 949                 hpet_msi_capability_lookup(2);
 950         else
 951                 hpet_msi_capability_lookup(0);
 952
 953         hpet_reserve_platform_timers(hpet_readl(HPET_ID));
 954         hpet_print_config();
 955
 956         if (hpet_msi_disable)
 957                 return 0;
 958
 959         if (boot_cpu_has(X86_FEATURE_ARAT))
 960                 return 0;
 961
 962         for_each_online_cpu(cpu) {
 963                 hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
 964         }
 965
 966         /* This notifier should be called after workqueue is ready */
 967         hotcpu_notifier(hpet_cpuhp_notify, -20);
 968
 969         return 0;
 970 }
 971 fs_initcall(hpet_late_init);
 972
 973 void hpet_disable(void)
 974 {
 975         if (is_hpet_capable() && hpet_virt_address) {
 976                 unsigned int cfg = hpet_readl(HPET_CFG);
 977
 978                 if (hpet_legacy_int_enabled) {
 979                         cfg &= ~HPET_CFG_LEGACY;
 980                         hpet_legacy_int_enabled = 0;
 981                 }
 982                 cfg &= ~HPET_CFG_ENABLE;
 983                 hpet_writel(cfg, HPET_CFG);
 984         }
 985 }
 986
 987 #ifdef CONFIG_HPET_EMULATE_RTC
 988
 989 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
 990  * is enabled, we support RTC interrupt functionality in software.
 991  * RTC has 3 kinds of interrupts:
 992  * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
 993  *    is updated
 994  * 2) Alarm Interrupt - generate an interrupt at a specific time of day
 995  * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
 996  *    2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
 997  * (1) and (2) above are implemented using polling at a frequency of
 998  * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
 999  * overhead. (DEFAULT_RTC_INT_FREQ)
1000  * For (3), we use interrupts at 64Hz or user specified periodic
1001  * frequency, whichever is higher.
1002  */
1003 #include <linux/mc146818rtc.h>
1004 #include <linux/rtc.h>
1005 #include <asm/rtc.h>
1006
1007 #define DEFAULT_RTC_INT_FREQ    64
1008 #define DEFAULT_RTC_SHIFT       6
1009 #define RTC_NUM_INTS            1
1010
1011 static unsigned long hpet_rtc_flags;
1012 static int hpet_prev_update_sec;
1013 static struct rtc_time hpet_alarm_time;
1014 static unsigned long hpet_pie_count;
1015 static u32 hpet_t1_cmp;
1016 static u32 hpet_default_delta;
1017 static u32 hpet_pie_delta;
1018 static unsigned long hpet_pie_limit;
1019
1020 static rtc_irq_handler irq_handler;
1021
1022 /*
1023  * Check that the hpet counter c1 is ahead of the c2
1024  */
1025 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1026 {
1027         return (s32)(c2 - c1) < 0;
1028 }
1029
1030 /*
1031  * Registers a IRQ handler.
1032  */
1033 int hpet_register_irq_handler(rtc_irq_handler handler)
1034 {
1035         if (!is_hpet_enabled())
1036                 return -ENODEV;
1037         if (irq_handler)
1038                 return -EBUSY;
1039
1040         irq_handler = handler;
1041
1042         return 0;
1043 }
1044 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1045
1046 /*
1047  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1048  * and does cleanup.
1049  */
1050 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1051 {
1052         if (!is_hpet_enabled())
1053                 return;
1054
1055         irq_handler = NULL;
1056         hpet_rtc_flags = 0;
1057 }
1058 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1059
1060 /*
1061  * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1062  * is not supported by all HPET implementations for timer 1.
1063  *
1064  * hpet_rtc_timer_init() is called when the rtc is initialized.
1065  */
1066 int hpet_rtc_timer_init(void)
1067 {
1068         unsigned int cfg, cnt, delta;
1069         unsigned long flags;
1070
1071         if (!is_hpet_enabled())
1072                 return 0;
1073
1074         if (!hpet_default_delta) {
1075                 uint64_t clc;
1076
1077                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1078                 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1079                 hpet_default_delta = clc;
1080         }
1081
1082         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1083                 delta = hpet_default_delta;
1084         else
1085                 delta = hpet_pie_delta;
1086
1087         local_irq_save(flags);
1088
1089         cnt = delta + hpet_readl(HPET_COUNTER);
1090         hpet_writel(cnt, HPET_T1_CMP);
1091         hpet_t1_cmp = cnt;
1092
1093         cfg = hpet_readl(HPET_T1_CFG);
1094         cfg &= ~HPET_TN_PERIODIC;
1095         cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1096         hpet_writel(cfg, HPET_T1_CFG);
1097
1098         local_irq_restore(flags);
1099
1100         return 1;
1101 }
1102 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1103
1104 /*
1105  * The functions below are called from rtc driver.
1106  * Return 0 if HPET is not being used.
1107  * Otherwise do the necessary changes and return 1.
1108  */
1109 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1110 {
1111         if (!is_hpet_enabled())
1112                 return 0;
1113
1114         hpet_rtc_flags &= ~bit_mask;
1115         return 1;
1116 }
1117 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1118
1119 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1120 {
1121         unsigned long oldbits = hpet_rtc_flags;
1122
1123         if (!is_hpet_enabled())
1124                 return 0;
1125
1126         hpet_rtc_flags |= bit_mask;
1127
1128         if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1129                 hpet_prev_update_sec = -1;
1130
1131         if (!oldbits)
1132                 hpet_rtc_timer_init();
1133
1134         return 1;
1135 }
1136 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1137
1138 int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1139                         unsigned char sec)
1140 {
1141         if (!is_hpet_enabled())
1142                 return 0;
1143
1144         hpet_alarm_time.tm_hour = hrs;
1145         hpet_alarm_time.tm_min = min;
1146         hpet_alarm_time.tm_sec = sec;
1147
1148         return 1;
1149 }
1150 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1151
1152 int hpet_set_periodic_freq(unsigned long freq)
1153 {
1154         uint64_t clc;
1155
1156         if (!is_hpet_enabled())
1157                 return 0;
1158
1159         if (freq <= DEFAULT_RTC_INT_FREQ)
1160                 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1161         else {
1162                 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1163                 do_div(clc, freq);
1164                 clc >>= hpet_clockevent.shift;
1165                 hpet_pie_delta = clc;
1166                 hpet_pie_limit = 0;
1167         }
1168         return 1;
1169 }
1170 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1171
1172 int hpet_rtc_dropped_irq(void)
1173 {
1174         return is_hpet_enabled();
1175 }
1176 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1177
1178 static void hpet_rtc_timer_reinit(void)
1179 {
1180         unsigned int cfg, delta;
1181         int lost_ints = -1;
1182
1183         if (unlikely(!hpet_rtc_flags)) {
1184                 cfg = hpet_readl(HPET_T1_CFG);
1185                 cfg &= ~HPET_TN_ENABLE;
1186                 hpet_writel(cfg, HPET_T1_CFG);
1187                 return;
1188         }
1189
1190         if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1191                 delta = hpet_default_delta;
1192         else
1193                 delta = hpet_pie_delta;
1194
1195         /*
1196          * Increment the comparator value until we are ahead of the
1197          * current count.
1198          */
1199         do {
1200                 hpet_t1_cmp += delta;
1201                 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1202                 lost_ints++;
1203         } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1204
1205         if (lost_ints) {
1206                 if (hpet_rtc_flags & RTC_PIE)
1207                         hpet_pie_count += lost_ints;
1208                 if (printk_ratelimit())
1209                         printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1210                                 lost_ints);
1211         }
1212 }
1213
1214 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1215 {
1216         struct rtc_time curr_time;
1217         unsigned long rtc_int_flag = 0;
1218
1219         hpet_rtc_timer_reinit();
1220         memset(&curr_time, 0, sizeof(struct rtc_time));
1221
1222         if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1223                 get_rtc_time(&curr_time);
1224
1225         if (hpet_rtc_flags & RTC_UIE &&
1226             curr_time.tm_sec != hpet_prev_update_sec) {
1227                 if (hpet_prev_update_sec >= 0)
1228                         rtc_int_flag = RTC_UF;
1229                 hpet_prev_update_sec = curr_time.tm_sec;
1230         }
1231
1232         if (hpet_rtc_flags & RTC_PIE &&
1233             ++hpet_pie_count >= hpet_pie_limit) {
1234                 rtc_int_flag |= RTC_PF;
1235                 hpet_pie_count = 0;
1236         }
1237
1238         if (hpet_rtc_flags & RTC_AIE &&
1239             (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1240             (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1241             (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1242                         rtc_int_flag |= RTC_AF;
1243
1244         if (rtc_int_flag) {
1245                 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1246                 if (irq_handler)
1247                         irq_handler(rtc_int_flag, dev_id);
1248         }
1249         return IRQ_HANDLED;
1250 }
1251 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1252 #endif