git://bbs.cooldavid.org / net-next-2.6.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $ |
| 2 | * tg3.h: Definitions for Broadcom Tigon3 ethernet driver. | |
| 3 | * | |
| 4 | * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) | |
| 5 | * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com) | |
| 6 | * Copyright (C) 2004 Sun Microsystems Inc. | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef _T3_H | |
| 10 | #define _T3_H | |
| 11 | ||
| 12 | #define TG3_64BIT_REG_HIGH 0x00UL | |
| 13 | #define TG3_64BIT_REG_LOW 0x04UL | |
| 14 | ||
| 15 | /* Descriptor block info. */ | |
| 16 | #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */ | |
| 17 | #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */ | |
| 18 | #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */ | |
| 19 | #define BDINFO_FLAGS_DISABLED 0x00000002 | |
| 20 | #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000 | |
| 21 | #define BDINFO_FLAGS_MAXLEN_SHIFT 16 | |
| 22 | #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */ | |
| 23 | #define TG3_BDINFO_SIZE 0x10UL | |
| 24 | ||
| 25 | #define RX_COPY_THRESHOLD 256 | |
| 26 | ||
| b5d3772c MC |
27 | #define TG3_RX_INTERNAL_RING_SZ_5906 32 |
| 28 | ||
| 1da177e4 LT |
29 | #define RX_STD_MAX_SIZE 1536 |
| 30 | #define RX_STD_MAX_SIZE_5705 512 | |
| 31 | #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */ | |
| 32 | ||
| 33 | /* First 256 bytes are a mirror of PCI config space. */ | |
| 34 | #define TG3PCI_VENDOR 0x00000000 | |
| 35 | #define TG3PCI_VENDOR_BROADCOM 0x14e4 | |
| 36 | #define TG3PCI_DEVICE 0x00000002 | |
| 37 | #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */ | |
| 38 | #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */ | |
| 39 | #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */ | |
| 40 | #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */ | |
| c88e668b MC |
41 | #define TG3PCI_DEVICE_TIGON3_5761S 0x1688 |
| 42 | #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689 | |
| 321d32a0 MC |
43 | #define TG3PCI_DEVICE_TIGON3_57780 0x1692 |
| 44 | #define TG3PCI_DEVICE_TIGON3_57760 0x1690 | |
| 45 | #define TG3PCI_DEVICE_TIGON3_57790 0x1694 | |
| 46 | #define TG3PCI_DEVICE_TIGON3_57720 0x168c | |
| aa10f27d | 47 | /* 0x04 --> 0x64 unused */ |
| 1da177e4 LT |
48 | #define TG3PCI_MSI_DATA 0x00000064 |
| 49 | /* 0x66 --> 0x68 unused */ | |
| 50 | #define TG3PCI_MISC_HOST_CTRL 0x00000068 | |
| 51 | #define MISC_HOST_CTRL_CLEAR_INT 0x00000001 | |
| 52 | #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002 | |
| 53 | #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004 | |
| 54 | #define MISC_HOST_CTRL_WORD_SWAP 0x00000008 | |
| 55 | #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010 | |
| 56 | #define MISC_HOST_CTRL_CLKREG_RW 0x00000020 | |
| 57 | #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040 | |
| 58 | #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080 | |
| 59 | #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 | |
| 60 | #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200 | |
| 61 | #define MISC_HOST_CTRL_CHIPREV 0xffff0000 | |
| 62 | #define MISC_HOST_CTRL_CHIPREV_SHIFT 16 | |
| 63 | #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \ | |
| 64 | (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \ | |
| 65 | MISC_HOST_CTRL_CHIPREV_SHIFT) | |
| 66 | #define CHIPREV_ID_5700_A0 0x7000 | |
| 67 | #define CHIPREV_ID_5700_A1 0x7001 | |
| 68 | #define CHIPREV_ID_5700_B0 0x7100 | |
| 69 | #define CHIPREV_ID_5700_B1 0x7101 | |
| 70 | #define CHIPREV_ID_5700_B3 0x7102 | |
| 71 | #define CHIPREV_ID_5700_ALTIMA 0x7104 | |
| 72 | #define CHIPREV_ID_5700_C0 0x7200 | |
| 73 | #define CHIPREV_ID_5701_A0 0x0000 | |
| 74 | #define CHIPREV_ID_5701_B0 0x0100 | |
| 75 | #define CHIPREV_ID_5701_B2 0x0102 | |
| 76 | #define CHIPREV_ID_5701_B5 0x0105 | |
| 77 | #define CHIPREV_ID_5703_A0 0x1000 | |
| 78 | #define CHIPREV_ID_5703_A1 0x1001 | |
| 79 | #define CHIPREV_ID_5703_A2 0x1002 | |
| 80 | #define CHIPREV_ID_5703_A3 0x1003 | |
| 81 | #define CHIPREV_ID_5704_A0 0x2000 | |
| 82 | #define CHIPREV_ID_5704_A1 0x2001 | |
| 83 | #define CHIPREV_ID_5704_A2 0x2002 | |
| 84 | #define CHIPREV_ID_5704_A3 0x2003 | |
| 85 | #define CHIPREV_ID_5705_A0 0x3000 | |
| 86 | #define CHIPREV_ID_5705_A1 0x3001 | |
| 87 | #define CHIPREV_ID_5705_A2 0x3002 | |
| 88 | #define CHIPREV_ID_5705_A3 0x3003 | |
| 89 | #define CHIPREV_ID_5750_A0 0x4000 | |
| 90 | #define CHIPREV_ID_5750_A1 0x4001 | |
| 91 | #define CHIPREV_ID_5750_A3 0x4003 | |
| 52c0fd83 | 92 | #define CHIPREV_ID_5750_C2 0x4202 |
| ff645bec MC |
93 | #define CHIPREV_ID_5752_A0_HW 0x5000 |
| 94 | #define CHIPREV_ID_5752_A0 0x6000 | |
| 053d7800 | 95 | #define CHIPREV_ID_5752_A1 0x6001 |
| 7544b097 | 96 | #define CHIPREV_ID_5714_A2 0x9002 |
| b5d3772c | 97 | #define CHIPREV_ID_5906_A1 0xc001 |
| 9cf74ebb MC |
98 | #define CHIPREV_ID_57780_A0 0x57780000 |
| 99 | #define CHIPREV_ID_57780_A1 0x57780001 | |
| 1da177e4 LT |
100 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
| 101 | #define ASIC_REV_5700 0x07 | |
| 102 | #define ASIC_REV_5701 0x00 | |
| 103 | #define ASIC_REV_5703 0x01 | |
| 104 | #define ASIC_REV_5704 0x02 | |
| 105 | #define ASIC_REV_5705 0x03 | |
| 106 | #define ASIC_REV_5750 0x04 | |
| ff645bec | 107 | #define ASIC_REV_5752 0x06 |
| 4cf78e4f | 108 | #define ASIC_REV_5780 0x08 |
| a4e2b347 | 109 | #define ASIC_REV_5714 0x09 |
| af36e6b6 | 110 | #define ASIC_REV_5755 0x0a |
| d9ab5ad1 | 111 | #define ASIC_REV_5787 0x0b |
| b5d3772c | 112 | #define ASIC_REV_5906 0x0c |
| 795d01c5 | 113 | #define ASIC_REV_USE_PROD_ID_REG 0x0f |
| d30cdd28 | 114 | #define ASIC_REV_5784 0x5784 |
| 6b91fa02 | 115 | #define ASIC_REV_5761 0x5761 |
| 57e6983c | 116 | #define ASIC_REV_5785 0x5785 |
| 321d32a0 | 117 | #define ASIC_REV_57780 0x57780 |
| 1da177e4 LT |
118 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) |
| 119 | #define CHIPREV_5700_AX 0x70 | |
| 120 | #define CHIPREV_5700_BX 0x71 | |
| 121 | #define CHIPREV_5700_CX 0x72 | |
| 122 | #define CHIPREV_5701_AX 0x00 | |
| 123 | #define CHIPREV_5703_AX 0x10 | |
| 124 | #define CHIPREV_5704_AX 0x20 | |
| 125 | #define CHIPREV_5704_BX 0x21 | |
| 126 | #define CHIPREV_5750_AX 0x40 | |
| 127 | #define CHIPREV_5750_BX 0x41 | |
| b2a5c19c MC |
128 | #define CHIPREV_5784_AX 0x57840 |
| 129 | #define CHIPREV_5761_AX 0x57610 | |
| 1da177e4 LT |
130 | #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff) |
| 131 | #define METAL_REV_A0 0x00 | |
| 132 | #define METAL_REV_A1 0x01 | |
| 133 | #define METAL_REV_B0 0x00 | |
| 134 | #define METAL_REV_B1 0x01 | |
| 135 | #define METAL_REV_B2 0x02 | |
| 136 | #define TG3PCI_DMA_RW_CTRL 0x0000006c | |
| 137 | #define DMA_RWCTRL_MIN_DMA 0x000000ff | |
| 138 | #define DMA_RWCTRL_MIN_DMA_SHIFT 0 | |
| 139 | #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700 | |
| 140 | #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 | |
| 141 | #define DMA_RWCTRL_READ_BNDRY_16 0x00000100 | |
| 142 | #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100 | |
| 143 | #define DMA_RWCTRL_READ_BNDRY_32 0x00000200 | |
| 144 | #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200 | |
| 145 | #define DMA_RWCTRL_READ_BNDRY_64 0x00000300 | |
| 146 | #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300 | |
| 147 | #define DMA_RWCTRL_READ_BNDRY_128 0x00000400 | |
| 148 | #define DMA_RWCTRL_READ_BNDRY_256 0x00000500 | |
| 149 | #define DMA_RWCTRL_READ_BNDRY_512 0x00000600 | |
| 150 | #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700 | |
| 151 | #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 | |
| 152 | #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 | |
| 153 | #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 | |
| 154 | #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800 | |
| 155 | #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 | |
| 156 | #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000 | |
| 157 | #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 | |
| 158 | #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800 | |
| 159 | #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 | |
| 160 | #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 | |
| 161 | #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 | |
| 162 | #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 | |
| 163 | #define DMA_RWCTRL_ONE_DMA 0x00004000 | |
| 164 | #define DMA_RWCTRL_READ_WATER 0x00070000 | |
| 165 | #define DMA_RWCTRL_READ_WATER_SHIFT 16 | |
| 166 | #define DMA_RWCTRL_WRITE_WATER 0x00380000 | |
| 167 | #define DMA_RWCTRL_WRITE_WATER_SHIFT 19 | |
| 168 | #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 | |
| 169 | #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000 | |
| 170 | #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000 | |
| 171 | #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24 | |
| 172 | #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 | |
| 173 | #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 | |
| 174 | #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000 | |
| 175 | #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000 | |
| 176 | #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000 | |
| 177 | #define TG3PCI_PCISTATE 0x00000070 | |
| 178 | #define PCISTATE_FORCE_RESET 0x00000001 | |
| 179 | #define PCISTATE_INT_NOT_ACTIVE 0x00000002 | |
| 180 | #define PCISTATE_CONV_PCI_MODE 0x00000004 | |
| 181 | #define PCISTATE_BUS_SPEED_HIGH 0x00000008 | |
| 182 | #define PCISTATE_BUS_32BIT 0x00000010 | |
| 183 | #define PCISTATE_ROM_ENABLE 0x00000020 | |
| 184 | #define PCISTATE_ROM_RETRY_ENABLE 0x00000040 | |
| 185 | #define PCISTATE_FLAT_VIEW 0x00000100 | |
| 186 | #define PCISTATE_RETRY_SAME_DMA 0x00002000 | |
| 0d3031d9 MC |
187 | #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 |
| 188 | #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 | |
| 1da177e4 LT |
189 | #define TG3PCI_CLOCK_CTRL 0x00000074 |
| 190 | #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200 | |
| 191 | #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400 | |
| 192 | #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800 | |
| 193 | #define CLOCK_CTRL_ALTCLK 0x00001000 | |
| 194 | #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 | |
| 195 | #define CLOCK_CTRL_44MHZ_CORE 0x00040000 | |
| 196 | #define CLOCK_CTRL_625_CORE 0x00100000 | |
| 197 | #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000 | |
| 198 | #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000 | |
| 199 | #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 | |
| 200 | #define TG3PCI_REG_BASE_ADDR 0x00000078 | |
| 201 | #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c | |
| 202 | #define TG3PCI_REG_DATA 0x00000080 | |
| 203 | #define TG3PCI_MEM_WIN_DATA 0x00000084 | |
| 204 | #define TG3PCI_MODE_CTRL 0x00000088 | |
| 205 | #define TG3PCI_MISC_CFG 0x0000008c | |
| 206 | #define TG3PCI_MISC_LOCAL_CTRL 0x00000090 | |
| 207 | /* 0x94 --> 0x98 unused */ | |
| 208 | #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */ | |
| 209 | #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */ | |
| 210 | #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */ | |
| 211 | /* 0xb0 --> 0xb8 unused */ | |
| 212 | #define TG3PCI_DUAL_MAC_CTRL 0x000000b8 | |
| 213 | #define DUAL_MAC_CTRL_CH_MASK 0x00000003 | |
| 214 | #define DUAL_MAC_CTRL_ID 0x00000004 | |
| 795d01c5 MC |
215 | #define TG3PCI_PRODID_ASICREV 0x000000bc |
| 216 | #define PROD_ID_ASIC_REV_MASK 0x0fffffff | |
| 521e6b90 | 217 | /* 0xc0 --> 0x110 unused */ |
| 1da177e4 | 218 | |
| 521e6b90 MC |
219 | #define TG3_CORR_ERR_STAT 0x00000110 |
| 220 | #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff | |
| 221 | /* 0x114 --> 0x200 unused */ | |
| 1da177e4 LT |
222 | |
| 223 | /* Mailbox registers */ | |
| 224 | #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */ | |
| 225 | #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */ | |
| 226 | #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */ | |
| 227 | #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */ | |
| 228 | #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */ | |
| 229 | #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */ | |
| 230 | #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */ | |
| 231 | #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */ | |
| 232 | #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */ | |
| 233 | #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */ | |
| 234 | #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */ | |
| 235 | #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */ | |
| 236 | #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */ | |
| 237 | #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */ | |
| 238 | #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */ | |
| 239 | #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */ | |
| 240 | #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */ | |
| 241 | #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */ | |
| 242 | #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */ | |
| 243 | #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */ | |
| 244 | #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */ | |
| 245 | #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */ | |
| 246 | #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */ | |
| 247 | #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */ | |
| 248 | #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */ | |
| 249 | #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */ | |
| 250 | #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */ | |
| 251 | #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */ | |
| 252 | #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */ | |
| 253 | #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */ | |
| 254 | #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */ | |
| 255 | #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */ | |
| 256 | #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */ | |
| 257 | #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */ | |
| 258 | #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */ | |
| 259 | #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */ | |
| 260 | #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */ | |
| 261 | #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */ | |
| 262 | #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */ | |
| 263 | #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */ | |
| 264 | #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */ | |
| 265 | #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */ | |
| 266 | #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */ | |
| 267 | #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */ | |
| 268 | #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */ | |
| 269 | #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */ | |
| 270 | #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */ | |
| 271 | #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */ | |
| 272 | #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */ | |
| 273 | #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */ | |
| 274 | #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */ | |
| 275 | #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */ | |
| 276 | #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */ | |
| 277 | #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */ | |
| 278 | #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */ | |
| 279 | #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */ | |
| 280 | #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */ | |
| 281 | #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */ | |
| 282 | #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */ | |
| 283 | #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */ | |
| 284 | #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */ | |
| 285 | #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */ | |
| 286 | #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */ | |
| 287 | #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */ | |
| 288 | ||
| 289 | /* MAC control registers */ | |
| 290 | #define MAC_MODE 0x00000400 | |
| 291 | #define MAC_MODE_RESET 0x00000001 | |
| 292 | #define MAC_MODE_HALF_DUPLEX 0x00000002 | |
| 293 | #define MAC_MODE_PORT_MODE_MASK 0x0000000c | |
| 294 | #define MAC_MODE_PORT_MODE_TBI 0x0000000c | |
| 295 | #define MAC_MODE_PORT_MODE_GMII 0x00000008 | |
| 296 | #define MAC_MODE_PORT_MODE_MII 0x00000004 | |
| 297 | #define MAC_MODE_PORT_MODE_NONE 0x00000000 | |
| 298 | #define MAC_MODE_PORT_INT_LPBACK 0x00000010 | |
| 299 | #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080 | |
| 300 | #define MAC_MODE_TX_BURSTING 0x00000100 | |
| 301 | #define MAC_MODE_MAX_DEFER 0x00000200 | |
| 302 | #define MAC_MODE_LINK_POLARITY 0x00000400 | |
| 303 | #define MAC_MODE_RXSTAT_ENABLE 0x00000800 | |
| 304 | #define MAC_MODE_RXSTAT_CLEAR 0x00001000 | |
| 305 | #define MAC_MODE_RXSTAT_FLUSH 0x00002000 | |
| 306 | #define MAC_MODE_TXSTAT_ENABLE 0x00004000 | |
| 307 | #define MAC_MODE_TXSTAT_CLEAR 0x00008000 | |
| 308 | #define MAC_MODE_TXSTAT_FLUSH 0x00010000 | |
| 309 | #define MAC_MODE_SEND_CONFIGS 0x00020000 | |
| 310 | #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000 | |
| 311 | #define MAC_MODE_ACPI_ENABLE 0x00080000 | |
| 312 | #define MAC_MODE_MIP_ENABLE 0x00100000 | |
| 313 | #define MAC_MODE_TDE_ENABLE 0x00200000 | |
| 314 | #define MAC_MODE_RDE_ENABLE 0x00400000 | |
| 315 | #define MAC_MODE_FHDE_ENABLE 0x00800000 | |
| b2aee154 | 316 | #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000 |
| 3bda1258 MC |
317 | #define MAC_MODE_APE_RX_EN 0x08000000 |
| 318 | #define MAC_MODE_APE_TX_EN 0x10000000 | |
| 1da177e4 LT |
319 | #define MAC_STATUS 0x00000404 |
| 320 | #define MAC_STATUS_PCS_SYNCED 0x00000001 | |
| 321 | #define MAC_STATUS_SIGNAL_DET 0x00000002 | |
| 322 | #define MAC_STATUS_RCVD_CFG 0x00000004 | |
| 323 | #define MAC_STATUS_CFG_CHANGED 0x00000008 | |
| 324 | #define MAC_STATUS_SYNC_CHANGED 0x00000010 | |
| 325 | #define MAC_STATUS_PORT_DEC_ERR 0x00000400 | |
| 326 | #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000 | |
| 327 | #define MAC_STATUS_MI_COMPLETION 0x00400000 | |
| 328 | #define MAC_STATUS_MI_INTERRUPT 0x00800000 | |
| 329 | #define MAC_STATUS_AP_ERROR 0x01000000 | |
| 330 | #define MAC_STATUS_ODI_ERROR 0x02000000 | |
| 331 | #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000 | |
| 332 | #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000 | |
| 333 | #define MAC_EVENT 0x00000408 | |
| 334 | #define MAC_EVENT_PORT_DECODE_ERR 0x00000400 | |
| 335 | #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000 | |
| 336 | #define MAC_EVENT_MI_COMPLETION 0x00400000 | |
| 337 | #define MAC_EVENT_MI_INTERRUPT 0x00800000 | |
| 338 | #define MAC_EVENT_AP_ERROR 0x01000000 | |
| 339 | #define MAC_EVENT_ODI_ERROR 0x02000000 | |
| 340 | #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000 | |
| 341 | #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000 | |
| 342 | #define MAC_LED_CTRL 0x0000040c | |
| 343 | #define LED_CTRL_LNKLED_OVERRIDE 0x00000001 | |
| 344 | #define LED_CTRL_1000MBPS_ON 0x00000002 | |
| 345 | #define LED_CTRL_100MBPS_ON 0x00000004 | |
| 346 | #define LED_CTRL_10MBPS_ON 0x00000008 | |
| 347 | #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010 | |
| 348 | #define LED_CTRL_TRAFFIC_BLINK 0x00000020 | |
| 349 | #define LED_CTRL_TRAFFIC_LED 0x00000040 | |
| 350 | #define LED_CTRL_1000MBPS_STATUS 0x00000080 | |
| 351 | #define LED_CTRL_100MBPS_STATUS 0x00000100 | |
| 352 | #define LED_CTRL_10MBPS_STATUS 0x00000200 | |
| 353 | #define LED_CTRL_TRAFFIC_STATUS 0x00000400 | |
| 354 | #define LED_CTRL_MODE_MAC 0x00000000 | |
| 355 | #define LED_CTRL_MODE_PHY_1 0x00000800 | |
| 356 | #define LED_CTRL_MODE_PHY_2 0x00001000 | |
| 357 | #define LED_CTRL_MODE_SHASTA_MAC 0x00002000 | |
| 358 | #define LED_CTRL_MODE_SHARED 0x00004000 | |
| 359 | #define LED_CTRL_MODE_COMBO 0x00008000 | |
| 360 | #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000 | |
| 361 | #define LED_CTRL_BLINK_RATE_SHIFT 19 | |
| 362 | #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000 | |
| 363 | #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 | |
| 364 | #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */ | |
| 365 | #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */ | |
| 366 | #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */ | |
| 367 | #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */ | |
| 368 | #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */ | |
| 369 | #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */ | |
| 370 | #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */ | |
| 371 | #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */ | |
| 372 | #define MAC_ACPI_MBUF_PTR 0x00000430 | |
| 373 | #define MAC_ACPI_LEN_OFFSET 0x00000434 | |
| 374 | #define ACPI_LENOFF_LEN_MASK 0x0000ffff | |
| 375 | #define ACPI_LENOFF_LEN_SHIFT 0 | |
| 376 | #define ACPI_LENOFF_OFF_MASK 0x0fff0000 | |
| 377 | #define ACPI_LENOFF_OFF_SHIFT 16 | |
| 378 | #define MAC_TX_BACKOFF_SEED 0x00000438 | |
| 379 | #define TX_BACKOFF_SEED_MASK 0x000003ff | |
| 380 | #define MAC_RX_MTU_SIZE 0x0000043c | |
| 381 | #define RX_MTU_SIZE_MASK 0x0000ffff | |
| 382 | #define MAC_PCS_TEST 0x00000440 | |
| 383 | #define PCS_TEST_PATTERN_MASK 0x000fffff | |
| 384 | #define PCS_TEST_PATTERN_SHIFT 0 | |
| 385 | #define PCS_TEST_ENABLE 0x00100000 | |
| 386 | #define MAC_TX_AUTO_NEG 0x00000444 | |
| 387 | #define TX_AUTO_NEG_MASK 0x0000ffff | |
| 388 | #define TX_AUTO_NEG_SHIFT 0 | |
| 389 | #define MAC_RX_AUTO_NEG 0x00000448 | |
| 390 | #define RX_AUTO_NEG_MASK 0x0000ffff | |
| 391 | #define RX_AUTO_NEG_SHIFT 0 | |
| 392 | #define MAC_MI_COM 0x0000044c | |
| 393 | #define MI_COM_CMD_MASK 0x0c000000 | |
| 394 | #define MI_COM_CMD_WRITE 0x04000000 | |
| 395 | #define MI_COM_CMD_READ 0x08000000 | |
| 396 | #define MI_COM_READ_FAILED 0x10000000 | |
| 397 | #define MI_COM_START 0x20000000 | |
| 398 | #define MI_COM_BUSY 0x20000000 | |
| 399 | #define MI_COM_PHY_ADDR_MASK 0x03e00000 | |
| 400 | #define MI_COM_PHY_ADDR_SHIFT 21 | |
| 401 | #define MI_COM_REG_ADDR_MASK 0x001f0000 | |
| 402 | #define MI_COM_REG_ADDR_SHIFT 16 | |
| 403 | #define MI_COM_DATA_MASK 0x0000ffff | |
| 404 | #define MAC_MI_STAT 0x00000450 | |
| 405 | #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 | |
| fcb389df | 406 | #define MAC_MI_STAT_10MBPS_MODE 0x00000002 |
| 1da177e4 LT |
407 | #define MAC_MI_MODE 0x00000454 |
| 408 | #define MAC_MI_MODE_CLK_10MHZ 0x00000001 | |
| 409 | #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002 | |
| 410 | #define MAC_MI_MODE_AUTO_POLL 0x00000010 | |
| 8ef21428 | 411 | #define MAC_MI_MODE_500KHZ_CONST 0x00008000 |
| 1da177e4 LT |
412 | #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */ |
| 413 | #define MAC_AUTO_POLL_STATUS 0x00000458 | |
| 414 | #define MAC_AUTO_POLL_ERROR 0x00000001 | |
| 415 | #define MAC_TX_MODE 0x0000045c | |
| 416 | #define TX_MODE_RESET 0x00000001 | |
| 417 | #define TX_MODE_ENABLE 0x00000002 | |
| 418 | #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010 | |
| 419 | #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020 | |
| 420 | #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040 | |
| 421 | #define MAC_TX_STATUS 0x00000460 | |
| 422 | #define TX_STATUS_XOFFED 0x00000001 | |
| 423 | #define TX_STATUS_SENT_XOFF 0x00000002 | |
| 424 | #define TX_STATUS_SENT_XON 0x00000004 | |
| 425 | #define TX_STATUS_LINK_UP 0x00000008 | |
| 426 | #define TX_STATUS_ODI_UNDERRUN 0x00000010 | |
| 427 | #define TX_STATUS_ODI_OVERRUN 0x00000020 | |
| 428 | #define MAC_TX_LENGTHS 0x00000464 | |
| 429 | #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff | |
| 430 | #define TX_LENGTHS_SLOT_TIME_SHIFT 0 | |
| 431 | #define TX_LENGTHS_IPG_MASK 0x00000f00 | |
| 432 | #define TX_LENGTHS_IPG_SHIFT 8 | |
| 433 | #define TX_LENGTHS_IPG_CRS_MASK 0x00003000 | |
| 434 | #define TX_LENGTHS_IPG_CRS_SHIFT 12 | |
| 435 | #define MAC_RX_MODE 0x00000468 | |
| 436 | #define RX_MODE_RESET 0x00000001 | |
| 437 | #define RX_MODE_ENABLE 0x00000002 | |
| 438 | #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004 | |
| 439 | #define RX_MODE_KEEP_MAC_CTRL 0x00000008 | |
| 440 | #define RX_MODE_KEEP_PAUSE 0x00000010 | |
| 441 | #define RX_MODE_ACCEPT_OVERSIZED 0x00000020 | |
| 442 | #define RX_MODE_ACCEPT_RUNTS 0x00000040 | |
| 443 | #define RX_MODE_LEN_CHECK 0x00000080 | |
| 444 | #define RX_MODE_PROMISC 0x00000100 | |
| 445 | #define RX_MODE_NO_CRC_CHECK 0x00000200 | |
| 446 | #define RX_MODE_KEEP_VLAN_TAG 0x00000400 | |
| af36e6b6 | 447 | #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000 |
| 1da177e4 LT |
448 | #define MAC_RX_STATUS 0x0000046c |
| 449 | #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001 | |
| 450 | #define RX_STATUS_XOFF_RCVD 0x00000002 | |
| 451 | #define RX_STATUS_XON_RCVD 0x00000004 | |
| 452 | #define MAC_HASH_REG_0 0x00000470 | |
| 453 | #define MAC_HASH_REG_1 0x00000474 | |
| 454 | #define MAC_HASH_REG_2 0x00000478 | |
| 455 | #define MAC_HASH_REG_3 0x0000047c | |
| 456 | #define MAC_RCV_RULE_0 0x00000480 | |
| 457 | #define MAC_RCV_VALUE_0 0x00000484 | |
| 458 | #define MAC_RCV_RULE_1 0x00000488 | |
| 459 | #define MAC_RCV_VALUE_1 0x0000048c | |
| 460 | #define MAC_RCV_RULE_2 0x00000490 | |
| 461 | #define MAC_RCV_VALUE_2 0x00000494 | |
| 462 | #define MAC_RCV_RULE_3 0x00000498 | |
| 463 | #define MAC_RCV_VALUE_3 0x0000049c | |
| 464 | #define MAC_RCV_RULE_4 0x000004a0 | |
| 465 | #define MAC_RCV_VALUE_4 0x000004a4 | |
| 466 | #define MAC_RCV_RULE_5 0x000004a8 | |
| 467 | #define MAC_RCV_VALUE_5 0x000004ac | |
| 468 | #define MAC_RCV_RULE_6 0x000004b0 | |
| 469 | #define MAC_RCV_VALUE_6 0x000004b4 | |
| 470 | #define MAC_RCV_RULE_7 0x000004b8 | |
| 471 | #define MAC_RCV_VALUE_7 0x000004bc | |
| 472 | #define MAC_RCV_RULE_8 0x000004c0 | |
| 473 | #define MAC_RCV_VALUE_8 0x000004c4 | |
| 474 | #define MAC_RCV_RULE_9 0x000004c8 | |
| 475 | #define MAC_RCV_VALUE_9 0x000004cc | |
| 476 | #define MAC_RCV_RULE_10 0x000004d0 | |
| 477 | #define MAC_RCV_VALUE_10 0x000004d4 | |
| 478 | #define MAC_RCV_RULE_11 0x000004d8 | |
| 479 | #define MAC_RCV_VALUE_11 0x000004dc | |
| 480 | #define MAC_RCV_RULE_12 0x000004e0 | |
| 481 | #define MAC_RCV_VALUE_12 0x000004e4 | |
| 482 | #define MAC_RCV_RULE_13 0x000004e8 | |
| 483 | #define MAC_RCV_VALUE_13 0x000004ec | |
| 484 | #define MAC_RCV_RULE_14 0x000004f0 | |
| 485 | #define MAC_RCV_VALUE_14 0x000004f4 | |
| 486 | #define MAC_RCV_RULE_15 0x000004f8 | |
| 487 | #define MAC_RCV_VALUE_15 0x000004fc | |
| 488 | #define RCV_RULE_DISABLE_MASK 0x7fffffff | |
| 489 | #define MAC_RCV_RULE_CFG 0x00000500 | |
| 490 | #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008 | |
| 491 | #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 | |
| 492 | /* 0x508 --> 0x520 unused */ | |
| 493 | #define MAC_HASHREGU_0 0x00000520 | |
| 494 | #define MAC_HASHREGU_1 0x00000524 | |
| 495 | #define MAC_HASHREGU_2 0x00000528 | |
| 496 | #define MAC_HASHREGU_3 0x0000052c | |
| 497 | #define MAC_EXTADDR_0_HIGH 0x00000530 | |
| 498 | #define MAC_EXTADDR_0_LOW 0x00000534 | |
| 499 | #define MAC_EXTADDR_1_HIGH 0x00000538 | |
| 500 | #define MAC_EXTADDR_1_LOW 0x0000053c | |
| 501 | #define MAC_EXTADDR_2_HIGH 0x00000540 | |
| 502 | #define MAC_EXTADDR_2_LOW 0x00000544 | |
| 503 | #define MAC_EXTADDR_3_HIGH 0x00000548 | |
| 504 | #define MAC_EXTADDR_3_LOW 0x0000054c | |
| 505 | #define MAC_EXTADDR_4_HIGH 0x00000550 | |
| 506 | #define MAC_EXTADDR_4_LOW 0x00000554 | |
| 507 | #define MAC_EXTADDR_5_HIGH 0x00000558 | |
| 508 | #define MAC_EXTADDR_5_LOW 0x0000055c | |
| 509 | #define MAC_EXTADDR_6_HIGH 0x00000560 | |
| 510 | #define MAC_EXTADDR_6_LOW 0x00000564 | |
| 511 | #define MAC_EXTADDR_7_HIGH 0x00000568 | |
| 512 | #define MAC_EXTADDR_7_LOW 0x0000056c | |
| 513 | #define MAC_EXTADDR_8_HIGH 0x00000570 | |
| 514 | #define MAC_EXTADDR_8_LOW 0x00000574 | |
| 515 | #define MAC_EXTADDR_9_HIGH 0x00000578 | |
| 516 | #define MAC_EXTADDR_9_LOW 0x0000057c | |
| 517 | #define MAC_EXTADDR_10_HIGH 0x00000580 | |
| 518 | #define MAC_EXTADDR_10_LOW 0x00000584 | |
| 519 | #define MAC_EXTADDR_11_HIGH 0x00000588 | |
| 520 | #define MAC_EXTADDR_11_LOW 0x0000058c | |
| 521 | #define MAC_SERDES_CFG 0x00000590 | |
| 522 | #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000 | |
| 523 | #define MAC_SERDES_STAT 0x00000594 | |
| a9daf367 MC |
524 | /* 0x598 --> 0x5a0 unused */ |
| 525 | #define MAC_PHYCFG1 0x000005a0 | |
| 526 | #define MAC_PHYCFG1_RGMII_INT 0x00000001 | |
| 527 | #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000 | |
| 528 | #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000 | |
| 529 | #define MAC_PHYCFG1_TXC_DRV 0x20000000 | |
| 530 | #define MAC_PHYCFG2 0x000005a4 | |
| 531 | #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001 | |
| fcb389df MC |
532 | #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0 |
| 533 | #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0 | |
| 534 | #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100 | |
| 535 | #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000 | |
| 536 | #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0 | |
| 537 | #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00 | |
| 538 | #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600 | |
| 539 | #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400 | |
| 540 | #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800 | |
| 541 | #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000 | |
| 542 | #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000 | |
| 543 | #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000 | |
| 544 | #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000 | |
| 545 | #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000 | |
| 546 | #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000 | |
| 547 | #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000 | |
| 548 | #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000 | |
| 549 | #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000 | |
| 550 | #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000 | |
| 551 | #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000 | |
| 552 | #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000 | |
| 553 | #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000 | |
| 554 | #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000 | |
| 555 | #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000 | |
| 556 | #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000 | |
| 557 | #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000 | |
| 558 | #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000 | |
| 559 | #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000 | |
| 560 | #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000 | |
| 561 | #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000 | |
| 562 | #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000 | |
| 563 | #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000 | |
| 564 | #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000 | |
| 565 | #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000 | |
| 566 | #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000 | |
| 567 | #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000 | |
| 568 | #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000 | |
| 569 | #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000 | |
| 570 | #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000 | |
| 571 | #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000 | |
| 572 | #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000 | |
| 573 | #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000 | |
| 574 | #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000 | |
| 575 | #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000 | |
| 576 | #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000 | |
| 577 | #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000 | |
| 578 | #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000 | |
| 579 | #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000 | |
| 580 | #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000 | |
| 581 | #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000 | |
| 582 | #define MAC_PHYCFG2_50610_LED_MODES \ | |
| 583 | (MAC_PHYCFG2_EMODE_MASK_50610 | \ | |
| 584 | MAC_PHYCFG2_EMODE_COMP_50610 | \ | |
| 585 | MAC_PHYCFG2_FMODE_MASK_50610 | \ | |
| 586 | MAC_PHYCFG2_FMODE_COMP_50610 | \ | |
| 587 | MAC_PHYCFG2_GMODE_MASK_50610 | \ | |
| 588 | MAC_PHYCFG2_GMODE_COMP_50610 | \ | |
| 589 | MAC_PHYCFG2_ACT_MASK_50610 | \ | |
| 590 | MAC_PHYCFG2_ACT_COMP_50610 | \ | |
| 591 | MAC_PHYCFG2_QUAL_MASK_50610 | \ | |
| 592 | MAC_PHYCFG2_QUAL_COMP_50610) | |
| 593 | #define MAC_PHYCFG2_AC131_LED_MODES \ | |
| 594 | (MAC_PHYCFG2_EMODE_MASK_AC131 | \ | |
| 595 | MAC_PHYCFG2_EMODE_COMP_AC131 | \ | |
| 596 | MAC_PHYCFG2_FMODE_MASK_AC131 | \ | |
| 597 | MAC_PHYCFG2_FMODE_COMP_AC131 | \ | |
| 598 | MAC_PHYCFG2_GMODE_MASK_AC131 | \ | |
| 599 | MAC_PHYCFG2_GMODE_COMP_AC131 | \ | |
| 600 | MAC_PHYCFG2_ACT_MASK_AC131 | \ | |
| 601 | MAC_PHYCFG2_ACT_COMP_AC131 | \ | |
| 602 | MAC_PHYCFG2_QUAL_MASK_AC131 | \ | |
| 603 | MAC_PHYCFG2_QUAL_COMP_AC131) | |
| 604 | #define MAC_PHYCFG2_RTL8211C_LED_MODES \ | |
| 605 | (MAC_PHYCFG2_EMODE_MASK_RT8211 | \ | |
| 606 | MAC_PHYCFG2_EMODE_COMP_RT8211 | \ | |
| 607 | MAC_PHYCFG2_FMODE_MASK_RT8211 | \ | |
| 608 | MAC_PHYCFG2_FMODE_COMP_RT8211 | \ | |
| 609 | MAC_PHYCFG2_GMODE_MASK_RT8211 | \ | |
| 610 | MAC_PHYCFG2_GMODE_COMP_RT8211 | \ | |
| 611 | MAC_PHYCFG2_ACT_MASK_RT8211 | \ | |
| 612 | MAC_PHYCFG2_ACT_COMP_RT8211 | \ | |
| 613 | MAC_PHYCFG2_QUAL_MASK_RT8211 | \ | |
| 614 | MAC_PHYCFG2_QUAL_COMP_RT8211) | |
| 615 | #define MAC_PHYCFG2_RTL8201E_LED_MODES \ | |
| 616 | (MAC_PHYCFG2_EMODE_MASK_RT8201 | \ | |
| 617 | MAC_PHYCFG2_EMODE_COMP_RT8201 | \ | |
| 618 | MAC_PHYCFG2_FMODE_MASK_RT8201 | \ | |
| 619 | MAC_PHYCFG2_FMODE_COMP_RT8201 | \ | |
| 620 | MAC_PHYCFG2_GMODE_MASK_RT8201 | \ | |
| 621 | MAC_PHYCFG2_GMODE_COMP_RT8201 | \ | |
| 622 | MAC_PHYCFG2_ACT_MASK_RT8201 | \ | |
| 623 | MAC_PHYCFG2_ACT_COMP_RT8201 | \ | |
| 624 | MAC_PHYCFG2_QUAL_MASK_RT8201 | \ | |
| 625 | MAC_PHYCFG2_QUAL_COMP_RT8201) | |
| a9daf367 MC |
626 | #define MAC_EXT_RGMII_MODE 0x000005a8 |
| 627 | #define MAC_RGMII_MODE_TX_ENABLE 0x00000001 | |
| 628 | #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002 | |
| 629 | #define MAC_RGMII_MODE_TX_RESET 0x00000004 | |
| 630 | #define MAC_RGMII_MODE_RX_INT_B 0x00000100 | |
| 631 | #define MAC_RGMII_MODE_RX_QUALITY 0x00000200 | |
| 632 | #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400 | |
| 633 | #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800 | |
| 634 | /* 0x5ac --> 0x5b0 unused */ | |
| a4e2b347 MC |
635 | #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */ |
| 636 | #define SERDES_RX_SIG_DETECT 0x00000400 | |
| 1da177e4 LT |
637 | #define SG_DIG_CTRL 0x000005b0 |
| 638 | #define SG_DIG_USING_HW_AUTONEG 0x80000000 | |
| 639 | #define SG_DIG_SOFT_RESET 0x40000000 | |
| 640 | #define SG_DIG_DISABLE_LINKRDY 0x20000000 | |
| 641 | #define SG_DIG_CRC16_CLEAR_N 0x01000000 | |
| 642 | #define SG_DIG_EN10B 0x00800000 | |
| 643 | #define SG_DIG_CLEAR_STATUS 0x00400000 | |
| 644 | #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000 | |
| 645 | #define SG_DIG_LOCAL_LINK_STATUS 0x00100000 | |
| 646 | #define SG_DIG_SPEED_STATUS_MASK 0x000c0000 | |
| 647 | #define SG_DIG_SPEED_STATUS_SHIFT 18 | |
| 648 | #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000 | |
| 649 | #define SG_DIG_RESTART_AUTONEG 0x00010000 | |
| 650 | #define SG_DIG_FIBER_MODE 0x00008000 | |
| 651 | #define SG_DIG_REMOTE_FAULT_MASK 0x00006000 | |
| 652 | #define SG_DIG_PAUSE_MASK 0x00001800 | |
| c98f6e3b MC |
653 | #define SG_DIG_PAUSE_CAP 0x00000800 |
| 654 | #define SG_DIG_ASYM_PAUSE 0x00001000 | |
| 1da177e4 LT |
655 | #define SG_DIG_GBIC_ENABLE 0x00000400 |
| 656 | #define SG_DIG_CHECK_END_ENABLE 0x00000200 | |
| 657 | #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100 | |
| 658 | #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080 | |
| 659 | #define SG_DIG_GMII_INPUT_SELECT 0x00000040 | |
| 660 | #define SG_DIG_MRADV_CRC16_SELECT 0x00000020 | |
| 661 | #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010 | |
| 662 | #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008 | |
| 663 | #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004 | |
| 664 | #define SG_DIG_REMOTE_LOOPBACK 0x00000002 | |
| 665 | #define SG_DIG_LOOPBACK 0x00000001 | |
| c98f6e3b MC |
666 | #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \ |
| 667 | SG_DIG_LOCAL_DUPLEX_STATUS | \ | |
| 668 | SG_DIG_LOCAL_LINK_STATUS | \ | |
| 669 | (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \ | |
| 670 | SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE) | |
| 1da177e4 LT |
671 | #define SG_DIG_STATUS 0x000005b4 |
| 672 | #define SG_DIG_CRC16_BUS_MASK 0xffff0000 | |
| 673 | #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */ | |
| 674 | #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */ | |
| 675 | #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */ | |
| 676 | #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */ | |
| 677 | #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */ | |
| 678 | #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */ | |
| 679 | #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0 | |
| 680 | #define SG_DIG_COMMA_DETECTOR 0x00000008 | |
| 681 | #define SG_DIG_MAC_ACK_STATUS 0x00000004 | |
| 682 | #define SG_DIG_AUTONEG_COMPLETE 0x00000002 | |
| 683 | #define SG_DIG_AUTONEG_ERROR 0x00000001 | |
| 684 | /* 0x5b8 --> 0x600 unused */ | |
| 685 | #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */ | |
| 686 | #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */ | |
| 687 | /* 0x624 --> 0x800 unused */ | |
| 688 | #define MAC_TX_STATS_OCTETS 0x00000800 | |
| 689 | #define MAC_TX_STATS_RESV1 0x00000804 | |
| 690 | #define MAC_TX_STATS_COLLISIONS 0x00000808 | |
| 691 | #define MAC_TX_STATS_XON_SENT 0x0000080c | |
| 692 | #define MAC_TX_STATS_XOFF_SENT 0x00000810 | |
| 693 | #define MAC_TX_STATS_RESV2 0x00000814 | |
| 694 | #define MAC_TX_STATS_MAC_ERRORS 0x00000818 | |
| 695 | #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c | |
| 696 | #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820 | |
| 697 | #define MAC_TX_STATS_DEFERRED 0x00000824 | |
| 698 | #define MAC_TX_STATS_RESV3 0x00000828 | |
| 699 | #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c | |
| 700 | #define MAC_TX_STATS_LATE_COL 0x00000830 | |
| 701 | #define MAC_TX_STATS_RESV4_1 0x00000834 | |
| 702 | #define MAC_TX_STATS_RESV4_2 0x00000838 | |
| 703 | #define MAC_TX_STATS_RESV4_3 0x0000083c | |
| 704 | #define MAC_TX_STATS_RESV4_4 0x00000840 | |
| 705 | #define MAC_TX_STATS_RESV4_5 0x00000844 | |
| 706 | #define MAC_TX_STATS_RESV4_6 0x00000848 | |
| 707 | #define MAC_TX_STATS_RESV4_7 0x0000084c | |
| 708 | #define MAC_TX_STATS_RESV4_8 0x00000850 | |
| 709 | #define MAC_TX_STATS_RESV4_9 0x00000854 | |
| 710 | #define MAC_TX_STATS_RESV4_10 0x00000858 | |
| 711 | #define MAC_TX_STATS_RESV4_11 0x0000085c | |
| 712 | #define MAC_TX_STATS_RESV4_12 0x00000860 | |
| 713 | #define MAC_TX_STATS_RESV4_13 0x00000864 | |
| 714 | #define MAC_TX_STATS_RESV4_14 0x00000868 | |
| 715 | #define MAC_TX_STATS_UCAST 0x0000086c | |
| 716 | #define MAC_TX_STATS_MCAST 0x00000870 | |
| 717 | #define MAC_TX_STATS_BCAST 0x00000874 | |
| 718 | #define MAC_TX_STATS_RESV5_1 0x00000878 | |
| 719 | #define MAC_TX_STATS_RESV5_2 0x0000087c | |
| 720 | #define MAC_RX_STATS_OCTETS 0x00000880 | |
| 721 | #define MAC_RX_STATS_RESV1 0x00000884 | |
| 722 | #define MAC_RX_STATS_FRAGMENTS 0x00000888 | |
| 723 | #define MAC_RX_STATS_UCAST 0x0000088c | |
| 724 | #define MAC_RX_STATS_MCAST 0x00000890 | |
| 725 | #define MAC_RX_STATS_BCAST 0x00000894 | |
| 726 | #define MAC_RX_STATS_FCS_ERRORS 0x00000898 | |
| 727 | #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c | |
| 728 | #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 | |
| 729 | #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 | |
| 730 | #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 | |
| 731 | #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac | |
| 732 | #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 | |
| 733 | #define MAC_RX_STATS_JABBERS 0x000008b4 | |
| 734 | #define MAC_RX_STATS_UNDERSIZE 0x000008b8 | |
| 735 | /* 0x8bc --> 0xc00 unused */ | |
| 736 | ||
| 737 | /* Send data initiator control registers */ | |
| 738 | #define SNDDATAI_MODE 0x00000c00 | |
| 739 | #define SNDDATAI_MODE_RESET 0x00000001 | |
| 740 | #define SNDDATAI_MODE_ENABLE 0x00000002 | |
| 741 | #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 | |
| 742 | #define SNDDATAI_STATUS 0x00000c04 | |
| 743 | #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004 | |
| 744 | #define SNDDATAI_STATSCTRL 0x00000c08 | |
| 745 | #define SNDDATAI_SCTRL_ENABLE 0x00000001 | |
| 746 | #define SNDDATAI_SCTRL_FASTUPD 0x00000002 | |
| 747 | #define SNDDATAI_SCTRL_CLEAR 0x00000004 | |
| 748 | #define SNDDATAI_SCTRL_FLUSH 0x00000008 | |
| 749 | #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010 | |
| 750 | #define SNDDATAI_STATSENAB 0x00000c0c | |
| 751 | #define SNDDATAI_STATSINCMASK 0x00000c10 | |
| b5d3772c MC |
752 | #define ISO_PKT_TX 0x00000c20 |
| 753 | /* 0xc24 --> 0xc80 unused */ | |
| 1da177e4 LT |
754 | #define SNDDATAI_COS_CNT_0 0x00000c80 |
| 755 | #define SNDDATAI_COS_CNT_1 0x00000c84 | |
| 756 | #define SNDDATAI_COS_CNT_2 0x00000c88 | |
| 757 | #define SNDDATAI_COS_CNT_3 0x00000c8c | |
| 758 | #define SNDDATAI_COS_CNT_4 0x00000c90 | |
| 759 | #define SNDDATAI_COS_CNT_5 0x00000c94 | |
| 760 | #define SNDDATAI_COS_CNT_6 0x00000c98 | |
| 761 | #define SNDDATAI_COS_CNT_7 0x00000c9c | |
| 762 | #define SNDDATAI_COS_CNT_8 0x00000ca0 | |
| 763 | #define SNDDATAI_COS_CNT_9 0x00000ca4 | |
| 764 | #define SNDDATAI_COS_CNT_10 0x00000ca8 | |
| 765 | #define SNDDATAI_COS_CNT_11 0x00000cac | |
| 766 | #define SNDDATAI_COS_CNT_12 0x00000cb0 | |
| 767 | #define SNDDATAI_COS_CNT_13 0x00000cb4 | |
| 768 | #define SNDDATAI_COS_CNT_14 0x00000cb8 | |
| 769 | #define SNDDATAI_COS_CNT_15 0x00000cbc | |
| 770 | #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 | |
| 771 | #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 | |
| 772 | #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8 | |
| 773 | #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc | |
| 774 | #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0 | |
| 775 | #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4 | |
| 776 | #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 | |
| 777 | #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc | |
| 778 | /* 0xce0 --> 0x1000 unused */ | |
| 779 | ||
| 780 | /* Send data completion control registers */ | |
| 781 | #define SNDDATAC_MODE 0x00001000 | |
| 782 | #define SNDDATAC_MODE_RESET 0x00000001 | |
| 783 | #define SNDDATAC_MODE_ENABLE 0x00000002 | |
| 9936bcf6 | 784 | #define SNDDATAC_MODE_CDELAY 0x00000010 |
| 1da177e4 LT |
785 | /* 0x1004 --> 0x1400 unused */ |
| 786 | ||
| 787 | /* Send BD ring selector */ | |
| 788 | #define SNDBDS_MODE 0x00001400 | |
| 789 | #define SNDBDS_MODE_RESET 0x00000001 | |
| 790 | #define SNDBDS_MODE_ENABLE 0x00000002 | |
| 791 | #define SNDBDS_MODE_ATTN_ENABLE 0x00000004 | |
| 792 | #define SNDBDS_STATUS 0x00001404 | |
| 793 | #define SNDBDS_STATUS_ERROR_ATTN 0x00000004 | |
| 794 | #define SNDBDS_HWDIAG 0x00001408 | |
| 795 | /* 0x140c --> 0x1440 */ | |
| 796 | #define SNDBDS_SEL_CON_IDX_0 0x00001440 | |
| 797 | #define SNDBDS_SEL_CON_IDX_1 0x00001444 | |
| 798 | #define SNDBDS_SEL_CON_IDX_2 0x00001448 | |
| 799 | #define SNDBDS_SEL_CON_IDX_3 0x0000144c | |
| 800 | #define SNDBDS_SEL_CON_IDX_4 0x00001450 | |
| 801 | #define SNDBDS_SEL_CON_IDX_5 0x00001454 | |
| 802 | #define SNDBDS_SEL_CON_IDX_6 0x00001458 | |
| 803 | #define SNDBDS_SEL_CON_IDX_7 0x0000145c | |
| 804 | #define SNDBDS_SEL_CON_IDX_8 0x00001460 | |
| 805 | #define SNDBDS_SEL_CON_IDX_9 0x00001464 | |
| 806 | #define SNDBDS_SEL_CON_IDX_10 0x00001468 | |
| 807 | #define SNDBDS_SEL_CON_IDX_11 0x0000146c | |
| 808 | #define SNDBDS_SEL_CON_IDX_12 0x00001470 | |
| 809 | #define SNDBDS_SEL_CON_IDX_13 0x00001474 | |
| 810 | #define SNDBDS_SEL_CON_IDX_14 0x00001478 | |
| 811 | #define SNDBDS_SEL_CON_IDX_15 0x0000147c | |
| 812 | /* 0x1480 --> 0x1800 unused */ | |
| 813 | ||
| 814 | /* Send BD initiator control registers */ | |
| 815 | #define SNDBDI_MODE 0x00001800 | |
| 816 | #define SNDBDI_MODE_RESET 0x00000001 | |
| 817 | #define SNDBDI_MODE_ENABLE 0x00000002 | |
| 818 | #define SNDBDI_MODE_ATTN_ENABLE 0x00000004 | |
| 819 | #define SNDBDI_STATUS 0x00001804 | |
| 820 | #define SNDBDI_STATUS_ERROR_ATTN 0x00000004 | |
| 821 | #define SNDBDI_IN_PROD_IDX_0 0x00001808 | |
| 822 | #define SNDBDI_IN_PROD_IDX_1 0x0000180c | |
| 823 | #define SNDBDI_IN_PROD_IDX_2 0x00001810 | |
| 824 | #define SNDBDI_IN_PROD_IDX_3 0x00001814 | |
| 825 | #define SNDBDI_IN_PROD_IDX_4 0x00001818 | |
| 826 | #define SNDBDI_IN_PROD_IDX_5 0x0000181c | |
| 827 | #define SNDBDI_IN_PROD_IDX_6 0x00001820 | |
| 828 | #define SNDBDI_IN_PROD_IDX_7 0x00001824 | |
| 829 | #define SNDBDI_IN_PROD_IDX_8 0x00001828 | |
| 830 | #define SNDBDI_IN_PROD_IDX_9 0x0000182c | |
| 831 | #define SNDBDI_IN_PROD_IDX_10 0x00001830 | |
| 832 | #define SNDBDI_IN_PROD_IDX_11 0x00001834 | |
| 833 | #define SNDBDI_IN_PROD_IDX_12 0x00001838 | |
| 834 | #define SNDBDI_IN_PROD_IDX_13 0x0000183c | |
| 835 | #define SNDBDI_IN_PROD_IDX_14 0x00001840 | |
| 836 | #define SNDBDI_IN_PROD_IDX_15 0x00001844 | |
| 837 | /* 0x1848 --> 0x1c00 unused */ | |
| 838 | ||
| 839 | /* Send BD completion control registers */ | |
| 840 | #define SNDBDC_MODE 0x00001c00 | |
| 841 | #define SNDBDC_MODE_RESET 0x00000001 | |
| 842 | #define SNDBDC_MODE_ENABLE 0x00000002 | |
| 843 | #define SNDBDC_MODE_ATTN_ENABLE 0x00000004 | |
| 844 | /* 0x1c04 --> 0x2000 unused */ | |
| 845 | ||
| 846 | /* Receive list placement control registers */ | |
| 847 | #define RCVLPC_MODE 0x00002000 | |
| 848 | #define RCVLPC_MODE_RESET 0x00000001 | |
| 849 | #define RCVLPC_MODE_ENABLE 0x00000002 | |
| 850 | #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 | |
| 851 | #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 | |
| 852 | #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 | |
| 853 | #define RCVLPC_STATUS 0x00002004 | |
| 854 | #define RCVLPC_STATUS_CLASS0 0x00000004 | |
| 855 | #define RCVLPC_STATUS_MAPOOR 0x00000008 | |
| 856 | #define RCVLPC_STATUS_STAT_OFLOW 0x00000010 | |
| 857 | #define RCVLPC_LOCK 0x00002008 | |
| 858 | #define RCVLPC_LOCK_REQ_MASK 0x0000ffff | |
| 859 | #define RCVLPC_LOCK_REQ_SHIFT 0 | |
| 860 | #define RCVLPC_LOCK_GRANT_MASK 0xffff0000 | |
| 861 | #define RCVLPC_LOCK_GRANT_SHIFT 16 | |
| 862 | #define RCVLPC_NON_EMPTY_BITS 0x0000200c | |
| 863 | #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff | |
| 864 | #define RCVLPC_CONFIG 0x00002010 | |
| 865 | #define RCVLPC_STATSCTRL 0x00002014 | |
| 866 | #define RCVLPC_STATSCTRL_ENABLE 0x00000001 | |
| 867 | #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 | |
| 868 | #define RCVLPC_STATS_ENABLE 0x00002018 | |
| 255ca311 | 869 | #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 |
| 1661394e | 870 | #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 |
| 1da177e4 LT |
871 | #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 |
| 872 | #define RCVLPC_STATS_INCMASK 0x0000201c | |
| 873 | /* 0x2020 --> 0x2100 unused */ | |
| 874 | #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */ | |
| 875 | #define SELLST_TAIL 0x00000004 | |
| 876 | #define SELLST_CONT 0x00000008 | |
| 877 | #define SELLST_UNUSED 0x0000000c | |
| 878 | #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */ | |
| 879 | #define RCVLPC_DROP_FILTER_CNT 0x00002240 | |
| 880 | #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244 | |
| 881 | #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 | |
| 882 | #define RCVLPC_NO_RCV_BD_CNT 0x0000224c | |
| 883 | #define RCVLPC_IN_DISCARDS_CNT 0x00002250 | |
| 884 | #define RCVLPC_IN_ERRORS_CNT 0x00002254 | |
| 885 | #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258 | |
| 886 | /* 0x225c --> 0x2400 unused */ | |
| 887 | ||
| 888 | /* Receive Data and Receive BD Initiator Control */ | |
| 889 | #define RCVDBDI_MODE 0x00002400 | |
| 890 | #define RCVDBDI_MODE_RESET 0x00000001 | |
| 891 | #define RCVDBDI_MODE_ENABLE 0x00000002 | |
| 892 | #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 | |
| 893 | #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008 | |
| 894 | #define RCVDBDI_MODE_INV_RING_SZ 0x00000010 | |
| 895 | #define RCVDBDI_STATUS 0x00002404 | |
| 896 | #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 | |
| 897 | #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 | |
| 898 | #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010 | |
| 899 | #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 | |
| 900 | /* 0x240c --> 0x2440 unused */ | |
| 901 | #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */ | |
| 902 | #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */ | |
| 903 | #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */ | |
| 904 | #define RCVDBDI_JUMBO_CON_IDX 0x00002470 | |
| 905 | #define RCVDBDI_STD_CON_IDX 0x00002474 | |
| 906 | #define RCVDBDI_MINI_CON_IDX 0x00002478 | |
| 907 | /* 0x247c --> 0x2480 unused */ | |
| 908 | #define RCVDBDI_BD_PROD_IDX_0 0x00002480 | |
| 909 | #define RCVDBDI_BD_PROD_IDX_1 0x00002484 | |
| 910 | #define RCVDBDI_BD_PROD_IDX_2 0x00002488 | |
| 911 | #define RCVDBDI_BD_PROD_IDX_3 0x0000248c | |
| 912 | #define RCVDBDI_BD_PROD_IDX_4 0x00002490 | |
| 913 | #define RCVDBDI_BD_PROD_IDX_5 0x00002494 | |
| 914 | #define RCVDBDI_BD_PROD_IDX_6 0x00002498 | |
| 915 | #define RCVDBDI_BD_PROD_IDX_7 0x0000249c | |
| 916 | #define RCVDBDI_BD_PROD_IDX_8 0x000024a0 | |
| 917 | #define RCVDBDI_BD_PROD_IDX_9 0x000024a4 | |
| 918 | #define RCVDBDI_BD_PROD_IDX_10 0x000024a8 | |
| 919 | #define RCVDBDI_BD_PROD_IDX_11 0x000024ac | |
| 920 | #define RCVDBDI_BD_PROD_IDX_12 0x000024b0 | |
| 921 | #define RCVDBDI_BD_PROD_IDX_13 0x000024b4 | |
| 922 | #define RCVDBDI_BD_PROD_IDX_14 0x000024b8 | |
| 923 | #define RCVDBDI_BD_PROD_IDX_15 0x000024bc | |
| 924 | #define RCVDBDI_HWDIAG 0x000024c0 | |
| 925 | /* 0x24c4 --> 0x2800 unused */ | |
| 926 | ||
| 927 | /* Receive Data Completion Control */ | |
| 928 | #define RCVDCC_MODE 0x00002800 | |
| 929 | #define RCVDCC_MODE_RESET 0x00000001 | |
| 930 | #define RCVDCC_MODE_ENABLE 0x00000002 | |
| 931 | #define RCVDCC_MODE_ATTN_ENABLE 0x00000004 | |
| 932 | /* 0x2804 --> 0x2c00 unused */ | |
| 933 | ||
| 934 | /* Receive BD Initiator Control Registers */ | |
| 935 | #define RCVBDI_MODE 0x00002c00 | |
| 936 | #define RCVBDI_MODE_RESET 0x00000001 | |
| 937 | #define RCVBDI_MODE_ENABLE 0x00000002 | |
| 938 | #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 | |
| 939 | #define RCVBDI_STATUS 0x00002c04 | |
| 940 | #define RCVBDI_STATUS_RCB_ATTN 0x00000004 | |
| 941 | #define RCVBDI_JUMBO_PROD_IDX 0x00002c08 | |
| 942 | #define RCVBDI_STD_PROD_IDX 0x00002c0c | |
| 943 | #define RCVBDI_MINI_PROD_IDX 0x00002c10 | |
| 944 | #define RCVBDI_MINI_THRESH 0x00002c14 | |
| 945 | #define RCVBDI_STD_THRESH 0x00002c18 | |
| 946 | #define RCVBDI_JUMBO_THRESH 0x00002c1c | |
| 947 | /* 0x2c20 --> 0x3000 unused */ | |
| 948 | ||
| 949 | /* Receive BD Completion Control Registers */ | |
| 950 | #define RCVCC_MODE 0x00003000 | |
| 951 | #define RCVCC_MODE_RESET 0x00000001 | |
| 952 | #define RCVCC_MODE_ENABLE 0x00000002 | |
| 953 | #define RCVCC_MODE_ATTN_ENABLE 0x00000004 | |
| 954 | #define RCVCC_STATUS 0x00003004 | |
| 955 | #define RCVCC_STATUS_ERROR_ATTN 0x00000004 | |
| 956 | #define RCVCC_JUMP_PROD_IDX 0x00003008 | |
| 957 | #define RCVCC_STD_PROD_IDX 0x0000300c | |
| 958 | #define RCVCC_MINI_PROD_IDX 0x00003010 | |
| 959 | /* 0x3014 --> 0x3400 unused */ | |
| 960 | ||
| 961 | /* Receive list selector control registers */ | |
| 962 | #define RCVLSC_MODE 0x00003400 | |
| 963 | #define RCVLSC_MODE_RESET 0x00000001 | |
| 964 | #define RCVLSC_MODE_ENABLE 0x00000002 | |
| 965 | #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 | |
| 966 | #define RCVLSC_STATUS 0x00003404 | |
| 967 | #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 | |
| d30cdd28 MC |
968 | /* 0x3408 --> 0x3600 unused */ |
| 969 | ||
| 970 | /* CPMU registers */ | |
| 971 | #define TG3_CPMU_CTRL 0x00003600 | |
| 972 | #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 | |
| 973 | #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 | |
| 9936bcf6 | 974 | #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000 |
| b2a5c19c | 975 | #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 |
| 9acb961e MC |
976 | #define TG3_CPMU_LSPD_10MB_CLK 0x00003604 |
| 977 | #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000 | |
| 978 | #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 | |
| 979 | /* 0x3608 --> 0x360c unused */ | |
| ce057f01 MC |
980 | |
| 981 | #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c | |
| 982 | #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 | |
| 983 | #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 | |
| 984 | #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000 | |
| 9acb961e MC |
985 | #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610 |
| 986 | #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000 | |
| 987 | #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 | |
| 988 | /* 0x3614 --> 0x361c unused */ | |
| 989 | ||
| 990 | #define TG3_CPMU_HST_ACC 0x0000361c | |
| 991 | #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 | |
| 992 | #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 | |
| aa6c91fe MC |
993 | /* 0x3620 --> 0x3630 unused */ |
| 994 | ||
| 995 | #define TG3_CPMU_CLCK_STAT 0x00003630 | |
| 996 | #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 | |
| 997 | #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 | |
| 998 | #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 | |
| 999 | #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 | |
| 1000 | /* 0x3634 --> 0x365c unused */ | |
| 9936bcf6 MC |
1001 | |
| 1002 | #define TG3_CPMU_MUTEX_REQ 0x0000365c | |
| 1003 | #define CPMU_MUTEX_REQ_DRIVER 0x00001000 | |
| 1004 | #define TG3_CPMU_MUTEX_GNT 0x00003660 | |
| 1005 | #define CPMU_MUTEX_GNT_DRIVER 0x00001000 | |
| 1006 | /* 0x3664 --> 0x3800 unused */ | |
| 1da177e4 LT |
1007 | |
| 1008 | /* Mbuf cluster free registers */ | |
| 1009 | #define MBFREE_MODE 0x00003800 | |
| 1010 | #define MBFREE_MODE_RESET 0x00000001 | |
| 1011 | #define MBFREE_MODE_ENABLE 0x00000002 | |
| 1012 | #define MBFREE_STATUS 0x00003804 | |
| 1013 | /* 0x3808 --> 0x3c00 unused */ | |
| 1014 | ||
| 1015 | /* Host coalescing control registers */ | |
| 1016 | #define HOSTCC_MODE 0x00003c00 | |
| 1017 | #define HOSTCC_MODE_RESET 0x00000001 | |
| 1018 | #define HOSTCC_MODE_ENABLE 0x00000002 | |
| 1019 | #define HOSTCC_MODE_ATTN 0x00000004 | |
| 1020 | #define HOSTCC_MODE_NOW 0x00000008 | |
| 1021 | #define HOSTCC_MODE_FULL_STATUS 0x00000000 | |
| 1022 | #define HOSTCC_MODE_64BYTE 0x00000080 | |
| 1023 | #define HOSTCC_MODE_32BYTE 0x00000100 | |
| 1024 | #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200 | |
| 1025 | #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400 | |
| 1026 | #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800 | |
| 1027 | #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000 | |
| 1028 | #define HOSTCC_STATUS 0x00003c04 | |
| 1029 | #define HOSTCC_STATUS_ERROR_ATTN 0x00000004 | |
| 1030 | #define HOSTCC_RXCOL_TICKS 0x00003c08 | |
| 1031 | #define LOW_RXCOL_TICKS 0x00000032 | |
| 15f9850d | 1032 | #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014 |
| 1da177e4 LT |
1033 | #define DEFAULT_RXCOL_TICKS 0x00000048 |
| 1034 | #define HIGH_RXCOL_TICKS 0x00000096 | |
| d244c892 | 1035 | #define MAX_RXCOL_TICKS 0x000003ff |
| 1da177e4 LT |
1036 | #define HOSTCC_TXCOL_TICKS 0x00003c0c |
| 1037 | #define LOW_TXCOL_TICKS 0x00000096 | |
| 15f9850d | 1038 | #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048 |
| 1da177e4 LT |
1039 | #define DEFAULT_TXCOL_TICKS 0x0000012c |
| 1040 | #define HIGH_TXCOL_TICKS 0x00000145 | |
| d244c892 | 1041 | #define MAX_TXCOL_TICKS 0x000003ff |
| 1da177e4 LT |
1042 | #define HOSTCC_RXMAX_FRAMES 0x00003c10 |
| 1043 | #define LOW_RXMAX_FRAMES 0x00000005 | |
| 1044 | #define DEFAULT_RXMAX_FRAMES 0x00000008 | |
| 1045 | #define HIGH_RXMAX_FRAMES 0x00000012 | |
| d244c892 | 1046 | #define MAX_RXMAX_FRAMES 0x000000ff |
| 1da177e4 LT |
1047 | #define HOSTCC_TXMAX_FRAMES 0x00003c14 |
| 1048 | #define LOW_TXMAX_FRAMES 0x00000035 | |
| 1049 | #define DEFAULT_TXMAX_FRAMES 0x0000004b | |
| 1050 | #define HIGH_TXMAX_FRAMES 0x00000052 | |
| d244c892 | 1051 | #define MAX_TXMAX_FRAMES 0x000000ff |
| 1da177e4 LT |
1052 | #define HOSTCC_RXCOAL_TICK_INT 0x00003c18 |
| 1053 | #define DEFAULT_RXCOAL_TICK_INT 0x00000019 | |
| 15f9850d | 1054 | #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014 |
| d244c892 | 1055 | #define MAX_RXCOAL_TICK_INT 0x000003ff |
| 1da177e4 LT |
1056 | #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c |
| 1057 | #define DEFAULT_TXCOAL_TICK_INT 0x00000019 | |
| 15f9850d | 1058 | #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014 |
| d244c892 | 1059 | #define MAX_TXCOAL_TICK_INT 0x000003ff |
| 1da177e4 LT |
1060 | #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20 |
| 1061 | #define DEFAULT_RXCOAL_MAXF_INT 0x00000005 | |
| d244c892 | 1062 | #define MAX_RXCOAL_MAXF_INT 0x000000ff |
| 1da177e4 LT |
1063 | #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24 |
| 1064 | #define DEFAULT_TXCOAL_MAXF_INT 0x00000005 | |
| d244c892 | 1065 | #define MAX_TXCOAL_MAXF_INT 0x000000ff |
| 1da177e4 LT |
1066 | #define HOSTCC_STAT_COAL_TICKS 0x00003c28 |
| 1067 | #define DEFAULT_STAT_COAL_TICKS 0x000f4240 | |
| d244c892 MC |
1068 | #define MAX_STAT_COAL_TICKS 0xd693d400 |
| 1069 | #define MIN_STAT_COAL_TICKS 0x00000064 | |
| 1da177e4 LT |
1070 | /* 0x3c2c --> 0x3c30 unused */ |
| 1071 | #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */ | |
| 1072 | #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */ | |
| 1073 | #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 | |
| 1074 | #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 | |
| 1075 | #define HOSTCC_FLOW_ATTN 0x00003c48 | |
| 1076 | /* 0x3c4c --> 0x3c50 unused */ | |
| 1077 | #define HOSTCC_JUMBO_CON_IDX 0x00003c50 | |
| 1078 | #define HOSTCC_STD_CON_IDX 0x00003c54 | |
| 1079 | #define HOSTCC_MINI_CON_IDX 0x00003c58 | |
| 1080 | /* 0x3c5c --> 0x3c80 unused */ | |
| 1081 | #define HOSTCC_RET_PROD_IDX_0 0x00003c80 | |
| 1082 | #define HOSTCC_RET_PROD_IDX_1 0x00003c84 | |
| 1083 | #define HOSTCC_RET_PROD_IDX_2 0x00003c88 | |
| 1084 | #define HOSTCC_RET_PROD_IDX_3 0x00003c8c | |
| 1085 | #define HOSTCC_RET_PROD_IDX_4 0x00003c90 | |
| 1086 | #define HOSTCC_RET_PROD_IDX_5 0x00003c94 | |
| 1087 | #define HOSTCC_RET_PROD_IDX_6 0x00003c98 | |
| 1088 | #define HOSTCC_RET_PROD_IDX_7 0x00003c9c | |
| 1089 | #define HOSTCC_RET_PROD_IDX_8 0x00003ca0 | |
| 1090 | #define HOSTCC_RET_PROD_IDX_9 0x00003ca4 | |
| 1091 | #define HOSTCC_RET_PROD_IDX_10 0x00003ca8 | |
| 1092 | #define HOSTCC_RET_PROD_IDX_11 0x00003cac | |
| 1093 | #define HOSTCC_RET_PROD_IDX_12 0x00003cb0 | |
| 1094 | #define HOSTCC_RET_PROD_IDX_13 0x00003cb4 | |
| 1095 | #define HOSTCC_RET_PROD_IDX_14 0x00003cb8 | |
| 1096 | #define HOSTCC_RET_PROD_IDX_15 0x00003cbc | |
| 1097 | #define HOSTCC_SND_CON_IDX_0 0x00003cc0 | |
| 1098 | #define HOSTCC_SND_CON_IDX_1 0x00003cc4 | |
| 1099 | #define HOSTCC_SND_CON_IDX_2 0x00003cc8 | |
| 1100 | #define HOSTCC_SND_CON_IDX_3 0x00003ccc | |
| 1101 | #define HOSTCC_SND_CON_IDX_4 0x00003cd0 | |
| 1102 | #define HOSTCC_SND_CON_IDX_5 0x00003cd4 | |
| 1103 | #define HOSTCC_SND_CON_IDX_6 0x00003cd8 | |
| 1104 | #define HOSTCC_SND_CON_IDX_7 0x00003cdc | |
| 1105 | #define HOSTCC_SND_CON_IDX_8 0x00003ce0 | |
| 1106 | #define HOSTCC_SND_CON_IDX_9 0x00003ce4 | |
| 1107 | #define HOSTCC_SND_CON_IDX_10 0x00003ce8 | |
| 1108 | #define HOSTCC_SND_CON_IDX_11 0x00003cec | |
| 1109 | #define HOSTCC_SND_CON_IDX_12 0x00003cf0 | |
| 1110 | #define HOSTCC_SND_CON_IDX_13 0x00003cf4 | |
| 1111 | #define HOSTCC_SND_CON_IDX_14 0x00003cf8 | |
| 1112 | #define HOSTCC_SND_CON_IDX_15 0x00003cfc | |
| 1113 | /* 0x3d00 --> 0x4000 unused */ | |
| 1114 | ||
| 1115 | /* Memory arbiter control registers */ | |
| 1116 | #define MEMARB_MODE 0x00004000 | |
| 1117 | #define MEMARB_MODE_RESET 0x00000001 | |
| 1118 | #define MEMARB_MODE_ENABLE 0x00000002 | |
| 1119 | #define MEMARB_STATUS 0x00004004 | |
| 1120 | #define MEMARB_TRAP_ADDR_LOW 0x00004008 | |
| 1121 | #define MEMARB_TRAP_ADDR_HIGH 0x0000400c | |
| 1122 | /* 0x4010 --> 0x4400 unused */ | |
| 1123 | ||
| 1124 | /* Buffer manager control registers */ | |
| 1125 | #define BUFMGR_MODE 0x00004400 | |
| 1126 | #define BUFMGR_MODE_RESET 0x00000001 | |
| 1127 | #define BUFMGR_MODE_ENABLE 0x00000002 | |
| 1128 | #define BUFMGR_MODE_ATTN_ENABLE 0x00000004 | |
| 1129 | #define BUFMGR_MODE_BM_TEST 0x00000008 | |
| 1130 | #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 | |
| 1131 | #define BUFMGR_STATUS 0x00004404 | |
| 1132 | #define BUFMGR_STATUS_ERROR 0x00000004 | |
| 1133 | #define BUFMGR_STATUS_MBLOW 0x00000010 | |
| 1134 | #define BUFMGR_MB_POOL_ADDR 0x00004408 | |
| 1135 | #define BUFMGR_MB_POOL_SIZE 0x0000440c | |
| 1136 | #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410 | |
| 1137 | #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050 | |
| 1138 | #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 | |
| 1139 | #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 | |
| fdfec172 | 1140 | #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000 |
| 1da177e4 LT |
1141 | #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414 |
| 1142 | #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020 | |
| 1143 | #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 | |
| b5d3772c | 1144 | #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004 |
| 1da177e4 | 1145 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098 |
| fdfec172 | 1146 | #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b |
| 1da177e4 LT |
1147 | #define BUFMGR_MB_HIGH_WATER 0x00004418 |
| 1148 | #define DEFAULT_MB_HIGH_WATER 0x00000060 | |
| 1149 | #define DEFAULT_MB_HIGH_WATER_5705 0x00000060 | |
| b5d3772c | 1150 | #define DEFAULT_MB_HIGH_WATER_5906 0x00000010 |
| 1da177e4 | 1151 | #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c |
| fdfec172 | 1152 | #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096 |
| 1da177e4 LT |
1153 | #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c |
| 1154 | #define BUFMGR_MB_ALLOC_BIT 0x10000000 | |
| 1155 | #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420 | |
| 1156 | #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424 | |
| 1157 | #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428 | |
| 1158 | #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c | |
| 1159 | #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430 | |
| 1160 | #define BUFMGR_DMA_LOW_WATER 0x00004434 | |
| 1161 | #define DEFAULT_DMA_LOW_WATER 0x00000005 | |
| 1162 | #define BUFMGR_DMA_HIGH_WATER 0x00004438 | |
| 1163 | #define DEFAULT_DMA_HIGH_WATER 0x0000000a | |
| 1164 | #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c | |
| 1165 | #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440 | |
| 1166 | #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444 | |
| 1167 | #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448 | |
| 1168 | #define BUFMGR_HWDIAG_0 0x0000444c | |
| 1169 | #define BUFMGR_HWDIAG_1 0x00004450 | |
| 1170 | #define BUFMGR_HWDIAG_2 0x00004454 | |
| 1171 | /* 0x4458 --> 0x4800 unused */ | |
| 1172 | ||
| 1173 | /* Read DMA control registers */ | |
| 1174 | #define RDMAC_MODE 0x00004800 | |
| 1175 | #define RDMAC_MODE_RESET 0x00000001 | |
| 1176 | #define RDMAC_MODE_ENABLE 0x00000002 | |
| 1177 | #define RDMAC_MODE_TGTABORT_ENAB 0x00000004 | |
| 1178 | #define RDMAC_MODE_MSTABORT_ENAB 0x00000008 | |
| 1179 | #define RDMAC_MODE_PARITYERR_ENAB 0x00000010 | |
| 1180 | #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020 | |
| 1181 | #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 | |
| 1182 | #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080 | |
| 1183 | #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | |
| 1184 | #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 | |
| 1185 | #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 | |
| d30cdd28 | 1186 | #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 |
| 1da177e4 | 1187 | #define RDMAC_MODE_SPLIT_RESET 0x00001000 |
| d30cdd28 MC |
1188 | #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 |
| 1189 | #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 | |
| 1da177e4 LT |
1190 | #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 |
| 1191 | #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 | |
| 027455ad MC |
1192 | #define RDMAC_MODE_IPV4_LSO_EN 0x08000000 |
| 1193 | #define RDMAC_MODE_IPV6_LSO_EN 0x10000000 | |
| 1da177e4 LT |
1194 | #define RDMAC_STATUS 0x00004804 |
| 1195 | #define RDMAC_STATUS_TGTABORT 0x00000004 | |
| 1196 | #define RDMAC_STATUS_MSTABORT 0x00000008 | |
| 1197 | #define RDMAC_STATUS_PARITYERR 0x00000010 | |
| 1198 | #define RDMAC_STATUS_ADDROFLOW 0x00000020 | |
| 1199 | #define RDMAC_STATUS_FIFOOFLOW 0x00000040 | |
| 1200 | #define RDMAC_STATUS_FIFOURUN 0x00000080 | |
| 1201 | #define RDMAC_STATUS_FIFOOREAD 0x00000100 | |
| 1202 | #define RDMAC_STATUS_LNGREAD 0x00000200 | |
| 1203 | /* 0x4808 --> 0x4c00 unused */ | |
| 1204 | ||
| 1205 | /* Write DMA control registers */ | |
| 1206 | #define WDMAC_MODE 0x00004c00 | |
| 1207 | #define WDMAC_MODE_RESET 0x00000001 | |
| 1208 | #define WDMAC_MODE_ENABLE 0x00000002 | |
| 1209 | #define WDMAC_MODE_TGTABORT_ENAB 0x00000004 | |
| 1210 | #define WDMAC_MODE_MSTABORT_ENAB 0x00000008 | |
| 1211 | #define WDMAC_MODE_PARITYERR_ENAB 0x00000010 | |
| 1212 | #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020 | |
| 1213 | #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 | |
| 1214 | #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080 | |
| 1215 | #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | |
| 1216 | #define WDMAC_MODE_LNGREAD_ENAB 0x00000200 | |
| 1217 | #define WDMAC_MODE_RX_ACCEL 0x00000400 | |
| f51f3562 | 1218 | #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000 |
| 1da177e4 LT |
1219 | #define WDMAC_STATUS 0x00004c04 |
| 1220 | #define WDMAC_STATUS_TGTABORT 0x00000004 | |
| 1221 | #define WDMAC_STATUS_MSTABORT 0x00000008 | |
| 1222 | #define WDMAC_STATUS_PARITYERR 0x00000010 | |
| 1223 | #define WDMAC_STATUS_ADDROFLOW 0x00000020 | |
| 1224 | #define WDMAC_STATUS_FIFOOFLOW 0x00000040 | |
| 1225 | #define WDMAC_STATUS_FIFOURUN 0x00000080 | |
| 1226 | #define WDMAC_STATUS_FIFOOREAD 0x00000100 | |
| 1227 | #define WDMAC_STATUS_LNGREAD 0x00000200 | |
| 1228 | /* 0x4c08 --> 0x5000 unused */ | |
| 1229 | ||
| 1230 | /* Per-cpu register offsets (arm9) */ | |
| 1231 | #define CPU_MODE 0x00000000 | |
| 1232 | #define CPU_MODE_RESET 0x00000001 | |
| 1233 | #define CPU_MODE_HALT 0x00000400 | |
| 1234 | #define CPU_STATE 0x00000004 | |
| 1235 | #define CPU_EVTMASK 0x00000008 | |
| 1236 | /* 0xc --> 0x1c reserved */ | |
| 1237 | #define CPU_PC 0x0000001c | |
| 1238 | #define CPU_INSN 0x00000020 | |
| 1239 | #define CPU_SPAD_UFLOW 0x00000024 | |
| 1240 | #define CPU_WDOG_CLEAR 0x00000028 | |
| 1241 | #define CPU_WDOG_VECTOR 0x0000002c | |
| 1242 | #define CPU_WDOG_PC 0x00000030 | |
| 1243 | #define CPU_HW_BP 0x00000034 | |
| 1244 | /* 0x38 --> 0x44 unused */ | |
| 1245 | #define CPU_WDOG_SAVED_STATE 0x00000044 | |
| 1246 | #define CPU_LAST_BRANCH_ADDR 0x00000048 | |
| 1247 | #define CPU_SPAD_UFLOW_SET 0x0000004c | |
| 1248 | /* 0x50 --> 0x200 unused */ | |
| 1249 | #define CPU_R0 0x00000200 | |
| 1250 | #define CPU_R1 0x00000204 | |
| 1251 | #define CPU_R2 0x00000208 | |
| 1252 | #define CPU_R3 0x0000020c | |
| 1253 | #define CPU_R4 0x00000210 | |
| 1254 | #define CPU_R5 0x00000214 | |
| 1255 | #define CPU_R6 0x00000218 | |
| 1256 | #define CPU_R7 0x0000021c | |
| 1257 | #define CPU_R8 0x00000220 | |
| 1258 | #define CPU_R9 0x00000224 | |
| 1259 | #define CPU_R10 0x00000228 | |
| 1260 | #define CPU_R11 0x0000022c | |
| 1261 | #define CPU_R12 0x00000230 | |
| 1262 | #define CPU_R13 0x00000234 | |
| 1263 | #define CPU_R14 0x00000238 | |
| 1264 | #define CPU_R15 0x0000023c | |
| 1265 | #define CPU_R16 0x00000240 | |
| 1266 | #define CPU_R17 0x00000244 | |
| 1267 | #define CPU_R18 0x00000248 | |
| 1268 | #define CPU_R19 0x0000024c | |
| 1269 | #define CPU_R20 0x00000250 | |
| 1270 | #define CPU_R21 0x00000254 | |
| 1271 | #define CPU_R22 0x00000258 | |
| 1272 | #define CPU_R23 0x0000025c | |
| 1273 | #define CPU_R24 0x00000260 | |
| 1274 | #define CPU_R25 0x00000264 | |
| 1275 | #define CPU_R26 0x00000268 | |
| 1276 | #define CPU_R27 0x0000026c | |
| 1277 | #define CPU_R28 0x00000270 | |
| 1278 | #define CPU_R29 0x00000274 | |
| 1279 | #define CPU_R30 0x00000278 | |
| 1280 | #define CPU_R31 0x0000027c | |
| 1281 | /* 0x280 --> 0x400 unused */ | |
| 1282 | ||
| 1283 | #define RX_CPU_BASE 0x00005000 | |
| 091465d7 CE |
1284 | #define RX_CPU_MODE 0x00005000 |
| 1285 | #define RX_CPU_STATE 0x00005004 | |
| 1286 | #define RX_CPU_PGMCTR 0x0000501c | |
| 1287 | #define RX_CPU_HWBKPT 0x00005034 | |
| 1da177e4 | 1288 | #define TX_CPU_BASE 0x00005400 |
| 091465d7 CE |
1289 | #define TX_CPU_MODE 0x00005400 |
| 1290 | #define TX_CPU_STATE 0x00005404 | |
| 1291 | #define TX_CPU_PGMCTR 0x0000541c | |
| 1da177e4 | 1292 | |
| b5d3772c MC |
1293 | #define VCPU_STATUS 0x00005100 |
| 1294 | #define VCPU_STATUS_INIT_DONE 0x04000000 | |
| 1295 | #define VCPU_STATUS_DRV_RESET 0x08000000 | |
| 1296 | ||
| 8ed5d97e | 1297 | #define VCPU_CFGSHDW 0x00005104 |
| 0527ba35 MC |
1298 | #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001 |
| 1299 | #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004 | |
| 8ed5d97e MC |
1300 | #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000 |
| 1301 | ||
| 1da177e4 | 1302 | /* Mailboxes */ |
| b5d3772c | 1303 | #define GRCMBOX_BASE 0x00005600 |
| 1da177e4 LT |
1304 | #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */ |
| 1305 | #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */ | |
| 1306 | #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */ | |
| 1307 | #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */ | |
| 1308 | #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */ | |
| 1309 | #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */ | |
| 1310 | #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */ | |
| 1311 | #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */ | |
| 1312 | #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */ | |
| 1313 | #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */ | |
| 1314 | #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */ | |
| 1315 | #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */ | |
| 1316 | #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */ | |
| 1317 | #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */ | |
| 1318 | #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */ | |
| 1319 | #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */ | |
| 1320 | #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */ | |
| 1321 | #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */ | |
| 1322 | #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */ | |
| 1323 | #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */ | |
| 1324 | #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */ | |
| 1325 | #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */ | |
| 1326 | #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */ | |
| 1327 | #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */ | |
| 1328 | #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */ | |
| 1329 | #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */ | |
| 1330 | #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */ | |
| 1331 | #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */ | |
| 1332 | #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */ | |
| 1333 | #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */ | |
| 1334 | #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */ | |
| 1335 | #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */ | |
| 1336 | #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */ | |
| 1337 | #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */ | |
| 1338 | #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */ | |
| 1339 | #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */ | |
| 1340 | #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */ | |
| 1341 | #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */ | |
| 1342 | #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */ | |
| 1343 | #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */ | |
| 1344 | #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */ | |
| 1345 | #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */ | |
| 1346 | #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */ | |
| 1347 | #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */ | |
| 1348 | #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */ | |
| 1349 | #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */ | |
| 1350 | #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */ | |
| 1351 | #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */ | |
| 1352 | #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */ | |
| 1353 | #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */ | |
| 1354 | #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */ | |
| 1355 | #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */ | |
| 1356 | #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */ | |
| 1357 | #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */ | |
| 1358 | #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */ | |
| 1359 | #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */ | |
| 1360 | #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */ | |
| 1361 | #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */ | |
| 1362 | #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */ | |
| 1363 | #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */ | |
| 1364 | #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */ | |
| 1365 | #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */ | |
| 1366 | #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */ | |
| 1367 | #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */ | |
| 1368 | #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 | |
| 1369 | #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 | |
| 1370 | #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 | |
| 1371 | #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c | |
| 1372 | /* 0x5a10 --> 0x5c00 */ | |
| 1373 | ||
| 1374 | /* Flow Through queues */ | |
| 1375 | #define FTQ_RESET 0x00005c00 | |
| 1376 | /* 0x5c04 --> 0x5c10 unused */ | |
| 1377 | #define FTQ_DMA_NORM_READ_CTL 0x00005c10 | |
| 1378 | #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 | |
| 1379 | #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 | |
| 1380 | #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c | |
| 1381 | #define FTQ_DMA_HIGH_READ_CTL 0x00005c20 | |
| 1382 | #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 | |
| 1383 | #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 | |
| 1384 | #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c | |
| 1385 | #define FTQ_DMA_COMP_DISC_CTL 0x00005c30 | |
| 1386 | #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 | |
| 1387 | #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 | |
| 1388 | #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c | |
| 1389 | #define FTQ_SEND_BD_COMP_CTL 0x00005c40 | |
| 1390 | #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 | |
| 1391 | #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 | |
| 1392 | #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c | |
| 1393 | #define FTQ_SEND_DATA_INIT_CTL 0x00005c50 | |
| 1394 | #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 | |
| 1395 | #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 | |
| 1396 | #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c | |
| 1397 | #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60 | |
| 1398 | #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 | |
| 1399 | #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 | |
| 1400 | #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c | |
| 1401 | #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70 | |
| 1402 | #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 | |
| 1403 | #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 | |
| 1404 | #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c | |
| 1405 | #define FTQ_SWTYPE1_CTL 0x00005c80 | |
| 1406 | #define FTQ_SWTYPE1_FULL_CNT 0x00005c84 | |
| 1407 | #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 | |
| 1408 | #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c | |
| 1409 | #define FTQ_SEND_DATA_COMP_CTL 0x00005c90 | |
| 1410 | #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 | |
| 1411 | #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 | |
| 1412 | #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c | |
| 1413 | #define FTQ_HOST_COAL_CTL 0x00005ca0 | |
| 1414 | #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4 | |
| 1415 | #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 | |
| 1416 | #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac | |
| 1417 | #define FTQ_MAC_TX_CTL 0x00005cb0 | |
| 1418 | #define FTQ_MAC_TX_FULL_CNT 0x00005cb4 | |
| 1419 | #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 | |
| 1420 | #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc | |
| 1421 | #define FTQ_MB_FREE_CTL 0x00005cc0 | |
| 1422 | #define FTQ_MB_FREE_FULL_CNT 0x00005cc4 | |
| 1423 | #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 | |
| 1424 | #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc | |
| 1425 | #define FTQ_RCVBD_COMP_CTL 0x00005cd0 | |
| 1426 | #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 | |
| 1427 | #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 | |
| 1428 | #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc | |
| 1429 | #define FTQ_RCVLST_PLMT_CTL 0x00005ce0 | |
| 1430 | #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 | |
| 1431 | #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 | |
| 1432 | #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec | |
| 1433 | #define FTQ_RCVDATA_INI_CTL 0x00005cf0 | |
| 1434 | #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 | |
| 1435 | #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 | |
| 1436 | #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc | |
| 1437 | #define FTQ_RCVDATA_COMP_CTL 0x00005d00 | |
| 1438 | #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 | |
| 1439 | #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 | |
| 1440 | #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c | |
| 1441 | #define FTQ_SWTYPE2_CTL 0x00005d10 | |
| 1442 | #define FTQ_SWTYPE2_FULL_CNT 0x00005d14 | |
| 1443 | #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 | |
| 1444 | #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c | |
| 1445 | /* 0x5d20 --> 0x6000 unused */ | |
| 1446 | ||
| 1447 | /* Message signaled interrupt registers */ | |
| 1448 | #define MSGINT_MODE 0x00006000 | |
| 1449 | #define MSGINT_MODE_RESET 0x00000001 | |
| 1450 | #define MSGINT_MODE_ENABLE 0x00000002 | |
| 1451 | #define MSGINT_STATUS 0x00006004 | |
| 1452 | #define MSGINT_FIFO 0x00006008 | |
| 1453 | /* 0x600c --> 0x6400 unused */ | |
| 1454 | ||
| 1455 | /* DMA completion registers */ | |
| 1456 | #define DMAC_MODE 0x00006400 | |
| 1457 | #define DMAC_MODE_RESET 0x00000001 | |
| 1458 | #define DMAC_MODE_ENABLE 0x00000002 | |
| 1459 | /* 0x6404 --> 0x6800 unused */ | |
| 1460 | ||
| 1461 | /* GRC registers */ | |
| 1462 | #define GRC_MODE 0x00006800 | |
| 1463 | #define GRC_MODE_UPD_ON_COAL 0x00000001 | |
| 1464 | #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002 | |
| 1465 | #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004 | |
| 1466 | #define GRC_MODE_BSWAP_DATA 0x00000010 | |
| 1467 | #define GRC_MODE_WSWAP_DATA 0x00000020 | |
| 1468 | #define GRC_MODE_SPLITHDR 0x00000100 | |
| 1469 | #define GRC_MODE_NOFRM_CRACKING 0x00000200 | |
| 1470 | #define GRC_MODE_INCL_CRC 0x00000400 | |
| 1471 | #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800 | |
| 1472 | #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000 | |
| 1473 | #define GRC_MODE_NOIRQ_ON_RCV 0x00004000 | |
| 1474 | #define GRC_MODE_FORCE_PCI32BIT 0x00008000 | |
| 1475 | #define GRC_MODE_HOST_STACKUP 0x00010000 | |
| 1476 | #define GRC_MODE_HOST_SENDBDS 0x00020000 | |
| 1477 | #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000 | |
| 1478 | #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000 | |
| 1479 | #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000 | |
| 1480 | #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 | |
| 1481 | #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 | |
| 1482 | #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 | |
| 1483 | #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 | |
| 1484 | #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 | |
| 1485 | #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000 | |
| 1486 | #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000 | |
| 1487 | #define GRC_MISC_CFG 0x00006804 | |
| 1488 | #define GRC_MISC_CFG_CORECLK_RESET 0x00000001 | |
| 1489 | #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe | |
| 1490 | #define GRC_MISC_CFG_PRESCALAR_SHIFT 1 | |
| 1491 | #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 | |
| 1492 | #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 | |
| 1493 | #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000 | |
| 1494 | #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 | |
| 1495 | #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000 | |
| 1496 | #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000 | |
| 1497 | #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000 | |
| 1498 | #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 | |
| 1499 | #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 | |
| 1500 | #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000 | |
| 1501 | #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000 | |
| 1502 | #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 | |
| 60189ddf | 1503 | #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000 |
| 1da177e4 LT |
1504 | #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 |
| 1505 | #define GRC_LOCAL_CTRL 0x00006808 | |
| 1506 | #define GRC_LCLCTRL_INT_ACTIVE 0x00000001 | |
| 1507 | #define GRC_LCLCTRL_CLEARINT 0x00000002 | |
| 1508 | #define GRC_LCLCTRL_SETINT 0x00000004 | |
| 1509 | #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 | |
| af36e6b6 | 1510 | #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */ |
| a4e2b347 MC |
1511 | #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */ |
| 1512 | #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */ | |
| 3e7d83bc MC |
1513 | #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020 |
| 1514 | #define GRC_LCLCTRL_GPIO_OE3 0x00000040 | |
| 1515 | #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080 | |
| 1da177e4 LT |
1516 | #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 |
| 1517 | #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 | |
| 1518 | #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 | |
| 1519 | #define GRC_LCLCTRL_GPIO_OE0 0x00000800 | |
| 1520 | #define GRC_LCLCTRL_GPIO_OE1 0x00001000 | |
| 1521 | #define GRC_LCLCTRL_GPIO_OE2 0x00002000 | |
| 1522 | #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 | |
| 1523 | #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 | |
| 1524 | #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 | |
| 1525 | #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 | |
| 1526 | #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000 | |
| 1527 | #define GRC_LCLCTRL_MEMSZ_256K 0x00000000 | |
| 1528 | #define GRC_LCLCTRL_MEMSZ_512K 0x00040000 | |
| 1529 | #define GRC_LCLCTRL_MEMSZ_1M 0x00080000 | |
| 1530 | #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000 | |
| 1531 | #define GRC_LCLCTRL_MEMSZ_4M 0x00100000 | |
| 1532 | #define GRC_LCLCTRL_MEMSZ_8M 0x00140000 | |
| 1533 | #define GRC_LCLCTRL_MEMSZ_16M 0x00180000 | |
| 1534 | #define GRC_LCLCTRL_BANK_SELECT 0x00200000 | |
| 1535 | #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000 | |
| 1536 | #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000 | |
| 1537 | #define GRC_TIMER 0x0000680c | |
| 1538 | #define GRC_RX_CPU_EVENT 0x00006810 | |
| 7c5026aa | 1539 | #define GRC_RX_CPU_DRIVER_EVENT 0x00004000 |
| 1da177e4 LT |
1540 | #define GRC_RX_TIMER_REF 0x00006814 |
| 1541 | #define GRC_RX_CPU_SEM 0x00006818 | |
| 1542 | #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c | |
| 1543 | #define GRC_TX_CPU_EVENT 0x00006820 | |
| 1544 | #define GRC_TX_TIMER_REF 0x00006824 | |
| 1545 | #define GRC_TX_CPU_SEM 0x00006828 | |
| 1546 | #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c | |
| 1547 | #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */ | |
| 1548 | #define GRC_EEPROM_ADDR 0x00006838 | |
| 1549 | #define EEPROM_ADDR_WRITE 0x00000000 | |
| 1550 | #define EEPROM_ADDR_READ 0x80000000 | |
| 1551 | #define EEPROM_ADDR_COMPLETE 0x40000000 | |
| 1552 | #define EEPROM_ADDR_FSM_RESET 0x20000000 | |
| 1553 | #define EEPROM_ADDR_DEVID_MASK 0x1c000000 | |
| 1554 | #define EEPROM_ADDR_DEVID_SHIFT 26 | |
| 1555 | #define EEPROM_ADDR_START 0x02000000 | |
| 1556 | #define EEPROM_ADDR_CLKPERD_SHIFT 16 | |
| 1557 | #define EEPROM_ADDR_ADDR_MASK 0x0000ffff | |
| 1558 | #define EEPROM_ADDR_ADDR_SHIFT 0 | |
| 1559 | #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60 | |
| 1560 | #define EEPROM_CHIP_SIZE (64 * 1024) | |
| 1561 | #define GRC_EEPROM_DATA 0x0000683c | |
| 1562 | #define GRC_EEPROM_CTRL 0x00006840 | |
| 1563 | #define GRC_MDI_CTRL 0x00006844 | |
| 1564 | #define GRC_SEEPROM_DELAY 0x00006848 | |
| b5d3772c MC |
1565 | /* 0x684c --> 0x6890 unused */ |
| 1566 | #define GRC_VCPU_EXT_CTRL 0x00006890 | |
| 1567 | #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000 | |
| 1568 | #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 | |
| d9ab5ad1 | 1569 | #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */ |
| 1da177e4 LT |
1570 | |
| 1571 | /* 0x6c00 --> 0x7000 unused */ | |
| 1572 | ||
| 1573 | /* NVRAM Control registers */ | |
| 1574 | #define NVRAM_CMD 0x00007000 | |
| 1575 | #define NVRAM_CMD_RESET 0x00000001 | |
| 1576 | #define NVRAM_CMD_DONE 0x00000008 | |
| 1577 | #define NVRAM_CMD_GO 0x00000010 | |
| 1578 | #define NVRAM_CMD_WR 0x00000020 | |
| 1579 | #define NVRAM_CMD_RD 0x00000000 | |
| 1580 | #define NVRAM_CMD_ERASE 0x00000040 | |
| 1581 | #define NVRAM_CMD_FIRST 0x00000080 | |
| 1582 | #define NVRAM_CMD_LAST 0x00000100 | |
| 1583 | #define NVRAM_CMD_WREN 0x00010000 | |
| 1584 | #define NVRAM_CMD_WRDI 0x00020000 | |
| 1585 | #define NVRAM_STAT 0x00007004 | |
| 1586 | #define NVRAM_WRDATA 0x00007008 | |
| 1587 | #define NVRAM_ADDR 0x0000700c | |
| 1588 | #define NVRAM_ADDR_MSK 0x00ffffff | |
| 1589 | #define NVRAM_RDDATA 0x00007010 | |
| 1590 | #define NVRAM_CFG1 0x00007014 | |
| 1591 | #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001 | |
| 1592 | #define NVRAM_CFG1_BUFFERED_MODE 0x00000002 | |
| 1593 | #define NVRAM_CFG1_PASS_THRU 0x00000004 | |
| 1594 | #define NVRAM_CFG1_STATUS_BITS 0x00000070 | |
| 1595 | #define NVRAM_CFG1_BIT_BANG 0x00000008 | |
| 1596 | #define NVRAM_CFG1_FLASH_SIZE 0x02000000 | |
| 1597 | #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000 | |
| 1598 | #define NVRAM_CFG1_VENDOR_MASK 0x03000003 | |
| 1599 | #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000 | |
| 1600 | #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 | |
| 1601 | #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003 | |
| 1602 | #define FLASH_VENDOR_ST 0x03000001 | |
| 1603 | #define FLASH_VENDOR_SAIFUN 0x01000003 | |
| 1604 | #define FLASH_VENDOR_SST_SMALL 0x00000001 | |
| 1605 | #define FLASH_VENDOR_SST_LARGE 0x02000001 | |
| 361b4ac2 MC |
1606 | #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003 |
| 1607 | #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000 | |
| 1608 | #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000 | |
| 1609 | #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003 | |
| 1610 | #define FLASH_5752VENDOR_ST_M45PE10 0x02400000 | |
| 1611 | #define FLASH_5752VENDOR_ST_M45PE20 0x02400002 | |
| 1612 | #define FLASH_5752VENDOR_ST_M45PE40 0x02400001 | |
| 1b27777a MC |
1613 | #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001 |
| 1614 | #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002 | |
| 1615 | #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000 | |
| d3c7b886 | 1616 | #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003 |
| 70b65a2d | 1617 | #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003 |
| d3c7b886 MC |
1618 | #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003 |
| 1619 | #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002 | |
| 1b27777a MC |
1620 | #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003 |
| 1621 | #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002 | |
| 1622 | #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000 | |
| 1623 | #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000 | |
| 6b91fa02 MC |
1624 | #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003 |
| 1625 | #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000 | |
| 1626 | #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002 | |
| 1627 | #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001 | |
| 1628 | #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003 | |
| 1629 | #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000 | |
| 1630 | #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002 | |
| 1631 | #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001 | |
| 1632 | #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001 | |
| 1633 | #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000 | |
| 1634 | #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002 | |
| 1635 | #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003 | |
| 1636 | #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001 | |
| 1637 | #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000 | |
| 1638 | #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002 | |
| 1639 | #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003 | |
| 321d32a0 MC |
1640 | #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000 |
| 1641 | #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000 | |
| 1642 | #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002 | |
| 1643 | #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 | |
| 1644 | #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 | |
| 1645 | #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 | |
| 361b4ac2 MC |
1646 | #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 |
| 1647 | #define FLASH_5752PAGE_SIZE_256 0x00000000 | |
| 1648 | #define FLASH_5752PAGE_SIZE_512 0x10000000 | |
| 1649 | #define FLASH_5752PAGE_SIZE_1K 0x20000000 | |
| 1650 | #define FLASH_5752PAGE_SIZE_2K 0x30000000 | |
| 1651 | #define FLASH_5752PAGE_SIZE_4K 0x40000000 | |
| 1652 | #define FLASH_5752PAGE_SIZE_264 0x50000000 | |
| 321d32a0 | 1653 | #define FLASH_5752PAGE_SIZE_528 0x60000000 |
| 1da177e4 LT |
1654 | #define NVRAM_CFG2 0x00007018 |
| 1655 | #define NVRAM_CFG3 0x0000701c | |
| 1656 | #define NVRAM_SWARB 0x00007020 | |
| 1657 | #define SWARB_REQ_SET0 0x00000001 | |
| 1658 | #define SWARB_REQ_SET1 0x00000002 | |
| 1659 | #define SWARB_REQ_SET2 0x00000004 | |
| 1660 | #define SWARB_REQ_SET3 0x00000008 | |
| 1661 | #define SWARB_REQ_CLR0 0x00000010 | |
| 1662 | #define SWARB_REQ_CLR1 0x00000020 | |
| 1663 | #define SWARB_REQ_CLR2 0x00000040 | |
| 1664 | #define SWARB_REQ_CLR3 0x00000080 | |
| 1665 | #define SWARB_GNT0 0x00000100 | |
| 1666 | #define SWARB_GNT1 0x00000200 | |
| 1667 | #define SWARB_GNT2 0x00000400 | |
| 1668 | #define SWARB_GNT3 0x00000800 | |
| 1669 | #define SWARB_REQ0 0x00001000 | |
| 1670 | #define SWARB_REQ1 0x00002000 | |
| 1671 | #define SWARB_REQ2 0x00004000 | |
| 1672 | #define SWARB_REQ3 0x00008000 | |
| 1673 | #define NVRAM_ACCESS 0x00007024 | |
| 1674 | #define ACCESS_ENABLE 0x00000001 | |
| 1675 | #define ACCESS_WR_ENABLE 0x00000002 | |
| 1676 | #define NVRAM_WRITE1 0x00007028 | |
| 6b91fa02 MC |
1677 | /* 0x702c unused */ |
| 1678 | ||
| 1679 | #define NVRAM_ADDR_LOCKOUT 0x00007030 | |
| b2a5c19c MC |
1680 | /* 0x7034 --> 0x7500 unused */ |
| 1681 | ||
| 1682 | #define OTP_MODE 0x00007500 | |
| 1683 | #define OTP_MODE_OTP_THRU_GRC 0x00000001 | |
| 1684 | #define OTP_CTRL 0x00007504 | |
| 1685 | #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000 | |
| 1686 | #define OTP_CTRL_OTP_CMD_READ 0x00000000 | |
| 1687 | #define OTP_CTRL_OTP_CMD_INIT 0x00000008 | |
| 1688 | #define OTP_CTRL_OTP_CMD_START 0x00000001 | |
| 1689 | #define OTP_STATUS 0x00007508 | |
| 1690 | #define OTP_STATUS_CMD_DONE 0x00000001 | |
| 1691 | #define OTP_ADDRESS 0x0000750c | |
| 1692 | #define OTP_ADDRESS_MAGIC1 0x000000a0 | |
| 1693 | #define OTP_ADDRESS_MAGIC2 0x00000080 | |
| 1694 | /* 0x7510 unused */ | |
| 1695 | ||
| 1696 | #define OTP_READ_DATA 0x00007514 | |
| 1697 | /* 0x7518 --> 0x7c04 unused */ | |
| 1da177e4 | 1698 | |
| b5d3772c MC |
1699 | #define PCIE_TRANSACTION_CFG 0x00007c04 |
| 1700 | #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000 | |
| 1701 | #define PCIE_TRANS_CFG_LOM 0x00000020 | |
| 521e6b90 | 1702 | /* 0x7c08 --> 0x7d28 unused */ |
| b5d3772c | 1703 | |
| 8ed5d97e MC |
1704 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 |
| 1705 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | |
| 33466d93 MC |
1706 | #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 |
| 1707 | #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 | |
| 255ca311 MC |
1708 | /* 0x7d2c --> 0x7d54 unused */ |
| 1709 | ||
| 1710 | #define TG3_PCIE_LNKCTL 0x00007d54 | |
| 1711 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 | |
| 1712 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 | |
| 1713 | /* 0x7d58 --> 0x7e70 unused */ | |
| 521e6b90 MC |
1714 | |
| 1715 | #define TG3_PCIE_EIDLE_DELAY 0x00007e70 | |
| 1716 | #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f | |
| 1717 | #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c | |
| 1718 | /* 0x7e74 --> 0x8000 unused */ | |
| 1da177e4 | 1719 | |
| b2a5c19c MC |
1720 | |
| 1721 | /* OTP bit definitions */ | |
| 1722 | #define TG3_OTP_AGCTGT_MASK 0x000000e0 | |
| 1723 | #define TG3_OTP_AGCTGT_SHIFT 1 | |
| 1724 | #define TG3_OTP_HPFFLTR_MASK 0x00000300 | |
| 1725 | #define TG3_OTP_HPFFLTR_SHIFT 1 | |
| 1726 | #define TG3_OTP_HPFOVER_MASK 0x00000400 | |
| 1727 | #define TG3_OTP_HPFOVER_SHIFT 1 | |
| 1728 | #define TG3_OTP_LPFDIS_MASK 0x00000800 | |
| 1729 | #define TG3_OTP_LPFDIS_SHIFT 11 | |
| 1730 | #define TG3_OTP_VDAC_MASK 0xff000000 | |
| 1731 | #define TG3_OTP_VDAC_SHIFT 24 | |
| 1732 | #define TG3_OTP_10BTAMP_MASK 0x0000f000 | |
| 1733 | #define TG3_OTP_10BTAMP_SHIFT 8 | |
| 1734 | #define TG3_OTP_ROFF_MASK 0x00e00000 | |
| 1735 | #define TG3_OTP_ROFF_SHIFT 11 | |
| 1736 | #define TG3_OTP_RCOFF_MASK 0x001c0000 | |
| 1737 | #define TG3_OTP_RCOFF_SHIFT 16 | |
| 1738 | ||
| 1739 | #define TG3_OTP_DEFAULT 0x286c1640 | |
| 1740 | ||
| a6f6cb1c MC |
1741 | /* Hardware Selfboot NVRAM layout */ |
| 1742 | #define TG3_NVM_HWSB_CFG1 0x00000004 | |
| 1743 | #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000 | |
| 1744 | #define TG3_NVM_HWSB_CFG1_MAJSFT 27 | |
| 1745 | #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000 | |
| 1746 | #define TG3_NVM_HWSB_CFG1_MINSFT 22 | |
| b2a5c19c | 1747 | |
| 1da177e4 | 1748 | #define TG3_EEPROM_MAGIC 0x669955aa |
| b16250e3 MC |
1749 | #define TG3_EEPROM_MAGIC_FW 0xa5000000 |
| 1750 | #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000 | |
| a5767dec MC |
1751 | #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000 |
| 1752 | #define TG3_EEPROM_SB_FORMAT_1 0x00200000 | |
| 1753 | #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000 | |
| 1754 | #define TG3_EEPROM_SB_REVISION_0 0x00000000 | |
| 1755 | #define TG3_EEPROM_SB_REVISION_2 0x00020000 | |
| 1756 | #define TG3_EEPROM_SB_REVISION_3 0x00030000 | |
| b16250e3 MC |
1757 | #define TG3_EEPROM_MAGIC_HW 0xabcd |
| 1758 | #define TG3_EEPROM_MAGIC_HW_MSK 0xffff | |
| 1da177e4 | 1759 | |
| 9c8a620e MC |
1760 | #define TG3_NVM_DIR_START 0x18 |
| 1761 | #define TG3_NVM_DIR_END 0x78 | |
| 1762 | #define TG3_NVM_DIRENT_SIZE 0xc | |
| 1763 | #define TG3_NVM_DIRTYPE_SHIFT 24 | |
| 1764 | #define TG3_NVM_DIRTYPE_ASFINI 1 | |
| ff3a7cb2 MC |
1765 | #define TG3_NVM_PTREV_BCVER 0x94 |
| 1766 | #define TG3_NVM_BCVER_MAJMSK 0x0000ff00 | |
| 1767 | #define TG3_NVM_BCVER_MAJSFT 8 | |
| 1768 | #define TG3_NVM_BCVER_MINMSK 0x000000ff | |
| 9c8a620e | 1769 | |
| dfe00d7d MC |
1770 | #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10 |
| 1771 | #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14 | |
| 1772 | #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 | |
| 1773 | #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18 | |
| 1774 | #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700 | |
| 1775 | #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8 | |
| 1776 | #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff | |
| 1777 | #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800 | |
| 1778 | #define TG3_EEPROM_SB_EDH_BLD_SHFT 11 | |
| 1779 | ||
| 1780 | ||
| 1da177e4 LT |
1781 | /* 32K Window into NIC internal memory */ |
| 1782 | #define NIC_SRAM_WIN_BASE 0x00008000 | |
| 1783 | ||
| 1784 | /* Offsets into first 32k of NIC internal memory. */ | |
| 1785 | #define NIC_SRAM_PAGE_ZERO 0x00000000 | |
| 1786 | #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */ | |
| 1787 | #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */ | |
| 1788 | #define NIC_SRAM_STATS_BLK 0x00000300 | |
| 1789 | #define NIC_SRAM_STATUS_BLK 0x00000b00 | |
| 1790 | ||
| 1791 | #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50 | |
| 1792 | #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 | |
| 1793 | #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */ | |
| 1794 | ||
| 1795 | #define NIC_SRAM_DATA_SIG 0x00000b54 | |
| 1796 | #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */ | |
| 1797 | ||
| 1798 | #define NIC_SRAM_DATA_CFG 0x00000b58 | |
| 1799 | #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c | |
| 1800 | #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000 | |
| 1801 | #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004 | |
| 1802 | #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008 | |
| 1803 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 | |
| 1804 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000 | |
| 1805 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010 | |
| 1806 | #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020 | |
| 1807 | #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 | |
| 1808 | #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 | |
| 1809 | #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 | |
| 1810 | #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 | |
| 1811 | #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 | |
| 1812 | #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000 | |
| 0d3031d9 | 1813 | #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000 |
| 1da177e4 LT |
1814 | |
| 1815 | #define NIC_SRAM_DATA_VER 0x00000b5c | |
| 1816 | #define NIC_SRAM_DATA_VER_SHIFT 16 | |
| 1817 | ||
| 1818 | #define NIC_SRAM_DATA_PHY_ID 0x00000b74 | |
| 1819 | #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 | |
| 1820 | #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff | |
| 1821 | ||
| 1822 | #define NIC_SRAM_FW_CMD_MBOX 0x00000b78 | |
| 1823 | #define FWCMD_NICDRV_ALIVE 0x00000001 | |
| 1824 | #define FWCMD_NICDRV_PAUSE_FW 0x00000002 | |
| 1825 | #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 | |
| 1826 | #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 | |
| 1827 | #define FWCMD_NICDRV_FIX_DMAR 0x00000005 | |
| 1828 | #define FWCMD_NICDRV_FIX_DMAW 0x00000006 | |
| 7c5026aa | 1829 | #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c |
| 28fbef78 | 1830 | #define FWCMD_NICDRV_ALIVE2 0x0000000d |
| 130b8e4d | 1831 | #define FWCMD_NICDRV_ALIVE3 0x0000000e |
| 1da177e4 LT |
1832 | #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c |
| 1833 | #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 | |
| 1834 | #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 | |
| 1835 | #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 | |
| 1836 | #define DRV_STATE_START 0x00000001 | |
| 1837 | #define DRV_STATE_START_DONE 0x80000001 | |
| 1838 | #define DRV_STATE_UNLOAD 0x00000002 | |
| 1839 | #define DRV_STATE_UNLOAD_DONE 0x80000002 | |
| 1840 | #define DRV_STATE_WOL 0x00000003 | |
| 1841 | #define DRV_STATE_SUSPEND 0x00000004 | |
| 1842 | ||
| 1843 | #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 | |
| 1844 | ||
| 1845 | #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 | |
| 1846 | #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 | |
| 1847 | ||
| 6921d201 MC |
1848 | #define NIC_SRAM_WOL_MBOX 0x00000d30 |
| 1849 | #define WOL_SIGNATURE 0x474c0000 | |
| 1850 | #define WOL_DRV_STATE_SHUTDOWN 0x00000001 | |
| 1851 | #define WOL_DRV_WOL 0x00000002 | |
| 1852 | #define WOL_SET_MAGIC_PKT 0x00000004 | |
| 1853 | ||
| 1da177e4 LT |
1854 | #define NIC_SRAM_DATA_CFG_2 0x00000d38 |
| 1855 | ||
| 6833c043 | 1856 | #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400 |
| 1da177e4 LT |
1857 | #define SHASTA_EXT_LED_MODE_MASK 0x00018000 |
| 1858 | #define SHASTA_EXT_LED_LEGACY 0x00000000 | |
| 1859 | #define SHASTA_EXT_LED_SHARED 0x00008000 | |
| 1860 | #define SHASTA_EXT_LED_MAC 0x00010000 | |
| 1861 | #define SHASTA_EXT_LED_COMBO 0x00018000 | |
| 1862 | ||
| 8ed5d97e MC |
1863 | #define NIC_SRAM_DATA_CFG_3 0x00000d3c |
| 1864 | #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002 | |
| 1865 | ||
| a9daf367 MC |
1866 | #define NIC_SRAM_DATA_CFG_4 0x00000d60 |
| 1867 | #define NIC_SRAM_GMII_MODE 0x00000002 | |
| 1868 | #define NIC_SRAM_RGMII_STD_IBND_DISABLE 0x00000004 | |
| 1869 | #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008 | |
| 1870 | #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010 | |
| 1871 | ||
| 1da177e4 LT |
1872 | #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 |
| 1873 | ||
| 1874 | #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 | |
| 1875 | #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 | |
| 1876 | #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */ | |
| 1877 | #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */ | |
| 1878 | #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */ | |
| 1879 | #define NIC_SRAM_MBUF_POOL_BASE 0x00008000 | |
| 1880 | #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 | |
| 1881 | #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 | |
| 1882 | #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 | |
| 1883 | #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 | |
| 1884 | ||
| 1885 | /* Currently this is fixed. */ | |
| 1886 | #define PHY_ADDR 0x01 | |
| 1887 | ||
| 1888 | /* Tigon3 specific PHY MII registers. */ | |
| 1889 | #define TG3_BMCR_SPEED1000 0x0040 | |
| 1890 | ||
| 1891 | #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */ | |
| 1892 | #define MII_TG3_CTRL_ADV_1000_HALF 0x0100 | |
| 1893 | #define MII_TG3_CTRL_ADV_1000_FULL 0x0200 | |
| 1894 | #define MII_TG3_CTRL_AS_MASTER 0x0800 | |
| 1895 | #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 | |
| 1896 | ||
| 1897 | #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */ | |
| 1898 | #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001 | |
| 1899 | #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 | |
| 6921d201 | 1900 | #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008 |
| 1da177e4 LT |
1901 | #define MII_TG3_EXT_CTRL_TBI 0x8000 |
| 1902 | ||
| 1903 | #define MII_TG3_EXT_STAT 0x11 /* Extended status register */ | |
| 1904 | #define MII_TG3_EXT_STAT_LPASS 0x0100 | |
| 1905 | ||
| 1906 | #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ | |
| 1907 | ||
| 715116a1 | 1908 | #define MII_TG3_EPHY_PTEST 0x17 /* 5906 PHY register */ |
| b2a5c19c MC |
1909 | #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ |
| 1910 | ||
| 1911 | #define MII_TG3_DSP_TAP1 0x0001 | |
| 1912 | #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007 | |
| 1913 | #define MII_TG3_DSP_AADJ1CH0 0x001f | |
| 1914 | #define MII_TG3_DSP_AADJ1CH3 0x601f | |
| 1915 | #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 | |
| 1916 | #define MII_TG3_DSP_EXP8 0x0708 | |
| 1917 | #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 | |
| 1918 | #define MII_TG3_DSP_EXP8_AEDW 0x0200 | |
| 1919 | #define MII_TG3_DSP_EXP75 0x0f75 | |
| 1920 | #define MII_TG3_DSP_EXP96 0x0f96 | |
| 1921 | #define MII_TG3_DSP_EXP97 0x0f97 | |
| 1da177e4 LT |
1922 | |
| 1923 | #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */ | |
| 1924 | ||
| 0a459aac MC |
1925 | #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010 |
| 1926 | #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020 | |
| 1927 | #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180 | |
| 1928 | #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002 | |
| 1929 | ||
| 9ef8ca99 MC |
1930 | #define MII_TG3_AUXCTL_MISC_WREN 0x8000 |
| 1931 | #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200 | |
| 1932 | #define MII_TG3_AUXCTL_MISC_RDSEL_MISC 0x7000 | |
| b2a5c19c MC |
1933 | #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007 |
| 1934 | ||
| 1935 | #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800 | |
| 1936 | #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400 | |
| 1937 | #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000 | |
| 9ef8ca99 | 1938 | |
| 1da177e4 LT |
1939 | #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */ |
| 1940 | #define MII_TG3_AUX_STAT_LPASS 0x0004 | |
| 1941 | #define MII_TG3_AUX_STAT_SPDMASK 0x0700 | |
| 1942 | #define MII_TG3_AUX_STAT_10HALF 0x0100 | |
| 1943 | #define MII_TG3_AUX_STAT_10FULL 0x0200 | |
| 1944 | #define MII_TG3_AUX_STAT_100HALF 0x0300 | |
| 1945 | #define MII_TG3_AUX_STAT_100_4 0x0400 | |
| 1946 | #define MII_TG3_AUX_STAT_100FULL 0x0500 | |
| 1947 | #define MII_TG3_AUX_STAT_1000HALF 0x0600 | |
| 1948 | #define MII_TG3_AUX_STAT_1000FULL 0x0700 | |
| 715116a1 MC |
1949 | #define MII_TG3_AUX_STAT_100 0x0008 |
| 1950 | #define MII_TG3_AUX_STAT_FULL 0x0001 | |
| 1da177e4 LT |
1951 | |
| 1952 | #define MII_TG3_ISTAT 0x1a /* IRQ status register */ | |
| 1953 | #define MII_TG3_IMASK 0x1b /* IRQ mask register */ | |
| 1954 | ||
| 1955 | /* ISTAT/IMASK event bits */ | |
| 1956 | #define MII_TG3_INT_LINKCHG 0x0002 | |
| 1957 | #define MII_TG3_INT_SPEEDCHG 0x0004 | |
| 1958 | #define MII_TG3_INT_DUPLEXCHG 0x0008 | |
| 1959 | #define MII_TG3_INT_ANEG_PAGE_RX 0x0400 | |
| 1960 | ||
| b2a5c19c MC |
1961 | #define MII_TG3_MISC_SHDW 0x1c |
| 1962 | #define MII_TG3_MISC_SHDW_WREN 0x8000 | |
| aa10f27d MC |
1963 | |
| 1964 | #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001 | |
| 1965 | #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020 | |
| b2a5c19c MC |
1966 | #define MII_TG3_MISC_SHDW_APD_SEL 0x2800 |
| 1967 | ||
| 1968 | #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001 | |
| 1969 | #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002 | |
| 1970 | #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004 | |
| 1971 | #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008 | |
| 1972 | #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010 | |
| aa10f27d | 1973 | #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400 |
| b2a5c19c | 1974 | |
| b2a5c19c | 1975 | |
| 715116a1 MC |
1976 | #define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ |
| 1977 | #define MII_TG3_EPHY_SHADOW_EN 0x80 | |
| 1978 | ||
| 9ef8ca99 MC |
1979 | #define MII_TG3_EPHYTST_MISCCTRL 0x10 /* 5906 EPHY misc ctrl shadow register */ |
| 1980 | #define MII_TG3_EPHYTST_MISCCTRL_MDIX 0x4000 | |
| 1981 | ||
| c1d2a196 MC |
1982 | #define MII_TG3_TEST1 0x1e |
| 1983 | #define MII_TG3_TEST1_TRIM_EN 0x0010 | |
| 569a5df8 | 1984 | #define MII_TG3_TEST1_CRC_EN 0x8000 |
| c1d2a196 | 1985 | |
| 0d3031d9 MC |
1986 | /* APE registers. Accessible through BAR1 */ |
| 1987 | #define TG3_APE_EVENT 0x000c | |
| 1988 | #define APE_EVENT_1 0x00000001 | |
| 1989 | #define TG3_APE_LOCK_REQ 0x002c | |
| 1990 | #define APE_LOCK_REQ_DRIVER 0x00001000 | |
| 1991 | #define TG3_APE_LOCK_GRANT 0x004c | |
| 1992 | #define APE_LOCK_GRANT_DRIVER 0x00001000 | |
| 1993 | #define TG3_APE_SEG_SIG 0x4000 | |
| 1994 | #define APE_SEG_SIG_MAGIC 0x41504521 | |
| 1995 | ||
| 1996 | /* APE shared memory. Accessible through BAR1 */ | |
| 1997 | #define TG3_APE_FW_STATUS 0x400c | |
| 1998 | #define APE_FW_STATUS_READY 0x00000100 | |
| 7fd76445 MC |
1999 | #define TG3_APE_FW_VERSION 0x4018 |
| 2000 | #define APE_FW_VERSION_MAJMSK 0xff000000 | |
| 2001 | #define APE_FW_VERSION_MAJSFT 24 | |
| 2002 | #define APE_FW_VERSION_MINMSK 0x00ff0000 | |
| 2003 | #define APE_FW_VERSION_MINSFT 16 | |
| 2004 | #define APE_FW_VERSION_REVMSK 0x0000ff00 | |
| 2005 | #define APE_FW_VERSION_REVSFT 8 | |
| 2006 | #define APE_FW_VERSION_BLDMSK 0x000000ff | |
| 0d3031d9 MC |
2007 | #define TG3_APE_HOST_SEG_SIG 0x4200 |
| 2008 | #define APE_HOST_SEG_SIG_MAGIC 0x484f5354 | |
| 2009 | #define TG3_APE_HOST_SEG_LEN 0x4204 | |
| 2010 | #define APE_HOST_SEG_LEN_MAGIC 0x0000001c | |
| 2011 | #define TG3_APE_HOST_INIT_COUNT 0x4208 | |
| 2012 | #define TG3_APE_HOST_DRIVER_ID 0x420c | |
| 2013 | #define APE_HOST_DRIVER_ID_MAGIC 0xf0035100 | |
| 2014 | #define TG3_APE_HOST_BEHAVIOR 0x4210 | |
| 2015 | #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 | |
| 2016 | #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214 | |
| 2017 | #define APE_HOST_HEARTBEAT_INT_DISABLE 0 | |
| 2018 | #define APE_HOST_HEARTBEAT_INT_5SEC 5000 | |
| 2019 | #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218 | |
| 2020 | ||
| 2021 | #define TG3_APE_EVENT_STATUS 0x4300 | |
| 2022 | ||
| 2023 | #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 | |
| 2024 | #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500 | |
| 2025 | #define APE_EVENT_STATUS_STATE_START 0x00010000 | |
| 2026 | #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 | |
| 2027 | #define APE_EVENT_STATUS_STATE_WOL 0x00030000 | |
| 2028 | #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 | |
| 2029 | #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000 | |
| 2030 | ||
| 2031 | /* APE convenience enumerations. */ | |
| 77b483f1 | 2032 | #define TG3_APE_LOCK_GRC 1 |
| 0d3031d9 MC |
2033 | #define TG3_APE_LOCK_MEM 4 |
| 2034 | ||
| a5767dec MC |
2035 | #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10 |
| 2036 | ||
| 0d3031d9 | 2037 | |
| 1da177e4 LT |
2038 | /* There are two ways to manage the TX descriptors on the tigon3. |
| 2039 | * Either the descriptors are in host DMA'able memory, or they | |
| 2040 | * exist only in the cards on-chip SRAM. All 16 send bds are under | |
| 2041 | * the same mode, they may not be configured individually. | |
| 2042 | * | |
| 2043 | * This driver always uses host memory TX descriptors. | |
| 2044 | * | |
| 2045 | * To use host memory TX descriptors: | |
| 2046 | * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register. | |
| 2047 | * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear. | |
| 2048 | * 2) Allocate DMA'able memory. | |
| 2049 | * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: | |
| 2050 | * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory | |
| 2051 | * obtained in step 2 | |
| 2052 | * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC. | |
| 2053 | * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number | |
| 2054 | * of TX descriptors. Leave flags field clear. | |
| 2055 | * 4) Access TX descriptors via host memory. The chip | |
| 2056 | * will refetch into local SRAM as needed when producer | |
| 2057 | * index mailboxes are updated. | |
| 2058 | * | |
| 2059 | * To use on-chip TX descriptors: | |
| 2060 | * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register. | |
| 2061 | * Make sure GRC_MODE_HOST_SENDBDS is clear. | |
| 2062 | * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM: | |
| 2063 | * a) Set TG3_BDINFO_HOST_ADDR to zero. | |
| 2064 | * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC | |
| 2065 | * c) TG3_BDINFO_MAXLEN_FLAGS is don't care. | |
| 2066 | * 3) Access TX descriptors directly in on-chip SRAM | |
| 2067 | * using normal {read,write}l(). (and not using | |
| 2068 | * pointer dereferencing of ioremap()'d memory like | |
| 2069 | * the broken Broadcom driver does) | |
| 2070 | * | |
| 2071 | * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of | |
| 2072 | * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices. | |
| 2073 | */ | |
| 2074 | struct tg3_tx_buffer_desc { | |
| 2075 | u32 addr_hi; | |
| 2076 | u32 addr_lo; | |
| 2077 | ||
| 2078 | u32 len_flags; | |
| 2079 | #define TXD_FLAG_TCPUDP_CSUM 0x0001 | |
| 2080 | #define TXD_FLAG_IP_CSUM 0x0002 | |
| 2081 | #define TXD_FLAG_END 0x0004 | |
| 2082 | #define TXD_FLAG_IP_FRAG 0x0008 | |
| 2083 | #define TXD_FLAG_IP_FRAG_END 0x0010 | |
| 2084 | #define TXD_FLAG_VLAN 0x0040 | |
| 2085 | #define TXD_FLAG_COAL_NOW 0x0080 | |
| 2086 | #define TXD_FLAG_CPU_PRE_DMA 0x0100 | |
| 2087 | #define TXD_FLAG_CPU_POST_DMA 0x0200 | |
| 2088 | #define TXD_FLAG_ADD_SRC_ADDR 0x1000 | |
| 2089 | #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000 | |
| 2090 | #define TXD_FLAG_NO_CRC 0x8000 | |
| 2091 | #define TXD_LEN_SHIFT 16 | |
| 2092 | ||
| 2093 | u32 vlan_tag; | |
| 2094 | #define TXD_VLAN_TAG_SHIFT 0 | |
| 2095 | #define TXD_MSS_SHIFT 16 | |
| 2096 | }; | |
| 2097 | ||
| 2098 | #define TXD_ADDR 0x00UL /* 64-bit */ | |
| 2099 | #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */ | |
| 2100 | #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */ | |
| 2101 | #define TXD_SIZE 0x10UL | |
| 2102 | ||
| 2103 | struct tg3_rx_buffer_desc { | |
| 2104 | u32 addr_hi; | |
| 2105 | u32 addr_lo; | |
| 2106 | ||
| 2107 | u32 idx_len; | |
| 2108 | #define RXD_IDX_MASK 0xffff0000 | |
| 2109 | #define RXD_IDX_SHIFT 16 | |
| 2110 | #define RXD_LEN_MASK 0x0000ffff | |
| 2111 | #define RXD_LEN_SHIFT 0 | |
| 2112 | ||
| 2113 | u32 type_flags; | |
| 2114 | #define RXD_TYPE_SHIFT 16 | |
| 2115 | #define RXD_FLAGS_SHIFT 0 | |
| 2116 | ||
| 2117 | #define RXD_FLAG_END 0x0004 | |
| 2118 | #define RXD_FLAG_MINI 0x0800 | |
| 2119 | #define RXD_FLAG_JUMBO 0x0020 | |
| 2120 | #define RXD_FLAG_VLAN 0x0040 | |
| 2121 | #define RXD_FLAG_ERROR 0x0400 | |
| 2122 | #define RXD_FLAG_IP_CSUM 0x1000 | |
| 2123 | #define RXD_FLAG_TCPUDP_CSUM 0x2000 | |
| 2124 | #define RXD_FLAG_IS_TCP 0x4000 | |
| 2125 | ||
| 2126 | u32 ip_tcp_csum; | |
| 2127 | #define RXD_IPCSUM_MASK 0xffff0000 | |
| 2128 | #define RXD_IPCSUM_SHIFT 16 | |
| 2129 | #define RXD_TCPCSUM_MASK 0x0000ffff | |
| 2130 | #define RXD_TCPCSUM_SHIFT 0 | |
| 2131 | ||
| 2132 | u32 err_vlan; | |
| 2133 | ||
| 2134 | #define RXD_VLAN_MASK 0x0000ffff | |
| 2135 | ||
| 2136 | #define RXD_ERR_BAD_CRC 0x00010000 | |
| 2137 | #define RXD_ERR_COLLISION 0x00020000 | |
| 2138 | #define RXD_ERR_LINK_LOST 0x00040000 | |
| 2139 | #define RXD_ERR_PHY_DECODE 0x00080000 | |
| 2140 | #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000 | |
| 2141 | #define RXD_ERR_MAC_ABRT 0x00200000 | |
| 2142 | #define RXD_ERR_TOO_SMALL 0x00400000 | |
| 2143 | #define RXD_ERR_NO_RESOURCES 0x00800000 | |
| 2144 | #define RXD_ERR_HUGE_FRAME 0x01000000 | |
| 2145 | #define RXD_ERR_MASK 0xffff0000 | |
| 2146 | ||
| 2147 | u32 reserved; | |
| 2148 | u32 opaque; | |
| 2149 | #define RXD_OPAQUE_INDEX_MASK 0x0000ffff | |
| 2150 | #define RXD_OPAQUE_INDEX_SHIFT 0 | |
| 2151 | #define RXD_OPAQUE_RING_STD 0x00010000 | |
| 2152 | #define RXD_OPAQUE_RING_JUMBO 0x00020000 | |
| 2153 | #define RXD_OPAQUE_RING_MINI 0x00040000 | |
| 2154 | #define RXD_OPAQUE_RING_MASK 0x00070000 | |
| 2155 | }; | |
| 2156 | ||
| 2157 | struct tg3_ext_rx_buffer_desc { | |
| 2158 | struct { | |
| 2159 | u32 addr_hi; | |
| 2160 | u32 addr_lo; | |
| 2161 | } addrlist[3]; | |
| 2162 | u32 len2_len1; | |
| 2163 | u32 resv_len3; | |
| 2164 | struct tg3_rx_buffer_desc std; | |
| 2165 | }; | |
| 2166 | ||
| 2167 | /* We only use this when testing out the DMA engine | |
| 2168 | * at probe time. This is the internal format of buffer | |
| 2169 | * descriptors used by the chip at NIC_SRAM_DMA_DESCS. | |
| 2170 | */ | |
| 2171 | struct tg3_internal_buffer_desc { | |
| 2172 | u32 addr_hi; | |
| 2173 | u32 addr_lo; | |
| 2174 | u32 nic_mbuf; | |
| 2175 | /* XXX FIX THIS */ | |
| 2176 | #ifdef __BIG_ENDIAN | |
| 2177 | u16 cqid_sqid; | |
| 2178 | u16 len; | |
| 2179 | #else | |
| 2180 | u16 len; | |
| 2181 | u16 cqid_sqid; | |
| 2182 | #endif | |
| 2183 | u32 flags; | |
| 2184 | u32 __cookie1; | |
| 2185 | u32 __cookie2; | |
| 2186 | u32 __cookie3; | |
| 2187 | }; | |
| 2188 | ||
| 2189 | #define TG3_HW_STATUS_SIZE 0x50 | |
| 2190 | struct tg3_hw_status { | |
| 2191 | u32 status; | |
| 2192 | #define SD_STATUS_UPDATED 0x00000001 | |
| 2193 | #define SD_STATUS_LINK_CHG 0x00000002 | |
| 2194 | #define SD_STATUS_ERROR 0x00000004 | |
| 2195 | ||
| 2196 | u32 status_tag; | |
| 2197 | ||
| 2198 | #ifdef __BIG_ENDIAN | |
| 2199 | u16 rx_consumer; | |
| 2200 | u16 rx_jumbo_consumer; | |
| 2201 | #else | |
| 2202 | u16 rx_jumbo_consumer; | |
| 2203 | u16 rx_consumer; | |
| 2204 | #endif | |
| 2205 | ||
| 2206 | #ifdef __BIG_ENDIAN | |
| 2207 | u16 reserved; | |
| 2208 | u16 rx_mini_consumer; | |
| 2209 | #else | |
| 2210 | u16 rx_mini_consumer; | |
| 2211 | u16 reserved; | |
| 2212 | #endif | |
| 2213 | struct { | |
| 2214 | #ifdef __BIG_ENDIAN | |
| 2215 | u16 tx_consumer; | |
| 2216 | u16 rx_producer; | |
| 2217 | #else | |
| 2218 | u16 rx_producer; | |
| 2219 | u16 tx_consumer; | |
| 2220 | #endif | |
| 2221 | } idx[16]; | |
| 2222 | }; | |
| 2223 | ||
| 2224 | typedef struct { | |
| 2225 | u32 high, low; | |
| 2226 | } tg3_stat64_t; | |
| 2227 | ||
| 2228 | struct tg3_hw_stats { | |
| 2229 | u8 __reserved0[0x400-0x300]; | |
| 2230 | ||
| 2231 | /* Statistics maintained by Receive MAC. */ | |
| 2232 | tg3_stat64_t rx_octets; | |
| 2233 | u64 __reserved1; | |
| 2234 | tg3_stat64_t rx_fragments; | |
| 2235 | tg3_stat64_t rx_ucast_packets; | |
| 2236 | tg3_stat64_t rx_mcast_packets; | |
| 2237 | tg3_stat64_t rx_bcast_packets; | |
| 2238 | tg3_stat64_t rx_fcs_errors; | |
| 2239 | tg3_stat64_t rx_align_errors; | |
| 2240 | tg3_stat64_t rx_xon_pause_rcvd; | |
| 2241 | tg3_stat64_t rx_xoff_pause_rcvd; | |
| 2242 | tg3_stat64_t rx_mac_ctrl_rcvd; | |
| 2243 | tg3_stat64_t rx_xoff_entered; | |
| 2244 | tg3_stat64_t rx_frame_too_long_errors; | |
| 2245 | tg3_stat64_t rx_jabbers; | |
| 2246 | tg3_stat64_t rx_undersize_packets; | |
| 2247 | tg3_stat64_t rx_in_length_errors; | |
| 2248 | tg3_stat64_t rx_out_length_errors; | |
| 2249 | tg3_stat64_t rx_64_or_less_octet_packets; | |
| 2250 | tg3_stat64_t rx_65_to_127_octet_packets; | |
| 2251 | tg3_stat64_t rx_128_to_255_octet_packets; | |
| 2252 | tg3_stat64_t rx_256_to_511_octet_packets; | |
| 2253 | tg3_stat64_t rx_512_to_1023_octet_packets; | |
| 2254 | tg3_stat64_t rx_1024_to_1522_octet_packets; | |
| 2255 | tg3_stat64_t rx_1523_to_2047_octet_packets; | |
| 2256 | tg3_stat64_t rx_2048_to_4095_octet_packets; | |
| 2257 | tg3_stat64_t rx_4096_to_8191_octet_packets; | |
| 2258 | tg3_stat64_t rx_8192_to_9022_octet_packets; | |
| 2259 | ||
| 2260 | u64 __unused0[37]; | |
| 2261 | ||
| 2262 | /* Statistics maintained by Transmit MAC. */ | |
| 2263 | tg3_stat64_t tx_octets; | |
| 2264 | u64 __reserved2; | |
| 2265 | tg3_stat64_t tx_collisions; | |
| 2266 | tg3_stat64_t tx_xon_sent; | |
| 2267 | tg3_stat64_t tx_xoff_sent; | |
| 2268 | tg3_stat64_t tx_flow_control; | |
| 2269 | tg3_stat64_t tx_mac_errors; | |
| 2270 | tg3_stat64_t tx_single_collisions; | |
| 2271 | tg3_stat64_t tx_mult_collisions; | |
| 2272 | tg3_stat64_t tx_deferred; | |
| 2273 | u64 __reserved3; | |
| 2274 | tg3_stat64_t tx_excessive_collisions; | |
| 2275 | tg3_stat64_t tx_late_collisions; | |
| 2276 | tg3_stat64_t tx_collide_2times; | |
| 2277 | tg3_stat64_t tx_collide_3times; | |
| 2278 | tg3_stat64_t tx_collide_4times; | |
| 2279 | tg3_stat64_t tx_collide_5times; | |
| 2280 | tg3_stat64_t tx_collide_6times; | |
| 2281 | tg3_stat64_t tx_collide_7times; | |
| 2282 | tg3_stat64_t tx_collide_8times; | |
| 2283 | tg3_stat64_t tx_collide_9times; | |
| 2284 | tg3_stat64_t tx_collide_10times; | |
| 2285 | tg3_stat64_t tx_collide_11times; | |
| 2286 | tg3_stat64_t tx_collide_12times; | |
| 2287 | tg3_stat64_t tx_collide_13times; | |
| 2288 | tg3_stat64_t tx_collide_14times; | |
| 2289 | tg3_stat64_t tx_collide_15times; | |
| 2290 | tg3_stat64_t tx_ucast_packets; | |
| 2291 | tg3_stat64_t tx_mcast_packets; | |
| 2292 | tg3_stat64_t tx_bcast_packets; | |
| 2293 | tg3_stat64_t tx_carrier_sense_errors; | |
| 2294 | tg3_stat64_t tx_discards; | |
| 2295 | tg3_stat64_t tx_errors; | |
| 2296 | ||
| 2297 | u64 __unused1[31]; | |
| 2298 | ||
| 2299 | /* Statistics maintained by Receive List Placement. */ | |
| 2300 | tg3_stat64_t COS_rx_packets[16]; | |
| 2301 | tg3_stat64_t COS_rx_filter_dropped; | |
| 2302 | tg3_stat64_t dma_writeq_full; | |
| 2303 | tg3_stat64_t dma_write_prioq_full; | |
| 2304 | tg3_stat64_t rxbds_empty; | |
| 2305 | tg3_stat64_t rx_discards; | |
| 2306 | tg3_stat64_t rx_errors; | |
| 2307 | tg3_stat64_t rx_threshold_hit; | |
| 2308 | ||
| 2309 | u64 __unused2[9]; | |
| 2310 | ||
| 2311 | /* Statistics maintained by Send Data Initiator. */ | |
| 2312 | tg3_stat64_t COS_out_packets[16]; | |
| 2313 | tg3_stat64_t dma_readq_full; | |
| 2314 | tg3_stat64_t dma_read_prioq_full; | |
| 2315 | tg3_stat64_t tx_comp_queue_full; | |
| 2316 | ||
| 2317 | /* Statistics maintained by Host Coalescing. */ | |
| 2318 | tg3_stat64_t ring_set_send_prod_index; | |
| 2319 | tg3_stat64_t ring_status_update; | |
| 2320 | tg3_stat64_t nic_irqs; | |
| 2321 | tg3_stat64_t nic_avoided_irqs; | |
| 2322 | tg3_stat64_t nic_tx_threshold_hit; | |
| 2323 | ||
| 2324 | u8 __reserved4[0xb00-0x9c0]; | |
| 2325 | }; | |
| 2326 | ||
| 2327 | /* 'mapping' is superfluous as the chip does not write into | |
| 2328 | * the tx/rx post rings so we could just fetch it from there. | |
| 2329 | * But the cache behavior is better how we are doing it now. | |
| 2330 | */ | |
| 2331 | struct ring_info { | |
| 2332 | struct sk_buff *skb; | |
| 2333 | DECLARE_PCI_UNMAP_ADDR(mapping) | |
| 2334 | }; | |
| 2335 | ||
| 2336 | struct tx_ring_info { | |
| 2337 | struct sk_buff *skb; | |
| 1da177e4 LT |
2338 | u32 prev_vlan_tag; |
| 2339 | }; | |
| 2340 | ||
| 2341 | struct tg3_config_info { | |
| 2342 | u32 flags; | |
| 2343 | }; | |
| 2344 | ||
| 2345 | struct tg3_link_config { | |
| 2346 | /* Describes what we're trying to get. */ | |
| 2347 | u32 advertising; | |
| 2348 | u16 speed; | |
| 2349 | u8 duplex; | |
| 2350 | u8 autoneg; | |
| 8d018621 | 2351 | u8 flowctrl; |
| 1da177e4 LT |
2352 | |
| 2353 | /* Describes what we actually have. */ | |
| 8d018621 MC |
2354 | u8 active_flowctrl; |
| 2355 | ||
| 1da177e4 LT |
2356 | u8 active_duplex; |
| 2357 | #define SPEED_INVALID 0xffff | |
| 2358 | #define DUPLEX_INVALID 0xff | |
| 2359 | #define AUTONEG_INVALID 0xff | |
| 8d018621 | 2360 | u16 active_speed; |
| 1da177e4 LT |
2361 | |
| 2362 | /* When we go in and out of low power mode we need | |
| 2363 | * to swap with this state. | |
| 2364 | */ | |
| 2365 | int phy_is_low_power; | |
| 2366 | u16 orig_speed; | |
| 2367 | u8 orig_duplex; | |
| 2368 | u8 orig_autoneg; | |
| b02fd9e3 | 2369 | u32 orig_advertising; |
| 1da177e4 LT |
2370 | }; |
| 2371 | ||
| 2372 | struct tg3_bufmgr_config { | |
| 2373 | u32 mbuf_read_dma_low_water; | |
| 2374 | u32 mbuf_mac_rx_low_water; | |
| 2375 | u32 mbuf_high_water; | |
| 2376 | ||
| 2377 | u32 mbuf_read_dma_low_water_jumbo; | |
| 2378 | u32 mbuf_mac_rx_low_water_jumbo; | |
| 2379 | u32 mbuf_high_water_jumbo; | |
| 2380 | ||
| 2381 | u32 dma_low_water; | |
| 2382 | u32 dma_high_water; | |
| 2383 | }; | |
| 2384 | ||
| 2385 | struct tg3_ethtool_stats { | |
| 2386 | /* Statistics maintained by Receive MAC. */ | |
| 2387 | u64 rx_octets; | |
| 2388 | u64 rx_fragments; | |
| 2389 | u64 rx_ucast_packets; | |
| 2390 | u64 rx_mcast_packets; | |
| 2391 | u64 rx_bcast_packets; | |
| 2392 | u64 rx_fcs_errors; | |
| 2393 | u64 rx_align_errors; | |
| 2394 | u64 rx_xon_pause_rcvd; | |
| 2395 | u64 rx_xoff_pause_rcvd; | |
| 2396 | u64 rx_mac_ctrl_rcvd; | |
| 2397 | u64 rx_xoff_entered; | |
| 2398 | u64 rx_frame_too_long_errors; | |
| 2399 | u64 rx_jabbers; | |
| 2400 | u64 rx_undersize_packets; | |
| 2401 | u64 rx_in_length_errors; | |
| 2402 | u64 rx_out_length_errors; | |
| 2403 | u64 rx_64_or_less_octet_packets; | |
| 2404 | u64 rx_65_to_127_octet_packets; | |
| 2405 | u64 rx_128_to_255_octet_packets; | |
| 2406 | u64 rx_256_to_511_octet_packets; | |
| 2407 | u64 rx_512_to_1023_octet_packets; | |
| 2408 | u64 rx_1024_to_1522_octet_packets; | |
| 2409 | u64 rx_1523_to_2047_octet_packets; | |
| 2410 | u64 rx_2048_to_4095_octet_packets; | |
| 2411 | u64 rx_4096_to_8191_octet_packets; | |
| 2412 | u64 rx_8192_to_9022_octet_packets; | |
| 2413 | ||
| 2414 | /* Statistics maintained by Transmit MAC. */ | |
| 2415 | u64 tx_octets; | |
| 2416 | u64 tx_collisions; | |
| 2417 | u64 tx_xon_sent; | |
| 2418 | u64 tx_xoff_sent; | |
| 2419 | u64 tx_flow_control; | |
| 2420 | u64 tx_mac_errors; | |
| 2421 | u64 tx_single_collisions; | |
| 2422 | u64 tx_mult_collisions; | |
| 2423 | u64 tx_deferred; | |
| 2424 | u64 tx_excessive_collisions; | |
| 2425 | u64 tx_late_collisions; | |
| 2426 | u64 tx_collide_2times; | |
| 2427 | u64 tx_collide_3times; | |
| 2428 | u64 tx_collide_4times; | |
| 2429 | u64 tx_collide_5times; | |
| 2430 | u64 tx_collide_6times; | |
| 2431 | u64 tx_collide_7times; | |
| 2432 | u64 tx_collide_8times; | |
| 2433 | u64 tx_collide_9times; | |
| 2434 | u64 tx_collide_10times; | |
| 2435 | u64 tx_collide_11times; | |
| 2436 | u64 tx_collide_12times; | |
| 2437 | u64 tx_collide_13times; | |
| 2438 | u64 tx_collide_14times; | |
| 2439 | u64 tx_collide_15times; | |
| 2440 | u64 tx_ucast_packets; | |
| 2441 | u64 tx_mcast_packets; | |
| 2442 | u64 tx_bcast_packets; | |
| 2443 | u64 tx_carrier_sense_errors; | |
| 2444 | u64 tx_discards; | |
| 2445 | u64 tx_errors; | |
| 2446 | ||
| 2447 | /* Statistics maintained by Receive List Placement. */ | |
| 2448 | u64 dma_writeq_full; | |
| 2449 | u64 dma_write_prioq_full; | |
| 2450 | u64 rxbds_empty; | |
| 2451 | u64 rx_discards; | |
| 2452 | u64 rx_errors; | |
| 2453 | u64 rx_threshold_hit; | |
| 2454 | ||
| 2455 | /* Statistics maintained by Send Data Initiator. */ | |
| 2456 | u64 dma_readq_full; | |
| 2457 | u64 dma_read_prioq_full; | |
| 2458 | u64 tx_comp_queue_full; | |
| 2459 | ||
| 2460 | /* Statistics maintained by Host Coalescing. */ | |
| 2461 | u64 ring_set_send_prod_index; | |
| 2462 | u64 ring_status_update; | |
| 2463 | u64 nic_irqs; | |
| 2464 | u64 nic_avoided_irqs; | |
| 2465 | u64 nic_tx_threshold_hit; | |
| 2466 | }; | |
| 2467 | ||
| 2468 | struct tg3 { | |
| 2469 | /* begin "general, frequently-used members" cacheline section */ | |
| 2470 | ||
| f47c11ee DM |
2471 | /* If the IRQ handler (which runs lockless) needs to be |
| 2472 | * quiesced, the following bitmask state is used. The | |
| 2473 | * SYNC flag is set by non-IRQ context code to initiate | |
| 2474 | * the quiescence. | |
| 2475 | * | |
| 2476 | * When the IRQ handler notices that SYNC is set, it | |
| 2477 | * disables interrupts and returns. | |
| 2478 | * | |
| 2479 | * When all outstanding IRQ handlers have returned after | |
| 2480 | * the SYNC flag has been set, the setter can be assured | |
| 2481 | * that interrupts will no longer get run. | |
| 2482 | * | |
| 2483 | * In this way all SMP driver locks are never acquired | |
| 2484 | * in hw IRQ context, only sw IRQ context or lower. | |
| 2485 | */ | |
| 2486 | unsigned int irq_sync; | |
| 2487 | ||
| 1da177e4 LT |
2488 | /* SMP locking strategy: |
| 2489 | * | |
| 00b70504 MC |
2490 | * lock: Held during reset, PHY access, timer, and when |
| 2491 | * updating tg3_flags and tg3_flags2. | |
| 1da177e4 | 2492 | * |
| 1b2a7205 MC |
2493 | * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds |
| 2494 | * netif_tx_lock when it needs to call | |
| 2495 | * netif_wake_queue. | |
| 1da177e4 | 2496 | * |
| f47c11ee | 2497 | * Both of these locks are to be held with BH safety. |
| 00b70504 MC |
2498 | * |
| 2499 | * Because the IRQ handler, tg3_poll, and tg3_start_xmit | |
| 2500 | * are running lockless, it is necessary to completely | |
| 2501 | * quiesce the chip with tg3_netif_stop and tg3_full_lock | |
| 2502 | * before reconfiguring the device. | |
| 2503 | * | |
| 2504 | * indirect_lock: Held when accessing registers indirectly | |
| 2505 | * with IRQ disabling. | |
| 1da177e4 LT |
2506 | */ |
| 2507 | spinlock_t lock; | |
| 2508 | spinlock_t indirect_lock; | |
| 2509 | ||
| 20094930 MC |
2510 | u32 (*read32) (struct tg3 *, u32); |
| 2511 | void (*write32) (struct tg3 *, u32, u32); | |
| 09ee929c | 2512 | u32 (*read32_mbox) (struct tg3 *, u32); |
| 20094930 MC |
2513 | void (*write32_mbox) (struct tg3 *, u32, |
| 2514 | u32); | |
| 1da177e4 | 2515 | void __iomem *regs; |
| 0d3031d9 | 2516 | void __iomem *aperegs; |
| 1da177e4 LT |
2517 | struct net_device *dev; |
| 2518 | struct pci_dev *pdev; | |
| 2519 | ||
| 2520 | struct tg3_hw_status *hw_status; | |
| 2521 | dma_addr_t status_mapping; | |
| fac9b83e | 2522 | u32 last_tag; |
| 624f8e50 | 2523 | u32 last_irq_tag; |
| 1da177e4 LT |
2524 | |
| 2525 | u32 msg_enable; | |
| 2526 | ||
| 2527 | /* begin "tx thread" cacheline section */ | |
| 20094930 MC |
2528 | void (*write32_tx_mbox) (struct tg3 *, u32, |
| 2529 | u32); | |
| 1da177e4 LT |
2530 | u32 tx_prod; |
| 2531 | u32 tx_cons; | |
| 2532 | u32 tx_pending; | |
| 2533 | ||
| 1da177e4 LT |
2534 | struct tg3_tx_buffer_desc *tx_ring; |
| 2535 | struct tx_ring_info *tx_buffers; | |
| 2536 | dma_addr_t tx_desc_mapping; | |
| 2537 | ||
| 2538 | /* begin "rx thread" cacheline section */ | |
| bea3348e | 2539 | struct napi_struct napi; |
| 20094930 MC |
2540 | void (*write32_rx_mbox) (struct tg3 *, u32, |
| 2541 | u32); | |
| 1da177e4 LT |
2542 | u32 rx_rcb_ptr; |
| 2543 | u32 rx_std_ptr; | |
| 2544 | u32 rx_jumbo_ptr; | |
| 2545 | u32 rx_pending; | |
| 2546 | u32 rx_jumbo_pending; | |
| 2547 | #if TG3_VLAN_TAG_USED | |
| 2548 | struct vlan_group *vlgrp; | |
| 2549 | #endif | |
| 2550 | ||
| 2551 | struct tg3_rx_buffer_desc *rx_std; | |
| 2552 | struct ring_info *rx_std_buffers; | |
| 2553 | dma_addr_t rx_std_mapping; | |
| f92905de | 2554 | u32 rx_std_max_post; |
| 1da177e4 LT |
2555 | |
| 2556 | struct tg3_rx_buffer_desc *rx_jumbo; | |
| 2557 | struct ring_info *rx_jumbo_buffers; | |
| 2558 | dma_addr_t rx_jumbo_mapping; | |
| 2559 | ||
| 2560 | struct tg3_rx_buffer_desc *rx_rcb; | |
| 2561 | dma_addr_t rx_rcb_mapping; | |
| 2562 | ||
| 7e72aad4 MC |
2563 | u32 rx_pkt_buf_sz; |
| 2564 | ||
| 1da177e4 LT |
2565 | /* begin "everything else" cacheline(s) section */ |
| 2566 | struct net_device_stats net_stats; | |
| 2567 | struct net_device_stats net_stats_prev; | |
| 2568 | struct tg3_ethtool_stats estats; | |
| 2569 | struct tg3_ethtool_stats estats_prev; | |
| 2570 | ||
| 4ba526ce | 2571 | union { |
| 1da177e4 | 2572 | unsigned long phy_crc_errors; |
| 4ba526ce MC |
2573 | unsigned long last_event_jiffies; |
| 2574 | }; | |
| 1da177e4 LT |
2575 | |
| 2576 | u32 rx_offset; | |
| 2577 | u32 tg3_flags; | |
| fac9b83e | 2578 | #define TG3_FLAG_TAGGED_STATUS 0x00000001 |
| 1da177e4 LT |
2579 | #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002 |
| 2580 | #define TG3_FLAG_RX_CHECKSUMS 0x00000004 | |
| 2581 | #define TG3_FLAG_USE_LINKCHG_REG 0x00000008 | |
| 2582 | #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010 | |
| 2583 | #define TG3_FLAG_ENABLE_ASF 0x00000020 | |
| 8ed5d97e | 2584 | #define TG3_FLAG_ASPM_WORKAROUND 0x00000040 |
| 1da177e4 | 2585 | #define TG3_FLAG_POLL_SERDES 0x00000080 |
| 1da177e4 | 2586 | #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100 |
| 1da177e4 LT |
2587 | #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200 |
| 2588 | #define TG3_FLAG_WOL_SPEED_100MB 0x00000400 | |
| 2589 | #define TG3_FLAG_WOL_ENABLE 0x00000800 | |
| 2590 | #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000 | |
| 2591 | #define TG3_FLAG_NVRAM 0x00002000 | |
| 2592 | #define TG3_FLAG_NVRAM_BUFFERED 0x00004000 | |
| 1da177e4 LT |
2593 | #define TG3_FLAG_PCIX_MODE 0x00020000 |
| 2594 | #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000 | |
| 2595 | #define TG3_FLAG_PCI_32BIT 0x00080000 | |
| bbadf503 | 2596 | #define TG3_FLAG_SRAM_USE_CONFIG 0x00100000 |
| df3e6548 | 2597 | #define TG3_FLAG_TX_RECOVERY_PENDING 0x00200000 |
| a85feb8c | 2598 | #define TG3_FLAG_WOL_CAP 0x00400000 |
| 0f893dc6 | 2599 | #define TG3_FLAG_JUMBO_RING_ENABLE 0x00800000 |
| 1da177e4 LT |
2600 | #define TG3_FLAG_10_100_ONLY 0x01000000 |
| 2601 | #define TG3_FLAG_PAUSE_AUTONEG 0x02000000 | |
| 795d01c5 | 2602 | #define TG3_FLAG_CPMU_PRESENT 0x04000000 |
| 4a29cc2e | 2603 | #define TG3_FLAG_40BIT_DMA_BUG 0x08000000 |
| 1da177e4 | 2604 | #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000 |
| 7544b097 | 2605 | #define TG3_FLAG_SUPPORT_MSI 0x20000000 |
| d18edcb2 | 2606 | #define TG3_FLAG_CHIP_RESETTING 0x40000000 |
| 1da177e4 LT |
2607 | #define TG3_FLAG_INIT_COMPLETE 0x80000000 |
| 2608 | u32 tg3_flags2; | |
| 2609 | #define TG3_FLG2_RESTART_TIMER 0x00000001 | |
| 7f62ad5d | 2610 | #define TG3_FLG2_TSO_BUG 0x00000002 |
| 1da177e4 LT |
2611 | #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004 |
| 2612 | #define TG3_FLG2_IS_5788 0x00000008 | |
| 2613 | #define TG3_FLG2_MAX_RXPEND_64 0x00000010 | |
| 2614 | #define TG3_FLG2_TSO_CAPABLE 0x00000020 | |
| 2615 | #define TG3_FLG2_PHY_ADC_BUG 0x00000040 | |
| 2616 | #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080 | |
| 2617 | #define TG3_FLG2_PHY_BER_BUG 0x00000100 | |
| 2618 | #define TG3_FLG2_PCI_EXPRESS 0x00000200 | |
| 2619 | #define TG3_FLG2_ASF_NEW_HANDSHAKE 0x00000400 | |
| 2620 | #define TG3_FLG2_HW_AUTONEG 0x00000800 | |
| 9d26e213 | 2621 | #define TG3_FLG2_IS_NIC 0x00001000 |
| 1da177e4 LT |
2622 | #define TG3_FLG2_PHY_SERDES 0x00002000 |
| 2623 | #define TG3_FLG2_CAPACITIVE_COUPLING 0x00004000 | |
| 2624 | #define TG3_FLG2_FLASH 0x00008000 | |
| 5a6f3074 | 2625 | #define TG3_FLG2_HW_TSO_1 0x00010000 |
| 1da177e4 LT |
2626 | #define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000 |
| 2627 | #define TG3_FLG2_5705_PLUS 0x00040000 | |
| 6708e5cc | 2628 | #define TG3_FLG2_5750_PLUS 0x00080000 |
| e6af301b | 2629 | #define TG3_FLG2_PROTECTED_NVRAM 0x00100000 |
| 88b06bc2 | 2630 | #define TG3_FLG2_USING_MSI 0x00200000 |
| 0f893dc6 | 2631 | #define TG3_FLG2_JUMBO_CAPABLE 0x00400000 |
| 747e8f8b MC |
2632 | #define TG3_FLG2_MII_SERDES 0x00800000 |
| 2633 | #define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \ | |
| 2634 | TG3_FLG2_MII_SERDES) | |
| 2635 | #define TG3_FLG2_PARALLEL_DETECT 0x01000000 | |
| 6892914f | 2636 | #define TG3_FLG2_ICH_WORKAROUND 0x02000000 |
| a4e2b347 | 2637 | #define TG3_FLG2_5780_CLASS 0x04000000 |
| 5a6f3074 MC |
2638 | #define TG3_FLG2_HW_TSO_2 0x08000000 |
| 2639 | #define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2) | |
| fcfa0a32 | 2640 | #define TG3_FLG2_1SHOT_MSI 0x10000000 |
| c424cb24 | 2641 | #define TG3_FLG2_PHY_JITTER_BUG 0x20000000 |
| f49639e6 | 2642 | #define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 |
| c1d2a196 | 2643 | #define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000 |
| 6b91fa02 MC |
2644 | u32 tg3_flags3; |
| 2645 | #define TG3_FLG3_NO_NVRAM_ADDR_TRANS 0x00000001 | |
| 0d3031d9 | 2646 | #define TG3_FLG3_ENABLE_APE 0x00000002 |
| 41588ba1 | 2647 | #define TG3_FLG3_5701_DMA_BUG 0x00000008 |
| dd477003 | 2648 | #define TG3_FLG3_USE_PHYLIB 0x00000010 |
| 158d7abd MC |
2649 | #define TG3_FLG3_MDIOBUS_INITED 0x00000020 |
| 2650 | #define TG3_FLG3_MDIOBUS_PAUSED 0x00000040 | |
| b02fd9e3 | 2651 | #define TG3_FLG3_PHY_CONNECTED 0x00000080 |
| a9daf367 MC |
2652 | #define TG3_FLG3_RGMII_STD_IBND_DISABLE 0x00000100 |
| 2653 | #define TG3_FLG3_RGMII_EXT_IBND_RX_EN 0x00000200 | |
| 2654 | #define TG3_FLG3_RGMII_EXT_IBND_TX_EN 0x00000400 | |
| 5e7dfd0f | 2655 | #define TG3_FLG3_CLKREQ_BUG 0x00000800 |
| 6833c043 | 2656 | #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 |
| 321d32a0 | 2657 | #define TG3_FLG3_5755_PLUS 0x00002000 |
| df259d8c | 2658 | #define TG3_FLG3_NO_NVRAM 0x00004000 |
| 255ca311 | 2659 | #define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000 |
| 1da177e4 | 2660 | |
| 1da177e4 LT |
2661 | struct timer_list timer; |
| 2662 | u16 timer_counter; | |
| 2663 | u16 timer_multiplier; | |
| 2664 | u32 timer_offset; | |
| 2665 | u16 asf_counter; | |
| 2666 | u16 asf_multiplier; | |
| 2667 | ||
| 3d3ebe74 MC |
2668 | /* 1 second counter for transient serdes link events */ |
| 2669 | u32 serdes_counter; | |
| 2670 | #define SERDES_AN_TIMEOUT_5704S 2 | |
| 2671 | #define SERDES_PARALLEL_DET_TIMEOUT 1 | |
| 2672 | #define SERDES_AN_TIMEOUT_5714S 1 | |
| 2673 | ||
| 1da177e4 LT |
2674 | struct tg3_link_config link_config; |
| 2675 | struct tg3_bufmgr_config bufmgr_config; | |
| 2676 | ||
| 2677 | /* cache h/w values, often passed straight to h/w */ | |
| 2678 | u32 rx_mode; | |
| 2679 | u32 tx_mode; | |
| 2680 | u32 mac_mode; | |
| 2681 | u32 mi_mode; | |
| 2682 | u32 misc_host_ctrl; | |
| 2683 | u32 grc_mode; | |
| 2684 | u32 grc_local_ctrl; | |
| 2685 | u32 dma_rwctrl; | |
| 2686 | u32 coalesce_mode; | |
| 8ed5d97e | 2687 | u32 pwrmgmt_thresh; |
| 1da177e4 LT |
2688 | |
| 2689 | /* PCI block */ | |
| 795d01c5 | 2690 | u32 pci_chip_rev_id; |
| 69fc4053 | 2691 | u16 pci_cmd; |
| 1da177e4 LT |
2692 | u8 pci_cacheline_sz; |
| 2693 | u8 pci_lat_timer; | |
| 1da177e4 LT |
2694 | |
| 2695 | int pm_cap; | |
| 4cf78e4f | 2696 | int msi_cap; |
| 5e7dfd0f | 2697 | union { |
| 9974a356 | 2698 | int pcix_cap; |
| 5e7dfd0f MC |
2699 | int pcie_cap; |
| 2700 | }; | |
| 1da177e4 | 2701 | |
| 298cf9be | 2702 | struct mii_bus *mdio_bus; |
| 158d7abd MC |
2703 | int mdio_irq[PHY_MAX_ADDR]; |
| 2704 | ||
| 1da177e4 LT |
2705 | /* PHY info */ |
| 2706 | u32 phy_id; | |
| 2707 | #define PHY_ID_MASK 0xfffffff0 | |
| 2708 | #define PHY_ID_BCM5400 0x60008040 | |
| 2709 | #define PHY_ID_BCM5401 0x60008050 | |
| 2710 | #define PHY_ID_BCM5411 0x60008070 | |
| 2711 | #define PHY_ID_BCM5701 0x60008110 | |
| 2712 | #define PHY_ID_BCM5703 0x60008160 | |
| 2713 | #define PHY_ID_BCM5704 0x60008190 | |
| 2714 | #define PHY_ID_BCM5705 0x600081a0 | |
| 2715 | #define PHY_ID_BCM5750 0x60008180 | |
| 85e94ced | 2716 | #define PHY_ID_BCM5752 0x60008100 |
| a4e2b347 | 2717 | #define PHY_ID_BCM5714 0x60008340 |
| 4cf78e4f | 2718 | #define PHY_ID_BCM5780 0x60008350 |
| af36e6b6 | 2719 | #define PHY_ID_BCM5755 0xbc050cc0 |
| d9ab5ad1 | 2720 | #define PHY_ID_BCM5787 0xbc050ce0 |
| 126a3368 | 2721 | #define PHY_ID_BCM5756 0xbc050ed0 |
| d30cdd28 | 2722 | #define PHY_ID_BCM5784 0xbc050fa0 |
| 9936bcf6 | 2723 | #define PHY_ID_BCM5761 0xbc050fd0 |
| b5d3772c | 2724 | #define PHY_ID_BCM5906 0xdc00ac40 |
| 1da177e4 LT |
2725 | #define PHY_ID_BCM8002 0x60010140 |
| 2726 | #define PHY_ID_INVALID 0xffffffff | |
| 2727 | #define PHY_ID_REV_MASK 0x0000000f | |
| 2728 | #define PHY_REV_BCM5401_B0 0x1 | |
| 2729 | #define PHY_REV_BCM5401_B2 0x3 | |
| 2730 | #define PHY_REV_BCM5401_C0 0x6 | |
| 2731 | #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */ | |
| a9daf367 MC |
2732 | #define TG3_PHY_ID_BCM50610 0x143bd60 |
| 2733 | #define TG3_PHY_ID_BCMAC131 0x143bc70 | |
| fcb389df MC |
2734 | #define TG3_PHY_ID_RTL8211C 0x001cc910 |
| 2735 | #define TG3_PHY_ID_RTL8201E 0x00008200 | |
| 321d32a0 | 2736 | #define TG3_PHY_ID_BCM57780 0x03625d90 |
| 0a459aac MC |
2737 | #define TG3_PHY_OUI_MASK 0xfffffc00 |
| 2738 | #define TG3_PHY_OUI_1 0x00206000 | |
| 2739 | #define TG3_PHY_OUI_2 0x0143bc00 | |
| 2740 | #define TG3_PHY_OUI_3 0x03625c00 | |
| 1da177e4 LT |
2741 | |
| 2742 | u32 led_ctrl; | |
| b2a5c19c | 2743 | u32 phy_otp; |
| 1da177e4 LT |
2744 | |
| 2745 | char board_part_number[24]; | |
| 9c8a620e MC |
2746 | #define TG3_VER_SIZE 32 |
| 2747 | char fw_ver[TG3_VER_SIZE]; | |
| 1da177e4 LT |
2748 | u32 nic_sram_data_cfg; |
| 2749 | u32 pci_clock_ctrl; | |
| 2750 | struct pci_dev *pdev_peer; | |
| 2751 | ||
| 2752 | /* This macro assumes the passed PHY ID is already masked | |
| 2753 | * with PHY_ID_MASK. | |
| 2754 | */ | |
| 2755 | #define KNOWN_PHY_ID(X) \ | |
| 2756 | ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \ | |
| 2757 | (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \ | |
| 2758 | (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \ | |
| 2759 | (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \ | |
| a4e2b347 | 2760 | (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \ |
| d9ab5ad1 | 2761 | (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \ |
| 126a3368 | 2762 | (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \ |
| 9936bcf6 MC |
2763 | (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \ |
| 2764 | (X) == PHY_ID_BCM8002) | |
| 1da177e4 LT |
2765 | |
| 2766 | struct tg3_hw_stats *hw_stats; | |
| 2767 | dma_addr_t stats_mapping; | |
| 2768 | struct work_struct reset_task; | |
| 2769 | ||
| ec41c7df | 2770 | int nvram_lock_cnt; |
| 1da177e4 | 2771 | u32 nvram_size; |
| fd1122a2 MC |
2772 | #define TG3_NVRAM_SIZE_64KB 0x00010000 |
| 2773 | #define TG3_NVRAM_SIZE_128KB 0x00020000 | |
| 2774 | #define TG3_NVRAM_SIZE_256KB 0x00040000 | |
| 2775 | #define TG3_NVRAM_SIZE_512KB 0x00080000 | |
| 2776 | #define TG3_NVRAM_SIZE_1MB 0x00100000 | |
| 2777 | #define TG3_NVRAM_SIZE_2MB 0x00200000 | |
| 2778 | ||
| 1da177e4 LT |
2779 | u32 nvram_pagesize; |
| 2780 | u32 nvram_jedecnum; | |
| 2781 | ||
| 2782 | #define JEDEC_ATMEL 0x1f | |
| 2783 | #define JEDEC_ST 0x20 | |
| 2784 | #define JEDEC_SAIFUN 0x4f | |
| 2785 | #define JEDEC_SST 0xbf | |
| 2786 | ||
| fd1122a2 | 2787 | #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB |
| 1da177e4 LT |
2788 | #define ATMEL_AT24C64_PAGE_SIZE (32) |
| 2789 | ||
| fd1122a2 | 2790 | #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB |
| 1da177e4 LT |
2791 | #define ATMEL_AT24C512_PAGE_SIZE (128) |
| 2792 | ||
| 2793 | #define ATMEL_AT45DB0X1B_PAGE_POS 9 | |
| 2794 | #define ATMEL_AT45DB0X1B_PAGE_SIZE 264 | |
| 2795 | ||
| 2796 | #define ATMEL_AT25F512_PAGE_SIZE 256 | |
| 2797 | ||
| 2798 | #define ST_M45PEX0_PAGE_SIZE 256 | |
| 2799 | ||
| 2800 | #define SAIFUN_SA25F0XX_PAGE_SIZE 256 | |
| 2801 | ||
| 2802 | #define SST_25VF0X0_PAGE_SIZE 4098 | |
| 2803 | ||
| 15f9850d | 2804 | struct ethtool_coalesce coal; |
| 077f849d JSR |
2805 | |
| 2806 | /* firmware info */ | |
| 9e9fd12d | 2807 | const char *fw_needed; |
| 077f849d JSR |
2808 | const struct firmware *fw; |
| 2809 | u32 fw_len; /* includes BSS */ | |
| 1da177e4 LT |
2810 | }; |
| 2811 | ||
| 2812 | #endif /* !(_T3_H) */ |