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ixgbe: cleanup ixgbe_set_tx_csum ethtool flags configuration
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
9a799d71
AK		 33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
29c3a050
AK		 44enum {NETDEV_STATS, IXGBE_STATS};
45
9a799d71
AK		 46struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
29c3a050 48 int type;
9a799d71
AK		 49 int sizeof_stat;
50 int stat_offset;
51};
52
29c3a050
AK		 53#define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
29c3a050 59
9a799d71 60static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
55bad823
ED		 87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 105#ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112#endif /* IXGBE_FCOE */
9a799d71
AK		 113};
114
115#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 119#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 120#define IXGBE_PB_STATS_LEN ( \
9d2f4720 121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
9a799d71 131
da4dd0f7
PWJ		 132static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136};
137#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
9a799d71 139static int ixgbe_get_settings(struct net_device *netdev,
b4617240 140 struct ethtool_cmd *ecmd)
9a799d71
AK		 141{
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
9a799d71 146
735441fb
AV		 147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 149 ecmd->transceiver = XCVR_EXTERNAL;
74766013 150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 151 (hw->phy.multispeed_fiber)) {
735441fb 152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 153 SUPPORTED_Autoneg);
735441fb 154
74766013 155 ecmd->advertising = ADVERTISED_Autoneg;
735441fb
AV		 156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
735441fb 169
74766013
MC		 170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
1e336d0f
DS		 179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
46a72b35
MC		 188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
1e336d0f 195 }
735441fb
AV		 196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 199 ADVERTISED_FIBRE);
735441fb 200 ecmd->port = PORT_FIBRE;
c44ade9e 201 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 202 }
9a799d71 203
3b8626ba
PW		 204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
cb836a97
DS		 237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
3b8626ba
PW		 244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
c44ade9e 261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 264 SPEED_10000 : SPEED_1000;
9a799d71
AK		 265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
9a799d71
AK		 271 return 0;
272}
273
274static int ixgbe_set_settings(struct net_device *netdev,
b4617240 275 struct ethtool_cmd *ecmd)
9a799d71
AK		 276{
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 278 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 279 u32 advertised, old;
74766013 280 s32 err = 0;
9a799d71 281
74766013 282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 283 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
74766013 299 return err;
0befdb3e 300 /* this sets the link speed and restarts auto-neg */
74766013 301 hw->mac.autotry_restart = true;
8620a103 302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 303 if (err) {
396e799c 304 e_info(probe, "setup link failed with code %d\n", err);
8620a103 305 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 306 }
74766013
MC		 307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
74766013
MC		 311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
9a799d71
AK		 313 }
314
74766013 315 return err;
9a799d71
AK		 316}
317
318static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 319 struct ethtool_pauseparam *pause)
9a799d71
AK		 320{
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
71fd570b
DS		 324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
9a799d71 334
8756924c
PWJ		 335#ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341#endif
0ecc061d 342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 343 pause->rx_pause = 1;
0ecc061d 344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 345 pause->tx_pause = 1;
0ecc061d 346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350}
351
352static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
620fa036 357 struct ixgbe_fc_info fc;
9a799d71 358
264857b8
PWJ		 359#ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365#endif
620fa036
MC		 366
367 fc = hw->fc;
368
71fd570b 369 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 370 fc.disable_fc_autoneg = true;
71fd570b 371 else
620fa036 372 fc.disable_fc_autoneg = false;
71fd570b 373
1c4f0ef8 374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 375 fc.requested_mode = ixgbe_fc_full;
9a799d71 376 else if (pause->rx_pause && !pause->tx_pause)
620fa036 377 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 378 else if (!pause->rx_pause && pause->tx_pause)
620fa036 379 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 380 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 381 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 382 else
383 return -EINVAL;
9a799d71 384
264857b8 385#ifdef CONFIG_DCB
620fa036 386 adapter->last_lfc_mode = fc.requested_mode;
264857b8 387#endif
620fa036
MC		 388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
9a799d71
AK		 397
398 return 0;
399}
400
401static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402{
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
807540ba 404 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
9a799d71
AK		 405}
406
407static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408{
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
9a799d71
AK		 415 return 0;
416}
417
418static u32 ixgbe_get_tx_csum(struct net_device *netdev)
419{
22f32b7a 420 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 421}
422
423static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
424{
45a5ead0
JB		 425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
426
427 if (data) {
e2b4e216 428 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
45a5ead0
JB		 429 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
430 netdev->features |= NETIF_F_SCTP_CSUM;
431 } else {
e2b4e216
AD		 432 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
433 NETIF_F_SCTP_CSUM);
45a5ead0 434 }
9a799d71
AK		 435
436 return 0;
437}
438
439static int ixgbe_set_tso(struct net_device *netdev, u32 data)
440{
9a799d71
AK		 441 if (data) {
442 netdev->features |= NETIF_F_TSO;
443 netdev->features |= NETIF_F_TSO6;
444 } else {
445 netdev->features &= ~NETIF_F_TSO;
446 netdev->features &= ~NETIF_F_TSO6;
447 }
448 return 0;
449}
450
451static u32 ixgbe_get_msglevel(struct net_device *netdev)
452{
453 struct ixgbe_adapter *adapter = netdev_priv(netdev);
454 return adapter->msg_enable;
455}
456
457static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
458{
459 struct ixgbe_adapter *adapter = netdev_priv(netdev);
460 adapter->msg_enable = data;
461}
462
463static int ixgbe_get_regs_len(struct net_device *netdev)
464{
465#define IXGBE_REGS_LEN 1128
466 return IXGBE_REGS_LEN * sizeof(u32);
467}
468
469#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
470
471static void ixgbe_get_regs(struct net_device *netdev,
b4617240 472 struct ethtool_regs *regs, void *p)
9a799d71
AK		 473{
474 struct ixgbe_adapter *adapter = netdev_priv(netdev);
475 struct ixgbe_hw *hw = &adapter->hw;
476 u32 *regs_buff = p;
477 u8 i;
478
479 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
480
481 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
482
483 /* General Registers */
484 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
485 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
486 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
487 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
488 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
489 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
490 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
491 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
492
493 /* NVM Register */
494 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
495 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
496 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
497 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
498 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
499 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
500 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
501 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
502 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
503 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
504
505 /* Interrupt */
98c00a1c
JB		 506 /* don't read EICR because it can clear interrupt causes, instead
507 * read EICS which is a shadow but doesn't clear EICR */
508 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 509 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
510 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
511 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
512 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
513 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
514 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
515 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
516 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
517 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 518 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 519 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
520
521 /* Flow Control */
522 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
523 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
524 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
525 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
526 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 527 for (i = 0; i < 8; i++) {
528 switch (hw->mac.type) {
529 case ixgbe_mac_82598EB:
530 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
531 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
532 break;
533 case ixgbe_mac_82599EB:
534 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
535 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
536 break;
537 default:
538 break;
539 }
540 }
9a799d71
AK		 541 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
542 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
543
544 /* Receive DMA */
545 for (i = 0; i < 64; i++)
546 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
547 for (i = 0; i < 64; i++)
548 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
549 for (i = 0; i < 64; i++)
550 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
551 for (i = 0; i < 64; i++)
552 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
553 for (i = 0; i < 64; i++)
554 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
555 for (i = 0; i < 64; i++)
556 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
557 for (i = 0; i < 16; i++)
558 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
559 for (i = 0; i < 16; i++)
560 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
561 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
562 for (i = 0; i < 8; i++)
563 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
564 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
565 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
566
567 /* Receive */
568 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
569 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
570 for (i = 0; i < 16; i++)
571 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
572 for (i = 0; i < 16; i++)
573 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 574 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 575 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
576 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
577 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
578 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
579 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
580 for (i = 0; i < 8; i++)
581 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
582 for (i = 0; i < 8; i++)
583 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
584 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
585
586 /* Transmit */
587 for (i = 0; i < 32; i++)
588 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
589 for (i = 0; i < 32; i++)
590 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
591 for (i = 0; i < 32; i++)
592 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
593 for (i = 0; i < 32; i++)
594 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
595 for (i = 0; i < 32; i++)
596 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
597 for (i = 0; i < 32; i++)
598 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
599 for (i = 0; i < 32; i++)
600 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
601 for (i = 0; i < 32; i++)
602 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
603 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
604 for (i = 0; i < 16; i++)
605 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
606 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
607 for (i = 0; i < 8; i++)
608 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
609 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
610
611 /* Wake Up */
612 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
613 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
614 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
615 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
616 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
617 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
618 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
619 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 620 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 621
9a799d71
AK		 622 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
623 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
624 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
625 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
626 for (i = 0; i < 8; i++)
627 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
628 for (i = 0; i < 8; i++)
629 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
630 for (i = 0; i < 8; i++)
631 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
632 for (i = 0; i < 8; i++)
633 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
634 for (i = 0; i < 8; i++)
635 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
636 for (i = 0; i < 8; i++)
637 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
638
639 /* Statistics */
640 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
641 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
642 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
643 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
644 for (i = 0; i < 8; i++)
645 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
646 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
647 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
648 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
649 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
650 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
651 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
652 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
653 for (i = 0; i < 8; i++)
654 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
655 for (i = 0; i < 8; i++)
656 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
657 for (i = 0; i < 8; i++)
658 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
659 for (i = 0; i < 8; i++)
660 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
661 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
662 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
663 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
664 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
665 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
666 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
667 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
668 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
669 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
670 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
671 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
672 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
673 for (i = 0; i < 8; i++)
674 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
675 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
676 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
677 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
678 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
679 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
680 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
681 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
682 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
683 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
684 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
685 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
686 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
687 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
688 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
689 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
690 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
691 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
692 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
693 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
694 for (i = 0; i < 16; i++)
695 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
696 for (i = 0; i < 16; i++)
697 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
698 for (i = 0; i < 16; i++)
699 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
700 for (i = 0; i < 16; i++)
701 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
702
703 /* MAC */
704 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
705 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
706 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
707 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
708 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
709 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
710 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
711 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
712 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
713 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
714 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
715 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
716 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
717 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
718 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
719 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
720 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
721 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
722 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
723 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
724 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
725 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
726 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
727 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
728 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
729 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
730 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
731 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
732 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
733 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
734 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
735 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
736 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
737
738 /* Diagnostic */
739 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
740 for (i = 0; i < 8; i++)
98c00a1c 741 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 742 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 743 for (i = 0; i < 4; i++)
744 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 745 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
746 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
747 for (i = 0; i < 8; i++)
98c00a1c 748 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 749 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 750 for (i = 0; i < 4; i++)
751 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 752 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
753 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
754 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
755 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
756 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
757 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
758 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
759 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
760 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
761 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
762 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
763 for (i = 0; i < 8; i++)
98c00a1c 764 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 765 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
766 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
767 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
768 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
769 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
770 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
771 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
772 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
773 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
774}
775
776static int ixgbe_get_eeprom_len(struct net_device *netdev)
777{
778 struct ixgbe_adapter *adapter = netdev_priv(netdev);
779 return adapter->hw.eeprom.word_size * 2;
780}
781
782static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 783 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 784{
785 struct ixgbe_adapter *adapter = netdev_priv(netdev);
786 struct ixgbe_hw *hw = &adapter->hw;
787 u16 *eeprom_buff;
788 int first_word, last_word, eeprom_len;
789 int ret_val = 0;
790 u16 i;
791
792 if (eeprom->len == 0)
793 return -EINVAL;
794
795 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
796
797 first_word = eeprom->offset >> 1;
798 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
799 eeprom_len = last_word - first_word + 1;
800
801 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
802 if (!eeprom_buff)
803 return -ENOMEM;
804
805 for (i = 0; i < eeprom_len; i++) {
c44ade9e 806 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 807 &eeprom_buff[i])))
9a799d71
AK		 808 break;
809 }
810
811 /* Device's eeprom is always little-endian, word addressable */
812 for (i = 0; i < eeprom_len; i++)
813 le16_to_cpus(&eeprom_buff[i]);
814
815 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
816 kfree(eeprom_buff);
817
818 return ret_val;
819}
820
821static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 822 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 823{
824 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 825 char firmware_version[32];
9a799d71 826
083fc582
DS		 827 strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
828 strncpy(drvinfo->version, ixgbe_driver_version,
829 sizeof(drvinfo->version));
830
831 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
832 (adapter->eeprom_version & 0xF000) >> 12,
833 (adapter->eeprom_version & 0x0FF0) >> 4,
834 adapter->eeprom_version & 0x000F);
835
836 strncpy(drvinfo->fw_version, firmware_version,
837 sizeof(drvinfo->fw_version));
838 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
839 sizeof(drvinfo->bus_info));
9a799d71 840 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 841 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 842 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
843}
844
845static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 846 struct ethtool_ringparam *ring)
9a799d71
AK		 847{
848 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 849 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
850 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 851
852 ring->rx_max_pending = IXGBE_MAX_RXD;
853 ring->tx_max_pending = IXGBE_MAX_TXD;
854 ring->rx_mini_max_pending = 0;
855 ring->rx_jumbo_max_pending = 0;
856 ring->rx_pending = rx_ring->count;
857 ring->tx_pending = tx_ring->count;
858 ring->rx_mini_pending = 0;
859 ring->rx_jumbo_pending = 0;
860}
861
862static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 863 struct ethtool_ringparam *ring)
9a799d71
AK		 864{
865 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 866 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 867 int i, err = 0;
c431f97e 868 u32 new_rx_count, new_tx_count;
f9ed8854 869 bool need_update = false;
9a799d71
AK		 870
871 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
872 return -EINVAL;
873
874 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
875 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
876 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
877
878 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
879 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
880 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
881
4a0b9ca0
PW		 882 if ((new_tx_count == adapter->tx_ring[0]->count) &&
883 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 884 /* nothing to do */
885 return 0;
886 }
887
d4f80882
AV		 888 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
889 msleep(1);
890
759884b4
AD		 891 if (!netif_running(adapter->netdev)) {
892 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 893 adapter->tx_ring[i]->count = new_tx_count;
759884b4 894 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 895 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 896 adapter->tx_ring_count = new_tx_count;
897 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 898 goto clear_reset;
759884b4
AD		 899 }
900
4a0b9ca0 901 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 902 if (!temp_tx_ring) {
903 err = -ENOMEM;
4a0b9ca0 904 goto clear_reset;
f9ed8854
MC		 905 }
906
907 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 908 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 909 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
910 sizeof(struct ixgbe_ring));
f9ed8854 911 temp_tx_ring[i].count = new_tx_count;
b6ec895e 912 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 913 if (err) {
c431f97e
JB		 914 while (i) {
915 i--;
b6ec895e 916 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 917 }
4a0b9ca0 918 goto clear_reset;
9a799d71 919 }
9a799d71 920 }
f9ed8854 921 need_update = true;
9a799d71
AK		 922 }
923
4a0b9ca0
PW		 924 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
925 if (!temp_rx_ring) {
f9ed8854
MC		 926 err = -ENOMEM;
927 goto err_setup;
d3fa4721 928 }
9a799d71 929
f9ed8854 930 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 931 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 932 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
933 sizeof(struct ixgbe_ring));
f9ed8854 934 temp_rx_ring[i].count = new_rx_count;
b6ec895e 935 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 936 if (err) {
c431f97e
JB		 937 while (i) {
938 i--;
b6ec895e 939 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 940 }
9a799d71
AK		 941 goto err_setup;
942 }
9a799d71 943 }
f9ed8854
MC		 944 need_update = true;
945 }
946
947 /* if rings need to be updated, here's the place to do it in one shot */
948 if (need_update) {
759884b4 949 ixgbe_down(adapter);
f9ed8854
MC		 950
951 /* tx */
952 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 953 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 954 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 955 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
956 sizeof(struct ixgbe_ring));
957 }
f9ed8854
MC		 958 adapter->tx_ring_count = new_tx_count;
959 }
960
961 /* rx */
962 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 963 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 964 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 965 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
966 sizeof(struct ixgbe_ring));
967 }
f9ed8854
MC		 968 adapter->rx_ring_count = new_rx_count;
969 }
f9ed8854 970 ixgbe_up(adapter);
759884b4 971 }
4a0b9ca0
PW		 972
973 vfree(temp_rx_ring);
f9ed8854 974err_setup:
4a0b9ca0
PW		 975 vfree(temp_tx_ring);
976clear_reset:
d4f80882 977 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 978 return err;
979}
980
b9f2c044 981static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 982{
b9f2c044 983 switch (sset) {
da4dd0f7
PWJ		 984 case ETH_SS_TEST:
985 return IXGBE_TEST_LEN;
b9f2c044
JG		 986 case ETH_SS_STATS:
987 return IXGBE_STATS_LEN;
9a713e7c 988 case ETH_SS_NTUPLE_FILTERS:
807540ba
ED		 989 return ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
990 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY;
b9f2c044
JG		 991 default:
992 return -EOPNOTSUPP;
993 }
9a799d71
AK		 994}
995
996static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 997 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 998{
999 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1000 struct rtnl_link_stats64 temp;
1001 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1002 unsigned int start;
1003 struct ixgbe_ring *ring;
1004 int i, j;
29c3a050 1005 char *p = NULL;
9a799d71
AK		 1006
1007 ixgbe_update_stats(adapter);
28172739 1008 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1009 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1010 switch (ixgbe_gstrings_stats[i].type) {
1011 case NETDEV_STATS:
28172739 1012 p = (char *) net_stats +
29c3a050
AK		 1013 ixgbe_gstrings_stats[i].stat_offset;
1014 break;
1015 case IXGBE_STATS:
1016 p = (char *) adapter +
1017 ixgbe_gstrings_stats[i].stat_offset;
1018 break;
1019 }
1020
9a799d71 1021 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1022 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1023 }
1024 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1025 ring = adapter->tx_ring[j];
1026 do {
1027 start = u64_stats_fetch_begin_bh(&ring->syncp);
1028 data[i] = ring->stats.packets;
1029 data[i+1] = ring->stats.bytes;
1030 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1031 i += 2;
9a799d71
AK		 1032 }
1033 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1034 ring = adapter->rx_ring[j];
1035 do {
1036 start = u64_stats_fetch_begin_bh(&ring->syncp);
1037 data[i] = ring->stats.packets;
1038 data[i+1] = ring->stats.bytes;
1039 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1040 i += 2;
9a799d71 1041 }
2f90b865
AD		 1042 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1043 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1044 data[i++] = adapter->stats.pxontxc[j];
1045 data[i++] = adapter->stats.pxofftxc[j];
1046 }
1047 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1048 data[i++] = adapter->stats.pxonrxc[j];
1049 data[i++] = adapter->stats.pxoffrxc[j];
1050 }
1051 }
9a799d71
AK		 1052}
1053
1054static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1055 u8 *data)
9a799d71
AK		 1056{
1057 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1058 char *p = (char *)data;
9a799d71
AK		 1059 int i;
1060
1061 switch (stringset) {
da4dd0f7
PWJ		 1062 case ETH_SS_TEST:
1063 memcpy(data, *ixgbe_gstrings_test,
1064 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1065 break;
9a799d71
AK		 1066 case ETH_SS_STATS:
1067 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1068 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1069 ETH_GSTRING_LEN);
1070 p += ETH_GSTRING_LEN;
1071 }
1072 for (i = 0; i < adapter->num_tx_queues; i++) {
1073 sprintf(p, "tx_queue_%u_packets", i);
1074 p += ETH_GSTRING_LEN;
1075 sprintf(p, "tx_queue_%u_bytes", i);
1076 p += ETH_GSTRING_LEN;
1077 }
1078 for (i = 0; i < adapter->num_rx_queues; i++) {
1079 sprintf(p, "rx_queue_%u_packets", i);
1080 p += ETH_GSTRING_LEN;
1081 sprintf(p, "rx_queue_%u_bytes", i);
1082 p += ETH_GSTRING_LEN;
1083 }
2f90b865
AD		 1084 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1085 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1086 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1087 p += ETH_GSTRING_LEN;
1088 sprintf(p, "tx_pb_%u_pxoff", i);
1089 p += ETH_GSTRING_LEN;
2f90b865
AD		 1090 }
1091 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1092 sprintf(p, "rx_pb_%u_pxon", i);
1093 p += ETH_GSTRING_LEN;
1094 sprintf(p, "rx_pb_%u_pxoff", i);
1095 p += ETH_GSTRING_LEN;
2f90b865
AD		 1096 }
1097 }
b4617240 1098 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1099 break;
1100 }
1101}
1102
da4dd0f7
PWJ		 1103static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1104{
1105 struct ixgbe_hw *hw = &adapter->hw;
1106 bool link_up;
1107 u32 link_speed = 0;
1108 *data = 0;
1109
1110 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1111 if (link_up)
1112 return *data;
1113 else
1114 *data = 1;
1115 return *data;
1116}
1117
1118/* ethtool register test data */
1119struct ixgbe_reg_test {
1120 u16 reg;
1121 u8 array_len;
1122 u8 test_type;
1123 u32 mask;
1124 u32 write;
1125};
1126
1127/* In the hardware, registers are laid out either singly, in arrays
1128 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1129 * most tests take place on arrays or single registers (handled
1130 * as a single-element array) and special-case the tables.
1131 * Table tests are always pattern tests.
1132 *
1133 * We also make provision for some required setup steps by specifying
1134 * registers to be written without any read-back testing.
1135 */
1136
1137#define PATTERN_TEST 1
1138#define SET_READ_TEST 2
1139#define WRITE_NO_TEST 3
1140#define TABLE32_TEST 4
1141#define TABLE64_TEST_LO 5
1142#define TABLE64_TEST_HI 6
1143
1144/* default 82599 register test */
1145static struct ixgbe_reg_test reg_test_82599[] = {
1146 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1147 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1148 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1149 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1150 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1151 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1152 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1153 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1154 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1155 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1156 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1157 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1158 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1159 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1160 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1161 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1162 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1163 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1164 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1165 { 0, 0, 0, 0 }
1166};
1167
1168/* default 82598 register test */
1169static struct ixgbe_reg_test reg_test_82598[] = {
1170 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1171 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1172 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1173 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1174 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1175 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1176 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1177 /* Enable all four RX queues before testing. */
1178 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1179 /* RDH is read-only for 82598, only test RDT. */
1180 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1181 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1182 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1183 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1184 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1185 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1186 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1187 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1188 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1189 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1190 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1191 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1192 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1193 { 0, 0, 0, 0 }
1194};
1195
1196#define REG_PATTERN_TEST(R, M, W) \
1197{ \
1198 u32 pat, val, before; \
1199 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1200 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1201 before = readl(adapter->hw.hw_addr + R); \
1202 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1203 val = readl(adapter->hw.hw_addr + R); \
1204 if (val != (_test[pat] & W & M)) { \
396e799c
ET		 1205 e_err(drv, "pattern test reg %04X failed: got " \
1206 "0x%08X expected 0x%08X\n", \
849c4542 1207 R, val, (_test[pat] & W & M)); \
da4dd0f7
PWJ		 1208 *data = R; \
1209 writel(before, adapter->hw.hw_addr + R); \
1210 return 1; \
1211 } \
1212 writel(before, adapter->hw.hw_addr + R); \
1213 } \
1214}
1215
1216#define REG_SET_AND_CHECK(R, M, W) \
1217{ \
1218 u32 val, before; \
1219 before = readl(adapter->hw.hw_addr + R); \
1220 writel((W & M), (adapter->hw.hw_addr + R)); \
1221 val = readl(adapter->hw.hw_addr + R); \
1222 if ((W & M) != (val & M)) { \
396e799c
ET		 1223 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
1224 "expected 0x%08X\n", R, (val & M), (W & M)); \
da4dd0f7
PWJ		 1225 *data = R; \
1226 writel(before, (adapter->hw.hw_addr + R)); \
1227 return 1; \
1228 } \
1229 writel(before, (adapter->hw.hw_addr + R)); \
1230}
1231
1232static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1233{
1234 struct ixgbe_reg_test *test;
1235 u32 value, before, after;
1236 u32 i, toggle;
1237
bd508178
AD		 1238 switch (adapter->hw.mac.type) {
1239 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1240 toggle = 0x7FFFF3FF;
1241 test = reg_test_82598;
bd508178
AD		 1242 break;
1243 case ixgbe_mac_82599EB:
1244 toggle = 0x7FFFF30F;
1245 test = reg_test_82599;
1246 break;
1247 default:
1248 *data = 1;
1249 return 1;
1250 break;
da4dd0f7
PWJ		 1251 }
1252
1253 /*
1254 * Because the status register is such a special case,
1255 * we handle it separately from the rest of the register
1256 * tests. Some bits are read-only, some toggle, and some
1257 * are writeable on newer MACs.
1258 */
1259 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1260 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1261 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1262 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1263 if (value != after) {
396e799c
ET		 1264 e_err(drv, "failed STATUS register test got: 0x%08X "
1265 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1266 *data = 1;
1267 return 1;
1268 }
1269 /* restore previous status */
1270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1271
1272 /*
1273 * Perform the remainder of the register test, looping through
1274 * the test table until we either fail or reach the null entry.
1275 */
1276 while (test->reg) {
1277 for (i = 0; i < test->array_len; i++) {
1278 switch (test->test_type) {
1279 case PATTERN_TEST:
1280 REG_PATTERN_TEST(test->reg + (i * 0x40),
1281 test->mask,
1282 test->write);
1283 break;
1284 case SET_READ_TEST:
1285 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1286 test->mask,
1287 test->write);
1288 break;
1289 case WRITE_NO_TEST:
1290 writel(test->write,
1291 (adapter->hw.hw_addr + test->reg)
1292 + (i * 0x40));
1293 break;
1294 case TABLE32_TEST:
1295 REG_PATTERN_TEST(test->reg + (i * 4),
1296 test->mask,
1297 test->write);
1298 break;
1299 case TABLE64_TEST_LO:
1300 REG_PATTERN_TEST(test->reg + (i * 8),
1301 test->mask,
1302 test->write);
1303 break;
1304 case TABLE64_TEST_HI:
1305 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1306 test->mask,
1307 test->write);
1308 break;
1309 }
1310 }
1311 test++;
1312 }
1313
1314 *data = 0;
1315 return 0;
1316}
1317
1318static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1319{
1320 struct ixgbe_hw *hw = &adapter->hw;
1321 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1322 *data = 1;
1323 else
1324 *data = 0;
1325 return *data;
1326}
1327
1328static irqreturn_t ixgbe_test_intr(int irq, void *data)
1329{
1330 struct net_device *netdev = (struct net_device *) data;
1331 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1332
1333 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1334
1335 return IRQ_HANDLED;
1336}
1337
1338static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1339{
1340 struct net_device *netdev = adapter->netdev;
1341 u32 mask, i = 0, shared_int = true;
1342 u32 irq = adapter->pdev->irq;
1343
1344 *data = 0;
1345
1346 /* Hook up test interrupt handler just for this test */
1347 if (adapter->msix_entries) {
1348 /* NOTE: we don't test MSI-X interrupts here, yet */
1349 return 0;
1350 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1351 shared_int = false;
a0607fd3 1352 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1353 netdev)) {
1354 *data = 1;
1355 return -1;
1356 }
a0607fd3 1357 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1358 netdev->name, netdev)) {
1359 shared_int = false;
a0607fd3 1360 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1361 netdev->name, netdev)) {
1362 *data = 1;
1363 return -1;
1364 }
396e799c
ET		 1365 e_info(hw, "testing %s interrupt\n", shared_int ?
1366 "shared" : "unshared");
da4dd0f7
PWJ		 1367
1368 /* Disable all the interrupts */
1369 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1370 msleep(10);
1371
1372 /* Test each interrupt */
1373 for (; i < 10; i++) {
1374 /* Interrupt to test */
1375 mask = 1 << i;
1376
1377 if (!shared_int) {
1378 /*
1379 * Disable the interrupts to be reported in
1380 * the cause register and then force the same
1381 * interrupt and see if one gets posted. If
1382 * an interrupt was posted to the bus, the
1383 * test failed.
1384 */
1385 adapter->test_icr = 0;
1386 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1387 ~mask & 0x00007FFF);
1388 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1389 ~mask & 0x00007FFF);
1390 msleep(10);
1391
1392 if (adapter->test_icr & mask) {
1393 *data = 3;
1394 break;
1395 }
1396 }
1397
1398 /*
1399 * Enable the interrupt to be reported in the cause
1400 * register and then force the same interrupt and see
1401 * if one gets posted. If an interrupt was not posted
1402 * to the bus, the test failed.
1403 */
1404 adapter->test_icr = 0;
1405 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1407 msleep(10);
1408
1409 if (!(adapter->test_icr &mask)) {
1410 *data = 4;
1411 break;
1412 }
1413
1414 if (!shared_int) {
1415 /*
1416 * Disable the other interrupts to be reported in
1417 * the cause register and then force the other
1418 * interrupts and see if any get posted. If
1419 * an interrupt was posted to the bus, the
1420 * test failed.
1421 */
1422 adapter->test_icr = 0;
1423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1424 ~mask & 0x00007FFF);
1425 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1426 ~mask & 0x00007FFF);
1427 msleep(10);
1428
1429 if (adapter->test_icr) {
1430 *data = 5;
1431 break;
1432 }
1433 }
1434 }
1435
1436 /* Disable all the interrupts */
1437 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1438 msleep(10);
1439
1440 /* Unhook test interrupt handler */
1441 free_irq(irq, netdev);
1442
1443 return *data;
1444}
1445
1446static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1447{
1448 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1449 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1450 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1451 u32 reg_ctl;
da4dd0f7
PWJ		 1452
1453 /* shut down the DMA engines now so they can be reinitialized later */
1454
1455 /* first Rx */
1456 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1457 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1458 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
84418e3b 1459 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
da4dd0f7 1460 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
84418e3b 1461 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
da4dd0f7
PWJ		 1462
1463 /* now Tx */
84418e3b 1464 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1465 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1466 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1467
bd508178
AD		 1468 switch (hw->mac.type) {
1469 case ixgbe_mac_82599EB:
da4dd0f7
PWJ		 1470 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1471 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1472 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1473 break;
1474 default:
1475 break;
da4dd0f7
PWJ		 1476 }
1477
1478 ixgbe_reset(adapter);
1479
b6ec895e
AD		 1480 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1481 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1482}
1483
1484static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1485{
1486 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1487 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1488 u32 rctl, reg_data;
84418e3b
AD		 1489 int ret_val;
1490 int err;
da4dd0f7
PWJ		 1491
1492 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1493 tx_ring->count = IXGBE_DEFAULT_TXD;
1494 tx_ring->queue_index = 0;
b6ec895e 1495 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1496 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1497 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1498 tx_ring->numa_node = adapter->node;
da4dd0f7 1499
b6ec895e 1500 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1501 if (err)
1502 return 1;
da4dd0f7 1503
bd508178
AD		 1504 switch (adapter->hw.mac.type) {
1505 case ixgbe_mac_82599EB:
da4dd0f7
PWJ		 1506 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1507 reg_data |= IXGBE_DMATXCTL_TE;
1508 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1509 break;
1510 default:
1511 break;
da4dd0f7 1512 }
f4ec443b 1513
84418e3b 1514 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1515
1516 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1517 rx_ring->count = IXGBE_DEFAULT_RXD;
1518 rx_ring->queue_index = 0;
b6ec895e 1519 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1520 rx_ring->netdev = adapter->netdev;
84418e3b
AD		 1521 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1522 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1523 rx_ring->numa_node = adapter->node;
1524
b6ec895e 1525 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1526 if (err) {
da4dd0f7
PWJ		 1527 ret_val = 4;
1528 goto err_nomem;
1529 }
1530
da4dd0f7
PWJ		 1531 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1533
84418e3b 1534 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1535
1536 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1537 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1538
da4dd0f7
PWJ		 1539 return 0;
1540
1541err_nomem:
1542 ixgbe_free_desc_rings(adapter);
1543 return ret_val;
1544}
1545
1546static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1547{
1548 struct ixgbe_hw *hw = &adapter->hw;
1549 u32 reg_data;
1550
1551 /* right now we only support MAC loopback in the driver */
da4dd0f7 1552 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1553 /* Setup MAC loopback */
da4dd0f7
PWJ		 1554 reg_data |= IXGBE_HLREG0_LPBK;
1555 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1556
84418e3b
AD		 1557 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1558 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1559 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1560
da4dd0f7
PWJ		 1561 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1562 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1563 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b
AD		 1565 IXGBE_WRITE_FLUSH(&adapter->hw);
1566 msleep(10);
da4dd0f7
PWJ		 1567
1568 /* Disable Atlas Tx lanes; re-enabled in reset path */
1569 if (hw->mac.type == ixgbe_mac_82598EB) {
1570 u8 atlas;
1571
1572 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1573 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1574 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1575
1576 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1577 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1578 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1579
1580 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1581 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1582 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1583
1584 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1585 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1586 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1587 }
1588
1589 return 0;
1590}
1591
1592static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1593{
1594 u32 reg_data;
1595
1596 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1597 reg_data &= ~IXGBE_HLREG0_LPBK;
1598 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1599}
1600
1601static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1602 unsigned int frame_size)
1603{
1604 memset(skb->data, 0xFF, frame_size);
1605 frame_size &= ~1;
1606 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1607 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1608 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1609}
1610
1611static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1612 unsigned int frame_size)
1613{
1614 frame_size &= ~1;
1615 if (*(skb->data + 3) == 0xFF) {
1616 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1617 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1618 return 0;
1619 }
1620 }
1621 return 13;
1622}
1623
fc77dc3c 1624static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1625 struct ixgbe_ring *tx_ring,
1626 unsigned int size)
1627{
1628 union ixgbe_adv_rx_desc *rx_desc;
1629 struct ixgbe_rx_buffer *rx_buffer_info;
1630 struct ixgbe_tx_buffer *tx_buffer_info;
1631 const int bufsz = rx_ring->rx_buf_len;
1632 u32 staterr;
1633 u16 rx_ntc, tx_ntc, count = 0;
1634
1635 /* initialize next to clean and descriptor values */
1636 rx_ntc = rx_ring->next_to_clean;
1637 tx_ntc = tx_ring->next_to_clean;
1638 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1639 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1640
1641 while (staterr & IXGBE_RXD_STAT_DD) {
1642 /* check Rx buffer */
1643 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1644
1645 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1646 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1647 rx_buffer_info->dma,
1648 bufsz,
1649 DMA_FROM_DEVICE);
1650 rx_buffer_info->dma = 0;
1651
1652 /* verify contents of skb */
1653 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1654 count++;
1655
1656 /* unmap buffer on Tx side */
1657 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1658 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1659
1660 /* increment Rx/Tx next to clean counters */
1661 rx_ntc++;
1662 if (rx_ntc == rx_ring->count)
1663 rx_ntc = 0;
1664 tx_ntc++;
1665 if (tx_ntc == tx_ring->count)
1666 tx_ntc = 0;
1667
1668 /* fetch next descriptor */
1669 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1670 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1671 }
1672
1673 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1674 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1675 rx_ring->next_to_clean = rx_ntc;
1676 tx_ring->next_to_clean = tx_ntc;
1677
1678 return count;
1679}
1680
da4dd0f7
PWJ		 1681static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1682{
1683 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1684 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1685 int i, j, lc, good_cnt, ret_val = 0;
1686 unsigned int size = 1024;
1687 netdev_tx_t tx_ret_val;
1688 struct sk_buff *skb;
1689
1690 /* allocate test skb */
1691 skb = alloc_skb(size, GFP_KERNEL);
1692 if (!skb)
1693 return 11;
da4dd0f7 1694
84418e3b
AD		 1695 /* place data into test skb */
1696 ixgbe_create_lbtest_frame(skb, size);
1697 skb_put(skb, size);
da4dd0f7
PWJ		 1698
1699 /*
1700 * Calculate the loop count based on the largest descriptor ring
1701 * The idea is to wrap the largest ring a number of times using 64
1702 * send/receive pairs during each loop
1703 */
1704
1705 if (rx_ring->count <= tx_ring->count)
1706 lc = ((tx_ring->count / 64) * 2) + 1;
1707 else
1708 lc = ((rx_ring->count / 64) * 2) + 1;
1709
da4dd0f7 1710 for (j = 0; j <= lc; j++) {
84418e3b 1711 /* reset count of good packets */
da4dd0f7 1712 good_cnt = 0;
84418e3b
AD		 1713
1714 /* place 64 packets on the transmit queue*/
1715 for (i = 0; i < 64; i++) {
1716 skb_get(skb);
1717 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1718 adapter,
1719 tx_ring);
1720 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1721 good_cnt++;
84418e3b
AD		 1722 }
1723
da4dd0f7 1724 if (good_cnt != 64) {
84418e3b 1725 ret_val = 12;
da4dd0f7
PWJ		 1726 break;
1727 }
84418e3b
AD		 1728
1729 /* allow 200 milliseconds for packets to go from Tx to Rx */
1730 msleep(200);
1731
fc77dc3c 1732 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1733 if (good_cnt != 64) {
1734 ret_val = 13;
da4dd0f7
PWJ		 1735 break;
1736 }
1737 }
1738
84418e3b
AD		 1739 /* free the original skb */
1740 kfree_skb(skb);
1741
da4dd0f7
PWJ		 1742 return ret_val;
1743}
1744
1745static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1746{
1747 *data = ixgbe_setup_desc_rings(adapter);
1748 if (*data)
1749 goto out;
1750 *data = ixgbe_setup_loopback_test(adapter);
1751 if (*data)
1752 goto err_loopback;
1753 *data = ixgbe_run_loopback_test(adapter);
1754 ixgbe_loopback_cleanup(adapter);
1755
1756err_loopback:
1757 ixgbe_free_desc_rings(adapter);
1758out:
1759 return *data;
1760}
1761
1762static void ixgbe_diag_test(struct net_device *netdev,
1763 struct ethtool_test *eth_test, u64 *data)
1764{
1765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1766 bool if_running = netif_running(netdev);
1767
1768 set_bit(__IXGBE_TESTING, &adapter->state);
1769 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1770 /* Offline tests */
1771
396e799c 1772 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1773
1774 /* Link test performed before hardware reset so autoneg doesn't
1775 * interfere with test result */
1776 if (ixgbe_link_test(adapter, &data[4]))
1777 eth_test->flags |= ETH_TEST_FL_FAILED;
1778
e7d481a6
GR		 1779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1780 int i;
1781 for (i = 0; i < adapter->num_vfs; i++) {
1782 if (adapter->vfinfo[i].clear_to_send) {
1783 netdev_warn(netdev, "%s",
1784 "offline diagnostic is not "
1785 "supported when VFs are "
1786 "present\n");
1787 data[0] = 1;
1788 data[1] = 1;
1789 data[2] = 1;
1790 data[3] = 1;
1791 eth_test->flags |= ETH_TEST_FL_FAILED;
1792 clear_bit(__IXGBE_TESTING,
1793 &adapter->state);
1794 goto skip_ol_tests;
1795 }
1796 }
1797 }
1798
da4dd0f7
PWJ		 1799 if (if_running)
1800 /* indicate we're in test mode */
1801 dev_close(netdev);
1802 else
1803 ixgbe_reset(adapter);
1804
396e799c 1805 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1806 if (ixgbe_reg_test(adapter, &data[0]))
1807 eth_test->flags |= ETH_TEST_FL_FAILED;
1808
1809 ixgbe_reset(adapter);
396e799c 1810 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1811 if (ixgbe_eeprom_test(adapter, &data[1]))
1812 eth_test->flags |= ETH_TEST_FL_FAILED;
1813
1814 ixgbe_reset(adapter);
396e799c 1815 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1816 if (ixgbe_intr_test(adapter, &data[2]))
1817 eth_test->flags |= ETH_TEST_FL_FAILED;
1818
bdbec4b8
GR		 1819 /* If SRIOV or VMDq is enabled then skip MAC
1820 * loopback diagnostic. */
1821 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1822 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1823 e_info(hw, "Skip MAC loopback diagnostic in VT "
1824 "mode\n");
bdbec4b8
GR		 1825 data[3] = 0;
1826 goto skip_loopback;
1827 }
1828
da4dd0f7 1829 ixgbe_reset(adapter);
396e799c 1830 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1831 if (ixgbe_loopback_test(adapter, &data[3]))
1832 eth_test->flags |= ETH_TEST_FL_FAILED;
1833
bdbec4b8 1834skip_loopback:
da4dd0f7
PWJ		 1835 ixgbe_reset(adapter);
1836
1837 clear_bit(__IXGBE_TESTING, &adapter->state);
1838 if (if_running)
1839 dev_open(netdev);
1840 } else {
396e799c 1841 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1842 /* Online tests */
1843 if (ixgbe_link_test(adapter, &data[4]))
1844 eth_test->flags |= ETH_TEST_FL_FAILED;
1845
1846 /* Online tests aren't run; pass by default */
1847 data[0] = 0;
1848 data[1] = 0;
1849 data[2] = 0;
1850 data[3] = 0;
1851
1852 clear_bit(__IXGBE_TESTING, &adapter->state);
1853 }
e7d481a6 1854skip_ol_tests:
da4dd0f7
PWJ		 1855 msleep_interruptible(4 * 1000);
1856}
9a799d71 1857
d6c519e1
AD		 1858static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1859 struct ethtool_wolinfo *wol)
1860{
1861 struct ixgbe_hw *hw = &adapter->hw;
1862 int retval = 1;
1863
1864 switch(hw->device_id) {
1865 case IXGBE_DEV_ID_82599_KX4:
1866 retval = 0;
1867 break;
1868 default:
1869 wol->supported = 0;
d6c519e1
AD		 1870 }
1871
1872 return retval;
1873}
1874
9a799d71 1875static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1876 struct ethtool_wolinfo *wol)
9a799d71 1877{
e63d9762
PW		 1878 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1879
1880 wol->supported = WAKE_UCAST | WAKE_MCAST |
1881 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1882 wol->wolopts = 0;
1883
d6c519e1
AD		 1884 if (ixgbe_wol_exclusion(adapter, wol) ||
1885 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1886 return;
1887
1888 if (adapter->wol & IXGBE_WUFC_EX)
1889 wol->wolopts |= WAKE_UCAST;
1890 if (adapter->wol & IXGBE_WUFC_MC)
1891 wol->wolopts |= WAKE_MCAST;
1892 if (adapter->wol & IXGBE_WUFC_BC)
1893 wol->wolopts |= WAKE_BCAST;
1894 if (adapter->wol & IXGBE_WUFC_MAG)
1895 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1896}
1897
e63d9762
PW		 1898static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1899{
1900 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1901
1902 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1903 return -EOPNOTSUPP;
1904
d6c519e1
AD		 1905 if (ixgbe_wol_exclusion(adapter, wol))
1906 return wol->wolopts ? -EOPNOTSUPP : 0;
1907
e63d9762
PW		 1908 adapter->wol = 0;
1909
1910 if (wol->wolopts & WAKE_UCAST)
1911 adapter->wol |= IXGBE_WUFC_EX;
1912 if (wol->wolopts & WAKE_MCAST)
1913 adapter->wol |= IXGBE_WUFC_MC;
1914 if (wol->wolopts & WAKE_BCAST)
1915 adapter->wol |= IXGBE_WUFC_BC;
1916 if (wol->wolopts & WAKE_MAGIC)
1917 adapter->wol |= IXGBE_WUFC_MAG;
1918
1919 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1920
1921 return 0;
1922}
1923
9a799d71
AK		 1924static int ixgbe_nway_reset(struct net_device *netdev)
1925{
1926 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1927
d4f80882
AV		 1928 if (netif_running(netdev))
1929 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1930
1931 return 0;
1932}
1933
1934static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1935{
1936 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 1937 struct ixgbe_hw *hw = &adapter->hw;
1938 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 1939 u32 i;
1940
1941 if (!data || data > 300)
1942 data = 300;
1943
1944 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 1945 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 1946 msleep_interruptible(200);
c44ade9e 1947 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 1948 msleep_interruptible(200);
1949 }
1950
1951 /* Restore LED settings */
1952 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1953
1954 return 0;
1955}
1956
1957static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 1958 struct ethtool_coalesce *ec)
9a799d71
AK		 1959{
1960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1961
4a0b9ca0 1962 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 1963
1964 /* only valid if in constant ITR mode */
f7554a2b 1965 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 1966 case 0:
1967 /* throttling disabled */
1968 ec->rx_coalesce_usecs = 0;
1969 break;
1970 case 1:
1971 /* dynamic ITR mode */
1972 ec->rx_coalesce_usecs = 1;
1973 break;
1974 default:
1975 /* fixed interrupt rate mode */
f7554a2b 1976 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 1977 break;
1978 }
f7554a2b 1979
cfb3f91a
SN		 1980 /* if in mixed tx/rx queues per vector mode, report only rx settings */
1981 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1982 return 0;
1983
f7554a2b
NS		 1984 /* only valid if in constant ITR mode */
1985 switch (adapter->tx_itr_setting) {
1986 case 0:
1987 /* throttling disabled */
1988 ec->tx_coalesce_usecs = 0;
1989 break;
1990 case 1:
1991 /* dynamic ITR mode */
1992 ec->tx_coalesce_usecs = 1;
1993 break;
1994 default:
1995 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1996 break;
1997 }
1998
9a799d71
AK		 1999 return 0;
2000}
2001
80fba3f4
AD		 2002/*
2003 * this function must be called before setting the new value of
2004 * rx_itr_setting
2005 */
2006static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2007 struct ethtool_coalesce *ec)
2008{
2009 struct net_device *netdev = adapter->netdev;
2010
2011 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2012 return false;
2013
2014 /* if interrupt rate is too high then disable RSC */
2015 if (ec->rx_coalesce_usecs != 1 &&
2016 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2017 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2018 e_info(probe, "rx-usecs set too low, "
2019 "disabling RSC\n");
2020 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2021 return true;
2022 }
2023 } else {
2024 /* check the feature flag value and enable RSC if necessary */
2025 if ((netdev->features & NETIF_F_LRO) &&
2026 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2027 e_info(probe, "rx-usecs set to %d, "
2028 "re-enabling RSC\n",
2029 ec->rx_coalesce_usecs);
2030 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2031 return true;
2032 }
2033 }
2034 return false;
2035}
2036
9a799d71 2037static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2038 struct ethtool_coalesce *ec)
9a799d71
AK		 2039{
2040 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2041 struct ixgbe_q_vector *q_vector;
30efa5a3 2042 int i;
ef021194 2043 bool need_reset = false;
9a799d71 2044
cfb3f91a
SN		 2045 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2046 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2047 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2048 return -EINVAL;
2049
9a799d71 2050 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2051 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2052
2053 if (ec->rx_coalesce_usecs > 1) {
509ee935 2054 /* check the limits */
80fba3f4 2055 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2056 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2057 return -EINVAL;
2058
80fba3f4
AD		 2059 /* check the old value and enable RSC if necessary */
2060 need_reset = ixgbe_update_rsc(adapter, ec);
2061
30efa5a3 2062 /* store the value in ints/second */
f7554a2b 2063 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2064
2065 /* static value of interrupt rate */
f7554a2b 2066 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2067 /* clear the lower bit as its used for dynamic state */
f7554a2b 2068 adapter->rx_itr_setting &= ~1;
30efa5a3 2069 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2070 /* check the old value and enable RSC if necessary */
2071 need_reset = ixgbe_update_rsc(adapter, ec);
2072
30efa5a3 2073 /* 1 means dynamic mode */
f7554a2b
NS		 2074 adapter->rx_eitr_param = 20000;
2075 adapter->rx_itr_setting = 1;
30efa5a3 2076 } else {
80fba3f4
AD		 2077 /* check the old value and enable RSC if necessary */
2078 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2079 /*
2080 * any other value means disable eitr, which is best
2081 * served by setting the interrupt rate very high
2082 */
f8d1dcaf 2083 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2084 adapter->rx_itr_setting = 0;
2085 }
2086
2087 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2088 /*
2089 * don't have to worry about max_int as above because
2090 * tx vectors don't do hardware RSC (an rx function)
2091 */
f7554a2b
NS		 2092 /* check the limits */
2093 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2094 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2095 return -EINVAL;
2096
2097 /* store the value in ints/second */
2098 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2099
2100 /* static value of interrupt rate */
2101 adapter->tx_itr_setting = adapter->tx_eitr_param;
2102
2103 /* clear the lower bit as its used for dynamic state */
2104 adapter->tx_itr_setting &= ~1;
2105 } else if (ec->tx_coalesce_usecs == 1) {
2106 /* 1 means dynamic mode */
2107 adapter->tx_eitr_param = 10000;
2108 adapter->tx_itr_setting = 1;
2109 } else {
2110 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2111 adapter->tx_itr_setting = 0;
30efa5a3 2112 }
9a799d71 2113
237057ad
DS		 2114 /* MSI/MSIx Interrupt Mode */
2115 if (adapter->flags &
2116 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2117 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2118 for (i = 0; i < num_vectors; i++) {
2119 q_vector = adapter->q_vector[i];
2120 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2121 /* tx only */
2122 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2123 else
2124 /* rx only or mixed */
f7554a2b 2125 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2126 ixgbe_write_eitr(q_vector);
2127 }
2128 /* Legacy Interrupt Mode */
2129 } else {
2130 q_vector = adapter->q_vector[0];
f7554a2b 2131 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2132 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2133 }
2134
ef021194
JB		 2135 /*
2136 * do reset here at the end to make sure EITR==0 case is handled
2137 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2138 * also locks in RSC enable/disable which requires reset
2139 */
2140 if (need_reset) {
2141 if (netif_running(netdev))
2142 ixgbe_reinit_locked(adapter);
2143 else
2144 ixgbe_reset(adapter);
2145 }
2146
9a799d71
AK		 2147 return 0;
2148}
2149
f8212f97
AD		 2150static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2151{
2152 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2153 bool need_reset = false;
1437ce39 2154 int rc;
f8212f97 2155
f62bbb5e
JG		 2156#ifdef CONFIG_IXGBE_DCB
2157 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2158 !(data & ETH_FLAG_RXVLAN))
2159 return -EINVAL;
2160#endif
2161
2162 need_reset = (data & ETH_FLAG_RXVLAN) !=
2163 (netdev->features & NETIF_F_HW_VLAN_RX);
2164
2165 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO |
2166 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
1437ce39
BH		 2167 if (rc)
2168 return rc;
f8212f97 2169
f8212f97 2170 /* if state changes we need to update adapter->flags and reset */
80fba3f4
AD		 2171 if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
2172 (!!(data & ETH_FLAG_LRO) !=
2173 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2174 if ((data & ETH_FLAG_LRO) &&
2175 (!adapter->rx_itr_setting ||
2176 (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
2177 e_info(probe, "rx-usecs set too low, "
2178 "not enabling RSC.\n");
2179 } else {
f8d1dcaf
JB		 2180 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2181 switch (adapter->hw.mac.type) {
2182 case ixgbe_mac_82599EB:
2183 need_reset = true;
2184 break;
2185 default:
2186 break;
2187 }
f8d1dcaf 2188 }
9a713e7c
PW		 2189 }
2190
2191 /*
2192 * Check if Flow Director n-tuple support was enabled or disabled. If
2193 * the state changed, we need to reset.
2194 */
2195 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2196 (!(data & ETH_FLAG_NTUPLE))) {
2197 /* turn off Flow Director perfect, set hash and reset */
2198 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2199 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2200 need_reset = true;
2201 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2202 (data & ETH_FLAG_NTUPLE)) {
2203 /* turn off Flow Director hash, enable perfect and reset */
2204 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2205 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2206 need_reset = true;
2207 } else {
2208 /* no state change */
2209 }
2210
2211 if (need_reset) {
f8212f97
AD		 2212 if (netif_running(netdev))
2213 ixgbe_reinit_locked(adapter);
2214 else
2215 ixgbe_reset(adapter);
2216 }
9a713e7c 2217
f8212f97 2218 return 0;
9a713e7c
PW		 2219}
2220
2221static int ixgbe_set_rx_ntuple(struct net_device *dev,
2222 struct ethtool_rx_ntuple *cmd)
2223{
2224 struct ixgbe_adapter *adapter = netdev_priv(dev);
2225 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2226 struct ixgbe_atr_input input_struct;
2227 struct ixgbe_atr_input_masks input_masks;
2228 int target_queue;
2229
2230 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2231 return -EOPNOTSUPP;
2232
2233 /*
2234 * Don't allow programming if the action is a queue greater than
2235 * the number of online Tx queues.
2236 */
2237 if ((fs.action >= adapter->num_tx_queues) ||
2238 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2239 return -EINVAL;
2240
2241 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2242 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2243
2244 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2245 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2246 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2247 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2248 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2249 /* only use the lowest 2 bytes for flex bytes */
2250 input_masks.data_mask = (fs.data_mask & 0xffff);
2251
2252 switch (fs.flow_type) {
2253 case TCP_V4_FLOW:
2254 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2255 break;
2256 case UDP_V4_FLOW:
2257 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2258 break;
2259 case SCTP_V4_FLOW:
2260 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2261 break;
2262 default:
2263 return -1;
2264 }
f8212f97 2265
9a713e7c
PW		 2266 /* Mask bits from the inputs based on user-supplied mask */
2267 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2268 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2269 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2270 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2271 /* 82599 expects these to be byte-swapped for perfect filtering */
2272 ixgbe_atr_set_src_port_82599(&input_struct,
2273 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2274 ixgbe_atr_set_dst_port_82599(&input_struct,
2275 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2276
2277 /* VLAN and Flex bytes are either completely masked or not */
2278 if (!fs.vlan_tag_mask)
2279 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2280
2281 if (!input_masks.data_mask)
2282 /* make sure we only use the first 2 bytes of user data */
2283 ixgbe_atr_set_flex_byte_82599(&input_struct,
2284 (fs.data & 0xffff));
2285
2286 /* determine if we need to drop or route the packet */
2287 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2288 target_queue = MAX_RX_QUEUES - 1;
2289 else
2290 target_queue = fs.action;
2291
2292 spin_lock(&adapter->fdir_perfect_lock);
2293 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2294 &input_masks, 0, target_queue);
2295 spin_unlock(&adapter->fdir_perfect_lock);
2296
2297 return 0;
f8212f97 2298}
9a799d71 2299
b9804972 2300static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2301 .get_settings = ixgbe_get_settings,
2302 .set_settings = ixgbe_set_settings,
2303 .get_drvinfo = ixgbe_get_drvinfo,
2304 .get_regs_len = ixgbe_get_regs_len,
2305 .get_regs = ixgbe_get_regs,
2306 .get_wol = ixgbe_get_wol,
e63d9762 2307 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2308 .nway_reset = ixgbe_nway_reset,
2309 .get_link = ethtool_op_get_link,
2310 .get_eeprom_len = ixgbe_get_eeprom_len,
2311 .get_eeprom = ixgbe_get_eeprom,
2312 .get_ringparam = ixgbe_get_ringparam,
2313 .set_ringparam = ixgbe_set_ringparam,
2314 .get_pauseparam = ixgbe_get_pauseparam,
2315 .set_pauseparam = ixgbe_set_pauseparam,
2316 .get_rx_csum = ixgbe_get_rx_csum,
2317 .set_rx_csum = ixgbe_set_rx_csum,
2318 .get_tx_csum = ixgbe_get_tx_csum,
2319 .set_tx_csum = ixgbe_set_tx_csum,
2320 .get_sg = ethtool_op_get_sg,
2321 .set_sg = ethtool_op_set_sg,
2322 .get_msglevel = ixgbe_get_msglevel,
2323 .set_msglevel = ixgbe_set_msglevel,
2324 .get_tso = ethtool_op_get_tso,
2325 .set_tso = ixgbe_set_tso,
da4dd0f7 2326 .self_test = ixgbe_diag_test,
9a799d71
AK		 2327 .get_strings = ixgbe_get_strings,
2328 .phys_id = ixgbe_phys_id,
b4617240 2329 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2330 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2331 .get_coalesce = ixgbe_get_coalesce,
2332 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2333 .get_flags = ethtool_op_get_flags,
f8212f97 2334 .set_flags = ixgbe_set_flags,
9a713e7c 2335 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2336};
2337
2338void ixgbe_set_ethtool_ops(struct net_device *netdev)
2339{
2340 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2341}
Clone of davem's net-next-2.6 tree