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ixgbe: change mac_type if statements to switch statements
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe_ethtool.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for ixgbe */
29
30#include <linux/types.h>
31#include <linux/module.h>
5a0e3ad6 32#include <linux/slab.h>
9a799d71
AK		 33#include <linux/pci.h>
34#include <linux/netdevice.h>
35#include <linux/ethtool.h>
36#include <linux/vmalloc.h>
37#include <linux/uaccess.h>
38
39#include "ixgbe.h"
40
41
42#define IXGBE_ALL_RAR_ENTRIES 16
43
29c3a050
AK		 44enum {NETDEV_STATS, IXGBE_STATS};
45
9a799d71
AK		 46struct ixgbe_stats {
47 char stat_string[ETH_GSTRING_LEN];
29c3a050 48 int type;
9a799d71
AK		 49 int sizeof_stat;
50 int stat_offset;
51};
52
29c3a050
AK		 53#define IXGBE_STAT(m) IXGBE_STATS, \
54 sizeof(((struct ixgbe_adapter *)0)->m), \
55 offsetof(struct ixgbe_adapter, m)
56#define IXGBE_NETDEV_STAT(m) NETDEV_STATS, \
55bad823
ED		 57 sizeof(((struct rtnl_link_stats64 *)0)->m), \
58 offsetof(struct rtnl_link_stats64, m)
29c3a050 59
9a799d71 60static struct ixgbe_stats ixgbe_gstrings_stats[] = {
55bad823
ED		 61 {"rx_packets", IXGBE_NETDEV_STAT(rx_packets)},
62 {"tx_packets", IXGBE_NETDEV_STAT(tx_packets)},
63 {"rx_bytes", IXGBE_NETDEV_STAT(rx_bytes)},
64 {"tx_bytes", IXGBE_NETDEV_STAT(tx_bytes)},
aad71918
BG		 65 {"rx_pkts_nic", IXGBE_STAT(stats.gprc)},
66 {"tx_pkts_nic", IXGBE_STAT(stats.gptc)},
67 {"rx_bytes_nic", IXGBE_STAT(stats.gorc)},
68 {"tx_bytes_nic", IXGBE_STAT(stats.gotc)},
9a799d71
AK		 69 {"lsc_int", IXGBE_STAT(lsc_int)},
70 {"tx_busy", IXGBE_STAT(tx_busy)},
71 {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
55bad823
ED		 72 {"rx_errors", IXGBE_NETDEV_STAT(rx_errors)},
73 {"tx_errors", IXGBE_NETDEV_STAT(tx_errors)},
74 {"rx_dropped", IXGBE_NETDEV_STAT(rx_dropped)},
75 {"tx_dropped", IXGBE_NETDEV_STAT(tx_dropped)},
76 {"multicast", IXGBE_NETDEV_STAT(multicast)},
9a799d71
AK		 77 {"broadcast", IXGBE_STAT(stats.bprc)},
78 {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
55bad823
ED		 79 {"collisions", IXGBE_NETDEV_STAT(collisions)},
80 {"rx_over_errors", IXGBE_NETDEV_STAT(rx_over_errors)},
81 {"rx_crc_errors", IXGBE_NETDEV_STAT(rx_crc_errors)},
82 {"rx_frame_errors", IXGBE_NETDEV_STAT(rx_frame_errors)},
94b982b2
MC		 83 {"hw_rsc_aggregated", IXGBE_STAT(rsc_total_count)},
84 {"hw_rsc_flushed", IXGBE_STAT(rsc_total_flush)},
c4cf55e5
PWJ		 85 {"fdir_match", IXGBE_STAT(stats.fdirmatch)},
86 {"fdir_miss", IXGBE_STAT(stats.fdirmiss)},
55bad823
ED		 87 {"rx_fifo_errors", IXGBE_NETDEV_STAT(rx_fifo_errors)},
88 {"rx_missed_errors", IXGBE_NETDEV_STAT(rx_missed_errors)},
89 {"tx_aborted_errors", IXGBE_NETDEV_STAT(tx_aborted_errors)},
90 {"tx_carrier_errors", IXGBE_NETDEV_STAT(tx_carrier_errors)},
91 {"tx_fifo_errors", IXGBE_NETDEV_STAT(tx_fifo_errors)},
92 {"tx_heartbeat_errors", IXGBE_NETDEV_STAT(tx_heartbeat_errors)},
9a799d71
AK		 93 {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
94 {"tx_restart_queue", IXGBE_STAT(restart_queue)},
95 {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
96 {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
9a799d71
AK		 97 {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
98 {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
99 {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
100 {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
9a799d71 101 {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
9a799d71
AK		 102 {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
103 {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
e8e26350 104 {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
6d45522c
YZ		 105#ifdef IXGBE_FCOE
106 {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
107 {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
108 {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
109 {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
110 {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
111 {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
112#endif /* IXGBE_FCOE */
9a799d71
AK		 113};
114
115#define IXGBE_QUEUE_STATS_LEN \
454d7c9b
WC		 116 ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
117 ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
118 (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
b4617240 119#define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
2f90b865 120#define IXGBE_PB_STATS_LEN ( \
9d2f4720 121 (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
2f90b865
AD		 122 IXGBE_FLAG_DCB_ENABLED) ? \
123 (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
124 sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
125 sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
126 sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
127 / sizeof(u64) : 0)
128#define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
129 IXGBE_PB_STATS_LEN + \
130 IXGBE_QUEUE_STATS_LEN)
9a799d71 131
da4dd0f7
PWJ		 132static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Register test (offline)", "Eeprom test (offline)",
134 "Interrupt test (offline)", "Loopback test (offline)",
135 "Link test (on/offline)"
136};
137#define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
138
9a799d71 139static int ixgbe_get_settings(struct net_device *netdev,
b4617240 140 struct ethtool_cmd *ecmd)
9a799d71
AK		 141{
142 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb
AV		 143 struct ixgbe_hw *hw = &adapter->hw;
144 u32 link_speed = 0;
145 bool link_up;
9a799d71 146
735441fb
AV		 147 ecmd->supported = SUPPORTED_10000baseT_Full;
148 ecmd->autoneg = AUTONEG_ENABLE;
9a799d71 149 ecmd->transceiver = XCVR_EXTERNAL;
74766013 150 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 151 (hw->phy.multispeed_fiber)) {
735441fb 152 ecmd->supported |= (SUPPORTED_1000baseT_Full |
74766013 153 SUPPORTED_Autoneg);
735441fb 154
74766013 155 ecmd->advertising = ADVERTISED_Autoneg;
735441fb
AV		 156 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
157 ecmd->advertising |= ADVERTISED_10000baseT_Full;
158 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
159 ecmd->advertising |= ADVERTISED_1000baseT_Full;
7c5b8323
DS		 160 /*
161 * It's possible that phy.autoneg_advertised may not be
162 * set yet. If so display what the default would be -
163 * both 1G and 10G supported.
164 */
165 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
166 ADVERTISED_10000baseT_Full)))
167 ecmd->advertising |= (ADVERTISED_10000baseT_Full |
168 ADVERTISED_1000baseT_Full);
735441fb 169
74766013
MC		 170 if (hw->phy.media_type == ixgbe_media_type_copper) {
171 ecmd->supported |= SUPPORTED_TP;
172 ecmd->advertising |= ADVERTISED_TP;
173 ecmd->port = PORT_TP;
174 } else {
175 ecmd->supported |= SUPPORTED_FIBRE;
176 ecmd->advertising |= ADVERTISED_FIBRE;
177 ecmd->port = PORT_FIBRE;
178 }
1e336d0f
DS		 179 } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
180 /* Set as FIBRE until SERDES defined in kernel */
46a72b35 181 if (hw->device_id == IXGBE_DEV_ID_82598_BX) {
2f21bdd3
DS		 182 ecmd->supported = (SUPPORTED_1000baseT_Full |
183 SUPPORTED_FIBRE);
184 ecmd->advertising = (ADVERTISED_1000baseT_Full |
185 ADVERTISED_FIBRE);
186 ecmd->port = PORT_FIBRE;
187 ecmd->autoneg = AUTONEG_DISABLE;
46a72b35
MC		 188 } else {
189 ecmd->supported |= (SUPPORTED_1000baseT_Full |
190 SUPPORTED_FIBRE);
191 ecmd->advertising = (ADVERTISED_10000baseT_Full |
192 ADVERTISED_1000baseT_Full |
193 ADVERTISED_FIBRE);
194 ecmd->port = PORT_FIBRE;
1e336d0f 195 }
735441fb
AV		 196 } else {
197 ecmd->supported |= SUPPORTED_FIBRE;
198 ecmd->advertising = (ADVERTISED_10000baseT_Full |
b4617240 199 ADVERTISED_FIBRE);
735441fb 200 ecmd->port = PORT_FIBRE;
c44ade9e 201 ecmd->autoneg = AUTONEG_DISABLE;
735441fb 202 }
9a799d71 203
3b8626ba
PW		 204 /* Get PHY type */
205 switch (adapter->hw.phy.type) {
206 case ixgbe_phy_tn:
207 case ixgbe_phy_cu_unknown:
208 /* Copper 10G-BASET */
209 ecmd->port = PORT_TP;
210 break;
211 case ixgbe_phy_qt:
212 ecmd->port = PORT_FIBRE;
213 break;
214 case ixgbe_phy_nl:
ea0a04df
DS		 215 case ixgbe_phy_sfp_passive_tyco:
216 case ixgbe_phy_sfp_passive_unknown:
3b8626ba
PW		 217 case ixgbe_phy_sfp_ftl:
218 case ixgbe_phy_sfp_avago:
219 case ixgbe_phy_sfp_intel:
220 case ixgbe_phy_sfp_unknown:
221 switch (adapter->hw.phy.sfp_type) {
222 /* SFP+ devices, further checking needed */
223 case ixgbe_sfp_type_da_cu:
224 case ixgbe_sfp_type_da_cu_core0:
225 case ixgbe_sfp_type_da_cu_core1:
226 ecmd->port = PORT_DA;
227 break;
228 case ixgbe_sfp_type_sr:
229 case ixgbe_sfp_type_lr:
230 case ixgbe_sfp_type_srlr_core0:
231 case ixgbe_sfp_type_srlr_core1:
232 ecmd->port = PORT_FIBRE;
233 break;
234 case ixgbe_sfp_type_not_present:
235 ecmd->port = PORT_NONE;
236 break;
cb836a97
DS		 237 case ixgbe_sfp_type_1g_cu_core0:
238 case ixgbe_sfp_type_1g_cu_core1:
239 ecmd->port = PORT_TP;
240 ecmd->supported = SUPPORTED_TP;
241 ecmd->advertising = (ADVERTISED_1000baseT_Full |
242 ADVERTISED_TP);
243 break;
3b8626ba
PW		 244 case ixgbe_sfp_type_unknown:
245 default:
246 ecmd->port = PORT_OTHER;
247 break;
248 }
249 break;
250 case ixgbe_phy_xaui:
251 ecmd->port = PORT_NONE;
252 break;
253 case ixgbe_phy_unknown:
254 case ixgbe_phy_generic:
255 case ixgbe_phy_sfp_unsupported:
256 default:
257 ecmd->port = PORT_OTHER;
258 break;
259 }
260
c44ade9e 261 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
735441fb
AV		 262 if (link_up) {
263 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
b4617240 264 SPEED_10000 : SPEED_1000;
9a799d71
AK		 265 ecmd->duplex = DUPLEX_FULL;
266 } else {
267 ecmd->speed = -1;
268 ecmd->duplex = -1;
269 }
270
9a799d71
AK		 271 return 0;
272}
273
274static int ixgbe_set_settings(struct net_device *netdev,
b4617240 275 struct ethtool_cmd *ecmd)
9a799d71
AK		 276{
277 struct ixgbe_adapter *adapter = netdev_priv(netdev);
735441fb 278 struct ixgbe_hw *hw = &adapter->hw;
0befdb3e 279 u32 advertised, old;
74766013 280 s32 err = 0;
9a799d71 281
74766013 282 if ((hw->phy.media_type == ixgbe_media_type_copper) ||
a3801379 283 (hw->phy.multispeed_fiber)) {
0befdb3e
JB		 284 /* 10000/copper and 1000/copper must autoneg
285 * this function does not support any duplex forcing, but can
286 * limit the advertising of the adapter to only 10000 or 1000 */
287 if (ecmd->autoneg == AUTONEG_DISABLE)
288 return -EINVAL;
289
290 old = hw->phy.autoneg_advertised;
291 advertised = 0;
292 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
293 advertised |= IXGBE_LINK_SPEED_10GB_FULL;
294
295 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
296 advertised |= IXGBE_LINK_SPEED_1GB_FULL;
297
298 if (old == advertised)
74766013 299 return err;
0befdb3e 300 /* this sets the link speed and restarts auto-neg */
74766013 301 hw->mac.autotry_restart = true;
8620a103 302 err = hw->mac.ops.setup_link(hw, advertised, true, true);
0befdb3e 303 if (err) {
396e799c 304 e_info(probe, "setup link failed with code %d\n", err);
8620a103 305 hw->mac.ops.setup_link(hw, old, true, true);
0befdb3e 306 }
74766013
MC		 307 } else {
308 /* in this case we currently only support 10Gb/FULL */
309 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
a3801379 310 (ecmd->advertising != ADVERTISED_10000baseT_Full) ||
74766013
MC		 311 (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
312 return -EINVAL;
9a799d71
AK		 313 }
314
74766013 315 return err;
9a799d71
AK		 316}
317
318static void ixgbe_get_pauseparam(struct net_device *netdev,
b4617240 319 struct ethtool_pauseparam *pause)
9a799d71
AK		 320{
321 struct ixgbe_adapter *adapter = netdev_priv(netdev);
322 struct ixgbe_hw *hw = &adapter->hw;
323
71fd570b
DS		 324 /*
325 * Flow Control Autoneg isn't on if
326 * - we didn't ask for it OR
327 * - it failed, we know this by tx & rx being off
328 */
329 if (hw->fc.disable_fc_autoneg ||
330 (hw->fc.current_mode == ixgbe_fc_none))
331 pause->autoneg = 0;
332 else
333 pause->autoneg = 1;
9a799d71 334
8756924c
PWJ		 335#ifdef CONFIG_DCB
336 if (hw->fc.current_mode == ixgbe_fc_pfc) {
337 pause->rx_pause = 0;
338 pause->tx_pause = 0;
339 }
340
341#endif
0ecc061d 342 if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
9a799d71 343 pause->rx_pause = 1;
0ecc061d 344 } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
9a799d71 345 pause->tx_pause = 1;
0ecc061d 346 } else if (hw->fc.current_mode == ixgbe_fc_full) {
9a799d71
AK		 347 pause->rx_pause = 1;
348 pause->tx_pause = 1;
349 }
350}
351
352static int ixgbe_set_pauseparam(struct net_device *netdev,
b4617240 353 struct ethtool_pauseparam *pause)
9a799d71
AK		 354{
355 struct ixgbe_adapter *adapter = netdev_priv(netdev);
356 struct ixgbe_hw *hw = &adapter->hw;
620fa036 357 struct ixgbe_fc_info fc;
9a799d71 358
264857b8
PWJ		 359#ifdef CONFIG_DCB
360 if (adapter->dcb_cfg.pfc_mode_enable ||
361 ((hw->mac.type == ixgbe_mac_82598EB) &&
362 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
363 return -EINVAL;
364
365#endif
620fa036
MC		 366
367 fc = hw->fc;
368
71fd570b 369 if (pause->autoneg != AUTONEG_ENABLE)
620fa036 370 fc.disable_fc_autoneg = true;
71fd570b 371 else
620fa036 372 fc.disable_fc_autoneg = false;
71fd570b 373
1c4f0ef8 374 if ((pause->rx_pause && pause->tx_pause) || pause->autoneg)
620fa036 375 fc.requested_mode = ixgbe_fc_full;
9a799d71 376 else if (pause->rx_pause && !pause->tx_pause)
620fa036 377 fc.requested_mode = ixgbe_fc_rx_pause;
9a799d71 378 else if (!pause->rx_pause && pause->tx_pause)
620fa036 379 fc.requested_mode = ixgbe_fc_tx_pause;
9a799d71 380 else if (!pause->rx_pause && !pause->tx_pause)
620fa036 381 fc.requested_mode = ixgbe_fc_none;
9c83b070
AV		 382 else
383 return -EINVAL;
9a799d71 384
264857b8 385#ifdef CONFIG_DCB
620fa036 386 adapter->last_lfc_mode = fc.requested_mode;
264857b8 387#endif
620fa036
MC		 388
389 /* if the thing changed then we'll update and use new autoneg */
390 if (memcmp(&fc, &hw->fc, sizeof(struct ixgbe_fc_info))) {
391 hw->fc = fc;
392 if (netif_running(netdev))
393 ixgbe_reinit_locked(adapter);
394 else
395 ixgbe_reset(adapter);
396 }
9a799d71
AK		 397
398 return 0;
399}
400
401static u32 ixgbe_get_rx_csum(struct net_device *netdev)
402{
403 struct ixgbe_adapter *adapter = netdev_priv(netdev);
807540ba 404 return adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED;
9a799d71
AK		 405}
406
407static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
408{
409 struct ixgbe_adapter *adapter = netdev_priv(netdev);
410 if (data)
411 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
412 else
413 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
414
9a799d71
AK		 415 return 0;
416}
417
418static u32 ixgbe_get_tx_csum(struct net_device *netdev)
419{
22f32b7a 420 return (netdev->features & NETIF_F_IP_CSUM) != 0;
9a799d71
AK		 421}
422
423static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
424{
45a5ead0
JB		 425 struct ixgbe_adapter *adapter = netdev_priv(netdev);
426
427 if (data) {
22f32b7a 428 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 429 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
430 netdev->features |= NETIF_F_SCTP_CSUM;
431 } else {
3d3d6d3c 432 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
45a5ead0
JB		 433 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
434 netdev->features &= ~NETIF_F_SCTP_CSUM;
435 }
9a799d71
AK		 436
437 return 0;
438}
439
440static int ixgbe_set_tso(struct net_device *netdev, u32 data)
441{
9a799d71
AK		 442 if (data) {
443 netdev->features |= NETIF_F_TSO;
444 netdev->features |= NETIF_F_TSO6;
445 } else {
446 netdev->features &= ~NETIF_F_TSO;
447 netdev->features &= ~NETIF_F_TSO6;
448 }
449 return 0;
450}
451
452static u32 ixgbe_get_msglevel(struct net_device *netdev)
453{
454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
455 return adapter->msg_enable;
456}
457
458static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
459{
460 struct ixgbe_adapter *adapter = netdev_priv(netdev);
461 adapter->msg_enable = data;
462}
463
464static int ixgbe_get_regs_len(struct net_device *netdev)
465{
466#define IXGBE_REGS_LEN 1128
467 return IXGBE_REGS_LEN * sizeof(u32);
468}
469
470#define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
471
472static void ixgbe_get_regs(struct net_device *netdev,
b4617240 473 struct ethtool_regs *regs, void *p)
9a799d71
AK		 474{
475 struct ixgbe_adapter *adapter = netdev_priv(netdev);
476 struct ixgbe_hw *hw = &adapter->hw;
477 u32 *regs_buff = p;
478 u8 i;
479
480 memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
481
482 regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
483
484 /* General Registers */
485 regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
486 regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
487 regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
488 regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
489 regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
490 regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
491 regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
492 regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
493
494 /* NVM Register */
495 regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
496 regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
497 regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
498 regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
499 regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
500 regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
501 regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
502 regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
503 regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
504 regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
505
506 /* Interrupt */
98c00a1c
JB		 507 /* don't read EICR because it can clear interrupt causes, instead
508 * read EICS which is a shadow but doesn't clear EICR */
509 regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
9a799d71
AK		 510 regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
511 regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
512 regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
513 regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
514 regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
515 regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
516 regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
517 regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
518 regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
c44ade9e 519 regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
9a799d71
AK		 520 regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
521
522 /* Flow Control */
523 regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
524 regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
525 regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
526 regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
527 regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
bd508178
AD		 528 for (i = 0; i < 8; i++) {
529 switch (hw->mac.type) {
530 case ixgbe_mac_82598EB:
531 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
532 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
533 break;
534 case ixgbe_mac_82599EB:
535 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL_82599(i));
536 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH_82599(i));
537 break;
538 default:
539 break;
540 }
541 }
9a799d71
AK		 542 regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
543 regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
544
545 /* Receive DMA */
546 for (i = 0; i < 64; i++)
547 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
548 for (i = 0; i < 64; i++)
549 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
550 for (i = 0; i < 64; i++)
551 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
552 for (i = 0; i < 64; i++)
553 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
554 for (i = 0; i < 64; i++)
555 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
556 for (i = 0; i < 64; i++)
557 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
558 for (i = 0; i < 16; i++)
559 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
560 for (i = 0; i < 16; i++)
561 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
562 regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
563 for (i = 0; i < 8; i++)
564 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
565 regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
566 regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
567
568 /* Receive */
569 regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
570 regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
571 for (i = 0; i < 16; i++)
572 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
573 for (i = 0; i < 16; i++)
574 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
c44ade9e 575 regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
9a799d71
AK		 576 regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
577 regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
578 regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
579 regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
580 regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
581 for (i = 0; i < 8; i++)
582 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
583 for (i = 0; i < 8; i++)
584 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
585 regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
586
587 /* Transmit */
588 for (i = 0; i < 32; i++)
589 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
590 for (i = 0; i < 32; i++)
591 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
592 for (i = 0; i < 32; i++)
593 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
594 for (i = 0; i < 32; i++)
595 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
596 for (i = 0; i < 32; i++)
597 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
598 for (i = 0; i < 32; i++)
599 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
600 for (i = 0; i < 32; i++)
601 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
602 for (i = 0; i < 32; i++)
603 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
604 regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
605 for (i = 0; i < 16; i++)
606 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
607 regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
608 for (i = 0; i < 8; i++)
609 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
610 regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
611
612 /* Wake Up */
613 regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
614 regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
615 regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
616 regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
617 regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
618 regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
619 regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
620 regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
11afc1b1 621 regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
9a799d71 622
9a799d71
AK		 623 regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
624 regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
625 regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
626 regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
627 for (i = 0; i < 8; i++)
628 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
629 for (i = 0; i < 8; i++)
630 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
631 for (i = 0; i < 8; i++)
632 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
633 for (i = 0; i < 8; i++)
634 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
635 for (i = 0; i < 8; i++)
636 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
637 for (i = 0; i < 8; i++)
638 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
639
640 /* Statistics */
641 regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
642 regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
643 regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
644 regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
645 for (i = 0; i < 8; i++)
646 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
647 regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
648 regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
649 regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
650 regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
651 regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
652 regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
653 regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
654 for (i = 0; i < 8; i++)
655 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
656 for (i = 0; i < 8; i++)
657 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
658 for (i = 0; i < 8; i++)
659 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
660 for (i = 0; i < 8; i++)
661 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
662 regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
663 regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
664 regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
665 regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
666 regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
667 regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
668 regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
669 regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
670 regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
671 regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
672 regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
673 regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
674 for (i = 0; i < 8; i++)
675 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
676 regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
677 regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
678 regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
679 regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
680 regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
681 regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
682 regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
683 regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
684 regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
685 regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
686 regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
687 regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
688 regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
689 regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
690 regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
691 regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
692 regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
693 regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
694 regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
695 for (i = 0; i < 16; i++)
696 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
697 for (i = 0; i < 16; i++)
698 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
699 for (i = 0; i < 16; i++)
700 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
701 for (i = 0; i < 16; i++)
702 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
703
704 /* MAC */
705 regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
706 regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
707 regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
708 regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
709 regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
710 regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
711 regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
712 regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
713 regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
714 regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
715 regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
716 regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
717 regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
718 regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
719 regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
720 regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
721 regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
722 regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
723 regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
724 regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
725 regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
726 regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
727 regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
728 regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
729 regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
730 regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
731 regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
732 regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
733 regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
734 regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
735 regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
736 regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
737 regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
738
739 /* Diagnostic */
740 regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
741 for (i = 0; i < 8; i++)
98c00a1c 742 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
9a799d71 743 regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
98c00a1c
JB		 744 for (i = 0; i < 4; i++)
745 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
9a799d71
AK		 746 regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
747 regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
748 for (i = 0; i < 8; i++)
98c00a1c 749 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
9a799d71 750 regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
98c00a1c
JB		 751 for (i = 0; i < 4; i++)
752 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
9a799d71
AK		 753 regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
754 regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
755 regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
756 regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
757 regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
758 regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
759 regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
760 regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
761 regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
762 regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
763 regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
764 for (i = 0; i < 8; i++)
98c00a1c 765 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
9a799d71
AK		 766 regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
767 regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
768 regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
769 regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
770 regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
771 regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
772 regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
773 regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
774 regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
775}
776
777static int ixgbe_get_eeprom_len(struct net_device *netdev)
778{
779 struct ixgbe_adapter *adapter = netdev_priv(netdev);
780 return adapter->hw.eeprom.word_size * 2;
781}
782
783static int ixgbe_get_eeprom(struct net_device *netdev,
b4617240 784 struct ethtool_eeprom *eeprom, u8 *bytes)
9a799d71
AK		 785{
786 struct ixgbe_adapter *adapter = netdev_priv(netdev);
787 struct ixgbe_hw *hw = &adapter->hw;
788 u16 *eeprom_buff;
789 int first_word, last_word, eeprom_len;
790 int ret_val = 0;
791 u16 i;
792
793 if (eeprom->len == 0)
794 return -EINVAL;
795
796 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
797
798 first_word = eeprom->offset >> 1;
799 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
800 eeprom_len = last_word - first_word + 1;
801
802 eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
803 if (!eeprom_buff)
804 return -ENOMEM;
805
806 for (i = 0; i < eeprom_len; i++) {
c44ade9e 807 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
b4617240 808 &eeprom_buff[i])))
9a799d71
AK		 809 break;
810 }
811
812 /* Device's eeprom is always little-endian, word addressable */
813 for (i = 0; i < eeprom_len; i++)
814 le16_to_cpus(&eeprom_buff[i]);
815
816 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
817 kfree(eeprom_buff);
818
819 return ret_val;
820}
821
822static void ixgbe_get_drvinfo(struct net_device *netdev,
b4617240 823 struct ethtool_drvinfo *drvinfo)
9a799d71
AK		 824{
825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
34b0368c 826 char firmware_version[32];
9a799d71 827
083fc582
DS		 828 strncpy(drvinfo->driver, ixgbe_driver_name, sizeof(drvinfo->driver));
829 strncpy(drvinfo->version, ixgbe_driver_version,
830 sizeof(drvinfo->version));
831
832 snprintf(firmware_version, sizeof(firmware_version), "%d.%d-%d",
833 (adapter->eeprom_version & 0xF000) >> 12,
834 (adapter->eeprom_version & 0x0FF0) >> 4,
835 adapter->eeprom_version & 0x000F);
836
837 strncpy(drvinfo->fw_version, firmware_version,
838 sizeof(drvinfo->fw_version));
839 strncpy(drvinfo->bus_info, pci_name(adapter->pdev),
840 sizeof(drvinfo->bus_info));
9a799d71 841 drvinfo->n_stats = IXGBE_STATS_LEN;
da4dd0f7 842 drvinfo->testinfo_len = IXGBE_TEST_LEN;
9a799d71
AK		 843 drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
844}
845
846static void ixgbe_get_ringparam(struct net_device *netdev,
b4617240 847 struct ethtool_ringparam *ring)
9a799d71
AK		 848{
849 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4a0b9ca0
PW		 850 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
851 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
9a799d71
AK		 852
853 ring->rx_max_pending = IXGBE_MAX_RXD;
854 ring->tx_max_pending = IXGBE_MAX_TXD;
855 ring->rx_mini_max_pending = 0;
856 ring->rx_jumbo_max_pending = 0;
857 ring->rx_pending = rx_ring->count;
858 ring->tx_pending = tx_ring->count;
859 ring->rx_mini_pending = 0;
860 ring->rx_jumbo_pending = 0;
861}
862
863static int ixgbe_set_ringparam(struct net_device *netdev,
b4617240 864 struct ethtool_ringparam *ring)
9a799d71
AK		 865{
866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
f9ed8854 867 struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
759884b4 868 int i, err = 0;
c431f97e 869 u32 new_rx_count, new_tx_count;
f9ed8854 870 bool need_update = false;
9a799d71
AK		 871
872 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
873 return -EINVAL;
874
875 new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
876 new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
877 new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
878
879 new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
880 new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
881 new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
882
4a0b9ca0
PW		 883 if ((new_tx_count == adapter->tx_ring[0]->count) &&
884 (new_rx_count == adapter->rx_ring[0]->count)) {
9a799d71
AK		 885 /* nothing to do */
886 return 0;
887 }
888
d4f80882
AV		 889 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
890 msleep(1);
891
759884b4
AD		 892 if (!netif_running(adapter->netdev)) {
893 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 894 adapter->tx_ring[i]->count = new_tx_count;
759884b4 895 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 896 adapter->rx_ring[i]->count = new_rx_count;
759884b4
AD		 897 adapter->tx_ring_count = new_tx_count;
898 adapter->rx_ring_count = new_rx_count;
4a0b9ca0 899 goto clear_reset;
759884b4
AD		 900 }
901
4a0b9ca0 902 temp_tx_ring = vmalloc(adapter->num_tx_queues * sizeof(struct ixgbe_ring));
f9ed8854
MC		 903 if (!temp_tx_ring) {
904 err = -ENOMEM;
4a0b9ca0 905 goto clear_reset;
f9ed8854
MC		 906 }
907
908 if (new_tx_count != adapter->tx_ring_count) {
9a799d71 909 for (i = 0; i < adapter->num_tx_queues; i++) {
4a0b9ca0
PW		 910 memcpy(&temp_tx_ring[i], adapter->tx_ring[i],
911 sizeof(struct ixgbe_ring));
f9ed8854 912 temp_tx_ring[i].count = new_tx_count;
b6ec895e 913 err = ixgbe_setup_tx_resources(&temp_tx_ring[i]);
9a799d71 914 if (err) {
c431f97e
JB		 915 while (i) {
916 i--;
b6ec895e 917 ixgbe_free_tx_resources(&temp_tx_ring[i]);
c431f97e 918 }
4a0b9ca0 919 goto clear_reset;
9a799d71 920 }
9a799d71 921 }
f9ed8854 922 need_update = true;
9a799d71
AK		 923 }
924
4a0b9ca0
PW		 925 temp_rx_ring = vmalloc(adapter->num_rx_queues * sizeof(struct ixgbe_ring));
926 if (!temp_rx_ring) {
f9ed8854
MC		 927 err = -ENOMEM;
928 goto err_setup;
d3fa4721 929 }
9a799d71 930
f9ed8854 931 if (new_rx_count != adapter->rx_ring_count) {
c431f97e 932 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0
PW		 933 memcpy(&temp_rx_ring[i], adapter->rx_ring[i],
934 sizeof(struct ixgbe_ring));
f9ed8854 935 temp_rx_ring[i].count = new_rx_count;
b6ec895e 936 err = ixgbe_setup_rx_resources(&temp_rx_ring[i]);
9a799d71 937 if (err) {
c431f97e
JB		 938 while (i) {
939 i--;
b6ec895e 940 ixgbe_free_rx_resources(&temp_rx_ring[i]);
c431f97e 941 }
9a799d71
AK		 942 goto err_setup;
943 }
9a799d71 944 }
f9ed8854
MC		 945 need_update = true;
946 }
947
948 /* if rings need to be updated, here's the place to do it in one shot */
949 if (need_update) {
759884b4 950 ixgbe_down(adapter);
f9ed8854
MC		 951
952 /* tx */
953 if (new_tx_count != adapter->tx_ring_count) {
4a0b9ca0 954 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 955 ixgbe_free_tx_resources(adapter->tx_ring[i]);
4a0b9ca0
PW		 956 memcpy(adapter->tx_ring[i], &temp_tx_ring[i],
957 sizeof(struct ixgbe_ring));
958 }
f9ed8854
MC		 959 adapter->tx_ring_count = new_tx_count;
960 }
961
962 /* rx */
963 if (new_rx_count != adapter->rx_ring_count) {
4a0b9ca0 964 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 965 ixgbe_free_rx_resources(adapter->rx_ring[i]);
4a0b9ca0
PW		 966 memcpy(adapter->rx_ring[i], &temp_rx_ring[i],
967 sizeof(struct ixgbe_ring));
968 }
f9ed8854
MC		 969 adapter->rx_ring_count = new_rx_count;
970 }
f9ed8854 971 ixgbe_up(adapter);
759884b4 972 }
4a0b9ca0
PW		 973
974 vfree(temp_rx_ring);
f9ed8854 975err_setup:
4a0b9ca0
PW		 976 vfree(temp_tx_ring);
977clear_reset:
d4f80882 978 clear_bit(__IXGBE_RESETTING, &adapter->state);
9a799d71
AK		 979 return err;
980}
981
b9f2c044 982static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
9a799d71 983{
b9f2c044 984 switch (sset) {
da4dd0f7
PWJ		 985 case ETH_SS_TEST:
986 return IXGBE_TEST_LEN;
b9f2c044
JG		 987 case ETH_SS_STATS:
988 return IXGBE_STATS_LEN;
9a713e7c 989 case ETH_SS_NTUPLE_FILTERS:
807540ba
ED		 990 return ETHTOOL_MAX_NTUPLE_LIST_ENTRY *
991 ETHTOOL_MAX_NTUPLE_STRING_PER_ENTRY;
b9f2c044
JG		 992 default:
993 return -EOPNOTSUPP;
994 }
9a799d71
AK		 995}
996
997static void ixgbe_get_ethtool_stats(struct net_device *netdev,
b4617240 998 struct ethtool_stats *stats, u64 *data)
9a799d71
AK		 999{
1000 struct ixgbe_adapter *adapter = netdev_priv(netdev);
28172739
ED		 1001 struct rtnl_link_stats64 temp;
1002 const struct rtnl_link_stats64 *net_stats;
de1036b1
ED		 1003 unsigned int start;
1004 struct ixgbe_ring *ring;
1005 int i, j;
29c3a050 1006 char *p = NULL;
9a799d71
AK		 1007
1008 ixgbe_update_stats(adapter);
28172739 1009 net_stats = dev_get_stats(netdev, &temp);
9a799d71 1010 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
29c3a050
AK		 1011 switch (ixgbe_gstrings_stats[i].type) {
1012 case NETDEV_STATS:
28172739 1013 p = (char *) net_stats +
29c3a050
AK		 1014 ixgbe_gstrings_stats[i].stat_offset;
1015 break;
1016 case IXGBE_STATS:
1017 p = (char *) adapter +
1018 ixgbe_gstrings_stats[i].stat_offset;
1019 break;
1020 }
1021
9a799d71 1022 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
b4617240 1023 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
9a799d71
AK		 1024 }
1025 for (j = 0; j < adapter->num_tx_queues; j++) {
de1036b1
ED		 1026 ring = adapter->tx_ring[j];
1027 do {
1028 start = u64_stats_fetch_begin_bh(&ring->syncp);
1029 data[i] = ring->stats.packets;
1030 data[i+1] = ring->stats.bytes;
1031 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1032 i += 2;
9a799d71
AK		 1033 }
1034 for (j = 0; j < adapter->num_rx_queues; j++) {
de1036b1
ED		 1035 ring = adapter->rx_ring[j];
1036 do {
1037 start = u64_stats_fetch_begin_bh(&ring->syncp);
1038 data[i] = ring->stats.packets;
1039 data[i+1] = ring->stats.bytes;
1040 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
1041 i += 2;
9a799d71 1042 }
2f90b865
AD		 1043 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1044 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
1045 data[i++] = adapter->stats.pxontxc[j];
1046 data[i++] = adapter->stats.pxofftxc[j];
1047 }
1048 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
1049 data[i++] = adapter->stats.pxonrxc[j];
1050 data[i++] = adapter->stats.pxoffrxc[j];
1051 }
1052 }
9a799d71
AK		 1053}
1054
1055static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
b4617240 1056 u8 *data)
9a799d71
AK		 1057{
1058 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e 1059 char *p = (char *)data;
9a799d71
AK		 1060 int i;
1061
1062 switch (stringset) {
da4dd0f7
PWJ		 1063 case ETH_SS_TEST:
1064 memcpy(data, *ixgbe_gstrings_test,
1065 IXGBE_TEST_LEN * ETH_GSTRING_LEN);
1066 break;
9a799d71
AK		 1067 case ETH_SS_STATS:
1068 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
1069 memcpy(p, ixgbe_gstrings_stats[i].stat_string,
1070 ETH_GSTRING_LEN);
1071 p += ETH_GSTRING_LEN;
1072 }
1073 for (i = 0; i < adapter->num_tx_queues; i++) {
1074 sprintf(p, "tx_queue_%u_packets", i);
1075 p += ETH_GSTRING_LEN;
1076 sprintf(p, "tx_queue_%u_bytes", i);
1077 p += ETH_GSTRING_LEN;
1078 }
1079 for (i = 0; i < adapter->num_rx_queues; i++) {
1080 sprintf(p, "rx_queue_%u_packets", i);
1081 p += ETH_GSTRING_LEN;
1082 sprintf(p, "rx_queue_%u_bytes", i);
1083 p += ETH_GSTRING_LEN;
1084 }
2f90b865
AD		 1085 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
1086 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
1087 sprintf(p, "tx_pb_%u_pxon", i);
bfb8cc31
DS		 1088 p += ETH_GSTRING_LEN;
1089 sprintf(p, "tx_pb_%u_pxoff", i);
1090 p += ETH_GSTRING_LEN;
2f90b865
AD		 1091 }
1092 for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
bfb8cc31
DS		 1093 sprintf(p, "rx_pb_%u_pxon", i);
1094 p += ETH_GSTRING_LEN;
1095 sprintf(p, "rx_pb_%u_pxoff", i);
1096 p += ETH_GSTRING_LEN;
2f90b865
AD		 1097 }
1098 }
b4617240 1099 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
9a799d71
AK		 1100 break;
1101 }
1102}
1103
da4dd0f7
PWJ		 1104static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
1105{
1106 struct ixgbe_hw *hw = &adapter->hw;
1107 bool link_up;
1108 u32 link_speed = 0;
1109 *data = 0;
1110
1111 hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1112 if (link_up)
1113 return *data;
1114 else
1115 *data = 1;
1116 return *data;
1117}
1118
1119/* ethtool register test data */
1120struct ixgbe_reg_test {
1121 u16 reg;
1122 u8 array_len;
1123 u8 test_type;
1124 u32 mask;
1125 u32 write;
1126};
1127
1128/* In the hardware, registers are laid out either singly, in arrays
1129 * spaced 0x40 bytes apart, or in contiguous tables. We assume
1130 * most tests take place on arrays or single registers (handled
1131 * as a single-element array) and special-case the tables.
1132 * Table tests are always pattern tests.
1133 *
1134 * We also make provision for some required setup steps by specifying
1135 * registers to be written without any read-back testing.
1136 */
1137
1138#define PATTERN_TEST 1
1139#define SET_READ_TEST 2
1140#define WRITE_NO_TEST 3
1141#define TABLE32_TEST 4
1142#define TABLE64_TEST_LO 5
1143#define TABLE64_TEST_HI 6
1144
1145/* default 82599 register test */
1146static struct ixgbe_reg_test reg_test_82599[] = {
1147 { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1148 { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1149 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1150 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1151 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1152 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1153 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1154 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1155 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1156 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1157 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1158 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1159 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1160 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1161 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1162 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1163 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1164 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1165 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1166 { 0, 0, 0, 0 }
1167};
1168
1169/* default 82598 register test */
1170static struct ixgbe_reg_test reg_test_82598[] = {
1171 { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1172 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1173 { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1174 { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1175 { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1176 { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1177 { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1178 /* Enable all four RX queues before testing. */
1179 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1180 /* RDH is read-only for 82598, only test RDT. */
1181 { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1182 { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1183 { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1184 { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1185 { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1186 { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1187 { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1188 { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1189 { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1190 { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1191 { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1192 { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1193 { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1194 { 0, 0, 0, 0 }
1195};
1196
1197#define REG_PATTERN_TEST(R, M, W) \
1198{ \
1199 u32 pat, val, before; \
1200 const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1201 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { \
1202 before = readl(adapter->hw.hw_addr + R); \
1203 writel((_test[pat] & W), (adapter->hw.hw_addr + R)); \
1204 val = readl(adapter->hw.hw_addr + R); \
1205 if (val != (_test[pat] & W & M)) { \
396e799c
ET		 1206 e_err(drv, "pattern test reg %04X failed: got " \
1207 "0x%08X expected 0x%08X\n", \
849c4542 1208 R, val, (_test[pat] & W & M)); \
da4dd0f7
PWJ		 1209 *data = R; \
1210 writel(before, adapter->hw.hw_addr + R); \
1211 return 1; \
1212 } \
1213 writel(before, adapter->hw.hw_addr + R); \
1214 } \
1215}
1216
1217#define REG_SET_AND_CHECK(R, M, W) \
1218{ \
1219 u32 val, before; \
1220 before = readl(adapter->hw.hw_addr + R); \
1221 writel((W & M), (adapter->hw.hw_addr + R)); \
1222 val = readl(adapter->hw.hw_addr + R); \
1223 if ((W & M) != (val & M)) { \
396e799c
ET		 1224 e_err(drv, "set/check reg %04X test failed: got 0x%08X " \
1225 "expected 0x%08X\n", R, (val & M), (W & M)); \
da4dd0f7
PWJ		 1226 *data = R; \
1227 writel(before, (adapter->hw.hw_addr + R)); \
1228 return 1; \
1229 } \
1230 writel(before, (adapter->hw.hw_addr + R)); \
1231}
1232
1233static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1234{
1235 struct ixgbe_reg_test *test;
1236 u32 value, before, after;
1237 u32 i, toggle;
1238
bd508178
AD		 1239 switch (adapter->hw.mac.type) {
1240 case ixgbe_mac_82598EB:
da4dd0f7
PWJ		 1241 toggle = 0x7FFFF3FF;
1242 test = reg_test_82598;
bd508178
AD		 1243 break;
1244 case ixgbe_mac_82599EB:
1245 toggle = 0x7FFFF30F;
1246 test = reg_test_82599;
1247 break;
1248 default:
1249 *data = 1;
1250 return 1;
1251 break;
da4dd0f7
PWJ		 1252 }
1253
1254 /*
1255 * Because the status register is such a special case,
1256 * we handle it separately from the rest of the register
1257 * tests. Some bits are read-only, some toggle, and some
1258 * are writeable on newer MACs.
1259 */
1260 before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1261 value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1262 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1263 after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1264 if (value != after) {
396e799c
ET		 1265 e_err(drv, "failed STATUS register test got: 0x%08X "
1266 "expected: 0x%08X\n", after, value);
da4dd0f7
PWJ		 1267 *data = 1;
1268 return 1;
1269 }
1270 /* restore previous status */
1271 IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1272
1273 /*
1274 * Perform the remainder of the register test, looping through
1275 * the test table until we either fail or reach the null entry.
1276 */
1277 while (test->reg) {
1278 for (i = 0; i < test->array_len; i++) {
1279 switch (test->test_type) {
1280 case PATTERN_TEST:
1281 REG_PATTERN_TEST(test->reg + (i * 0x40),
1282 test->mask,
1283 test->write);
1284 break;
1285 case SET_READ_TEST:
1286 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1287 test->mask,
1288 test->write);
1289 break;
1290 case WRITE_NO_TEST:
1291 writel(test->write,
1292 (adapter->hw.hw_addr + test->reg)
1293 + (i * 0x40));
1294 break;
1295 case TABLE32_TEST:
1296 REG_PATTERN_TEST(test->reg + (i * 4),
1297 test->mask,
1298 test->write);
1299 break;
1300 case TABLE64_TEST_LO:
1301 REG_PATTERN_TEST(test->reg + (i * 8),
1302 test->mask,
1303 test->write);
1304 break;
1305 case TABLE64_TEST_HI:
1306 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1307 test->mask,
1308 test->write);
1309 break;
1310 }
1311 }
1312 test++;
1313 }
1314
1315 *data = 0;
1316 return 0;
1317}
1318
1319static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1320{
1321 struct ixgbe_hw *hw = &adapter->hw;
1322 if (hw->eeprom.ops.validate_checksum(hw, NULL))
1323 *data = 1;
1324 else
1325 *data = 0;
1326 return *data;
1327}
1328
1329static irqreturn_t ixgbe_test_intr(int irq, void *data)
1330{
1331 struct net_device *netdev = (struct net_device *) data;
1332 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1333
1334 adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1335
1336 return IRQ_HANDLED;
1337}
1338
1339static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1340{
1341 struct net_device *netdev = adapter->netdev;
1342 u32 mask, i = 0, shared_int = true;
1343 u32 irq = adapter->pdev->irq;
1344
1345 *data = 0;
1346
1347 /* Hook up test interrupt handler just for this test */
1348 if (adapter->msix_entries) {
1349 /* NOTE: we don't test MSI-X interrupts here, yet */
1350 return 0;
1351 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1352 shared_int = false;
a0607fd3 1353 if (request_irq(irq, ixgbe_test_intr, 0, netdev->name,
da4dd0f7
PWJ		 1354 netdev)) {
1355 *data = 1;
1356 return -1;
1357 }
a0607fd3 1358 } else if (!request_irq(irq, ixgbe_test_intr, IRQF_PROBE_SHARED,
da4dd0f7
PWJ		 1359 netdev->name, netdev)) {
1360 shared_int = false;
a0607fd3 1361 } else if (request_irq(irq, ixgbe_test_intr, IRQF_SHARED,
da4dd0f7
PWJ		 1362 netdev->name, netdev)) {
1363 *data = 1;
1364 return -1;
1365 }
396e799c
ET		 1366 e_info(hw, "testing %s interrupt\n", shared_int ?
1367 "shared" : "unshared");
da4dd0f7
PWJ		 1368
1369 /* Disable all the interrupts */
1370 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1371 msleep(10);
1372
1373 /* Test each interrupt */
1374 for (; i < 10; i++) {
1375 /* Interrupt to test */
1376 mask = 1 << i;
1377
1378 if (!shared_int) {
1379 /*
1380 * Disable the interrupts to be reported in
1381 * the cause register and then force the same
1382 * interrupt and see if one gets posted. If
1383 * an interrupt was posted to the bus, the
1384 * test failed.
1385 */
1386 adapter->test_icr = 0;
1387 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1388 ~mask & 0x00007FFF);
1389 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1390 ~mask & 0x00007FFF);
1391 msleep(10);
1392
1393 if (adapter->test_icr & mask) {
1394 *data = 3;
1395 break;
1396 }
1397 }
1398
1399 /*
1400 * Enable the interrupt to be reported in the cause
1401 * register and then force the same interrupt and see
1402 * if one gets posted. If an interrupt was not posted
1403 * to the bus, the test failed.
1404 */
1405 adapter->test_icr = 0;
1406 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1407 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1408 msleep(10);
1409
1410 if (!(adapter->test_icr &mask)) {
1411 *data = 4;
1412 break;
1413 }
1414
1415 if (!shared_int) {
1416 /*
1417 * Disable the other interrupts to be reported in
1418 * the cause register and then force the other
1419 * interrupts and see if any get posted. If
1420 * an interrupt was posted to the bus, the
1421 * test failed.
1422 */
1423 adapter->test_icr = 0;
1424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1425 ~mask & 0x00007FFF);
1426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1427 ~mask & 0x00007FFF);
1428 msleep(10);
1429
1430 if (adapter->test_icr) {
1431 *data = 5;
1432 break;
1433 }
1434 }
1435 }
1436
1437 /* Disable all the interrupts */
1438 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1439 msleep(10);
1440
1441 /* Unhook test interrupt handler */
1442 free_irq(irq, netdev);
1443
1444 return *data;
1445}
1446
1447static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1448{
1449 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1450 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1451 struct ixgbe_hw *hw = &adapter->hw;
da4dd0f7 1452 u32 reg_ctl;
da4dd0f7
PWJ		 1453
1454 /* shut down the DMA engines now so they can be reinitialized later */
1455
1456 /* first Rx */
1457 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1458 reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1459 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
84418e3b 1460 reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx));
da4dd0f7 1461 reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
84418e3b 1462 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(rx_ring->reg_idx), reg_ctl);
da4dd0f7
PWJ		 1463
1464 /* now Tx */
84418e3b 1465 reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx));
da4dd0f7 1466 reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
84418e3b
AD		 1467 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(tx_ring->reg_idx), reg_ctl);
1468
bd508178
AD		 1469 switch (hw->mac.type) {
1470 case ixgbe_mac_82599EB:
da4dd0f7
PWJ		 1471 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1472 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1473 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
bd508178
AD		 1474 break;
1475 default:
1476 break;
da4dd0f7
PWJ		 1477 }
1478
1479 ixgbe_reset(adapter);
1480
b6ec895e
AD		 1481 ixgbe_free_tx_resources(&adapter->test_tx_ring);
1482 ixgbe_free_rx_resources(&adapter->test_rx_ring);
da4dd0f7
PWJ		 1483}
1484
1485static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1486{
1487 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1488 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
da4dd0f7 1489 u32 rctl, reg_data;
84418e3b
AD		 1490 int ret_val;
1491 int err;
da4dd0f7
PWJ		 1492
1493 /* Setup Tx descriptor ring and Tx buffers */
84418e3b
AD		 1494 tx_ring->count = IXGBE_DEFAULT_TXD;
1495 tx_ring->queue_index = 0;
b6ec895e 1496 tx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1497 tx_ring->netdev = adapter->netdev;
84418e3b
AD		 1498 tx_ring->reg_idx = adapter->tx_ring[0]->reg_idx;
1499 tx_ring->numa_node = adapter->node;
da4dd0f7 1500
b6ec895e 1501 err = ixgbe_setup_tx_resources(tx_ring);
84418e3b
AD		 1502 if (err)
1503 return 1;
da4dd0f7 1504
bd508178
AD		 1505 switch (adapter->hw.mac.type) {
1506 case ixgbe_mac_82599EB:
da4dd0f7
PWJ		 1507 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1508 reg_data |= IXGBE_DMATXCTL_TE;
1509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
bd508178
AD		 1510 break;
1511 default:
1512 break;
da4dd0f7 1513 }
f4ec443b 1514
84418e3b 1515 ixgbe_configure_tx_ring(adapter, tx_ring);
da4dd0f7
PWJ		 1516
1517 /* Setup Rx Descriptor ring and Rx buffers */
84418e3b
AD		 1518 rx_ring->count = IXGBE_DEFAULT_RXD;
1519 rx_ring->queue_index = 0;
b6ec895e 1520 rx_ring->dev = &adapter->pdev->dev;
fc77dc3c 1521 rx_ring->netdev = adapter->netdev;
84418e3b
AD		 1522 rx_ring->reg_idx = adapter->rx_ring[0]->reg_idx;
1523 rx_ring->rx_buf_len = IXGBE_RXBUFFER_2048;
1524 rx_ring->numa_node = adapter->node;
1525
b6ec895e 1526 err = ixgbe_setup_rx_resources(rx_ring);
84418e3b 1527 if (err) {
da4dd0f7
PWJ		 1528 ret_val = 4;
1529 goto err_nomem;
1530 }
1531
da4dd0f7
PWJ		 1532 rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
da4dd0f7 1534
84418e3b 1535 ixgbe_configure_rx_ring(adapter, rx_ring);
da4dd0f7
PWJ		 1536
1537 rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1538 IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1539
da4dd0f7
PWJ		 1540 return 0;
1541
1542err_nomem:
1543 ixgbe_free_desc_rings(adapter);
1544 return ret_val;
1545}
1546
1547static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1548{
1549 struct ixgbe_hw *hw = &adapter->hw;
1550 u32 reg_data;
1551
1552 /* right now we only support MAC loopback in the driver */
da4dd0f7 1553 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
84418e3b 1554 /* Setup MAC loopback */
da4dd0f7
PWJ		 1555 reg_data |= IXGBE_HLREG0_LPBK;
1556 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1557
84418e3b
AD		 1558 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1559 reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1560 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1561
da4dd0f7
PWJ		 1562 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1563 reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1564 reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1565 IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
84418e3b
AD		 1566 IXGBE_WRITE_FLUSH(&adapter->hw);
1567 msleep(10);
da4dd0f7
PWJ		 1568
1569 /* Disable Atlas Tx lanes; re-enabled in reset path */
1570 if (hw->mac.type == ixgbe_mac_82598EB) {
1571 u8 atlas;
1572
1573 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1574 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1575 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1576
1577 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1578 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1579 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1580
1581 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1582 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1583 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1584
1585 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1586 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1587 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1588 }
1589
1590 return 0;
1591}
1592
1593static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1594{
1595 u32 reg_data;
1596
1597 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1598 reg_data &= ~IXGBE_HLREG0_LPBK;
1599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1600}
1601
1602static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1603 unsigned int frame_size)
1604{
1605 memset(skb->data, 0xFF, frame_size);
1606 frame_size &= ~1;
1607 memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1608 memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1609 memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1610}
1611
1612static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1613 unsigned int frame_size)
1614{
1615 frame_size &= ~1;
1616 if (*(skb->data + 3) == 0xFF) {
1617 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1618 (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1619 return 0;
1620 }
1621 }
1622 return 13;
1623}
1624
fc77dc3c 1625static u16 ixgbe_clean_test_rings(struct ixgbe_ring *rx_ring,
84418e3b
AD		 1626 struct ixgbe_ring *tx_ring,
1627 unsigned int size)
1628{
1629 union ixgbe_adv_rx_desc *rx_desc;
1630 struct ixgbe_rx_buffer *rx_buffer_info;
1631 struct ixgbe_tx_buffer *tx_buffer_info;
1632 const int bufsz = rx_ring->rx_buf_len;
1633 u32 staterr;
1634 u16 rx_ntc, tx_ntc, count = 0;
1635
1636 /* initialize next to clean and descriptor values */
1637 rx_ntc = rx_ring->next_to_clean;
1638 tx_ntc = tx_ring->next_to_clean;
1639 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1640 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1641
1642 while (staterr & IXGBE_RXD_STAT_DD) {
1643 /* check Rx buffer */
1644 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1645
1646 /* unmap Rx buffer, will be remapped by alloc_rx_buffers */
b6ec895e 1647 dma_unmap_single(rx_ring->dev,
84418e3b
AD		 1648 rx_buffer_info->dma,
1649 bufsz,
1650 DMA_FROM_DEVICE);
1651 rx_buffer_info->dma = 0;
1652
1653 /* verify contents of skb */
1654 if (!ixgbe_check_lbtest_frame(rx_buffer_info->skb, size))
1655 count++;
1656
1657 /* unmap buffer on Tx side */
1658 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
b6ec895e 1659 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
84418e3b
AD		 1660
1661 /* increment Rx/Tx next to clean counters */
1662 rx_ntc++;
1663 if (rx_ntc == rx_ring->count)
1664 rx_ntc = 0;
1665 tx_ntc++;
1666 if (tx_ntc == tx_ring->count)
1667 tx_ntc = 0;
1668
1669 /* fetch next descriptor */
1670 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, rx_ntc);
1671 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1672 }
1673
1674 /* re-map buffers to ring, store next to clean values */
fc77dc3c 1675 ixgbe_alloc_rx_buffers(rx_ring, count);
84418e3b
AD		 1676 rx_ring->next_to_clean = rx_ntc;
1677 tx_ring->next_to_clean = tx_ntc;
1678
1679 return count;
1680}
1681
da4dd0f7
PWJ		 1682static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1683{
1684 struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1685 struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
84418e3b
AD		 1686 int i, j, lc, good_cnt, ret_val = 0;
1687 unsigned int size = 1024;
1688 netdev_tx_t tx_ret_val;
1689 struct sk_buff *skb;
1690
1691 /* allocate test skb */
1692 skb = alloc_skb(size, GFP_KERNEL);
1693 if (!skb)
1694 return 11;
da4dd0f7 1695
84418e3b
AD		 1696 /* place data into test skb */
1697 ixgbe_create_lbtest_frame(skb, size);
1698 skb_put(skb, size);
da4dd0f7
PWJ		 1699
1700 /*
1701 * Calculate the loop count based on the largest descriptor ring
1702 * The idea is to wrap the largest ring a number of times using 64
1703 * send/receive pairs during each loop
1704 */
1705
1706 if (rx_ring->count <= tx_ring->count)
1707 lc = ((tx_ring->count / 64) * 2) + 1;
1708 else
1709 lc = ((rx_ring->count / 64) * 2) + 1;
1710
da4dd0f7 1711 for (j = 0; j <= lc; j++) {
84418e3b 1712 /* reset count of good packets */
da4dd0f7 1713 good_cnt = 0;
84418e3b
AD		 1714
1715 /* place 64 packets on the transmit queue*/
1716 for (i = 0; i < 64; i++) {
1717 skb_get(skb);
1718 tx_ret_val = ixgbe_xmit_frame_ring(skb,
84418e3b
AD		 1719 adapter,
1720 tx_ring);
1721 if (tx_ret_val == NETDEV_TX_OK)
da4dd0f7 1722 good_cnt++;
84418e3b
AD		 1723 }
1724
da4dd0f7 1725 if (good_cnt != 64) {
84418e3b 1726 ret_val = 12;
da4dd0f7
PWJ		 1727 break;
1728 }
84418e3b
AD		 1729
1730 /* allow 200 milliseconds for packets to go from Tx to Rx */
1731 msleep(200);
1732
fc77dc3c 1733 good_cnt = ixgbe_clean_test_rings(rx_ring, tx_ring, size);
84418e3b
AD		 1734 if (good_cnt != 64) {
1735 ret_val = 13;
da4dd0f7
PWJ		 1736 break;
1737 }
1738 }
1739
84418e3b
AD		 1740 /* free the original skb */
1741 kfree_skb(skb);
1742
da4dd0f7
PWJ		 1743 return ret_val;
1744}
1745
1746static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1747{
1748 *data = ixgbe_setup_desc_rings(adapter);
1749 if (*data)
1750 goto out;
1751 *data = ixgbe_setup_loopback_test(adapter);
1752 if (*data)
1753 goto err_loopback;
1754 *data = ixgbe_run_loopback_test(adapter);
1755 ixgbe_loopback_cleanup(adapter);
1756
1757err_loopback:
1758 ixgbe_free_desc_rings(adapter);
1759out:
1760 return *data;
1761}
1762
1763static void ixgbe_diag_test(struct net_device *netdev,
1764 struct ethtool_test *eth_test, u64 *data)
1765{
1766 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1767 bool if_running = netif_running(netdev);
1768
1769 set_bit(__IXGBE_TESTING, &adapter->state);
1770 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1771 /* Offline tests */
1772
396e799c 1773 e_info(hw, "offline testing starting\n");
da4dd0f7
PWJ		 1774
1775 /* Link test performed before hardware reset so autoneg doesn't
1776 * interfere with test result */
1777 if (ixgbe_link_test(adapter, &data[4]))
1778 eth_test->flags |= ETH_TEST_FL_FAILED;
1779
e7d481a6
GR		 1780 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
1781 int i;
1782 for (i = 0; i < adapter->num_vfs; i++) {
1783 if (adapter->vfinfo[i].clear_to_send) {
1784 netdev_warn(netdev, "%s",
1785 "offline diagnostic is not "
1786 "supported when VFs are "
1787 "present\n");
1788 data[0] = 1;
1789 data[1] = 1;
1790 data[2] = 1;
1791 data[3] = 1;
1792 eth_test->flags |= ETH_TEST_FL_FAILED;
1793 clear_bit(__IXGBE_TESTING,
1794 &adapter->state);
1795 goto skip_ol_tests;
1796 }
1797 }
1798 }
1799
da4dd0f7
PWJ		 1800 if (if_running)
1801 /* indicate we're in test mode */
1802 dev_close(netdev);
1803 else
1804 ixgbe_reset(adapter);
1805
396e799c 1806 e_info(hw, "register testing starting\n");
da4dd0f7
PWJ		 1807 if (ixgbe_reg_test(adapter, &data[0]))
1808 eth_test->flags |= ETH_TEST_FL_FAILED;
1809
1810 ixgbe_reset(adapter);
396e799c 1811 e_info(hw, "eeprom testing starting\n");
da4dd0f7
PWJ		 1812 if (ixgbe_eeprom_test(adapter, &data[1]))
1813 eth_test->flags |= ETH_TEST_FL_FAILED;
1814
1815 ixgbe_reset(adapter);
396e799c 1816 e_info(hw, "interrupt testing starting\n");
da4dd0f7
PWJ		 1817 if (ixgbe_intr_test(adapter, &data[2]))
1818 eth_test->flags |= ETH_TEST_FL_FAILED;
1819
bdbec4b8
GR		 1820 /* If SRIOV or VMDq is enabled then skip MAC
1821 * loopback diagnostic. */
1822 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
1823 IXGBE_FLAG_VMDQ_ENABLED)) {
396e799c
ET		 1824 e_info(hw, "Skip MAC loopback diagnostic in VT "
1825 "mode\n");
bdbec4b8
GR		 1826 data[3] = 0;
1827 goto skip_loopback;
1828 }
1829
da4dd0f7 1830 ixgbe_reset(adapter);
396e799c 1831 e_info(hw, "loopback testing starting\n");
da4dd0f7
PWJ		 1832 if (ixgbe_loopback_test(adapter, &data[3]))
1833 eth_test->flags |= ETH_TEST_FL_FAILED;
1834
bdbec4b8 1835skip_loopback:
da4dd0f7
PWJ		 1836 ixgbe_reset(adapter);
1837
1838 clear_bit(__IXGBE_TESTING, &adapter->state);
1839 if (if_running)
1840 dev_open(netdev);
1841 } else {
396e799c 1842 e_info(hw, "online testing starting\n");
da4dd0f7
PWJ		 1843 /* Online tests */
1844 if (ixgbe_link_test(adapter, &data[4]))
1845 eth_test->flags |= ETH_TEST_FL_FAILED;
1846
1847 /* Online tests aren't run; pass by default */
1848 data[0] = 0;
1849 data[1] = 0;
1850 data[2] = 0;
1851 data[3] = 0;
1852
1853 clear_bit(__IXGBE_TESTING, &adapter->state);
1854 }
e7d481a6 1855skip_ol_tests:
da4dd0f7
PWJ		 1856 msleep_interruptible(4 * 1000);
1857}
9a799d71 1858
d6c519e1
AD		 1859static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1860 struct ethtool_wolinfo *wol)
1861{
1862 struct ixgbe_hw *hw = &adapter->hw;
1863 int retval = 1;
1864
1865 switch(hw->device_id) {
1866 case IXGBE_DEV_ID_82599_KX4:
1867 retval = 0;
1868 break;
1869 default:
1870 wol->supported = 0;
d6c519e1
AD		 1871 }
1872
1873 return retval;
1874}
1875
9a799d71 1876static void ixgbe_get_wol(struct net_device *netdev,
b4617240 1877 struct ethtool_wolinfo *wol)
9a799d71 1878{
e63d9762
PW		 1879 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1880
1881 wol->supported = WAKE_UCAST | WAKE_MCAST |
1882 WAKE_BCAST | WAKE_MAGIC;
9a799d71
AK		 1883 wol->wolopts = 0;
1884
d6c519e1
AD		 1885 if (ixgbe_wol_exclusion(adapter, wol) ||
1886 !device_can_wakeup(&adapter->pdev->dev))
e63d9762
PW		 1887 return;
1888
1889 if (adapter->wol & IXGBE_WUFC_EX)
1890 wol->wolopts |= WAKE_UCAST;
1891 if (adapter->wol & IXGBE_WUFC_MC)
1892 wol->wolopts |= WAKE_MCAST;
1893 if (adapter->wol & IXGBE_WUFC_BC)
1894 wol->wolopts |= WAKE_BCAST;
1895 if (adapter->wol & IXGBE_WUFC_MAG)
1896 wol->wolopts |= WAKE_MAGIC;
9a799d71
AK		 1897}
1898
e63d9762
PW		 1899static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1900{
1901 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1902
1903 if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1904 return -EOPNOTSUPP;
1905
d6c519e1
AD		 1906 if (ixgbe_wol_exclusion(adapter, wol))
1907 return wol->wolopts ? -EOPNOTSUPP : 0;
1908
e63d9762
PW		 1909 adapter->wol = 0;
1910
1911 if (wol->wolopts & WAKE_UCAST)
1912 adapter->wol |= IXGBE_WUFC_EX;
1913 if (wol->wolopts & WAKE_MCAST)
1914 adapter->wol |= IXGBE_WUFC_MC;
1915 if (wol->wolopts & WAKE_BCAST)
1916 adapter->wol |= IXGBE_WUFC_BC;
1917 if (wol->wolopts & WAKE_MAGIC)
1918 adapter->wol |= IXGBE_WUFC_MAG;
1919
1920 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1921
1922 return 0;
1923}
1924
9a799d71
AK		 1925static int ixgbe_nway_reset(struct net_device *netdev)
1926{
1927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1928
d4f80882
AV		 1929 if (netif_running(netdev))
1930 ixgbe_reinit_locked(adapter);
9a799d71
AK		 1931
1932 return 0;
1933}
1934
1935static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1936{
1937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
c44ade9e
JB		 1938 struct ixgbe_hw *hw = &adapter->hw;
1939 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
9a799d71
AK		 1940 u32 i;
1941
1942 if (!data || data > 300)
1943 data = 300;
1944
1945 for (i = 0; i < (data * 1000); i += 400) {
c44ade9e 1946 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
9a799d71 1947 msleep_interruptible(200);
c44ade9e 1948 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
9a799d71
AK		 1949 msleep_interruptible(200);
1950 }
1951
1952 /* Restore LED settings */
1953 IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1954
1955 return 0;
1956}
1957
1958static int ixgbe_get_coalesce(struct net_device *netdev,
b4617240 1959 struct ethtool_coalesce *ec)
9a799d71
AK		 1960{
1961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1962
4a0b9ca0 1963 ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0]->work_limit;
30efa5a3
JB		 1964
1965 /* only valid if in constant ITR mode */
f7554a2b 1966 switch (adapter->rx_itr_setting) {
30efa5a3
JB		 1967 case 0:
1968 /* throttling disabled */
1969 ec->rx_coalesce_usecs = 0;
1970 break;
1971 case 1:
1972 /* dynamic ITR mode */
1973 ec->rx_coalesce_usecs = 1;
1974 break;
1975 default:
1976 /* fixed interrupt rate mode */
f7554a2b 1977 ec->rx_coalesce_usecs = 1000000/adapter->rx_eitr_param;
30efa5a3
JB		 1978 break;
1979 }
f7554a2b 1980
cfb3f91a
SN		 1981 /* if in mixed tx/rx queues per vector mode, report only rx settings */
1982 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count)
1983 return 0;
1984
f7554a2b
NS		 1985 /* only valid if in constant ITR mode */
1986 switch (adapter->tx_itr_setting) {
1987 case 0:
1988 /* throttling disabled */
1989 ec->tx_coalesce_usecs = 0;
1990 break;
1991 case 1:
1992 /* dynamic ITR mode */
1993 ec->tx_coalesce_usecs = 1;
1994 break;
1995 default:
1996 ec->tx_coalesce_usecs = 1000000/adapter->tx_eitr_param;
1997 break;
1998 }
1999
9a799d71
AK		 2000 return 0;
2001}
2002
80fba3f4
AD		 2003/*
2004 * this function must be called before setting the new value of
2005 * rx_itr_setting
2006 */
2007static bool ixgbe_update_rsc(struct ixgbe_adapter *adapter,
2008 struct ethtool_coalesce *ec)
2009{
2010 struct net_device *netdev = adapter->netdev;
2011
2012 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
2013 return false;
2014
2015 /* if interrupt rate is too high then disable RSC */
2016 if (ec->rx_coalesce_usecs != 1 &&
2017 ec->rx_coalesce_usecs <= 1000000/IXGBE_MAX_RSC_INT_RATE) {
2018 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2019 e_info(probe, "rx-usecs set too low, "
2020 "disabling RSC\n");
2021 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
2022 return true;
2023 }
2024 } else {
2025 /* check the feature flag value and enable RSC if necessary */
2026 if ((netdev->features & NETIF_F_LRO) &&
2027 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
2028 e_info(probe, "rx-usecs set to %d, "
2029 "re-enabling RSC\n",
2030 ec->rx_coalesce_usecs);
2031 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
2032 return true;
2033 }
2034 }
2035 return false;
2036}
2037
9a799d71 2038static int ixgbe_set_coalesce(struct net_device *netdev,
b4617240 2039 struct ethtool_coalesce *ec)
9a799d71
AK		 2040{
2041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
237057ad 2042 struct ixgbe_q_vector *q_vector;
30efa5a3 2043 int i;
ef021194 2044 bool need_reset = false;
9a799d71 2045
cfb3f91a
SN		 2046 /* don't accept tx specific changes if we've got mixed RxTx vectors */
2047 if (adapter->q_vector[0]->txr_count && adapter->q_vector[0]->rxr_count
2048 && ec->tx_coalesce_usecs)
f7554a2b
NS		 2049 return -EINVAL;
2050
9a799d71 2051 if (ec->tx_max_coalesced_frames_irq)
4a0b9ca0 2052 adapter->tx_ring[0]->work_limit = ec->tx_max_coalesced_frames_irq;
30efa5a3
JB		 2053
2054 if (ec->rx_coalesce_usecs > 1) {
509ee935 2055 /* check the limits */
80fba3f4 2056 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
509ee935
JB		 2057 (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2058 return -EINVAL;
2059
80fba3f4
AD		 2060 /* check the old value and enable RSC if necessary */
2061 need_reset = ixgbe_update_rsc(adapter, ec);
2062
30efa5a3 2063 /* store the value in ints/second */
f7554a2b 2064 adapter->rx_eitr_param = 1000000/ec->rx_coalesce_usecs;
30efa5a3
JB		 2065
2066 /* static value of interrupt rate */
f7554a2b 2067 adapter->rx_itr_setting = adapter->rx_eitr_param;
509ee935 2068 /* clear the lower bit as its used for dynamic state */
f7554a2b 2069 adapter->rx_itr_setting &= ~1;
30efa5a3 2070 } else if (ec->rx_coalesce_usecs == 1) {
80fba3f4
AD		 2071 /* check the old value and enable RSC if necessary */
2072 need_reset = ixgbe_update_rsc(adapter, ec);
2073
30efa5a3 2074 /* 1 means dynamic mode */
f7554a2b
NS		 2075 adapter->rx_eitr_param = 20000;
2076 adapter->rx_itr_setting = 1;
30efa5a3 2077 } else {
80fba3f4
AD		 2078 /* check the old value and enable RSC if necessary */
2079 need_reset = ixgbe_update_rsc(adapter, ec);
509ee935
JB		 2080 /*
2081 * any other value means disable eitr, which is best
2082 * served by setting the interrupt rate very high
2083 */
f8d1dcaf 2084 adapter->rx_eitr_param = IXGBE_MAX_INT_RATE;
f7554a2b
NS		 2085 adapter->rx_itr_setting = 0;
2086 }
2087
2088 if (ec->tx_coalesce_usecs > 1) {
f8d1dcaf
JB		 2089 /*
2090 * don't have to worry about max_int as above because
2091 * tx vectors don't do hardware RSC (an rx function)
2092 */
f7554a2b
NS		 2093 /* check the limits */
2094 if ((1000000/ec->tx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
2095 (1000000/ec->tx_coalesce_usecs < IXGBE_MIN_INT_RATE))
2096 return -EINVAL;
2097
2098 /* store the value in ints/second */
2099 adapter->tx_eitr_param = 1000000/ec->tx_coalesce_usecs;
2100
2101 /* static value of interrupt rate */
2102 adapter->tx_itr_setting = adapter->tx_eitr_param;
2103
2104 /* clear the lower bit as its used for dynamic state */
2105 adapter->tx_itr_setting &= ~1;
2106 } else if (ec->tx_coalesce_usecs == 1) {
2107 /* 1 means dynamic mode */
2108 adapter->tx_eitr_param = 10000;
2109 adapter->tx_itr_setting = 1;
2110 } else {
2111 adapter->tx_eitr_param = IXGBE_MAX_INT_RATE;
2112 adapter->tx_itr_setting = 0;
30efa5a3 2113 }
9a799d71 2114
237057ad
DS		 2115 /* MSI/MSIx Interrupt Mode */
2116 if (adapter->flags &
2117 (IXGBE_FLAG_MSIX_ENABLED | IXGBE_FLAG_MSI_ENABLED)) {
2118 int num_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2119 for (i = 0; i < num_vectors; i++) {
2120 q_vector = adapter->q_vector[i];
2121 if (q_vector->txr_count && !q_vector->rxr_count)
f7554a2b
NS		 2122 /* tx only */
2123 q_vector->eitr = adapter->tx_eitr_param;
237057ad
DS		 2124 else
2125 /* rx only or mixed */
f7554a2b 2126 q_vector->eitr = adapter->rx_eitr_param;
237057ad
DS		 2127 ixgbe_write_eitr(q_vector);
2128 }
2129 /* Legacy Interrupt Mode */
2130 } else {
2131 q_vector = adapter->q_vector[0];
f7554a2b 2132 q_vector->eitr = adapter->rx_eitr_param;
fe49f04a 2133 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2134 }
2135
ef021194
JB		 2136 /*
2137 * do reset here at the end to make sure EITR==0 case is handled
2138 * correctly w.r.t stopping tx, and changing TXDCTL.WTHRESH settings
2139 * also locks in RSC enable/disable which requires reset
2140 */
2141 if (need_reset) {
2142 if (netif_running(netdev))
2143 ixgbe_reinit_locked(adapter);
2144 else
2145 ixgbe_reset(adapter);
2146 }
2147
9a799d71
AK		 2148 return 0;
2149}
2150
f8212f97
AD		 2151static int ixgbe_set_flags(struct net_device *netdev, u32 data)
2152{
2153 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a713e7c 2154 bool need_reset = false;
1437ce39 2155 int rc;
f8212f97 2156
f62bbb5e
JG		 2157#ifdef CONFIG_IXGBE_DCB
2158 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
2159 !(data & ETH_FLAG_RXVLAN))
2160 return -EINVAL;
2161#endif
2162
2163 need_reset = (data & ETH_FLAG_RXVLAN) !=
2164 (netdev->features & NETIF_F_HW_VLAN_RX);
2165
2166 rc = ethtool_op_set_flags(netdev, data, ETH_FLAG_LRO |
2167 ETH_FLAG_RXVLAN | ETH_FLAG_TXVLAN);
1437ce39
BH		 2168 if (rc)
2169 return rc;
f8212f97 2170
f8212f97 2171 /* if state changes we need to update adapter->flags and reset */
80fba3f4
AD		 2172 if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
2173 (!!(data & ETH_FLAG_LRO) !=
2174 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))) {
2175 if ((data & ETH_FLAG_LRO) &&
2176 (!adapter->rx_itr_setting ||
2177 (adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE))) {
2178 e_info(probe, "rx-usecs set too low, "
2179 "not enabling RSC.\n");
2180 } else {
f8d1dcaf
JB		 2181 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
2182 switch (adapter->hw.mac.type) {
2183 case ixgbe_mac_82599EB:
2184 need_reset = true;
2185 break;
2186 default:
2187 break;
2188 }
f8d1dcaf 2189 }
9a713e7c
PW		 2190 }
2191
2192 /*
2193 * Check if Flow Director n-tuple support was enabled or disabled. If
2194 * the state changed, we need to reset.
2195 */
2196 if ((adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) &&
2197 (!(data & ETH_FLAG_NTUPLE))) {
2198 /* turn off Flow Director perfect, set hash and reset */
2199 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2200 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
2201 need_reset = true;
2202 } else if ((!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) &&
2203 (data & ETH_FLAG_NTUPLE)) {
2204 /* turn off Flow Director hash, enable perfect and reset */
2205 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
2206 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
2207 need_reset = true;
2208 } else {
2209 /* no state change */
2210 }
2211
2212 if (need_reset) {
f8212f97
AD		 2213 if (netif_running(netdev))
2214 ixgbe_reinit_locked(adapter);
2215 else
2216 ixgbe_reset(adapter);
2217 }
9a713e7c 2218
f8212f97 2219 return 0;
9a713e7c
PW		 2220}
2221
2222static int ixgbe_set_rx_ntuple(struct net_device *dev,
2223 struct ethtool_rx_ntuple *cmd)
2224{
2225 struct ixgbe_adapter *adapter = netdev_priv(dev);
2226 struct ethtool_rx_ntuple_flow_spec fs = cmd->fs;
2227 struct ixgbe_atr_input input_struct;
2228 struct ixgbe_atr_input_masks input_masks;
2229 int target_queue;
2230
2231 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2232 return -EOPNOTSUPP;
2233
2234 /*
2235 * Don't allow programming if the action is a queue greater than
2236 * the number of online Tx queues.
2237 */
2238 if ((fs.action >= adapter->num_tx_queues) ||
2239 (fs.action < ETHTOOL_RXNTUPLE_ACTION_DROP))
2240 return -EINVAL;
2241
2242 memset(&input_struct, 0, sizeof(struct ixgbe_atr_input));
2243 memset(&input_masks, 0, sizeof(struct ixgbe_atr_input_masks));
2244
2245 input_masks.src_ip_mask = fs.m_u.tcp_ip4_spec.ip4src;
2246 input_masks.dst_ip_mask = fs.m_u.tcp_ip4_spec.ip4dst;
2247 input_masks.src_port_mask = fs.m_u.tcp_ip4_spec.psrc;
2248 input_masks.dst_port_mask = fs.m_u.tcp_ip4_spec.pdst;
2249 input_masks.vlan_id_mask = fs.vlan_tag_mask;
2250 /* only use the lowest 2 bytes for flex bytes */
2251 input_masks.data_mask = (fs.data_mask & 0xffff);
2252
2253 switch (fs.flow_type) {
2254 case TCP_V4_FLOW:
2255 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_TCP);
2256 break;
2257 case UDP_V4_FLOW:
2258 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_UDP);
2259 break;
2260 case SCTP_V4_FLOW:
2261 ixgbe_atr_set_l4type_82599(&input_struct, IXGBE_ATR_L4TYPE_SCTP);
2262 break;
2263 default:
2264 return -1;
2265 }
f8212f97 2266
9a713e7c
PW		 2267 /* Mask bits from the inputs based on user-supplied mask */
2268 ixgbe_atr_set_src_ipv4_82599(&input_struct,
2269 (fs.h_u.tcp_ip4_spec.ip4src & ~fs.m_u.tcp_ip4_spec.ip4src));
2270 ixgbe_atr_set_dst_ipv4_82599(&input_struct,
2271 (fs.h_u.tcp_ip4_spec.ip4dst & ~fs.m_u.tcp_ip4_spec.ip4dst));
2272 /* 82599 expects these to be byte-swapped for perfect filtering */
2273 ixgbe_atr_set_src_port_82599(&input_struct,
2274 ((ntohs(fs.h_u.tcp_ip4_spec.psrc)) & ~fs.m_u.tcp_ip4_spec.psrc));
2275 ixgbe_atr_set_dst_port_82599(&input_struct,
2276 ((ntohs(fs.h_u.tcp_ip4_spec.pdst)) & ~fs.m_u.tcp_ip4_spec.pdst));
2277
2278 /* VLAN and Flex bytes are either completely masked or not */
2279 if (!fs.vlan_tag_mask)
2280 ixgbe_atr_set_vlan_id_82599(&input_struct, fs.vlan_tag);
2281
2282 if (!input_masks.data_mask)
2283 /* make sure we only use the first 2 bytes of user data */
2284 ixgbe_atr_set_flex_byte_82599(&input_struct,
2285 (fs.data & 0xffff));
2286
2287 /* determine if we need to drop or route the packet */
2288 if (fs.action == ETHTOOL_RXNTUPLE_ACTION_DROP)
2289 target_queue = MAX_RX_QUEUES - 1;
2290 else
2291 target_queue = fs.action;
2292
2293 spin_lock(&adapter->fdir_perfect_lock);
2294 ixgbe_fdir_add_perfect_filter_82599(&adapter->hw, &input_struct,
2295 &input_masks, 0, target_queue);
2296 spin_unlock(&adapter->fdir_perfect_lock);
2297
2298 return 0;
f8212f97 2299}
9a799d71 2300
b9804972 2301static const struct ethtool_ops ixgbe_ethtool_ops = {
9a799d71
AK		 2302 .get_settings = ixgbe_get_settings,
2303 .set_settings = ixgbe_set_settings,
2304 .get_drvinfo = ixgbe_get_drvinfo,
2305 .get_regs_len = ixgbe_get_regs_len,
2306 .get_regs = ixgbe_get_regs,
2307 .get_wol = ixgbe_get_wol,
e63d9762 2308 .set_wol = ixgbe_set_wol,
9a799d71
AK		 2309 .nway_reset = ixgbe_nway_reset,
2310 .get_link = ethtool_op_get_link,
2311 .get_eeprom_len = ixgbe_get_eeprom_len,
2312 .get_eeprom = ixgbe_get_eeprom,
2313 .get_ringparam = ixgbe_get_ringparam,
2314 .set_ringparam = ixgbe_set_ringparam,
2315 .get_pauseparam = ixgbe_get_pauseparam,
2316 .set_pauseparam = ixgbe_set_pauseparam,
2317 .get_rx_csum = ixgbe_get_rx_csum,
2318 .set_rx_csum = ixgbe_set_rx_csum,
2319 .get_tx_csum = ixgbe_get_tx_csum,
2320 .set_tx_csum = ixgbe_set_tx_csum,
2321 .get_sg = ethtool_op_get_sg,
2322 .set_sg = ethtool_op_set_sg,
2323 .get_msglevel = ixgbe_get_msglevel,
2324 .set_msglevel = ixgbe_set_msglevel,
2325 .get_tso = ethtool_op_get_tso,
2326 .set_tso = ixgbe_set_tso,
da4dd0f7 2327 .self_test = ixgbe_diag_test,
9a799d71
AK		 2328 .get_strings = ixgbe_get_strings,
2329 .phys_id = ixgbe_phys_id,
b4617240 2330 .get_sset_count = ixgbe_get_sset_count,
9a799d71
AK		 2331 .get_ethtool_stats = ixgbe_get_ethtool_stats,
2332 .get_coalesce = ixgbe_get_coalesce,
2333 .set_coalesce = ixgbe_set_coalesce,
177db6ff 2334 .get_flags = ethtool_op_get_flags,
f8212f97 2335 .set_flags = ixgbe_set_flags,
9a713e7c 2336 .set_rx_ntuple = ixgbe_set_rx_ntuple,
9a799d71
AK		 2337};
2338
2339void ixgbe_set_ethtool_ops(struct net_device *netdev)
2340{
2341 SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2342}
Clone of davem's net-next-2.6 tree