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ixgbe: add a netdev pointer to the ring structure
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 56#define IXGBE_MAX_TXD 4096
57#define IXGBE_MIN_TXD 64
58
6bacb300 59#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 60#define IXGBE_MAX_RXD 4096
61#define IXGBE_MIN_RXD 64
62
9a799d71 63/* flow control */
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71 65#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
109#define VMDQ_P(p) ((p) + adapter->num_vfs)
110
111struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
116 u16 vlans_enabled;
7f870475 117 bool clear_to_send;
7f01648a 118 bool pf_set_mac;
7f01648a
GR		 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
120 u16 pf_qos;
7f870475
GR		 121};
122
9a799d71
AK		 123/* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125struct ixgbe_tx_buffer {
126 struct sk_buff *skb;
127 dma_addr_t dma;
128 unsigned long time_stamp;
129 u16 length;
130 u16 next_to_watch;
8ad494b0
AD		 131 unsigned int bytecount;
132 u16 gso_segs;
133 u8 mapped_as_page;
9a799d71
AK		 134};
135
136struct ixgbe_rx_buffer {
137 struct sk_buff *skb;
138 dma_addr_t dma;
139 struct page *page;
140 dma_addr_t page_dma;
762f4c57 141 unsigned int page_offset;
9a799d71
AK		 142};
143
144struct ixgbe_queue_stats {
145 u64 packets;
146 u64 bytes;
147};
148
5b7da515
AD		 149struct ixgbe_tx_queue_stats {
150 u64 restart_queue;
151 u64 tx_busy;
152};
153
154struct ixgbe_rx_queue_stats {
155 u64 rsc_count;
156 u64 rsc_flush;
157 u64 non_eop_descs;
158 u64 alloc_rx_page_failed;
159 u64 alloc_rx_buff_failed;
160};
161
9a799d71 162struct ixgbe_ring {
9a799d71 163 void *desc; /* descriptor ring memory */
b6ec895e 164 struct device *dev; /* device for DMA mapping */
fc77dc3c 165 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 166 union {
167 struct ixgbe_tx_buffer *tx_buffer_info;
168 struct ixgbe_rx_buffer *rx_buffer_info;
169 };
ae540af1
JB		 170 u8 atr_sample_rate;
171 u8 atr_count;
172 u16 count; /* amount of descriptors */
173 u16 rx_buf_len;
174 u16 next_to_use;
175 u16 next_to_clean;
176
177 u8 queue_index; /* needed for multiqueue queue management */
9a799d71 178
6e455b89
YZ		 179#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
180 u8 flags; /* per ring feature flags */
84ea2591 181 u8 __iomem *tail;
9a799d71 182
f494e8fa
AV		 183 unsigned int total_bytes;
184 unsigned int total_packets;
9a799d71 185
5dd2d332 186#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 187 /* cpu for tx queue */
188 int cpu;
189#endif
ae540af1
JB		 190
191 u16 work_limit; /* max work per interrupt */
192 u16 reg_idx; /* holds the special value that gets
193 * the hardware register offset
194 * associated with this ring, which is
195 * different for DCB and RSS modes
196 */
197
9a799d71 198 struct ixgbe_queue_stats stats;
de1036b1 199 struct u64_stats_sync syncp;
5b7da515
AD		 200 union {
201 struct ixgbe_tx_queue_stats tx_stats;
202 struct ixgbe_rx_queue_stats rx_stats;
203 };
de1036b1 204 unsigned long reinit_state;
5b7da515 205 int numa_node;
ae540af1
JB		 206 unsigned int size; /* length in bytes */
207 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 208 struct rcu_head rcu;
7ca3bc58 209} ____cacheline_internodealigned_in_smp;
9a799d71 210
c7e4358a
SN		 211enum ixgbe_ring_f_enum {
212 RING_F_NONE = 0,
213 RING_F_DCB,
7f870475 214 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 215 RING_F_RSS,
c4cf55e5 216 RING_F_FDIR,
0331a832
YZ		 217#ifdef IXGBE_FCOE
218 RING_F_FCOE,
219#endif /* IXGBE_FCOE */
c7e4358a
SN		 220
221 RING_F_ARRAY_SIZE /* must be last in enum set */
222};
223
2f90b865 224#define IXGBE_MAX_DCB_INDICES 8
021230d4 225#define IXGBE_MAX_RSS_INDICES 16
7f870475 226#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 227#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 228#ifdef IXGBE_FCOE
229#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 230#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
231#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
232#else
233#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
234#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 235#endif /* IXGBE_FCOE */
021230d4
AV		 236struct ixgbe_ring_feature {
237 int indices;
238 int mask;
7ca3bc58 239} ____cacheline_internodealigned_in_smp;
021230d4 240
021230d4 241
2f90b865
AD		 242#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
243 ? 8 : 1)
244#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
245
021230d4
AV		 246/* MAX_MSIX_Q_VECTORS of these are allocated,
247 * but we only use one per queue-specific vector.
248 */
249struct ixgbe_q_vector {
250 struct ixgbe_adapter *adapter;
fe49f04a
AD		 251 unsigned int v_idx; /* index of q_vector within array, also used for
252 * finding the bit in EICR and friends that
253 * represents the vector for this ring */
021230d4
AV		 254 struct napi_struct napi;
255 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
256 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
257 u8 rxr_count; /* Rx ring count assigned to this vector */
258 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 259 u8 tx_itr;
260 u8 rx_itr;
021230d4 261 u32 eitr;
b25ebfd2 262 cpumask_var_t affinity_mask;
021230d4
AV		 263};
264
9a799d71 265/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 266 * And yes, it's the same math going both ways. The lowest value
267 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 268 */
269#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 270 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 271#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
272
273#define IXGBE_DESC_UNUSED(R) \
274 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
275 (R)->next_to_clean - (R)->next_to_use - 1)
276
277#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 278 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 279#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 280 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 281#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 282 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 283
284#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 285#ifdef IXGBE_FCOE
286/* Use 3K as the baby jumbo frame size for FCoE */
287#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
288#endif /* IXGBE_FCOE */
9a799d71 289
021230d4
AV		 290#define OTHER_VECTOR 1
291#define NON_Q_VECTORS (OTHER_VECTOR)
292
e8e26350
PW		 293#define MAX_MSIX_VECTORS_82599 64
294#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 295#define MAX_MSIX_VECTORS_82598 18
296#define MAX_MSIX_Q_VECTORS_82598 16
297
e8e26350
PW		 298#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
299#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 300
021230d4 301#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 302#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
303
9a799d71
AK		 304/* board specific private data structure */
305struct ixgbe_adapter {
306 struct timer_list watchdog_timer;
f62bbb5e 307 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 308 u16 bd_number;
9a799d71 309 struct work_struct reset_task;
7a921c93 310 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350 311 char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865
AD		 312 struct ixgbe_dcb_config dcb_cfg;
313 struct ixgbe_dcb_config temp_dcb_cfg;
314 u8 dcb_set_bitmap;
264857b8 315 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 316
f494e8fa 317 /* Interrupt Throttle Rate */
f7554a2b
NS		 318 u32 rx_itr_setting;
319 u32 tx_itr_setting;
f494e8fa
AV		 320 u16 eitr_low;
321 u16 eitr_high;
322
9a799d71 323 /* TX */
4a0b9ca0 324 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 325 int num_tx_queues;
9a799d71
AK		 326 u32 tx_timeout_count;
327 bool detect_tx_hung;
328
7ca3bc58
JB		 329 u64 restart_queue;
330 u64 lsc_int;
331
9a799d71 332 /* RX */
4a0b9ca0 333 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 334 int num_rx_queues;
7f870475
GR		 335 int num_rx_pools; /* == num_rx_queues in 82598 */
336 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 337 u64 hw_csum_rx_error;
e8e26350 338 u64 hw_rx_no_dma_resources;
9a799d71 339 u64 non_eop_descs;
021230d4 340 int num_msix_vectors;
eb7f139c 341 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 342 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 343 struct msix_entry *msix_entries;
344
9a799d71
AK		 345 u32 alloc_rx_page_failed;
346 u32 alloc_rx_buff_failed;
347
021230d4
AV		 348 /* Some features need tri-state capability,
349 * thus the additional *_CAPABLE flags.
350 */
9a799d71 351 u32 flags;
96b0e0f6
JB		 352#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
353#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
354#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
355#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
356#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
357#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
358#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
359#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
360#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
361#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
362#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
363#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
364#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 365#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 366#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
367#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
368#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
369#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 370#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 371#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955
JF		 372#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
373#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
374#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
375#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
376#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
377#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
378#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
379#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6 380
df647b5c
PWJ		 381 u32 flags2;
382#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
383#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a 384#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6
JB		 385/* default to trying for four seconds */
386#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 387
388 /* OS defined structs */
389 struct net_device *netdev;
390 struct pci_dev *pdev;
9a799d71 391
da4dd0f7
PWJ		 392 u32 test_icr;
393 struct ixgbe_ring test_tx_ring;
394 struct ixgbe_ring test_rx_ring;
395
9a799d71
AK		 396 /* structs defined in ixgbe_hw.h */
397 struct ixgbe_hw hw;
398 u16 msg_enable;
399 struct ixgbe_hw_stats stats;
021230d4
AV		 400
401 /* Interrupt Throttle Rate */
f7554a2b
NS		 402 u32 rx_eitr_param;
403 u32 tx_eitr_param;
9a799d71
AK		 404
405 unsigned long state;
406 u64 tx_busy;
30efa5a3
JB		 407 unsigned int tx_ring_count;
408 unsigned int rx_ring_count;
cf8280ee
JB		 409
410 u32 link_speed;
411 bool link_up;
412 unsigned long link_check_timeout;
413
414 struct work_struct watchdog_task;
c4900be0
DS		 415 struct work_struct sfp_task;
416 struct timer_list sfp_timer;
e8e26350
PW		 417 struct work_struct multispeed_fiber_task;
418 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 419 u32 fdir_pballoc;
420 u32 atr_sample_rate;
421 spinlock_t fdir_perfect_lock;
422 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 423#ifdef IXGBE_FCOE
424 struct ixgbe_fcoe fcoe;
425#endif /* IXGBE_FCOE */
94b982b2
MC		 426 u64 rsc_total_count;
427 u64 rsc_total_flush;
e8e26350 428 u32 wol;
34b0368c 429 u16 eeprom_version;
7f870475 430
1a6c14a2 431 int node;
119fc60a
MC		 432 struct work_struct check_overtemp_task;
433 u32 interrupt_event;
1a6c14a2 434
7f870475
GR		 435 /* SR-IOV */
436 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
437 unsigned int num_vfs;
438 struct vf_data_storage *vfinfo;
9a799d71
AK		 439};
440
441enum ixbge_state_t {
442 __IXGBE_TESTING,
443 __IXGBE_RESETTING,
c4900be0 444 __IXGBE_DOWN,
c4cf55e5 445 __IXGBE_FDIR_INIT_DONE,
c4900be0 446 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 447};
448
449enum ixgbe_boards {
3957d63d 450 board_82598,
e8e26350 451 board_82599,
9a799d71
AK		 452};
453
3957d63d 454extern struct ixgbe_info ixgbe_82598_info;
e8e26350 455extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 456#ifdef CONFIG_IXGBE_DCB
32953543 457extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 458extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
459 struct ixgbe_dcb_config *dst_dcb_cfg,
460 int tc_max);
461#endif
9a799d71
AK		 462
463extern char ixgbe_driver_name[];
9c8eb720 464extern const char ixgbe_driver_version[];
9a799d71
AK		 465
466extern int ixgbe_up(struct ixgbe_adapter *adapter);
467extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 468extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 469extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 470extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 471extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
472extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
473extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
474extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 475extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
476extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
b4617240 477extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 478extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 479extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 480extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 481 struct ixgbe_adapter *,
482 struct ixgbe_ring *);
b6ec895e 483extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 484 struct ixgbe_tx_buffer *);
fc77dc3c 485extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 486extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
487extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 488extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
489extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
490extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
491extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
492 struct ixgbe_atr_input *input,
493 u8 queue);
9a713e7c
PW		 494extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
495 struct ixgbe_atr_input *input,
496 struct ixgbe_atr_input_masks *input_masks,
497 u16 soft_id, u8 queue);
ffff4772
PWJ		 498extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
499 u16 vlan_id);
500extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
501 u32 src_addr);
502extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
503 u32 dst_addr);
ffff4772
PWJ		 504extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
505 u16 src_port);
506extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
507 u16 dst_port);
508extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
509 u16 flex_byte);
ffff4772
PWJ		 510extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
511 u8 l4type);
7f870475 512extern void ixgbe_set_rx_mode(struct net_device *netdev);
eacd73f7
YZ		 513#ifdef IXGBE_FCOE
514extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
515extern int ixgbe_fso(struct ixgbe_adapter *adapter,
516 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
517 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 518extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
519extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
520 union ixgbe_adv_rx_desc *rx_desc,
521 struct sk_buff *skb);
522extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
523 struct scatterlist *sgl, unsigned int sgc);
524extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 525extern int ixgbe_fcoe_enable(struct net_device *netdev);
526extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 527#ifdef CONFIG_IXGBE_DCB
528extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
529extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
530#endif /* CONFIG_IXGBE_DCB */
61a1fa10 531extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 532#endif /* IXGBE_FCOE */
9a799d71
AK		 533
534#endif /* _IXGBE_H_ */
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