[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h

/*******************************************************************************

  Intel 10 Gigabit PCI Express Linux driver
  Copyright(c) 1999 - 2010 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBE_H_
#define _IXGBE_H_

#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/cpumask.h>
#include <linux/aer.h>
#include <linux/if_vlan.h>

#include "ixgbe_type.h"
#include "ixgbe_common.h"
#include "ixgbe_dcb.h"
#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
#define IXGBE_FCOE
#include "ixgbe_fcoe.h"
#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
#ifdef CONFIG_IXGBE_DCA
#include <linux/dca.h>
#endif

/* common prefix used by pr_<> macros */
#undef pr_fmt
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

/* TX/RX descriptor defines */
#define IXGBE_DEFAULT_TXD		    512
#define IXGBE_MAX_TXD			   4096
#define IXGBE_MIN_TXD			     64

#define IXGBE_DEFAULT_RXD		    512
#define IXGBE_MAX_RXD			   4096
#define IXGBE_MIN_RXD			     64

/* flow control */
#define IXGBE_MIN_FCRTL			   0x40
#define IXGBE_MAX_FCRTL			0x7FF80
#define IXGBE_MIN_FCRTH			  0x600
#define IXGBE_MAX_FCRTH			0x7FFF0
#define IXGBE_DEFAULT_FCPAUSE		 0xFFFF
#define IXGBE_MIN_FCPAUSE		      0
#define IXGBE_MAX_FCPAUSE		 0xFFFF

/* Supported Rx Buffer Sizes */
#define IXGBE_RXBUFFER_512   512    /* Used for packet split */
#define IXGBE_RXBUFFER_2048  2048
#define IXGBE_RXBUFFER_4096  4096
#define IXGBE_RXBUFFER_8192  8192
#define IXGBE_MAX_RXBUFFER   16384  /* largest size for a single descriptor */

/*
 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
 * this adds up to 512 bytes of extra data meaning the smallest allocation
 * we could have is 1K.
 * i.e. RXBUFFER_512 --> size-1024 slab
 */
#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512

#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBE_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_FCOE		(u32)(1 << 4)
#define IXGBE_TX_FLAGS_FSO		(u32)(1 << 5)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK   0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

#define IXGBE_MAX_RSC_INT_RATE          162760

#define IXGBE_MAX_VF_MC_ENTRIES         30
#define IXGBE_MAX_VF_FUNCTIONS          64
#define IXGBE_MAX_VFTA_ENTRIES          128
#define MAX_EMULATION_MAC_ADDRS         16
#define VMDQ_P(p)   ((p) + adapter->num_vfs)

struct vf_data_storage {
	unsigned char vf_mac_addresses[ETH_ALEN];
	u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
	u16 num_vf_mc_hashes;
	u16 default_vf_vlan_id;
	u16 vlans_enabled;
	bool clear_to_send;
	bool pf_set_mac;
	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
	u16 pf_qos;
};

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbe_tx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	unsigned long time_stamp;
	u16 length;
	u16 next_to_watch;
	unsigned int bytecount;
	u16 gso_segs;
	u8 mapped_as_page;
};

struct ixgbe_rx_buffer {
	struct sk_buff *skb;
	dma_addr_t dma;
	struct page *page;
	dma_addr_t page_dma;
	unsigned int page_offset;
};

struct ixgbe_queue_stats {
	u64 packets;
	u64 bytes;
};

struct ixgbe_ring {
	void *desc;			/* descriptor ring memory */
	union {
		struct ixgbe_tx_buffer *tx_buffer_info;
		struct ixgbe_rx_buffer *rx_buffer_info;
	};
	u8 atr_sample_rate;
	u8 atr_count;
	u16 count;			/* amount of descriptors */
	u16 rx_buf_len;
	u16 next_to_use;
	u16 next_to_clean;

	u8 queue_index; /* needed for multiqueue queue management */

#define IXGBE_RING_RX_PS_ENABLED                (u8)(1)
	u8 flags;			/* per ring feature flags */
	u8 __iomem *tail;

	unsigned int total_bytes;
	unsigned int total_packets;

#ifdef CONFIG_IXGBE_DCA
	/* cpu for tx queue */
	int cpu;
#endif

	u16 work_limit;			/* max work per interrupt */
	u16 reg_idx;			/* holds the special value that gets
					 * the hardware register offset
					 * associated with this ring, which is
					 * different for DCB and RSS modes
					 */

	struct ixgbe_queue_stats stats;
	struct u64_stats_sync syncp;
	int numa_node;
	unsigned long reinit_state;
	u64 rsc_count;			/* stat for coalesced packets */
	u64 rsc_flush;			/* stats for flushed packets */
	u32 restart_queue;		/* track tx queue restarts */
	u32 non_eop_descs;		/* track hardware descriptor chaining */

	unsigned int size;		/* length in bytes */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	struct rcu_head rcu;
} ____cacheline_internodealigned_in_smp;

enum ixgbe_ring_f_enum {
	RING_F_NONE = 0,
	RING_F_DCB,
	RING_F_VMDQ,  /* SR-IOV uses the same ring feature */
	RING_F_RSS,
	RING_F_FDIR,
#ifdef IXGBE_FCOE
	RING_F_FCOE,
#endif /* IXGBE_FCOE */

	RING_F_ARRAY_SIZE      /* must be last in enum set */
};

#define IXGBE_MAX_DCB_INDICES   8
#define IXGBE_MAX_RSS_INDICES  16
#define IXGBE_MAX_VMDQ_INDICES 64
#define IXGBE_MAX_FDIR_INDICES 64
#ifdef IXGBE_FCOE
#define IXGBE_MAX_FCOE_INDICES  8
#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
#else
#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
#endif /* IXGBE_FCOE */
struct ixgbe_ring_feature {
	int indices;
	int mask;
} ____cacheline_internodealigned_in_smp;


#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
                              ? 8 : 1)
#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbe_q_vector {
	struct ixgbe_adapter *adapter;
	unsigned int v_idx; /* index of q_vector within array, also used for
	                     * finding the bit in EICR and friends that
	                     * represents the vector for this ring */
	struct napi_struct napi;
	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	u8 rxr_count;     /* Rx ring count assigned to this vector */
	u8 txr_count;     /* Tx ring count assigned to this vector */
	u8 tx_itr;
	u8 rx_itr;
	u32 eitr;
	cpumask_var_t affinity_mask;
};

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

#define IXGBE_DESC_UNUSED(R) \
	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	(R)->next_to_clean - (R)->next_to_use - 1)

#define IXGBE_RX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
#define IXGBE_TX_DESC_ADV(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
#define IXGBE_TX_CTXTDESC_ADV(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE        16128
#ifdef IXGBE_FCOE
/* Use 3K as the baby jumbo frame size for FCoE */
#define IXGBE_FCOE_JUMBO_FRAME_SIZE       3072
#endif /* IXGBE_FCOE */

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_VECTORS_82599 64
#define MAX_MSIX_Q_VECTORS_82599 64
#define MAX_MSIX_VECTORS_82598 18
#define MAX_MSIX_Q_VECTORS_82598 16

#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599

#define MIN_MSIX_Q_VECTORS 2
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbe_adapter {
	struct timer_list watchdog_timer;
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
	u16 bd_number;
	struct work_struct reset_task;
	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
	struct ixgbe_dcb_config dcb_cfg;
	struct ixgbe_dcb_config temp_dcb_cfg;
	u8 dcb_set_bitmap;
	enum ixgbe_fc_mode last_lfc_mode;

	/* Interrupt Throttle Rate */
	u32 rx_itr_setting;
	u32 tx_itr_setting;
	u16 eitr_low;
	u16 eitr_high;

	/* TX */
	struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
	int num_tx_queues;
	u32 tx_timeout_count;
	bool detect_tx_hung;

	u64 restart_queue;
	u64 lsc_int;

	/* RX */
	struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
	int num_rx_queues;
	int num_rx_pools;		/* == num_rx_queues in 82598 */
	int num_rx_queues_per_pool;	/* 1 if 82598, can be many if 82599 */
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	u64 non_eop_descs;
	int num_msix_vectors;
	int max_msix_q_vectors;         /* true count of q_vectors for device */
	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
	struct msix_entry *msix_entries;

	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_RX_CSUM_ENABLED              (u32)(1)
#define IXGBE_FLAG_MSI_CAPABLE                  (u32)(1 << 1)
#define IXGBE_FLAG_MSI_ENABLED                  (u32)(1 << 2)
#define IXGBE_FLAG_MSIX_CAPABLE                 (u32)(1 << 3)
#define IXGBE_FLAG_MSIX_ENABLED                 (u32)(1 << 4)
#define IXGBE_FLAG_RX_1BUF_CAPABLE              (u32)(1 << 6)
#define IXGBE_FLAG_RX_PS_CAPABLE                (u32)(1 << 7)
#define IXGBE_FLAG_RX_PS_ENABLED                (u32)(1 << 8)
#define IXGBE_FLAG_IN_NETPOLL                   (u32)(1 << 9)
#define IXGBE_FLAG_DCA_ENABLED                  (u32)(1 << 10)
#define IXGBE_FLAG_DCA_CAPABLE                  (u32)(1 << 11)
#define IXGBE_FLAG_IMIR_ENABLED                 (u32)(1 << 12)
#define IXGBE_FLAG_MQ_CAPABLE                   (u32)(1 << 13)
#define IXGBE_FLAG_DCB_ENABLED                  (u32)(1 << 14)
#define IXGBE_FLAG_RSS_ENABLED                  (u32)(1 << 16)
#define IXGBE_FLAG_RSS_CAPABLE                  (u32)(1 << 17)
#define IXGBE_FLAG_VMDQ_CAPABLE                 (u32)(1 << 18)
#define IXGBE_FLAG_VMDQ_ENABLED                 (u32)(1 << 19)
#define IXGBE_FLAG_FAN_FAIL_CAPABLE             (u32)(1 << 20)
#define IXGBE_FLAG_NEED_LINK_UPDATE             (u32)(1 << 22)
#define IXGBE_FLAG_IN_SFP_LINK_TASK             (u32)(1 << 23)
#define IXGBE_FLAG_IN_SFP_MOD_TASK              (u32)(1 << 24)
#define IXGBE_FLAG_FDIR_HASH_CAPABLE            (u32)(1 << 25)
#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE         (u32)(1 << 26)
#define IXGBE_FLAG_FCOE_CAPABLE                 (u32)(1 << 27)
#define IXGBE_FLAG_FCOE_ENABLED                 (u32)(1 << 28)
#define IXGBE_FLAG_SRIOV_CAPABLE                (u32)(1 << 29)
#define IXGBE_FLAG_SRIOV_ENABLED                (u32)(1 << 30)

	u32 flags2;
#define IXGBE_FLAG2_RSC_CAPABLE                 (u32)(1)
#define IXGBE_FLAG2_RSC_ENABLED                 (u32)(1 << 1)
#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE         (u32)(1 << 2)
/* default to trying for four seconds */
#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;

	u32 test_icr;
	struct ixgbe_ring test_tx_ring;
	struct ixgbe_ring test_rx_ring;

	/* structs defined in ixgbe_hw.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	struct ixgbe_hw_stats stats;

	/* Interrupt Throttle Rate */
	u32 rx_eitr_param;
	u32 tx_eitr_param;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

	u32 link_speed;
	bool link_up;
	unsigned long link_check_timeout;

	struct work_struct watchdog_task;
	struct work_struct sfp_task;
	struct timer_list sfp_timer;
	struct work_struct multispeed_fiber_task;
	struct work_struct sfp_config_module_task;
	u32 fdir_pballoc;
	u32 atr_sample_rate;
	spinlock_t fdir_perfect_lock;
	struct work_struct fdir_reinit_task;
#ifdef IXGBE_FCOE
	struct ixgbe_fcoe fcoe;
#endif /* IXGBE_FCOE */
	u64 rsc_total_count;
	u64 rsc_total_flush;
	u32 wol;
	u16 eeprom_version;

	int node;
	struct work_struct check_overtemp_task;
	u32 interrupt_event;

	/* SR-IOV */
	DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
	unsigned int num_vfs;
	struct vf_data_storage *vfinfo;
};

enum ixbge_state_t {
	__IXGBE_TESTING,
	__IXGBE_RESETTING,
	__IXGBE_DOWN,
	__IXGBE_FDIR_INIT_DONE,
	__IXGBE_SFP_MODULE_NOT_FOUND
};

enum ixgbe_boards {
	board_82598,
	board_82599,
};

extern struct ixgbe_info ixgbe_82598_info;
extern struct ixgbe_info ixgbe_82599_info;
#ifdef CONFIG_IXGBE_DCB
extern const struct dcbnl_rtnl_ops dcbnl_ops;
extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
                              struct ixgbe_dcb_config *dst_dcb_cfg,
                              int tc_max);
#endif

extern char ixgbe_driver_name[];
extern const char ixgbe_driver_version[];

extern int ixgbe_up(struct ixgbe_adapter *adapter);
extern void ixgbe_down(struct ixgbe_adapter *adapter);
extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
extern void ixgbe_reset(struct ixgbe_adapter *adapter);
extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
extern int ixgbe_setup_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern int ixgbe_setup_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_rx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_free_tx_resources(struct ixgbe_adapter *, struct ixgbe_ring *);
extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
					 struct net_device *,
					 struct ixgbe_adapter *,
					 struct ixgbe_ring *);
extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
                                             struct ixgbe_tx_buffer *);
extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
                                   struct ixgbe_ring *rx_ring,
				   u16 cleaned_count);
extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
extern int ethtool_ioctl(struct ifreq *ifr);
extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
                                                 struct ixgbe_atr_input *input,
                                                 u8 queue);
extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
                                      struct ixgbe_atr_input *input,
                                      struct ixgbe_atr_input_masks *input_masks,
                                      u16 soft_id, u8 queue);
extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
                                       u16 vlan_id);
extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
                                        u32 src_addr);
extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
                                        u32 dst_addr);
extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
                                        u16 src_port);
extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
                                        u16 dst_port);
extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
                                         u16 flex_byte);
extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
                                      u8 l4type);
extern void ixgbe_set_rx_mode(struct net_device *netdev);
#ifdef IXGBE_FCOE
extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fso(struct ixgbe_adapter *adapter,
                     struct ixgbe_ring *tx_ring, struct sk_buff *skb,
                     u32 tx_flags, u8 *hdr_len);
extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
                          union ixgbe_adv_rx_desc *rx_desc,
                          struct sk_buff *skb);
extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
                              struct scatterlist *sgl, unsigned int sgc);
extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
extern int ixgbe_fcoe_enable(struct net_device *netdev);
extern int ixgbe_fcoe_disable(struct net_device *netdev);
#ifdef CONFIG_IXGBE_DCB
extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
#endif /* CONFIG_IXGBE_DCB */
extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
#endif /* IXGBE_FCOE */

#endif /* _IXGBE_H_ */
Commit	Line	Data
9a799d71 AK	1	/*******************************************************************************
	2
	3	Intel 10 Gigabit PCI Express Linux driver
8c47eaa7	4	Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71 AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
9a799d71 AK	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBE_H_
	29	#define _IXGBE_H_
	30
f62bbb5e	31	#include <linux/bitops.h>
9a799d71 AK	32	#include <linux/types.h>
	33	#include <linux/pci.h>
	34	#include <linux/netdevice.h>
b25ebfd2	35	#include <linux/cpumask.h>
6fabd715	36	#include <linux/aer.h>
f62bbb5e	37	#include <linux/if_vlan.h>
9a799d71 AK	38
	39	#include "ixgbe_type.h"
	40	#include "ixgbe_common.h"
2f90b865	41	#include "ixgbe_dcb.h"
eacd73f7 YZ	42	#if defined(CONFIG_FCOE) \|\| defined(CONFIG_FCOE_MODULE)
	43	#define IXGBE_FCOE
	44	#include "ixgbe_fcoe.h"
	45	#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332	46	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	47	#include <linux/dca.h>
bd0362dd JC	48	#endif
9a799d71	49
849c4542 ET	50	/* common prefix used by pr_<> macros */
	51	#undef pr_fmt
	52	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71 AK	53
9a799d71 AK	54	/* TX/RX descriptor defines */
6bacb300	55	#define IXGBE_DEFAULT_TXD 512
9a799d71 AK	56	#define IXGBE_MAX_TXD 4096
	57	#define IXGBE_MIN_TXD 64
	58
6bacb300	59	#define IXGBE_DEFAULT_RXD 512
9a799d71 AK	60	#define IXGBE_MAX_RXD 4096
	61	#define IXGBE_MIN_RXD 64
	62
9a799d71	63	/* flow control */
2b9ade93	64	#define IXGBE_MIN_FCRTL 0x40
9a799d71	65	#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93	66	#define IXGBE_MIN_FCRTH 0x600
9a799d71	67	#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93	68	#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71 AK	69	#define IXGBE_MIN_FCPAUSE 0
	70	#define IXGBE_MAX_FCPAUSE 0xFFFF
	71
	72	/* Supported Rx Buffer Sizes */
13958070	73	#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71	74	#define IXGBE_RXBUFFER_2048 2048
e76678dd AD	75	#define IXGBE_RXBUFFER_4096 4096
e76678dd AD	76	#define IXGBE_RXBUFFER_8192 8192
32344a39	77	#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71	78
13958070 AD	79	/*
	80	* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
	81	* reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
	82	* this adds up to 512 bytes of extra data meaning the smallest allocation
	83	* we could have is 1K.
	84	* i.e. RXBUFFER_512 --> size-1024 slab
	85	*/
	86	#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71 AK	87
	88	#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
	89
9a799d71 AK	90	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	91	#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	92
	93	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	94	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	95	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	96	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7 YZ	97	#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
eacd73f7 YZ	98	#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71	99	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865	100	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71 AK	101	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
9a799d71 AK	102
0a924578 PWJ	103	#define IXGBE_MAX_RSC_INT_RATE 162760
0a924578 PWJ	104
7f870475 GR	105	#define IXGBE_MAX_VF_MC_ENTRIES 30
	106	#define IXGBE_MAX_VF_FUNCTIONS 64
	107	#define IXGBE_MAX_VFTA_ENTRIES 128
	108	#define MAX_EMULATION_MAC_ADDRS 16
	109	#define VMDQ_P(p) ((p) + adapter->num_vfs)
	110
	111	struct vf_data_storage {
	112	unsigned char vf_mac_addresses[ETH_ALEN];
	113	u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
	114	u16 num_vf_mc_hashes;
	115	u16 default_vf_vlan_id;
	116	u16 vlans_enabled;
7f870475	117	bool clear_to_send;
7f01648a	118	bool pf_set_mac;
7f01648a GR	119	u16 pf_vlan; /* When set, guest VLAN config not allowed. */
7f01648a GR	120	u16 pf_qos;
7f870475 GR	121	};
7f870475 GR	122
9a799d71 AK	123	/* wrapper around a pointer to a socket buffer,
	124	* so a DMA handle can be stored along with the buffer */
	125	struct ixgbe_tx_buffer {
	126	struct sk_buff *skb;
	127	dma_addr_t dma;
	128	unsigned long time_stamp;
	129	u16 length;
	130	u16 next_to_watch;
8ad494b0 AD	131	unsigned int bytecount;
	132	u16 gso_segs;
	133	u8 mapped_as_page;
9a799d71 AK	134	};
	135
	136	struct ixgbe_rx_buffer {
	137	struct sk_buff *skb;
	138	dma_addr_t dma;
	139	struct page *page;
	140	dma_addr_t page_dma;
762f4c57	141	unsigned int page_offset;
9a799d71 AK	142	};
	143
	144	struct ixgbe_queue_stats {
	145	u64 packets;
	146	u64 bytes;
	147	};
	148
	149	struct ixgbe_ring {
9a799d71	150	void desc; / descriptor ring memory */
9a799d71 AK	151	union {
	152	struct ixgbe_tx_buffer *tx_buffer_info;
	153	struct ixgbe_rx_buffer *rx_buffer_info;
	154	};
ae540af1 JB	155	u8 atr_sample_rate;
	156	u8 atr_count;
	157	u16 count; /* amount of descriptors */
	158	u16 rx_buf_len;
	159	u16 next_to_use;
	160	u16 next_to_clean;
	161
	162	u8 queue_index; /* needed for multiqueue queue management */
9a799d71	163
6e455b89 YZ	164	#define IXGBE_RING_RX_PS_ENABLED (u8)(1)
6e455b89 YZ	165	u8 flags; /* per ring feature flags */
84ea2591	166	u8 __iomem *tail;
9a799d71	167
f494e8fa AV	168	unsigned int total_bytes;
f494e8fa AV	169	unsigned int total_packets;
9a799d71	170
5dd2d332	171	#ifdef CONFIG_IXGBE_DCA
bd0362dd JC	172	/* cpu for tx queue */
	173	int cpu;
	174	#endif
ae540af1 JB	175
	176	u16 work_limit; /* max work per interrupt */
	177	u16 reg_idx; /* holds the special value that gets
	178	* the hardware register offset
	179	* associated with this ring, which is
	180	* different for DCB and RSS modes
	181	*/
	182
9a799d71	183	struct ixgbe_queue_stats stats;
de1036b1	184	struct u64_stats_sync syncp;
4a0b9ca0	185	int numa_node;
de1036b1	186	unsigned long reinit_state;
ae540af1	187	u64 rsc_count; /* stat for coalesced packets */
94b982b2	188	u64 rsc_flush; /* stats for flushed packets */
7ca3bc58 JB	189	u32 restart_queue; /* track tx queue restarts */
7ca3bc58 JB	190	u32 non_eop_descs; /* track hardware descriptor chaining */
9a799d71	191
ae540af1 JB	192	unsigned int size; /* length in bytes */
ae540af1 JB	193	dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b	194	struct rcu_head rcu;
7ca3bc58	195	} ____cacheline_internodealigned_in_smp;
9a799d71	196
c7e4358a SN	197	enum ixgbe_ring_f_enum {
	198	RING_F_NONE = 0,
	199	RING_F_DCB,
7f870475	200	RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a	201	RING_F_RSS,
c4cf55e5	202	RING_F_FDIR,
0331a832 YZ	203	#ifdef IXGBE_FCOE
	204	RING_F_FCOE,
	205	#endif /* IXGBE_FCOE */
c7e4358a SN	206
	207	RING_F_ARRAY_SIZE /* must be last in enum set */
	208	};
	209
2f90b865	210	#define IXGBE_MAX_DCB_INDICES 8
021230d4	211	#define IXGBE_MAX_RSS_INDICES 16
7f870475	212	#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5	213	#define IXGBE_MAX_FDIR_INDICES 64
0331a832 YZ	214	#ifdef IXGBE_FCOE
0331a832 YZ	215	#define IXGBE_MAX_FCOE_INDICES 8
e0fce695 JF	216	#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
	217	#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
	218	#else
	219	#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
	220	#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832	221	#endif /* IXGBE_FCOE */
021230d4 AV	222	struct ixgbe_ring_feature {
	223	int indices;
	224	int mask;
7ca3bc58	225	} ____cacheline_internodealigned_in_smp;
021230d4	226
021230d4	227
2f90b865 AD	228	#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
	229	? 8 : 1)
	230	#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
	231
021230d4 AV	232	/* MAX_MSIX_Q_VECTORS of these are allocated,
	233	* but we only use one per queue-specific vector.
	234	*/
	235	struct ixgbe_q_vector {
	236	struct ixgbe_adapter *adapter;
fe49f04a AD	237	unsigned int v_idx; /* index of q_vector within array, also used for
	238	* finding the bit in EICR and friends that
	239	* represents the vector for this ring */
021230d4 AV	240	struct napi_struct napi;
	241	DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
	242	DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
	243	u8 rxr_count; /* Rx ring count assigned to this vector */
	244	u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3 JB	245	u8 tx_itr;
30efa5a3 JB	246	u8 rx_itr;
021230d4	247	u32 eitr;
b25ebfd2	248	cpumask_var_t affinity_mask;
021230d4 AV	249	};
021230d4 AV	250
9a799d71	251	/* Helper macros to switch between ints/sec and what the register uses.
509ee935 JB	252	* And yes, it's the same math going both ways. The lowest value
509ee935 JB	253	* supported by all of the ixgbe hardware is 8.
9a799d71 AK	254	*/
9a799d71 AK	255	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935	256	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71 AK	257	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	258
	259	#define IXGBE_DESC_UNUSED(R) \
	260	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	261	(R)->next_to_clean - (R)->next_to_use - 1)
	262
	263	#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d	264	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71	265	#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d	266	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71	267	#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d	268	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71 AK	269
9a799d71 AK	270	#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1 YZ	271	#ifdef IXGBE_FCOE
	272	/* Use 3K as the baby jumbo frame size for FCoE */
	273	#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
	274	#endif /* IXGBE_FCOE */
9a799d71	275
021230d4 AV	276	#define OTHER_VECTOR 1
	277	#define NON_Q_VECTORS (OTHER_VECTOR)
	278
e8e26350 PW	279	#define MAX_MSIX_VECTORS_82599 64
e8e26350 PW	280	#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c PWJ	281	#define MAX_MSIX_VECTORS_82598 18
	282	#define MAX_MSIX_Q_VECTORS_82598 16
	283
e8e26350 PW	284	#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
e8e26350 PW	285	#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c	286
021230d4	287	#define MIN_MSIX_Q_VECTORS 2
021230d4 AV	288	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
021230d4 AV	289
9a799d71 AK	290	/* board specific private data structure */
	291	struct ixgbe_adapter {
	292	struct timer_list watchdog_timer;
f62bbb5e	293	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71	294	u16 bd_number;
9a799d71	295	struct work_struct reset_task;
7a921c93	296	struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
e8e26350	297	char name[MAX_MSIX_COUNT][IFNAMSIZ + 9];
2f90b865 AD	298	struct ixgbe_dcb_config dcb_cfg;
	299	struct ixgbe_dcb_config temp_dcb_cfg;
	300	u8 dcb_set_bitmap;
264857b8	301	enum ixgbe_fc_mode last_lfc_mode;
9a799d71	302
f494e8fa	303	/* Interrupt Throttle Rate */
f7554a2b NS	304	u32 rx_itr_setting;
f7554a2b NS	305	u32 tx_itr_setting;
f494e8fa AV	306	u16 eitr_low;
	307	u16 eitr_high;
	308
9a799d71	309	/* TX */
4a0b9ca0	310	struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3	311	int num_tx_queues;
9a799d71 AK	312	u32 tx_timeout_count;
	313	bool detect_tx_hung;
	314
7ca3bc58 JB	315	u64 restart_queue;
	316	u64 lsc_int;
	317
9a799d71	318	/* RX */
4a0b9ca0	319	struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3	320	int num_rx_queues;
7f870475 GR	321	int num_rx_pools; /* == num_rx_queues in 82598 */
7f870475 GR	322	int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71	323	u64 hw_csum_rx_error;
e8e26350	324	u64 hw_rx_no_dma_resources;
9a799d71	325	u64 non_eop_descs;
021230d4	326	int num_msix_vectors;
eb7f139c	327	int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a	328	struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71 AK	329	struct msix_entry *msix_entries;
9a799d71 AK	330
9a799d71 AK	331	u32 alloc_rx_page_failed;
	332	u32 alloc_rx_buff_failed;
	333
021230d4 AV	334	/* Some features need tri-state capability,
	335	* thus the additional *_CAPABLE flags.
	336	*/
9a799d71	337	u32 flags;
96b0e0f6 JB	338	#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
	339	#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
	340	#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
	341	#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
	342	#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
	343	#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
	344	#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
	345	#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
	346	#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
	347	#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
	348	#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
	349	#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
	350	#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350	351	#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6 JB	352	#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
	353	#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
	354	#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
	355	#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e	356	#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6	357	#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955 JF	358	#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
	359	#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
	360	#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
	361	#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
	362	#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
	363	#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
	364	#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
	365	#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6	366
df647b5c PWJ	367	u32 flags2;
	368	#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
	369	#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a	370	#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6 JB	371	/* default to trying for four seconds */
96b0e0f6 JB	372	#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71 AK	373
	374	/* OS defined structs */
	375	struct net_device *netdev;
	376	struct pci_dev *pdev;
9a799d71	377
da4dd0f7 PWJ	378	u32 test_icr;
	379	struct ixgbe_ring test_tx_ring;
	380	struct ixgbe_ring test_rx_ring;
	381
9a799d71 AK	382	/* structs defined in ixgbe_hw.h */
	383	struct ixgbe_hw hw;
	384	u16 msg_enable;
	385	struct ixgbe_hw_stats stats;
021230d4 AV	386
021230d4 AV	387	/* Interrupt Throttle Rate */
f7554a2b NS	388	u32 rx_eitr_param;
f7554a2b NS	389	u32 tx_eitr_param;
9a799d71 AK	390
	391	unsigned long state;
	392	u64 tx_busy;
30efa5a3 JB	393	unsigned int tx_ring_count;
30efa5a3 JB	394	unsigned int rx_ring_count;
cf8280ee JB	395
	396	u32 link_speed;
	397	bool link_up;
	398	unsigned long link_check_timeout;
	399
	400	struct work_struct watchdog_task;
c4900be0 DS	401	struct work_struct sfp_task;
c4900be0 DS	402	struct timer_list sfp_timer;
e8e26350 PW	403	struct work_struct multispeed_fiber_task;
e8e26350 PW	404	struct work_struct sfp_config_module_task;
c4cf55e5 PWJ	405	u32 fdir_pballoc;
	406	u32 atr_sample_rate;
	407	spinlock_t fdir_perfect_lock;
	408	struct work_struct fdir_reinit_task;
d0ed8937 YZ	409	#ifdef IXGBE_FCOE
	410	struct ixgbe_fcoe fcoe;
	411	#endif /* IXGBE_FCOE */
94b982b2 MC	412	u64 rsc_total_count;
94b982b2 MC	413	u64 rsc_total_flush;
e8e26350	414	u32 wol;
34b0368c	415	u16 eeprom_version;
7f870475	416
1a6c14a2	417	int node;
119fc60a MC	418	struct work_struct check_overtemp_task;
119fc60a MC	419	u32 interrupt_event;
1a6c14a2	420
7f870475 GR	421	/* SR-IOV */
	422	DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
	423	unsigned int num_vfs;
	424	struct vf_data_storage *vfinfo;
9a799d71 AK	425	};
	426
	427	enum ixbge_state_t {
	428	__IXGBE_TESTING,
	429	__IXGBE_RESETTING,
c4900be0	430	__IXGBE_DOWN,
c4cf55e5	431	__IXGBE_FDIR_INIT_DONE,
c4900be0	432	__IXGBE_SFP_MODULE_NOT_FOUND
9a799d71 AK	433	};
	434
	435	enum ixgbe_boards {
3957d63d	436	board_82598,
e8e26350	437	board_82599,
9a799d71 AK	438	};
9a799d71 AK	439
3957d63d	440	extern struct ixgbe_info ixgbe_82598_info;
e8e26350	441	extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51	442	#ifdef CONFIG_IXGBE_DCB
32953543	443	extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865 AD	444	extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
	445	struct ixgbe_dcb_config *dst_dcb_cfg,
	446	int tc_max);
	447	#endif
9a799d71 AK	448
9a799d71 AK	449	extern char ixgbe_driver_name[];
9c8eb720	450	extern const char ixgbe_driver_version[];
9a799d71 AK	451
	452	extern int ixgbe_up(struct ixgbe_adapter *adapter);
	453	extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882	454	extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71	455	extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71	456	extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b4617240 PW	457	extern int ixgbe_setup_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	458	extern int ixgbe_setup_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	459	extern void ixgbe_free_rx_resources(struct ixgbe_adapter , struct ixgbe_ring );
	460	extern void ixgbe_free_tx_resources(struct ixgbe_adapter , struct ixgbe_ring );
84418e3b AD	461	extern void ixgbe_configure_rx_ring(struct ixgbe_adapter ,struct ixgbe_ring );
84418e3b AD	462	extern void ixgbe_configure_tx_ring(struct ixgbe_adapter ,struct ixgbe_ring );
b4617240	463	extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865	464	extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93	465	extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b AD	466	extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
	467	struct net_device *,
	468	struct ixgbe_adapter *,
	469	struct ixgbe_ring *);
	470	extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *,
	471	struct ixgbe_tx_buffer *);
	472	extern void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
	473	struct ixgbe_ring *rx_ring,
d5f398ed	474	u16 cleaned_count);
fe49f04a AD	475	extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
fe49f04a AD	476	extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772 PWJ	477	extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
	478	extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
	479	extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
	480	extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
	481	struct ixgbe_atr_input *input,
	482	u8 queue);
9a713e7c PW	483	extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
	484	struct ixgbe_atr_input *input,
	485	struct ixgbe_atr_input_masks *input_masks,
	486	u16 soft_id, u8 queue);
ffff4772 PWJ	487	extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
	488	u16 vlan_id);
	489	extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
	490	u32 src_addr);
	491	extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
	492	u32 dst_addr);
ffff4772 PWJ	493	extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
	494	u16 src_port);
	495	extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
	496	u16 dst_port);
	497	extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
	498	u16 flex_byte);
ffff4772 PWJ	499	extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
ffff4772 PWJ	500	u8 l4type);
7f870475	501	extern void ixgbe_set_rx_mode(struct net_device *netdev);
eacd73f7 YZ	502	#ifdef IXGBE_FCOE
	503	extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
	504	extern int ixgbe_fso(struct ixgbe_adapter *adapter,
	505	struct ixgbe_ring tx_ring, struct sk_buff skb,
	506	u32 tx_flags, u8 *hdr_len);
332d4a7d YZ	507	extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
	508	extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
	509	union ixgbe_adv_rx_desc *rx_desc,
	510	struct sk_buff *skb);
	511	extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
	512	struct scatterlist *sgl, unsigned int sgc);
	513	extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c YZ	514	extern int ixgbe_fcoe_enable(struct net_device *netdev);
8450ff8c YZ	515	extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520 YZ	516	#ifdef CONFIG_IXGBE_DCB
	517	extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
	518	extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
	519	#endif /* CONFIG_IXGBE_DCB */
61a1fa10	520	extern int ixgbe_fcoe_get_wwn(struct net_device netdev, u64 wwn, int type);
eacd73f7	521	#endif /* IXGBE_FCOE */
9a799d71 AK	522
9a799d71 AK	523	#endif /* _IXGBE_H_ */