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ixgbe: cleanup ixgbe_map_rings_to_vectors
[net-next-2.6.git] / drivers / net / ixgbe / ixgbe.h
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
8c47eaa7 4 Copyright(c) 1999 - 2010 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#ifndef _IXGBE_H_
29#define _IXGBE_H_
30
f62bbb5e 31#include <linux/bitops.h>
9a799d71
AK		 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/netdevice.h>
b25ebfd2 35#include <linux/cpumask.h>
6fabd715 36#include <linux/aer.h>
f62bbb5e 37#include <linux/if_vlan.h>
9a799d71
AK		 38
39#include "ixgbe_type.h"
40#include "ixgbe_common.h"
2f90b865 41#include "ixgbe_dcb.h"
eacd73f7
YZ		 42#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE)
43#define IXGBE_FCOE
44#include "ixgbe_fcoe.h"
45#endif /* CONFIG_FCOE or CONFIG_FCOE_MODULE */
5dd2d332 46#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 47#include <linux/dca.h>
48#endif
9a799d71 49
849c4542
ET		 50/* common prefix used by pr_<> macros */
51#undef pr_fmt
52#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9a799d71
AK		 53
54/* TX/RX descriptor defines */
6bacb300 55#define IXGBE_DEFAULT_TXD 512
9a799d71
AK		 56#define IXGBE_MAX_TXD 4096
57#define IXGBE_MIN_TXD 64
58
6bacb300 59#define IXGBE_DEFAULT_RXD 512
9a799d71
AK		 60#define IXGBE_MAX_RXD 4096
61#define IXGBE_MIN_RXD 64
62
9a799d71 63/* flow control */
2b9ade93 64#define IXGBE_MIN_FCRTL 0x40
9a799d71 65#define IXGBE_MAX_FCRTL 0x7FF80
2b9ade93 66#define IXGBE_MIN_FCRTH 0x600
9a799d71 67#define IXGBE_MAX_FCRTH 0x7FFF0
2b9ade93 68#define IXGBE_DEFAULT_FCPAUSE 0xFFFF
9a799d71
AK		 69#define IXGBE_MIN_FCPAUSE 0
70#define IXGBE_MAX_FCPAUSE 0xFFFF
71
72/* Supported Rx Buffer Sizes */
13958070 73#define IXGBE_RXBUFFER_512 512 /* Used for packet split */
9a799d71 74#define IXGBE_RXBUFFER_2048 2048
e76678dd
AD		 75#define IXGBE_RXBUFFER_4096 4096
76#define IXGBE_RXBUFFER_8192 8192
32344a39 77#define IXGBE_MAX_RXBUFFER 16384 /* largest size for a single descriptor */
9a799d71 78
13958070
AD		 79/*
80 * NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN mans we
81 * reserve 2 more, and skb_shared_info adds an additional 384 bytes more,
82 * this adds up to 512 bytes of extra data meaning the smallest allocation
83 * we could have is 1K.
84 * i.e. RXBUFFER_512 --> size-1024 slab
85 */
86#define IXGBE_RX_HDR_SIZE IXGBE_RXBUFFER_512
9a799d71
AK		 87
88#define MAXIMUM_ETHERNET_VLAN_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
89
9a799d71
AK		 90/* How many Rx Buffers do we bundle into one write to the hardware ? */
91#define IXGBE_RX_BUFFER_WRITE 16 /* Must be power of 2 */
92
93#define IXGBE_TX_FLAGS_CSUM (u32)(1)
94#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
95#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
96#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
eacd73f7
YZ		 97#define IXGBE_TX_FLAGS_FCOE (u32)(1 << 4)
98#define IXGBE_TX_FLAGS_FSO (u32)(1 << 5)
9a799d71 99#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
2f90b865 100#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
9a799d71
AK		 101#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
102
0a924578
PWJ		 103#define IXGBE_MAX_RSC_INT_RATE 162760
104
7f870475
GR		 105#define IXGBE_MAX_VF_MC_ENTRIES 30
106#define IXGBE_MAX_VF_FUNCTIONS 64
107#define IXGBE_MAX_VFTA_ENTRIES 128
108#define MAX_EMULATION_MAC_ADDRS 16
109#define VMDQ_P(p) ((p) + adapter->num_vfs)
110
111struct vf_data_storage {
112 unsigned char vf_mac_addresses[ETH_ALEN];
113 u16 vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
114 u16 num_vf_mc_hashes;
115 u16 default_vf_vlan_id;
116 u16 vlans_enabled;
7f870475 117 bool clear_to_send;
7f01648a 118 bool pf_set_mac;
7f01648a
GR		 119 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
120 u16 pf_qos;
7f870475
GR		 121};
122
9a799d71
AK		 123/* wrapper around a pointer to a socket buffer,
124 * so a DMA handle can be stored along with the buffer */
125struct ixgbe_tx_buffer {
126 struct sk_buff *skb;
127 dma_addr_t dma;
128 unsigned long time_stamp;
129 u16 length;
130 u16 next_to_watch;
8ad494b0
AD		 131 unsigned int bytecount;
132 u16 gso_segs;
133 u8 mapped_as_page;
9a799d71
AK		 134};
135
136struct ixgbe_rx_buffer {
137 struct sk_buff *skb;
138 dma_addr_t dma;
139 struct page *page;
140 dma_addr_t page_dma;
762f4c57 141 unsigned int page_offset;
9a799d71
AK		 142};
143
144struct ixgbe_queue_stats {
145 u64 packets;
146 u64 bytes;
147};
148
5b7da515
AD		 149struct ixgbe_tx_queue_stats {
150 u64 restart_queue;
151 u64 tx_busy;
152};
153
154struct ixgbe_rx_queue_stats {
155 u64 rsc_count;
156 u64 rsc_flush;
157 u64 non_eop_descs;
158 u64 alloc_rx_page_failed;
159 u64 alloc_rx_buff_failed;
160};
161
7d637bcc
AD		 162enum ixbge_ring_state_t {
163 __IXGBE_TX_FDIR_INIT_DONE,
164 __IXGBE_TX_DETECT_HANG,
165 __IXGBE_RX_PS_ENABLED,
166 __IXGBE_RX_RSC_ENABLED,
167};
168
169#define ring_is_ps_enabled(ring) \
170 test_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
171#define set_ring_ps_enabled(ring) \
172 set_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
173#define clear_ring_ps_enabled(ring) \
174 clear_bit(__IXGBE_RX_PS_ENABLED, &(ring)->state)
175#define check_for_tx_hang(ring) \
176 test_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
177#define set_check_for_tx_hang(ring) \
178 set_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
179#define clear_check_for_tx_hang(ring) \
180 clear_bit(__IXGBE_TX_DETECT_HANG, &(ring)->state)
181#define ring_is_rsc_enabled(ring) \
182 test_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
183#define set_ring_rsc_enabled(ring) \
184 set_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
185#define clear_ring_rsc_enabled(ring) \
186 clear_bit(__IXGBE_RX_RSC_ENABLED, &(ring)->state)
9a799d71 187struct ixgbe_ring {
9a799d71 188 void *desc; /* descriptor ring memory */
b6ec895e 189 struct device *dev; /* device for DMA mapping */
fc77dc3c 190 struct net_device *netdev; /* netdev ring belongs to */
9a799d71
AK		 191 union {
192 struct ixgbe_tx_buffer *tx_buffer_info;
193 struct ixgbe_rx_buffer *rx_buffer_info;
194 };
7d637bcc 195 unsigned long state;
ae540af1
JB		 196 u8 atr_sample_rate;
197 u8 atr_count;
198 u16 count; /* amount of descriptors */
199 u16 rx_buf_len;
200 u16 next_to_use;
201 u16 next_to_clean;
202
203 u8 queue_index; /* needed for multiqueue queue management */
7d637bcc
AD		 204 u8 reg_idx; /* holds the special value that gets
205 * the hardware register offset
206 * associated with this ring, which is
207 * different for DCB and RSS modes
208 */
209
210 u16 work_limit; /* max work per interrupt */
9a799d71 211
84ea2591 212 u8 __iomem *tail;
9a799d71 213
f494e8fa
AV		 214 unsigned int total_bytes;
215 unsigned int total_packets;
9a799d71
AK		 216
217 struct ixgbe_queue_stats stats;
de1036b1 218 struct u64_stats_sync syncp;
5b7da515
AD		 219 union {
220 struct ixgbe_tx_queue_stats tx_stats;
221 struct ixgbe_rx_queue_stats rx_stats;
222 };
5b7da515 223 int numa_node;
ae540af1
JB		 224 unsigned int size; /* length in bytes */
225 dma_addr_t dma; /* phys. address of descriptor ring */
1a51502b 226 struct rcu_head rcu;
33cf09c9 227 struct ixgbe_q_vector *q_vector; /* back-pointer to host q_vector */
7ca3bc58 228} ____cacheline_internodealigned_in_smp;
9a799d71 229
c7e4358a
SN		 230enum ixgbe_ring_f_enum {
231 RING_F_NONE = 0,
232 RING_F_DCB,
7f870475 233 RING_F_VMDQ, /* SR-IOV uses the same ring feature */
c7e4358a 234 RING_F_RSS,
c4cf55e5 235 RING_F_FDIR,
0331a832
YZ		 236#ifdef IXGBE_FCOE
237 RING_F_FCOE,
238#endif /* IXGBE_FCOE */
c7e4358a
SN		 239
240 RING_F_ARRAY_SIZE /* must be last in enum set */
241};
242
2f90b865 243#define IXGBE_MAX_DCB_INDICES 8
021230d4 244#define IXGBE_MAX_RSS_INDICES 16
7f870475 245#define IXGBE_MAX_VMDQ_INDICES 64
c4cf55e5 246#define IXGBE_MAX_FDIR_INDICES 64
0331a832
YZ		 247#ifdef IXGBE_FCOE
248#define IXGBE_MAX_FCOE_INDICES 8
e0fce695
JF		 249#define MAX_RX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
250#define MAX_TX_QUEUES (IXGBE_MAX_FDIR_INDICES + IXGBE_MAX_FCOE_INDICES)
251#else
252#define MAX_RX_QUEUES IXGBE_MAX_FDIR_INDICES
253#define MAX_TX_QUEUES IXGBE_MAX_FDIR_INDICES
0331a832 254#endif /* IXGBE_FCOE */
021230d4
AV		 255struct ixgbe_ring_feature {
256 int indices;
257 int mask;
7ca3bc58 258} ____cacheline_internodealigned_in_smp;
021230d4 259
021230d4 260
2f90b865
AD		 261#define MAX_RX_PACKET_BUFFERS ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) \
262 ? 8 : 1)
263#define MAX_TX_PACKET_BUFFERS MAX_RX_PACKET_BUFFERS
264
021230d4
AV		 265/* MAX_MSIX_Q_VECTORS of these are allocated,
266 * but we only use one per queue-specific vector.
267 */
268struct ixgbe_q_vector {
269 struct ixgbe_adapter *adapter;
fe49f04a
AD		 270 unsigned int v_idx; /* index of q_vector within array, also used for
271 * finding the bit in EICR and friends that
272 * represents the vector for this ring */
33cf09c9
AD		 273#ifdef CONFIG_IXGBE_DCA
274 int cpu; /* CPU for DCA */
275#endif
021230d4
AV		 276 struct napi_struct napi;
277 DECLARE_BITMAP(rxr_idx, MAX_RX_QUEUES); /* Rx ring indices */
278 DECLARE_BITMAP(txr_idx, MAX_TX_QUEUES); /* Tx ring indices */
279 u8 rxr_count; /* Rx ring count assigned to this vector */
280 u8 txr_count; /* Tx ring count assigned to this vector */
30efa5a3
JB		 281 u8 tx_itr;
282 u8 rx_itr;
021230d4 283 u32 eitr;
b25ebfd2 284 cpumask_var_t affinity_mask;
d0759ebb 285 char name[IFNAMSIZ + 9];
021230d4
AV		 286};
287
9a799d71 288/* Helper macros to switch between ints/sec and what the register uses.
509ee935
JB		 289 * And yes, it's the same math going both ways. The lowest value
290 * supported by all of the ixgbe hardware is 8.
9a799d71
AK		 291 */
292#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
509ee935 293 ((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
9a799d71
AK		 294#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
295
296#define IXGBE_DESC_UNUSED(R) \
297 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
298 (R)->next_to_clean - (R)->next_to_use - 1)
299
300#define IXGBE_RX_DESC_ADV(R, i) \
31f05a2d 301 (&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
9a799d71 302#define IXGBE_TX_DESC_ADV(R, i) \
31f05a2d 303 (&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
9a799d71 304#define IXGBE_TX_CTXTDESC_ADV(R, i) \
31f05a2d 305 (&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
9a799d71
AK		 306
307#define IXGBE_MAX_JUMBO_FRAME_SIZE 16128
63f39bd1
YZ		 308#ifdef IXGBE_FCOE
309/* Use 3K as the baby jumbo frame size for FCoE */
310#define IXGBE_FCOE_JUMBO_FRAME_SIZE 3072
311#endif /* IXGBE_FCOE */
9a799d71 312
021230d4
AV		 313#define OTHER_VECTOR 1
314#define NON_Q_VECTORS (OTHER_VECTOR)
315
e8e26350
PW		 316#define MAX_MSIX_VECTORS_82599 64
317#define MAX_MSIX_Q_VECTORS_82599 64
eb7f139c
PWJ		 318#define MAX_MSIX_VECTORS_82598 18
319#define MAX_MSIX_Q_VECTORS_82598 16
320
e8e26350
PW		 321#define MAX_MSIX_Q_VECTORS MAX_MSIX_Q_VECTORS_82599
322#define MAX_MSIX_COUNT MAX_MSIX_VECTORS_82599
eb7f139c 323
021230d4 324#define MIN_MSIX_Q_VECTORS 2
021230d4
AV		 325#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
326
9a799d71
AK		 327/* board specific private data structure */
328struct ixgbe_adapter {
329 struct timer_list watchdog_timer;
f62bbb5e 330 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
9a799d71 331 u16 bd_number;
9a799d71 332 struct work_struct reset_task;
7a921c93 333 struct ixgbe_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
2f90b865
AD		 334 struct ixgbe_dcb_config dcb_cfg;
335 struct ixgbe_dcb_config temp_dcb_cfg;
336 u8 dcb_set_bitmap;
264857b8 337 enum ixgbe_fc_mode last_lfc_mode;
9a799d71 338
f494e8fa 339 /* Interrupt Throttle Rate */
f7554a2b
NS		 340 u32 rx_itr_setting;
341 u32 tx_itr_setting;
f494e8fa
AV		 342 u16 eitr_low;
343 u16 eitr_high;
344
9a799d71 345 /* TX */
4a0b9ca0 346 struct ixgbe_ring *tx_ring[MAX_TX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 347 int num_tx_queues;
9a799d71
AK		 348 u32 tx_timeout_count;
349 bool detect_tx_hung;
350
7ca3bc58
JB		 351 u64 restart_queue;
352 u64 lsc_int;
353
9a799d71 354 /* RX */
4a0b9ca0 355 struct ixgbe_ring *rx_ring[MAX_RX_QUEUES] ____cacheline_aligned_in_smp;
30efa5a3 356 int num_rx_queues;
7f870475
GR		 357 int num_rx_pools; /* == num_rx_queues in 82598 */
358 int num_rx_queues_per_pool; /* 1 if 82598, can be many if 82599 */
9a799d71 359 u64 hw_csum_rx_error;
e8e26350 360 u64 hw_rx_no_dma_resources;
9a799d71 361 u64 non_eop_descs;
021230d4 362 int num_msix_vectors;
eb7f139c 363 int max_msix_q_vectors; /* true count of q_vectors for device */
c7e4358a 364 struct ixgbe_ring_feature ring_feature[RING_F_ARRAY_SIZE];
9a799d71
AK		 365 struct msix_entry *msix_entries;
366
9a799d71
AK		 367 u32 alloc_rx_page_failed;
368 u32 alloc_rx_buff_failed;
369
021230d4
AV		 370 /* Some features need tri-state capability,
371 * thus the additional *_CAPABLE flags.
372 */
9a799d71 373 u32 flags;
96b0e0f6
JB		 374#define IXGBE_FLAG_RX_CSUM_ENABLED (u32)(1)
375#define IXGBE_FLAG_MSI_CAPABLE (u32)(1 << 1)
376#define IXGBE_FLAG_MSI_ENABLED (u32)(1 << 2)
377#define IXGBE_FLAG_MSIX_CAPABLE (u32)(1 << 3)
378#define IXGBE_FLAG_MSIX_ENABLED (u32)(1 << 4)
379#define IXGBE_FLAG_RX_1BUF_CAPABLE (u32)(1 << 6)
380#define IXGBE_FLAG_RX_PS_CAPABLE (u32)(1 << 7)
381#define IXGBE_FLAG_RX_PS_ENABLED (u32)(1 << 8)
382#define IXGBE_FLAG_IN_NETPOLL (u32)(1 << 9)
383#define IXGBE_FLAG_DCA_ENABLED (u32)(1 << 10)
384#define IXGBE_FLAG_DCA_CAPABLE (u32)(1 << 11)
385#define IXGBE_FLAG_IMIR_ENABLED (u32)(1 << 12)
386#define IXGBE_FLAG_MQ_CAPABLE (u32)(1 << 13)
e8e26350 387#define IXGBE_FLAG_DCB_ENABLED (u32)(1 << 14)
96b0e0f6
JB		 388#define IXGBE_FLAG_RSS_ENABLED (u32)(1 << 16)
389#define IXGBE_FLAG_RSS_CAPABLE (u32)(1 << 17)
390#define IXGBE_FLAG_VMDQ_CAPABLE (u32)(1 << 18)
391#define IXGBE_FLAG_VMDQ_ENABLED (u32)(1 << 19)
0befdb3e 392#define IXGBE_FLAG_FAN_FAIL_CAPABLE (u32)(1 << 20)
96b0e0f6 393#define IXGBE_FLAG_NEED_LINK_UPDATE (u32)(1 << 22)
10eec955
JF		 394#define IXGBE_FLAG_IN_SFP_LINK_TASK (u32)(1 << 23)
395#define IXGBE_FLAG_IN_SFP_MOD_TASK (u32)(1 << 24)
396#define IXGBE_FLAG_FDIR_HASH_CAPABLE (u32)(1 << 25)
397#define IXGBE_FLAG_FDIR_PERFECT_CAPABLE (u32)(1 << 26)
398#define IXGBE_FLAG_FCOE_CAPABLE (u32)(1 << 27)
399#define IXGBE_FLAG_FCOE_ENABLED (u32)(1 << 28)
400#define IXGBE_FLAG_SRIOV_CAPABLE (u32)(1 << 29)
401#define IXGBE_FLAG_SRIOV_ENABLED (u32)(1 << 30)
96b0e0f6 402
df647b5c
PWJ		 403 u32 flags2;
404#define IXGBE_FLAG2_RSC_CAPABLE (u32)(1)
405#define IXGBE_FLAG2_RSC_ENABLED (u32)(1 << 1)
119fc60a 406#define IXGBE_FLAG2_TEMP_SENSOR_CAPABLE (u32)(1 << 2)
96b0e0f6
JB		 407/* default to trying for four seconds */
408#define IXGBE_TRY_LINK_TIMEOUT (4 * HZ)
9a799d71
AK		 409
410 /* OS defined structs */
411 struct net_device *netdev;
412 struct pci_dev *pdev;
9a799d71 413
da4dd0f7
PWJ		 414 u32 test_icr;
415 struct ixgbe_ring test_tx_ring;
416 struct ixgbe_ring test_rx_ring;
417
9a799d71
AK		 418 /* structs defined in ixgbe_hw.h */
419 struct ixgbe_hw hw;
420 u16 msg_enable;
421 struct ixgbe_hw_stats stats;
021230d4
AV		 422
423 /* Interrupt Throttle Rate */
f7554a2b
NS		 424 u32 rx_eitr_param;
425 u32 tx_eitr_param;
9a799d71
AK		 426
427 unsigned long state;
428 u64 tx_busy;
30efa5a3
JB		 429 unsigned int tx_ring_count;
430 unsigned int rx_ring_count;
cf8280ee
JB		 431
432 u32 link_speed;
433 bool link_up;
434 unsigned long link_check_timeout;
435
436 struct work_struct watchdog_task;
c4900be0
DS		 437 struct work_struct sfp_task;
438 struct timer_list sfp_timer;
e8e26350
PW		 439 struct work_struct multispeed_fiber_task;
440 struct work_struct sfp_config_module_task;
c4cf55e5
PWJ		 441 u32 fdir_pballoc;
442 u32 atr_sample_rate;
443 spinlock_t fdir_perfect_lock;
444 struct work_struct fdir_reinit_task;
d0ed8937
YZ		 445#ifdef IXGBE_FCOE
446 struct ixgbe_fcoe fcoe;
447#endif /* IXGBE_FCOE */
94b982b2
MC		 448 u64 rsc_total_count;
449 u64 rsc_total_flush;
e8e26350 450 u32 wol;
34b0368c 451 u16 eeprom_version;
7f870475 452
1a6c14a2 453 int node;
119fc60a
MC		 454 struct work_struct check_overtemp_task;
455 u32 interrupt_event;
d0759ebb 456 char lsc_int_name[IFNAMSIZ + 9];
1a6c14a2 457
7f870475
GR		 458 /* SR-IOV */
459 DECLARE_BITMAP(active_vfs, IXGBE_MAX_VF_FUNCTIONS);
460 unsigned int num_vfs;
461 struct vf_data_storage *vfinfo;
9a799d71
AK		 462};
463
464enum ixbge_state_t {
465 __IXGBE_TESTING,
466 __IXGBE_RESETTING,
c4900be0
DS		 467 __IXGBE_DOWN,
468 __IXGBE_SFP_MODULE_NOT_FOUND
9a799d71
AK		 469};
470
aa80175a
AD		 471struct ixgbe_rsc_cb {
472 dma_addr_t dma;
473 u16 skb_cnt;
474 bool delay_unmap;
475};
476#define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
477
9a799d71 478enum ixgbe_boards {
3957d63d 479 board_82598,
e8e26350 480 board_82599,
9a799d71
AK		 481};
482
3957d63d 483extern struct ixgbe_info ixgbe_82598_info;
e8e26350 484extern struct ixgbe_info ixgbe_82599_info;
7a6b6f51 485#ifdef CONFIG_IXGBE_DCB
32953543 486extern const struct dcbnl_rtnl_ops dcbnl_ops;
2f90b865
AD		 487extern int ixgbe_copy_dcb_cfg(struct ixgbe_dcb_config *src_dcb_cfg,
488 struct ixgbe_dcb_config *dst_dcb_cfg,
489 int tc_max);
490#endif
9a799d71
AK		 491
492extern char ixgbe_driver_name[];
9c8eb720 493extern const char ixgbe_driver_version[];
9a799d71
AK		 494
495extern int ixgbe_up(struct ixgbe_adapter *adapter);
496extern void ixgbe_down(struct ixgbe_adapter *adapter);
d4f80882 497extern void ixgbe_reinit_locked(struct ixgbe_adapter *adapter);
9a799d71 498extern void ixgbe_reset(struct ixgbe_adapter *adapter);
9a799d71 499extern void ixgbe_set_ethtool_ops(struct net_device *netdev);
b6ec895e
AD		 500extern int ixgbe_setup_rx_resources(struct ixgbe_ring *);
501extern int ixgbe_setup_tx_resources(struct ixgbe_ring *);
502extern void ixgbe_free_rx_resources(struct ixgbe_ring *);
503extern void ixgbe_free_tx_resources(struct ixgbe_ring *);
84418e3b
AD		 504extern void ixgbe_configure_rx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
505extern void ixgbe_configure_tx_ring(struct ixgbe_adapter *,struct ixgbe_ring *);
b4617240 506extern void ixgbe_update_stats(struct ixgbe_adapter *adapter);
2f90b865 507extern int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter);
7a921c93 508extern void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter);
84418e3b 509extern netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *,
84418e3b
AD		 510 struct ixgbe_adapter *,
511 struct ixgbe_ring *);
b6ec895e 512extern void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *,
84418e3b 513 struct ixgbe_tx_buffer *);
fc77dc3c 514extern void ixgbe_alloc_rx_buffers(struct ixgbe_ring *, u16);
fe49f04a
AD		 515extern void ixgbe_write_eitr(struct ixgbe_q_vector *);
516extern int ethtool_ioctl(struct ifreq *ifr);
ffff4772
PWJ		 517extern s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw);
518extern s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc);
519extern s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc);
520extern s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
521 struct ixgbe_atr_input *input,
522 u8 queue);
9a713e7c
PW		 523extern s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
524 struct ixgbe_atr_input *input,
525 struct ixgbe_atr_input_masks *input_masks,
526 u16 soft_id, u8 queue);
ffff4772
PWJ		 527extern s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input,
528 u16 vlan_id);
529extern s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input,
530 u32 src_addr);
531extern s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input,
532 u32 dst_addr);
ffff4772
PWJ		 533extern s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input,
534 u16 src_port);
535extern s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input,
536 u16 dst_port);
537extern s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input,
538 u16 flex_byte);
ffff4772
PWJ		 539extern s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input,
540 u8 l4type);
7f870475 541extern void ixgbe_set_rx_mode(struct net_device *netdev);
eacd73f7
YZ		 542#ifdef IXGBE_FCOE
543extern void ixgbe_configure_fcoe(struct ixgbe_adapter *adapter);
544extern int ixgbe_fso(struct ixgbe_adapter *adapter,
545 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
546 u32 tx_flags, u8 *hdr_len);
332d4a7d
YZ		 547extern void ixgbe_cleanup_fcoe(struct ixgbe_adapter *adapter);
548extern int ixgbe_fcoe_ddp(struct ixgbe_adapter *adapter,
549 union ixgbe_adv_rx_desc *rx_desc,
550 struct sk_buff *skb);
551extern int ixgbe_fcoe_ddp_get(struct net_device *netdev, u16 xid,
552 struct scatterlist *sgl, unsigned int sgc);
553extern int ixgbe_fcoe_ddp_put(struct net_device *netdev, u16 xid);
8450ff8c
YZ		 554extern int ixgbe_fcoe_enable(struct net_device *netdev);
555extern int ixgbe_fcoe_disable(struct net_device *netdev);
6ee16520
YZ		 556#ifdef CONFIG_IXGBE_DCB
557extern u8 ixgbe_fcoe_getapp(struct ixgbe_adapter *adapter);
558extern u8 ixgbe_fcoe_setapp(struct ixgbe_adapter *adapter, u8 up);
559#endif /* CONFIG_IXGBE_DCB */
61a1fa10 560extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type);
eacd73f7 561#endif /* IXGBE_FCOE */
9a799d71
AK		 562
563#endif /* _IXGBE_H_ */
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