#define __JME_H_INCLUDED__
#define DRV_NAME "jme"
-#define DRV_VERSION "1.0.7-jmmod"
+#define DRV_VERSION "1.0.8-jmmod"
#define PFX DRV_NAME ": "
#define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
};
#define TX_TIMEOUT (5 * HZ)
-#define JME_REG_LEN 0x500
+#define JME_REG_LEN 0x600
#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
#define JME_PHY_TIMEOUT 100 /* 100 msec */
#define JME_PHY_REG_NR 32
+#define JME_PHY_SPEC_REG_NR 128
/*
* Global Host Control
PREG17_SPEED_1000M = 0x8000,
};
+enum jme_phy_gctrl_masks {
+ JME_PHY_GCTRL_TESTMASK = 0xA000,
+};
+
+enum jme_phy_gctrl_vals {
+ JME_PHY_GCTRL_TESTOFF = 0x0000,
+ JME_PHY_GCTRL_TESTMODE1 = 0x2000,
+ JME_PHY_GCTRL_TESTMODE2 = 0x4000,
+ JME_PHY_GCTRL_TESTMODE3 = 0x6000,
+ JME_PHY_GCTRL_TESTMODE4 = 0x8000,
+};
+
#define BMSR_ANCOMP 0x0020
+/*
+ * For extended PHY register interface
+ */
+enum jme_phy_spec_regs {
+ JME_PHY_SPEC_ADDR_REG = 0x1E,
+ JME_PHY_SPEC_DATA_REG = 0x1F,
+};
+enum jme_phy_spec_addr_bits {
+ JME_PHY_SPEC_REG_READ = 0x4000u,
+ JME_PHY_SPEC_REG_WRITE = 0x8000u,
+};
+enum jme_extphy_regs {
+ JME_PHYEXT_COMM0 = 0x30,
+ JME_PHYEXT_COMM1 = 0x31,
+ JME_PHYEXT_COMM2 = 0x32,
+};
+
/*
* Workaround
*/
*/
static int jme_set_settings(struct net_device *netdev,
struct ethtool_cmd *ecmd);
+static void jme_set_unicastaddr(struct net_device *netdev);
static void jme_set_multi(struct net_device *netdev);
#endif