+/*
+ * For extended PHY register interface
+ */
+enum jme_phy_spec_regs {
+ JME_PHY_SPEC_ADDR_REG = 0x1E,
+ JME_PHY_SPEC_DATA_REG = 0x1F,
+};
+enum jme_phy_spec_addr_bits {
+ JME_PHY_SPEC_REG_READ = 0x4000u,
+ JME_PHY_SPEC_REG_WRITE = 0x8000u,
+};
+enum jme_extphy_regs {
+ JME_PHYEXT_COMM0 = 0x30,
+ JME_PHYEXT_COMM1 = 0x31,
+ JME_PHYEXT_COMM2 = 0x32,
+};
+