2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
28 #define DRV_NAME "jme"
29 #define DRV_VERSION "1.0.8-jmmod"
30 #define PFX DRV_NAME ": "
32 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
33 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
36 * Message related definitions
38 #define JME_DEF_MSG_ENABLE \
45 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
46 #define pr_err(fmt, arg...) \
47 printk(KERN_ERR fmt, ##arg)
49 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
50 #define netdev_err(netdev, fmt, arg...) \
55 #define tx_dbg(priv, fmt, args...) \
56 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
58 #define tx_dbg(priv, fmt, args...) \
61 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
65 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
66 #define jme_msg(msglvl, type, priv, fmt, args...) \
67 if (netif_msg_##type(priv)) \
68 printk(msglvl "%s: " fmt, (priv)->dev->name, ## args)
70 #define msg_probe(priv, fmt, args...) \
71 jme_msg(KERN_INFO, probe, priv, fmt, ## args)
73 #define msg_link(priv, fmt, args...) \
74 jme_msg(KERN_INFO, link, priv, fmt, ## args)
76 #define msg_intr(priv, fmt, args...) \
77 jme_msg(KERN_INFO, intr, priv, fmt, ## args)
79 #define msg_rx_err(priv, fmt, args...) \
80 jme_msg(KERN_ERR, rx_err, priv, fmt, ## args)
82 #define msg_rx_status(priv, fmt, args...) \
83 jme_msg(KERN_INFO, rx_status, priv, fmt, ## args)
85 #define msg_tx_err(priv, fmt, args...) \
86 jme_msg(KERN_ERR, tx_err, priv, fmt, ## args)
88 #define msg_tx_done(priv, fmt, args...) \
89 jme_msg(KERN_INFO, tx_done, priv, fmt, ## args)
91 #define msg_tx_queued(priv, fmt, args...) \
92 jme_msg(KERN_INFO, tx_queued, priv, fmt, ## args)
94 #define msg_hw(priv, fmt, args...) \
95 jme_msg(KERN_ERR, hw, priv, fmt, ## args)
97 #define netif_info(priv, type, dev, fmt, args...) \
98 msg_ ## type(priv, fmt, ## args)
99 #define netif_err(priv, type, dev, fmt, args...) \
100 msg_ ## type(priv, fmt, ## args)
104 #define NETIF_F_TSO6 0
106 #ifndef NETIF_F_IPV6_CSUM
107 #define NETIF_F_IPV6_CSUM 0
111 * Extra PCI Configuration space interface
113 #define PCI_DCSR_MRRS 0x59
114 #define PCI_DCSR_MRRS_MASK 0x70
116 enum pci_dcsr_mrrs_vals {
138 __u8 wn; /* Number of write actions */
139 __u8 rn; /* Number of read actions */
140 __u8 bitn; /* Number of bits per action */
141 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
142 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
144 /* Internal use only */
148 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
151 enum jme_spi_op_bits {
152 SPI_MODE_CPHA = 0x01,
153 SPI_MODE_CPOL = 0x02,
157 #define HALF_US 500 /* 500 ns */
158 #define JMESPIIOCTL SIOCDEVPRIVATE
160 #define PCI_PRIV_PE1 0xE4
162 enum pci_priv_pe1_bit_masks {
163 PE1_ASPMSUPRT = 0x00000003, /*
166 * (R/W Port of 5C[11:10])
168 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
169 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
170 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
171 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
172 PE1_GPREG0 = 0x0000FF00, /*
175 * [7:6] phy_giga BG control
176 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
179 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
180 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
181 PE1_REVID = 0xFF000000, /* RO: Rev ID */
184 enum pci_priv_pe1_values {
185 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
186 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
187 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
188 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
192 * Dynamic(adaptive)/Static PCC values
194 enum dynamic_pcc_values {
211 unsigned long last_bytes;
212 unsigned long last_pkts;
213 unsigned long intr_cnt;
215 unsigned char attempt;
218 #define PCC_INTERVAL_US 100000
219 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
220 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
221 #define PCC_P2_THRESHOLD 800
222 #define PCC_INTR_THRESHOLD 800
223 #define PCC_TX_TO 1000
229 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
231 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
232 #define TX_DESC_SIZE 16
234 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
294 enum jme_txdesc_flags_bits {
305 #define TXDESC_MSS_SHIFT 2
306 enum jme_txwbdesc_flags_bits {
309 TXWBFLAG_TMOUT = 0x20,
310 TXWBFLAG_TRYOUT = 0x10,
313 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
318 #define RX_DESC_SIZE 16
320 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
321 #define RX_BUF_DMA_ALIGN 8
322 #define RX_PREPAD_SIZE 10
323 #define ETH_CRC_LEN 2
324 #define RX_VLANHDR_LEN 2
325 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
372 enum jme_rxdesc_flags_bits {
378 enum jme_rxwbdesc_flags_bits {
379 RXWBFLAG_OWN = 0x8000,
380 RXWBFLAG_INT = 0x4000,
381 RXWBFLAG_MF = 0x2000,
382 RXWBFLAG_64BIT = 0x2000,
383 RXWBFLAG_TCPON = 0x1000,
384 RXWBFLAG_UDPON = 0x0800,
385 RXWBFLAG_IPCS = 0x0400,
386 RXWBFLAG_TCPCS = 0x0200,
387 RXWBFLAG_UDPCS = 0x0100,
388 RXWBFLAG_TAGON = 0x0080,
389 RXWBFLAG_IPV4 = 0x0040,
390 RXWBFLAG_IPV6 = 0x0020,
391 RXWBFLAG_PAUSE = 0x0010,
392 RXWBFLAG_MAGIC = 0x0008,
393 RXWBFLAG_WAKEUP = 0x0004,
394 RXWBFLAG_DEST = 0x0003,
395 RXWBFLAG_DEST_UNI = 0x0001,
396 RXWBFLAG_DEST_MUL = 0x0002,
397 RXWBFLAG_DEST_BRO = 0x0003,
400 enum jme_rxwbdesc_desccnt_mask {
401 RXWBDCNT_WBCPL = 0x80,
402 RXWBDCNT_DCNT = 0x7F,
405 enum jme_rxwbdesc_errstat_bits {
406 RXWBERR_LIMIT = 0x80,
407 RXWBERR_MIIER = 0x40,
408 RXWBERR_NIBON = 0x20,
409 RXWBERR_COLON = 0x10,
410 RXWBERR_ABORT = 0x08,
411 RXWBERR_SHORT = 0x04,
412 RXWBERR_OVERUN = 0x02,
413 RXWBERR_CRCERR = 0x01,
414 RXWBERR_ALLERR = 0xFF,
418 * Buffer information corresponding to ring descriptors.
420 struct jme_buffer_info {
425 unsigned long start_xmit;
429 * The structure holding buffer information and ring descriptors all together.
432 void *alloc; /* pointer to allocated memory */
433 void *desc; /* pointer to ring memory */
434 dma_addr_t dmaalloc; /* phys address of ring alloc */
435 dma_addr_t dma; /* phys address for ring dma */
437 /* Buffer information corresponding to each descriptor */
438 struct jme_buffer_info *bufinf;
441 atomic_t next_to_clean;
445 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
448 #define netdev_alloc_skb(dev, len) dev_alloc_skb(len)
449 #define PCI_VENDOR_ID_JMICRON 0x197B
452 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,19)
453 #define PCI_VDEVICE(vendor, device) \
454 PCI_VENDOR_ID_##vendor, (device), \
455 PCI_ANY_ID, PCI_ANY_ID, 0, 0
458 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
459 #define NET_STAT(priv) priv->stats
460 #define NETDEV_GET_STATS(netdev, fun_ptr) \
461 netdev->get_stats = fun_ptr
462 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
464 * CentOS 5.2 have *_hdr helpers back-ported
466 #ifdef RHEL_RELEASE_CODE
467 #if RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(5,2)
468 #define __DEFINE_IPHDR_HELPERS__
471 #define __DEFINE_IPHDR_HELPERS__
474 #define NET_STAT(priv) (priv->dev->stats)
475 #define NETDEV_GET_STATS(netdev, fun_ptr)
476 #define DECLARE_NET_DEVICE_STATS
479 #ifdef __DEFINE_IPHDR_HELPERS__
480 static inline struct iphdr *ip_hdr(const struct sk_buff *skb)
485 static inline struct ipv6hdr *ipv6_hdr(const struct sk_buff *skb)
487 return skb->nh.ipv6h;
490 static inline struct tcphdr *tcp_hdr(const struct sk_buff *skb)
496 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
497 #define DECLARE_NAPI_STRUCT
498 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
499 dev->poll = pollfn; \
501 #define JME_NAPI_HOLDER(holder) struct net_device *holder
502 #define JME_NAPI_WEIGHT(w) int *w
503 #define JME_NAPI_WEIGHT_VAL(w) *w
504 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
505 #define DECLARE_NETDEV struct net_device *netdev = jme->dev;
506 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
507 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
508 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
509 #define JME_RX_SCHEDULE_PREP(priv) \
510 netif_rx_schedule_prep(priv->dev)
511 #define JME_RX_SCHEDULE(priv) \
512 __netif_rx_schedule(priv->dev);
514 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
515 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
516 netif_napi_add(dev, napis, pollfn, q);
517 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
518 #define JME_NAPI_WEIGHT(w) int w
519 #define JME_NAPI_WEIGHT_VAL(w) w
520 #define JME_NAPI_WEIGHT_SET(w, r)
521 #define DECLARE_NETDEV
522 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
523 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
524 #define JME_NAPI_DISABLE(priv) \
525 if (!napi_disable_pending(&priv->napi)) \
526 napi_disable(&priv->napi);
527 #define JME_RX_SCHEDULE_PREP(priv) \
528 napi_schedule_prep(&priv->napi)
529 #define JME_RX_SCHEDULE(priv) \
530 __napi_schedule(&priv->napi);
533 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,38)
534 #define JME_NEW_PM_API
538 * Jmac Adapter Private data
541 struct pci_dev *pdev;
542 struct net_device *dev;
544 struct mii_if_info mii_if;
545 struct jme_ring rxring[RX_RING_NR];
546 struct jme_ring txring[TX_RING_NR];
548 spinlock_t macaddr_lock;
549 spinlock_t rxmcs_lock;
550 struct tasklet_struct rxempty_task;
551 struct tasklet_struct rxclean_task;
552 struct tasklet_struct txclean_task;
553 struct tasklet_struct linkch_task;
554 struct tasklet_struct pcc_task;
566 u32 tx_wake_threshold;
570 unsigned int fpgaver;
576 struct ethtool_cmd old_ecmd;
577 unsigned int old_mtu;
578 struct vlan_group *vlgrp;
579 struct dynpcc_info dpi;
581 atomic_t link_changing;
582 atomic_t tx_cleaning;
583 atomic_t rx_cleaning;
585 int (*jme_rx)(struct sk_buff *skb);
586 int (*jme_vlan_rx)(struct sk_buff *skb,
587 struct vlan_group *grp,
588 unsigned short vlan_tag);
590 DECLARE_NET_DEVICE_STATS
593 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
594 static struct net_device_stats *
595 jme_get_stats(struct net_device *netdev)
597 struct jme_adapter *jme = netdev_priv(netdev);
602 enum jme_flags_bits {
608 JME_FLAG_SHUTDOWN = 6,
611 #define TX_TIMEOUT (5 * HZ)
612 #define JME_REG_LEN 0x500
613 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
615 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
616 static inline struct jme_adapter*
617 jme_napi_priv(struct net_device *holder)
619 struct jme_adapter *jme;
620 jme = netdev_priv(holder);
624 static inline struct jme_adapter*
625 jme_napi_priv(struct napi_struct *napi)
627 struct jme_adapter *jme;
628 jme = container_of(napi, struct jme_adapter, napi);
636 enum jme_iomap_offsets {
643 enum jme_iomap_lens {
650 enum jme_iomap_regs {
651 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
652 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
653 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
654 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
655 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
656 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
657 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
658 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
660 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
661 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
662 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
663 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
664 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
665 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
666 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
667 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
668 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
669 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
670 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
671 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
673 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
674 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
675 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
678 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
679 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
680 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
681 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
682 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
685 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
686 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
687 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
688 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
689 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
690 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
691 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
692 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
693 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
694 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
695 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
696 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
697 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
698 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
699 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
700 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
704 * TX Control/Status Bits
707 TXCS_QUEUE7S = 0x00008000,
708 TXCS_QUEUE6S = 0x00004000,
709 TXCS_QUEUE5S = 0x00002000,
710 TXCS_QUEUE4S = 0x00001000,
711 TXCS_QUEUE3S = 0x00000800,
712 TXCS_QUEUE2S = 0x00000400,
713 TXCS_QUEUE1S = 0x00000200,
714 TXCS_QUEUE0S = 0x00000100,
715 TXCS_FIFOTH = 0x000000C0,
716 TXCS_DMASIZE = 0x00000030,
717 TXCS_BURST = 0x00000004,
718 TXCS_ENABLE = 0x00000001,
721 enum jme_txcs_value {
722 TXCS_FIFOTH_16QW = 0x000000C0,
723 TXCS_FIFOTH_12QW = 0x00000080,
724 TXCS_FIFOTH_8QW = 0x00000040,
725 TXCS_FIFOTH_4QW = 0x00000000,
727 TXCS_DMASIZE_64B = 0x00000000,
728 TXCS_DMASIZE_128B = 0x00000010,
729 TXCS_DMASIZE_256B = 0x00000020,
730 TXCS_DMASIZE_512B = 0x00000030,
732 TXCS_SELECT_QUEUE0 = 0x00000000,
733 TXCS_SELECT_QUEUE1 = 0x00010000,
734 TXCS_SELECT_QUEUE2 = 0x00020000,
735 TXCS_SELECT_QUEUE3 = 0x00030000,
736 TXCS_SELECT_QUEUE4 = 0x00040000,
737 TXCS_SELECT_QUEUE5 = 0x00050000,
738 TXCS_SELECT_QUEUE6 = 0x00060000,
739 TXCS_SELECT_QUEUE7 = 0x00070000,
741 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
745 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
748 * TX MAC Control/Status Bits
750 enum jme_txmcs_bit_masks {
751 TXMCS_IFG2 = 0xC0000000,
752 TXMCS_IFG1 = 0x30000000,
753 TXMCS_TTHOLD = 0x00000300,
754 TXMCS_FBURST = 0x00000080,
755 TXMCS_CARRIEREXT = 0x00000040,
756 TXMCS_DEFER = 0x00000020,
757 TXMCS_BACKOFF = 0x00000010,
758 TXMCS_CARRIERSENSE = 0x00000008,
759 TXMCS_COLLISION = 0x00000004,
760 TXMCS_CRC = 0x00000002,
761 TXMCS_PADDING = 0x00000001,
764 enum jme_txmcs_values {
765 TXMCS_IFG2_6_4 = 0x00000000,
766 TXMCS_IFG2_8_5 = 0x40000000,
767 TXMCS_IFG2_10_6 = 0x80000000,
768 TXMCS_IFG2_12_7 = 0xC0000000,
770 TXMCS_IFG1_8_4 = 0x00000000,
771 TXMCS_IFG1_12_6 = 0x10000000,
772 TXMCS_IFG1_16_8 = 0x20000000,
773 TXMCS_IFG1_20_10 = 0x30000000,
775 TXMCS_TTHOLD_1_8 = 0x00000000,
776 TXMCS_TTHOLD_1_4 = 0x00000100,
777 TXMCS_TTHOLD_1_2 = 0x00000200,
778 TXMCS_TTHOLD_FULL = 0x00000300,
780 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
788 enum jme_txpfc_bits_masks {
789 TXPFC_VLAN_TAG = 0xFFFF0000,
790 TXPFC_VLAN_EN = 0x00008000,
791 TXPFC_PF_EN = 0x00000001,
794 enum jme_txtrhd_bits_masks {
795 TXTRHD_TXPEN = 0x80000000,
796 TXTRHD_TXP = 0x7FFFFF00,
797 TXTRHD_TXREN = 0x00000080,
798 TXTRHD_TXRL = 0x0000007F,
801 enum jme_txtrhd_shifts {
802 TXTRHD_TXP_SHIFT = 8,
803 TXTRHD_TXRL_SHIFT = 0,
806 enum jme_txtrhd_values {
807 TXTRHD_FULLDUPLEX = 0x00000000,
808 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
809 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
811 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
815 * RX Control/Status Bits
817 enum jme_rxcs_bit_masks {
818 /* FIFO full threshold for transmitting Tx Pause Packet */
819 RXCS_FIFOTHTP = 0x30000000,
820 /* FIFO threshold for processing next packet */
821 RXCS_FIFOTHNP = 0x0C000000,
822 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
823 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
824 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
825 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
826 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
827 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
828 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
829 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
830 RXCS_QST = 0x00000004, /* Receive queue start */
831 RXCS_SUSPEND = 0x00000002,
832 RXCS_ENABLE = 0x00000001,
835 enum jme_rxcs_values {
836 RXCS_FIFOTHTP_16T = 0x00000000,
837 RXCS_FIFOTHTP_32T = 0x10000000,
838 RXCS_FIFOTHTP_64T = 0x20000000,
839 RXCS_FIFOTHTP_128T = 0x30000000,
841 RXCS_FIFOTHNP_16QW = 0x00000000,
842 RXCS_FIFOTHNP_32QW = 0x04000000,
843 RXCS_FIFOTHNP_64QW = 0x08000000,
844 RXCS_FIFOTHNP_128QW = 0x0C000000,
846 RXCS_DMAREQSZ_16B = 0x00000000,
847 RXCS_DMAREQSZ_32B = 0x01000000,
848 RXCS_DMAREQSZ_64B = 0x02000000,
849 RXCS_DMAREQSZ_128B = 0x03000000,
851 RXCS_QUEUESEL_Q0 = 0x00000000,
852 RXCS_QUEUESEL_Q1 = 0x00010000,
853 RXCS_QUEUESEL_Q2 = 0x00020000,
854 RXCS_QUEUESEL_Q3 = 0x00030000,
856 RXCS_RETRYGAP_256ns = 0x00000000,
857 RXCS_RETRYGAP_512ns = 0x00001000,
858 RXCS_RETRYGAP_1024ns = 0x00002000,
859 RXCS_RETRYGAP_2048ns = 0x00003000,
860 RXCS_RETRYGAP_4096ns = 0x00004000,
861 RXCS_RETRYGAP_8192ns = 0x00005000,
862 RXCS_RETRYGAP_16384ns = 0x00006000,
863 RXCS_RETRYGAP_32768ns = 0x00007000,
865 RXCS_RETRYCNT_0 = 0x00000000,
866 RXCS_RETRYCNT_4 = 0x00000100,
867 RXCS_RETRYCNT_8 = 0x00000200,
868 RXCS_RETRYCNT_12 = 0x00000300,
869 RXCS_RETRYCNT_16 = 0x00000400,
870 RXCS_RETRYCNT_20 = 0x00000500,
871 RXCS_RETRYCNT_24 = 0x00000600,
872 RXCS_RETRYCNT_28 = 0x00000700,
873 RXCS_RETRYCNT_32 = 0x00000800,
874 RXCS_RETRYCNT_36 = 0x00000900,
875 RXCS_RETRYCNT_40 = 0x00000A00,
876 RXCS_RETRYCNT_44 = 0x00000B00,
877 RXCS_RETRYCNT_48 = 0x00000C00,
878 RXCS_RETRYCNT_52 = 0x00000D00,
879 RXCS_RETRYCNT_56 = 0x00000E00,
880 RXCS_RETRYCNT_60 = 0x00000F00,
882 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
883 RXCS_FIFOTHNP_128QW |
885 RXCS_RETRYGAP_256ns |
889 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
892 * RX MAC Control/Status Bits
894 enum jme_rxmcs_bits {
895 RXMCS_ALLFRAME = 0x00000800,
896 RXMCS_BRDFRAME = 0x00000400,
897 RXMCS_MULFRAME = 0x00000200,
898 RXMCS_UNIFRAME = 0x00000100,
899 RXMCS_ALLMULFRAME = 0x00000080,
900 RXMCS_MULFILTERED = 0x00000040,
901 RXMCS_RXCOLLDEC = 0x00000020,
902 RXMCS_FLOWCTRL = 0x00000008,
903 RXMCS_VTAGRM = 0x00000004,
904 RXMCS_PREPAD = 0x00000002,
905 RXMCS_CHECKSUM = 0x00000001,
907 RXMCS_DEFAULT = RXMCS_VTAGRM |
914 * Wakeup Frame setup interface registers
916 #define WAKEUP_FRAME_NR 8
917 #define WAKEUP_FRAME_MASK_DWNR 4
919 enum jme_wfoi_bit_masks {
920 WFOI_MASK_SEL = 0x00000070,
921 WFOI_CRC_SEL = 0x00000008,
922 WFOI_FRAME_SEL = 0x00000007,
925 enum jme_wfoi_shifts {
930 * SMI Related definitions
932 enum jme_smi_bit_mask {
933 SMI_DATA_MASK = 0xFFFF0000,
934 SMI_REG_ADDR_MASK = 0x0000F800,
935 SMI_PHY_ADDR_MASK = 0x000007C0,
936 SMI_OP_WRITE = 0x00000020,
937 /* Set to 1, after req done it'll be cleared to 0 */
938 SMI_OP_REQ = 0x00000010,
939 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
940 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
941 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
942 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
945 enum jme_smi_bit_shift {
947 SMI_REG_ADDR_SHIFT = 11,
948 SMI_PHY_ADDR_SHIFT = 6,
951 static inline u32 smi_reg_addr(int x)
953 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
956 static inline u32 smi_phy_addr(int x)
958 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
961 #define JME_PHY_TIMEOUT 100 /* 100 msec */
962 #define JME_PHY_REG_NR 32
965 * Global Host Control
967 enum jme_ghc_bit_mask {
968 GHC_SWRST = 0x40000000,
969 GHC_TO_CLK_SRC = 0x00C00000,
970 GHC_TXMAC_CLK_SRC = 0x00300000,
971 GHC_DPX = 0x00000040,
972 GHC_SPEED = 0x00000030,
973 GHC_LINK_POLL = 0x00000001,
976 enum jme_ghc_speed_val {
977 GHC_SPEED_10M = 0x00000010,
978 GHC_SPEED_100M = 0x00000020,
979 GHC_SPEED_1000M = 0x00000030,
982 enum jme_ghc_to_clk {
983 GHC_TO_CLK_OFF = 0x00000000,
984 GHC_TO_CLK_GPHY = 0x00400000,
985 GHC_TO_CLK_PCIE = 0x00800000,
986 GHC_TO_CLK_INVALID = 0x00C00000,
989 enum jme_ghc_txmac_clk {
990 GHC_TXMAC_CLK_OFF = 0x00000000,
991 GHC_TXMAC_CLK_GPHY = 0x00100000,
992 GHC_TXMAC_CLK_PCIE = 0x00200000,
993 GHC_TXMAC_CLK_INVALID = 0x00300000,
997 * Power management control and status register
999 enum jme_pmcs_bit_masks {
1000 PMCS_STMASK = 0xFFFF0000,
1001 PMCS_WF7DET = 0x80000000,
1002 PMCS_WF6DET = 0x40000000,
1003 PMCS_WF5DET = 0x20000000,
1004 PMCS_WF4DET = 0x10000000,
1005 PMCS_WF3DET = 0x08000000,
1006 PMCS_WF2DET = 0x04000000,
1007 PMCS_WF1DET = 0x02000000,
1008 PMCS_WF0DET = 0x01000000,
1009 PMCS_LFDET = 0x00040000,
1010 PMCS_LRDET = 0x00020000,
1011 PMCS_MFDET = 0x00010000,
1012 PMCS_ENMASK = 0x0000FFFF,
1013 PMCS_WF7EN = 0x00008000,
1014 PMCS_WF6EN = 0x00004000,
1015 PMCS_WF5EN = 0x00002000,
1016 PMCS_WF4EN = 0x00001000,
1017 PMCS_WF3EN = 0x00000800,
1018 PMCS_WF2EN = 0x00000400,
1019 PMCS_WF1EN = 0x00000200,
1020 PMCS_WF0EN = 0x00000100,
1021 PMCS_LFEN = 0x00000004,
1022 PMCS_LREN = 0x00000002,
1023 PMCS_MFEN = 0x00000001,
1027 * New PHY Power Control Register
1029 enum jme_phy_pwr_bit_masks {
1030 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
1031 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
1032 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
1033 PHY_PWR_CLKSEL = 0x08000000, /*
1034 * XTL_OUT Clock select
1035 * (an internal free-running clock)
1036 * 0: xtl_out = phy_giga.A_XTL25_O
1037 * 1: xtl_out = phy_giga.PD_OSC
1042 * Giga PHY Status Registers
1044 enum jme_phy_link_bit_mask {
1045 PHY_LINK_SPEED_MASK = 0x0000C000,
1046 PHY_LINK_DUPLEX = 0x00002000,
1047 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
1048 PHY_LINK_UP = 0x00000400,
1049 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
1050 PHY_LINK_MDI_STAT = 0x00000040,
1053 enum jme_phy_link_speed_val {
1054 PHY_LINK_SPEED_10M = 0x00000000,
1055 PHY_LINK_SPEED_100M = 0x00004000,
1056 PHY_LINK_SPEED_1000M = 0x00008000,
1059 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
1062 * SMB Control and Status
1064 enum jme_smbcsr_bit_mask {
1065 SMBCSR_CNACK = 0x00020000,
1066 SMBCSR_RELOAD = 0x00010000,
1067 SMBCSR_EEPROMD = 0x00000020,
1068 SMBCSR_INITDONE = 0x00000010,
1069 SMBCSR_BUSY = 0x0000000F,
1072 enum jme_smbintf_bit_mask {
1073 SMBINTF_HWDATR = 0xFF000000,
1074 SMBINTF_HWDATW = 0x00FF0000,
1075 SMBINTF_HWADDR = 0x0000FF00,
1076 SMBINTF_HWRWN = 0x00000020,
1077 SMBINTF_HWCMD = 0x00000010,
1078 SMBINTF_FASTM = 0x00000008,
1079 SMBINTF_GPIOSCL = 0x00000004,
1080 SMBINTF_GPIOSDA = 0x00000002,
1081 SMBINTF_GPIOEN = 0x00000001,
1084 enum jme_smbintf_vals {
1085 SMBINTF_HWRWN_READ = 0x00000020,
1086 SMBINTF_HWRWN_WRITE = 0x00000000,
1089 enum jme_smbintf_shifts {
1090 SMBINTF_HWDATR_SHIFT = 24,
1091 SMBINTF_HWDATW_SHIFT = 16,
1092 SMBINTF_HWADDR_SHIFT = 8,
1095 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
1096 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
1097 #define JME_SMB_LEN 256
1098 #define JME_EEPROM_MAGIC 0x250
1101 * Timer Control/Status Register
1103 enum jme_tmcsr_bit_masks {
1104 TMCSR_SWIT = 0x80000000,
1105 TMCSR_EN = 0x01000000,
1106 TMCSR_CNT = 0x00FFFFFF,
1110 * General Purpose REG-0
1112 enum jme_gpreg0_masks {
1113 GPREG0_DISSH = 0xFF000000,
1114 GPREG0_PCIRLMT = 0x00300000,
1115 GPREG0_PCCNOMUTCLR = 0x00040000,
1116 GPREG0_LNKINTPOLL = 0x00001000,
1117 GPREG0_PCCTMR = 0x00000300,
1118 GPREG0_PHYADDR = 0x0000001F,
1121 enum jme_gpreg0_vals {
1122 GPREG0_DISSH_DW7 = 0x80000000,
1123 GPREG0_DISSH_DW6 = 0x40000000,
1124 GPREG0_DISSH_DW5 = 0x20000000,
1125 GPREG0_DISSH_DW4 = 0x10000000,
1126 GPREG0_DISSH_DW3 = 0x08000000,
1127 GPREG0_DISSH_DW2 = 0x04000000,
1128 GPREG0_DISSH_DW1 = 0x02000000,
1129 GPREG0_DISSH_DW0 = 0x01000000,
1130 GPREG0_DISSH_ALL = 0xFF000000,
1132 GPREG0_PCIRLMT_8 = 0x00000000,
1133 GPREG0_PCIRLMT_6 = 0x00100000,
1134 GPREG0_PCIRLMT_5 = 0x00200000,
1135 GPREG0_PCIRLMT_4 = 0x00300000,
1137 GPREG0_PCCTMR_16ns = 0x00000000,
1138 GPREG0_PCCTMR_256ns = 0x00000100,
1139 GPREG0_PCCTMR_1us = 0x00000200,
1140 GPREG0_PCCTMR_1ms = 0x00000300,
1142 GPREG0_PHYADDR_1 = 0x00000001,
1144 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1150 * General Purpose REG-1
1152 enum jme_gpreg1_bit_masks {
1153 GPREG1_RXCLKOFF = 0x04000000,
1154 GPREG1_PCREQN = 0x00020000,
1155 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1156 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1157 GPREG1_INTRDELAYUNIT = 0x00000018,
1158 GPREG1_INTRDELAYENABLE = 0x00000007,
1161 enum jme_gpreg1_vals {
1162 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1163 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1164 GPREG1_INTDLYUNIT_1US = 0x00000010,
1165 GPREG1_INTDLYUNIT_16US = 0x00000018,
1167 GPREG1_INTDLYEN_1U = 0x00000001,
1168 GPREG1_INTDLYEN_2U = 0x00000002,
1169 GPREG1_INTDLYEN_3U = 0x00000003,
1170 GPREG1_INTDLYEN_4U = 0x00000004,
1171 GPREG1_INTDLYEN_5U = 0x00000005,
1172 GPREG1_INTDLYEN_6U = 0x00000006,
1173 GPREG1_INTDLYEN_7U = 0x00000007,
1175 GPREG1_DEFAULT = GPREG1_PCREQN,
1179 * Interrupt Status Bits
1181 enum jme_interrupt_bits {
1182 INTR_SWINTR = 0x80000000,
1183 INTR_TMINTR = 0x40000000,
1184 INTR_LINKCH = 0x20000000,
1185 INTR_PAUSERCV = 0x10000000,
1186 INTR_MAGICRCV = 0x08000000,
1187 INTR_WAKERCV = 0x04000000,
1188 INTR_PCCRX0TO = 0x02000000,
1189 INTR_PCCRX1TO = 0x01000000,
1190 INTR_PCCRX2TO = 0x00800000,
1191 INTR_PCCRX3TO = 0x00400000,
1192 INTR_PCCTXTO = 0x00200000,
1193 INTR_PCCRX0 = 0x00100000,
1194 INTR_PCCRX1 = 0x00080000,
1195 INTR_PCCRX2 = 0x00040000,
1196 INTR_PCCRX3 = 0x00020000,
1197 INTR_PCCTX = 0x00010000,
1198 INTR_RX3EMP = 0x00008000,
1199 INTR_RX2EMP = 0x00004000,
1200 INTR_RX1EMP = 0x00002000,
1201 INTR_RX0EMP = 0x00001000,
1202 INTR_RX3 = 0x00000800,
1203 INTR_RX2 = 0x00000400,
1204 INTR_RX1 = 0x00000200,
1205 INTR_RX0 = 0x00000100,
1206 INTR_TX7 = 0x00000080,
1207 INTR_TX6 = 0x00000040,
1208 INTR_TX5 = 0x00000020,
1209 INTR_TX4 = 0x00000010,
1210 INTR_TX3 = 0x00000008,
1211 INTR_TX2 = 0x00000004,
1212 INTR_TX1 = 0x00000002,
1213 INTR_TX0 = 0x00000001,
1216 static const u32 INTR_ENABLE = INTR_SWINTR |
1226 * PCC Control Registers
1228 enum jme_pccrx_masks {
1229 PCCRXTO_MASK = 0xFFFF0000,
1230 PCCRX_MASK = 0x0000FF00,
1233 enum jme_pcctx_masks {
1234 PCCTXTO_MASK = 0xFFFF0000,
1235 PCCTX_MASK = 0x0000FF00,
1236 PCCTX_QS_MASK = 0x000000FF,
1239 enum jme_pccrx_shifts {
1244 enum jme_pcctx_shifts {
1249 enum jme_pcctx_bits {
1250 PCCTXQ0_EN = 0x00000001,
1251 PCCTXQ1_EN = 0x00000002,
1252 PCCTXQ2_EN = 0x00000004,
1253 PCCTXQ3_EN = 0x00000008,
1254 PCCTXQ4_EN = 0x00000010,
1255 PCCTXQ5_EN = 0x00000020,
1256 PCCTXQ6_EN = 0x00000040,
1257 PCCTXQ7_EN = 0x00000080,
1261 * Chip Mode Register
1263 enum jme_chipmode_bit_masks {
1264 CM_FPGAVER_MASK = 0xFFFF0000,
1265 CM_CHIPREV_MASK = 0x0000FF00,
1266 CM_CHIPMODE_MASK = 0x0000000F,
1269 enum jme_chipmode_shifts {
1270 CM_FPGAVER_SHIFT = 16,
1271 CM_CHIPREV_SHIFT = 8,
1275 * Aggressive Power Mode Control
1277 enum jme_apmc_bits {
1278 JME_APMC_PCIE_SD_EN = 0x40000000,
1279 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1280 JME_APMC_EPIEN = 0x04000000,
1281 JME_APMC_EPIEN_CTRL = 0x03000000,
1284 enum jme_apmc_values {
1285 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1286 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1289 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1292 static char *MAC_REG_NAME[] = {
1293 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1294 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1295 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1296 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1297 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1298 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1301 static char *PE_REG_NAME[] = {
1302 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1303 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1304 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1305 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1306 "JME_SMBCSR", "JME_SMBINTF"};
1308 static char *MISC_REG_NAME[] = {
1309 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1310 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1311 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1312 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1313 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1314 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1315 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1316 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1319 static inline void reg_dbg(const struct jme_adapter *jme,
1320 const char *msg, u32 val, u32 reg)
1322 const char *regname;
1323 switch (reg & 0xF00) {
1325 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1328 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1331 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1334 regname = PE_REG_NAME[0];
1336 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1340 static inline void reg_dbg(const struct jme_adapter *jme,
1341 const char *msg, u32 val, u32 reg) {}
1345 * Read/Write MMaped I/O Registers
1347 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1349 return readl(jme->regs + reg);
1352 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1354 reg_dbg(jme, "REG WRITE", val, reg);
1355 writel(val, jme->regs + reg);
1356 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1359 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1362 * Read after write should cause flush
1364 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1365 writel(val, jme->regs + reg);
1366 readl(jme->regs + reg);
1367 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1373 enum jme_phy_reg17_bit_masks {
1374 PREG17_SPEED = 0xC000,
1375 PREG17_DUPLEX = 0x2000,
1376 PREG17_SPDRSV = 0x0800,
1377 PREG17_LNKUP = 0x0400,
1378 PREG17_MDI = 0x0040,
1381 enum jme_phy_reg17_vals {
1382 PREG17_SPEED_10M = 0x0000,
1383 PREG17_SPEED_100M = 0x4000,
1384 PREG17_SPEED_1000M = 0x8000,
1387 #define BMSR_ANCOMP 0x0020
1392 static inline int is_buggy250(unsigned short device, u8 chiprev)
1394 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1397 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1399 return chip_main_rev >= 5;
1403 * Function prototypes
1405 static int jme_set_settings(struct net_device *netdev,
1406 struct ethtool_cmd *ecmd);
1407 static void jme_set_unicastaddr(struct net_device *netdev);
1408 static void jme_set_multi(struct net_device *netdev);