2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/version.h>
26 #define DRV_NAME "jme"
27 #define DRV_VERSION "0.9d-msix"
28 #define PFX DRV_NAME ": "
30 #define JME_GE_DEVICE 0x250
31 #define JME_FE_DEVICE 0x260
34 #define dprintk(devname, fmt, args...) \
35 printk(KERN_DEBUG "%s: " fmt, devname, ## args)
37 #define dprintk(devname, fmt, args...)
41 #define tx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
43 #define tx_dbg(args...)
47 #define rx_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
49 #define rx_dbg(args...)
53 #define queue_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
55 #define queue_dbg(args...)
59 #define csum_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
61 #define csum_dbg(args...)
65 #define vlan_dbg(devname, fmt, args...) dprintk(devname, fmt, ## args)
67 #define vlan_dbg(args...)
70 #define jprintk(devname, fmt, args...) \
71 printk(KERN_INFO "%s: " fmt, devname, ## args)
73 #define jeprintk(devname, fmt, args...) \
74 printk(KERN_ERR "%s: " fmt, devname, ## args)
76 #define PCI_CONF_DCSR_MRRS 0x59
77 #define PCI_CONF_DCSR_MRRS_MASK 0x70
78 enum pci_conf_dcsr_mrrs_vals {
87 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
88 #define MIN_ETHERNET_PACKET_SIZE 60
91 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
92 #define NET_STAT(priv) priv->stats
93 #define NETDEV_GET_STATS(netdev, fun_ptr) \
94 netdev->get_stats = fun_ptr
95 #define DECLARE_NET_DEVICE_STATS struct net_device_stats stats;
97 #define NET_STAT(priv) priv->dev->stats
98 #define NETDEV_GET_STATS(netdev, fun_ptr)
99 #define DECLARE_NET_DEVICE_STATS
102 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
103 #define DECLARE_NAPI_STRUCT
104 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
105 dev->poll = pollfn; \
107 #define JME_NAPI_HOLDER(holder) struct net_device *holder
108 #define JME_NAPI_WEIGHT(w) int *w
109 #define JME_NAPI_WEIGHT_VAL(w) *w
110 #define JME_NAPI_WEIGHT_SET(w, r) *w = r
111 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev)
112 #define JME_NAPI_ENABLE(priv) netif_poll_enable(priv->dev);
113 #define JME_NAPI_DISABLE(priv) netif_poll_disable(priv->dev);
114 #define JME_RX_SCHEDULE_PREP(priv) \
115 netif_rx_schedule_prep(priv->dev)
116 #define JME_RX_SCHEDULE(priv) \
117 __netif_rx_schedule(priv->dev);
119 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
120 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
121 netif_napi_add(dev, napis, pollfn, q);
122 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
123 #define JME_NAPI_WEIGHT(w) int w
124 #define JME_NAPI_WEIGHT_VAL(w) w
125 #define JME_NAPI_WEIGHT_SET(w, r)
126 #define JME_RX_COMPLETE(dev, napis) netif_rx_complete(dev, napis)
127 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
128 #define JME_NAPI_DISABLE(priv) \
129 if(!napi_disable_pending(&priv->napi)) \
130 napi_disable(&priv->napi);
131 #define JME_RX_SCHEDULE_PREP(priv) \
132 netif_rx_schedule_prep(priv->dev, &priv->napi)
133 #define JME_RX_SCHEDULE(priv) \
134 __netif_rx_schedule(priv->dev, &priv->napi);
138 enum dynamic_pcc_values {
155 unsigned long last_bytes;
156 unsigned long last_pkts;
157 unsigned long intr_cnt;
159 unsigned char attempt;
162 #define PCC_INTERVAL_US 100000
163 #define PCC_INTERVAL (HZ / (1000000/PCC_INTERVAL_US))
164 #define PCC_P3_THRESHOLD 2*1024*1024
165 #define PCC_P2_THRESHOLD 800
166 #define PCC_INTR_THRESHOLD 800
167 #define PCC_TX_TO 333
173 * TX/RX Ring DESC Count Must be multiple of 16
174 * RX Ring DESC Count Must be <= 1024
176 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
178 #define TX_DESC_SIZE 16
180 #define TX_RING_ALLOC_SIZE(s) (s * TX_DESC_SIZE) + RING_DESC_ALIGN
239 enum jme_txdesc_flags_bits {
249 #define TXDESC_MSS_SHIFT 2
250 enum jme_rxdescwb_flags_bits {
253 TXWBFLAG_TMOUT = 0x20,
254 TXWBFLAG_TRYOUT = 0x10,
257 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
263 #define RX_DESC_SIZE 16
265 #define RX_RING_ALLOC_SIZE(s) (s * RX_DESC_SIZE) + RING_DESC_ALIGN
267 #define RX_BUF_DMA_ALIGN 8
268 #define RX_PREPAD_SIZE 10
269 #define ETH_CRC_LEN 2
270 #define RX_VLANHDR_LEN 2
271 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
317 enum jme_rxdesc_flags_bits {
322 enum jme_rxwbdesc_flags_bits {
323 RXWBFLAG_OWN = 0x8000,
324 RXWBFLAG_INT = 0x4000,
325 RXWBFLAG_MF = 0x2000,
326 RXWBFLAG_64BIT = 0x2000,
327 RXWBFLAG_TCPON = 0x1000,
328 RXWBFLAG_UDPON = 0x0800,
329 RXWBFLAG_IPCS = 0x0400,
330 RXWBFLAG_TCPCS = 0x0200,
331 RXWBFLAG_UDPCS = 0x0100,
332 RXWBFLAG_TAGON = 0x0080,
333 RXWBFLAG_IPV4 = 0x0040,
334 RXWBFLAG_IPV6 = 0x0020,
335 RXWBFLAG_PAUSE = 0x0010,
336 RXWBFLAG_MAGIC = 0x0008,
337 RXWBFLAG_WAKEUP = 0x0004,
338 RXWBFLAG_DEST = 0x0003,
339 RXWBFLAG_DEST_UNI = 0x0001,
340 RXWBFLAG_DEST_MUL = 0x0002,
341 RXWBFLAG_DEST_BRO = 0x0003,
343 enum jme_rxwbdesc_desccnt_mask {
344 RXWBDCNT_WBCPL = 0x80,
345 RXWBDCNT_DCNT = 0x7F,
347 enum jme_rxwbdesc_errstat_bits {
348 RXWBERR_LIMIT = 0x80,
349 RXWBERR_MIIER = 0x40,
350 RXWBERR_NIBON = 0x20,
351 RXWBERR_COLON = 0x10,
352 RXWBERR_ABORT = 0x08,
353 RXWBERR_SHORT = 0x04,
354 RXWBERR_OVERUN = 0x02,
355 RXWBERR_CRCERR = 0x01,
356 RXWBERR_ALLERR = 0xFF,
359 struct jme_buffer_info {
364 unsigned long start_xmit;
367 #define MAX_RING_DESC_NR 1024
369 void* alloc; /* pointer to allocated memory */
370 volatile void* desc; /* pointer to ring memory */
371 dma_addr_t dmaalloc; /* phys address of ring alloc */
372 dma_addr_t dma; /* phys address for ring dma */
374 /* Buffer information corresponding to each descriptor */
375 struct jme_buffer_info bufinf[MAX_RING_DESC_NR];
378 atomic_t next_to_clean;
382 #define JME_MSIX_VEC_NR 3
383 struct jme_msix_info {
384 irq_handler_t handler;
391 * Jmac Adapter Private data
393 #define SHADOW_REG_NR 8
395 struct pci_dev *pdev;
396 struct net_device *dev;
398 dma_addr_t shadow_dma;
400 struct mii_if_info mii_if;
401 struct jme_ring rxring[RX_RING_NR];
402 struct jme_ring txring[TX_RING_NR];
404 spinlock_t macaddr_lock;
405 spinlock_t rxmcs_lock;
406 struct tasklet_struct rxempty_task;
407 struct tasklet_struct rxclean_task;
408 struct tasklet_struct txclean_task;
409 struct tasklet_struct linkch_task;
410 struct tasklet_struct pcc_task;
411 struct jme_msix_info msix[JME_MSIX_VEC_NR];
422 __u32 tx_wake_threshold;
428 struct ethtool_cmd old_ecmd;
429 unsigned int old_mtu;
430 struct vlan_group* vlgrp;
431 struct dynpcc_info dpi;
433 atomic_t link_changing;
434 atomic_t tx_cleaning;
435 atomic_t rx_cleaning;
437 int (*jme_rx)(struct sk_buff *skb);
438 int (*jme_vlan_rx)(struct sk_buff *skb,
439 struct vlan_group *grp,
440 unsigned short vlan_tag);
442 DECLARE_NET_DEVICE_STATS
444 enum shadow_reg_val {
447 enum jme_flags_bits {
448 JME_FLAG_MSI = 0x00000001,
449 JME_FLAG_MSIX = 0x00000002,
450 JME_FLAG_SSET = 0x00000004,
451 JME_FLAG_TXCSUM = 0x00000008,
452 JME_FLAG_TSO = 0x00000010,
453 JME_FLAG_POLL = 0x00000020,
455 #define WAIT_TASKLET_TIMEOUT 500 /* 500 ms */
456 #define TX_TIMEOUT (5*HZ)
457 #define JME_REG_LEN 0x500
459 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,23)
460 __always_inline static struct jme_adapter*
461 jme_napi_priv(struct net_device *holder)
463 struct jme_adapter* jme;
464 jme = netdev_priv(holder);
468 __always_inline static struct jme_adapter*
469 jme_napi_priv(struct napi_struct *napi)
471 struct jme_adapter* jme;
472 jme = container_of(napi, struct jme_adapter, napi);
480 enum jme_iomap_offsets {
487 enum jme_iomap_lens {
494 enum jme_iomap_regs {
495 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
496 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
497 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
498 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
499 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
500 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
501 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
502 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
504 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
505 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
506 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
507 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
508 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
509 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
510 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
511 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
512 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
513 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
514 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
515 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
517 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
518 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
519 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
522 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
523 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
524 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
525 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
528 JME_TMCSR = JME_MISC| 0x00, /* Timer Control/Status Register */
529 JME_GPREG0 = JME_MISC| 0x08, /* General purpose REG-0 */
530 JME_GPREG1 = JME_MISC| 0x0C, /* General purpose REG-1 */
531 JME_MSIX_ENT = JME_MISC| 0x10, /* MSIX Entry table */
532 JME_IEVE = JME_MISC| 0x20, /* Interrupt Event Status */
533 JME_IREQ = JME_MISC| 0x24, /* Interrupt Req Status(For Debug) */
534 JME_IENS = JME_MISC| 0x28, /* Interrupt Enable - Setting Port */
535 JME_IENC = JME_MISC| 0x2C, /* Interrupt Enable - Clear Port */
536 JME_PCCRX0 = JME_MISC| 0x30, /* PCC Control for RX Queue 0 */
537 JME_PCCTX = JME_MISC| 0x40, /* PCC Control for TX Queues */
538 JME_CHIPMODE = JME_MISC| 0x44, /* Identify FPGA Version */
539 JME_SHBA_HI = JME_MISC| 0x48, /* Shadow Register Base HI */
540 JME_SHBA_LO = JME_MISC| 0x4C, /* Shadow Register Base LO */
541 JME_PCCSRX0 = JME_MISC| 0x80, /* PCC Status of RX0 */
545 * TX Control/Status Bits
548 TXCS_QUEUE7S = 0x00008000,
549 TXCS_QUEUE6S = 0x00004000,
550 TXCS_QUEUE5S = 0x00002000,
551 TXCS_QUEUE4S = 0x00001000,
552 TXCS_QUEUE3S = 0x00000800,
553 TXCS_QUEUE2S = 0x00000400,
554 TXCS_QUEUE1S = 0x00000200,
555 TXCS_QUEUE0S = 0x00000100,
556 TXCS_FIFOTH = 0x000000C0,
557 TXCS_DMASIZE = 0x00000030,
558 TXCS_BURST = 0x00000004,
559 TXCS_ENABLE = 0x00000001,
561 enum jme_txcs_value {
562 TXCS_FIFOTH_16QW = 0x000000C0,
563 TXCS_FIFOTH_12QW = 0x00000080,
564 TXCS_FIFOTH_8QW = 0x00000040,
565 TXCS_FIFOTH_4QW = 0x00000000,
567 TXCS_DMASIZE_64B = 0x00000000,
568 TXCS_DMASIZE_128B = 0x00000010,
569 TXCS_DMASIZE_256B = 0x00000020,
570 TXCS_DMASIZE_512B = 0x00000030,
572 TXCS_SELECT_QUEUE0 = 0x00000000,
573 TXCS_SELECT_QUEUE1 = 0x00010000,
574 TXCS_SELECT_QUEUE2 = 0x00020000,
575 TXCS_SELECT_QUEUE3 = 0x00030000,
576 TXCS_SELECT_QUEUE4 = 0x00040000,
577 TXCS_SELECT_QUEUE5 = 0x00050000,
578 TXCS_SELECT_QUEUE6 = 0x00060000,
579 TXCS_SELECT_QUEUE7 = 0x00070000,
581 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
584 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
587 * TX MAC Control/Status Bits
589 enum jme_txmcs_bit_masks {
590 TXMCS_IFG2 = 0xC0000000,
591 TXMCS_IFG1 = 0x30000000,
592 TXMCS_TTHOLD = 0x00000300,
593 TXMCS_FBURST = 0x00000080,
594 TXMCS_CARRIEREXT = 0x00000040,
595 TXMCS_DEFER = 0x00000020,
596 TXMCS_BACKOFF = 0x00000010,
597 TXMCS_CARRIERSENSE = 0x00000008,
598 TXMCS_COLLISION = 0x00000004,
599 TXMCS_CRC = 0x00000002,
600 TXMCS_PADDING = 0x00000001,
602 enum jme_txmcs_values {
603 TXMCS_IFG2_6_4 = 0x00000000,
604 TXMCS_IFG2_8_5 = 0x40000000,
605 TXMCS_IFG2_10_6 = 0x80000000,
606 TXMCS_IFG2_12_7 = 0xC0000000,
608 TXMCS_IFG1_8_4 = 0x00000000,
609 TXMCS_IFG1_12_6 = 0x10000000,
610 TXMCS_IFG1_16_8 = 0x20000000,
611 TXMCS_IFG1_20_10 = 0x30000000,
613 TXMCS_TTHOLD_1_8 = 0x00000000,
614 TXMCS_TTHOLD_1_4 = 0x00000100,
615 TXMCS_TTHOLD_1_2 = 0x00000200,
616 TXMCS_TTHOLD_FULL = 0x00000300,
618 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
626 enum jme_txpfc_bits_masks {
627 TXPFC_VLAN_TAG = 0xFFFF0000,
628 TXPFC_VLAN_EN = 0x00008000,
629 TXPFC_PF_EN = 0x00000001,
632 enum jme_txtrhd_bits_masks {
633 TXTRHD_TXPEN = 0x80000000,
634 TXTRHD_TXP = 0x7FFFFF00,
635 TXTRHD_TXREN = 0x00000080,
636 TXTRHD_TXRL = 0x0000007F,
638 enum jme_txtrhd_shifts {
639 TXTRHD_TXP_SHIFT = 8,
640 TXTRHD_TXRL_SHIFT = 0,
645 * RX Control/Status Bits
647 enum jme_rxcs_bit_masks {
648 /* FIFO full threshold for transmitting Tx Pause Packet */
649 RXCS_FIFOTHTP = 0x30000000,
650 /* FIFO threshold for processing next packet */
651 RXCS_FIFOTHNP = 0x0C000000,
652 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
653 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
654 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
655 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
656 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
657 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
658 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
659 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
660 RXCS_QST = 0x00000004, /* Receive queue start */
661 RXCS_SUSPEND = 0x00000002,
662 RXCS_ENABLE = 0x00000001,
664 enum jme_rxcs_values {
665 RXCS_FIFOTHTP_16T = 0x00000000,
666 RXCS_FIFOTHTP_32T = 0x10000000,
667 RXCS_FIFOTHTP_64T = 0x20000000,
668 RXCS_FIFOTHTP_128T = 0x30000000,
670 RXCS_FIFOTHNP_16QW = 0x00000000,
671 RXCS_FIFOTHNP_32QW = 0x04000000,
672 RXCS_FIFOTHNP_64QW = 0x08000000,
673 RXCS_FIFOTHNP_128QW = 0x0C000000,
675 RXCS_DMAREQSZ_16B = 0x00000000,
676 RXCS_DMAREQSZ_32B = 0x01000000,
677 RXCS_DMAREQSZ_64B = 0x02000000,
678 RXCS_DMAREQSZ_128B = 0x03000000,
680 RXCS_QUEUESEL_Q0 = 0x00000000,
681 RXCS_QUEUESEL_Q1 = 0x00010000,
682 RXCS_QUEUESEL_Q2 = 0x00020000,
683 RXCS_QUEUESEL_Q3 = 0x00030000,
685 RXCS_RETRYGAP_256ns = 0x00000000,
686 RXCS_RETRYGAP_512ns = 0x00001000,
687 RXCS_RETRYGAP_1024ns = 0x00002000,
688 RXCS_RETRYGAP_2048ns = 0x00003000,
689 RXCS_RETRYGAP_4096ns = 0x00004000,
690 RXCS_RETRYGAP_8192ns = 0x00005000,
691 RXCS_RETRYGAP_16384ns = 0x00006000,
692 RXCS_RETRYGAP_32768ns = 0x00007000,
694 RXCS_RETRYCNT_0 = 0x00000000,
695 RXCS_RETRYCNT_4 = 0x00000100,
696 RXCS_RETRYCNT_8 = 0x00000200,
697 RXCS_RETRYCNT_12 = 0x00000300,
698 RXCS_RETRYCNT_16 = 0x00000400,
699 RXCS_RETRYCNT_20 = 0x00000500,
700 RXCS_RETRYCNT_24 = 0x00000600,
701 RXCS_RETRYCNT_28 = 0x00000700,
702 RXCS_RETRYCNT_32 = 0x00000800,
703 RXCS_RETRYCNT_36 = 0x00000900,
704 RXCS_RETRYCNT_40 = 0x00000A00,
705 RXCS_RETRYCNT_44 = 0x00000B00,
706 RXCS_RETRYCNT_48 = 0x00000C00,
707 RXCS_RETRYCNT_52 = 0x00000D00,
708 RXCS_RETRYCNT_56 = 0x00000E00,
709 RXCS_RETRYCNT_60 = 0x00000F00,
711 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
712 RXCS_FIFOTHNP_128QW |
714 RXCS_RETRYGAP_256ns |
717 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
720 * RX MAC Control/Status Bits
722 enum jme_rxmcs_bits {
723 RXMCS_ALLFRAME = 0x00000800,
724 RXMCS_BRDFRAME = 0x00000400,
725 RXMCS_MULFRAME = 0x00000200,
726 RXMCS_UNIFRAME = 0x00000100,
727 RXMCS_ALLMULFRAME = 0x00000080,
728 RXMCS_MULFILTERED = 0x00000040,
729 RXMCS_RXCOLLDEC = 0x00000020,
730 RXMCS_FLOWCTRL = 0x00000008,
731 RXMCS_VTAGRM = 0x00000004,
732 RXMCS_PREPAD = 0x00000002,
733 RXMCS_CHECKSUM = 0x00000001,
735 RXMCS_DEFAULT = RXMCS_VTAGRM |
742 * Wakeup Frame setup interface registers
744 #define WAKEUP_FRAME_NR 8
745 #define WAKEUP_FRAME_MASK_DWNR 4
746 enum jme_wfoi_bit_masks {
747 WFOI_MASK_SEL = 0x00000070,
748 WFOI_CRC_SEL = 0x00000008,
749 WFOI_FRAME_SEL = 0x00000007,
751 enum jme_wfoi_shifts {
756 * SMI Related definitions
758 enum jme_smi_bit_mask
760 SMI_DATA_MASK = 0xFFFF0000,
761 SMI_REG_ADDR_MASK = 0x0000F800,
762 SMI_PHY_ADDR_MASK = 0x000007C0,
763 SMI_OP_WRITE = 0x00000020,
764 /* Set to 1, after req done it'll be cleared to 0 */
765 SMI_OP_REQ = 0x00000010,
766 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
767 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
768 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
769 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
771 enum jme_smi_bit_shift
774 SMI_REG_ADDR_SHIFT = 11,
775 SMI_PHY_ADDR_SHIFT = 6,
777 __always_inline __u32 smi_reg_addr(int x)
779 return (((x) << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK);
781 __always_inline __u32 smi_phy_addr(int x)
783 return (((x) << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK);
785 #define JME_PHY_TIMEOUT 100 /* 100 msec */
786 #define JME_PHY_REG_NR 32
789 * Global Host Control
791 enum jme_ghc_bit_mask {
792 GHC_SWRST = 0x40000000,
793 GHC_DPX = 0x00000040,
794 GHC_SPEED = 0x00000030,
795 GHC_LINK_POLL = 0x00000001,
797 enum jme_ghc_speed_val {
798 GHC_SPEED_10M = 0x00000010,
799 GHC_SPEED_100M = 0x00000020,
800 GHC_SPEED_1000M = 0x00000030,
804 * Power management control and status register
806 enum jme_pmcs_bit_masks {
807 PMCS_WF7DET = 0x80000000,
808 PMCS_WF6DET = 0x40000000,
809 PMCS_WF5DET = 0x20000000,
810 PMCS_WF4DET = 0x10000000,
811 PMCS_WF3DET = 0x08000000,
812 PMCS_WF2DET = 0x04000000,
813 PMCS_WF1DET = 0x02000000,
814 PMCS_WF0DET = 0x01000000,
815 PMCS_LFDET = 0x00040000,
816 PMCS_LRDET = 0x00020000,
817 PMCS_MFDET = 0x00010000,
818 PMCS_WF7EN = 0x00008000,
819 PMCS_WF6EN = 0x00004000,
820 PMCS_WF5EN = 0x00002000,
821 PMCS_WF4EN = 0x00001000,
822 PMCS_WF3EN = 0x00000800,
823 PMCS_WF2EN = 0x00000400,
824 PMCS_WF1EN = 0x00000200,
825 PMCS_WF0EN = 0x00000100,
826 PMCS_LFEN = 0x00000004,
827 PMCS_LREN = 0x00000002,
828 PMCS_MFEN = 0x00000001,
832 * Giga PHY Status Registers
834 enum jme_phy_link_bit_mask {
835 PHY_LINK_SPEED_MASK = 0x0000C000,
836 PHY_LINK_DUPLEX = 0x00002000,
837 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
838 PHY_LINK_UP = 0x00000400,
839 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
840 PHY_LINK_MDI_STAT = 0x00000040,
842 enum jme_phy_link_speed_val {
843 PHY_LINK_SPEED_10M = 0x00000000,
844 PHY_LINK_SPEED_100M = 0x00004000,
845 PHY_LINK_SPEED_1000M = 0x00008000,
847 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
850 * SMB Control and Status
852 enum jme_smbcsr_bit_mask {
853 SMBCSR_CNACK = 0x00020000,
854 SMBCSR_RELOAD = 0x00010000,
855 SMBCSR_EEPROMD = 0x00000020,
856 SMBCSR_INITDONE = 0x00000010,
857 SMBCSR_BUSY = 0x0000000F,
859 enum jme_smbintf_bit_mask {
860 SMBINTF_HWDATR = 0xFF000000,
861 SMBINTF_HWDATW = 0x00FF0000,
862 SMBINTF_HWADDR = 0x0000FF00,
863 SMBINTF_HWRWN = 0x00000020,
864 SMBINTF_HWCMD = 0x00000010,
865 SMBINTF_FASTM = 0x00000008,
866 SMBINTF_GPIOSCL = 0x00000004,
867 SMBINTF_GPIOSDA = 0x00000002,
868 SMBINTF_GPIOEN = 0x00000001,
870 enum jme_smbintf_vals {
871 SMBINTF_HWRWN_READ = 0x00000020,
872 SMBINTF_HWRWN_WRITE = 0x00000000,
874 enum jme_smbintf_shifts {
875 SMBINTF_HWDATR_SHIFT = 24,
876 SMBINTF_HWDATW_SHIFT = 16,
877 SMBINTF_HWADDR_SHIFT = 8,
879 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
880 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
881 #define JME_SMB_LEN 256
882 #define JME_EEPROM_MAGIC 0x250
885 * Timer Control/Status Register
887 enum jme_tmcsr_bit_masks {
888 TMCSR_SWIT = 0x80000000,
889 TMCSR_EN = 0x01000000,
890 TMCSR_CNT = 0x00FFFFFF,
895 * General Purpost REG-0
897 enum jme_gpreg0_masks {
898 GPREG0_DISSH = 0xFF000000,
899 GPREG0_PCIRLMT = 0x00300000,
900 GPREG0_PCCNOMUTCLR = 0x00040000,
901 GPREG0_LNKINTPOLL = 0x00001000,
902 GPREG0_PCCTMR = 0x00000300,
903 GPREG0_PHYADDR = 0x0000001F,
905 enum jme_gpreg0_vals {
906 GPREG0_DISSH_DW7 = 0x80000000,
907 GPREG0_DISSH_DW6 = 0x40000000,
908 GPREG0_DISSH_DW5 = 0x20000000,
909 GPREG0_DISSH_DW4 = 0x10000000,
910 GPREG0_DISSH_DW3 = 0x08000000,
911 GPREG0_DISSH_DW2 = 0x04000000,
912 GPREG0_DISSH_DW1 = 0x02000000,
913 GPREG0_DISSH_DW0 = 0x01000000,
914 GPREG0_DISSH_ALL = 0xFF000000,
916 GPREG0_PCIRLMT_8 = 0x00000000,
917 GPREG0_PCIRLMT_6 = 0x00100000,
918 GPREG0_PCIRLMT_5 = 0x00200000,
919 GPREG0_PCIRLMT_4 = 0x00300000,
921 GPREG0_PCCTMR_16ns = 0x00000000,
922 GPREG0_PCCTMR_256ns = 0x00000100,
923 GPREG0_PCCTMR_1us = 0x00000200,
924 GPREG0_PCCTMR_1ms = 0x00000300,
926 GPREG0_PHYADDR_1 = 0x00000001,
928 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
935 * Interrupt Status Bits
937 enum jme_interrupt_bits {
938 INTR_SWINTR = 0x80000000,
939 INTR_TMINTR = 0x40000000,
940 INTR_LINKCH = 0x20000000,
941 INTR_PAUSERCV = 0x10000000,
942 INTR_MAGICRCV = 0x08000000,
943 INTR_WAKERCV = 0x04000000,
944 INTR_PCCRX0TO = 0x02000000,
945 INTR_PCCRX1TO = 0x01000000,
946 INTR_PCCRX2TO = 0x00800000,
947 INTR_PCCRX3TO = 0x00400000,
948 INTR_PCCTXTO = 0x00200000,
949 INTR_PCCRX0 = 0x00100000,
950 INTR_PCCRX1 = 0x00080000,
951 INTR_PCCRX2 = 0x00040000,
952 INTR_PCCRX3 = 0x00020000,
953 INTR_PCCTX = 0x00010000,
954 INTR_RX3EMP = 0x00008000,
955 INTR_RX2EMP = 0x00004000,
956 INTR_RX1EMP = 0x00002000,
957 INTR_RX0EMP = 0x00001000,
958 INTR_RX3 = 0x00000800,
959 INTR_RX2 = 0x00000400,
960 INTR_RX1 = 0x00000200,
961 INTR_RX0 = 0x00000100,
962 INTR_TX7 = 0x00000080,
963 INTR_TX6 = 0x00000040,
964 INTR_TX5 = 0x00000020,
965 INTR_TX4 = 0x00000010,
966 INTR_TX3 = 0x00000008,
967 INTR_TX2 = 0x00000004,
968 INTR_TX1 = 0x00000002,
969 INTR_TX0 = 0x00000001,
971 enum jme_interrupt_enables {
972 INTR_ENABLE = INTR_SWINTR |
981 INTR_EN_TX = INTR_PCCTXTO |
984 INTR_EN_RX0 = INTR_PCCRX0TO |
988 INTR_EN_MISC = INTR_ENABLE & ~(INTR_EN_TX | INTR_EN_RX0),
992 * PCC Control Registers
994 enum jme_pccrx_masks {
995 PCCRXTO_MASK = 0xFFFF0000,
996 PCCRX_MASK = 0x0000FF00,
998 enum jme_pcctx_masks {
999 PCCTXTO_MASK = 0xFFFF0000,
1000 PCCTX_MASK = 0x0000FF00,
1001 PCCTX_QS_MASK = 0x000000FF,
1003 enum jme_pccrx_shifts {
1007 enum jme_pcctx_shifts {
1011 enum jme_pcctx_bits {
1012 PCCTXQ0_EN = 0x00000001,
1013 PCCTXQ1_EN = 0x00000002,
1014 PCCTXQ2_EN = 0x00000004,
1015 PCCTXQ3_EN = 0x00000008,
1016 PCCTXQ4_EN = 0x00000010,
1017 PCCTXQ5_EN = 0x00000020,
1018 PCCTXQ6_EN = 0x00000040,
1019 PCCTXQ7_EN = 0x00000080,
1023 * Chip Mode Register
1025 enum jme_chipmode_bit_masks {
1026 CM_FPGAVER_MASK = 0xFFFF0000,
1027 CM_CHIPVER_MASK = 0x0000FF00,
1028 CM_CHIPMODE_MASK = 0x0000000F,
1030 enum jme_chipmode_shifts {
1031 CM_FPGAVER_SHIFT = 16,
1032 CM_CHIPVER_SHIFT = 8,
1036 * Shadow base address register bits
1038 enum jme_shadow_base_address_bits {
1043 * Read/Write MMaped I/O Registers
1045 __always_inline __u32 jread32(struct jme_adapter *jme, __u32 reg)
1047 return le32_to_cpu(readl((__u8*)jme->regs + reg));
1049 __always_inline void jwrite32(struct jme_adapter *jme, __u32 reg, __u32 val)
1051 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1053 __always_inline void jwrite32f(struct jme_adapter *jme, __u32 reg, __u32 val)
1056 * Read after write should cause flush
1058 writel(cpu_to_le32(val), (__u8*)jme->regs + reg);
1059 readl((__u8*)jme->regs + reg);
1065 enum jme_phy_reg17_bit_masks {
1066 PREG17_SPEED = 0xC000,
1067 PREG17_DUPLEX = 0x2000,
1068 PREG17_SPDRSV = 0x0800,
1069 PREG17_LNKUP = 0x0400,
1070 PREG17_MDI = 0x0040,
1072 enum jme_phy_reg17_vals {
1073 PREG17_SPEED_10M = 0x0000,
1074 PREG17_SPEED_100M = 0x4000,
1075 PREG17_SPEED_1000M = 0x8000,
1077 #define BMSR_ANCOMP 0x0020
1080 * Function prototypes for ethtool
1082 static void jme_get_drvinfo(struct net_device *netdev,
1083 struct ethtool_drvinfo *info);
1084 static int jme_get_settings(struct net_device *netdev,
1085 struct ethtool_cmd *ecmd);
1086 static int jme_set_settings(struct net_device *netdev,
1087 struct ethtool_cmd *ecmd);
1088 static u32 jme_get_link(struct net_device *netdev);
1092 * Function prototypes for netdev
1094 static int jme_open(struct net_device *netdev);
1095 static int jme_close(struct net_device *netdev);
1096 static int jme_start_xmit(struct sk_buff *skb, struct net_device *netdev);
1097 static int jme_set_macaddr(struct net_device *netdev, void *p);
1098 static void jme_set_multi(struct net_device *netdev);