2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
63 jme_mdio_read(struct net_device *netdev, int phy, int reg)
65 struct jme_adapter *jme = netdev_priv(netdev);
66 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
69 jwrite32(jme, JME_SMI, SMI_OP_REQ |
74 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
76 val = jread32(jme, JME_SMI);
77 if ((val & SMI_OP_REQ) == 0)
82 pr_err("phy(%d) read timeout : %d\n", phy, reg);
89 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
93 jme_mdio_write(struct net_device *netdev,
94 int phy, int reg, int val)
96 struct jme_adapter *jme = netdev_priv(netdev);
99 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
100 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
101 smi_phy_addr(phy) | smi_reg_addr(reg));
104 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
106 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
111 pr_err("phy(%d) write timeout : %d\n", phy, reg);
115 jme_phyext_read(struct jme_adapter *jme, int reg)
117 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
118 JME_PHY_SPEC_ADDR_REG,
119 JME_PHY_SPEC_REG_READ | (reg & 0x3FFF));
120 return jme_mdio_read(jme->dev, jme->mii_if.phy_id,
121 JME_PHY_SPEC_DATA_REG);
125 jme_phyext_write(struct jme_adapter *jme, int reg, int val)
127 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
128 JME_PHY_SPEC_DATA_REG, val);
129 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
130 JME_PHY_SPEC_ADDR_REG,
131 JME_PHY_SPEC_REG_WRITE | (reg & 0x3FFF));
135 jme_phyext_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
140 for (i = 0 ; i < reg_nr ; ++i)
141 p16[i] = jme_phyext_read(jme, i);
145 jme_reset_phy_processor(struct jme_adapter *jme)
149 jme_mdio_write(jme->dev,
151 MII_ADVERTISE, ADVERTISE_ALL |
152 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
154 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
155 jme_mdio_write(jme->dev,
158 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
160 val = jme_mdio_read(jme->dev,
164 jme_mdio_write(jme->dev,
166 MII_BMCR, val | BMCR_RESET);
170 jme_setup_wakeup_frame(struct jme_adapter *jme,
171 const u32 *mask, u32 crc, int fnr)
178 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
180 jwrite32(jme, JME_WFODP, crc);
186 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
187 jwrite32(jme, JME_WFOI,
188 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
189 (fnr & WFOI_FRAME_SEL));
191 jwrite32(jme, JME_WFODP, mask[i]);
197 jme_mac_rxclk_off(struct jme_adapter *jme)
199 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
200 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
204 jme_mac_rxclk_on(struct jme_adapter *jme)
206 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
207 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
211 jme_mac_txclk_off(struct jme_adapter *jme)
213 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
214 jwrite32f(jme, JME_GHC, jme->reg_ghc);
218 jme_mac_txclk_on(struct jme_adapter *jme)
220 u32 speed = jme->reg_ghc & GHC_SPEED;
221 if (speed == GHC_SPEED_1000M)
222 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
224 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
225 jwrite32f(jme, JME_GHC, jme->reg_ghc);
229 jme_reset_ghc_speed(struct jme_adapter *jme)
231 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
236 jme_reset_250A2_workaround(struct jme_adapter *jme)
238 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
240 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
244 jme_assert_ghc_reset(struct jme_adapter *jme)
246 jme->reg_ghc |= GHC_SWRST;
247 jwrite32f(jme, JME_GHC, jme->reg_ghc);
251 jme_clear_ghc_reset(struct jme_adapter *jme)
253 jme->reg_ghc &= ~GHC_SWRST;
254 jwrite32f(jme, JME_GHC, jme->reg_ghc);
258 jme_reset_mac_processor(struct jme_adapter *jme)
260 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
261 u32 crc = 0xCDCDCDCD;
265 jme_reset_ghc_speed(jme);
266 jme_reset_250A2_workaround(jme);
268 jme_mac_rxclk_on(jme);
269 jme_mac_txclk_on(jme);
271 jme_assert_ghc_reset(jme);
273 jme_mac_rxclk_off(jme);
274 jme_mac_txclk_off(jme);
276 jme_clear_ghc_reset(jme);
278 jme_mac_rxclk_on(jme);
279 jme_mac_txclk_on(jme);
281 jme_mac_rxclk_off(jme);
282 jme_mac_txclk_off(jme);
284 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
285 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
286 jwrite32(jme, JME_RXQDC, 0x00000000);
287 jwrite32(jme, JME_RXNDA, 0x00000000);
288 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
289 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
290 jwrite32(jme, JME_TXQDC, 0x00000000);
291 jwrite32(jme, JME_TXNDA, 0x00000000);
293 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
294 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
295 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
296 jme_setup_wakeup_frame(jme, mask, crc, i);
298 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
300 gpreg0 = GPREG0_DEFAULT;
301 jwrite32(jme, JME_GPREG0, gpreg0);
305 jme_clear_pm(struct jme_adapter *jme)
307 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
308 pci_set_power_state(jme->pdev, PCI_D0);
309 pci_enable_wake(jme->pdev, PCI_D0, false);
313 jme_reload_eeprom(struct jme_adapter *jme)
318 val = jread32(jme, JME_SMBCSR);
320 if (val & SMBCSR_EEPROMD) {
322 jwrite32(jme, JME_SMBCSR, val);
323 val |= SMBCSR_RELOAD;
324 jwrite32(jme, JME_SMBCSR, val);
327 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
329 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
334 pr_err("eeprom reload timeout\n");
343 jme_load_macaddr(struct net_device *netdev)
345 struct jme_adapter *jme = netdev_priv(netdev);
346 unsigned char macaddr[6];
349 spin_lock_bh(&jme->macaddr_lock);
350 val = jread32(jme, JME_RXUMA_LO);
351 macaddr[0] = (val >> 0) & 0xFF;
352 macaddr[1] = (val >> 8) & 0xFF;
353 macaddr[2] = (val >> 16) & 0xFF;
354 macaddr[3] = (val >> 24) & 0xFF;
355 val = jread32(jme, JME_RXUMA_HI);
356 macaddr[4] = (val >> 0) & 0xFF;
357 macaddr[5] = (val >> 8) & 0xFF;
358 memcpy(netdev->dev_addr, macaddr, 6);
359 spin_unlock_bh(&jme->macaddr_lock);
363 jme_set_rx_pcc(struct jme_adapter *jme, int p)
367 jwrite32(jme, JME_PCCRX0,
368 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
369 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
372 jwrite32(jme, JME_PCCRX0,
373 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
374 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
377 jwrite32(jme, JME_PCCRX0,
378 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
379 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
382 jwrite32(jme, JME_PCCRX0,
383 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
384 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
391 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
392 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
396 jme_start_irq(struct jme_adapter *jme)
398 register struct dynpcc_info *dpi = &(jme->dpi);
400 jme_set_rx_pcc(jme, PCC_P1);
402 dpi->attempt = PCC_P1;
405 jwrite32(jme, JME_PCCTX,
406 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
407 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
414 jwrite32(jme, JME_IENS, INTR_ENABLE);
418 jme_stop_irq(struct jme_adapter *jme)
423 jwrite32f(jme, JME_IENC, INTR_ENABLE);
427 jme_linkstat_from_phy(struct jme_adapter *jme)
431 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
432 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
433 if (bmsr & BMSR_ANCOMP)
434 phylink |= PHY_LINK_AUTONEG_COMPLETE;
440 jme_set_phyfifo_5level(struct jme_adapter *jme)
442 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
446 jme_set_phyfifo_8level(struct jme_adapter *jme)
448 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
452 jme_check_link(struct net_device *netdev, int testonly)
454 struct jme_adapter *jme = netdev_priv(netdev);
455 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
462 phylink = jme_linkstat_from_phy(jme);
464 phylink = jread32(jme, JME_PHY_LINK);
466 if (phylink & PHY_LINK_UP) {
467 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
469 * If we did not enable AN
470 * Speed/Duplex Info should be obtained from SMI
472 phylink = PHY_LINK_UP;
474 bmcr = jme_mdio_read(jme->dev,
478 phylink |= ((bmcr & BMCR_SPEED1000) &&
479 (bmcr & BMCR_SPEED100) == 0) ?
480 PHY_LINK_SPEED_1000M :
481 (bmcr & BMCR_SPEED100) ?
482 PHY_LINK_SPEED_100M :
485 phylink |= (bmcr & BMCR_FULLDPLX) ?
488 strcat(linkmsg, "Forced: ");
491 * Keep polling for speed/duplex resolve complete
493 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
499 phylink = jme_linkstat_from_phy(jme);
501 phylink = jread32(jme, JME_PHY_LINK);
504 pr_err("Waiting speed resolve timeout\n");
506 strcat(linkmsg, "ANed: ");
509 if (jme->phylink == phylink) {
516 jme->phylink = phylink;
519 * The speed/duplex setting of jme->reg_ghc already cleared
520 * by jme_reset_mac_processor()
522 switch (phylink & PHY_LINK_SPEED_MASK) {
523 case PHY_LINK_SPEED_10M:
524 jme->reg_ghc |= GHC_SPEED_10M;
525 strcat(linkmsg, "10 Mbps, ");
527 case PHY_LINK_SPEED_100M:
528 jme->reg_ghc |= GHC_SPEED_100M;
529 strcat(linkmsg, "100 Mbps, ");
531 case PHY_LINK_SPEED_1000M:
532 jme->reg_ghc |= GHC_SPEED_1000M;
533 strcat(linkmsg, "1000 Mbps, ");
539 if (phylink & PHY_LINK_DUPLEX) {
540 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
541 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
542 jme->reg_ghc |= GHC_DPX;
544 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
548 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
551 jwrite32(jme, JME_GHC, jme->reg_ghc);
553 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
554 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
556 if (!(phylink & PHY_LINK_DUPLEX))
557 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
558 switch (phylink & PHY_LINK_SPEED_MASK) {
559 case PHY_LINK_SPEED_10M:
560 jme_set_phyfifo_8level(jme);
561 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
563 case PHY_LINK_SPEED_100M:
564 jme_set_phyfifo_5level(jme);
565 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
567 case PHY_LINK_SPEED_1000M:
568 jme_set_phyfifo_8level(jme);
574 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
576 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
579 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
582 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
583 netif_carrier_on(netdev);
588 netif_info(jme, link, jme->dev, "Link is down\n");
590 netif_carrier_off(netdev);
598 jme_setup_tx_resources(struct jme_adapter *jme)
600 struct jme_ring *txring = &(jme->txring[0]);
602 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
603 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
613 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
615 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
616 txring->next_to_use = 0;
617 atomic_set(&txring->next_to_clean, 0);
618 atomic_set(&txring->nr_free, jme->tx_ring_size);
620 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
621 jme->tx_ring_size, GFP_ATOMIC);
622 if (unlikely(!(txring->bufinf)))
623 goto err_free_txring;
626 * Initialize Transmit Descriptors
628 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
629 memset(txring->bufinf, 0,
630 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
635 dma_free_coherent(&(jme->pdev->dev),
636 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
642 txring->dmaalloc = 0;
644 txring->bufinf = NULL;
650 jme_free_tx_resources(struct jme_adapter *jme)
653 struct jme_ring *txring = &(jme->txring[0]);
654 struct jme_buffer_info *txbi;
657 if (txring->bufinf) {
658 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
659 txbi = txring->bufinf + i;
661 dev_kfree_skb(txbi->skb);
667 txbi->start_xmit = 0;
669 kfree(txring->bufinf);
672 dma_free_coherent(&(jme->pdev->dev),
673 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
677 txring->alloc = NULL;
679 txring->dmaalloc = 0;
681 txring->bufinf = NULL;
683 txring->next_to_use = 0;
684 atomic_set(&txring->next_to_clean, 0);
685 atomic_set(&txring->nr_free, 0);
689 jme_enable_tx_engine(struct jme_adapter *jme)
694 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
698 * Setup TX Queue 0 DMA Bass Address
700 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
701 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
702 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
705 * Setup TX Descptor Count
707 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
713 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
718 * Start clock for TX MAC Processor
720 jme_mac_txclk_on(jme);
724 jme_restart_tx_engine(struct jme_adapter *jme)
729 jwrite32(jme, JME_TXCS, jme->reg_txcs |
735 jme_disable_tx_engine(struct jme_adapter *jme)
743 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
746 val = jread32(jme, JME_TXCS);
747 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
749 val = jread32(jme, JME_TXCS);
754 pr_err("Disable TX engine timeout\n");
757 * Stop clock for TX MAC Processor
759 jme_mac_txclk_off(jme);
763 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
765 struct jme_ring *rxring = &(jme->rxring[0]);
766 register struct rxdesc *rxdesc = rxring->desc;
767 struct jme_buffer_info *rxbi = rxring->bufinf;
773 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
774 rxdesc->desc1.bufaddrl = cpu_to_le32(
775 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
776 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
777 if (jme->dev->features & NETIF_F_HIGHDMA)
778 rxdesc->desc1.flags = RXFLAG_64BIT;
780 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
784 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
786 struct jme_ring *rxring = &(jme->rxring[0]);
787 struct jme_buffer_info *rxbi = rxring->bufinf + i;
790 skb = netdev_alloc_skb(jme->dev,
791 jme->dev->mtu + RX_EXTRA_LEN);
794 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
799 rxbi->len = skb_tailroom(skb);
800 rxbi->mapping = pci_map_page(jme->pdev,
801 virt_to_page(skb->data),
802 offset_in_page(skb->data),
810 jme_free_rx_buf(struct jme_adapter *jme, int i)
812 struct jme_ring *rxring = &(jme->rxring[0]);
813 struct jme_buffer_info *rxbi = rxring->bufinf;
817 pci_unmap_page(jme->pdev,
821 dev_kfree_skb(rxbi->skb);
829 jme_free_rx_resources(struct jme_adapter *jme)
832 struct jme_ring *rxring = &(jme->rxring[0]);
835 if (rxring->bufinf) {
836 for (i = 0 ; i < jme->rx_ring_size ; ++i)
837 jme_free_rx_buf(jme, i);
838 kfree(rxring->bufinf);
841 dma_free_coherent(&(jme->pdev->dev),
842 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
845 rxring->alloc = NULL;
847 rxring->dmaalloc = 0;
849 rxring->bufinf = NULL;
851 rxring->next_to_use = 0;
852 atomic_set(&rxring->next_to_clean, 0);
856 jme_setup_rx_resources(struct jme_adapter *jme)
859 struct jme_ring *rxring = &(jme->rxring[0]);
861 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
862 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
873 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
874 rxring->next_to_use = 0;
875 atomic_set(&rxring->next_to_clean, 0);
877 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
878 jme->rx_ring_size, GFP_ATOMIC);
879 if (unlikely(!(rxring->bufinf)))
880 goto err_free_rxring;
883 * Initiallize Receive Descriptors
885 memset(rxring->bufinf, 0,
886 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
887 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
888 if (unlikely(jme_make_new_rx_buf(jme, i))) {
889 jme_free_rx_resources(jme);
893 jme_set_clean_rxdesc(jme, i);
899 dma_free_coherent(&(jme->pdev->dev),
900 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
905 rxring->dmaalloc = 0;
907 rxring->bufinf = NULL;
913 jme_enable_rx_engine(struct jme_adapter *jme)
918 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
923 * Setup RX DMA Bass Address
925 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
926 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
927 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
930 * Setup RX Descriptor Count
932 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
935 * Setup Unicast Filter
937 jme_set_unicastaddr(jme->dev);
938 jme_set_multi(jme->dev);
944 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
950 * Start clock for RX MAC Processor
952 jme_mac_rxclk_on(jme);
956 jme_restart_rx_engine(struct jme_adapter *jme)
961 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
968 jme_disable_rx_engine(struct jme_adapter *jme)
976 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
979 val = jread32(jme, JME_RXCS);
980 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
982 val = jread32(jme, JME_RXCS);
987 pr_err("Disable RX engine timeout\n");
990 * Stop clock for RX MAC Processor
992 jme_mac_rxclk_off(jme);
996 jme_udpsum(struct sk_buff *skb)
1000 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
1002 if (skb->protocol != htons(ETH_P_IP))
1004 skb_set_network_header(skb, ETH_HLEN);
1005 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
1006 (skb->len < (ETH_HLEN +
1007 (ip_hdr(skb)->ihl << 2) +
1008 sizeof(struct udphdr)))) {
1009 skb_reset_network_header(skb);
1012 skb_set_transport_header(skb,
1013 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
1014 csum = udp_hdr(skb)->check;
1015 skb_reset_transport_header(skb);
1016 skb_reset_network_header(skb);
1022 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1024 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1027 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1028 == RXWBFLAG_TCPON)) {
1029 if (flags & RXWBFLAG_IPV4)
1030 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1034 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1035 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1036 if (flags & RXWBFLAG_IPV4)
1037 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1041 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1042 == RXWBFLAG_IPV4)) {
1043 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1051 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1053 struct jme_ring *rxring = &(jme->rxring[0]);
1054 struct rxdesc *rxdesc = rxring->desc;
1055 struct jme_buffer_info *rxbi = rxring->bufinf;
1056 struct sk_buff *skb;
1063 pci_dma_sync_single_for_cpu(jme->pdev,
1066 PCI_DMA_FROMDEVICE);
1068 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1069 pci_dma_sync_single_for_device(jme->pdev,
1072 PCI_DMA_FROMDEVICE);
1074 ++(NET_STAT(jme).rx_dropped);
1076 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1079 skb_reserve(skb, RX_PREPAD_SIZE);
1080 skb_put(skb, framesize);
1081 skb->protocol = eth_type_trans(skb, jme->dev);
1083 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1084 skb->ip_summed = CHECKSUM_UNNECESSARY;
1086 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,35)
1087 skb->ip_summed = CHECKSUM_NONE;
1089 skb_checksum_none_assert(skb);
1092 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1094 jme->jme_vlan_rx(skb, jme->vlgrp,
1095 le16_to_cpu(rxdesc->descwb.vlan));
1096 NET_STAT(jme).rx_bytes += 4;
1104 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1105 cpu_to_le16(RXWBFLAG_DEST_MUL))
1106 ++(NET_STAT(jme).multicast);
1108 NET_STAT(jme).rx_bytes += framesize;
1109 ++(NET_STAT(jme).rx_packets);
1112 jme_set_clean_rxdesc(jme, idx);
1117 jme_process_receive(struct jme_adapter *jme, int limit)
1119 struct jme_ring *rxring = &(jme->rxring[0]);
1120 struct rxdesc *rxdesc = rxring->desc;
1121 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1123 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1126 if (unlikely(atomic_read(&jme->link_changing) != 1))
1129 if (unlikely(!netif_carrier_ok(jme->dev)))
1132 i = atomic_read(&rxring->next_to_clean);
1134 rxdesc = rxring->desc;
1137 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1138 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1143 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1145 if (unlikely(desccnt > 1 ||
1146 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1148 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1149 ++(NET_STAT(jme).rx_crc_errors);
1150 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1151 ++(NET_STAT(jme).rx_fifo_errors);
1153 ++(NET_STAT(jme).rx_errors);
1156 limit -= desccnt - 1;
1158 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1159 jme_set_clean_rxdesc(jme, j);
1160 j = (j + 1) & (mask);
1164 jme_alloc_and_feed_skb(jme, i);
1167 i = (i + desccnt) & (mask);
1171 atomic_set(&rxring->next_to_clean, i);
1174 atomic_inc(&jme->rx_cleaning);
1176 return limit > 0 ? limit : 0;
1181 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1183 if (likely(atmp == dpi->cur)) {
1188 if (dpi->attempt == atmp) {
1191 dpi->attempt = atmp;
1198 jme_dynamic_pcc(struct jme_adapter *jme)
1200 register struct dynpcc_info *dpi = &(jme->dpi);
1202 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1203 jme_attempt_pcc(dpi, PCC_P3);
1204 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1205 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1206 jme_attempt_pcc(dpi, PCC_P2);
1208 jme_attempt_pcc(dpi, PCC_P1);
1210 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1211 if (dpi->attempt < dpi->cur)
1212 tasklet_schedule(&jme->rxclean_task);
1213 jme_set_rx_pcc(jme, dpi->attempt);
1214 dpi->cur = dpi->attempt;
1220 jme_start_pcc_timer(struct jme_adapter *jme)
1222 struct dynpcc_info *dpi = &(jme->dpi);
1223 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1224 dpi->last_pkts = NET_STAT(jme).rx_packets;
1226 jwrite32(jme, JME_TMCSR,
1227 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1231 jme_stop_pcc_timer(struct jme_adapter *jme)
1233 jwrite32(jme, JME_TMCSR, 0);
1237 jme_shutdown_nic(struct jme_adapter *jme)
1241 phylink = jme_linkstat_from_phy(jme);
1243 if (!(phylink & PHY_LINK_UP)) {
1245 * Disable all interrupt before issue timer
1248 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1253 jme_pcc_tasklet(unsigned long arg)
1255 struct jme_adapter *jme = (struct jme_adapter *)arg;
1256 struct net_device *netdev = jme->dev;
1258 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1259 jme_shutdown_nic(jme);
1263 if (unlikely(!netif_carrier_ok(netdev) ||
1264 (atomic_read(&jme->link_changing) != 1)
1266 jme_stop_pcc_timer(jme);
1270 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1271 jme_dynamic_pcc(jme);
1273 jme_start_pcc_timer(jme);
1277 jme_polling_mode(struct jme_adapter *jme)
1279 jme_set_rx_pcc(jme, PCC_OFF);
1283 jme_interrupt_mode(struct jme_adapter *jme)
1285 jme_set_rx_pcc(jme, PCC_P1);
1289 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1292 apmc = jread32(jme, JME_APMC);
1293 return apmc & JME_APMC_PSEUDO_HP_EN;
1297 jme_start_shutdown_timer(struct jme_adapter *jme)
1301 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1302 apmc &= ~JME_APMC_EPIEN_CTRL;
1304 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1307 jwrite32f(jme, JME_APMC, apmc);
1309 jwrite32f(jme, JME_TIMER2, 0);
1310 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1311 jwrite32(jme, JME_TMCSR,
1312 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1316 jme_stop_shutdown_timer(struct jme_adapter *jme)
1320 jwrite32f(jme, JME_TMCSR, 0);
1321 jwrite32f(jme, JME_TIMER2, 0);
1322 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1324 apmc = jread32(jme, JME_APMC);
1325 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1326 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1328 jwrite32f(jme, JME_APMC, apmc);
1332 jme_link_change_tasklet(unsigned long arg)
1334 struct jme_adapter *jme = (struct jme_adapter *)arg;
1335 struct net_device *netdev = jme->dev;
1338 while (!atomic_dec_and_test(&jme->link_changing)) {
1339 atomic_inc(&jme->link_changing);
1340 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1341 while (atomic_read(&jme->link_changing) != 1)
1342 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1345 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1348 jme->old_mtu = netdev->mtu;
1349 netif_stop_queue(netdev);
1350 if (jme_pseudo_hotplug_enabled(jme))
1351 jme_stop_shutdown_timer(jme);
1353 jme_stop_pcc_timer(jme);
1354 tasklet_disable(&jme->txclean_task);
1355 tasklet_disable(&jme->rxclean_task);
1356 tasklet_disable(&jme->rxempty_task);
1358 if (netif_carrier_ok(netdev)) {
1359 jme_disable_rx_engine(jme);
1360 jme_disable_tx_engine(jme);
1361 jme_reset_mac_processor(jme);
1362 jme_free_rx_resources(jme);
1363 jme_free_tx_resources(jme);
1365 if (test_bit(JME_FLAG_POLL, &jme->flags))
1366 jme_polling_mode(jme);
1368 netif_carrier_off(netdev);
1371 jme_check_link(netdev, 0);
1372 if (netif_carrier_ok(netdev)) {
1373 rc = jme_setup_rx_resources(jme);
1375 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1376 goto out_enable_tasklet;
1379 rc = jme_setup_tx_resources(jme);
1381 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1382 goto err_out_free_rx_resources;
1385 jme_enable_rx_engine(jme);
1386 jme_enable_tx_engine(jme);
1388 netif_start_queue(netdev);
1390 if (test_bit(JME_FLAG_POLL, &jme->flags))
1391 jme_interrupt_mode(jme);
1393 jme_start_pcc_timer(jme);
1394 } else if (jme_pseudo_hotplug_enabled(jme)) {
1395 jme_start_shutdown_timer(jme);
1398 goto out_enable_tasklet;
1400 err_out_free_rx_resources:
1401 jme_free_rx_resources(jme);
1403 tasklet_enable(&jme->txclean_task);
1404 tasklet_hi_enable(&jme->rxclean_task);
1405 tasklet_hi_enable(&jme->rxempty_task);
1407 atomic_inc(&jme->link_changing);
1411 jme_rx_clean_tasklet(unsigned long arg)
1413 struct jme_adapter *jme = (struct jme_adapter *)arg;
1414 struct dynpcc_info *dpi = &(jme->dpi);
1416 jme_process_receive(jme, jme->rx_ring_size);
1422 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1424 struct jme_adapter *jme = jme_napi_priv(holder);
1428 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1430 while (atomic_read(&jme->rx_empty) > 0) {
1431 atomic_dec(&jme->rx_empty);
1432 ++(NET_STAT(jme).rx_dropped);
1433 jme_restart_rx_engine(jme);
1435 atomic_inc(&jme->rx_empty);
1438 JME_RX_COMPLETE(netdev, holder);
1439 jme_interrupt_mode(jme);
1442 JME_NAPI_WEIGHT_SET(budget, rest);
1443 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1447 jme_rx_empty_tasklet(unsigned long arg)
1449 struct jme_adapter *jme = (struct jme_adapter *)arg;
1451 if (unlikely(atomic_read(&jme->link_changing) != 1))
1454 if (unlikely(!netif_carrier_ok(jme->dev)))
1457 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1459 jme_rx_clean_tasklet(arg);
1461 while (atomic_read(&jme->rx_empty) > 0) {
1462 atomic_dec(&jme->rx_empty);
1463 ++(NET_STAT(jme).rx_dropped);
1464 jme_restart_rx_engine(jme);
1466 atomic_inc(&jme->rx_empty);
1470 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1472 struct jme_ring *txring = &(jme->txring[0]);
1475 if (unlikely(netif_queue_stopped(jme->dev) &&
1476 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1477 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1478 netif_wake_queue(jme->dev);
1484 jme_tx_clean_tasklet(unsigned long arg)
1486 struct jme_adapter *jme = (struct jme_adapter *)arg;
1487 struct jme_ring *txring = &(jme->txring[0]);
1488 struct txdesc *txdesc = txring->desc;
1489 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1490 int i, j, cnt = 0, max, err, mask;
1492 tx_dbg(jme, "Into txclean\n");
1494 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1497 if (unlikely(atomic_read(&jme->link_changing) != 1))
1500 if (unlikely(!netif_carrier_ok(jme->dev)))
1503 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1504 mask = jme->tx_ring_mask;
1506 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1510 if (likely(ctxbi->skb &&
1511 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1513 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1514 i, ctxbi->nr_desc, jiffies);
1516 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1518 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1519 ttxbi = txbi + ((i + j) & (mask));
1520 txdesc[(i + j) & (mask)].dw[0] = 0;
1522 pci_unmap_page(jme->pdev,
1531 dev_kfree_skb(ctxbi->skb);
1533 cnt += ctxbi->nr_desc;
1535 if (unlikely(err)) {
1536 ++(NET_STAT(jme).tx_carrier_errors);
1538 ++(NET_STAT(jme).tx_packets);
1539 NET_STAT(jme).tx_bytes += ctxbi->len;
1544 ctxbi->start_xmit = 0;
1550 i = (i + ctxbi->nr_desc) & mask;
1555 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1556 atomic_set(&txring->next_to_clean, i);
1557 atomic_add(cnt, &txring->nr_free);
1559 jme_wake_queue_if_stopped(jme);
1562 atomic_inc(&jme->tx_cleaning);
1566 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1571 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1573 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1575 * Link change event is critical
1576 * all other events are ignored
1578 jwrite32(jme, JME_IEVE, intrstat);
1579 tasklet_schedule(&jme->linkch_task);
1583 if (intrstat & INTR_TMINTR) {
1584 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1585 tasklet_schedule(&jme->pcc_task);
1588 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1589 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1590 tasklet_schedule(&jme->txclean_task);
1593 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1594 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1600 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1601 if (intrstat & INTR_RX0EMP)
1602 atomic_inc(&jme->rx_empty);
1604 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1605 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1606 jme_polling_mode(jme);
1607 JME_RX_SCHEDULE(jme);
1611 if (intrstat & INTR_RX0EMP) {
1612 atomic_inc(&jme->rx_empty);
1613 tasklet_hi_schedule(&jme->rxempty_task);
1614 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1615 tasklet_hi_schedule(&jme->rxclean_task);
1621 * Re-enable interrupt
1623 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1626 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1628 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1631 jme_intr(int irq, void *dev_id)
1634 struct net_device *netdev = dev_id;
1635 struct jme_adapter *jme = netdev_priv(netdev);
1638 intrstat = jread32(jme, JME_IEVE);
1641 * Check if it's really an interrupt for us
1643 if (unlikely((intrstat & INTR_ENABLE) == 0))
1647 * Check if the device still exist
1649 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1652 jme_intr_msi(jme, intrstat);
1657 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1659 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1662 jme_msi(int irq, void *dev_id)
1665 struct net_device *netdev = dev_id;
1666 struct jme_adapter *jme = netdev_priv(netdev);
1669 intrstat = jread32(jme, JME_IEVE);
1671 jme_intr_msi(jme, intrstat);
1677 jme_reset_link(struct jme_adapter *jme)
1679 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1683 jme_restart_an(struct jme_adapter *jme)
1687 spin_lock_bh(&jme->phy_lock);
1688 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1689 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1690 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1691 spin_unlock_bh(&jme->phy_lock);
1695 jme_request_irq(struct jme_adapter *jme)
1698 struct net_device *netdev = jme->dev;
1699 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1700 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1701 int irq_flags = SA_SHIRQ;
1703 irq_handler_t handler = jme_intr;
1704 int irq_flags = IRQF_SHARED;
1707 if (!pci_enable_msi(jme->pdev)) {
1708 set_bit(JME_FLAG_MSI, &jme->flags);
1713 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1717 "Unable to request %s interrupt (return: %d)\n",
1718 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1721 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1722 pci_disable_msi(jme->pdev);
1723 clear_bit(JME_FLAG_MSI, &jme->flags);
1726 netdev->irq = jme->pdev->irq;
1733 jme_free_irq(struct jme_adapter *jme)
1735 free_irq(jme->pdev->irq, jme->dev);
1736 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1737 pci_disable_msi(jme->pdev);
1738 clear_bit(JME_FLAG_MSI, &jme->flags);
1739 jme->dev->irq = jme->pdev->irq;
1744 jme_new_phy_on(struct jme_adapter *jme)
1748 reg = jread32(jme, JME_PHY_PWR);
1749 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1750 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1751 jwrite32(jme, JME_PHY_PWR, reg);
1753 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1754 reg &= ~PE1_GPREG0_PBG;
1755 reg |= PE1_GPREG0_ENBG;
1756 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1760 jme_new_phy_off(struct jme_adapter *jme)
1764 reg = jread32(jme, JME_PHY_PWR);
1765 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1766 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1767 jwrite32(jme, JME_PHY_PWR, reg);
1769 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1770 reg &= ~PE1_GPREG0_PBG;
1771 reg |= PE1_GPREG0_PDD3COLD;
1772 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1776 jme_phy_on(struct jme_adapter *jme)
1780 if (new_phy_power_ctrl(jme->chip_main_rev))
1781 jme_new_phy_on(jme);
1783 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1784 bmcr &= ~BMCR_PDOWN;
1785 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1789 jme_phy_off(struct jme_adapter *jme)
1793 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1795 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1797 if (new_phy_power_ctrl(jme->chip_main_rev))
1798 jme_new_phy_off(jme);
1802 jme_open(struct net_device *netdev)
1804 struct jme_adapter *jme = netdev_priv(netdev);
1808 JME_NAPI_ENABLE(jme);
1810 tasklet_enable(&jme->linkch_task);
1811 tasklet_enable(&jme->txclean_task);
1812 tasklet_hi_enable(&jme->rxclean_task);
1813 tasklet_hi_enable(&jme->rxempty_task);
1815 rc = jme_request_irq(jme);
1822 if (test_bit(JME_FLAG_SSET, &jme->flags))
1823 jme_set_settings(netdev, &jme->old_ecmd);
1825 jme_reset_phy_processor(jme);
1827 jme_reset_link(jme);
1832 netif_stop_queue(netdev);
1833 netif_carrier_off(netdev);
1838 jme_set_100m_half(struct jme_adapter *jme)
1843 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1844 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1845 BMCR_SPEED1000 | BMCR_FULLDPLX);
1846 tmp |= BMCR_SPEED100;
1849 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1852 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1854 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1857 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1859 jme_wait_link(struct jme_adapter *jme)
1861 u32 phylink, to = JME_WAIT_LINK_TIME;
1864 phylink = jme_linkstat_from_phy(jme);
1865 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1867 phylink = jme_linkstat_from_phy(jme);
1872 jme_powersave_phy(struct jme_adapter *jme)
1874 if (jme->reg_pmcs) {
1875 jme_set_100m_half(jme);
1877 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1880 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
1887 jme_close(struct net_device *netdev)
1889 struct jme_adapter *jme = netdev_priv(netdev);
1891 netif_stop_queue(netdev);
1892 netif_carrier_off(netdev);
1897 JME_NAPI_DISABLE(jme);
1899 tasklet_disable(&jme->linkch_task);
1900 tasklet_disable(&jme->txclean_task);
1901 tasklet_disable(&jme->rxclean_task);
1902 tasklet_disable(&jme->rxempty_task);
1904 jme_disable_rx_engine(jme);
1905 jme_disable_tx_engine(jme);
1906 jme_reset_mac_processor(jme);
1907 jme_free_rx_resources(jme);
1908 jme_free_tx_resources(jme);
1916 jme_alloc_txdesc(struct jme_adapter *jme,
1917 struct sk_buff *skb)
1919 struct jme_ring *txring = &(jme->txring[0]);
1920 int idx, nr_alloc, mask = jme->tx_ring_mask;
1922 idx = txring->next_to_use;
1923 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1925 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1928 atomic_sub(nr_alloc, &txring->nr_free);
1930 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1936 jme_fill_tx_map(struct pci_dev *pdev,
1937 struct txdesc *txdesc,
1938 struct jme_buffer_info *txbi,
1946 dmaaddr = pci_map_page(pdev,
1952 pci_dma_sync_single_for_device(pdev,
1959 txdesc->desc2.flags = TXFLAG_OWN;
1960 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1961 txdesc->desc2.datalen = cpu_to_le16(len);
1962 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1963 txdesc->desc2.bufaddrl = cpu_to_le32(
1964 (__u64)dmaaddr & 0xFFFFFFFFUL);
1966 txbi->mapping = dmaaddr;
1971 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1973 struct jme_ring *txring = &(jme->txring[0]);
1974 struct txdesc *txdesc = txring->desc, *ctxdesc;
1975 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1976 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1977 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1978 int mask = jme->tx_ring_mask;
1979 struct skb_frag_struct *frag;
1982 for (i = 0 ; i < nr_frags ; ++i) {
1983 frag = &skb_shinfo(skb)->frags[i];
1984 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1985 ctxbi = txbi + ((idx + i + 2) & (mask));
1987 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1988 frag->page_offset, frag->size, hidma);
1991 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1992 ctxdesc = txdesc + ((idx + 1) & (mask));
1993 ctxbi = txbi + ((idx + 1) & (mask));
1994 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1995 offset_in_page(skb->data), len, hidma);
2000 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
2003 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2004 skb_shinfo(skb)->tso_size
2006 skb_shinfo(skb)->gso_size
2008 && skb_header_cloned(skb) &&
2009 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
2018 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2020 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2021 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2023 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2026 *flags |= TXFLAG_LSEN;
2028 if (skb->protocol == htons(ETH_P_IP)) {
2029 struct iphdr *iph = ip_hdr(skb);
2032 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2037 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2039 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2052 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2054 #ifdef CHECKSUM_PARTIAL
2055 if (skb->ip_summed == CHECKSUM_PARTIAL)
2057 if (skb->ip_summed == CHECKSUM_HW)
2062 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2063 if (skb->protocol == htons(ETH_P_IP))
2064 ip_proto = ip_hdr(skb)->protocol;
2065 else if (skb->protocol == htons(ETH_P_IPV6))
2066 ip_proto = ipv6_hdr(skb)->nexthdr;
2070 switch (skb->protocol) {
2071 case htons(ETH_P_IP):
2072 ip_proto = ip_hdr(skb)->protocol;
2074 case htons(ETH_P_IPV6):
2075 ip_proto = ipv6_hdr(skb)->nexthdr;
2085 *flags |= TXFLAG_TCPCS;
2088 *flags |= TXFLAG_UDPCS;
2091 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2098 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2100 if (vlan_tx_tag_present(skb)) {
2101 *flags |= TXFLAG_TAGON;
2102 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2107 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2109 struct jme_ring *txring = &(jme->txring[0]);
2110 struct txdesc *txdesc;
2111 struct jme_buffer_info *txbi;
2114 txdesc = (struct txdesc *)txring->desc + idx;
2115 txbi = txring->bufinf + idx;
2121 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2123 * Set OWN bit at final.
2124 * When kernel transmit faster than NIC.
2125 * And NIC trying to send this descriptor before we tell
2126 * it to start sending this TX queue.
2127 * Other fields are already filled correctly.
2130 flags = TXFLAG_OWN | TXFLAG_INT;
2132 * Set checksum flags while not tso
2134 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2135 jme_tx_csum(jme, skb, &flags);
2136 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2137 jme_map_tx_skb(jme, skb, idx);
2138 txdesc->desc1.flags = flags;
2140 * Set tx buffer info after telling NIC to send
2141 * For better tx_clean timing
2144 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2146 txbi->len = skb->len;
2147 txbi->start_xmit = jiffies;
2148 if (!txbi->start_xmit)
2149 txbi->start_xmit = (0UL-1);
2155 jme_stop_queue_if_full(struct jme_adapter *jme)
2157 struct jme_ring *txring = &(jme->txring[0]);
2158 struct jme_buffer_info *txbi = txring->bufinf;
2159 int idx = atomic_read(&txring->next_to_clean);
2164 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2165 netif_stop_queue(jme->dev);
2166 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2168 if (atomic_read(&txring->nr_free)
2169 >= (jme->tx_wake_threshold)) {
2170 netif_wake_queue(jme->dev);
2171 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2175 if (unlikely(txbi->start_xmit &&
2176 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2178 netif_stop_queue(jme->dev);
2179 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu\n", idx, jiffies);
2184 * This function is already protected by netif_tx_lock()
2187 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2192 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2194 struct jme_adapter *jme = netdev_priv(netdev);
2197 if (unlikely(jme_expand_header(jme, skb))) {
2198 ++(NET_STAT(jme).tx_dropped);
2199 return NETDEV_TX_OK;
2202 idx = jme_alloc_txdesc(jme, skb);
2204 if (unlikely(idx < 0)) {
2205 netif_stop_queue(netdev);
2206 netif_err(jme, tx_err, jme->dev,
2207 "BUG! Tx ring full when queue awake!\n");
2209 return NETDEV_TX_BUSY;
2212 jme_fill_tx_desc(jme, skb, idx);
2214 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2215 TXCS_SELECT_QUEUE0 |
2218 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2219 netdev->trans_start = jiffies;
2222 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2223 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2224 jme_stop_queue_if_full(jme);
2226 return NETDEV_TX_OK;
2230 jme_set_unicastaddr(struct net_device *netdev)
2232 struct jme_adapter *jme = netdev_priv(netdev);
2235 val = (netdev->dev_addr[3] & 0xff) << 24 |
2236 (netdev->dev_addr[2] & 0xff) << 16 |
2237 (netdev->dev_addr[1] & 0xff) << 8 |
2238 (netdev->dev_addr[0] & 0xff);
2239 jwrite32(jme, JME_RXUMA_LO, val);
2240 val = (netdev->dev_addr[5] & 0xff) << 8 |
2241 (netdev->dev_addr[4] & 0xff);
2242 jwrite32(jme, JME_RXUMA_HI, val);
2246 jme_set_macaddr(struct net_device *netdev, void *p)
2248 struct jme_adapter *jme = netdev_priv(netdev);
2249 struct sockaddr *addr = p;
2251 if (netif_running(netdev))
2254 spin_lock_bh(&jme->macaddr_lock);
2255 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2256 jme_set_unicastaddr(netdev);
2257 spin_unlock_bh(&jme->macaddr_lock);
2263 jme_set_multi(struct net_device *netdev)
2265 struct jme_adapter *jme = netdev_priv(netdev);
2266 u32 mc_hash[2] = {};
2267 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2271 spin_lock_bh(&jme->rxmcs_lock);
2273 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2275 if (netdev->flags & IFF_PROMISC) {
2276 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2277 } else if (netdev->flags & IFF_ALLMULTI) {
2278 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2279 } else if (netdev->flags & IFF_MULTICAST) {
2280 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2281 struct dev_mc_list *mclist;
2283 struct netdev_hw_addr *ha;
2287 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2288 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2289 for (i = 0, mclist = netdev->mc_list;
2290 mclist && i < netdev->mc_count;
2291 ++i, mclist = mclist->next) {
2292 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2293 netdev_for_each_mc_addr(mclist, netdev) {
2295 netdev_for_each_mc_addr(ha, netdev) {
2297 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2298 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2300 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2302 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2305 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2306 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2310 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2312 spin_unlock_bh(&jme->rxmcs_lock);
2316 jme_change_mtu(struct net_device *netdev, int new_mtu)
2318 struct jme_adapter *jme = netdev_priv(netdev);
2320 if (new_mtu == jme->old_mtu)
2323 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2324 ((new_mtu) < IPV6_MIN_MTU))
2327 if (new_mtu > 4000) {
2328 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2329 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2330 jme_restart_rx_engine(jme);
2332 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2333 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2334 jme_restart_rx_engine(jme);
2337 if (new_mtu > 1900) {
2338 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2339 NETIF_F_TSO | NETIF_F_TSO6);
2341 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2342 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2343 if (test_bit(JME_FLAG_TSO, &jme->flags))
2344 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2347 netdev->mtu = new_mtu;
2348 jme_reset_link(jme);
2354 jme_tx_timeout(struct net_device *netdev)
2356 struct jme_adapter *jme = netdev_priv(netdev);
2359 jme_reset_phy_processor(jme);
2360 if (test_bit(JME_FLAG_SSET, &jme->flags))
2361 jme_set_settings(netdev, &jme->old_ecmd);
2364 * Force to Reset the link again
2366 jme_reset_link(jme);
2369 static inline void jme_pause_rx(struct jme_adapter *jme)
2371 atomic_dec(&jme->link_changing);
2373 jme_set_rx_pcc(jme, PCC_OFF);
2374 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2375 JME_NAPI_DISABLE(jme);
2377 tasklet_disable(&jme->rxclean_task);
2378 tasklet_disable(&jme->rxempty_task);
2382 static inline void jme_resume_rx(struct jme_adapter *jme)
2384 struct dynpcc_info *dpi = &(jme->dpi);
2386 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2387 JME_NAPI_ENABLE(jme);
2389 tasklet_hi_enable(&jme->rxclean_task);
2390 tasklet_hi_enable(&jme->rxempty_task);
2393 dpi->attempt = PCC_P1;
2395 jme_set_rx_pcc(jme, PCC_P1);
2397 atomic_inc(&jme->link_changing);
2401 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2403 struct jme_adapter *jme = netdev_priv(netdev);
2410 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2412 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2414 struct jme_adapter *jme = netdev_priv(netdev);
2418 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2419 jme->vlgrp->vlan_devices[vid] = NULL;
2421 vlan_group_set_device(jme->vlgrp, vid, NULL);
2429 jme_get_drvinfo(struct net_device *netdev,
2430 struct ethtool_drvinfo *info)
2432 struct jme_adapter *jme = netdev_priv(netdev);
2434 strcpy(info->driver, DRV_NAME);
2435 strcpy(info->version, DRV_VERSION);
2436 strcpy(info->bus_info, pci_name(jme->pdev));
2440 jme_get_regs_len(struct net_device *netdev)
2446 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2450 for (i = 0 ; i < len ; i += 4)
2451 p[i >> 2] = jread32(jme, reg + i);
2455 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2458 u16 *p16 = (u16 *)p;
2460 for (i = 0 ; i < reg_nr ; ++i)
2461 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2465 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2467 struct jme_adapter *jme = netdev_priv(netdev);
2468 u32 *p32 = (u32 *)p;
2470 memset(p, 0xFF, JME_REG_LEN);
2473 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2476 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2479 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2482 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2485 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2488 jme_phyext_memcpy(jme, p32, JME_PHY_SPEC_REG_NR);
2492 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2494 struct jme_adapter *jme = netdev_priv(netdev);
2496 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2497 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2499 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2500 ecmd->use_adaptive_rx_coalesce = false;
2501 ecmd->rx_coalesce_usecs = 0;
2502 ecmd->rx_max_coalesced_frames = 0;
2506 ecmd->use_adaptive_rx_coalesce = true;
2508 switch (jme->dpi.cur) {
2510 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2511 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2514 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2515 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2518 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2519 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2529 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2531 struct jme_adapter *jme = netdev_priv(netdev);
2532 struct dynpcc_info *dpi = &(jme->dpi);
2534 if (netif_running(netdev))
2537 if (ecmd->use_adaptive_rx_coalesce &&
2538 test_bit(JME_FLAG_POLL, &jme->flags)) {
2539 clear_bit(JME_FLAG_POLL, &jme->flags);
2540 jme->jme_rx = netif_rx;
2541 jme->jme_vlan_rx = vlan_hwaccel_rx;
2543 dpi->attempt = PCC_P1;
2545 jme_set_rx_pcc(jme, PCC_P1);
2546 jme_interrupt_mode(jme);
2547 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2548 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2549 set_bit(JME_FLAG_POLL, &jme->flags);
2550 jme->jme_rx = netif_receive_skb;
2551 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2552 jme_interrupt_mode(jme);
2559 jme_get_pauseparam(struct net_device *netdev,
2560 struct ethtool_pauseparam *ecmd)
2562 struct jme_adapter *jme = netdev_priv(netdev);
2565 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2566 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2568 spin_lock_bh(&jme->phy_lock);
2569 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2570 spin_unlock_bh(&jme->phy_lock);
2573 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2577 jme_set_pauseparam(struct net_device *netdev,
2578 struct ethtool_pauseparam *ecmd)
2580 struct jme_adapter *jme = netdev_priv(netdev);
2583 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2584 (ecmd->tx_pause != 0)) {
2587 jme->reg_txpfc |= TXPFC_PF_EN;
2589 jme->reg_txpfc &= ~TXPFC_PF_EN;
2591 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2594 spin_lock_bh(&jme->rxmcs_lock);
2595 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2596 (ecmd->rx_pause != 0)) {
2599 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2601 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2603 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2605 spin_unlock_bh(&jme->rxmcs_lock);
2607 spin_lock_bh(&jme->phy_lock);
2608 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2609 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2610 (ecmd->autoneg != 0)) {
2613 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2615 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2617 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2618 MII_ADVERTISE, val);
2620 spin_unlock_bh(&jme->phy_lock);
2626 jme_get_wol(struct net_device *netdev,
2627 struct ethtool_wolinfo *wol)
2629 struct jme_adapter *jme = netdev_priv(netdev);
2631 wol->supported = WAKE_MAGIC | WAKE_PHY;
2635 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2636 wol->wolopts |= WAKE_PHY;
2638 if (jme->reg_pmcs & PMCS_MFEN)
2639 wol->wolopts |= WAKE_MAGIC;
2644 jme_set_wol(struct net_device *netdev,
2645 struct ethtool_wolinfo *wol)
2647 struct jme_adapter *jme = netdev_priv(netdev);
2649 if (wol->wolopts & (WAKE_MAGICSECURE |
2658 if (wol->wolopts & WAKE_PHY)
2659 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2661 if (wol->wolopts & WAKE_MAGIC)
2662 jme->reg_pmcs |= PMCS_MFEN;
2664 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2670 jme_get_settings(struct net_device *netdev,
2671 struct ethtool_cmd *ecmd)
2673 struct jme_adapter *jme = netdev_priv(netdev);
2676 spin_lock_bh(&jme->phy_lock);
2677 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2678 spin_unlock_bh(&jme->phy_lock);
2683 jme_set_settings(struct net_device *netdev,
2684 struct ethtool_cmd *ecmd)
2686 struct jme_adapter *jme = netdev_priv(netdev);
2689 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2693 * Check If user changed duplex only while force_media.
2694 * Hardware would not generate link change interrupt.
2696 if (jme->mii_if.force_media &&
2697 ecmd->autoneg != AUTONEG_ENABLE &&
2698 (jme->mii_if.full_duplex != ecmd->duplex))
2701 spin_lock_bh(&jme->phy_lock);
2702 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2703 spin_unlock_bh(&jme->phy_lock);
2707 jme_reset_link(jme);
2708 jme->old_ecmd = *ecmd;
2709 set_bit(JME_FLAG_SSET, &jme->flags);
2716 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2719 struct jme_adapter *jme = netdev_priv(netdev);
2720 struct mii_ioctl_data *mii_data = if_mii(rq);
2721 unsigned int duplex_chg;
2723 if (cmd == SIOCSMIIREG) {
2724 u16 val = mii_data->val_in;
2725 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2726 (val & BMCR_SPEED1000))
2730 spin_lock_bh(&jme->phy_lock);
2731 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2732 spin_unlock_bh(&jme->phy_lock);
2734 if (!rc && (cmd == SIOCSMIIREG)) {
2736 jme_reset_link(jme);
2737 jme_get_settings(netdev, &jme->old_ecmd);
2738 set_bit(JME_FLAG_SSET, &jme->flags);
2745 jme_get_link(struct net_device *netdev)
2747 struct jme_adapter *jme = netdev_priv(netdev);
2748 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2752 jme_get_msglevel(struct net_device *netdev)
2754 struct jme_adapter *jme = netdev_priv(netdev);
2755 return jme->msg_enable;
2759 jme_set_msglevel(struct net_device *netdev, u32 value)
2761 struct jme_adapter *jme = netdev_priv(netdev);
2762 jme->msg_enable = value;
2766 jme_get_rx_csum(struct net_device *netdev)
2768 struct jme_adapter *jme = netdev_priv(netdev);
2769 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2773 jme_set_rx_csum(struct net_device *netdev, u32 on)
2775 struct jme_adapter *jme = netdev_priv(netdev);
2777 spin_lock_bh(&jme->rxmcs_lock);
2779 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2781 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2782 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2783 spin_unlock_bh(&jme->rxmcs_lock);
2789 jme_set_tx_csum(struct net_device *netdev, u32 on)
2791 struct jme_adapter *jme = netdev_priv(netdev);
2794 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2795 if (netdev->mtu <= 1900)
2797 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2799 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2801 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2808 jme_set_tso(struct net_device *netdev, u32 on)
2810 struct jme_adapter *jme = netdev_priv(netdev);
2813 set_bit(JME_FLAG_TSO, &jme->flags);
2814 if (netdev->mtu <= 1900)
2815 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2817 clear_bit(JME_FLAG_TSO, &jme->flags);
2818 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2825 jme_nway_reset(struct net_device *netdev)
2827 struct jme_adapter *jme = netdev_priv(netdev);
2828 jme_restart_an(jme);
2833 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2838 val = jread32(jme, JME_SMBCSR);
2839 to = JME_SMB_BUSY_TIMEOUT;
2840 while ((val & SMBCSR_BUSY) && --to) {
2842 val = jread32(jme, JME_SMBCSR);
2845 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2849 jwrite32(jme, JME_SMBINTF,
2850 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2851 SMBINTF_HWRWN_READ |
2854 val = jread32(jme, JME_SMBINTF);
2855 to = JME_SMB_BUSY_TIMEOUT;
2856 while ((val & SMBINTF_HWCMD) && --to) {
2858 val = jread32(jme, JME_SMBINTF);
2861 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2865 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2869 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2874 val = jread32(jme, JME_SMBCSR);
2875 to = JME_SMB_BUSY_TIMEOUT;
2876 while ((val & SMBCSR_BUSY) && --to) {
2878 val = jread32(jme, JME_SMBCSR);
2881 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2885 jwrite32(jme, JME_SMBINTF,
2886 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2887 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2888 SMBINTF_HWRWN_WRITE |
2891 val = jread32(jme, JME_SMBINTF);
2892 to = JME_SMB_BUSY_TIMEOUT;
2893 while ((val & SMBINTF_HWCMD) && --to) {
2895 val = jread32(jme, JME_SMBINTF);
2898 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2906 jme_get_eeprom_len(struct net_device *netdev)
2908 struct jme_adapter *jme = netdev_priv(netdev);
2910 val = jread32(jme, JME_SMBCSR);
2911 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2915 jme_get_eeprom(struct net_device *netdev,
2916 struct ethtool_eeprom *eeprom, u8 *data)
2918 struct jme_adapter *jme = netdev_priv(netdev);
2919 int i, offset = eeprom->offset, len = eeprom->len;
2922 * ethtool will check the boundary for us
2924 eeprom->magic = JME_EEPROM_MAGIC;
2925 for (i = 0 ; i < len ; ++i)
2926 data[i] = jme_smb_read(jme, i + offset);
2932 jme_set_eeprom(struct net_device *netdev,
2933 struct ethtool_eeprom *eeprom, u8 *data)
2935 struct jme_adapter *jme = netdev_priv(netdev);
2936 int i, offset = eeprom->offset, len = eeprom->len;
2938 if (eeprom->magic != JME_EEPROM_MAGIC)
2942 * ethtool will check the boundary for us
2944 for (i = 0 ; i < len ; ++i)
2945 jme_smb_write(jme, i + offset, data[i]);
2950 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2951 static struct ethtool_ops jme_ethtool_ops = {
2953 static const struct ethtool_ops jme_ethtool_ops = {
2955 .get_drvinfo = jme_get_drvinfo,
2956 .get_regs_len = jme_get_regs_len,
2957 .get_regs = jme_get_regs,
2958 .get_coalesce = jme_get_coalesce,
2959 .set_coalesce = jme_set_coalesce,
2960 .get_pauseparam = jme_get_pauseparam,
2961 .set_pauseparam = jme_set_pauseparam,
2962 .get_wol = jme_get_wol,
2963 .set_wol = jme_set_wol,
2964 .get_settings = jme_get_settings,
2965 .set_settings = jme_set_settings,
2966 .get_link = jme_get_link,
2967 .get_msglevel = jme_get_msglevel,
2968 .set_msglevel = jme_set_msglevel,
2969 .get_rx_csum = jme_get_rx_csum,
2970 .set_rx_csum = jme_set_rx_csum,
2971 .set_tx_csum = jme_set_tx_csum,
2972 .set_tso = jme_set_tso,
2973 .set_sg = ethtool_op_set_sg,
2974 .nway_reset = jme_nway_reset,
2975 .get_eeprom_len = jme_get_eeprom_len,
2976 .get_eeprom = jme_get_eeprom,
2977 .set_eeprom = jme_set_eeprom,
2981 jme_pci_dma64(struct pci_dev *pdev)
2983 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2984 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2985 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2987 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2990 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2991 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2993 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2997 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2998 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2999 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
3001 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
3004 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3005 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
3007 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
3011 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3012 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
3013 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3015 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3016 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3024 jme_phy_init(struct jme_adapter *jme)
3028 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3029 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3033 jme_check_hw_ver(struct jme_adapter *jme)
3037 chipmode = jread32(jme, JME_CHIPMODE);
3039 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3040 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3041 jme->chip_main_rev = jme->chiprev & 0xF;
3042 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3045 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3046 static const struct net_device_ops jme_netdev_ops = {
3047 .ndo_open = jme_open,
3048 .ndo_stop = jme_close,
3049 .ndo_validate_addr = eth_validate_addr,
3050 .ndo_do_ioctl = jme_ioctl,
3051 .ndo_start_xmit = jme_start_xmit,
3052 .ndo_set_mac_address = jme_set_macaddr,
3053 .ndo_set_multicast_list = jme_set_multi,
3054 .ndo_change_mtu = jme_change_mtu,
3055 .ndo_tx_timeout = jme_tx_timeout,
3056 .ndo_vlan_rx_register = jme_vlan_rx_register,
3060 static int __devinit
3061 jme_init_one(struct pci_dev *pdev,
3062 const struct pci_device_id *ent)
3064 int rc = 0, using_dac, i;
3065 struct net_device *netdev;
3066 struct jme_adapter *jme;
3071 * set up PCI device basics
3073 rc = pci_enable_device(pdev);
3075 pr_err("Cannot enable PCI device\n");
3079 using_dac = jme_pci_dma64(pdev);
3080 if (using_dac < 0) {
3081 pr_err("Cannot set PCI DMA Mask\n");
3083 goto err_out_disable_pdev;
3086 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3087 pr_err("No PCI resource region found\n");
3089 goto err_out_disable_pdev;
3092 rc = pci_request_regions(pdev, DRV_NAME);
3094 pr_err("Cannot obtain PCI resource region\n");
3095 goto err_out_disable_pdev;
3098 pci_set_master(pdev);
3101 * alloc and init net device
3103 netdev = alloc_etherdev(sizeof(*jme));
3105 pr_err("Cannot allocate netdev structure\n");
3107 goto err_out_release_regions;
3109 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3110 netdev->netdev_ops = &jme_netdev_ops;
3112 netdev->open = jme_open;
3113 netdev->stop = jme_close;
3114 netdev->do_ioctl = jme_ioctl;
3115 netdev->hard_start_xmit = jme_start_xmit;
3116 netdev->set_mac_address = jme_set_macaddr;
3117 netdev->set_multicast_list = jme_set_multi;
3118 netdev->change_mtu = jme_change_mtu;
3119 netdev->tx_timeout = jme_tx_timeout;
3120 netdev->vlan_rx_register = jme_vlan_rx_register;
3121 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3122 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3124 NETDEV_GET_STATS(netdev, &jme_get_stats);
3126 netdev->ethtool_ops = &jme_ethtool_ops;
3127 netdev->watchdog_timeo = TX_TIMEOUT;
3128 netdev->features = NETIF_F_IP_CSUM |
3133 NETIF_F_HW_VLAN_TX |
3136 netdev->features |= NETIF_F_HIGHDMA;
3138 SET_NETDEV_DEV(netdev, &pdev->dev);
3139 pci_set_drvdata(pdev, netdev);
3144 jme = netdev_priv(netdev);
3147 jme->jme_rx = netif_rx;
3148 jme->jme_vlan_rx = vlan_hwaccel_rx;
3149 jme->old_mtu = netdev->mtu = 1500;
3151 jme->tx_ring_size = 1 << 10;
3152 jme->tx_ring_mask = jme->tx_ring_size - 1;
3153 jme->tx_wake_threshold = 1 << 9;
3154 jme->rx_ring_size = 1 << 9;
3155 jme->rx_ring_mask = jme->rx_ring_size - 1;
3156 jme->msg_enable = JME_DEF_MSG_ENABLE;
3157 jme->regs = ioremap(pci_resource_start(pdev, 0),
3158 pci_resource_len(pdev, 0));
3160 pr_err("Mapping PCI resource region error\n");
3162 goto err_out_free_netdev;
3166 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3167 jwrite32(jme, JME_APMC, apmc);
3168 } else if (force_pseudohp) {
3169 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3170 jwrite32(jme, JME_APMC, apmc);
3173 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3175 spin_lock_init(&jme->phy_lock);
3176 spin_lock_init(&jme->macaddr_lock);
3177 spin_lock_init(&jme->rxmcs_lock);
3179 atomic_set(&jme->link_changing, 1);
3180 atomic_set(&jme->rx_cleaning, 1);
3181 atomic_set(&jme->tx_cleaning, 1);
3182 atomic_set(&jme->rx_empty, 1);
3184 tasklet_init(&jme->pcc_task,
3186 (unsigned long) jme);
3187 tasklet_init(&jme->linkch_task,
3188 jme_link_change_tasklet,
3189 (unsigned long) jme);
3190 tasklet_init(&jme->txclean_task,
3191 jme_tx_clean_tasklet,
3192 (unsigned long) jme);
3193 tasklet_init(&jme->rxclean_task,
3194 jme_rx_clean_tasklet,
3195 (unsigned long) jme);
3196 tasklet_init(&jme->rxempty_task,
3197 jme_rx_empty_tasklet,
3198 (unsigned long) jme);
3199 tasklet_disable_nosync(&jme->linkch_task);
3200 tasklet_disable_nosync(&jme->txclean_task);
3201 tasklet_disable_nosync(&jme->rxclean_task);
3202 tasklet_disable_nosync(&jme->rxempty_task);
3203 jme->dpi.cur = PCC_P1;
3206 jme->reg_rxcs = RXCS_DEFAULT;
3207 jme->reg_rxmcs = RXMCS_DEFAULT;
3209 jme->reg_pmcs = PMCS_MFEN;
3210 jme->reg_gpreg1 = GPREG1_DEFAULT;
3211 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3212 set_bit(JME_FLAG_TSO, &jme->flags);
3215 * Get Max Read Req Size from PCI Config Space
3217 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3218 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3219 switch (jme->mrrs) {
3221 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3224 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3227 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3232 * Must check before reset_mac_processor
3234 jme_check_hw_ver(jme);
3235 jme->mii_if.dev = netdev;
3237 jme->mii_if.phy_id = 0;
3238 for (i = 1 ; i < 32 ; ++i) {
3239 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3240 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3241 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3242 jme->mii_if.phy_id = i;
3247 if (!jme->mii_if.phy_id) {
3249 pr_err("Can not find phy_id\n");
3253 jme->reg_ghc |= GHC_LINK_POLL;
3255 jme->mii_if.phy_id = 1;
3257 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3258 jme->mii_if.supports_gmii = true;
3260 jme->mii_if.supports_gmii = false;
3261 jme->mii_if.phy_id_mask = 0x1F;
3262 jme->mii_if.reg_num_mask = 0x1F;
3263 jme->mii_if.mdio_read = jme_mdio_read;
3264 jme->mii_if.mdio_write = jme_mdio_write;
3267 jme_set_phyfifo_5level(jme);
3268 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3274 * Reset MAC processor and reload EEPROM for MAC Address
3276 jme_reset_mac_processor(jme);
3277 rc = jme_reload_eeprom(jme);
3279 pr_err("Reload eeprom for reading MAC Address error\n");
3282 jme_load_macaddr(netdev);
3285 * Tell stack that we are not ready to work until open()
3287 netif_carrier_off(netdev);
3289 rc = register_netdev(netdev);
3291 pr_err("Cannot register net device\n");
3295 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3296 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3297 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3298 "JMC250 Gigabit Ethernet" :
3299 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3300 "JMC260 Fast Ethernet" : "Unknown",
3301 (jme->fpgaver != 0) ? " (FPGA)" : "",
3302 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3304 netdev->dev_addr[0],
3305 netdev->dev_addr[1],
3306 netdev->dev_addr[2],
3307 netdev->dev_addr[3],
3308 netdev->dev_addr[4],
3309 netdev->dev_addr[5]);
3315 err_out_free_netdev:
3316 pci_set_drvdata(pdev, NULL);
3317 free_netdev(netdev);
3318 err_out_release_regions:
3319 pci_release_regions(pdev);
3320 err_out_disable_pdev:
3321 pci_disable_device(pdev);
3326 static void __devexit
3327 jme_remove_one(struct pci_dev *pdev)
3329 struct net_device *netdev = pci_get_drvdata(pdev);
3330 struct jme_adapter *jme = netdev_priv(netdev);
3332 unregister_netdev(netdev);
3334 pci_set_drvdata(pdev, NULL);
3335 free_netdev(netdev);
3336 pci_release_regions(pdev);
3337 pci_disable_device(pdev);
3342 jme_shutdown(struct pci_dev *pdev)
3344 struct net_device *netdev = pci_get_drvdata(pdev);
3345 struct jme_adapter *jme = netdev_priv(netdev);
3347 jme_powersave_phy(jme);
3348 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3349 pci_enable_wake(pdev, PCI_D3hot, true);
3351 pci_pme_active(pdev, true);
3357 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3359 struct net_device *netdev = pci_get_drvdata(pdev);
3360 struct jme_adapter *jme = netdev_priv(netdev);
3362 atomic_dec(&jme->link_changing);
3364 netif_device_detach(netdev);
3365 netif_stop_queue(netdev);
3368 tasklet_disable(&jme->txclean_task);
3369 tasklet_disable(&jme->rxclean_task);
3370 tasklet_disable(&jme->rxempty_task);
3372 if (netif_carrier_ok(netdev)) {
3373 if (test_bit(JME_FLAG_POLL, &jme->flags))
3374 jme_polling_mode(jme);
3376 jme_stop_pcc_timer(jme);
3377 jme_disable_rx_engine(jme);
3378 jme_disable_tx_engine(jme);
3379 jme_reset_mac_processor(jme);
3380 jme_free_rx_resources(jme);
3381 jme_free_tx_resources(jme);
3382 netif_carrier_off(netdev);
3386 tasklet_enable(&jme->txclean_task);
3387 tasklet_hi_enable(&jme->rxclean_task);
3388 tasklet_hi_enable(&jme->rxempty_task);
3390 pci_save_state(pdev);
3391 jme_powersave_phy(jme);
3392 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
3393 pci_enable_wake(pdev, PCI_D3hot, true);
3395 pci_pme_active(pdev, true);
3397 pci_set_power_state(pdev, PCI_D3hot);
3403 jme_resume(struct pci_dev *pdev)
3405 struct net_device *netdev = pci_get_drvdata(pdev);
3406 struct jme_adapter *jme = netdev_priv(netdev);
3409 pci_restore_state(pdev);
3412 if (test_bit(JME_FLAG_SSET, &jme->flags))
3413 jme_set_settings(netdev, &jme->old_ecmd);
3415 jme_reset_phy_processor(jme);
3418 netif_device_attach(netdev);
3420 atomic_inc(&jme->link_changing);
3422 jme_reset_link(jme);
3428 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3429 static struct pci_device_id jme_pci_tbl[] = {
3431 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3433 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3434 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3438 static struct pci_driver jme_driver = {
3440 .id_table = jme_pci_tbl,
3441 .probe = jme_init_one,
3442 .remove = __devexit_p(jme_remove_one),
3444 .suspend = jme_suspend,
3445 .resume = jme_resume,
3446 #endif /* CONFIG_PM */
3447 .shutdown = jme_shutdown,
3451 jme_init_module(void)
3453 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3454 return pci_register_driver(&jme_driver);
3458 jme_cleanup_module(void)
3460 pci_unregister_driver(&jme_driver);
3463 module_init(jme_init_module);
3464 module_exit(jme_cleanup_module);
3466 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3467 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3468 MODULE_LICENSE("GPL");
3469 MODULE_VERSION(DRV_VERSION);
3470 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);