2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
89 struct jme_adapter *jme = netdev_priv(netdev);
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
110 jme_reset_phy_processor(struct jme_adapter *jme)
114 jme_mdio_write(jme->dev,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
125 val = jme_mdio_read(jme->dev,
129 jme_mdio_write(jme->dev,
131 MII_BMCR, val | BMCR_RESET);
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
147 jwrite32(jme, JME_WFODP, crc);
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
158 jwrite32(jme, JME_WFODP, mask[i]);
164 jme_reset_mac_processor(struct jme_adapter *jme)
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
197 jme_reset_ghc_speed(struct jme_adapter *jme)
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
204 jme_clear_pm(struct jme_adapter *jme)
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
212 jme_reload_eeprom(struct jme_adapter *jme)
217 val = jread32(jme, JME_SMBCSR);
219 if (val & SMBCSR_EEPROMD) {
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device *netdev)
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
295 jme_start_irq(struct jme_adapter *jme)
297 register struct dynpcc_info *dpi = &(jme->dpi);
299 jme_set_rx_pcc(jme, PCC_P1);
301 dpi->attempt = PCC_P1;
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
317 jme_stop_irq(struct jme_adapter *jme)
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
326 jme_linkstat_from_phy(struct jme_adapter *jme)
330 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
331 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
332 if (bmsr & BMSR_ANCOMP)
333 phylink |= PHY_LINK_AUTONEG_COMPLETE;
339 jme_set_phyfifoa(struct jme_adapter *jme)
341 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
345 jme_set_phyfifob(struct jme_adapter *jme)
347 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
351 jme_check_link(struct net_device *netdev, int testonly)
353 struct jme_adapter *jme = netdev_priv(netdev);
354 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
361 phylink = jme_linkstat_from_phy(jme);
363 phylink = jread32(jme, JME_PHY_LINK);
365 if (phylink & PHY_LINK_UP) {
366 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
371 phylink = PHY_LINK_UP;
373 bmcr = jme_mdio_read(jme->dev,
377 phylink |= ((bmcr & BMCR_SPEED1000) &&
378 (bmcr & BMCR_SPEED100) == 0) ?
379 PHY_LINK_SPEED_1000M :
380 (bmcr & BMCR_SPEED100) ?
381 PHY_LINK_SPEED_100M :
384 phylink |= (bmcr & BMCR_FULLDPLX) ?
387 strcat(linkmsg, "Forced: ");
390 * Keep polling for speed/duplex resolve complete
392 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
398 phylink = jme_linkstat_from_phy(jme);
400 phylink = jread32(jme, JME_PHY_LINK);
404 "Waiting speed resolve timeout.\n");
406 strcat(linkmsg, "ANed: ");
409 if (jme->phylink == phylink) {
416 jme->phylink = phylink;
418 ghc = jme->reg_ghc & ~(GHC_SPEED | GHC_DPX |
419 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE |
420 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY);
421 switch (phylink & PHY_LINK_SPEED_MASK) {
422 case PHY_LINK_SPEED_10M:
423 ghc |= GHC_SPEED_10M |
424 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
425 strcat(linkmsg, "10 Mbps, ");
427 case PHY_LINK_SPEED_100M:
428 ghc |= GHC_SPEED_100M |
429 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
430 strcat(linkmsg, "100 Mbps, ");
432 case PHY_LINK_SPEED_1000M:
433 ghc |= GHC_SPEED_1000M |
434 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
435 strcat(linkmsg, "1000 Mbps, ");
441 if (phylink & PHY_LINK_DUPLEX) {
442 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
445 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
449 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
450 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
452 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
455 gpreg1 = GPREG1_DEFAULT;
456 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
457 if (!(phylink & PHY_LINK_DUPLEX))
458 gpreg1 |= GPREG1_HALFMODEPATCH;
459 switch (phylink & PHY_LINK_SPEED_MASK) {
460 case PHY_LINK_SPEED_10M:
461 jme_set_phyfifoa(jme);
462 gpreg1 |= GPREG1_RSSPATCH;
464 case PHY_LINK_SPEED_100M:
465 jme_set_phyfifob(jme);
466 gpreg1 |= GPREG1_RSSPATCH;
468 case PHY_LINK_SPEED_1000M:
469 jme_set_phyfifoa(jme);
476 jwrite32(jme, JME_GPREG1, gpreg1);
477 jwrite32(jme, JME_GHC, ghc);
480 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
483 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
486 netif_info(jme, link, jme->dev, "Link is up at %s.\n", linkmsg);
487 netif_carrier_on(netdev);
492 netif_info(jme, link, jme->dev, "Link is down.\n");
494 netif_carrier_off(netdev);
502 jme_setup_tx_resources(struct jme_adapter *jme)
504 struct jme_ring *txring = &(jme->txring[0]);
506 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
507 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
517 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
519 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
520 txring->next_to_use = 0;
521 atomic_set(&txring->next_to_clean, 0);
522 atomic_set(&txring->nr_free, jme->tx_ring_size);
524 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
525 jme->tx_ring_size, GFP_ATOMIC);
526 if (unlikely(!(txring->bufinf)))
527 goto err_free_txring;
530 * Initialize Transmit Descriptors
532 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
533 memset(txring->bufinf, 0,
534 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
539 dma_free_coherent(&(jme->pdev->dev),
540 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
546 txring->dmaalloc = 0;
548 txring->bufinf = NULL;
554 jme_free_tx_resources(struct jme_adapter *jme)
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi;
561 if (txring->bufinf) {
562 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
563 txbi = txring->bufinf + i;
565 dev_kfree_skb(txbi->skb);
571 txbi->start_xmit = 0;
573 kfree(txring->bufinf);
576 dma_free_coherent(&(jme->pdev->dev),
577 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
581 txring->alloc = NULL;
583 txring->dmaalloc = 0;
585 txring->bufinf = NULL;
587 txring->next_to_use = 0;
588 atomic_set(&txring->next_to_clean, 0);
589 atomic_set(&txring->nr_free, 0);
593 jme_enable_tx_engine(struct jme_adapter *jme)
598 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
602 * Setup TX Queue 0 DMA Bass Address
604 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
605 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
606 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
609 * Setup TX Descptor Count
611 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
617 jwrite32(jme, JME_TXCS, jme->reg_txcs |
624 jme_restart_tx_engine(struct jme_adapter *jme)
629 jwrite32(jme, JME_TXCS, jme->reg_txcs |
635 jme_disable_tx_engine(struct jme_adapter *jme)
643 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
646 val = jread32(jme, JME_TXCS);
647 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
649 val = jread32(jme, JME_TXCS);
654 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
658 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
660 struct jme_ring *rxring = &(jme->rxring[0]);
661 register struct rxdesc *rxdesc = rxring->desc;
662 struct jme_buffer_info *rxbi = rxring->bufinf;
668 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
669 rxdesc->desc1.bufaddrl = cpu_to_le32(
670 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
671 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
672 if (jme->dev->features & NETIF_F_HIGHDMA)
673 rxdesc->desc1.flags = RXFLAG_64BIT;
675 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
679 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
681 struct jme_ring *rxring = &(jme->rxring[0]);
682 struct jme_buffer_info *rxbi = rxring->bufinf + i;
685 skb = netdev_alloc_skb(jme->dev,
686 jme->dev->mtu + RX_EXTRA_LEN);
691 rxbi->len = skb_tailroom(skb);
692 rxbi->mapping = pci_map_page(jme->pdev,
693 virt_to_page(skb->data),
694 offset_in_page(skb->data),
702 jme_free_rx_buf(struct jme_adapter *jme, int i)
704 struct jme_ring *rxring = &(jme->rxring[0]);
705 struct jme_buffer_info *rxbi = rxring->bufinf;
709 pci_unmap_page(jme->pdev,
713 dev_kfree_skb(rxbi->skb);
721 jme_free_rx_resources(struct jme_adapter *jme)
724 struct jme_ring *rxring = &(jme->rxring[0]);
727 if (rxring->bufinf) {
728 for (i = 0 ; i < jme->rx_ring_size ; ++i)
729 jme_free_rx_buf(jme, i);
730 kfree(rxring->bufinf);
733 dma_free_coherent(&(jme->pdev->dev),
734 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
737 rxring->alloc = NULL;
739 rxring->dmaalloc = 0;
741 rxring->bufinf = NULL;
743 rxring->next_to_use = 0;
744 atomic_set(&rxring->next_to_clean, 0);
748 jme_setup_rx_resources(struct jme_adapter *jme)
751 struct jme_ring *rxring = &(jme->rxring[0]);
753 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
754 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
763 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
765 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
766 rxring->next_to_use = 0;
767 atomic_set(&rxring->next_to_clean, 0);
769 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
770 jme->rx_ring_size, GFP_ATOMIC);
771 if (unlikely(!(rxring->bufinf)))
772 goto err_free_rxring;
775 * Initiallize Receive Descriptors
777 memset(rxring->bufinf, 0,
778 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
779 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
780 if (unlikely(jme_make_new_rx_buf(jme, i))) {
781 jme_free_rx_resources(jme);
785 jme_set_clean_rxdesc(jme, i);
791 dma_free_coherent(&(jme->pdev->dev),
792 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
797 rxring->dmaalloc = 0;
799 rxring->bufinf = NULL;
805 jme_enable_rx_engine(struct jme_adapter *jme)
810 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
815 * Setup RX DMA Bass Address
817 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
818 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
819 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
822 * Setup RX Descriptor Count
824 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
827 * Setup Unicast Filter
829 jme_set_multi(jme->dev);
835 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
842 jme_restart_rx_engine(struct jme_adapter *jme)
847 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
854 jme_disable_rx_engine(struct jme_adapter *jme)
862 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
865 val = jread32(jme, JME_RXCS);
866 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
868 val = jread32(jme, JME_RXCS);
873 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
878 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
880 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
883 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
884 == RXWBFLAG_TCPON)) {
885 if (flags & RXWBFLAG_IPV4)
886 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
890 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
891 == RXWBFLAG_UDPON)) {
892 if (flags & RXWBFLAG_IPV4)
893 netif_err(jme, rx_err, jme->dev, "UDP Checksum error.\n");
897 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
899 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error.\n");
907 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
909 struct jme_ring *rxring = &(jme->rxring[0]);
910 struct rxdesc *rxdesc = rxring->desc;
911 struct jme_buffer_info *rxbi = rxring->bufinf;
919 pci_dma_sync_single_for_cpu(jme->pdev,
924 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
925 pci_dma_sync_single_for_device(jme->pdev,
930 ++(NET_STAT(jme).rx_dropped);
932 framesize = le16_to_cpu(rxdesc->descwb.framesize)
935 skb_reserve(skb, RX_PREPAD_SIZE);
936 skb_put(skb, framesize);
937 skb->protocol = eth_type_trans(skb, jme->dev);
939 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
940 skb->ip_summed = CHECKSUM_UNNECESSARY;
942 skb->ip_summed = CHECKSUM_NONE;
944 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
945 spin_lock(&jme->vlgrp_lock);
947 jme->jme_vlan_rx(skb, jme->vlgrp,
948 le16_to_cpu(rxdesc->descwb.vlan));
949 spin_unlock(&jme->vlgrp_lock);
950 NET_STAT(jme).rx_bytes += 4;
952 spin_unlock(&jme->vlgrp_lock);
959 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
960 cpu_to_le16(RXWBFLAG_DEST_MUL))
961 ++(NET_STAT(jme).multicast);
963 NET_STAT(jme).rx_bytes += framesize;
964 ++(NET_STAT(jme).rx_packets);
967 jme_set_clean_rxdesc(jme, idx);
972 jme_process_receive(struct jme_adapter *jme, int limit)
974 struct jme_ring *rxring = &(jme->rxring[0]);
975 struct rxdesc *rxdesc = rxring->desc;
976 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
978 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
981 if (unlikely(atomic_read(&jme->link_changing) != 1))
984 if (unlikely(!netif_carrier_ok(jme->dev)))
987 i = atomic_read(&rxring->next_to_clean);
989 rxdesc = rxring->desc;
992 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
993 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
997 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
999 if (unlikely(desccnt > 1 ||
1000 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1002 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1003 ++(NET_STAT(jme).rx_crc_errors);
1004 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1005 ++(NET_STAT(jme).rx_fifo_errors);
1007 ++(NET_STAT(jme).rx_errors);
1010 limit -= desccnt - 1;
1012 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1013 jme_set_clean_rxdesc(jme, j);
1014 j = (j + 1) & (mask);
1018 jme_alloc_and_feed_skb(jme, i);
1021 i = (i + desccnt) & (mask);
1025 atomic_set(&rxring->next_to_clean, i);
1028 atomic_inc(&jme->rx_cleaning);
1030 return limit > 0 ? limit : 0;
1035 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1037 if (likely(atmp == dpi->cur)) {
1042 if (dpi->attempt == atmp) {
1045 dpi->attempt = atmp;
1052 jme_dynamic_pcc(struct jme_adapter *jme)
1054 register struct dynpcc_info *dpi = &(jme->dpi);
1056 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1057 jme_attempt_pcc(dpi, PCC_P3);
1058 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1059 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1060 jme_attempt_pcc(dpi, PCC_P2);
1062 jme_attempt_pcc(dpi, PCC_P1);
1064 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1065 if (dpi->attempt < dpi->cur)
1066 tasklet_schedule(&jme->rxclean_task);
1067 jme_set_rx_pcc(jme, dpi->attempt);
1068 dpi->cur = dpi->attempt;
1074 jme_start_pcc_timer(struct jme_adapter *jme)
1076 struct dynpcc_info *dpi = &(jme->dpi);
1077 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1078 dpi->last_pkts = NET_STAT(jme).rx_packets;
1080 jwrite32(jme, JME_TMCSR,
1081 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1085 jme_stop_pcc_timer(struct jme_adapter *jme)
1087 jwrite32(jme, JME_TMCSR, 0);
1091 jme_shutdown_nic(struct jme_adapter *jme)
1095 phylink = jme_linkstat_from_phy(jme);
1097 if (!(phylink & PHY_LINK_UP)) {
1099 * Disable all interrupt before issue timer
1102 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1107 jme_pcc_tasklet(unsigned long arg)
1109 struct jme_adapter *jme = (struct jme_adapter *)arg;
1110 struct net_device *netdev = jme->dev;
1112 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1113 jme_shutdown_nic(jme);
1117 if (unlikely(!netif_carrier_ok(netdev) ||
1118 (atomic_read(&jme->link_changing) != 1)
1120 jme_stop_pcc_timer(jme);
1124 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1125 jme_dynamic_pcc(jme);
1127 jme_start_pcc_timer(jme);
1131 jme_polling_mode(struct jme_adapter *jme)
1133 jme_set_rx_pcc(jme, PCC_OFF);
1137 jme_interrupt_mode(struct jme_adapter *jme)
1139 jme_set_rx_pcc(jme, PCC_P1);
1143 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1146 apmc = jread32(jme, JME_APMC);
1147 return apmc & JME_APMC_PSEUDO_HP_EN;
1151 jme_start_shutdown_timer(struct jme_adapter *jme)
1155 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1156 apmc &= ~JME_APMC_EPIEN_CTRL;
1158 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1161 jwrite32f(jme, JME_APMC, apmc);
1163 jwrite32f(jme, JME_TIMER2, 0);
1164 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1165 jwrite32(jme, JME_TMCSR,
1166 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1170 jme_stop_shutdown_timer(struct jme_adapter *jme)
1174 jwrite32f(jme, JME_TMCSR, 0);
1175 jwrite32f(jme, JME_TIMER2, 0);
1176 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1178 apmc = jread32(jme, JME_APMC);
1179 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1180 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1182 jwrite32f(jme, JME_APMC, apmc);
1186 jme_link_change_tasklet(unsigned long arg)
1188 struct jme_adapter *jme = (struct jme_adapter *)arg;
1189 struct net_device *netdev = jme->dev;
1192 while (!atomic_dec_and_test(&jme->link_changing)) {
1193 atomic_inc(&jme->link_changing);
1194 netif_info(jme, intr, jme->dev, "Get link change lock failed.\n");
1195 while (atomic_read(&jme->link_changing) != 1)
1196 netif_info(jme, intr, jme->dev, "Waiting link change lock.\n");
1199 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1202 jme->old_mtu = netdev->mtu;
1203 netif_stop_queue(netdev);
1204 if (jme_pseudo_hotplug_enabled(jme))
1205 jme_stop_shutdown_timer(jme);
1207 jme_stop_pcc_timer(jme);
1208 tasklet_disable(&jme->txclean_task);
1209 tasklet_disable(&jme->rxclean_task);
1210 tasklet_disable(&jme->rxempty_task);
1212 if (netif_carrier_ok(netdev)) {
1213 jme_reset_ghc_speed(jme);
1214 jme_disable_rx_engine(jme);
1215 jme_disable_tx_engine(jme);
1216 jme_reset_mac_processor(jme);
1217 jme_free_rx_resources(jme);
1218 jme_free_tx_resources(jme);
1220 if (test_bit(JME_FLAG_POLL, &jme->flags))
1221 jme_polling_mode(jme);
1223 netif_carrier_off(netdev);
1226 jme_check_link(netdev, 0);
1227 if (netif_carrier_ok(netdev)) {
1228 rc = jme_setup_rx_resources(jme);
1230 jeprintk(jme->pdev, "Allocating resources for RX error"
1231 ", Device STOPPED!\n");
1232 goto out_enable_tasklet;
1235 rc = jme_setup_tx_resources(jme);
1237 jeprintk(jme->pdev, "Allocating resources for TX error"
1238 ", Device STOPPED!\n");
1239 goto err_out_free_rx_resources;
1242 jme_enable_rx_engine(jme);
1243 jme_enable_tx_engine(jme);
1245 netif_start_queue(netdev);
1247 if (test_bit(JME_FLAG_POLL, &jme->flags))
1248 jme_interrupt_mode(jme);
1250 jme_start_pcc_timer(jme);
1251 } else if (jme_pseudo_hotplug_enabled(jme)) {
1252 jme_start_shutdown_timer(jme);
1255 goto out_enable_tasklet;
1257 err_out_free_rx_resources:
1258 jme_free_rx_resources(jme);
1260 tasklet_enable(&jme->txclean_task);
1261 tasklet_hi_enable(&jme->rxclean_task);
1262 tasklet_hi_enable(&jme->rxempty_task);
1264 atomic_inc(&jme->link_changing);
1268 jme_rx_clean_tasklet(unsigned long arg)
1270 struct jme_adapter *jme = (struct jme_adapter *)arg;
1271 struct dynpcc_info *dpi = &(jme->dpi);
1273 jme_process_receive(jme, jme->rx_ring_size);
1279 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1281 struct jme_adapter *jme = jme_napi_priv(holder);
1284 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1286 while (atomic_read(&jme->rx_empty) > 0) {
1287 atomic_dec(&jme->rx_empty);
1288 ++(NET_STAT(jme).rx_dropped);
1289 jme_restart_rx_engine(jme);
1291 atomic_inc(&jme->rx_empty);
1294 JME_RX_COMPLETE(netdev, holder);
1295 jme_interrupt_mode(jme);
1298 JME_NAPI_WEIGHT_SET(budget, rest);
1299 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1303 jme_rx_empty_tasklet(unsigned long arg)
1305 struct jme_adapter *jme = (struct jme_adapter *)arg;
1307 if (unlikely(atomic_read(&jme->link_changing) != 1))
1310 if (unlikely(!netif_carrier_ok(jme->dev)))
1313 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1315 jme_rx_clean_tasklet(arg);
1317 while (atomic_read(&jme->rx_empty) > 0) {
1318 atomic_dec(&jme->rx_empty);
1319 ++(NET_STAT(jme).rx_dropped);
1320 jme_restart_rx_engine(jme);
1322 atomic_inc(&jme->rx_empty);
1326 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1328 struct jme_ring *txring = &(jme->txring[0]);
1331 if (unlikely(netif_queue_stopped(jme->dev) &&
1332 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1333 netif_info(jme, tx_done, jme->dev, "TX Queue Waked.\n");
1334 netif_wake_queue(jme->dev);
1340 jme_tx_clean_tasklet(unsigned long arg)
1342 struct jme_adapter *jme = (struct jme_adapter *)arg;
1343 struct jme_ring *txring = &(jme->txring[0]);
1344 struct txdesc *txdesc = txring->desc;
1345 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1346 int i, j, cnt = 0, max, err, mask;
1348 tx_dbg(jme, "Into txclean.\n");
1350 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1353 if (unlikely(atomic_read(&jme->link_changing) != 1))
1356 if (unlikely(!netif_carrier_ok(jme->dev)))
1359 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1360 mask = jme->tx_ring_mask;
1362 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1366 if (likely(ctxbi->skb &&
1367 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1369 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1370 i, ctxbi->nr_desc, jiffies);
1372 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1374 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1375 ttxbi = txbi + ((i + j) & (mask));
1376 txdesc[(i + j) & (mask)].dw[0] = 0;
1378 pci_unmap_page(jme->pdev,
1387 dev_kfree_skb(ctxbi->skb);
1389 cnt += ctxbi->nr_desc;
1391 if (unlikely(err)) {
1392 ++(NET_STAT(jme).tx_carrier_errors);
1394 ++(NET_STAT(jme).tx_packets);
1395 NET_STAT(jme).tx_bytes += ctxbi->len;
1400 ctxbi->start_xmit = 0;
1406 i = (i + ctxbi->nr_desc) & mask;
1411 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1412 atomic_set(&txring->next_to_clean, i);
1413 atomic_add(cnt, &txring->nr_free);
1415 jme_wake_queue_if_stopped(jme);
1418 atomic_inc(&jme->tx_cleaning);
1422 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1427 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1429 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1431 * Link change event is critical
1432 * all other events are ignored
1434 jwrite32(jme, JME_IEVE, intrstat);
1435 tasklet_schedule(&jme->linkch_task);
1439 if (intrstat & INTR_TMINTR) {
1440 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1441 tasklet_schedule(&jme->pcc_task);
1444 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1445 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1446 tasklet_schedule(&jme->txclean_task);
1449 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1450 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1456 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1457 if (intrstat & INTR_RX0EMP)
1458 atomic_inc(&jme->rx_empty);
1460 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1461 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1462 jme_polling_mode(jme);
1463 JME_RX_SCHEDULE(jme);
1467 if (intrstat & INTR_RX0EMP) {
1468 atomic_inc(&jme->rx_empty);
1469 tasklet_hi_schedule(&jme->rxempty_task);
1470 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1471 tasklet_hi_schedule(&jme->rxclean_task);
1477 * Re-enable interrupt
1479 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1483 jme_intr(int irq, void *dev_id)
1485 struct net_device *netdev = dev_id;
1486 struct jme_adapter *jme = netdev_priv(netdev);
1489 intrstat = jread32(jme, JME_IEVE);
1492 * Check if it's really an interrupt for us
1494 if (unlikely((intrstat & INTR_ENABLE) == 0))
1498 * Check if the device still exist
1500 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1503 jme_intr_msi(jme, intrstat);
1509 jme_msi(int irq, void *dev_id)
1511 struct net_device *netdev = dev_id;
1512 struct jme_adapter *jme = netdev_priv(netdev);
1515 intrstat = jread32(jme, JME_IEVE);
1517 jme_intr_msi(jme, intrstat);
1523 jme_reset_link(struct jme_adapter *jme)
1525 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1529 jme_restart_an(struct jme_adapter *jme)
1533 spin_lock_bh(&jme->phy_lock);
1534 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1535 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1536 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1537 spin_unlock_bh(&jme->phy_lock);
1541 jme_request_irq(struct jme_adapter *jme)
1544 struct net_device *netdev = jme->dev;
1545 irq_handler_t handler = jme_intr;
1546 int irq_flags = IRQF_SHARED;
1548 if (!pci_enable_msi(jme->pdev)) {
1549 set_bit(JME_FLAG_MSI, &jme->flags);
1554 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1558 "Unable to request %s interrupt (return: %d)\n",
1559 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1562 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1563 pci_disable_msi(jme->pdev);
1564 clear_bit(JME_FLAG_MSI, &jme->flags);
1567 netdev->irq = jme->pdev->irq;
1574 jme_free_irq(struct jme_adapter *jme)
1576 free_irq(jme->pdev->irq, jme->dev);
1577 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1578 pci_disable_msi(jme->pdev);
1579 clear_bit(JME_FLAG_MSI, &jme->flags);
1580 jme->dev->irq = jme->pdev->irq;
1585 jme_open(struct net_device *netdev)
1587 struct jme_adapter *jme = netdev_priv(netdev);
1591 JME_NAPI_ENABLE(jme);
1593 tasklet_enable(&jme->linkch_task);
1594 tasklet_enable(&jme->txclean_task);
1595 tasklet_hi_enable(&jme->rxclean_task);
1596 tasklet_hi_enable(&jme->rxempty_task);
1598 rc = jme_request_irq(jme);
1604 if (test_bit(JME_FLAG_SSET, &jme->flags))
1605 jme_set_settings(netdev, &jme->old_ecmd);
1607 jme_reset_phy_processor(jme);
1609 jme_reset_link(jme);
1614 netif_stop_queue(netdev);
1615 netif_carrier_off(netdev);
1621 jme_set_100m_half(struct jme_adapter *jme)
1625 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1626 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1627 BMCR_SPEED1000 | BMCR_FULLDPLX);
1628 tmp |= BMCR_SPEED100;
1631 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1634 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1636 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1639 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1641 jme_wait_link(struct jme_adapter *jme)
1643 u32 phylink, to = JME_WAIT_LINK_TIME;
1646 phylink = jme_linkstat_from_phy(jme);
1647 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1649 phylink = jme_linkstat_from_phy(jme);
1655 jme_phy_off(struct jme_adapter *jme)
1657 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1661 jme_close(struct net_device *netdev)
1663 struct jme_adapter *jme = netdev_priv(netdev);
1665 netif_stop_queue(netdev);
1666 netif_carrier_off(netdev);
1671 JME_NAPI_DISABLE(jme);
1673 tasklet_disable(&jme->linkch_task);
1674 tasklet_disable(&jme->txclean_task);
1675 tasklet_disable(&jme->rxclean_task);
1676 tasklet_disable(&jme->rxempty_task);
1678 jme_reset_ghc_speed(jme);
1679 jme_disable_rx_engine(jme);
1680 jme_disable_tx_engine(jme);
1681 jme_reset_mac_processor(jme);
1682 jme_free_rx_resources(jme);
1683 jme_free_tx_resources(jme);
1691 jme_alloc_txdesc(struct jme_adapter *jme,
1692 struct sk_buff *skb)
1694 struct jme_ring *txring = &(jme->txring[0]);
1695 int idx, nr_alloc, mask = jme->tx_ring_mask;
1697 idx = txring->next_to_use;
1698 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1700 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1703 atomic_sub(nr_alloc, &txring->nr_free);
1705 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1711 jme_fill_tx_map(struct pci_dev *pdev,
1712 struct txdesc *txdesc,
1713 struct jme_buffer_info *txbi,
1721 dmaaddr = pci_map_page(pdev,
1727 pci_dma_sync_single_for_device(pdev,
1734 txdesc->desc2.flags = TXFLAG_OWN;
1735 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1736 txdesc->desc2.datalen = cpu_to_le16(len);
1737 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1738 txdesc->desc2.bufaddrl = cpu_to_le32(
1739 (__u64)dmaaddr & 0xFFFFFFFFUL);
1741 txbi->mapping = dmaaddr;
1746 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1748 struct jme_ring *txring = &(jme->txring[0]);
1749 struct txdesc *txdesc = txring->desc, *ctxdesc;
1750 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1751 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1752 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1753 int mask = jme->tx_ring_mask;
1754 struct skb_frag_struct *frag;
1757 for (i = 0 ; i < nr_frags ; ++i) {
1758 frag = &skb_shinfo(skb)->frags[i];
1759 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1760 ctxbi = txbi + ((idx + i + 2) & (mask));
1762 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1763 frag->page_offset, frag->size, hidma);
1766 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1767 ctxdesc = txdesc + ((idx + 1) & (mask));
1768 ctxbi = txbi + ((idx + 1) & (mask));
1769 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1770 offset_in_page(skb->data), len, hidma);
1775 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1777 if (unlikely(skb_shinfo(skb)->gso_size &&
1778 skb_header_cloned(skb) &&
1779 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1788 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1790 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1792 *flags |= TXFLAG_LSEN;
1794 if (skb->protocol == htons(ETH_P_IP)) {
1795 struct iphdr *iph = ip_hdr(skb);
1798 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1803 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1805 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1818 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1820 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1823 switch (skb->protocol) {
1824 case htons(ETH_P_IP):
1825 ip_proto = ip_hdr(skb)->protocol;
1827 case htons(ETH_P_IPV6):
1828 ip_proto = ipv6_hdr(skb)->nexthdr;
1837 *flags |= TXFLAG_TCPCS;
1840 *flags |= TXFLAG_UDPCS;
1843 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol.\n");
1850 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1852 if (vlan_tx_tag_present(skb)) {
1853 *flags |= TXFLAG_TAGON;
1854 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1859 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1861 struct jme_ring *txring = &(jme->txring[0]);
1862 struct txdesc *txdesc;
1863 struct jme_buffer_info *txbi;
1866 txdesc = (struct txdesc *)txring->desc + idx;
1867 txbi = txring->bufinf + idx;
1873 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1875 * Set OWN bit at final.
1876 * When kernel transmit faster than NIC.
1877 * And NIC trying to send this descriptor before we tell
1878 * it to start sending this TX queue.
1879 * Other fields are already filled correctly.
1882 flags = TXFLAG_OWN | TXFLAG_INT;
1884 * Set checksum flags while not tso
1886 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1887 jme_tx_csum(jme, skb, &flags);
1888 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1889 jme_map_tx_skb(jme, skb, idx);
1890 txdesc->desc1.flags = flags;
1892 * Set tx buffer info after telling NIC to send
1893 * For better tx_clean timing
1896 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1898 txbi->len = skb->len;
1899 txbi->start_xmit = jiffies;
1900 if (!txbi->start_xmit)
1901 txbi->start_xmit = (0UL-1);
1907 jme_stop_queue_if_full(struct jme_adapter *jme)
1909 struct jme_ring *txring = &(jme->txring[0]);
1910 struct jme_buffer_info *txbi = txring->bufinf;
1911 int idx = atomic_read(&txring->next_to_clean);
1916 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1917 netif_stop_queue(jme->dev);
1918 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused.\n");
1920 if (atomic_read(&txring->nr_free)
1921 >= (jme->tx_wake_threshold)) {
1922 netif_wake_queue(jme->dev);
1923 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked.\n");
1927 if (unlikely(txbi->start_xmit &&
1928 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1930 netif_stop_queue(jme->dev);
1931 netif_info(jme, tx_queued, jme->dev, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1936 * This function is already protected by netif_tx_lock()
1940 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1942 struct jme_adapter *jme = netdev_priv(netdev);
1945 if (unlikely(jme_expand_header(jme, skb))) {
1946 ++(NET_STAT(jme).tx_dropped);
1947 return NETDEV_TX_OK;
1950 idx = jme_alloc_txdesc(jme, skb);
1952 if (unlikely(idx < 0)) {
1953 netif_stop_queue(netdev);
1954 netif_err(jme, tx_err, jme->dev, "BUG! Tx ring full when queue awake!\n");
1956 return NETDEV_TX_BUSY;
1959 jme_fill_tx_desc(jme, skb, idx);
1961 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1962 TXCS_SELECT_QUEUE0 |
1966 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1967 skb_shinfo(skb)->nr_frags + 2,
1969 jme_stop_queue_if_full(jme);
1971 return NETDEV_TX_OK;
1975 jme_set_macaddr(struct net_device *netdev, void *p)
1977 struct jme_adapter *jme = netdev_priv(netdev);
1978 struct sockaddr *addr = p;
1981 if (netif_running(netdev))
1984 spin_lock_bh(&jme->macaddr_lock);
1985 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1987 val = (addr->sa_data[3] & 0xff) << 24 |
1988 (addr->sa_data[2] & 0xff) << 16 |
1989 (addr->sa_data[1] & 0xff) << 8 |
1990 (addr->sa_data[0] & 0xff);
1991 jwrite32(jme, JME_RXUMA_LO, val);
1992 val = (addr->sa_data[5] & 0xff) << 8 |
1993 (addr->sa_data[4] & 0xff);
1994 jwrite32(jme, JME_RXUMA_HI, val);
1995 spin_unlock_bh(&jme->macaddr_lock);
2001 jme_set_multi(struct net_device *netdev)
2003 struct jme_adapter *jme = netdev_priv(netdev);
2004 u32 mc_hash[2] = {};
2006 spin_lock_bh(&jme->rxmcs_lock);
2008 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2010 if (netdev->flags & IFF_PROMISC) {
2011 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2012 } else if (netdev->flags & IFF_ALLMULTI) {
2013 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2014 } else if (netdev->flags & IFF_MULTICAST) {
2015 struct dev_mc_list *mclist;
2018 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2019 netdev_for_each_mc_addr(mclist, netdev) {
2020 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2021 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2024 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2025 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2029 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2031 spin_unlock_bh(&jme->rxmcs_lock);
2035 jme_change_mtu(struct net_device *netdev, int new_mtu)
2037 struct jme_adapter *jme = netdev_priv(netdev);
2039 if (new_mtu == jme->old_mtu)
2042 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2043 ((new_mtu) < IPV6_MIN_MTU))
2046 if (new_mtu > 4000) {
2047 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2048 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2049 jme_restart_rx_engine(jme);
2051 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2052 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2053 jme_restart_rx_engine(jme);
2056 if (new_mtu > 1900) {
2057 netdev->features &= ~(NETIF_F_HW_CSUM |
2061 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2062 netdev->features |= NETIF_F_HW_CSUM;
2063 if (test_bit(JME_FLAG_TSO, &jme->flags))
2064 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2067 netdev->mtu = new_mtu;
2068 jme_reset_link(jme);
2074 jme_tx_timeout(struct net_device *netdev)
2076 struct jme_adapter *jme = netdev_priv(netdev);
2079 jme_reset_phy_processor(jme);
2080 if (test_bit(JME_FLAG_SSET, &jme->flags))
2081 jme_set_settings(netdev, &jme->old_ecmd);
2084 * Force to Reset the link again
2086 jme_reset_link(jme);
2090 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2092 struct jme_adapter *jme = netdev_priv(netdev);
2094 spin_lock_bh(&jme->vlgrp_lock);
2096 spin_unlock_bh(&jme->vlgrp_lock);
2100 jme_get_drvinfo(struct net_device *netdev,
2101 struct ethtool_drvinfo *info)
2103 struct jme_adapter *jme = netdev_priv(netdev);
2105 strcpy(info->driver, DRV_NAME);
2106 strcpy(info->version, DRV_VERSION);
2107 strcpy(info->bus_info, pci_name(jme->pdev));
2111 jme_get_regs_len(struct net_device *netdev)
2117 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2121 for (i = 0 ; i < len ; i += 4)
2122 p[i >> 2] = jread32(jme, reg + i);
2126 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2129 u16 *p16 = (u16 *)p;
2131 for (i = 0 ; i < reg_nr ; ++i)
2132 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2136 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2138 struct jme_adapter *jme = netdev_priv(netdev);
2139 u32 *p32 = (u32 *)p;
2141 memset(p, 0xFF, JME_REG_LEN);
2144 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2147 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2150 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2153 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2156 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2160 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2162 struct jme_adapter *jme = netdev_priv(netdev);
2164 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2165 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2167 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2168 ecmd->use_adaptive_rx_coalesce = false;
2169 ecmd->rx_coalesce_usecs = 0;
2170 ecmd->rx_max_coalesced_frames = 0;
2174 ecmd->use_adaptive_rx_coalesce = true;
2176 switch (jme->dpi.cur) {
2178 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2179 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2182 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2183 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2186 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2187 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2197 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2199 struct jme_adapter *jme = netdev_priv(netdev);
2200 struct dynpcc_info *dpi = &(jme->dpi);
2202 if (netif_running(netdev))
2205 if (ecmd->use_adaptive_rx_coalesce &&
2206 test_bit(JME_FLAG_POLL, &jme->flags)) {
2207 clear_bit(JME_FLAG_POLL, &jme->flags);
2208 jme->jme_rx = netif_rx;
2209 jme->jme_vlan_rx = vlan_hwaccel_rx;
2211 dpi->attempt = PCC_P1;
2213 jme_set_rx_pcc(jme, PCC_P1);
2214 jme_interrupt_mode(jme);
2215 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2216 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2217 set_bit(JME_FLAG_POLL, &jme->flags);
2218 jme->jme_rx = netif_receive_skb;
2219 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2220 jme_interrupt_mode(jme);
2227 jme_get_pauseparam(struct net_device *netdev,
2228 struct ethtool_pauseparam *ecmd)
2230 struct jme_adapter *jme = netdev_priv(netdev);
2233 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2234 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2236 spin_lock_bh(&jme->phy_lock);
2237 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2238 spin_unlock_bh(&jme->phy_lock);
2241 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2245 jme_set_pauseparam(struct net_device *netdev,
2246 struct ethtool_pauseparam *ecmd)
2248 struct jme_adapter *jme = netdev_priv(netdev);
2251 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2252 (ecmd->tx_pause != 0)) {
2255 jme->reg_txpfc |= TXPFC_PF_EN;
2257 jme->reg_txpfc &= ~TXPFC_PF_EN;
2259 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2262 spin_lock_bh(&jme->rxmcs_lock);
2263 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2264 (ecmd->rx_pause != 0)) {
2267 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2269 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2271 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2273 spin_unlock_bh(&jme->rxmcs_lock);
2275 spin_lock_bh(&jme->phy_lock);
2276 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2277 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2278 (ecmd->autoneg != 0)) {
2281 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2283 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2285 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2286 MII_ADVERTISE, val);
2288 spin_unlock_bh(&jme->phy_lock);
2294 jme_get_wol(struct net_device *netdev,
2295 struct ethtool_wolinfo *wol)
2297 struct jme_adapter *jme = netdev_priv(netdev);
2299 wol->supported = WAKE_MAGIC | WAKE_PHY;
2303 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2304 wol->wolopts |= WAKE_PHY;
2306 if (jme->reg_pmcs & PMCS_MFEN)
2307 wol->wolopts |= WAKE_MAGIC;
2312 jme_set_wol(struct net_device *netdev,
2313 struct ethtool_wolinfo *wol)
2315 struct jme_adapter *jme = netdev_priv(netdev);
2317 if (wol->wolopts & (WAKE_MAGICSECURE |
2326 if (wol->wolopts & WAKE_PHY)
2327 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2329 if (wol->wolopts & WAKE_MAGIC)
2330 jme->reg_pmcs |= PMCS_MFEN;
2332 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2338 jme_get_settings(struct net_device *netdev,
2339 struct ethtool_cmd *ecmd)
2341 struct jme_adapter *jme = netdev_priv(netdev);
2344 spin_lock_bh(&jme->phy_lock);
2345 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2346 spin_unlock_bh(&jme->phy_lock);
2351 jme_set_settings(struct net_device *netdev,
2352 struct ethtool_cmd *ecmd)
2354 struct jme_adapter *jme = netdev_priv(netdev);
2357 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2360 if (jme->mii_if.force_media &&
2361 ecmd->autoneg != AUTONEG_ENABLE &&
2362 (jme->mii_if.full_duplex != ecmd->duplex))
2365 spin_lock_bh(&jme->phy_lock);
2366 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2367 spin_unlock_bh(&jme->phy_lock);
2370 jme_reset_link(jme);
2373 set_bit(JME_FLAG_SSET, &jme->flags);
2374 jme->old_ecmd = *ecmd;
2381 jme_get_link(struct net_device *netdev)
2383 struct jme_adapter *jme = netdev_priv(netdev);
2384 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2388 jme_get_msglevel(struct net_device *netdev)
2390 struct jme_adapter *jme = netdev_priv(netdev);
2391 return jme->msg_enable;
2395 jme_set_msglevel(struct net_device *netdev, u32 value)
2397 struct jme_adapter *jme = netdev_priv(netdev);
2398 jme->msg_enable = value;
2402 jme_get_rx_csum(struct net_device *netdev)
2404 struct jme_adapter *jme = netdev_priv(netdev);
2405 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2409 jme_set_rx_csum(struct net_device *netdev, u32 on)
2411 struct jme_adapter *jme = netdev_priv(netdev);
2413 spin_lock_bh(&jme->rxmcs_lock);
2415 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2417 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2418 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2419 spin_unlock_bh(&jme->rxmcs_lock);
2425 jme_set_tx_csum(struct net_device *netdev, u32 on)
2427 struct jme_adapter *jme = netdev_priv(netdev);
2430 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2431 if (netdev->mtu <= 1900)
2432 netdev->features |= NETIF_F_HW_CSUM;
2434 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2435 netdev->features &= ~NETIF_F_HW_CSUM;
2442 jme_set_tso(struct net_device *netdev, u32 on)
2444 struct jme_adapter *jme = netdev_priv(netdev);
2447 set_bit(JME_FLAG_TSO, &jme->flags);
2448 if (netdev->mtu <= 1900)
2449 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2451 clear_bit(JME_FLAG_TSO, &jme->flags);
2452 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2459 jme_nway_reset(struct net_device *netdev)
2461 struct jme_adapter *jme = netdev_priv(netdev);
2462 jme_restart_an(jme);
2467 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2472 val = jread32(jme, JME_SMBCSR);
2473 to = JME_SMB_BUSY_TIMEOUT;
2474 while ((val & SMBCSR_BUSY) && --to) {
2476 val = jread32(jme, JME_SMBCSR);
2479 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2483 jwrite32(jme, JME_SMBINTF,
2484 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2485 SMBINTF_HWRWN_READ |
2488 val = jread32(jme, JME_SMBINTF);
2489 to = JME_SMB_BUSY_TIMEOUT;
2490 while ((val & SMBINTF_HWCMD) && --to) {
2492 val = jread32(jme, JME_SMBINTF);
2495 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2499 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2503 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2508 val = jread32(jme, JME_SMBCSR);
2509 to = JME_SMB_BUSY_TIMEOUT;
2510 while ((val & SMBCSR_BUSY) && --to) {
2512 val = jread32(jme, JME_SMBCSR);
2515 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2519 jwrite32(jme, JME_SMBINTF,
2520 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2521 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2522 SMBINTF_HWRWN_WRITE |
2525 val = jread32(jme, JME_SMBINTF);
2526 to = JME_SMB_BUSY_TIMEOUT;
2527 while ((val & SMBINTF_HWCMD) && --to) {
2529 val = jread32(jme, JME_SMBINTF);
2532 netif_err(jme, hw, jme->dev, "SMB Bus Busy.\n");
2540 jme_get_eeprom_len(struct net_device *netdev)
2542 struct jme_adapter *jme = netdev_priv(netdev);
2544 val = jread32(jme, JME_SMBCSR);
2545 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2549 jme_get_eeprom(struct net_device *netdev,
2550 struct ethtool_eeprom *eeprom, u8 *data)
2552 struct jme_adapter *jme = netdev_priv(netdev);
2553 int i, offset = eeprom->offset, len = eeprom->len;
2556 * ethtool will check the boundary for us
2558 eeprom->magic = JME_EEPROM_MAGIC;
2559 for (i = 0 ; i < len ; ++i)
2560 data[i] = jme_smb_read(jme, i + offset);
2566 jme_set_eeprom(struct net_device *netdev,
2567 struct ethtool_eeprom *eeprom, u8 *data)
2569 struct jme_adapter *jme = netdev_priv(netdev);
2570 int i, offset = eeprom->offset, len = eeprom->len;
2572 if (eeprom->magic != JME_EEPROM_MAGIC)
2576 * ethtool will check the boundary for us
2578 for (i = 0 ; i < len ; ++i)
2579 jme_smb_write(jme, i + offset, data[i]);
2584 static const struct ethtool_ops jme_ethtool_ops = {
2585 .get_drvinfo = jme_get_drvinfo,
2586 .get_regs_len = jme_get_regs_len,
2587 .get_regs = jme_get_regs,
2588 .get_coalesce = jme_get_coalesce,
2589 .set_coalesce = jme_set_coalesce,
2590 .get_pauseparam = jme_get_pauseparam,
2591 .set_pauseparam = jme_set_pauseparam,
2592 .get_wol = jme_get_wol,
2593 .set_wol = jme_set_wol,
2594 .get_settings = jme_get_settings,
2595 .set_settings = jme_set_settings,
2596 .get_link = jme_get_link,
2597 .get_msglevel = jme_get_msglevel,
2598 .set_msglevel = jme_set_msglevel,
2599 .get_rx_csum = jme_get_rx_csum,
2600 .set_rx_csum = jme_set_rx_csum,
2601 .set_tx_csum = jme_set_tx_csum,
2602 .set_tso = jme_set_tso,
2603 .set_sg = ethtool_op_set_sg,
2604 .nway_reset = jme_nway_reset,
2605 .get_eeprom_len = jme_get_eeprom_len,
2606 .get_eeprom = jme_get_eeprom,
2607 .set_eeprom = jme_set_eeprom,
2611 jme_pci_dma64(struct pci_dev *pdev)
2613 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2614 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2615 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2618 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2619 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2620 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2623 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2624 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2631 jme_phy_init(struct jme_adapter *jme)
2635 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2636 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2640 jme_check_hw_ver(struct jme_adapter *jme)
2644 chipmode = jread32(jme, JME_CHIPMODE);
2646 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2647 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2650 static const struct net_device_ops jme_netdev_ops = {
2651 .ndo_open = jme_open,
2652 .ndo_stop = jme_close,
2653 .ndo_validate_addr = eth_validate_addr,
2654 .ndo_start_xmit = jme_start_xmit,
2655 .ndo_set_mac_address = jme_set_macaddr,
2656 .ndo_set_multicast_list = jme_set_multi,
2657 .ndo_change_mtu = jme_change_mtu,
2658 .ndo_tx_timeout = jme_tx_timeout,
2659 .ndo_vlan_rx_register = jme_vlan_rx_register,
2662 static int __devinit
2663 jme_init_one(struct pci_dev *pdev,
2664 const struct pci_device_id *ent)
2666 int rc = 0, using_dac, i;
2667 struct net_device *netdev;
2668 struct jme_adapter *jme;
2673 * set up PCI device basics
2675 rc = pci_enable_device(pdev);
2677 jeprintk(pdev, "Cannot enable PCI device.\n");
2681 using_dac = jme_pci_dma64(pdev);
2682 if (using_dac < 0) {
2683 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2685 goto err_out_disable_pdev;
2688 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2689 jeprintk(pdev, "No PCI resource region found.\n");
2691 goto err_out_disable_pdev;
2694 rc = pci_request_regions(pdev, DRV_NAME);
2696 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2697 goto err_out_disable_pdev;
2700 pci_set_master(pdev);
2703 * alloc and init net device
2705 netdev = alloc_etherdev(sizeof(*jme));
2707 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2709 goto err_out_release_regions;
2711 netdev->netdev_ops = &jme_netdev_ops;
2712 netdev->ethtool_ops = &jme_ethtool_ops;
2713 netdev->watchdog_timeo = TX_TIMEOUT;
2714 netdev->features = NETIF_F_HW_CSUM |
2718 NETIF_F_HW_VLAN_TX |
2721 netdev->features |= NETIF_F_HIGHDMA;
2723 SET_NETDEV_DEV(netdev, &pdev->dev);
2724 pci_set_drvdata(pdev, netdev);
2729 jme = netdev_priv(netdev);
2732 jme->jme_rx = netif_rx;
2733 jme->jme_vlan_rx = vlan_hwaccel_rx;
2734 jme->old_mtu = netdev->mtu = 1500;
2736 jme->tx_ring_size = 1 << 10;
2737 jme->tx_ring_mask = jme->tx_ring_size - 1;
2738 jme->tx_wake_threshold = 1 << 9;
2739 jme->rx_ring_size = 1 << 9;
2740 jme->rx_ring_mask = jme->rx_ring_size - 1;
2741 jme->msg_enable = JME_DEF_MSG_ENABLE;
2742 jme->regs = ioremap(pci_resource_start(pdev, 0),
2743 pci_resource_len(pdev, 0));
2745 jeprintk(pdev, "Mapping PCI resource region error.\n");
2747 goto err_out_free_netdev;
2751 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2752 jwrite32(jme, JME_APMC, apmc);
2753 } else if (force_pseudohp) {
2754 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2755 jwrite32(jme, JME_APMC, apmc);
2758 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2760 spin_lock_init(&jme->phy_lock);
2761 spin_lock_init(&jme->macaddr_lock);
2762 spin_lock_init(&jme->rxmcs_lock);
2763 spin_lock_init(&jme->vlgrp_lock);
2765 atomic_set(&jme->link_changing, 1);
2766 atomic_set(&jme->rx_cleaning, 1);
2767 atomic_set(&jme->tx_cleaning, 1);
2768 atomic_set(&jme->rx_empty, 1);
2770 tasklet_init(&jme->pcc_task,
2772 (unsigned long) jme);
2773 tasklet_init(&jme->linkch_task,
2774 jme_link_change_tasklet,
2775 (unsigned long) jme);
2776 tasklet_init(&jme->txclean_task,
2777 jme_tx_clean_tasklet,
2778 (unsigned long) jme);
2779 tasklet_init(&jme->rxclean_task,
2780 jme_rx_clean_tasklet,
2781 (unsigned long) jme);
2782 tasklet_init(&jme->rxempty_task,
2783 jme_rx_empty_tasklet,
2784 (unsigned long) jme);
2785 tasklet_disable_nosync(&jme->linkch_task);
2786 tasklet_disable_nosync(&jme->txclean_task);
2787 tasklet_disable_nosync(&jme->rxclean_task);
2788 tasklet_disable_nosync(&jme->rxempty_task);
2789 jme->dpi.cur = PCC_P1;
2792 jme->reg_rxcs = RXCS_DEFAULT;
2793 jme->reg_rxmcs = RXMCS_DEFAULT;
2795 jme->reg_pmcs = PMCS_MFEN;
2796 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2797 set_bit(JME_FLAG_TSO, &jme->flags);
2800 * Get Max Read Req Size from PCI Config Space
2802 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2803 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2804 switch (jme->mrrs) {
2806 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2809 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2812 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2817 * Must check before reset_mac_processor
2819 jme_check_hw_ver(jme);
2820 jme->mii_if.dev = netdev;
2822 jme->mii_if.phy_id = 0;
2823 for (i = 1 ; i < 32 ; ++i) {
2824 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2825 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2826 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2827 jme->mii_if.phy_id = i;
2832 if (!jme->mii_if.phy_id) {
2834 jeprintk(pdev, "Can not find phy_id.\n");
2838 jme->reg_ghc |= GHC_LINK_POLL;
2840 jme->mii_if.phy_id = 1;
2842 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2843 jme->mii_if.supports_gmii = true;
2845 jme->mii_if.supports_gmii = false;
2846 jme->mii_if.mdio_read = jme_mdio_read;
2847 jme->mii_if.mdio_write = jme_mdio_write;
2850 jme_set_phyfifoa(jme);
2851 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2857 * Reset MAC processor and reload EEPROM for MAC Address
2859 jme_reset_mac_processor(jme);
2860 rc = jme_reload_eeprom(jme);
2863 "Reload eeprom for reading MAC Address error.\n");
2866 jme_load_macaddr(netdev);
2869 * Tell stack that we are not ready to work until open()
2871 netif_carrier_off(netdev);
2872 netif_stop_queue(netdev);
2877 rc = register_netdev(netdev);
2879 jeprintk(pdev, "Cannot register net device.\n");
2883 netif_info(jme, probe, jme->dev, "%s%s ver:%x rev:%x macaddr:%pM\n",
2884 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
2885 "JMC250 Gigabit Ethernet" :
2886 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
2887 "JMC260 Fast Ethernet" : "Unknown",
2888 (jme->fpgaver != 0) ? " (FPGA)" : "",
2889 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2890 jme->rev, netdev->dev_addr);
2896 err_out_free_netdev:
2897 pci_set_drvdata(pdev, NULL);
2898 free_netdev(netdev);
2899 err_out_release_regions:
2900 pci_release_regions(pdev);
2901 err_out_disable_pdev:
2902 pci_disable_device(pdev);
2907 static void __devexit
2908 jme_remove_one(struct pci_dev *pdev)
2910 struct net_device *netdev = pci_get_drvdata(pdev);
2911 struct jme_adapter *jme = netdev_priv(netdev);
2913 unregister_netdev(netdev);
2915 pci_set_drvdata(pdev, NULL);
2916 free_netdev(netdev);
2917 pci_release_regions(pdev);
2918 pci_disable_device(pdev);
2924 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2926 struct net_device *netdev = pci_get_drvdata(pdev);
2927 struct jme_adapter *jme = netdev_priv(netdev);
2929 atomic_dec(&jme->link_changing);
2931 netif_device_detach(netdev);
2932 netif_stop_queue(netdev);
2935 tasklet_disable(&jme->txclean_task);
2936 tasklet_disable(&jme->rxclean_task);
2937 tasklet_disable(&jme->rxempty_task);
2939 if (netif_carrier_ok(netdev)) {
2940 if (test_bit(JME_FLAG_POLL, &jme->flags))
2941 jme_polling_mode(jme);
2943 jme_stop_pcc_timer(jme);
2944 jme_reset_ghc_speed(jme);
2945 jme_disable_rx_engine(jme);
2946 jme_disable_tx_engine(jme);
2947 jme_reset_mac_processor(jme);
2948 jme_free_rx_resources(jme);
2949 jme_free_tx_resources(jme);
2950 netif_carrier_off(netdev);
2954 tasklet_enable(&jme->txclean_task);
2955 tasklet_hi_enable(&jme->rxclean_task);
2956 tasklet_hi_enable(&jme->rxempty_task);
2958 pci_save_state(pdev);
2959 if (jme->reg_pmcs) {
2960 jme_set_100m_half(jme);
2962 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2965 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2967 pci_enable_wake(pdev, PCI_D3cold, true);
2971 pci_set_power_state(pdev, PCI_D3cold);
2977 jme_resume(struct pci_dev *pdev)
2979 struct net_device *netdev = pci_get_drvdata(pdev);
2980 struct jme_adapter *jme = netdev_priv(netdev);
2983 pci_restore_state(pdev);
2985 if (test_bit(JME_FLAG_SSET, &jme->flags))
2986 jme_set_settings(netdev, &jme->old_ecmd);
2988 jme_reset_phy_processor(jme);
2991 netif_device_attach(netdev);
2993 atomic_inc(&jme->link_changing);
2995 jme_reset_link(jme);
3001 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3002 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3003 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3007 static struct pci_driver jme_driver = {
3009 .id_table = jme_pci_tbl,
3010 .probe = jme_init_one,
3011 .remove = __devexit_p(jme_remove_one),
3013 .suspend = jme_suspend,
3014 .resume = jme_resume,
3015 #endif /* CONFIG_PM */
3019 jme_init_module(void)
3021 printk(KERN_INFO PFX "JMicron JMC2XX ethernet "
3022 "driver version %s\n", DRV_VERSION);
3023 return pci_register_driver(&jme_driver);
3027 jme_cleanup_module(void)
3029 pci_unregister_driver(&jme_driver);
3032 module_init(jme_init_module);
3033 module_exit(jme_cleanup_module);
3035 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3036 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3037 MODULE_LICENSE("GPL");
3038 MODULE_VERSION(DRV_VERSION);
3039 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);