2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/version.h>
26 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
27 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30 #include <linux/module.h>
31 #include <linux/kernel.h>
32 #include <linux/pci.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/mii.h>
37 #include <linux/crc32.h>
38 #include <linux/delay.h>
39 #include <linux/spinlock.h>
42 #include <linux/ipv6.h>
43 #include <linux/tcp.h>
44 #include <linux/udp.h>
45 #include <linux/if_vlan.h>
46 #include <linux/slab.h>
47 #include <net/ip6_checksum.h>
50 static int force_pseudohp = -1;
51 static int no_pseudohp = -1;
52 static int no_extplug = -1;
53 module_param(force_pseudohp, int, 0);
54 MODULE_PARM_DESC(force_pseudohp,
55 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
56 module_param(no_pseudohp, int, 0);
57 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
58 module_param(no_extplug, int, 0);
59 MODULE_PARM_DESC(no_extplug,
60 "Do not use external plug signal for pseudo hot-plug.");
62 #ifndef JME_NEW_PM_API
64 jme_pci_wakeup_enable(struct jme_adapter *jme, int enable)
66 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27)
67 pci_enable_wake(jme->pdev, PCI_D1, enable);
68 pci_enable_wake(jme->pdev, PCI_D2, enable);
69 pci_enable_wake(jme->pdev, PCI_D3hot, enable);
70 pci_enable_wake(jme->pdev, PCI_D3cold, enable);
72 pci_pme_active(jme->pdev, enable);
78 jme_mdio_read(struct net_device *netdev, int phy, int reg)
80 struct jme_adapter *jme = netdev_priv(netdev);
81 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
84 jwrite32(jme, JME_SMI, SMI_OP_REQ |
89 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
91 val = jread32(jme, JME_SMI);
92 if ((val & SMI_OP_REQ) == 0)
97 pr_err("phy(%d) read timeout : %d\n", phy, reg);
104 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
108 jme_mdio_write(struct net_device *netdev,
109 int phy, int reg, int val)
111 struct jme_adapter *jme = netdev_priv(netdev);
114 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
115 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
116 smi_phy_addr(phy) | smi_reg_addr(reg));
119 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
121 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
126 pr_err("phy(%d) write timeout : %d\n", phy, reg);
130 jme_reset_phy_processor(struct jme_adapter *jme)
134 jme_mdio_write(jme->dev,
136 MII_ADVERTISE, ADVERTISE_ALL |
137 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
139 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
140 jme_mdio_write(jme->dev,
143 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
145 val = jme_mdio_read(jme->dev,
149 jme_mdio_write(jme->dev,
151 MII_BMCR, val | BMCR_RESET);
155 jme_setup_wakeup_frame(struct jme_adapter *jme,
156 const u32 *mask, u32 crc, int fnr)
163 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
165 jwrite32(jme, JME_WFODP, crc);
171 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
172 jwrite32(jme, JME_WFOI,
173 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
174 (fnr & WFOI_FRAME_SEL));
176 jwrite32(jme, JME_WFODP, mask[i]);
182 jme_mac_rxclk_off(struct jme_adapter *jme)
184 jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
185 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
189 jme_mac_rxclk_on(struct jme_adapter *jme)
191 jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
192 jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
196 jme_mac_txclk_off(struct jme_adapter *jme)
198 jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
199 jwrite32f(jme, JME_GHC, jme->reg_ghc);
203 jme_mac_txclk_on(struct jme_adapter *jme)
205 u32 speed = jme->reg_ghc & GHC_SPEED;
206 if (speed == GHC_SPEED_1000M)
207 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
209 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
210 jwrite32f(jme, JME_GHC, jme->reg_ghc);
214 jme_reset_ghc_speed(struct jme_adapter *jme)
216 jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
217 jwrite32f(jme, JME_GHC, jme->reg_ghc);
221 jme_reset_250A2_workaround(struct jme_adapter *jme)
223 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
225 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
229 jme_assert_ghc_reset(struct jme_adapter *jme)
231 jme->reg_ghc |= GHC_SWRST;
232 jwrite32f(jme, JME_GHC, jme->reg_ghc);
236 jme_clear_ghc_reset(struct jme_adapter *jme)
238 jme->reg_ghc &= ~GHC_SWRST;
239 jwrite32f(jme, JME_GHC, jme->reg_ghc);
243 jme_reset_mac_processor(struct jme_adapter *jme)
245 static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
246 u32 crc = 0xCDCDCDCD;
250 jme_reset_ghc_speed(jme);
251 jme_reset_250A2_workaround(jme);
253 jme_mac_rxclk_on(jme);
254 jme_mac_txclk_on(jme);
256 jme_assert_ghc_reset(jme);
258 jme_mac_rxclk_off(jme);
259 jme_mac_txclk_off(jme);
261 jme_clear_ghc_reset(jme);
263 jme_mac_rxclk_on(jme);
264 jme_mac_txclk_on(jme);
266 jme_mac_rxclk_off(jme);
267 jme_mac_txclk_off(jme);
269 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
270 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
271 jwrite32(jme, JME_RXQDC, 0x00000000);
272 jwrite32(jme, JME_RXNDA, 0x00000000);
273 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
274 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
275 jwrite32(jme, JME_TXQDC, 0x00000000);
276 jwrite32(jme, JME_TXNDA, 0x00000000);
278 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
279 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
280 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
281 jme_setup_wakeup_frame(jme, mask, crc, i);
283 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
285 gpreg0 = GPREG0_DEFAULT;
286 jwrite32(jme, JME_GPREG0, gpreg0);
290 jme_clear_pm(struct jme_adapter *jme)
292 jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
296 jme_reload_eeprom(struct jme_adapter *jme)
301 val = jread32(jme, JME_SMBCSR);
303 if (val & SMBCSR_EEPROMD) {
305 jwrite32(jme, JME_SMBCSR, val);
306 val |= SMBCSR_RELOAD;
307 jwrite32(jme, JME_SMBCSR, val);
310 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
312 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
317 pr_err("eeprom reload timeout\n");
326 jme_load_macaddr(struct net_device *netdev)
328 struct jme_adapter *jme = netdev_priv(netdev);
329 unsigned char macaddr[6];
332 spin_lock_bh(&jme->macaddr_lock);
333 val = jread32(jme, JME_RXUMA_LO);
334 macaddr[0] = (val >> 0) & 0xFF;
335 macaddr[1] = (val >> 8) & 0xFF;
336 macaddr[2] = (val >> 16) & 0xFF;
337 macaddr[3] = (val >> 24) & 0xFF;
338 val = jread32(jme, JME_RXUMA_HI);
339 macaddr[4] = (val >> 0) & 0xFF;
340 macaddr[5] = (val >> 8) & 0xFF;
341 memcpy(netdev->dev_addr, macaddr, 6);
342 spin_unlock_bh(&jme->macaddr_lock);
346 jme_set_rx_pcc(struct jme_adapter *jme, int p)
350 jwrite32(jme, JME_PCCRX0,
351 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
352 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
355 jwrite32(jme, JME_PCCRX0,
356 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
357 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
360 jwrite32(jme, JME_PCCRX0,
361 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
362 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
365 jwrite32(jme, JME_PCCRX0,
366 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
367 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
374 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
375 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
379 jme_start_irq(struct jme_adapter *jme)
381 register struct dynpcc_info *dpi = &(jme->dpi);
383 jme_set_rx_pcc(jme, PCC_P1);
385 dpi->attempt = PCC_P1;
388 jwrite32(jme, JME_PCCTX,
389 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
390 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
397 jwrite32(jme, JME_IENS, INTR_ENABLE);
401 jme_stop_irq(struct jme_adapter *jme)
406 jwrite32f(jme, JME_IENC, INTR_ENABLE);
410 jme_linkstat_from_phy(struct jme_adapter *jme)
414 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
415 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
416 if (bmsr & BMSR_ANCOMP)
417 phylink |= PHY_LINK_AUTONEG_COMPLETE;
423 jme_set_phyfifo_5level(struct jme_adapter *jme)
425 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
429 jme_set_phyfifo_8level(struct jme_adapter *jme)
431 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
435 jme_check_link(struct net_device *netdev, int testonly)
437 struct jme_adapter *jme = netdev_priv(netdev);
438 u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
445 phylink = jme_linkstat_from_phy(jme);
447 phylink = jread32(jme, JME_PHY_LINK);
449 if (phylink & PHY_LINK_UP) {
450 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
452 * If we did not enable AN
453 * Speed/Duplex Info should be obtained from SMI
455 phylink = PHY_LINK_UP;
457 bmcr = jme_mdio_read(jme->dev,
461 phylink |= ((bmcr & BMCR_SPEED1000) &&
462 (bmcr & BMCR_SPEED100) == 0) ?
463 PHY_LINK_SPEED_1000M :
464 (bmcr & BMCR_SPEED100) ?
465 PHY_LINK_SPEED_100M :
468 phylink |= (bmcr & BMCR_FULLDPLX) ?
471 strcat(linkmsg, "Forced: ");
474 * Keep polling for speed/duplex resolve complete
476 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
482 phylink = jme_linkstat_from_phy(jme);
484 phylink = jread32(jme, JME_PHY_LINK);
487 pr_err("Waiting speed resolve timeout\n");
489 strcat(linkmsg, "ANed: ");
492 if (jme->phylink == phylink) {
499 jme->phylink = phylink;
502 * The speed/duplex setting of jme->reg_ghc already cleared
503 * by jme_reset_mac_processor()
505 switch (phylink & PHY_LINK_SPEED_MASK) {
506 case PHY_LINK_SPEED_10M:
507 jme->reg_ghc |= GHC_SPEED_10M;
508 strcat(linkmsg, "10 Mbps, ");
510 case PHY_LINK_SPEED_100M:
511 jme->reg_ghc |= GHC_SPEED_100M;
512 strcat(linkmsg, "100 Mbps, ");
514 case PHY_LINK_SPEED_1000M:
515 jme->reg_ghc |= GHC_SPEED_1000M;
516 strcat(linkmsg, "1000 Mbps, ");
522 if (phylink & PHY_LINK_DUPLEX) {
523 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
524 jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
525 jme->reg_ghc |= GHC_DPX;
527 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
531 jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
534 jwrite32(jme, JME_GHC, jme->reg_ghc);
536 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
537 jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
539 if (!(phylink & PHY_LINK_DUPLEX))
540 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
541 switch (phylink & PHY_LINK_SPEED_MASK) {
542 case PHY_LINK_SPEED_10M:
543 jme_set_phyfifo_8level(jme);
544 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
546 case PHY_LINK_SPEED_100M:
547 jme_set_phyfifo_5level(jme);
548 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
550 case PHY_LINK_SPEED_1000M:
551 jme_set_phyfifo_8level(jme);
557 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
559 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
562 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
565 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
566 netif_carrier_on(netdev);
571 netif_info(jme, link, jme->dev, "Link is down\n");
573 netif_carrier_off(netdev);
581 jme_setup_tx_resources(struct jme_adapter *jme)
583 struct jme_ring *txring = &(jme->txring[0]);
585 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
586 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
596 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
598 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
599 txring->next_to_use = 0;
600 atomic_set(&txring->next_to_clean, 0);
601 atomic_set(&txring->nr_free, jme->tx_ring_size);
603 txring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
604 jme->tx_ring_size, GFP_ATOMIC);
605 if (unlikely(!(txring->bufinf)))
606 goto err_free_txring;
609 * Initialize Transmit Descriptors
611 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
612 memset(txring->bufinf, 0,
613 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
618 dma_free_coherent(&(jme->pdev->dev),
619 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
625 txring->dmaalloc = 0;
627 txring->bufinf = NULL;
633 jme_free_tx_resources(struct jme_adapter *jme)
636 struct jme_ring *txring = &(jme->txring[0]);
637 struct jme_buffer_info *txbi;
640 if (txring->bufinf) {
641 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
642 txbi = txring->bufinf + i;
644 dev_kfree_skb(txbi->skb);
650 txbi->start_xmit = 0;
652 kfree(txring->bufinf);
655 dma_free_coherent(&(jme->pdev->dev),
656 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
660 txring->alloc = NULL;
662 txring->dmaalloc = 0;
664 txring->bufinf = NULL;
666 txring->next_to_use = 0;
667 atomic_set(&txring->next_to_clean, 0);
668 atomic_set(&txring->nr_free, 0);
672 jme_enable_tx_engine(struct jme_adapter *jme)
677 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
681 * Setup TX Queue 0 DMA Bass Address
683 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
684 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
685 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
688 * Setup TX Descptor Count
690 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
696 jwrite32f(jme, JME_TXCS, jme->reg_txcs |
701 * Start clock for TX MAC Processor
703 jme_mac_txclk_on(jme);
707 jme_restart_tx_engine(struct jme_adapter *jme)
712 jwrite32(jme, JME_TXCS, jme->reg_txcs |
718 jme_disable_tx_engine(struct jme_adapter *jme)
726 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
729 val = jread32(jme, JME_TXCS);
730 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
732 val = jread32(jme, JME_TXCS);
737 pr_err("Disable TX engine timeout\n");
740 * Stop clock for TX MAC Processor
742 jme_mac_txclk_off(jme);
746 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
748 struct jme_ring *rxring = &(jme->rxring[0]);
749 register struct rxdesc *rxdesc = rxring->desc;
750 struct jme_buffer_info *rxbi = rxring->bufinf;
756 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
757 rxdesc->desc1.bufaddrl = cpu_to_le32(
758 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
759 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
760 if (jme->dev->features & NETIF_F_HIGHDMA)
761 rxdesc->desc1.flags = RXFLAG_64BIT;
763 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
767 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
769 struct jme_ring *rxring = &(jme->rxring[0]);
770 struct jme_buffer_info *rxbi = rxring->bufinf + i;
773 skb = netdev_alloc_skb(jme->dev,
774 jme->dev->mtu + RX_EXTRA_LEN);
777 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
782 rxbi->len = skb_tailroom(skb);
783 rxbi->mapping = pci_map_page(jme->pdev,
784 virt_to_page(skb->data),
785 offset_in_page(skb->data),
793 jme_free_rx_buf(struct jme_adapter *jme, int i)
795 struct jme_ring *rxring = &(jme->rxring[0]);
796 struct jme_buffer_info *rxbi = rxring->bufinf;
800 pci_unmap_page(jme->pdev,
804 dev_kfree_skb(rxbi->skb);
812 jme_free_rx_resources(struct jme_adapter *jme)
815 struct jme_ring *rxring = &(jme->rxring[0]);
818 if (rxring->bufinf) {
819 for (i = 0 ; i < jme->rx_ring_size ; ++i)
820 jme_free_rx_buf(jme, i);
821 kfree(rxring->bufinf);
824 dma_free_coherent(&(jme->pdev->dev),
825 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
828 rxring->alloc = NULL;
830 rxring->dmaalloc = 0;
832 rxring->bufinf = NULL;
834 rxring->next_to_use = 0;
835 atomic_set(&rxring->next_to_clean, 0);
839 jme_setup_rx_resources(struct jme_adapter *jme)
842 struct jme_ring *rxring = &(jme->rxring[0]);
844 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
845 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
854 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
856 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
857 rxring->next_to_use = 0;
858 atomic_set(&rxring->next_to_clean, 0);
860 rxring->bufinf = kmalloc(sizeof(struct jme_buffer_info) *
861 jme->rx_ring_size, GFP_ATOMIC);
862 if (unlikely(!(rxring->bufinf)))
863 goto err_free_rxring;
866 * Initiallize Receive Descriptors
868 memset(rxring->bufinf, 0,
869 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
870 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
871 if (unlikely(jme_make_new_rx_buf(jme, i))) {
872 jme_free_rx_resources(jme);
876 jme_set_clean_rxdesc(jme, i);
882 dma_free_coherent(&(jme->pdev->dev),
883 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
888 rxring->dmaalloc = 0;
890 rxring->bufinf = NULL;
896 jme_enable_rx_engine(struct jme_adapter *jme)
901 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
906 * Setup RX DMA Bass Address
908 jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
909 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
910 jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
913 * Setup RX Descriptor Count
915 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
918 * Setup Unicast Filter
920 jme_set_unicastaddr(jme->dev);
921 jme_set_multi(jme->dev);
927 jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
933 * Start clock for RX MAC Processor
935 jme_mac_rxclk_on(jme);
939 jme_restart_rx_engine(struct jme_adapter *jme)
944 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
951 jme_disable_rx_engine(struct jme_adapter *jme)
959 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
962 val = jread32(jme, JME_RXCS);
963 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
965 val = jread32(jme, JME_RXCS);
970 pr_err("Disable RX engine timeout\n");
973 * Stop clock for RX MAC Processor
975 jme_mac_rxclk_off(jme);
979 jme_udpsum(struct sk_buff *skb)
983 if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
985 if (skb->protocol != htons(ETH_P_IP))
987 skb_set_network_header(skb, ETH_HLEN);
988 if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
989 (skb->len < (ETH_HLEN +
990 (ip_hdr(skb)->ihl << 2) +
991 sizeof(struct udphdr)))) {
992 skb_reset_network_header(skb);
995 skb_set_transport_header(skb,
996 ETH_HLEN + (ip_hdr(skb)->ihl << 2));
997 csum = udp_hdr(skb)->check;
998 skb_reset_transport_header(skb);
999 skb_reset_network_header(skb);
1005 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
1007 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
1010 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
1011 == RXWBFLAG_TCPON)) {
1012 if (flags & RXWBFLAG_IPV4)
1013 netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1017 if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1018 == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1019 if (flags & RXWBFLAG_IPV4)
1020 netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1024 if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1025 == RXWBFLAG_IPV4)) {
1026 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1034 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1036 struct jme_ring *rxring = &(jme->rxring[0]);
1037 struct rxdesc *rxdesc = rxring->desc;
1038 struct jme_buffer_info *rxbi = rxring->bufinf;
1039 struct sk_buff *skb;
1046 pci_dma_sync_single_for_cpu(jme->pdev,
1049 PCI_DMA_FROMDEVICE);
1051 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1052 pci_dma_sync_single_for_device(jme->pdev,
1055 PCI_DMA_FROMDEVICE);
1057 ++(NET_STAT(jme).rx_dropped);
1059 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1062 skb_reserve(skb, RX_PREPAD_SIZE);
1063 skb_put(skb, framesize);
1064 skb->protocol = eth_type_trans(skb, jme->dev);
1066 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1067 skb->ip_summed = CHECKSUM_UNNECESSARY;
1069 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,36)
1070 skb->ip_summed = CHECKSUM_NONE;
1072 skb_checksum_none_assert(skb);
1075 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1077 jme->jme_vlan_rx(skb, jme->vlgrp,
1078 le16_to_cpu(rxdesc->descwb.vlan));
1079 NET_STAT(jme).rx_bytes += 4;
1087 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1088 cpu_to_le16(RXWBFLAG_DEST_MUL))
1089 ++(NET_STAT(jme).multicast);
1091 NET_STAT(jme).rx_bytes += framesize;
1092 ++(NET_STAT(jme).rx_packets);
1095 jme_set_clean_rxdesc(jme, idx);
1100 jme_process_receive(struct jme_adapter *jme, int limit)
1102 struct jme_ring *rxring = &(jme->rxring[0]);
1103 struct rxdesc *rxdesc = rxring->desc;
1104 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1106 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1109 if (unlikely(atomic_read(&jme->link_changing) != 1))
1112 if (unlikely(!netif_carrier_ok(jme->dev)))
1115 i = atomic_read(&rxring->next_to_clean);
1117 rxdesc = rxring->desc;
1120 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1121 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1126 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1128 if (unlikely(desccnt > 1 ||
1129 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1131 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1132 ++(NET_STAT(jme).rx_crc_errors);
1133 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1134 ++(NET_STAT(jme).rx_fifo_errors);
1136 ++(NET_STAT(jme).rx_errors);
1139 limit -= desccnt - 1;
1141 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1142 jme_set_clean_rxdesc(jme, j);
1143 j = (j + 1) & (mask);
1147 jme_alloc_and_feed_skb(jme, i);
1150 i = (i + desccnt) & (mask);
1154 atomic_set(&rxring->next_to_clean, i);
1157 atomic_inc(&jme->rx_cleaning);
1159 return limit > 0 ? limit : 0;
1164 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1166 if (likely(atmp == dpi->cur)) {
1171 if (dpi->attempt == atmp) {
1174 dpi->attempt = atmp;
1181 jme_dynamic_pcc(struct jme_adapter *jme)
1183 register struct dynpcc_info *dpi = &(jme->dpi);
1185 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1186 jme_attempt_pcc(dpi, PCC_P3);
1187 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1188 dpi->intr_cnt > PCC_INTR_THRESHOLD)
1189 jme_attempt_pcc(dpi, PCC_P2);
1191 jme_attempt_pcc(dpi, PCC_P1);
1193 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1194 if (dpi->attempt < dpi->cur)
1195 tasklet_schedule(&jme->rxclean_task);
1196 jme_set_rx_pcc(jme, dpi->attempt);
1197 dpi->cur = dpi->attempt;
1203 jme_start_pcc_timer(struct jme_adapter *jme)
1205 struct dynpcc_info *dpi = &(jme->dpi);
1206 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1207 dpi->last_pkts = NET_STAT(jme).rx_packets;
1209 jwrite32(jme, JME_TMCSR,
1210 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1214 jme_stop_pcc_timer(struct jme_adapter *jme)
1216 jwrite32(jme, JME_TMCSR, 0);
1220 jme_shutdown_nic(struct jme_adapter *jme)
1224 phylink = jme_linkstat_from_phy(jme);
1226 if (!(phylink & PHY_LINK_UP)) {
1228 * Disable all interrupt before issue timer
1231 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1236 jme_pcc_tasklet(unsigned long arg)
1238 struct jme_adapter *jme = (struct jme_adapter *)arg;
1239 struct net_device *netdev = jme->dev;
1241 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1242 jme_shutdown_nic(jme);
1246 if (unlikely(!netif_carrier_ok(netdev) ||
1247 (atomic_read(&jme->link_changing) != 1)
1249 jme_stop_pcc_timer(jme);
1253 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1254 jme_dynamic_pcc(jme);
1256 jme_start_pcc_timer(jme);
1260 jme_polling_mode(struct jme_adapter *jme)
1262 jme_set_rx_pcc(jme, PCC_OFF);
1266 jme_interrupt_mode(struct jme_adapter *jme)
1268 jme_set_rx_pcc(jme, PCC_P1);
1272 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1275 apmc = jread32(jme, JME_APMC);
1276 return apmc & JME_APMC_PSEUDO_HP_EN;
1280 jme_start_shutdown_timer(struct jme_adapter *jme)
1284 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1285 apmc &= ~JME_APMC_EPIEN_CTRL;
1287 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1290 jwrite32f(jme, JME_APMC, apmc);
1292 jwrite32f(jme, JME_TIMER2, 0);
1293 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1294 jwrite32(jme, JME_TMCSR,
1295 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1299 jme_stop_shutdown_timer(struct jme_adapter *jme)
1303 jwrite32f(jme, JME_TMCSR, 0);
1304 jwrite32f(jme, JME_TIMER2, 0);
1305 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1307 apmc = jread32(jme, JME_APMC);
1308 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1309 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1311 jwrite32f(jme, JME_APMC, apmc);
1315 jme_link_change_tasklet(unsigned long arg)
1317 struct jme_adapter *jme = (struct jme_adapter *)arg;
1318 struct net_device *netdev = jme->dev;
1321 while (!atomic_dec_and_test(&jme->link_changing)) {
1322 atomic_inc(&jme->link_changing);
1323 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1324 while (atomic_read(&jme->link_changing) != 1)
1325 netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1328 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1331 jme->old_mtu = netdev->mtu;
1332 netif_stop_queue(netdev);
1333 if (jme_pseudo_hotplug_enabled(jme))
1334 jme_stop_shutdown_timer(jme);
1336 jme_stop_pcc_timer(jme);
1337 tasklet_disable(&jme->txclean_task);
1338 tasklet_disable(&jme->rxclean_task);
1339 tasklet_disable(&jme->rxempty_task);
1341 if (netif_carrier_ok(netdev)) {
1342 jme_disable_rx_engine(jme);
1343 jme_disable_tx_engine(jme);
1344 jme_reset_mac_processor(jme);
1345 jme_free_rx_resources(jme);
1346 jme_free_tx_resources(jme);
1348 if (test_bit(JME_FLAG_POLL, &jme->flags))
1349 jme_polling_mode(jme);
1351 netif_carrier_off(netdev);
1354 jme_check_link(netdev, 0);
1355 if (netif_carrier_ok(netdev)) {
1356 rc = jme_setup_rx_resources(jme);
1358 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1359 goto out_enable_tasklet;
1362 rc = jme_setup_tx_resources(jme);
1364 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1365 goto err_out_free_rx_resources;
1368 jme_enable_rx_engine(jme);
1369 jme_enable_tx_engine(jme);
1371 netif_start_queue(netdev);
1373 if (test_bit(JME_FLAG_POLL, &jme->flags))
1374 jme_interrupt_mode(jme);
1376 jme_start_pcc_timer(jme);
1377 } else if (jme_pseudo_hotplug_enabled(jme)) {
1378 jme_start_shutdown_timer(jme);
1381 goto out_enable_tasklet;
1383 err_out_free_rx_resources:
1384 jme_free_rx_resources(jme);
1386 tasklet_enable(&jme->txclean_task);
1387 tasklet_hi_enable(&jme->rxclean_task);
1388 tasklet_hi_enable(&jme->rxempty_task);
1390 atomic_inc(&jme->link_changing);
1394 jme_rx_clean_tasklet(unsigned long arg)
1396 struct jme_adapter *jme = (struct jme_adapter *)arg;
1397 struct dynpcc_info *dpi = &(jme->dpi);
1399 jme_process_receive(jme, jme->rx_ring_size);
1405 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1407 struct jme_adapter *jme = jme_napi_priv(holder);
1411 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1413 while (atomic_read(&jme->rx_empty) > 0) {
1414 atomic_dec(&jme->rx_empty);
1415 ++(NET_STAT(jme).rx_dropped);
1416 jme_restart_rx_engine(jme);
1418 atomic_inc(&jme->rx_empty);
1421 JME_RX_COMPLETE(netdev, holder);
1422 jme_interrupt_mode(jme);
1425 JME_NAPI_WEIGHT_SET(budget, rest);
1426 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1430 jme_rx_empty_tasklet(unsigned long arg)
1432 struct jme_adapter *jme = (struct jme_adapter *)arg;
1434 if (unlikely(atomic_read(&jme->link_changing) != 1))
1437 if (unlikely(!netif_carrier_ok(jme->dev)))
1440 netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1442 jme_rx_clean_tasklet(arg);
1444 while (atomic_read(&jme->rx_empty) > 0) {
1445 atomic_dec(&jme->rx_empty);
1446 ++(NET_STAT(jme).rx_dropped);
1447 jme_restart_rx_engine(jme);
1449 atomic_inc(&jme->rx_empty);
1453 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1455 struct jme_ring *txring = &(jme->txring[0]);
1458 if (unlikely(netif_queue_stopped(jme->dev) &&
1459 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1460 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1461 netif_wake_queue(jme->dev);
1467 jme_tx_clean_tasklet(unsigned long arg)
1469 struct jme_adapter *jme = (struct jme_adapter *)arg;
1470 struct jme_ring *txring = &(jme->txring[0]);
1471 struct txdesc *txdesc = txring->desc;
1472 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1473 int i, j, cnt = 0, max, err, mask;
1475 tx_dbg(jme, "Into txclean\n");
1477 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1480 if (unlikely(atomic_read(&jme->link_changing) != 1))
1483 if (unlikely(!netif_carrier_ok(jme->dev)))
1486 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1487 mask = jme->tx_ring_mask;
1489 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1493 if (likely(ctxbi->skb &&
1494 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1496 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1497 i, ctxbi->nr_desc, jiffies);
1499 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1501 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1502 ttxbi = txbi + ((i + j) & (mask));
1503 txdesc[(i + j) & (mask)].dw[0] = 0;
1505 pci_unmap_page(jme->pdev,
1514 dev_kfree_skb(ctxbi->skb);
1516 cnt += ctxbi->nr_desc;
1518 if (unlikely(err)) {
1519 ++(NET_STAT(jme).tx_carrier_errors);
1521 ++(NET_STAT(jme).tx_packets);
1522 NET_STAT(jme).tx_bytes += ctxbi->len;
1527 ctxbi->start_xmit = 0;
1533 i = (i + ctxbi->nr_desc) & mask;
1538 tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1539 atomic_set(&txring->next_to_clean, i);
1540 atomic_add(cnt, &txring->nr_free);
1542 jme_wake_queue_if_stopped(jme);
1545 atomic_inc(&jme->tx_cleaning);
1549 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1554 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1556 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1558 * Link change event is critical
1559 * all other events are ignored
1561 jwrite32(jme, JME_IEVE, intrstat);
1562 tasklet_schedule(&jme->linkch_task);
1566 if (intrstat & INTR_TMINTR) {
1567 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1568 tasklet_schedule(&jme->pcc_task);
1571 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1572 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1573 tasklet_schedule(&jme->txclean_task);
1576 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1577 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1583 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1584 if (intrstat & INTR_RX0EMP)
1585 atomic_inc(&jme->rx_empty);
1587 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1588 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1589 jme_polling_mode(jme);
1590 JME_RX_SCHEDULE(jme);
1594 if (intrstat & INTR_RX0EMP) {
1595 atomic_inc(&jme->rx_empty);
1596 tasklet_hi_schedule(&jme->rxempty_task);
1597 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1598 tasklet_hi_schedule(&jme->rxclean_task);
1604 * Re-enable interrupt
1606 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1609 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1611 jme_intr(int irq, void *dev_id, struct pt_regs *regs)
1614 jme_intr(int irq, void *dev_id)
1617 struct net_device *netdev = dev_id;
1618 struct jme_adapter *jme = netdev_priv(netdev);
1621 intrstat = jread32(jme, JME_IEVE);
1624 * Check if it's really an interrupt for us
1626 if (unlikely((intrstat & INTR_ENABLE) == 0))
1630 * Check if the device still exist
1632 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1635 jme_intr_msi(jme, intrstat);
1640 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1642 jme_msi(int irq, void *dev_id, struct pt_regs *regs)
1645 jme_msi(int irq, void *dev_id)
1648 struct net_device *netdev = dev_id;
1649 struct jme_adapter *jme = netdev_priv(netdev);
1652 intrstat = jread32(jme, JME_IEVE);
1654 jme_intr_msi(jme, intrstat);
1660 jme_reset_link(struct jme_adapter *jme)
1662 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1666 jme_restart_an(struct jme_adapter *jme)
1670 spin_lock_bh(&jme->phy_lock);
1671 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1672 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1673 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1674 spin_unlock_bh(&jme->phy_lock);
1678 jme_request_irq(struct jme_adapter *jme)
1681 struct net_device *netdev = jme->dev;
1682 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
1683 irqreturn_t (*handler)(int, void *, struct pt_regs *) = jme_intr;
1684 int irq_flags = SA_SHIRQ;
1686 irq_handler_t handler = jme_intr;
1687 int irq_flags = IRQF_SHARED;
1690 if (!pci_enable_msi(jme->pdev)) {
1691 set_bit(JME_FLAG_MSI, &jme->flags);
1696 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1700 "Unable to request %s interrupt (return: %d)\n",
1701 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1704 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1705 pci_disable_msi(jme->pdev);
1706 clear_bit(JME_FLAG_MSI, &jme->flags);
1709 netdev->irq = jme->pdev->irq;
1716 jme_free_irq(struct jme_adapter *jme)
1718 free_irq(jme->pdev->irq, jme->dev);
1719 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1720 pci_disable_msi(jme->pdev);
1721 clear_bit(JME_FLAG_MSI, &jme->flags);
1722 jme->dev->irq = jme->pdev->irq;
1727 jme_new_phy_on(struct jme_adapter *jme)
1731 reg = jread32(jme, JME_PHY_PWR);
1732 reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1733 PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1734 jwrite32(jme, JME_PHY_PWR, reg);
1736 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1737 reg &= ~PE1_GPREG0_PBG;
1738 reg |= PE1_GPREG0_ENBG;
1739 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1743 jme_new_phy_off(struct jme_adapter *jme)
1747 reg = jread32(jme, JME_PHY_PWR);
1748 reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1749 PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1750 jwrite32(jme, JME_PHY_PWR, reg);
1752 pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, ®);
1753 reg &= ~PE1_GPREG0_PBG;
1754 reg |= PE1_GPREG0_PDD3COLD;
1755 pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1759 jme_phy_on(struct jme_adapter *jme)
1763 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1764 bmcr &= ~BMCR_PDOWN;
1765 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1767 if (new_phy_power_ctrl(jme->chip_main_rev))
1768 jme_new_phy_on(jme);
1772 jme_phy_off(struct jme_adapter *jme)
1776 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1778 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1780 if (new_phy_power_ctrl(jme->chip_main_rev))
1781 jme_new_phy_off(jme);
1785 jme_open(struct net_device *netdev)
1787 struct jme_adapter *jme = netdev_priv(netdev);
1791 JME_NAPI_ENABLE(jme);
1793 tasklet_enable(&jme->linkch_task);
1794 tasklet_enable(&jme->txclean_task);
1795 tasklet_hi_enable(&jme->rxclean_task);
1796 tasklet_hi_enable(&jme->rxempty_task);
1798 rc = jme_request_irq(jme);
1805 if (test_bit(JME_FLAG_SSET, &jme->flags))
1806 jme_set_settings(netdev, &jme->old_ecmd);
1808 jme_reset_phy_processor(jme);
1810 jme_reset_link(jme);
1815 netif_stop_queue(netdev);
1816 netif_carrier_off(netdev);
1821 jme_set_100m_half(struct jme_adapter *jme)
1826 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1827 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1828 BMCR_SPEED1000 | BMCR_FULLDPLX);
1829 tmp |= BMCR_SPEED100;
1832 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1835 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1837 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1840 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1842 jme_wait_link(struct jme_adapter *jme)
1844 u32 phylink, to = JME_WAIT_LINK_TIME;
1847 phylink = jme_linkstat_from_phy(jme);
1848 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1850 phylink = jme_linkstat_from_phy(jme);
1855 jme_powersave_phy(struct jme_adapter *jme)
1857 if (jme->reg_pmcs) {
1858 jme_set_100m_half(jme);
1859 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1868 jme_close(struct net_device *netdev)
1870 struct jme_adapter *jme = netdev_priv(netdev);
1872 netif_stop_queue(netdev);
1873 netif_carrier_off(netdev);
1878 JME_NAPI_DISABLE(jme);
1880 tasklet_disable(&jme->linkch_task);
1881 tasklet_disable(&jme->txclean_task);
1882 tasklet_disable(&jme->rxclean_task);
1883 tasklet_disable(&jme->rxempty_task);
1885 jme_disable_rx_engine(jme);
1886 jme_disable_tx_engine(jme);
1887 jme_reset_mac_processor(jme);
1888 jme_free_rx_resources(jme);
1889 jme_free_tx_resources(jme);
1897 jme_alloc_txdesc(struct jme_adapter *jme,
1898 struct sk_buff *skb)
1900 struct jme_ring *txring = &(jme->txring[0]);
1901 int idx, nr_alloc, mask = jme->tx_ring_mask;
1903 idx = txring->next_to_use;
1904 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1906 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1909 atomic_sub(nr_alloc, &txring->nr_free);
1911 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1917 jme_fill_tx_map(struct pci_dev *pdev,
1918 struct txdesc *txdesc,
1919 struct jme_buffer_info *txbi,
1927 dmaaddr = pci_map_page(pdev,
1933 pci_dma_sync_single_for_device(pdev,
1940 txdesc->desc2.flags = TXFLAG_OWN;
1941 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1942 txdesc->desc2.datalen = cpu_to_le16(len);
1943 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1944 txdesc->desc2.bufaddrl = cpu_to_le32(
1945 (__u64)dmaaddr & 0xFFFFFFFFUL);
1947 txbi->mapping = dmaaddr;
1952 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1954 struct jme_ring *txring = &(jme->txring[0]);
1955 struct txdesc *txdesc = txring->desc, *ctxdesc;
1956 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1957 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1958 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1959 int mask = jme->tx_ring_mask;
1960 struct skb_frag_struct *frag;
1963 for (i = 0 ; i < nr_frags ; ++i) {
1964 frag = &skb_shinfo(skb)->frags[i];
1965 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1966 ctxbi = txbi + ((idx + i + 2) & (mask));
1968 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1969 frag->page_offset, frag->size, hidma);
1972 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1973 ctxdesc = txdesc + ((idx + 1) & (mask));
1974 ctxbi = txbi + ((idx + 1) & (mask));
1975 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1976 offset_in_page(skb->data), len, hidma);
1981 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1984 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
1985 skb_shinfo(skb)->tso_size
1987 skb_shinfo(skb)->gso_size
1989 && skb_header_cloned(skb) &&
1990 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1999 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
2001 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17)
2002 *mss = cpu_to_le16(skb_shinfo(skb)->tso_size << TXDESC_MSS_SHIFT);
2004 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
2007 *flags |= TXFLAG_LSEN;
2009 if (skb->protocol == htons(ETH_P_IP)) {
2010 struct iphdr *iph = ip_hdr(skb);
2013 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2018 struct ipv6hdr *ip6h = ipv6_hdr(skb);
2020 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
2033 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
2035 #ifdef CHECKSUM_PARTIAL
2036 if (skb->ip_summed == CHECKSUM_PARTIAL)
2038 if (skb->ip_summed == CHECKSUM_HW)
2043 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2044 if (skb->protocol == htons(ETH_P_IP))
2045 ip_proto = ip_hdr(skb)->protocol;
2046 else if (skb->protocol == htons(ETH_P_IPV6))
2047 ip_proto = ipv6_hdr(skb)->nexthdr;
2051 switch (skb->protocol) {
2052 case htons(ETH_P_IP):
2053 ip_proto = ip_hdr(skb)->protocol;
2055 case htons(ETH_P_IPV6):
2056 ip_proto = ipv6_hdr(skb)->nexthdr;
2066 *flags |= TXFLAG_TCPCS;
2069 *flags |= TXFLAG_UDPCS;
2072 netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2079 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2081 if (vlan_tx_tag_present(skb)) {
2082 *flags |= TXFLAG_TAGON;
2083 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2088 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2090 struct jme_ring *txring = &(jme->txring[0]);
2091 struct txdesc *txdesc;
2092 struct jme_buffer_info *txbi;
2095 txdesc = (struct txdesc *)txring->desc + idx;
2096 txbi = txring->bufinf + idx;
2102 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2104 * Set OWN bit at final.
2105 * When kernel transmit faster than NIC.
2106 * And NIC trying to send this descriptor before we tell
2107 * it to start sending this TX queue.
2108 * Other fields are already filled correctly.
2111 flags = TXFLAG_OWN | TXFLAG_INT;
2113 * Set checksum flags while not tso
2115 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2116 jme_tx_csum(jme, skb, &flags);
2117 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2118 jme_map_tx_skb(jme, skb, idx);
2119 txdesc->desc1.flags = flags;
2121 * Set tx buffer info after telling NIC to send
2122 * For better tx_clean timing
2125 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2127 txbi->len = skb->len;
2128 txbi->start_xmit = jiffies;
2129 if (!txbi->start_xmit)
2130 txbi->start_xmit = (0UL-1);
2136 jme_stop_queue_if_full(struct jme_adapter *jme)
2138 struct jme_ring *txring = &(jme->txring[0]);
2139 struct jme_buffer_info *txbi = txring->bufinf;
2140 int idx = atomic_read(&txring->next_to_clean);
2145 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2146 netif_stop_queue(jme->dev);
2147 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2149 if (atomic_read(&txring->nr_free)
2150 >= (jme->tx_wake_threshold)) {
2151 netif_wake_queue(jme->dev);
2152 netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2156 if (unlikely(txbi->start_xmit &&
2157 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2159 netif_stop_queue(jme->dev);
2160 netif_info(jme, tx_queued, jme->dev,
2161 "TX Queue Stopped %d@%lu\n", idx, jiffies);
2166 * This function is already protected by netif_tx_lock()
2169 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,31)
2174 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2176 struct jme_adapter *jme = netdev_priv(netdev);
2179 if (unlikely(jme_expand_header(jme, skb))) {
2180 ++(NET_STAT(jme).tx_dropped);
2181 return NETDEV_TX_OK;
2184 idx = jme_alloc_txdesc(jme, skb);
2186 if (unlikely(idx < 0)) {
2187 netif_stop_queue(netdev);
2188 netif_err(jme, tx_err, jme->dev,
2189 "BUG! Tx ring full when queue awake!\n");
2191 return NETDEV_TX_BUSY;
2194 jme_fill_tx_desc(jme, skb, idx);
2196 jwrite32(jme, JME_TXCS, jme->reg_txcs |
2197 TXCS_SELECT_QUEUE0 |
2200 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,29)
2201 netdev->trans_start = jiffies;
2204 tx_dbg(jme, "xmit: %d+%d@%lu\n",
2205 idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2206 jme_stop_queue_if_full(jme);
2208 return NETDEV_TX_OK;
2212 jme_set_unicastaddr(struct net_device *netdev)
2214 struct jme_adapter *jme = netdev_priv(netdev);
2217 val = (netdev->dev_addr[3] & 0xff) << 24 |
2218 (netdev->dev_addr[2] & 0xff) << 16 |
2219 (netdev->dev_addr[1] & 0xff) << 8 |
2220 (netdev->dev_addr[0] & 0xff);
2221 jwrite32(jme, JME_RXUMA_LO, val);
2222 val = (netdev->dev_addr[5] & 0xff) << 8 |
2223 (netdev->dev_addr[4] & 0xff);
2224 jwrite32(jme, JME_RXUMA_HI, val);
2228 jme_set_macaddr(struct net_device *netdev, void *p)
2230 struct jme_adapter *jme = netdev_priv(netdev);
2231 struct sockaddr *addr = p;
2233 if (netif_running(netdev))
2236 spin_lock_bh(&jme->macaddr_lock);
2237 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2238 jme_set_unicastaddr(netdev);
2239 spin_unlock_bh(&jme->macaddr_lock);
2245 jme_set_multi(struct net_device *netdev)
2247 struct jme_adapter *jme = netdev_priv(netdev);
2248 u32 mc_hash[2] = {};
2249 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2253 spin_lock_bh(&jme->rxmcs_lock);
2255 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2257 if (netdev->flags & IFF_PROMISC) {
2258 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2259 } else if (netdev->flags & IFF_ALLMULTI) {
2260 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2261 } else if (netdev->flags & IFF_MULTICAST) {
2262 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2263 struct dev_mc_list *mclist;
2265 struct netdev_hw_addr *ha;
2269 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2270 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,33)
2271 for (i = 0, mclist = netdev->mc_list;
2272 mclist && i < netdev->mc_count;
2273 ++i, mclist = mclist->next) {
2274 #elif LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2275 netdev_for_each_mc_addr(mclist, netdev) {
2277 netdev_for_each_mc_addr(ha, netdev) {
2279 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,34)
2280 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2282 bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2284 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2287 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2288 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2292 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2294 spin_unlock_bh(&jme->rxmcs_lock);
2298 jme_change_mtu(struct net_device *netdev, int new_mtu)
2300 struct jme_adapter *jme = netdev_priv(netdev);
2302 if (new_mtu == jme->old_mtu)
2305 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2306 ((new_mtu) < IPV6_MIN_MTU))
2309 if (new_mtu > 4000) {
2310 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2311 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2312 jme_restart_rx_engine(jme);
2314 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2315 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2316 jme_restart_rx_engine(jme);
2319 if (new_mtu > 1900) {
2320 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2321 NETIF_F_TSO | NETIF_F_TSO6);
2323 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2324 netdev->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2325 if (test_bit(JME_FLAG_TSO, &jme->flags))
2326 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2329 netdev->mtu = new_mtu;
2330 jme_reset_link(jme);
2336 jme_tx_timeout(struct net_device *netdev)
2338 struct jme_adapter *jme = netdev_priv(netdev);
2341 jme_reset_phy_processor(jme);
2342 if (test_bit(JME_FLAG_SSET, &jme->flags))
2343 jme_set_settings(netdev, &jme->old_ecmd);
2346 * Force to Reset the link again
2348 jme_reset_link(jme);
2351 static inline void jme_pause_rx(struct jme_adapter *jme)
2353 atomic_dec(&jme->link_changing);
2355 jme_set_rx_pcc(jme, PCC_OFF);
2356 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2357 JME_NAPI_DISABLE(jme);
2359 tasklet_disable(&jme->rxclean_task);
2360 tasklet_disable(&jme->rxempty_task);
2364 static inline void jme_resume_rx(struct jme_adapter *jme)
2366 struct dynpcc_info *dpi = &(jme->dpi);
2368 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2369 JME_NAPI_ENABLE(jme);
2371 tasklet_hi_enable(&jme->rxclean_task);
2372 tasklet_hi_enable(&jme->rxempty_task);
2375 dpi->attempt = PCC_P1;
2377 jme_set_rx_pcc(jme, PCC_P1);
2379 atomic_inc(&jme->link_changing);
2383 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2385 struct jme_adapter *jme = netdev_priv(netdev);
2392 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
2394 jme_vlan_rx_kill_vid(struct net_device *netdev, unsigned short vid)
2396 struct jme_adapter *jme = netdev_priv(netdev);
2400 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,20)
2401 jme->vlgrp->vlan_devices[vid] = NULL;
2403 vlan_group_set_device(jme->vlgrp, vid, NULL);
2411 jme_get_drvinfo(struct net_device *netdev,
2412 struct ethtool_drvinfo *info)
2414 struct jme_adapter *jme = netdev_priv(netdev);
2416 strcpy(info->driver, DRV_NAME);
2417 strcpy(info->version, DRV_VERSION);
2418 strcpy(info->bus_info, pci_name(jme->pdev));
2422 jme_get_regs_len(struct net_device *netdev)
2428 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2432 for (i = 0 ; i < len ; i += 4)
2433 p[i >> 2] = jread32(jme, reg + i);
2437 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2440 u16 *p16 = (u16 *)p;
2442 for (i = 0 ; i < reg_nr ; ++i)
2443 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2447 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2449 struct jme_adapter *jme = netdev_priv(netdev);
2450 u32 *p32 = (u32 *)p;
2452 memset(p, 0xFF, JME_REG_LEN);
2455 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2458 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2461 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2464 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2467 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2471 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2473 struct jme_adapter *jme = netdev_priv(netdev);
2475 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2476 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2478 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2479 ecmd->use_adaptive_rx_coalesce = false;
2480 ecmd->rx_coalesce_usecs = 0;
2481 ecmd->rx_max_coalesced_frames = 0;
2485 ecmd->use_adaptive_rx_coalesce = true;
2487 switch (jme->dpi.cur) {
2489 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2490 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2493 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2494 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2497 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2498 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2508 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2510 struct jme_adapter *jme = netdev_priv(netdev);
2511 struct dynpcc_info *dpi = &(jme->dpi);
2513 if (netif_running(netdev))
2516 if (ecmd->use_adaptive_rx_coalesce &&
2517 test_bit(JME_FLAG_POLL, &jme->flags)) {
2518 clear_bit(JME_FLAG_POLL, &jme->flags);
2519 jme->jme_rx = netif_rx;
2520 jme->jme_vlan_rx = vlan_hwaccel_rx;
2522 dpi->attempt = PCC_P1;
2524 jme_set_rx_pcc(jme, PCC_P1);
2525 jme_interrupt_mode(jme);
2526 } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2527 !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2528 set_bit(JME_FLAG_POLL, &jme->flags);
2529 jme->jme_rx = netif_receive_skb;
2530 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2531 jme_interrupt_mode(jme);
2538 jme_get_pauseparam(struct net_device *netdev,
2539 struct ethtool_pauseparam *ecmd)
2541 struct jme_adapter *jme = netdev_priv(netdev);
2544 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2545 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2547 spin_lock_bh(&jme->phy_lock);
2548 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2549 spin_unlock_bh(&jme->phy_lock);
2552 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2556 jme_set_pauseparam(struct net_device *netdev,
2557 struct ethtool_pauseparam *ecmd)
2559 struct jme_adapter *jme = netdev_priv(netdev);
2562 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2563 (ecmd->tx_pause != 0)) {
2566 jme->reg_txpfc |= TXPFC_PF_EN;
2568 jme->reg_txpfc &= ~TXPFC_PF_EN;
2570 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2573 spin_lock_bh(&jme->rxmcs_lock);
2574 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2575 (ecmd->rx_pause != 0)) {
2578 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2580 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2582 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2584 spin_unlock_bh(&jme->rxmcs_lock);
2586 spin_lock_bh(&jme->phy_lock);
2587 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2588 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2589 (ecmd->autoneg != 0)) {
2592 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2594 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2596 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2597 MII_ADVERTISE, val);
2599 spin_unlock_bh(&jme->phy_lock);
2605 jme_get_wol(struct net_device *netdev,
2606 struct ethtool_wolinfo *wol)
2608 struct jme_adapter *jme = netdev_priv(netdev);
2610 wol->supported = WAKE_MAGIC | WAKE_PHY;
2614 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2615 wol->wolopts |= WAKE_PHY;
2617 if (jme->reg_pmcs & PMCS_MFEN)
2618 wol->wolopts |= WAKE_MAGIC;
2623 jme_set_wol(struct net_device *netdev,
2624 struct ethtool_wolinfo *wol)
2626 struct jme_adapter *jme = netdev_priv(netdev);
2628 if (wol->wolopts & (WAKE_MAGICSECURE |
2637 if (wol->wolopts & WAKE_PHY)
2638 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2640 if (wol->wolopts & WAKE_MAGIC)
2641 jme->reg_pmcs |= PMCS_MFEN;
2643 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2644 #ifndef JME_NEW_PM_API
2645 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
2647 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
2648 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2655 jme_get_settings(struct net_device *netdev,
2656 struct ethtool_cmd *ecmd)
2658 struct jme_adapter *jme = netdev_priv(netdev);
2661 spin_lock_bh(&jme->phy_lock);
2662 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2663 spin_unlock_bh(&jme->phy_lock);
2668 jme_set_settings(struct net_device *netdev,
2669 struct ethtool_cmd *ecmd)
2671 struct jme_adapter *jme = netdev_priv(netdev);
2674 if (ethtool_cmd_speed(ecmd) == SPEED_1000
2675 && ecmd->autoneg != AUTONEG_ENABLE)
2679 * Check If user changed duplex only while force_media.
2680 * Hardware would not generate link change interrupt.
2682 if (jme->mii_if.force_media &&
2683 ecmd->autoneg != AUTONEG_ENABLE &&
2684 (jme->mii_if.full_duplex != ecmd->duplex))
2687 spin_lock_bh(&jme->phy_lock);
2688 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2689 spin_unlock_bh(&jme->phy_lock);
2693 jme_reset_link(jme);
2694 jme->old_ecmd = *ecmd;
2695 set_bit(JME_FLAG_SSET, &jme->flags);
2702 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2705 struct jme_adapter *jme = netdev_priv(netdev);
2706 struct mii_ioctl_data *mii_data = if_mii(rq);
2707 unsigned int duplex_chg;
2709 if (cmd == SIOCSMIIREG) {
2710 u16 val = mii_data->val_in;
2711 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2712 (val & BMCR_SPEED1000))
2716 spin_lock_bh(&jme->phy_lock);
2717 rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2718 spin_unlock_bh(&jme->phy_lock);
2720 if (!rc && (cmd == SIOCSMIIREG)) {
2722 jme_reset_link(jme);
2723 jme_get_settings(netdev, &jme->old_ecmd);
2724 set_bit(JME_FLAG_SSET, &jme->flags);
2731 jme_get_link(struct net_device *netdev)
2733 struct jme_adapter *jme = netdev_priv(netdev);
2734 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2738 jme_get_msglevel(struct net_device *netdev)
2740 struct jme_adapter *jme = netdev_priv(netdev);
2741 return jme->msg_enable;
2745 jme_set_msglevel(struct net_device *netdev, u32 value)
2747 struct jme_adapter *jme = netdev_priv(netdev);
2748 jme->msg_enable = value;
2752 jme_get_rx_csum(struct net_device *netdev)
2754 struct jme_adapter *jme = netdev_priv(netdev);
2755 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2759 jme_set_rx_csum(struct net_device *netdev, u32 on)
2761 struct jme_adapter *jme = netdev_priv(netdev);
2763 spin_lock_bh(&jme->rxmcs_lock);
2765 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2767 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2768 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2769 spin_unlock_bh(&jme->rxmcs_lock);
2775 jme_set_tx_csum(struct net_device *netdev, u32 on)
2777 struct jme_adapter *jme = netdev_priv(netdev);
2780 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2781 if (netdev->mtu <= 1900)
2783 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2785 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2787 ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
2794 jme_set_tso(struct net_device *netdev, u32 on)
2796 struct jme_adapter *jme = netdev_priv(netdev);
2799 set_bit(JME_FLAG_TSO, &jme->flags);
2800 if (netdev->mtu <= 1900)
2801 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2803 clear_bit(JME_FLAG_TSO, &jme->flags);
2804 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2811 jme_nway_reset(struct net_device *netdev)
2813 struct jme_adapter *jme = netdev_priv(netdev);
2814 jme_restart_an(jme);
2819 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2824 val = jread32(jme, JME_SMBCSR);
2825 to = JME_SMB_BUSY_TIMEOUT;
2826 while ((val & SMBCSR_BUSY) && --to) {
2828 val = jread32(jme, JME_SMBCSR);
2831 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2835 jwrite32(jme, JME_SMBINTF,
2836 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2837 SMBINTF_HWRWN_READ |
2840 val = jread32(jme, JME_SMBINTF);
2841 to = JME_SMB_BUSY_TIMEOUT;
2842 while ((val & SMBINTF_HWCMD) && --to) {
2844 val = jread32(jme, JME_SMBINTF);
2847 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2851 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2855 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2860 val = jread32(jme, JME_SMBCSR);
2861 to = JME_SMB_BUSY_TIMEOUT;
2862 while ((val & SMBCSR_BUSY) && --to) {
2864 val = jread32(jme, JME_SMBCSR);
2867 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2871 jwrite32(jme, JME_SMBINTF,
2872 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2873 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2874 SMBINTF_HWRWN_WRITE |
2877 val = jread32(jme, JME_SMBINTF);
2878 to = JME_SMB_BUSY_TIMEOUT;
2879 while ((val & SMBINTF_HWCMD) && --to) {
2881 val = jread32(jme, JME_SMBINTF);
2884 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2892 jme_get_eeprom_len(struct net_device *netdev)
2894 struct jme_adapter *jme = netdev_priv(netdev);
2896 val = jread32(jme, JME_SMBCSR);
2897 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2901 jme_get_eeprom(struct net_device *netdev,
2902 struct ethtool_eeprom *eeprom, u8 *data)
2904 struct jme_adapter *jme = netdev_priv(netdev);
2905 int i, offset = eeprom->offset, len = eeprom->len;
2908 * ethtool will check the boundary for us
2910 eeprom->magic = JME_EEPROM_MAGIC;
2911 for (i = 0 ; i < len ; ++i)
2912 data[i] = jme_smb_read(jme, i + offset);
2918 jme_set_eeprom(struct net_device *netdev,
2919 struct ethtool_eeprom *eeprom, u8 *data)
2921 struct jme_adapter *jme = netdev_priv(netdev);
2922 int i, offset = eeprom->offset, len = eeprom->len;
2924 if (eeprom->magic != JME_EEPROM_MAGIC)
2928 * ethtool will check the boundary for us
2930 for (i = 0 ; i < len ; ++i)
2931 jme_smb_write(jme, i + offset, data[i]);
2936 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,18)
2937 static struct ethtool_ops jme_ethtool_ops = {
2939 static const struct ethtool_ops jme_ethtool_ops = {
2941 .get_drvinfo = jme_get_drvinfo,
2942 .get_regs_len = jme_get_regs_len,
2943 .get_regs = jme_get_regs,
2944 .get_coalesce = jme_get_coalesce,
2945 .set_coalesce = jme_set_coalesce,
2946 .get_pauseparam = jme_get_pauseparam,
2947 .set_pauseparam = jme_set_pauseparam,
2948 .get_wol = jme_get_wol,
2949 .set_wol = jme_set_wol,
2950 .get_settings = jme_get_settings,
2951 .set_settings = jme_set_settings,
2952 .get_link = jme_get_link,
2953 .get_msglevel = jme_get_msglevel,
2954 .set_msglevel = jme_set_msglevel,
2955 .get_rx_csum = jme_get_rx_csum,
2956 .set_rx_csum = jme_set_rx_csum,
2957 .set_tx_csum = jme_set_tx_csum,
2958 .set_tso = jme_set_tso,
2959 .set_sg = ethtool_op_set_sg,
2960 .nway_reset = jme_nway_reset,
2961 .get_eeprom_len = jme_get_eeprom_len,
2962 .get_eeprom = jme_get_eeprom,
2963 .set_eeprom = jme_set_eeprom,
2967 jme_pci_dma64(struct pci_dev *pdev)
2969 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2970 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2971 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2973 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)
2976 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2977 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2979 if (!pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
2983 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2984 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2985 !pci_set_dma_mask(pdev, DMA_BIT_MASK(40))
2987 !pci_set_dma_mask(pdev, DMA_40BIT_MASK)
2990 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2991 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2993 if (!pci_set_consistent_dma_mask(pdev, DMA_40BIT_MASK))
2997 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
2998 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2999 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
3001 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
3002 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
3010 jme_phy_init(struct jme_adapter *jme)
3014 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
3015 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
3019 jme_check_hw_ver(struct jme_adapter *jme)
3023 chipmode = jread32(jme, JME_CHIPMODE);
3025 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
3026 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
3027 jme->chip_main_rev = jme->chiprev & 0xF;
3028 jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
3031 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3032 static const struct net_device_ops jme_netdev_ops = {
3033 .ndo_open = jme_open,
3034 .ndo_stop = jme_close,
3035 .ndo_validate_addr = eth_validate_addr,
3036 .ndo_do_ioctl = jme_ioctl,
3037 .ndo_start_xmit = jme_start_xmit,
3038 .ndo_set_mac_address = jme_set_macaddr,
3039 .ndo_set_multicast_list = jme_set_multi,
3040 .ndo_change_mtu = jme_change_mtu,
3041 .ndo_tx_timeout = jme_tx_timeout,
3042 .ndo_vlan_rx_register = jme_vlan_rx_register,
3046 static int __devinit
3047 jme_init_one(struct pci_dev *pdev,
3048 const struct pci_device_id *ent)
3050 int rc = 0, using_dac, i;
3051 struct net_device *netdev;
3052 struct jme_adapter *jme;
3057 * set up PCI device basics
3059 rc = pci_enable_device(pdev);
3061 pr_err("Cannot enable PCI device\n");
3065 using_dac = jme_pci_dma64(pdev);
3066 if (using_dac < 0) {
3067 pr_err("Cannot set PCI DMA Mask\n");
3069 goto err_out_disable_pdev;
3072 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3073 pr_err("No PCI resource region found\n");
3075 goto err_out_disable_pdev;
3078 rc = pci_request_regions(pdev, DRV_NAME);
3080 pr_err("Cannot obtain PCI resource region\n");
3081 goto err_out_disable_pdev;
3084 pci_set_master(pdev);
3087 * alloc and init net device
3089 netdev = alloc_etherdev(sizeof(*jme));
3091 pr_err("Cannot allocate netdev structure\n");
3093 goto err_out_release_regions;
3095 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29)
3096 netdev->netdev_ops = &jme_netdev_ops;
3098 netdev->open = jme_open;
3099 netdev->stop = jme_close;
3100 netdev->do_ioctl = jme_ioctl;
3101 netdev->hard_start_xmit = jme_start_xmit;
3102 netdev->set_mac_address = jme_set_macaddr;
3103 netdev->set_multicast_list = jme_set_multi;
3104 netdev->change_mtu = jme_change_mtu;
3105 netdev->tx_timeout = jme_tx_timeout;
3106 netdev->vlan_rx_register = jme_vlan_rx_register;
3107 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
3108 netdev->vlan_rx_kill_vid = jme_vlan_rx_kill_vid;
3110 NETDEV_GET_STATS(netdev, &jme_get_stats);
3112 netdev->ethtool_ops = &jme_ethtool_ops;
3113 netdev->watchdog_timeo = TX_TIMEOUT;
3114 netdev->features = NETIF_F_IP_CSUM |
3119 NETIF_F_HW_VLAN_TX |
3122 netdev->features |= NETIF_F_HIGHDMA;
3124 SET_NETDEV_DEV(netdev, &pdev->dev);
3125 pci_set_drvdata(pdev, netdev);
3130 jme = netdev_priv(netdev);
3133 jme->jme_rx = netif_rx;
3134 jme->jme_vlan_rx = vlan_hwaccel_rx;
3135 jme->old_mtu = netdev->mtu = 1500;
3137 jme->tx_ring_size = 1 << 10;
3138 jme->tx_ring_mask = jme->tx_ring_size - 1;
3139 jme->tx_wake_threshold = 1 << 9;
3140 jme->rx_ring_size = 1 << 9;
3141 jme->rx_ring_mask = jme->rx_ring_size - 1;
3142 jme->msg_enable = JME_DEF_MSG_ENABLE;
3143 jme->regs = ioremap(pci_resource_start(pdev, 0),
3144 pci_resource_len(pdev, 0));
3146 pr_err("Mapping PCI resource region error\n");
3148 goto err_out_free_netdev;
3152 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
3153 jwrite32(jme, JME_APMC, apmc);
3154 } else if (force_pseudohp) {
3155 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
3156 jwrite32(jme, JME_APMC, apmc);
3159 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
3161 spin_lock_init(&jme->phy_lock);
3162 spin_lock_init(&jme->macaddr_lock);
3163 spin_lock_init(&jme->rxmcs_lock);
3165 atomic_set(&jme->link_changing, 1);
3166 atomic_set(&jme->rx_cleaning, 1);
3167 atomic_set(&jme->tx_cleaning, 1);
3168 atomic_set(&jme->rx_empty, 1);
3170 tasklet_init(&jme->pcc_task,
3172 (unsigned long) jme);
3173 tasklet_init(&jme->linkch_task,
3174 jme_link_change_tasklet,
3175 (unsigned long) jme);
3176 tasklet_init(&jme->txclean_task,
3177 jme_tx_clean_tasklet,
3178 (unsigned long) jme);
3179 tasklet_init(&jme->rxclean_task,
3180 jme_rx_clean_tasklet,
3181 (unsigned long) jme);
3182 tasklet_init(&jme->rxempty_task,
3183 jme_rx_empty_tasklet,
3184 (unsigned long) jme);
3185 tasklet_disable_nosync(&jme->linkch_task);
3186 tasklet_disable_nosync(&jme->txclean_task);
3187 tasklet_disable_nosync(&jme->rxclean_task);
3188 tasklet_disable_nosync(&jme->rxempty_task);
3189 jme->dpi.cur = PCC_P1;
3192 jme->reg_rxcs = RXCS_DEFAULT;
3193 jme->reg_rxmcs = RXMCS_DEFAULT;
3195 jme->reg_pmcs = PMCS_MFEN;
3196 jme->reg_gpreg1 = GPREG1_DEFAULT;
3197 set_bit(JME_FLAG_TXCSUM, &jme->flags);
3198 set_bit(JME_FLAG_TSO, &jme->flags);
3201 * Get Max Read Req Size from PCI Config Space
3203 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3204 jme->mrrs &= PCI_DCSR_MRRS_MASK;
3205 switch (jme->mrrs) {
3207 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3210 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3213 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3218 * Must check before reset_mac_processor
3220 jme_check_hw_ver(jme);
3221 jme->mii_if.dev = netdev;
3223 jme->mii_if.phy_id = 0;
3224 for (i = 1 ; i < 32 ; ++i) {
3225 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3226 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3227 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3228 jme->mii_if.phy_id = i;
3233 if (!jme->mii_if.phy_id) {
3235 pr_err("Can not find phy_id\n");
3239 jme->reg_ghc |= GHC_LINK_POLL;
3241 jme->mii_if.phy_id = 1;
3243 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3244 jme->mii_if.supports_gmii = true;
3246 jme->mii_if.supports_gmii = false;
3247 jme->mii_if.phy_id_mask = 0x1F;
3248 jme->mii_if.reg_num_mask = 0x1F;
3249 jme->mii_if.mdio_read = jme_mdio_read;
3250 jme->mii_if.mdio_write = jme_mdio_write;
3253 pci_set_power_state(jme->pdev, PCI_D0);
3254 #ifndef JME_NEW_PM_API
3255 jme_pci_wakeup_enable(jme, true);
3257 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3258 device_set_wakeup_enable(&pdev->dev, true);
3261 jme_set_phyfifo_5level(jme);
3262 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,22)
3263 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->pcirev);
3265 jme->pcirev = pdev->revision;
3272 * Reset MAC processor and reload EEPROM for MAC Address
3274 jme_reset_mac_processor(jme);
3275 rc = jme_reload_eeprom(jme);
3277 pr_err("Reload eeprom for reading MAC Address error\n");
3280 jme_load_macaddr(netdev);
3283 * Tell stack that we are not ready to work until open()
3285 netif_carrier_off(netdev);
3287 rc = register_netdev(netdev);
3289 pr_err("Cannot register net device\n");
3293 netif_info(jme, probe, jme->dev, "%s%s chipver:%x pcirev:%x "
3294 "macaddr: %02x:%02x:%02x:%02x:%02x:%02x\n",
3295 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3296 "JMC250 Gigabit Ethernet" :
3297 (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3298 "JMC260 Fast Ethernet" : "Unknown",
3299 (jme->fpgaver != 0) ? " (FPGA)" : "",
3300 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3302 netdev->dev_addr[0],
3303 netdev->dev_addr[1],
3304 netdev->dev_addr[2],
3305 netdev->dev_addr[3],
3306 netdev->dev_addr[4],
3307 netdev->dev_addr[5]);
3313 err_out_free_netdev:
3314 pci_set_drvdata(pdev, NULL);
3315 free_netdev(netdev);
3316 err_out_release_regions:
3317 pci_release_regions(pdev);
3318 err_out_disable_pdev:
3319 pci_disable_device(pdev);
3324 static void __devexit
3325 jme_remove_one(struct pci_dev *pdev)
3327 struct net_device *netdev = pci_get_drvdata(pdev);
3328 struct jme_adapter *jme = netdev_priv(netdev);
3330 unregister_netdev(netdev);
3332 pci_set_drvdata(pdev, NULL);
3333 free_netdev(netdev);
3334 pci_release_regions(pdev);
3335 pci_disable_device(pdev);
3340 jme_shutdown(struct pci_dev *pdev)
3342 struct net_device *netdev = pci_get_drvdata(pdev);
3343 struct jme_adapter *jme = netdev_priv(netdev);
3345 jme_powersave_phy(jme);
3346 #ifndef JME_NEW_PM_API
3347 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3349 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
3350 device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
3354 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
3359 #ifdef CONFIG_PM_SLEEP
3366 #ifdef JME_NEW_PM_API
3367 jme_suspend(struct device *dev)
3369 jme_suspend(struct pci_dev *pdev, pm_message_t state)
3372 #ifdef JME_NEW_PM_API
3373 struct pci_dev *pdev = to_pci_dev(dev);
3375 struct net_device *netdev = pci_get_drvdata(pdev);
3376 struct jme_adapter *jme = netdev_priv(netdev);
3378 atomic_dec(&jme->link_changing);
3380 netif_device_detach(netdev);
3381 netif_stop_queue(netdev);
3384 tasklet_disable(&jme->txclean_task);
3385 tasklet_disable(&jme->rxclean_task);
3386 tasklet_disable(&jme->rxempty_task);
3388 if (netif_carrier_ok(netdev)) {
3389 if (test_bit(JME_FLAG_POLL, &jme->flags))
3390 jme_polling_mode(jme);
3392 jme_stop_pcc_timer(jme);
3393 jme_disable_rx_engine(jme);
3394 jme_disable_tx_engine(jme);
3395 jme_reset_mac_processor(jme);
3396 jme_free_rx_resources(jme);
3397 jme_free_tx_resources(jme);
3398 netif_carrier_off(netdev);
3402 tasklet_enable(&jme->txclean_task);
3403 tasklet_hi_enable(&jme->rxclean_task);
3404 tasklet_hi_enable(&jme->rxempty_task);
3406 jme_powersave_phy(jme);
3407 #ifndef JME_NEW_PM_API
3408 pci_save_state(pdev);
3409 jme_pci_wakeup_enable(jme, !!(jme->reg_pmcs));
3410 pci_set_power_state(pdev, PCI_D3hot);
3417 #ifdef JME_NEW_PM_API
3418 jme_resume(struct device *dev)
3420 jme_resume(struct pci_dev *pdev)
3423 #ifdef JME_NEW_PM_API
3424 struct pci_dev *pdev = to_pci_dev(dev);
3426 struct net_device *netdev = pci_get_drvdata(pdev);
3427 struct jme_adapter *jme = netdev_priv(netdev);
3430 #ifndef JME_NEW_PM_API
3431 pci_set_power_state(pdev, PCI_D0);
3432 pci_restore_state(pdev);
3436 if (test_bit(JME_FLAG_SSET, &jme->flags))
3437 jme_set_settings(netdev, &jme->old_ecmd);
3439 jme_reset_phy_processor(jme);
3442 netif_device_attach(netdev);
3444 atomic_inc(&jme->link_changing);
3446 jme_reset_link(jme);
3451 #ifdef JME_NEW_PM_API
3452 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3453 #define JME_PM_OPS (&jme_pm_ops)
3458 #ifdef JME_NEW_PM_API
3459 #define JME_PM_OPS NULL
3463 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24)
3464 static struct pci_device_id jme_pci_tbl[] = {
3466 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3468 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3469 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3473 static struct pci_driver jme_driver = {
3475 .id_table = jme_pci_tbl,
3476 .probe = jme_init_one,
3477 .remove = __devexit_p(jme_remove_one),
3478 .shutdown = jme_shutdown,
3479 #ifndef JME_NEW_PM_API
3480 .suspend = jme_suspend,
3481 .resume = jme_resume
3483 .driver.pm = JME_PM_OPS,
3488 jme_init_module(void)
3490 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3491 return pci_register_driver(&jme_driver);
3495 jme_cleanup_module(void)
3497 pci_unregister_driver(&jme_driver);
3500 module_init(jme_init_module);
3501 module_exit(jme_cleanup_module);
3503 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3504 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3505 MODULE_LICENSE("GPL");
3506 MODULE_VERSION(DRV_VERSION);
3507 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);