jme: Fix unmap error (Causing system freeze)
[jme.git] / jme.c
1 /*
2  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3  *
4  * Copyright 2008 JMicron Technology Corporation
5  * http://www.jmicron.com/
6  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7  *
8  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License as published by
12  * the Free Software Foundation; either version 2 of the License.
13  *
14  * This program is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  * GNU General Public License for more details.
18  *
19  * You should have received a copy of the GNU General Public License
20  * along with this program; if not, write to the Free Software
21  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22  *
23  */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
37 #include <linux/in.h>
38 #include <linux/ip.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
45 #include "jme.h"
46
47 static int force_pseudohp = -1;
48 static int no_pseudohp = -1;
49 static int no_extplug = -1;
50 module_param(force_pseudohp, int, 0);
51 MODULE_PARM_DESC(force_pseudohp,
52         "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp, int, 0);
54 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug, int, 0);
56 MODULE_PARM_DESC(no_extplug,
57         "Do not use external plug signal for pseudo hot-plug.");
58
59 static int
60 jme_mdio_read(struct net_device *netdev, int phy, int reg)
61 {
62         struct jme_adapter *jme = netdev_priv(netdev);
63         int i, val, again = (reg == MII_BMSR) ? 1 : 0;
64
65 read_again:
66         jwrite32(jme, JME_SMI, SMI_OP_REQ |
67                                 smi_phy_addr(phy) |
68                                 smi_reg_addr(reg));
69
70         wmb();
71         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
72                 udelay(20);
73                 val = jread32(jme, JME_SMI);
74                 if ((val & SMI_OP_REQ) == 0)
75                         break;
76         }
77
78         if (i == 0) {
79                 pr_err("phy(%d) read timeout : %d\n", phy, reg);
80                 return 0;
81         }
82
83         if (again--)
84                 goto read_again;
85
86         return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
87 }
88
89 static void
90 jme_mdio_write(struct net_device *netdev,
91                                 int phy, int reg, int val)
92 {
93         struct jme_adapter *jme = netdev_priv(netdev);
94         int i;
95
96         jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
97                 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
98                 smi_phy_addr(phy) | smi_reg_addr(reg));
99
100         wmb();
101         for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
102                 udelay(20);
103                 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
104                         break;
105         }
106
107         if (i == 0)
108                 pr_err("phy(%d) write timeout : %d\n", phy, reg);
109 }
110
111 static inline void
112 jme_reset_phy_processor(struct jme_adapter *jme)
113 {
114         u32 val;
115
116         jme_mdio_write(jme->dev,
117                         jme->mii_if.phy_id,
118                         MII_ADVERTISE, ADVERTISE_ALL |
119                         ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
120
121         if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
122                 jme_mdio_write(jme->dev,
123                                 jme->mii_if.phy_id,
124                                 MII_CTRL1000,
125                                 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
126
127         val = jme_mdio_read(jme->dev,
128                                 jme->mii_if.phy_id,
129                                 MII_BMCR);
130
131         jme_mdio_write(jme->dev,
132                         jme->mii_if.phy_id,
133                         MII_BMCR, val | BMCR_RESET);
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138                        const u32 *mask, u32 crc, int fnr)
139 {
140         int i;
141
142         /*
143          * Setup CRC pattern
144          */
145         jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146         wmb();
147         jwrite32(jme, JME_WFODP, crc);
148         wmb();
149
150         /*
151          * Setup Mask
152          */
153         for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154                 jwrite32(jme, JME_WFOI,
155                                 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156                                 (fnr & WFOI_FRAME_SEL));
157                 wmb();
158                 jwrite32(jme, JME_WFODP, mask[i]);
159                 wmb();
160         }
161 }
162
163 static inline void
164 jme_mac_rxclk_off(struct jme_adapter *jme)
165 {
166         jme->reg_gpreg1 |= GPREG1_RXCLKOFF;
167         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
168 }
169
170 static inline void
171 jme_mac_rxclk_on(struct jme_adapter *jme)
172 {
173         jme->reg_gpreg1 &= ~GPREG1_RXCLKOFF;
174         jwrite32f(jme, JME_GPREG1, jme->reg_gpreg1);
175 }
176
177 static inline void
178 jme_mac_txclk_off(struct jme_adapter *jme)
179 {
180         jme->reg_ghc &= ~(GHC_TO_CLK_SRC | GHC_TXMAC_CLK_SRC);
181         jwrite32f(jme, JME_GHC, jme->reg_ghc);
182 }
183
184 static inline void
185 jme_mac_txclk_on(struct jme_adapter *jme)
186 {
187         u32 speed = jme->reg_ghc & GHC_SPEED;
188         if (speed == GHC_SPEED_1000M)
189                 jme->reg_ghc |= GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
190         else
191                 jme->reg_ghc |= GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
192         jwrite32f(jme, JME_GHC, jme->reg_ghc);
193 }
194
195 static inline void
196 jme_reset_ghc_speed(struct jme_adapter *jme)
197 {
198         jme->reg_ghc &= ~(GHC_SPEED | GHC_DPX);
199         jwrite32f(jme, JME_GHC, jme->reg_ghc);
200 }
201
202 static inline void
203 jme_reset_250A2_workaround(struct jme_adapter *jme)
204 {
205         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
206                              GPREG1_RSSPATCH);
207         jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
208 }
209
210 static inline void
211 jme_assert_ghc_reset(struct jme_adapter *jme)
212 {
213         jme->reg_ghc |= GHC_SWRST;
214         jwrite32f(jme, JME_GHC, jme->reg_ghc);
215 }
216
217 static inline void
218 jme_clear_ghc_reset(struct jme_adapter *jme)
219 {
220         jme->reg_ghc &= ~GHC_SWRST;
221         jwrite32f(jme, JME_GHC, jme->reg_ghc);
222 }
223
224 static inline void
225 jme_reset_mac_processor(struct jme_adapter *jme)
226 {
227         static const u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
228         u32 crc = 0xCDCDCDCD;
229         u32 gpreg0;
230         int i;
231
232         jme_reset_ghc_speed(jme);
233         jme_reset_250A2_workaround(jme);
234
235         jme_mac_rxclk_on(jme);
236         jme_mac_txclk_on(jme);
237         udelay(1);
238         jme_assert_ghc_reset(jme);
239         udelay(1);
240         jme_mac_rxclk_off(jme);
241         jme_mac_txclk_off(jme);
242         udelay(1);
243         jme_clear_ghc_reset(jme);
244         udelay(1);
245         jme_mac_rxclk_on(jme);
246         jme_mac_txclk_on(jme);
247         udelay(1);
248         jme_mac_rxclk_off(jme);
249         jme_mac_txclk_off(jme);
250
251         jwrite32(jme, JME_RXDBA_LO, 0x00000000);
252         jwrite32(jme, JME_RXDBA_HI, 0x00000000);
253         jwrite32(jme, JME_RXQDC, 0x00000000);
254         jwrite32(jme, JME_RXNDA, 0x00000000);
255         jwrite32(jme, JME_TXDBA_LO, 0x00000000);
256         jwrite32(jme, JME_TXDBA_HI, 0x00000000);
257         jwrite32(jme, JME_TXQDC, 0x00000000);
258         jwrite32(jme, JME_TXNDA, 0x00000000);
259
260         jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
261         jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
262         for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
263                 jme_setup_wakeup_frame(jme, mask, crc, i);
264         if (jme->fpgaver)
265                 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
266         else
267                 gpreg0 = GPREG0_DEFAULT;
268         jwrite32(jme, JME_GPREG0, gpreg0);
269 }
270
271 static inline void
272 jme_clear_pm(struct jme_adapter *jme)
273 {
274         jwrite32(jme, JME_PMCS, PMCS_STMASK | jme->reg_pmcs);
275 }
276
277 static int
278 jme_reload_eeprom(struct jme_adapter *jme)
279 {
280         u32 val;
281         int i;
282
283         val = jread32(jme, JME_SMBCSR);
284
285         if (val & SMBCSR_EEPROMD) {
286                 val |= SMBCSR_CNACK;
287                 jwrite32(jme, JME_SMBCSR, val);
288                 val |= SMBCSR_RELOAD;
289                 jwrite32(jme, JME_SMBCSR, val);
290                 mdelay(12);
291
292                 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
293                         mdelay(1);
294                         if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
295                                 break;
296                 }
297
298                 if (i == 0) {
299                         pr_err("eeprom reload timeout\n");
300                         return -EIO;
301                 }
302         }
303
304         return 0;
305 }
306
307 static void
308 jme_load_macaddr(struct net_device *netdev)
309 {
310         struct jme_adapter *jme = netdev_priv(netdev);
311         unsigned char macaddr[6];
312         u32 val;
313
314         spin_lock_bh(&jme->macaddr_lock);
315         val = jread32(jme, JME_RXUMA_LO);
316         macaddr[0] = (val >>  0) & 0xFF;
317         macaddr[1] = (val >>  8) & 0xFF;
318         macaddr[2] = (val >> 16) & 0xFF;
319         macaddr[3] = (val >> 24) & 0xFF;
320         val = jread32(jme, JME_RXUMA_HI);
321         macaddr[4] = (val >>  0) & 0xFF;
322         macaddr[5] = (val >>  8) & 0xFF;
323         memcpy(netdev->dev_addr, macaddr, 6);
324         spin_unlock_bh(&jme->macaddr_lock);
325 }
326
327 static inline void
328 jme_set_rx_pcc(struct jme_adapter *jme, int p)
329 {
330         switch (p) {
331         case PCC_OFF:
332                 jwrite32(jme, JME_PCCRX0,
333                         ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
334                         ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
335                 break;
336         case PCC_P1:
337                 jwrite32(jme, JME_PCCRX0,
338                         ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
339                         ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
340                 break;
341         case PCC_P2:
342                 jwrite32(jme, JME_PCCRX0,
343                         ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
344                         ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
345                 break;
346         case PCC_P3:
347                 jwrite32(jme, JME_PCCRX0,
348                         ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
349                         ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
350                 break;
351         default:
352                 break;
353         }
354         wmb();
355
356         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
357                 netif_info(jme, rx_status, jme->dev, "Switched to PCC_P%d\n", p);
358 }
359
360 static void
361 jme_start_irq(struct jme_adapter *jme)
362 {
363         register struct dynpcc_info *dpi = &(jme->dpi);
364
365         jme_set_rx_pcc(jme, PCC_P1);
366         dpi->cur                = PCC_P1;
367         dpi->attempt            = PCC_P1;
368         dpi->cnt                = 0;
369
370         jwrite32(jme, JME_PCCTX,
371                         ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
372                         ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
373                         PCCTXQ0_EN
374                 );
375
376         /*
377          * Enable Interrupts
378          */
379         jwrite32(jme, JME_IENS, INTR_ENABLE);
380 }
381
382 static inline void
383 jme_stop_irq(struct jme_adapter *jme)
384 {
385         /*
386          * Disable Interrupts
387          */
388         jwrite32f(jme, JME_IENC, INTR_ENABLE);
389 }
390
391 static u32
392 jme_linkstat_from_phy(struct jme_adapter *jme)
393 {
394         u32 phylink, bmsr;
395
396         phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
397         bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
398         if (bmsr & BMSR_ANCOMP)
399                 phylink |= PHY_LINK_AUTONEG_COMPLETE;
400
401         return phylink;
402 }
403
404 static inline void
405 jme_set_phyfifo_5level(struct jme_adapter *jme)
406 {
407         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
408 }
409
410 static inline void
411 jme_set_phyfifo_8level(struct jme_adapter *jme)
412 {
413         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
414 }
415
416 static int
417 jme_check_link(struct net_device *netdev, int testonly)
418 {
419         struct jme_adapter *jme = netdev_priv(netdev);
420         u32 phylink, cnt = JME_SPDRSV_TIMEOUT, bmcr;
421         char linkmsg[64];
422         int rc = 0;
423
424         linkmsg[0] = '\0';
425
426         if (jme->fpgaver)
427                 phylink = jme_linkstat_from_phy(jme);
428         else
429                 phylink = jread32(jme, JME_PHY_LINK);
430
431         if (phylink & PHY_LINK_UP) {
432                 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
433                         /*
434                          * If we did not enable AN
435                          * Speed/Duplex Info should be obtained from SMI
436                          */
437                         phylink = PHY_LINK_UP;
438
439                         bmcr = jme_mdio_read(jme->dev,
440                                                 jme->mii_if.phy_id,
441                                                 MII_BMCR);
442
443                         phylink |= ((bmcr & BMCR_SPEED1000) &&
444                                         (bmcr & BMCR_SPEED100) == 0) ?
445                                         PHY_LINK_SPEED_1000M :
446                                         (bmcr & BMCR_SPEED100) ?
447                                         PHY_LINK_SPEED_100M :
448                                         PHY_LINK_SPEED_10M;
449
450                         phylink |= (bmcr & BMCR_FULLDPLX) ?
451                                          PHY_LINK_DUPLEX : 0;
452
453                         strcat(linkmsg, "Forced: ");
454                 } else {
455                         /*
456                          * Keep polling for speed/duplex resolve complete
457                          */
458                         while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
459                                 --cnt) {
460
461                                 udelay(1);
462
463                                 if (jme->fpgaver)
464                                         phylink = jme_linkstat_from_phy(jme);
465                                 else
466                                         phylink = jread32(jme, JME_PHY_LINK);
467                         }
468                         if (!cnt)
469                                 pr_err("Waiting speed resolve timeout\n");
470
471                         strcat(linkmsg, "ANed: ");
472                 }
473
474                 if (jme->phylink == phylink) {
475                         rc = 1;
476                         goto out;
477                 }
478                 if (testonly)
479                         goto out;
480
481                 jme->phylink = phylink;
482
483                 /*
484                  * The speed/duplex setting of jme->reg_ghc already cleared
485                  * by jme_reset_mac_processor()
486                  */
487                 switch (phylink & PHY_LINK_SPEED_MASK) {
488                 case PHY_LINK_SPEED_10M:
489                         jme->reg_ghc |= GHC_SPEED_10M;
490                         strcat(linkmsg, "10 Mbps, ");
491                         break;
492                 case PHY_LINK_SPEED_100M:
493                         jme->reg_ghc |= GHC_SPEED_100M;
494                         strcat(linkmsg, "100 Mbps, ");
495                         break;
496                 case PHY_LINK_SPEED_1000M:
497                         jme->reg_ghc |= GHC_SPEED_1000M;
498                         strcat(linkmsg, "1000 Mbps, ");
499                         break;
500                 default:
501                         break;
502                 }
503
504                 if (phylink & PHY_LINK_DUPLEX) {
505                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
506                         jwrite32(jme, JME_TXTRHD, TXTRHD_FULLDUPLEX);
507                         jme->reg_ghc |= GHC_DPX;
508                 } else {
509                         jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
510                                                 TXMCS_BACKOFF |
511                                                 TXMCS_CARRIERSENSE |
512                                                 TXMCS_COLLISION);
513                         jwrite32(jme, JME_TXTRHD, TXTRHD_HALFDUPLEX);
514                 }
515
516                 jwrite32(jme, JME_GHC, jme->reg_ghc);
517
518                 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
519                         jme->reg_gpreg1 &= ~(GPREG1_HALFMODEPATCH |
520                                              GPREG1_RSSPATCH);
521                         if (!(phylink & PHY_LINK_DUPLEX))
522                                 jme->reg_gpreg1 |= GPREG1_HALFMODEPATCH;
523                         switch (phylink & PHY_LINK_SPEED_MASK) {
524                         case PHY_LINK_SPEED_10M:
525                                 jme_set_phyfifo_8level(jme);
526                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
527                                 break;
528                         case PHY_LINK_SPEED_100M:
529                                 jme_set_phyfifo_5level(jme);
530                                 jme->reg_gpreg1 |= GPREG1_RSSPATCH;
531                                 break;
532                         case PHY_LINK_SPEED_1000M:
533                                 jme_set_phyfifo_8level(jme);
534                                 break;
535                         default:
536                                 break;
537                         }
538                 }
539                 jwrite32(jme, JME_GPREG1, jme->reg_gpreg1);
540
541                 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
542                                         "Full-Duplex, " :
543                                         "Half-Duplex, ");
544                 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
545                                         "MDI-X" :
546                                         "MDI");
547                 netif_info(jme, link, jme->dev, "Link is up at %s\n", linkmsg);
548                 netif_carrier_on(netdev);
549         } else {
550                 if (testonly)
551                         goto out;
552
553                 netif_info(jme, link, jme->dev, "Link is down\n");
554                 jme->phylink = 0;
555                 netif_carrier_off(netdev);
556         }
557
558 out:
559         return rc;
560 }
561
562 static int
563 jme_setup_tx_resources(struct jme_adapter *jme)
564 {
565         struct jme_ring *txring = &(jme->txring[0]);
566
567         txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
568                                    TX_RING_ALLOC_SIZE(jme->tx_ring_size),
569                                    &(txring->dmaalloc),
570                                    GFP_ATOMIC);
571
572         if (!txring->alloc)
573                 goto err_set_null;
574
575         /*
576          * 16 Bytes align
577          */
578         txring->desc            = (void *)ALIGN((unsigned long)(txring->alloc),
579                                                 RING_DESC_ALIGN);
580         txring->dma             = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
581         txring->next_to_use     = 0;
582         atomic_set(&txring->next_to_clean, 0);
583         atomic_set(&txring->nr_free, jme->tx_ring_size);
584
585         txring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
586                                         jme->tx_ring_size, GFP_ATOMIC);
587         if (unlikely(!(txring->bufinf)))
588                 goto err_free_txring;
589
590         /*
591          * Initialize Transmit Descriptors
592          */
593         memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
594         memset(txring->bufinf, 0,
595                 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
596
597         return 0;
598
599 err_free_txring:
600         dma_free_coherent(&(jme->pdev->dev),
601                           TX_RING_ALLOC_SIZE(jme->tx_ring_size),
602                           txring->alloc,
603                           txring->dmaalloc);
604
605 err_set_null:
606         txring->desc = NULL;
607         txring->dmaalloc = 0;
608         txring->dma = 0;
609         txring->bufinf = NULL;
610
611         return -ENOMEM;
612 }
613
614 static void
615 jme_free_tx_resources(struct jme_adapter *jme)
616 {
617         int i;
618         struct jme_ring *txring = &(jme->txring[0]);
619         struct jme_buffer_info *txbi;
620
621         if (txring->alloc) {
622                 if (txring->bufinf) {
623                         for (i = 0 ; i < jme->tx_ring_size ; ++i) {
624                                 txbi = txring->bufinf + i;
625                                 if (txbi->skb) {
626                                         dev_kfree_skb(txbi->skb);
627                                         txbi->skb = NULL;
628                                 }
629                                 txbi->mapping           = 0;
630                                 txbi->len               = 0;
631                                 txbi->nr_desc           = 0;
632                                 txbi->start_xmit        = 0;
633                         }
634                         kfree(txring->bufinf);
635                 }
636
637                 dma_free_coherent(&(jme->pdev->dev),
638                                   TX_RING_ALLOC_SIZE(jme->tx_ring_size),
639                                   txring->alloc,
640                                   txring->dmaalloc);
641
642                 txring->alloc           = NULL;
643                 txring->desc            = NULL;
644                 txring->dmaalloc        = 0;
645                 txring->dma             = 0;
646                 txring->bufinf          = NULL;
647         }
648         txring->next_to_use     = 0;
649         atomic_set(&txring->next_to_clean, 0);
650         atomic_set(&txring->nr_free, 0);
651 }
652
653 static inline void
654 jme_enable_tx_engine(struct jme_adapter *jme)
655 {
656         /*
657          * Select Queue 0
658          */
659         jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
660         wmb();
661
662         /*
663          * Setup TX Queue 0 DMA Bass Address
664          */
665         jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
666         jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
667         jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
668
669         /*
670          * Setup TX Descptor Count
671          */
672         jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
673
674         /*
675          * Enable TX Engine
676          */
677         wmb();
678         jwrite32f(jme, JME_TXCS, jme->reg_txcs |
679                                 TXCS_SELECT_QUEUE0 |
680                                 TXCS_ENABLE);
681
682         /*
683          * Start clock for TX MAC Processor
684          */
685         jme_mac_txclk_on(jme);
686 }
687
688 static inline void
689 jme_restart_tx_engine(struct jme_adapter *jme)
690 {
691         /*
692          * Restart TX Engine
693          */
694         jwrite32(jme, JME_TXCS, jme->reg_txcs |
695                                 TXCS_SELECT_QUEUE0 |
696                                 TXCS_ENABLE);
697 }
698
699 static inline void
700 jme_disable_tx_engine(struct jme_adapter *jme)
701 {
702         int i;
703         u32 val;
704
705         /*
706          * Disable TX Engine
707          */
708         jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
709         wmb();
710
711         val = jread32(jme, JME_TXCS);
712         for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
713                 mdelay(1);
714                 val = jread32(jme, JME_TXCS);
715                 rmb();
716         }
717
718         if (!i)
719                 pr_err("Disable TX engine timeout\n");
720
721         /*
722          * Stop clock for TX MAC Processor
723          */
724         jme_mac_txclk_off(jme);
725 }
726
727 static void
728 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
729 {
730         struct jme_ring *rxring = &(jme->rxring[0]);
731         register struct rxdesc *rxdesc = rxring->desc;
732         struct jme_buffer_info *rxbi = rxring->bufinf;
733         rxdesc += i;
734         rxbi += i;
735
736         rxdesc->dw[0] = 0;
737         rxdesc->dw[1] = 0;
738         rxdesc->desc1.bufaddrh  = cpu_to_le32((__u64)rxbi->mapping >> 32);
739         rxdesc->desc1.bufaddrl  = cpu_to_le32(
740                                         (__u64)rxbi->mapping & 0xFFFFFFFFUL);
741         rxdesc->desc1.datalen   = cpu_to_le16(rxbi->len);
742         if (jme->dev->features & NETIF_F_HIGHDMA)
743                 rxdesc->desc1.flags = RXFLAG_64BIT;
744         wmb();
745         rxdesc->desc1.flags     |= RXFLAG_OWN | RXFLAG_INT;
746 }
747
748 static int
749 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
750 {
751         struct jme_ring *rxring = &(jme->rxring[0]);
752         struct jme_buffer_info *rxbi = rxring->bufinf + i;
753         struct sk_buff *skb;
754         dma_addr_t mapping;
755
756         skb = netdev_alloc_skb(jme->dev,
757                 jme->dev->mtu + RX_EXTRA_LEN);
758         if (unlikely(!skb))
759                 return -ENOMEM;
760
761         mapping = pci_map_page(jme->pdev, virt_to_page(skb->data),
762                                offset_in_page(skb->data), skb_tailroom(skb),
763                                PCI_DMA_FROMDEVICE);
764         if (unlikely(pci_dma_mapping_error(jme->pdev, mapping))) {
765                 dev_kfree_skb(skb);
766                 return -ENOMEM;
767         }
768
769         if (likely(rxbi->mapping))
770                 pci_unmap_page(jme->pdev, rxbi->mapping,
771                                rxbi->len, PCI_DMA_FROMDEVICE);
772
773         rxbi->skb = skb;
774         rxbi->len = skb_tailroom(skb);
775         rxbi->mapping = mapping;
776         return 0;
777 }
778
779 static void
780 jme_free_rx_buf(struct jme_adapter *jme, int i)
781 {
782         struct jme_ring *rxring = &(jme->rxring[0]);
783         struct jme_buffer_info *rxbi = rxring->bufinf;
784         rxbi += i;
785
786         if (rxbi->skb) {
787                 pci_unmap_page(jme->pdev,
788                                  rxbi->mapping,
789                                  rxbi->len,
790                                  PCI_DMA_FROMDEVICE);
791                 dev_kfree_skb(rxbi->skb);
792                 rxbi->skb = NULL;
793                 rxbi->mapping = 0;
794                 rxbi->len = 0;
795         }
796 }
797
798 static void
799 jme_free_rx_resources(struct jme_adapter *jme)
800 {
801         int i;
802         struct jme_ring *rxring = &(jme->rxring[0]);
803
804         if (rxring->alloc) {
805                 if (rxring->bufinf) {
806                         for (i = 0 ; i < jme->rx_ring_size ; ++i)
807                                 jme_free_rx_buf(jme, i);
808                         kfree(rxring->bufinf);
809                 }
810
811                 dma_free_coherent(&(jme->pdev->dev),
812                                   RX_RING_ALLOC_SIZE(jme->rx_ring_size),
813                                   rxring->alloc,
814                                   rxring->dmaalloc);
815                 rxring->alloc    = NULL;
816                 rxring->desc     = NULL;
817                 rxring->dmaalloc = 0;
818                 rxring->dma      = 0;
819                 rxring->bufinf   = NULL;
820         }
821         rxring->next_to_use   = 0;
822         atomic_set(&rxring->next_to_clean, 0);
823 }
824
825 static int
826 jme_setup_rx_resources(struct jme_adapter *jme)
827 {
828         int i;
829         struct jme_ring *rxring = &(jme->rxring[0]);
830
831         rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
832                                    RX_RING_ALLOC_SIZE(jme->rx_ring_size),
833                                    &(rxring->dmaalloc),
834                                    GFP_ATOMIC);
835         if (!rxring->alloc)
836                 goto err_set_null;
837
838         /*
839          * 16 Bytes align
840          */
841         rxring->desc            = (void *)ALIGN((unsigned long)(rxring->alloc),
842                                                 RING_DESC_ALIGN);
843         rxring->dma             = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
844         rxring->next_to_use     = 0;
845         atomic_set(&rxring->next_to_clean, 0);
846
847         rxring->bufinf          = kmalloc(sizeof(struct jme_buffer_info) *
848                                         jme->rx_ring_size, GFP_ATOMIC);
849         if (unlikely(!(rxring->bufinf)))
850                 goto err_free_rxring;
851
852         /*
853          * Initiallize Receive Descriptors
854          */
855         memset(rxring->bufinf, 0,
856                 sizeof(struct jme_buffer_info) * jme->rx_ring_size);
857         for (i = 0 ; i < jme->rx_ring_size ; ++i) {
858                 if (unlikely(jme_make_new_rx_buf(jme, i))) {
859                         jme_free_rx_resources(jme);
860                         return -ENOMEM;
861                 }
862
863                 jme_set_clean_rxdesc(jme, i);
864         }
865
866         return 0;
867
868 err_free_rxring:
869         dma_free_coherent(&(jme->pdev->dev),
870                           RX_RING_ALLOC_SIZE(jme->rx_ring_size),
871                           rxring->alloc,
872                           rxring->dmaalloc);
873 err_set_null:
874         rxring->desc = NULL;
875         rxring->dmaalloc = 0;
876         rxring->dma = 0;
877         rxring->bufinf = NULL;
878
879         return -ENOMEM;
880 }
881
882 static inline void
883 jme_enable_rx_engine(struct jme_adapter *jme)
884 {
885         /*
886          * Select Queue 0
887          */
888         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
889                                 RXCS_QUEUESEL_Q0);
890         wmb();
891
892         /*
893          * Setup RX DMA Bass Address
894          */
895         jwrite32(jme, JME_RXDBA_LO, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
896         jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
897         jwrite32(jme, JME_RXNDA, (__u64)(jme->rxring[0].dma) & 0xFFFFFFFFUL);
898
899         /*
900          * Setup RX Descriptor Count
901          */
902         jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
903
904         /*
905          * Setup Unicast Filter
906          */
907         jme_set_unicastaddr(jme->dev);
908         jme_set_multi(jme->dev);
909
910         /*
911          * Enable RX Engine
912          */
913         wmb();
914         jwrite32f(jme, JME_RXCS, jme->reg_rxcs |
915                                 RXCS_QUEUESEL_Q0 |
916                                 RXCS_ENABLE |
917                                 RXCS_QST);
918
919         /*
920          * Start clock for RX MAC Processor
921          */
922         jme_mac_rxclk_on(jme);
923 }
924
925 static inline void
926 jme_restart_rx_engine(struct jme_adapter *jme)
927 {
928         /*
929          * Start RX Engine
930          */
931         jwrite32(jme, JME_RXCS, jme->reg_rxcs |
932                                 RXCS_QUEUESEL_Q0 |
933                                 RXCS_ENABLE |
934                                 RXCS_QST);
935 }
936
937 static inline void
938 jme_disable_rx_engine(struct jme_adapter *jme)
939 {
940         int i;
941         u32 val;
942
943         /*
944          * Disable RX Engine
945          */
946         jwrite32(jme, JME_RXCS, jme->reg_rxcs);
947         wmb();
948
949         val = jread32(jme, JME_RXCS);
950         for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
951                 mdelay(1);
952                 val = jread32(jme, JME_RXCS);
953                 rmb();
954         }
955
956         if (!i)
957                 pr_err("Disable RX engine timeout\n");
958
959         /*
960          * Stop clock for RX MAC Processor
961          */
962         jme_mac_rxclk_off(jme);
963 }
964
965 static u16
966 jme_udpsum(struct sk_buff *skb)
967 {
968         u16 csum = 0xFFFFu;
969
970         if (skb->len < (ETH_HLEN + sizeof(struct iphdr)))
971                 return csum;
972         if (skb->protocol != htons(ETH_P_IP))
973                 return csum;
974         skb_set_network_header(skb, ETH_HLEN);
975         if ((ip_hdr(skb)->protocol != IPPROTO_UDP) ||
976             (skb->len < (ETH_HLEN +
977                         (ip_hdr(skb)->ihl << 2) +
978                         sizeof(struct udphdr)))) {
979                 skb_reset_network_header(skb);
980                 return csum;
981         }
982         skb_set_transport_header(skb,
983                         ETH_HLEN + (ip_hdr(skb)->ihl << 2));
984         csum = udp_hdr(skb)->check;
985         skb_reset_transport_header(skb);
986         skb_reset_network_header(skb);
987
988         return csum;
989 }
990
991 static int
992 jme_rxsum_ok(struct jme_adapter *jme, u16 flags, struct sk_buff *skb)
993 {
994         if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
995                 return false;
996
997         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_TCPON | RXWBFLAG_TCPCS))
998                         == RXWBFLAG_TCPON)) {
999                 if (flags & RXWBFLAG_IPV4)
1000                         netif_err(jme, rx_err, jme->dev, "TCP Checksum error\n");
1001                 return false;
1002         }
1003
1004         if (unlikely((flags & (RXWBFLAG_MF | RXWBFLAG_UDPON | RXWBFLAG_UDPCS))
1005                         == RXWBFLAG_UDPON) && jme_udpsum(skb)) {
1006                 if (flags & RXWBFLAG_IPV4)
1007                         netif_err(jme, rx_err, jme->dev, "UDP Checksum error\n");
1008                 return false;
1009         }
1010
1011         if (unlikely((flags & (RXWBFLAG_IPV4 | RXWBFLAG_IPCS))
1012                         == RXWBFLAG_IPV4)) {
1013                 netif_err(jme, rx_err, jme->dev, "IPv4 Checksum error\n");
1014                 return false;
1015         }
1016
1017         return true;
1018 }
1019
1020 static void
1021 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
1022 {
1023         struct jme_ring *rxring = &(jme->rxring[0]);
1024         struct rxdesc *rxdesc = rxring->desc;
1025         struct jme_buffer_info *rxbi = rxring->bufinf;
1026         struct sk_buff *skb;
1027         int framesize;
1028
1029         rxdesc += idx;
1030         rxbi += idx;
1031
1032         skb = rxbi->skb;
1033         pci_dma_sync_single_for_cpu(jme->pdev,
1034                                         rxbi->mapping,
1035                                         rxbi->len,
1036                                         PCI_DMA_FROMDEVICE);
1037
1038         if (unlikely(jme_make_new_rx_buf(jme, idx))) {
1039                 pci_dma_sync_single_for_device(jme->pdev,
1040                                                 rxbi->mapping,
1041                                                 rxbi->len,
1042                                                 PCI_DMA_FROMDEVICE);
1043
1044                 ++(NET_STAT(jme).rx_dropped);
1045         } else {
1046                 framesize = le16_to_cpu(rxdesc->descwb.framesize)
1047                                 - RX_PREPAD_SIZE;
1048
1049                 skb_reserve(skb, RX_PREPAD_SIZE);
1050                 skb_put(skb, framesize);
1051                 skb->protocol = eth_type_trans(skb, jme->dev);
1052
1053                 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags), skb))
1054                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1055                 else
1056                         skb_checksum_none_assert(skb);
1057
1058                 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
1059                         if (jme->vlgrp) {
1060                                 jme->jme_vlan_rx(skb, jme->vlgrp,
1061                                         le16_to_cpu(rxdesc->descwb.vlan));
1062                                 NET_STAT(jme).rx_bytes += 4;
1063                         } else {
1064                                 dev_kfree_skb(skb);
1065                         }
1066                 } else {
1067                         jme->jme_rx(skb);
1068                 }
1069
1070                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
1071                     cpu_to_le16(RXWBFLAG_DEST_MUL))
1072                         ++(NET_STAT(jme).multicast);
1073
1074                 NET_STAT(jme).rx_bytes += framesize;
1075                 ++(NET_STAT(jme).rx_packets);
1076         }
1077
1078         jme_set_clean_rxdesc(jme, idx);
1079
1080 }
1081
1082 static int
1083 jme_process_receive(struct jme_adapter *jme, int limit)
1084 {
1085         struct jme_ring *rxring = &(jme->rxring[0]);
1086         struct rxdesc *rxdesc = rxring->desc;
1087         int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
1088
1089         if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
1090                 goto out_inc;
1091
1092         if (unlikely(atomic_read(&jme->link_changing) != 1))
1093                 goto out_inc;
1094
1095         if (unlikely(!netif_carrier_ok(jme->dev)))
1096                 goto out_inc;
1097
1098         i = atomic_read(&rxring->next_to_clean);
1099         while (limit > 0) {
1100                 rxdesc = rxring->desc;
1101                 rxdesc += i;
1102
1103                 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
1104                 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
1105                         goto out;
1106                 --limit;
1107
1108                 rmb();
1109                 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
1110
1111                 if (unlikely(desccnt > 1 ||
1112                 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
1113
1114                         if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
1115                                 ++(NET_STAT(jme).rx_crc_errors);
1116                         else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
1117                                 ++(NET_STAT(jme).rx_fifo_errors);
1118                         else
1119                                 ++(NET_STAT(jme).rx_errors);
1120
1121                         if (desccnt > 1)
1122                                 limit -= desccnt - 1;
1123
1124                         for (j = i, ccnt = desccnt ; ccnt-- ; ) {
1125                                 jme_set_clean_rxdesc(jme, j);
1126                                 j = (j + 1) & (mask);
1127                         }
1128
1129                 } else {
1130                         jme_alloc_and_feed_skb(jme, i);
1131                 }
1132
1133                 i = (i + desccnt) & (mask);
1134         }
1135
1136 out:
1137         atomic_set(&rxring->next_to_clean, i);
1138
1139 out_inc:
1140         atomic_inc(&jme->rx_cleaning);
1141
1142         return limit > 0 ? limit : 0;
1143
1144 }
1145
1146 static void
1147 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1148 {
1149         if (likely(atmp == dpi->cur)) {
1150                 dpi->cnt = 0;
1151                 return;
1152         }
1153
1154         if (dpi->attempt == atmp) {
1155                 ++(dpi->cnt);
1156         } else {
1157                 dpi->attempt = atmp;
1158                 dpi->cnt = 0;
1159         }
1160
1161 }
1162
1163 static void
1164 jme_dynamic_pcc(struct jme_adapter *jme)
1165 {
1166         register struct dynpcc_info *dpi = &(jme->dpi);
1167
1168         if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1169                 jme_attempt_pcc(dpi, PCC_P3);
1170         else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD ||
1171                  dpi->intr_cnt > PCC_INTR_THRESHOLD)
1172                 jme_attempt_pcc(dpi, PCC_P2);
1173         else
1174                 jme_attempt_pcc(dpi, PCC_P1);
1175
1176         if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1177                 if (dpi->attempt < dpi->cur)
1178                         tasklet_schedule(&jme->rxclean_task);
1179                 jme_set_rx_pcc(jme, dpi->attempt);
1180                 dpi->cur = dpi->attempt;
1181                 dpi->cnt = 0;
1182         }
1183 }
1184
1185 static void
1186 jme_start_pcc_timer(struct jme_adapter *jme)
1187 {
1188         struct dynpcc_info *dpi = &(jme->dpi);
1189         dpi->last_bytes         = NET_STAT(jme).rx_bytes;
1190         dpi->last_pkts          = NET_STAT(jme).rx_packets;
1191         dpi->intr_cnt           = 0;
1192         jwrite32(jme, JME_TMCSR,
1193                 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1194 }
1195
1196 static inline void
1197 jme_stop_pcc_timer(struct jme_adapter *jme)
1198 {
1199         jwrite32(jme, JME_TMCSR, 0);
1200 }
1201
1202 static void
1203 jme_shutdown_nic(struct jme_adapter *jme)
1204 {
1205         u32 phylink;
1206
1207         phylink = jme_linkstat_from_phy(jme);
1208
1209         if (!(phylink & PHY_LINK_UP)) {
1210                 /*
1211                  * Disable all interrupt before issue timer
1212                  */
1213                 jme_stop_irq(jme);
1214                 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1215         }
1216 }
1217
1218 static void
1219 jme_pcc_tasklet(unsigned long arg)
1220 {
1221         struct jme_adapter *jme = (struct jme_adapter *)arg;
1222         struct net_device *netdev = jme->dev;
1223
1224         if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1225                 jme_shutdown_nic(jme);
1226                 return;
1227         }
1228
1229         if (unlikely(!netif_carrier_ok(netdev) ||
1230                 (atomic_read(&jme->link_changing) != 1)
1231         )) {
1232                 jme_stop_pcc_timer(jme);
1233                 return;
1234         }
1235
1236         if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1237                 jme_dynamic_pcc(jme);
1238
1239         jme_start_pcc_timer(jme);
1240 }
1241
1242 static inline void
1243 jme_polling_mode(struct jme_adapter *jme)
1244 {
1245         jme_set_rx_pcc(jme, PCC_OFF);
1246 }
1247
1248 static inline void
1249 jme_interrupt_mode(struct jme_adapter *jme)
1250 {
1251         jme_set_rx_pcc(jme, PCC_P1);
1252 }
1253
1254 static inline int
1255 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1256 {
1257         u32 apmc;
1258         apmc = jread32(jme, JME_APMC);
1259         return apmc & JME_APMC_PSEUDO_HP_EN;
1260 }
1261
1262 static void
1263 jme_start_shutdown_timer(struct jme_adapter *jme)
1264 {
1265         u32 apmc;
1266
1267         apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1268         apmc &= ~JME_APMC_EPIEN_CTRL;
1269         if (!no_extplug) {
1270                 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1271                 wmb();
1272         }
1273         jwrite32f(jme, JME_APMC, apmc);
1274
1275         jwrite32f(jme, JME_TIMER2, 0);
1276         set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1277         jwrite32(jme, JME_TMCSR,
1278                 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1279 }
1280
1281 static void
1282 jme_stop_shutdown_timer(struct jme_adapter *jme)
1283 {
1284         u32 apmc;
1285
1286         jwrite32f(jme, JME_TMCSR, 0);
1287         jwrite32f(jme, JME_TIMER2, 0);
1288         clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1289
1290         apmc = jread32(jme, JME_APMC);
1291         apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1292         jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1293         wmb();
1294         jwrite32f(jme, JME_APMC, apmc);
1295 }
1296
1297 static void
1298 jme_link_change_tasklet(unsigned long arg)
1299 {
1300         struct jme_adapter *jme = (struct jme_adapter *)arg;
1301         struct net_device *netdev = jme->dev;
1302         int rc;
1303
1304         while (!atomic_dec_and_test(&jme->link_changing)) {
1305                 atomic_inc(&jme->link_changing);
1306                 netif_info(jme, intr, jme->dev, "Get link change lock failed\n");
1307                 while (atomic_read(&jme->link_changing) != 1)
1308                         netif_info(jme, intr, jme->dev, "Waiting link change lock\n");
1309         }
1310
1311         if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1312                 goto out;
1313
1314         jme->old_mtu = netdev->mtu;
1315         netif_stop_queue(netdev);
1316         if (jme_pseudo_hotplug_enabled(jme))
1317                 jme_stop_shutdown_timer(jme);
1318
1319         jme_stop_pcc_timer(jme);
1320         tasklet_disable(&jme->txclean_task);
1321         tasklet_disable(&jme->rxclean_task);
1322         tasklet_disable(&jme->rxempty_task);
1323
1324         if (netif_carrier_ok(netdev)) {
1325                 jme_disable_rx_engine(jme);
1326                 jme_disable_tx_engine(jme);
1327                 jme_reset_mac_processor(jme);
1328                 jme_free_rx_resources(jme);
1329                 jme_free_tx_resources(jme);
1330
1331                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1332                         jme_polling_mode(jme);
1333
1334                 netif_carrier_off(netdev);
1335         }
1336
1337         jme_check_link(netdev, 0);
1338         if (netif_carrier_ok(netdev)) {
1339                 rc = jme_setup_rx_resources(jme);
1340                 if (rc) {
1341                         pr_err("Allocating resources for RX error, Device STOPPED!\n");
1342                         goto out_enable_tasklet;
1343                 }
1344
1345                 rc = jme_setup_tx_resources(jme);
1346                 if (rc) {
1347                         pr_err("Allocating resources for TX error, Device STOPPED!\n");
1348                         goto err_out_free_rx_resources;
1349                 }
1350
1351                 jme_enable_rx_engine(jme);
1352                 jme_enable_tx_engine(jme);
1353
1354                 netif_start_queue(netdev);
1355
1356                 if (test_bit(JME_FLAG_POLL, &jme->flags))
1357                         jme_interrupt_mode(jme);
1358
1359                 jme_start_pcc_timer(jme);
1360         } else if (jme_pseudo_hotplug_enabled(jme)) {
1361                 jme_start_shutdown_timer(jme);
1362         }
1363
1364         goto out_enable_tasklet;
1365
1366 err_out_free_rx_resources:
1367         jme_free_rx_resources(jme);
1368 out_enable_tasklet:
1369         tasklet_enable(&jme->txclean_task);
1370         tasklet_hi_enable(&jme->rxclean_task);
1371         tasklet_hi_enable(&jme->rxempty_task);
1372 out:
1373         atomic_inc(&jme->link_changing);
1374 }
1375
1376 static void
1377 jme_rx_clean_tasklet(unsigned long arg)
1378 {
1379         struct jme_adapter *jme = (struct jme_adapter *)arg;
1380         struct dynpcc_info *dpi = &(jme->dpi);
1381
1382         jme_process_receive(jme, jme->rx_ring_size);
1383         ++(dpi->intr_cnt);
1384
1385 }
1386
1387 static int
1388 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1389 {
1390         struct jme_adapter *jme = jme_napi_priv(holder);
1391         int rest;
1392
1393         rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1394
1395         while (atomic_read(&jme->rx_empty) > 0) {
1396                 atomic_dec(&jme->rx_empty);
1397                 ++(NET_STAT(jme).rx_dropped);
1398                 jme_restart_rx_engine(jme);
1399         }
1400         atomic_inc(&jme->rx_empty);
1401
1402         if (rest) {
1403                 JME_RX_COMPLETE(netdev, holder);
1404                 jme_interrupt_mode(jme);
1405         }
1406
1407         JME_NAPI_WEIGHT_SET(budget, rest);
1408         return JME_NAPI_WEIGHT_VAL(budget) - rest;
1409 }
1410
1411 static void
1412 jme_rx_empty_tasklet(unsigned long arg)
1413 {
1414         struct jme_adapter *jme = (struct jme_adapter *)arg;
1415
1416         if (unlikely(atomic_read(&jme->link_changing) != 1))
1417                 return;
1418
1419         if (unlikely(!netif_carrier_ok(jme->dev)))
1420                 return;
1421
1422         netif_info(jme, rx_status, jme->dev, "RX Queue Full!\n");
1423
1424         jme_rx_clean_tasklet(arg);
1425
1426         while (atomic_read(&jme->rx_empty) > 0) {
1427                 atomic_dec(&jme->rx_empty);
1428                 ++(NET_STAT(jme).rx_dropped);
1429                 jme_restart_rx_engine(jme);
1430         }
1431         atomic_inc(&jme->rx_empty);
1432 }
1433
1434 static void
1435 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1436 {
1437         struct jme_ring *txring = &(jme->txring[0]);
1438
1439         smp_wmb();
1440         if (unlikely(netif_queue_stopped(jme->dev) &&
1441         atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1442                 netif_info(jme, tx_done, jme->dev, "TX Queue Waked\n");
1443                 netif_wake_queue(jme->dev);
1444         }
1445
1446 }
1447
1448 static void
1449 jme_tx_clean_tasklet(unsigned long arg)
1450 {
1451         struct jme_adapter *jme = (struct jme_adapter *)arg;
1452         struct jme_ring *txring = &(jme->txring[0]);
1453         struct txdesc *txdesc = txring->desc;
1454         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1455         int i, j, cnt = 0, max, err, mask;
1456
1457         tx_dbg(jme, "Into txclean\n");
1458
1459         if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1460                 goto out;
1461
1462         if (unlikely(atomic_read(&jme->link_changing) != 1))
1463                 goto out;
1464
1465         if (unlikely(!netif_carrier_ok(jme->dev)))
1466                 goto out;
1467
1468         max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1469         mask = jme->tx_ring_mask;
1470
1471         for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1472
1473                 ctxbi = txbi + i;
1474
1475                 if (likely(ctxbi->skb &&
1476                 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1477
1478                         tx_dbg(jme, "txclean: %d+%d@%lu\n",
1479                                i, ctxbi->nr_desc, jiffies);
1480
1481                         err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1482
1483                         for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1484                                 ttxbi = txbi + ((i + j) & (mask));
1485                                 txdesc[(i + j) & (mask)].dw[0] = 0;
1486
1487                                 pci_unmap_page(jme->pdev,
1488                                                  ttxbi->mapping,
1489                                                  ttxbi->len,
1490                                                  PCI_DMA_TODEVICE);
1491
1492                                 ttxbi->mapping = 0;
1493                                 ttxbi->len = 0;
1494                         }
1495
1496                         dev_kfree_skb(ctxbi->skb);
1497
1498                         cnt += ctxbi->nr_desc;
1499
1500                         if (unlikely(err)) {
1501                                 ++(NET_STAT(jme).tx_carrier_errors);
1502                         } else {
1503                                 ++(NET_STAT(jme).tx_packets);
1504                                 NET_STAT(jme).tx_bytes += ctxbi->len;
1505                         }
1506
1507                         ctxbi->skb = NULL;
1508                         ctxbi->len = 0;
1509                         ctxbi->start_xmit = 0;
1510
1511                 } else {
1512                         break;
1513                 }
1514
1515                 i = (i + ctxbi->nr_desc) & mask;
1516
1517                 ctxbi->nr_desc = 0;
1518         }
1519
1520         tx_dbg(jme, "txclean: done %d@%lu\n", i, jiffies);
1521         atomic_set(&txring->next_to_clean, i);
1522         atomic_add(cnt, &txring->nr_free);
1523
1524         jme_wake_queue_if_stopped(jme);
1525
1526 out:
1527         atomic_inc(&jme->tx_cleaning);
1528 }
1529
1530 static void
1531 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1532 {
1533         /*
1534          * Disable interrupt
1535          */
1536         jwrite32f(jme, JME_IENC, INTR_ENABLE);
1537
1538         if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1539                 /*
1540                  * Link change event is critical
1541                  * all other events are ignored
1542                  */
1543                 jwrite32(jme, JME_IEVE, intrstat);
1544                 tasklet_schedule(&jme->linkch_task);
1545                 goto out_reenable;
1546         }
1547
1548         if (intrstat & INTR_TMINTR) {
1549                 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1550                 tasklet_schedule(&jme->pcc_task);
1551         }
1552
1553         if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1554                 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1555                 tasklet_schedule(&jme->txclean_task);
1556         }
1557
1558         if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1559                 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1560                                                      INTR_PCCRX0 |
1561                                                      INTR_RX0EMP)) |
1562                                         INTR_RX0);
1563         }
1564
1565         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1566                 if (intrstat & INTR_RX0EMP)
1567                         atomic_inc(&jme->rx_empty);
1568
1569                 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1570                         if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1571                                 jme_polling_mode(jme);
1572                                 JME_RX_SCHEDULE(jme);
1573                         }
1574                 }
1575         } else {
1576                 if (intrstat & INTR_RX0EMP) {
1577                         atomic_inc(&jme->rx_empty);
1578                         tasklet_hi_schedule(&jme->rxempty_task);
1579                 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1580                         tasklet_hi_schedule(&jme->rxclean_task);
1581                 }
1582         }
1583
1584 out_reenable:
1585         /*
1586          * Re-enable interrupt
1587          */
1588         jwrite32f(jme, JME_IENS, INTR_ENABLE);
1589 }
1590
1591 static irqreturn_t
1592 jme_intr(int irq, void *dev_id)
1593 {
1594         struct net_device *netdev = dev_id;
1595         struct jme_adapter *jme = netdev_priv(netdev);
1596         u32 intrstat;
1597
1598         intrstat = jread32(jme, JME_IEVE);
1599
1600         /*
1601          * Check if it's really an interrupt for us
1602          */
1603         if (unlikely((intrstat & INTR_ENABLE) == 0))
1604                 return IRQ_NONE;
1605
1606         /*
1607          * Check if the device still exist
1608          */
1609         if (unlikely(intrstat == ~((typeof(intrstat))0)))
1610                 return IRQ_NONE;
1611
1612         jme_intr_msi(jme, intrstat);
1613
1614         return IRQ_HANDLED;
1615 }
1616
1617 static irqreturn_t
1618 jme_msi(int irq, void *dev_id)
1619 {
1620         struct net_device *netdev = dev_id;
1621         struct jme_adapter *jme = netdev_priv(netdev);
1622         u32 intrstat;
1623
1624         intrstat = jread32(jme, JME_IEVE);
1625
1626         jme_intr_msi(jme, intrstat);
1627
1628         return IRQ_HANDLED;
1629 }
1630
1631 static void
1632 jme_reset_link(struct jme_adapter *jme)
1633 {
1634         jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1635 }
1636
1637 static void
1638 jme_restart_an(struct jme_adapter *jme)
1639 {
1640         u32 bmcr;
1641
1642         spin_lock_bh(&jme->phy_lock);
1643         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1644         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1645         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1646         spin_unlock_bh(&jme->phy_lock);
1647 }
1648
1649 static int
1650 jme_request_irq(struct jme_adapter *jme)
1651 {
1652         int rc;
1653         struct net_device *netdev = jme->dev;
1654         irq_handler_t handler = jme_intr;
1655         int irq_flags = IRQF_SHARED;
1656
1657         if (!pci_enable_msi(jme->pdev)) {
1658                 set_bit(JME_FLAG_MSI, &jme->flags);
1659                 handler = jme_msi;
1660                 irq_flags = 0;
1661         }
1662
1663         rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1664                           netdev);
1665         if (rc) {
1666                 netdev_err(netdev,
1667                            "Unable to request %s interrupt (return: %d)\n",
1668                            test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1669                            rc);
1670
1671                 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1672                         pci_disable_msi(jme->pdev);
1673                         clear_bit(JME_FLAG_MSI, &jme->flags);
1674                 }
1675         } else {
1676                 netdev->irq = jme->pdev->irq;
1677         }
1678
1679         return rc;
1680 }
1681
1682 static void
1683 jme_free_irq(struct jme_adapter *jme)
1684 {
1685         free_irq(jme->pdev->irq, jme->dev);
1686         if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1687                 pci_disable_msi(jme->pdev);
1688                 clear_bit(JME_FLAG_MSI, &jme->flags);
1689                 jme->dev->irq = jme->pdev->irq;
1690         }
1691 }
1692
1693 static inline void
1694 jme_new_phy_on(struct jme_adapter *jme)
1695 {
1696         u32 reg;
1697
1698         reg = jread32(jme, JME_PHY_PWR);
1699         reg &= ~(PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1700                  PHY_PWR_DWN2 | PHY_PWR_CLKSEL);
1701         jwrite32(jme, JME_PHY_PWR, reg);
1702
1703         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1704         reg &= ~PE1_GPREG0_PBG;
1705         reg |= PE1_GPREG0_ENBG;
1706         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1707 }
1708
1709 static inline void
1710 jme_new_phy_off(struct jme_adapter *jme)
1711 {
1712         u32 reg;
1713
1714         reg = jread32(jme, JME_PHY_PWR);
1715         reg |= PHY_PWR_DWN1SEL | PHY_PWR_DWN1SW |
1716                PHY_PWR_DWN2 | PHY_PWR_CLKSEL;
1717         jwrite32(jme, JME_PHY_PWR, reg);
1718
1719         pci_read_config_dword(jme->pdev, PCI_PRIV_PE1, &reg);
1720         reg &= ~PE1_GPREG0_PBG;
1721         reg |= PE1_GPREG0_PDD3COLD;
1722         pci_write_config_dword(jme->pdev, PCI_PRIV_PE1, reg);
1723 }
1724
1725 static inline void
1726 jme_phy_on(struct jme_adapter *jme)
1727 {
1728         u32 bmcr;
1729
1730         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1731         bmcr &= ~BMCR_PDOWN;
1732         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1733
1734         if (new_phy_power_ctrl(jme->chip_main_rev))
1735                 jme_new_phy_on(jme);
1736 }
1737
1738 static inline void
1739 jme_phy_off(struct jme_adapter *jme)
1740 {
1741         u32 bmcr;
1742
1743         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1744         bmcr |= BMCR_PDOWN;
1745         jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1746
1747         if (new_phy_power_ctrl(jme->chip_main_rev))
1748                 jme_new_phy_off(jme);
1749 }
1750
1751 static int
1752 jme_open(struct net_device *netdev)
1753 {
1754         struct jme_adapter *jme = netdev_priv(netdev);
1755         int rc;
1756
1757         jme_clear_pm(jme);
1758         JME_NAPI_ENABLE(jme);
1759
1760         tasklet_enable(&jme->linkch_task);
1761         tasklet_enable(&jme->txclean_task);
1762         tasklet_hi_enable(&jme->rxclean_task);
1763         tasklet_hi_enable(&jme->rxempty_task);
1764
1765         rc = jme_request_irq(jme);
1766         if (rc)
1767                 goto err_out;
1768
1769         jme_start_irq(jme);
1770
1771         jme_phy_on(jme);
1772         if (test_bit(JME_FLAG_SSET, &jme->flags))
1773                 jme_set_settings(netdev, &jme->old_ecmd);
1774         else
1775                 jme_reset_phy_processor(jme);
1776
1777         jme_reset_link(jme);
1778
1779         return 0;
1780
1781 err_out:
1782         netif_stop_queue(netdev);
1783         netif_carrier_off(netdev);
1784         return rc;
1785 }
1786
1787 static void
1788 jme_set_100m_half(struct jme_adapter *jme)
1789 {
1790         u32 bmcr, tmp;
1791
1792         jme_phy_on(jme);
1793         bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1794         tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1795                        BMCR_SPEED1000 | BMCR_FULLDPLX);
1796         tmp |= BMCR_SPEED100;
1797
1798         if (bmcr != tmp)
1799                 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1800
1801         if (jme->fpgaver)
1802                 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1803         else
1804                 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1805 }
1806
1807 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1808 static void
1809 jme_wait_link(struct jme_adapter *jme)
1810 {
1811         u32 phylink, to = JME_WAIT_LINK_TIME;
1812
1813         mdelay(1000);
1814         phylink = jme_linkstat_from_phy(jme);
1815         while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1816                 mdelay(10);
1817                 phylink = jme_linkstat_from_phy(jme);
1818         }
1819 }
1820
1821 static void
1822 jme_powersave_phy(struct jme_adapter *jme)
1823 {
1824         if (jme->reg_pmcs) {
1825                 jme_set_100m_half(jme);
1826                 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
1827                         jme_wait_link(jme);
1828                 jme_clear_pm(jme);
1829         } else {
1830                 jme_phy_off(jme);
1831         }
1832 }
1833
1834 static int
1835 jme_close(struct net_device *netdev)
1836 {
1837         struct jme_adapter *jme = netdev_priv(netdev);
1838
1839         netif_stop_queue(netdev);
1840         netif_carrier_off(netdev);
1841
1842         jme_stop_irq(jme);
1843         jme_free_irq(jme);
1844
1845         JME_NAPI_DISABLE(jme);
1846
1847         tasklet_disable(&jme->linkch_task);
1848         tasklet_disable(&jme->txclean_task);
1849         tasklet_disable(&jme->rxclean_task);
1850         tasklet_disable(&jme->rxempty_task);
1851
1852         jme_disable_rx_engine(jme);
1853         jme_disable_tx_engine(jme);
1854         jme_reset_mac_processor(jme);
1855         jme_free_rx_resources(jme);
1856         jme_free_tx_resources(jme);
1857         jme->phylink = 0;
1858         jme_phy_off(jme);
1859
1860         return 0;
1861 }
1862
1863 static int
1864 jme_alloc_txdesc(struct jme_adapter *jme,
1865                         struct sk_buff *skb)
1866 {
1867         struct jme_ring *txring = &(jme->txring[0]);
1868         int idx, nr_alloc, mask = jme->tx_ring_mask;
1869
1870         idx = txring->next_to_use;
1871         nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1872
1873         if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1874                 return -1;
1875
1876         atomic_sub(nr_alloc, &txring->nr_free);
1877
1878         txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1879
1880         return idx;
1881 }
1882
1883 static void
1884 jme_fill_tx_map(struct pci_dev *pdev,
1885                 struct txdesc *txdesc,
1886                 struct jme_buffer_info *txbi,
1887                 struct page *page,
1888                 u32 page_offset,
1889                 u32 len,
1890                 u8 hidma)
1891 {
1892         dma_addr_t dmaaddr;
1893
1894         dmaaddr = pci_map_page(pdev,
1895                                 page,
1896                                 page_offset,
1897                                 len,
1898                                 PCI_DMA_TODEVICE);
1899
1900         pci_dma_sync_single_for_device(pdev,
1901                                        dmaaddr,
1902                                        len,
1903                                        PCI_DMA_TODEVICE);
1904
1905         txdesc->dw[0] = 0;
1906         txdesc->dw[1] = 0;
1907         txdesc->desc2.flags     = TXFLAG_OWN;
1908         txdesc->desc2.flags     |= (hidma) ? TXFLAG_64BIT : 0;
1909         txdesc->desc2.datalen   = cpu_to_le16(len);
1910         txdesc->desc2.bufaddrh  = cpu_to_le32((__u64)dmaaddr >> 32);
1911         txdesc->desc2.bufaddrl  = cpu_to_le32(
1912                                         (__u64)dmaaddr & 0xFFFFFFFFUL);
1913
1914         txbi->mapping = dmaaddr;
1915         txbi->len = len;
1916 }
1917
1918 static void
1919 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1920 {
1921         struct jme_ring *txring = &(jme->txring[0]);
1922         struct txdesc *txdesc = txring->desc, *ctxdesc;
1923         struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1924         u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1925         int i, nr_frags = skb_shinfo(skb)->nr_frags;
1926         int mask = jme->tx_ring_mask;
1927         struct skb_frag_struct *frag;
1928         u32 len;
1929
1930         for (i = 0 ; i < nr_frags ; ++i) {
1931                 frag = &skb_shinfo(skb)->frags[i];
1932                 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1933                 ctxbi = txbi + ((idx + i + 2) & (mask));
1934
1935                 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1936                                  frag->page_offset, frag->size, hidma);
1937         }
1938
1939         len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1940         ctxdesc = txdesc + ((idx + 1) & (mask));
1941         ctxbi = txbi + ((idx + 1) & (mask));
1942         jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1943                         offset_in_page(skb->data), len, hidma);
1944
1945 }
1946
1947 static int
1948 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1949 {
1950         if (unlikely(skb_shinfo(skb)->gso_size &&
1951                         skb_header_cloned(skb) &&
1952                         pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1953                 dev_kfree_skb(skb);
1954                 return -1;
1955         }
1956
1957         return 0;
1958 }
1959
1960 static int
1961 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1962 {
1963         *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1964         if (*mss) {
1965                 *flags |= TXFLAG_LSEN;
1966
1967                 if (skb->protocol == htons(ETH_P_IP)) {
1968                         struct iphdr *iph = ip_hdr(skb);
1969
1970                         iph->check = 0;
1971                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1972                                                                 iph->daddr, 0,
1973                                                                 IPPROTO_TCP,
1974                                                                 0);
1975                 } else {
1976                         struct ipv6hdr *ip6h = ipv6_hdr(skb);
1977
1978                         tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1979                                                                 &ip6h->daddr, 0,
1980                                                                 IPPROTO_TCP,
1981                                                                 0);
1982                 }
1983
1984                 return 0;
1985         }
1986
1987         return 1;
1988 }
1989
1990 static void
1991 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1992 {
1993         if (skb->ip_summed == CHECKSUM_PARTIAL) {
1994                 u8 ip_proto;
1995
1996                 switch (skb->protocol) {
1997                 case htons(ETH_P_IP):
1998                         ip_proto = ip_hdr(skb)->protocol;
1999                         break;
2000                 case htons(ETH_P_IPV6):
2001                         ip_proto = ipv6_hdr(skb)->nexthdr;
2002                         break;
2003                 default:
2004                         ip_proto = 0;
2005                         break;
2006                 }
2007
2008                 switch (ip_proto) {
2009                 case IPPROTO_TCP:
2010                         *flags |= TXFLAG_TCPCS;
2011                         break;
2012                 case IPPROTO_UDP:
2013                         *flags |= TXFLAG_UDPCS;
2014                         break;
2015                 default:
2016                         netif_err(jme, tx_err, jme->dev, "Error upper layer protocol\n");
2017                         break;
2018                 }
2019         }
2020 }
2021
2022 static inline void
2023 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
2024 {
2025         if (vlan_tx_tag_present(skb)) {
2026                 *flags |= TXFLAG_TAGON;
2027                 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
2028         }
2029 }
2030
2031 static int
2032 jme_fill_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
2033 {
2034         struct jme_ring *txring = &(jme->txring[0]);
2035         struct txdesc *txdesc;
2036         struct jme_buffer_info *txbi;
2037         u8 flags;
2038
2039         txdesc = (struct txdesc *)txring->desc + idx;
2040         txbi = txring->bufinf + idx;
2041
2042         txdesc->dw[0] = 0;
2043         txdesc->dw[1] = 0;
2044         txdesc->dw[2] = 0;
2045         txdesc->dw[3] = 0;
2046         txdesc->desc1.pktsize = cpu_to_le16(skb->len);
2047         /*
2048          * Set OWN bit at final.
2049          * When kernel transmit faster than NIC.
2050          * And NIC trying to send this descriptor before we tell
2051          * it to start sending this TX queue.
2052          * Other fields are already filled correctly.
2053          */
2054         wmb();
2055         flags = TXFLAG_OWN | TXFLAG_INT;
2056         /*
2057          * Set checksum flags while not tso
2058          */
2059         if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
2060                 jme_tx_csum(jme, skb, &flags);
2061         jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
2062         jme_map_tx_skb(jme, skb, idx);
2063         txdesc->desc1.flags = flags;
2064         /*
2065          * Set tx buffer info after telling NIC to send
2066          * For better tx_clean timing
2067          */
2068         wmb();
2069         txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
2070         txbi->skb = skb;
2071         txbi->len = skb->len;
2072         txbi->start_xmit = jiffies;
2073         if (!txbi->start_xmit)
2074                 txbi->start_xmit = (0UL-1);
2075
2076         return 0;
2077 }
2078
2079 static void
2080 jme_stop_queue_if_full(struct jme_adapter *jme)
2081 {
2082         struct jme_ring *txring = &(jme->txring[0]);
2083         struct jme_buffer_info *txbi = txring->bufinf;
2084         int idx = atomic_read(&txring->next_to_clean);
2085
2086         txbi += idx;
2087
2088         smp_wmb();
2089         if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
2090                 netif_stop_queue(jme->dev);
2091                 netif_info(jme, tx_queued, jme->dev, "TX Queue Paused\n");
2092                 smp_wmb();
2093                 if (atomic_read(&txring->nr_free)
2094                         >= (jme->tx_wake_threshold)) {
2095                         netif_wake_queue(jme->dev);
2096                         netif_info(jme, tx_queued, jme->dev, "TX Queue Fast Waked\n");
2097                 }
2098         }
2099
2100         if (unlikely(txbi->start_xmit &&
2101                         (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
2102                         txbi->skb)) {
2103                 netif_stop_queue(jme->dev);
2104                 netif_info(jme, tx_queued, jme->dev,
2105                            "TX Queue Stopped %d@%lu\n", idx, jiffies);
2106         }
2107 }
2108
2109 /*
2110  * This function is already protected by netif_tx_lock()
2111  */
2112
2113 static netdev_tx_t
2114 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
2115 {
2116         struct jme_adapter *jme = netdev_priv(netdev);
2117         int idx;
2118
2119         if (unlikely(jme_expand_header(jme, skb))) {
2120                 ++(NET_STAT(jme).tx_dropped);
2121                 return NETDEV_TX_OK;
2122         }
2123
2124         idx = jme_alloc_txdesc(jme, skb);
2125
2126         if (unlikely(idx < 0)) {
2127                 netif_stop_queue(netdev);
2128                 netif_err(jme, tx_err, jme->dev,
2129                           "BUG! Tx ring full when queue awake!\n");
2130
2131                 return NETDEV_TX_BUSY;
2132         }
2133
2134         jme_fill_tx_desc(jme, skb, idx);
2135
2136         jwrite32(jme, JME_TXCS, jme->reg_txcs |
2137                                 TXCS_SELECT_QUEUE0 |
2138                                 TXCS_QUEUE0S |
2139                                 TXCS_ENABLE);
2140
2141         tx_dbg(jme, "xmit: %d+%d@%lu\n",
2142                idx, skb_shinfo(skb)->nr_frags + 2, jiffies);
2143         jme_stop_queue_if_full(jme);
2144
2145         return NETDEV_TX_OK;
2146 }
2147
2148 static void
2149 jme_set_unicastaddr(struct net_device *netdev)
2150 {
2151         struct jme_adapter *jme = netdev_priv(netdev);
2152         u32 val;
2153
2154         val = (netdev->dev_addr[3] & 0xff) << 24 |
2155               (netdev->dev_addr[2] & 0xff) << 16 |
2156               (netdev->dev_addr[1] & 0xff) <<  8 |
2157               (netdev->dev_addr[0] & 0xff);
2158         jwrite32(jme, JME_RXUMA_LO, val);
2159         val = (netdev->dev_addr[5] & 0xff) << 8 |
2160               (netdev->dev_addr[4] & 0xff);
2161         jwrite32(jme, JME_RXUMA_HI, val);
2162 }
2163
2164 static int
2165 jme_set_macaddr(struct net_device *netdev, void *p)
2166 {
2167         struct jme_adapter *jme = netdev_priv(netdev);
2168         struct sockaddr *addr = p;
2169
2170         if (netif_running(netdev))
2171                 return -EBUSY;
2172
2173         spin_lock_bh(&jme->macaddr_lock);
2174         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2175         jme_set_unicastaddr(netdev);
2176         spin_unlock_bh(&jme->macaddr_lock);
2177
2178         return 0;
2179 }
2180
2181 static void
2182 jme_set_multi(struct net_device *netdev)
2183 {
2184         struct jme_adapter *jme = netdev_priv(netdev);
2185         u32 mc_hash[2] = {};
2186
2187         spin_lock_bh(&jme->rxmcs_lock);
2188
2189         jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
2190
2191         if (netdev->flags & IFF_PROMISC) {
2192                 jme->reg_rxmcs |= RXMCS_ALLFRAME;
2193         } else if (netdev->flags & IFF_ALLMULTI) {
2194                 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
2195         } else if (netdev->flags & IFF_MULTICAST) {
2196                 struct netdev_hw_addr *ha;
2197                 int bit_nr;
2198
2199                 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
2200                 netdev_for_each_mc_addr(ha, netdev) {
2201                         bit_nr = ether_crc(ETH_ALEN, ha->addr) & 0x3F;
2202                         mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2203                 }
2204
2205                 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2206                 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2207         }
2208
2209         wmb();
2210         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2211
2212         spin_unlock_bh(&jme->rxmcs_lock);
2213 }
2214
2215 static int
2216 jme_change_mtu(struct net_device *netdev, int new_mtu)
2217 {
2218         struct jme_adapter *jme = netdev_priv(netdev);
2219
2220         if (new_mtu == jme->old_mtu)
2221                 return 0;
2222
2223         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2224                 ((new_mtu) < IPV6_MIN_MTU))
2225                 return -EINVAL;
2226
2227         if (new_mtu > 4000) {
2228                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2229                 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2230                 jme_restart_rx_engine(jme);
2231         } else {
2232                 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2233                 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2234                 jme_restart_rx_engine(jme);
2235         }
2236
2237         netdev->mtu = new_mtu;
2238         netdev_update_features(netdev);
2239
2240         jme_reset_link(jme);
2241
2242         return 0;
2243 }
2244
2245 static void
2246 jme_tx_timeout(struct net_device *netdev)
2247 {
2248         struct jme_adapter *jme = netdev_priv(netdev);
2249
2250         jme->phylink = 0;
2251         jme_reset_phy_processor(jme);
2252         if (test_bit(JME_FLAG_SSET, &jme->flags))
2253                 jme_set_settings(netdev, &jme->old_ecmd);
2254
2255         /*
2256          * Force to Reset the link again
2257          */
2258         jme_reset_link(jme);
2259 }
2260
2261 static inline void jme_pause_rx(struct jme_adapter *jme)
2262 {
2263         atomic_dec(&jme->link_changing);
2264
2265         jme_set_rx_pcc(jme, PCC_OFF);
2266         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2267                 JME_NAPI_DISABLE(jme);
2268         } else {
2269                 tasklet_disable(&jme->rxclean_task);
2270                 tasklet_disable(&jme->rxempty_task);
2271         }
2272 }
2273
2274 static inline void jme_resume_rx(struct jme_adapter *jme)
2275 {
2276         struct dynpcc_info *dpi = &(jme->dpi);
2277
2278         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2279                 JME_NAPI_ENABLE(jme);
2280         } else {
2281                 tasklet_hi_enable(&jme->rxclean_task);
2282                 tasklet_hi_enable(&jme->rxempty_task);
2283         }
2284         dpi->cur                = PCC_P1;
2285         dpi->attempt            = PCC_P1;
2286         dpi->cnt                = 0;
2287         jme_set_rx_pcc(jme, PCC_P1);
2288
2289         atomic_inc(&jme->link_changing);
2290 }
2291
2292 static void
2293 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2294 {
2295         struct jme_adapter *jme = netdev_priv(netdev);
2296
2297         jme_pause_rx(jme);
2298         jme->vlgrp = grp;
2299         jme_resume_rx(jme);
2300 }
2301
2302 static void
2303 jme_get_drvinfo(struct net_device *netdev,
2304                      struct ethtool_drvinfo *info)
2305 {
2306         struct jme_adapter *jme = netdev_priv(netdev);
2307
2308         strcpy(info->driver, DRV_NAME);
2309         strcpy(info->version, DRV_VERSION);
2310         strcpy(info->bus_info, pci_name(jme->pdev));
2311 }
2312
2313 static int
2314 jme_get_regs_len(struct net_device *netdev)
2315 {
2316         return JME_REG_LEN;
2317 }
2318
2319 static void
2320 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2321 {
2322         int i;
2323
2324         for (i = 0 ; i < len ; i += 4)
2325                 p[i >> 2] = jread32(jme, reg + i);
2326 }
2327
2328 static void
2329 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2330 {
2331         int i;
2332         u16 *p16 = (u16 *)p;
2333
2334         for (i = 0 ; i < reg_nr ; ++i)
2335                 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2336 }
2337
2338 static void
2339 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2340 {
2341         struct jme_adapter *jme = netdev_priv(netdev);
2342         u32 *p32 = (u32 *)p;
2343
2344         memset(p, 0xFF, JME_REG_LEN);
2345
2346         regs->version = 1;
2347         mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2348
2349         p32 += 0x100 >> 2;
2350         mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2351
2352         p32 += 0x100 >> 2;
2353         mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2354
2355         p32 += 0x100 >> 2;
2356         mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2357
2358         p32 += 0x100 >> 2;
2359         mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2360 }
2361
2362 static int
2363 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2364 {
2365         struct jme_adapter *jme = netdev_priv(netdev);
2366
2367         ecmd->tx_coalesce_usecs = PCC_TX_TO;
2368         ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2369
2370         if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2371                 ecmd->use_adaptive_rx_coalesce = false;
2372                 ecmd->rx_coalesce_usecs = 0;
2373                 ecmd->rx_max_coalesced_frames = 0;
2374                 return 0;
2375         }
2376
2377         ecmd->use_adaptive_rx_coalesce = true;
2378
2379         switch (jme->dpi.cur) {
2380         case PCC_P1:
2381                 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2382                 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2383                 break;
2384         case PCC_P2:
2385                 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2386                 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2387                 break;
2388         case PCC_P3:
2389                 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2390                 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2391                 break;
2392         default:
2393                 break;
2394         }
2395
2396         return 0;
2397 }
2398
2399 static int
2400 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2401 {
2402         struct jme_adapter *jme = netdev_priv(netdev);
2403         struct dynpcc_info *dpi = &(jme->dpi);
2404
2405         if (netif_running(netdev))
2406                 return -EBUSY;
2407
2408         if (ecmd->use_adaptive_rx_coalesce &&
2409             test_bit(JME_FLAG_POLL, &jme->flags)) {
2410                 clear_bit(JME_FLAG_POLL, &jme->flags);
2411                 jme->jme_rx = netif_rx;
2412                 jme->jme_vlan_rx = vlan_hwaccel_rx;
2413                 dpi->cur                = PCC_P1;
2414                 dpi->attempt            = PCC_P1;
2415                 dpi->cnt                = 0;
2416                 jme_set_rx_pcc(jme, PCC_P1);
2417                 jme_interrupt_mode(jme);
2418         } else if (!(ecmd->use_adaptive_rx_coalesce) &&
2419                    !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2420                 set_bit(JME_FLAG_POLL, &jme->flags);
2421                 jme->jme_rx = netif_receive_skb;
2422                 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2423                 jme_interrupt_mode(jme);
2424         }
2425
2426         return 0;
2427 }
2428
2429 static void
2430 jme_get_pauseparam(struct net_device *netdev,
2431                         struct ethtool_pauseparam *ecmd)
2432 {
2433         struct jme_adapter *jme = netdev_priv(netdev);
2434         u32 val;
2435
2436         ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2437         ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2438
2439         spin_lock_bh(&jme->phy_lock);
2440         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2441         spin_unlock_bh(&jme->phy_lock);
2442
2443         ecmd->autoneg =
2444                 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2445 }
2446
2447 static int
2448 jme_set_pauseparam(struct net_device *netdev,
2449                         struct ethtool_pauseparam *ecmd)
2450 {
2451         struct jme_adapter *jme = netdev_priv(netdev);
2452         u32 val;
2453
2454         if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2455                 (ecmd->tx_pause != 0)) {
2456
2457                 if (ecmd->tx_pause)
2458                         jme->reg_txpfc |= TXPFC_PF_EN;
2459                 else
2460                         jme->reg_txpfc &= ~TXPFC_PF_EN;
2461
2462                 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2463         }
2464
2465         spin_lock_bh(&jme->rxmcs_lock);
2466         if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2467                 (ecmd->rx_pause != 0)) {
2468
2469                 if (ecmd->rx_pause)
2470                         jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2471                 else
2472                         jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2473
2474                 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2475         }
2476         spin_unlock_bh(&jme->rxmcs_lock);
2477
2478         spin_lock_bh(&jme->phy_lock);
2479         val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2480         if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2481                 (ecmd->autoneg != 0)) {
2482
2483                 if (ecmd->autoneg)
2484                         val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2485                 else
2486                         val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2487
2488                 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2489                                 MII_ADVERTISE, val);
2490         }
2491         spin_unlock_bh(&jme->phy_lock);
2492
2493         return 0;
2494 }
2495
2496 static void
2497 jme_get_wol(struct net_device *netdev,
2498                 struct ethtool_wolinfo *wol)
2499 {
2500         struct jme_adapter *jme = netdev_priv(netdev);
2501
2502         wol->supported = WAKE_MAGIC | WAKE_PHY;
2503
2504         wol->wolopts = 0;
2505
2506         if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2507                 wol->wolopts |= WAKE_PHY;
2508
2509         if (jme->reg_pmcs & PMCS_MFEN)
2510                 wol->wolopts |= WAKE_MAGIC;
2511
2512 }
2513
2514 static int
2515 jme_set_wol(struct net_device *netdev,
2516                 struct ethtool_wolinfo *wol)
2517 {
2518         struct jme_adapter *jme = netdev_priv(netdev);
2519
2520         if (wol->wolopts & (WAKE_MAGICSECURE |
2521                                 WAKE_UCAST |
2522                                 WAKE_MCAST |
2523                                 WAKE_BCAST |
2524                                 WAKE_ARP))
2525                 return -EOPNOTSUPP;
2526
2527         jme->reg_pmcs = 0;
2528
2529         if (wol->wolopts & WAKE_PHY)
2530                 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2531
2532         if (wol->wolopts & WAKE_MAGIC)
2533                 jme->reg_pmcs |= PMCS_MFEN;
2534
2535         jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2536         device_set_wakeup_enable(&jme->pdev->dev, !!(jme->reg_pmcs));
2537
2538         return 0;
2539 }
2540
2541 static int
2542 jme_get_settings(struct net_device *netdev,
2543                      struct ethtool_cmd *ecmd)
2544 {
2545         struct jme_adapter *jme = netdev_priv(netdev);
2546         int rc;
2547
2548         spin_lock_bh(&jme->phy_lock);
2549         rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2550         spin_unlock_bh(&jme->phy_lock);
2551         return rc;
2552 }
2553
2554 static int
2555 jme_set_settings(struct net_device *netdev,
2556                      struct ethtool_cmd *ecmd)
2557 {
2558         struct jme_adapter *jme = netdev_priv(netdev);
2559         int rc, fdc = 0;
2560
2561         if (ethtool_cmd_speed(ecmd) == SPEED_1000
2562             && ecmd->autoneg != AUTONEG_ENABLE)
2563                 return -EINVAL;
2564
2565         /*
2566          * Check If user changed duplex only while force_media.
2567          * Hardware would not generate link change interrupt.
2568          */
2569         if (jme->mii_if.force_media &&
2570         ecmd->autoneg != AUTONEG_ENABLE &&
2571         (jme->mii_if.full_duplex != ecmd->duplex))
2572                 fdc = 1;
2573
2574         spin_lock_bh(&jme->phy_lock);
2575         rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2576         spin_unlock_bh(&jme->phy_lock);
2577
2578         if (!rc) {
2579                 if (fdc)
2580                         jme_reset_link(jme);
2581                 jme->old_ecmd = *ecmd;
2582                 set_bit(JME_FLAG_SSET, &jme->flags);
2583         }
2584
2585         return rc;
2586 }
2587
2588 static int
2589 jme_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
2590 {
2591         int rc;
2592         struct jme_adapter *jme = netdev_priv(netdev);
2593         struct mii_ioctl_data *mii_data = if_mii(rq);
2594         unsigned int duplex_chg;
2595
2596         if (cmd == SIOCSMIIREG) {
2597                 u16 val = mii_data->val_in;
2598                 if (!(val & (BMCR_RESET|BMCR_ANENABLE)) &&
2599                     (val & BMCR_SPEED1000))
2600                         return -EINVAL;
2601         }
2602
2603         spin_lock_bh(&jme->phy_lock);
2604         rc = generic_mii_ioctl(&jme->mii_if, mii_data, cmd, &duplex_chg);
2605         spin_unlock_bh(&jme->phy_lock);
2606
2607         if (!rc && (cmd == SIOCSMIIREG)) {
2608                 if (duplex_chg)
2609                         jme_reset_link(jme);
2610                 jme_get_settings(netdev, &jme->old_ecmd);
2611                 set_bit(JME_FLAG_SSET, &jme->flags);
2612         }
2613
2614         return rc;
2615 }
2616
2617 static u32
2618 jme_get_link(struct net_device *netdev)
2619 {
2620         struct jme_adapter *jme = netdev_priv(netdev);
2621         return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2622 }
2623
2624 static u32
2625 jme_get_msglevel(struct net_device *netdev)
2626 {
2627         struct jme_adapter *jme = netdev_priv(netdev);
2628         return jme->msg_enable;
2629 }
2630
2631 static void
2632 jme_set_msglevel(struct net_device *netdev, u32 value)
2633 {
2634         struct jme_adapter *jme = netdev_priv(netdev);
2635         jme->msg_enable = value;
2636 }
2637
2638 static u32
2639 jme_fix_features(struct net_device *netdev, u32 features)
2640 {
2641         if (netdev->mtu > 1900)
2642                 features &= ~(NETIF_F_ALL_TSO | NETIF_F_ALL_CSUM);
2643         return features;
2644 }
2645
2646 static int
2647 jme_set_features(struct net_device *netdev, u32 features)
2648 {
2649         struct jme_adapter *jme = netdev_priv(netdev);
2650
2651         spin_lock_bh(&jme->rxmcs_lock);
2652         if (features & NETIF_F_RXCSUM)
2653                 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2654         else
2655                 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2656         jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2657         spin_unlock_bh(&jme->rxmcs_lock);
2658
2659         return 0;
2660 }
2661
2662 static int
2663 jme_nway_reset(struct net_device *netdev)
2664 {
2665         struct jme_adapter *jme = netdev_priv(netdev);
2666         jme_restart_an(jme);
2667         return 0;
2668 }
2669
2670 static u8
2671 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2672 {
2673         u32 val;
2674         int to;
2675
2676         val = jread32(jme, JME_SMBCSR);
2677         to = JME_SMB_BUSY_TIMEOUT;
2678         while ((val & SMBCSR_BUSY) && --to) {
2679                 msleep(1);
2680                 val = jread32(jme, JME_SMBCSR);
2681         }
2682         if (!to) {
2683                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2684                 return 0xFF;
2685         }
2686
2687         jwrite32(jme, JME_SMBINTF,
2688                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2689                 SMBINTF_HWRWN_READ |
2690                 SMBINTF_HWCMD);
2691
2692         val = jread32(jme, JME_SMBINTF);
2693         to = JME_SMB_BUSY_TIMEOUT;
2694         while ((val & SMBINTF_HWCMD) && --to) {
2695                 msleep(1);
2696                 val = jread32(jme, JME_SMBINTF);
2697         }
2698         if (!to) {
2699                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2700                 return 0xFF;
2701         }
2702
2703         return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2704 }
2705
2706 static void
2707 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2708 {
2709         u32 val;
2710         int to;
2711
2712         val = jread32(jme, JME_SMBCSR);
2713         to = JME_SMB_BUSY_TIMEOUT;
2714         while ((val & SMBCSR_BUSY) && --to) {
2715                 msleep(1);
2716                 val = jread32(jme, JME_SMBCSR);
2717         }
2718         if (!to) {
2719                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2720                 return;
2721         }
2722
2723         jwrite32(jme, JME_SMBINTF,
2724                 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2725                 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2726                 SMBINTF_HWRWN_WRITE |
2727                 SMBINTF_HWCMD);
2728
2729         val = jread32(jme, JME_SMBINTF);
2730         to = JME_SMB_BUSY_TIMEOUT;
2731         while ((val & SMBINTF_HWCMD) && --to) {
2732                 msleep(1);
2733                 val = jread32(jme, JME_SMBINTF);
2734         }
2735         if (!to) {
2736                 netif_err(jme, hw, jme->dev, "SMB Bus Busy\n");
2737                 return;
2738         }
2739
2740         mdelay(2);
2741 }
2742
2743 static int
2744 jme_get_eeprom_len(struct net_device *netdev)
2745 {
2746         struct jme_adapter *jme = netdev_priv(netdev);
2747         u32 val;
2748         val = jread32(jme, JME_SMBCSR);
2749         return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2750 }
2751
2752 static int
2753 jme_get_eeprom(struct net_device *netdev,
2754                 struct ethtool_eeprom *eeprom, u8 *data)
2755 {
2756         struct jme_adapter *jme = netdev_priv(netdev);
2757         int i, offset = eeprom->offset, len = eeprom->len;
2758
2759         /*
2760          * ethtool will check the boundary for us
2761          */
2762         eeprom->magic = JME_EEPROM_MAGIC;
2763         for (i = 0 ; i < len ; ++i)
2764                 data[i] = jme_smb_read(jme, i + offset);
2765
2766         return 0;
2767 }
2768
2769 static int
2770 jme_set_eeprom(struct net_device *netdev,
2771                 struct ethtool_eeprom *eeprom, u8 *data)
2772 {
2773         struct jme_adapter *jme = netdev_priv(netdev);
2774         int i, offset = eeprom->offset, len = eeprom->len;
2775
2776         if (eeprom->magic != JME_EEPROM_MAGIC)
2777                 return -EINVAL;
2778
2779         /*
2780          * ethtool will check the boundary for us
2781          */
2782         for (i = 0 ; i < len ; ++i)
2783                 jme_smb_write(jme, i + offset, data[i]);
2784
2785         return 0;
2786 }
2787
2788 static const struct ethtool_ops jme_ethtool_ops = {
2789         .get_drvinfo            = jme_get_drvinfo,
2790         .get_regs_len           = jme_get_regs_len,
2791         .get_regs               = jme_get_regs,
2792         .get_coalesce           = jme_get_coalesce,
2793         .set_coalesce           = jme_set_coalesce,
2794         .get_pauseparam         = jme_get_pauseparam,
2795         .set_pauseparam         = jme_set_pauseparam,
2796         .get_wol                = jme_get_wol,
2797         .set_wol                = jme_set_wol,
2798         .get_settings           = jme_get_settings,
2799         .set_settings           = jme_set_settings,
2800         .get_link               = jme_get_link,
2801         .get_msglevel           = jme_get_msglevel,
2802         .set_msglevel           = jme_set_msglevel,
2803         .nway_reset             = jme_nway_reset,
2804         .get_eeprom_len         = jme_get_eeprom_len,
2805         .get_eeprom             = jme_get_eeprom,
2806         .set_eeprom             = jme_set_eeprom,
2807 };
2808
2809 static int
2810 jme_pci_dma64(struct pci_dev *pdev)
2811 {
2812         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2813             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
2814                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
2815                         return 1;
2816
2817         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250 &&
2818             !pci_set_dma_mask(pdev, DMA_BIT_MASK(40)))
2819                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40)))
2820                         return 1;
2821
2822         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
2823                 if (!pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
2824                         return 0;
2825
2826         return -1;
2827 }
2828
2829 static inline void
2830 jme_phy_init(struct jme_adapter *jme)
2831 {
2832         u16 reg26;
2833
2834         reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2835         jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2836 }
2837
2838 static inline void
2839 jme_check_hw_ver(struct jme_adapter *jme)
2840 {
2841         u32 chipmode;
2842
2843         chipmode = jread32(jme, JME_CHIPMODE);
2844
2845         jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2846         jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2847         jme->chip_main_rev = jme->chiprev & 0xF;
2848         jme->chip_sub_rev = (jme->chiprev >> 4) & 0xF;
2849 }
2850
2851 static const struct net_device_ops jme_netdev_ops = {
2852         .ndo_open               = jme_open,
2853         .ndo_stop               = jme_close,
2854         .ndo_validate_addr      = eth_validate_addr,
2855         .ndo_do_ioctl           = jme_ioctl,
2856         .ndo_start_xmit         = jme_start_xmit,
2857         .ndo_set_mac_address    = jme_set_macaddr,
2858         .ndo_set_multicast_list = jme_set_multi,
2859         .ndo_change_mtu         = jme_change_mtu,
2860         .ndo_tx_timeout         = jme_tx_timeout,
2861         .ndo_vlan_rx_register   = jme_vlan_rx_register,
2862         .ndo_fix_features       = jme_fix_features,
2863         .ndo_set_features       = jme_set_features,
2864 };
2865
2866 static int __devinit
2867 jme_init_one(struct pci_dev *pdev,
2868              const struct pci_device_id *ent)
2869 {
2870         int rc = 0, using_dac, i;
2871         struct net_device *netdev;
2872         struct jme_adapter *jme;
2873         u16 bmcr, bmsr;
2874         u32 apmc;
2875
2876         /*
2877          * set up PCI device basics
2878          */
2879         rc = pci_enable_device(pdev);
2880         if (rc) {
2881                 pr_err("Cannot enable PCI device\n");
2882                 goto err_out;
2883         }
2884
2885         using_dac = jme_pci_dma64(pdev);
2886         if (using_dac < 0) {
2887                 pr_err("Cannot set PCI DMA Mask\n");
2888                 rc = -EIO;
2889                 goto err_out_disable_pdev;
2890         }
2891
2892         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2893                 pr_err("No PCI resource region found\n");
2894                 rc = -ENOMEM;
2895                 goto err_out_disable_pdev;
2896         }
2897
2898         rc = pci_request_regions(pdev, DRV_NAME);
2899         if (rc) {
2900                 pr_err("Cannot obtain PCI resource region\n");
2901                 goto err_out_disable_pdev;
2902         }
2903
2904         pci_set_master(pdev);
2905
2906         /*
2907          * alloc and init net device
2908          */
2909         netdev = alloc_etherdev(sizeof(*jme));
2910         if (!netdev) {
2911                 pr_err("Cannot allocate netdev structure\n");
2912                 rc = -ENOMEM;
2913                 goto err_out_release_regions;
2914         }
2915         netdev->netdev_ops = &jme_netdev_ops;
2916         netdev->ethtool_ops             = &jme_ethtool_ops;
2917         netdev->watchdog_timeo          = TX_TIMEOUT;
2918         netdev->hw_features             =       NETIF_F_IP_CSUM |
2919                                                 NETIF_F_IPV6_CSUM |
2920                                                 NETIF_F_SG |
2921                                                 NETIF_F_TSO |
2922                                                 NETIF_F_TSO6 |
2923                                                 NETIF_F_RXCSUM;
2924         netdev->features                =       NETIF_F_IP_CSUM |
2925                                                 NETIF_F_IPV6_CSUM |
2926                                                 NETIF_F_SG |
2927                                                 NETIF_F_TSO |
2928                                                 NETIF_F_TSO6 |
2929                                                 NETIF_F_HW_VLAN_TX |
2930                                                 NETIF_F_HW_VLAN_RX;
2931         if (using_dac)
2932                 netdev->features        |=      NETIF_F_HIGHDMA;
2933
2934         SET_NETDEV_DEV(netdev, &pdev->dev);
2935         pci_set_drvdata(pdev, netdev);
2936
2937         /*
2938          * init adapter info
2939          */
2940         jme = netdev_priv(netdev);
2941         jme->pdev = pdev;
2942         jme->dev = netdev;
2943         jme->jme_rx = netif_rx;
2944         jme->jme_vlan_rx = vlan_hwaccel_rx;
2945         jme->old_mtu = netdev->mtu = 1500;
2946         jme->phylink = 0;
2947         jme->tx_ring_size = 1 << 10;
2948         jme->tx_ring_mask = jme->tx_ring_size - 1;
2949         jme->tx_wake_threshold = 1 << 9;
2950         jme->rx_ring_size = 1 << 9;
2951         jme->rx_ring_mask = jme->rx_ring_size - 1;
2952         jme->msg_enable = JME_DEF_MSG_ENABLE;
2953         jme->regs = ioremap(pci_resource_start(pdev, 0),
2954                              pci_resource_len(pdev, 0));
2955         if (!(jme->regs)) {
2956                 pr_err("Mapping PCI resource region error\n");
2957                 rc = -ENOMEM;
2958                 goto err_out_free_netdev;
2959         }
2960
2961         if (no_pseudohp) {
2962                 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2963                 jwrite32(jme, JME_APMC, apmc);
2964         } else if (force_pseudohp) {
2965                 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2966                 jwrite32(jme, JME_APMC, apmc);
2967         }
2968
2969         NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2970
2971         spin_lock_init(&jme->phy_lock);
2972         spin_lock_init(&jme->macaddr_lock);
2973         spin_lock_init(&jme->rxmcs_lock);
2974
2975         atomic_set(&jme->link_changing, 1);
2976         atomic_set(&jme->rx_cleaning, 1);
2977         atomic_set(&jme->tx_cleaning, 1);
2978         atomic_set(&jme->rx_empty, 1);
2979
2980         tasklet_init(&jme->pcc_task,
2981                      jme_pcc_tasklet,
2982                      (unsigned long) jme);
2983         tasklet_init(&jme->linkch_task,
2984                      jme_link_change_tasklet,
2985                      (unsigned long) jme);
2986         tasklet_init(&jme->txclean_task,
2987                      jme_tx_clean_tasklet,
2988                      (unsigned long) jme);
2989         tasklet_init(&jme->rxclean_task,
2990                      jme_rx_clean_tasklet,
2991                      (unsigned long) jme);
2992         tasklet_init(&jme->rxempty_task,
2993                      jme_rx_empty_tasklet,
2994                      (unsigned long) jme);
2995         tasklet_disable_nosync(&jme->linkch_task);
2996         tasklet_disable_nosync(&jme->txclean_task);
2997         tasklet_disable_nosync(&jme->rxclean_task);
2998         tasklet_disable_nosync(&jme->rxempty_task);
2999         jme->dpi.cur = PCC_P1;
3000
3001         jme->reg_ghc = 0;
3002         jme->reg_rxcs = RXCS_DEFAULT;
3003         jme->reg_rxmcs = RXMCS_DEFAULT;
3004         jme->reg_txpfc = 0;
3005         jme->reg_pmcs = PMCS_MFEN;
3006         jme->reg_gpreg1 = GPREG1_DEFAULT;
3007
3008         if (jme->reg_rxmcs & RXMCS_CHECKSUM)
3009                 netdev->features |= NETIF_F_RXCSUM;
3010
3011         /*
3012          * Get Max Read Req Size from PCI Config Space
3013          */
3014         pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
3015         jme->mrrs &= PCI_DCSR_MRRS_MASK;
3016         switch (jme->mrrs) {
3017         case MRRS_128B:
3018                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
3019                 break;
3020         case MRRS_256B:
3021                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
3022                 break;
3023         default:
3024                 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
3025                 break;
3026         }
3027
3028         /*
3029          * Must check before reset_mac_processor
3030          */
3031         jme_check_hw_ver(jme);
3032         jme->mii_if.dev = netdev;
3033         if (jme->fpgaver) {
3034                 jme->mii_if.phy_id = 0;
3035                 for (i = 1 ; i < 32 ; ++i) {
3036                         bmcr = jme_mdio_read(netdev, i, MII_BMCR);
3037                         bmsr = jme_mdio_read(netdev, i, MII_BMSR);
3038                         if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
3039                                 jme->mii_if.phy_id = i;
3040                                 break;
3041                         }
3042                 }
3043
3044                 if (!jme->mii_if.phy_id) {
3045                         rc = -EIO;
3046                         pr_err("Can not find phy_id\n");
3047                         goto err_out_unmap;
3048                 }
3049
3050                 jme->reg_ghc |= GHC_LINK_POLL;
3051         } else {
3052                 jme->mii_if.phy_id = 1;
3053         }
3054         if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
3055                 jme->mii_if.supports_gmii = true;
3056         else
3057                 jme->mii_if.supports_gmii = false;
3058         jme->mii_if.phy_id_mask = 0x1F;
3059         jme->mii_if.reg_num_mask = 0x1F;
3060         jme->mii_if.mdio_read = jme_mdio_read;
3061         jme->mii_if.mdio_write = jme_mdio_write;
3062
3063         jme_clear_pm(jme);
3064         pci_set_power_state(jme->pdev, PCI_D0);
3065         device_set_wakeup_enable(&pdev->dev, true);
3066
3067         jme_set_phyfifo_5level(jme);
3068         jme->pcirev = pdev->revision;
3069         if (!jme->fpgaver)
3070                 jme_phy_init(jme);
3071         jme_phy_off(jme);
3072
3073         /*
3074          * Reset MAC processor and reload EEPROM for MAC Address
3075          */
3076         jme_reset_mac_processor(jme);
3077         rc = jme_reload_eeprom(jme);
3078         if (rc) {
3079                 pr_err("Reload eeprom for reading MAC Address error\n");
3080                 goto err_out_unmap;
3081         }
3082         jme_load_macaddr(netdev);
3083
3084         /*
3085          * Tell stack that we are not ready to work until open()
3086          */
3087         netif_carrier_off(netdev);
3088
3089         rc = register_netdev(netdev);
3090         if (rc) {
3091                 pr_err("Cannot register net device\n");
3092                 goto err_out_unmap;
3093         }
3094
3095         netif_info(jme, probe, jme->dev, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3096                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250) ?
3097                    "JMC250 Gigabit Ethernet" :
3098                    (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC260) ?
3099                    "JMC260 Fast Ethernet" : "Unknown",
3100                    (jme->fpgaver != 0) ? " (FPGA)" : "",
3101                    (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
3102                    jme->pcirev, netdev->dev_addr);
3103
3104         return 0;
3105
3106 err_out_unmap:
3107         iounmap(jme->regs);
3108 err_out_free_netdev:
3109         pci_set_drvdata(pdev, NULL);
3110         free_netdev(netdev);
3111 err_out_release_regions:
3112         pci_release_regions(pdev);
3113 err_out_disable_pdev:
3114         pci_disable_device(pdev);
3115 err_out:
3116         return rc;
3117 }
3118
3119 static void __devexit
3120 jme_remove_one(struct pci_dev *pdev)
3121 {
3122         struct net_device *netdev = pci_get_drvdata(pdev);
3123         struct jme_adapter *jme = netdev_priv(netdev);
3124
3125         unregister_netdev(netdev);
3126         iounmap(jme->regs);
3127         pci_set_drvdata(pdev, NULL);
3128         free_netdev(netdev);
3129         pci_release_regions(pdev);
3130         pci_disable_device(pdev);
3131
3132 }
3133
3134 static void
3135 jme_shutdown(struct pci_dev *pdev)
3136 {
3137         struct net_device *netdev = pci_get_drvdata(pdev);
3138         struct jme_adapter *jme = netdev_priv(netdev);
3139
3140         jme_powersave_phy(jme);
3141         pci_pme_active(pdev, true);
3142 }
3143
3144 #ifdef CONFIG_PM_SLEEP
3145 static int
3146 jme_suspend(struct device *dev)
3147 {
3148         struct pci_dev *pdev = to_pci_dev(dev);
3149         struct net_device *netdev = pci_get_drvdata(pdev);
3150         struct jme_adapter *jme = netdev_priv(netdev);
3151
3152         atomic_dec(&jme->link_changing);
3153
3154         netif_device_detach(netdev);
3155         netif_stop_queue(netdev);
3156         jme_stop_irq(jme);
3157
3158         tasklet_disable(&jme->txclean_task);
3159         tasklet_disable(&jme->rxclean_task);
3160         tasklet_disable(&jme->rxempty_task);
3161
3162         if (netif_carrier_ok(netdev)) {
3163                 if (test_bit(JME_FLAG_POLL, &jme->flags))
3164                         jme_polling_mode(jme);
3165
3166                 jme_stop_pcc_timer(jme);
3167                 jme_disable_rx_engine(jme);
3168                 jme_disable_tx_engine(jme);
3169                 jme_reset_mac_processor(jme);
3170                 jme_free_rx_resources(jme);
3171                 jme_free_tx_resources(jme);
3172                 netif_carrier_off(netdev);
3173                 jme->phylink = 0;
3174         }
3175
3176         tasklet_enable(&jme->txclean_task);
3177         tasklet_hi_enable(&jme->rxclean_task);
3178         tasklet_hi_enable(&jme->rxempty_task);
3179
3180         jme_powersave_phy(jme);
3181
3182         return 0;
3183 }
3184
3185 static int
3186 jme_resume(struct device *dev)
3187 {
3188         struct pci_dev *pdev = to_pci_dev(dev);
3189         struct net_device *netdev = pci_get_drvdata(pdev);
3190         struct jme_adapter *jme = netdev_priv(netdev);
3191
3192         jme_clear_pm(jme);
3193         jme_phy_on(jme);
3194         if (test_bit(JME_FLAG_SSET, &jme->flags))
3195                 jme_set_settings(netdev, &jme->old_ecmd);
3196         else
3197                 jme_reset_phy_processor(jme);
3198
3199         jme_start_irq(jme);
3200         netif_device_attach(netdev);
3201
3202         atomic_inc(&jme->link_changing);
3203
3204         jme_reset_link(jme);
3205
3206         return 0;
3207 }
3208
3209 static SIMPLE_DEV_PM_OPS(jme_pm_ops, jme_suspend, jme_resume);
3210 #define JME_PM_OPS (&jme_pm_ops)
3211
3212 #else
3213
3214 #define JME_PM_OPS NULL
3215 #endif
3216
3217 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl) = {
3218         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
3219         { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
3220         { }
3221 };
3222
3223 static struct pci_driver jme_driver = {
3224         .name           = DRV_NAME,
3225         .id_table       = jme_pci_tbl,
3226         .probe          = jme_init_one,
3227         .remove         = __devexit_p(jme_remove_one),
3228         .shutdown       = jme_shutdown,
3229         .driver.pm      = JME_PM_OPS,
3230 };
3231
3232 static int __init
3233 jme_init_module(void)
3234 {
3235         pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION);
3236         return pci_register_driver(&jme_driver);
3237 }
3238
3239 static void __exit
3240 jme_cleanup_module(void)
3241 {
3242         pci_unregister_driver(&jme_driver);
3243 }
3244
3245 module_init(jme_init_module);
3246 module_exit(jme_cleanup_module);
3247
3248 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3249 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3250 MODULE_LICENSE("GPL");
3251 MODULE_VERSION(DRV_VERSION);
3252 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3253