]> bbs.cooldavid.org Git - net-next-2.6.git/blobdiff - drivers/net/tg3.c
tg3: Set card 57765 card reader MRRS to 1024B
[net-next-2.6.git] / drivers / net / tg3.c
index 9b8d8a227281b251b6a7a6cf91aacd19b808573c..a0ab89eb8bcc3fc52d352244cb91120e38995fe6 100644 (file)
@@ -67,8 +67,8 @@
 #include "tg3.h"
 
 #define DRV_MODULE_NAME                "tg3"
-#define DRV_MODULE_VERSION     "3.108"
-#define DRV_MODULE_RELDATE     "February 17, 2010"
+#define DRV_MODULE_VERSION     "3.109"
+#define DRV_MODULE_RELDATE     "April 2, 2010"
 
 #define TG3_DEF_MAC_MODE       0
 #define TG3_DEF_RX_MODE                0
@@ -581,11 +581,11 @@ static int tg3_ape_lock(struct tg3 *tp, int locknum)
                return 0;
 
        switch (locknum) {
-               case TG3_APE_LOCK_GRC:
-               case TG3_APE_LOCK_MEM:
-                       break;
-               default:
-                       return -EINVAL;
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return -EINVAL;
        }
 
        off = 4 * locknum;
@@ -619,11 +619,11 @@ static void tg3_ape_unlock(struct tg3 *tp, int locknum)
                return;
 
        switch (locknum) {
-               case TG3_APE_LOCK_GRC:
-               case TG3_APE_LOCK_MEM:
-                       break;
-               default:
-                       return;
+       case TG3_APE_LOCK_GRC:
+       case TG3_APE_LOCK_MEM:
+               break;
+       default:
+               return;
        }
 
        off = 4 * locknum;
@@ -1858,8 +1858,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
                /* Set Extended packet length bit for jumbo frames */
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
-       }
-       else {
+       } else {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
        }
 
@@ -1977,8 +1976,7 @@ out:
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
                tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
-       }
-       else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
+       } else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
                tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
                tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
                if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
@@ -3428,7 +3426,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
        ap->rxconfig = rx_cfg_reg;
        ret = ANEG_OK;
 
-       switch(ap->state) {
+       switch (ap->state) {
        case ANEG_STATE_UNKNOWN:
                if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
                        ap->state = ANEG_STATE_AN_ENABLE;
@@ -3466,11 +3464,10 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
                /* fallthru */
        case ANEG_STATE_RESTART:
                delta = ap->cur_time - ap->link_time;
-               if (delta > ANEG_STATE_SETTLE_TIME) {
+               if (delta > ANEG_STATE_SETTLE_TIME)
                        ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
-               } else {
+               else
                        ret = ANEG_TIMER_ENAB;
-               }
                break;
 
        case ANEG_STATE_DISABLE_LINK_OK:
@@ -3494,9 +3491,8 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp,
                break;
 
        case ANEG_STATE_ABILITY_DETECT:
-               if (ap->ability_match != 0 && ap->rxconfig != 0) {
+               if (ap->ability_match != 0 && ap->rxconfig != 0)
                        ap->state = ANEG_STATE_ACK_DETECT_INIT;
-               }
                break;
 
        case ANEG_STATE_ACK_DETECT_INIT:
@@ -4174,9 +4170,9 @@ static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
                                        current_duplex = DUPLEX_FULL;
                                else
                                        current_duplex = DUPLEX_HALF;
-                       }
-                       else
+                       } else {
                                current_link_up = 0;
+                       }
                }
        }
 
@@ -4244,10 +4240,9 @@ static void tg3_serdes_parallel_detect(struct tg3 *tp)
                                tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
                        }
                }
-       }
-       else if (netif_carrier_ok(tp->dev) &&
-                (tp->link_config.autoneg == AUTONEG_ENABLE) &&
-                (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
+       } else if (netif_carrier_ok(tp->dev) &&
+                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
+                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
                u32 phy2;
 
                /* Select expansion interrupt status register */
@@ -4270,13 +4265,12 @@ static int tg3_setup_phy(struct tg3 *tp, int force_reset)
 {
        int err;
 
-       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
+       if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
                err = tg3_setup_fiber_phy(tp, force_reset);
-       } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
+       else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
                err = tg3_setup_fiber_mii_phy(tp, force_reset);
-       } else {
+       else
                err = tg3_setup_copper_phy(tp, force_reset);
-       }
 
        if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
                u32 val, scale;
@@ -5560,9 +5554,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
 
                tcp_hdr(skb)->check = 0;
 
-       }
-       else if (skb->ip_summed == CHECKSUM_PARTIAL)
+       } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
                base_flags |= TXD_FLAG_TCPUDP_CSUM;
+       }
+
 #if TG3_VLAN_TAG_USED
        if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
                base_flags |= (TXD_FLAG_VLAN |
@@ -5932,9 +5927,9 @@ static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
                if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
                        tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
                        ethtool_op_set_tso(dev, 0);
-               }
-               else
+               } else {
                        tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
+               }
        } else {
                if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
                        tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
@@ -6565,35 +6560,35 @@ static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
                return;
 
        switch (kind) {
-               case RESET_KIND_INIT:
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
-                                       APE_HOST_SEG_SIG_MAGIC);
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
-                                       APE_HOST_SEG_LEN_MAGIC);
-                       apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
-                       tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
-                       tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
-                                       APE_HOST_DRIVER_ID_MAGIC);
-                       tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
-                                       APE_HOST_BEHAV_NO_PHYLOCK);
-
-                       event = APE_EVENT_STATUS_STATE_START;
-                       break;
-               case RESET_KIND_SHUTDOWN:
-                       /* With the interface we are currently using,
-                        * APE does not track driver state.  Wiping
-                        * out the HOST SEGMENT SIGNATURE forces
-                        * the APE to assume OS absent status.
-                        */
-                       tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
+       case RESET_KIND_INIT:
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
+                               APE_HOST_SEG_SIG_MAGIC);
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
+                               APE_HOST_SEG_LEN_MAGIC);
+               apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
+               tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
+               tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
+                               APE_HOST_DRIVER_ID_MAGIC);
+               tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
+                               APE_HOST_BEHAV_NO_PHYLOCK);
+
+               event = APE_EVENT_STATUS_STATE_START;
+               break;
+       case RESET_KIND_SHUTDOWN:
+               /* With the interface we are currently using,
+                * APE does not track driver state.  Wiping
+                * out the HOST SEGMENT SIGNATURE forces
+                * the APE to assume OS absent status.
+                */
+               tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
 
-                       event = APE_EVENT_STATUS_STATE_UNLOAD;
-                       break;
-               case RESET_KIND_SUSPEND:
-                       event = APE_EVENT_STATUS_STATE_SUSPEND;
-                       break;
-               default:
-                       return;
+               event = APE_EVENT_STATUS_STATE_UNLOAD;
+               break;
+       case RESET_KIND_SUSPEND:
+               event = APE_EVENT_STATUS_STATE_SUSPEND;
+               break;
+       default:
+               return;
        }
 
        event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
@@ -7585,9 +7580,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
 
        tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
 
-       if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
+       if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)
                tg3_abort_hw(tp, 1);
-       }
 
        if (reset_phy)
                tg3_phy_reset(tp);
@@ -7648,6 +7642,20 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                tw32(GRC_MODE, grc_mode);
        }
 
+       if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
+               u32 grc_mode = tr32(GRC_MODE);
+
+               /* Access the lower 1K of PL PCIE block registers. */
+               val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
+               tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
+
+               val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5);
+               tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
+                    val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
+
+               tw32(GRC_MODE, grc_mode);
+       }
+
        /* This works around an issue with Athlon chipsets on
         * B3 tigon3 silicon.  This bit has no effect on any
         * other revision.  But do not set this on PCI Express
@@ -7696,6 +7704,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
            GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
                val = tr32(TG3PCI_DMA_RW_CTRL) &
                      ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
+               if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0)
+                       val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
                tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
        } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
                   GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
@@ -7740,8 +7750,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
                        tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
                tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
                tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
-       }
-       else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
+       } else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
                int fw_len;
 
                fw_len = tp->fw_len;
@@ -8932,236 +8941,6 @@ err_out1:
        return err;
 }
 
-#if 0
-/*static*/ void tg3_dump_state(struct tg3 *tp)
-{
-       u32 val32, val32_2, val32_3, val32_4, val32_5;
-       u16 val16;
-       int i;
-       struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
-
-       pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
-       pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
-       printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
-              val16, val32);
-
-       /* MAC block */
-       printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
-              tr32(MAC_MODE), tr32(MAC_STATUS));
-       printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
-              tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
-       printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
-              tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
-       printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
-              tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
-
-       /* Send data initiator control block */
-       printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
-              tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
-       printk("       SNDDATAI_STATSCTRL[%08x]\n",
-              tr32(SNDDATAI_STATSCTRL));
-
-       /* Send data completion control block */
-       printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
-
-       /* Send BD ring selector block */
-       printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
-              tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
-
-       /* Send BD initiator control block */
-       printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
-              tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
-
-       /* Send BD completion control block */
-       printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
-
-       /* Receive list placement control block */
-       printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
-              tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
-       printk("       RCVLPC_STATSCTRL[%08x]\n",
-              tr32(RCVLPC_STATSCTRL));
-
-       /* Receive data and receive BD initiator control block */
-       printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
-              tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
-
-       /* Receive data completion control block */
-       printk("DEBUG: RCVDCC_MODE[%08x]\n",
-              tr32(RCVDCC_MODE));
-
-       /* Receive BD initiator control block */
-       printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
-              tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
-
-       /* Receive BD completion control block */
-       printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
-              tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
-
-       /* Receive list selector control block */
-       printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
-              tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
-
-       /* Mbuf cluster free block */
-       printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
-              tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
-
-       /* Host coalescing control block */
-       printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
-              tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
-       printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
-              tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
-              tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
-       printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
-              tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
-              tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
-       printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
-              tr32(HOSTCC_STATS_BLK_NIC_ADDR));
-       printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
-              tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
-
-       /* Memory arbiter control block */
-       printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
-              tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
-
-       /* Buffer manager control block */
-       printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
-              tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
-       printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
-              tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
-       printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
-              "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
-              tr32(BUFMGR_DMA_DESC_POOL_ADDR),
-              tr32(BUFMGR_DMA_DESC_POOL_SIZE));
-
-       /* Read DMA control block */
-       printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
-              tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
-
-       /* Write DMA control block */
-       printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
-              tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
-
-       /* DMA completion block */
-       printk("DEBUG: DMAC_MODE[%08x]\n",
-              tr32(DMAC_MODE));
-
-       /* GRC block */
-       printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
-              tr32(GRC_MODE), tr32(GRC_MISC_CFG));
-       printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
-              tr32(GRC_LOCAL_CTRL));
-
-       /* TG3_BDINFOs */
-       printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_JUMBO_BD + 0x0),
-              tr32(RCVDBDI_JUMBO_BD + 0x4),
-              tr32(RCVDBDI_JUMBO_BD + 0x8),
-              tr32(RCVDBDI_JUMBO_BD + 0xc));
-       printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_STD_BD + 0x0),
-              tr32(RCVDBDI_STD_BD + 0x4),
-              tr32(RCVDBDI_STD_BD + 0x8),
-              tr32(RCVDBDI_STD_BD + 0xc));
-       printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
-              tr32(RCVDBDI_MINI_BD + 0x0),
-              tr32(RCVDBDI_MINI_BD + 0x4),
-              tr32(RCVDBDI_MINI_BD + 0x8),
-              tr32(RCVDBDI_MINI_BD + 0xc));
-
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
-       printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4);
-
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
-       printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4);
-
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
-       tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
-       printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
-              val32, val32_2, val32_3, val32_4, val32_5);
-
-       /* SW status block */
-       printk(KERN_DEBUG
-        "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
-              sblk->status,
-              sblk->status_tag,
-              sblk->rx_jumbo_consumer,
-              sblk->rx_consumer,
-              sblk->rx_mini_consumer,
-              sblk->idx[0].rx_producer,
-              sblk->idx[0].tx_consumer);
-
-       /* SW statistics block */
-       printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
-              ((u32 *)tp->hw_stats)[0],
-              ((u32 *)tp->hw_stats)[1],
-              ((u32 *)tp->hw_stats)[2],
-              ((u32 *)tp->hw_stats)[3]);
-
-       /* Mailboxes */
-       printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
-              tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
-              tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
-              tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
-              tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
-
-       /* NIC side send descriptors. */
-       for (i = 0; i < 6; i++) {
-               unsigned long txd;
-
-               txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
-                       + (i * sizeof(struct tg3_tx_buffer_desc));
-               printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(txd + 0x0), readl(txd + 0x4),
-                      readl(txd + 0x8), readl(txd + 0xc));
-       }
-
-       /* NIC side RX descriptors. */
-       for (i = 0; i < 6; i++) {
-               unsigned long rxd;
-
-               rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
-                       + (i * sizeof(struct tg3_rx_buffer_desc));
-               printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-               rxd += (4 * sizeof(u32));
-               printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-       }
-
-       for (i = 0; i < 6; i++) {
-               unsigned long rxd;
-
-               rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
-                       + (i * sizeof(struct tg3_rx_buffer_desc));
-               printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-               rxd += (4 * sizeof(u32));
-               printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
-                      i,
-                      readl(rxd + 0x0), readl(rxd + 0x4),
-                      readl(rxd + 0x8), readl(rxd + 0xc));
-       }
-}
-#endif
-
 static struct net_device_stats *tg3_get_stats(struct net_device *);
 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
 
@@ -9180,9 +8959,6 @@ static int tg3_close(struct net_device *dev)
        tg3_phy_stop(tp);
 
        tg3_full_lock(tp, 1);
-#if 0
-       tg3_dump_state(tp);
-#endif
 
        tg3_disable_ints(tp);
 
@@ -9424,9 +9200,8 @@ static inline u32 calc_crc(unsigned char *buf, int len)
 
                        reg >>= 1;
 
-                       if (tmp) {
+                       if (tmp)
                                reg ^= 0xedb88320;
-                       }
                }
        }
 
@@ -10380,8 +10155,7 @@ static int tg3_test_nvram(struct tg3 *tp)
                                for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
                                        parity[k++] = buf8[i] & msk;
                                i++;
-                       }
-                       else if (i == 16) {
+                       } else if (i == 16) {
                                int l;
                                u8 msk;
 
@@ -10844,9 +10618,9 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
                                     MII_TG3_EXT_CTRL_LNK3_LED_MODE);
                }
                tw32(MAC_MODE, mac_mode);
-       }
-       else
+       } else {
                return -EINVAL;
+       }
 
        err = -EIO;
 
@@ -11102,7 +10876,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                return phy_mii_ioctl(phydev, data, cmd);
        }
 
-       switch(cmd) {
+       switch (cmd) {
        case SIOCGMIIPHY:
                data->phy_id = tp->phy_addr;
 
@@ -12048,8 +11822,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 
        if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
                ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
-       }
-       else {
+       } else {
                u32 grc_mode;
 
                ret = tg3_nvram_lock(tp);
@@ -12069,8 +11842,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
 
                        ret = tg3_nvram_write_block_buffered(tp, offset, len,
                                buf);
-               }
-               else {
+               } else {
                        ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
                                buf);
                }
@@ -13119,8 +12891,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
                tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
                tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
                tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
-       }
-       else {
+       } else {
                struct pci_dev *bridge = NULL;
 
                do {
@@ -14018,11 +13789,10 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
        }
        pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 
-       if (to_device) {
+       if (to_device)
                tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
-       } else {
+       else
                tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
-       }
 
        ret = -ENODEV;
        for (i = 0; i < 40; i++) {
@@ -14227,10 +13997,10 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
                if (pci_dev_present(dma_wait_state_chipsets)) {
                        tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
                        tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
-               }
-               else
+               } else {
                        /* Safe to use the calculated DMA boundary. */
                        tp->dma_rwctrl = saved_dma_rwctrl;
+               }
 
                tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
        }