3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/delay.h> /* udelay */
11 #include "vb_setmode.h"
21 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
23 unsigned short XGINew_DRAMType[17][5] = {
24 {0x0C, 0x0A, 0x02, 0x40, 0x39}, {0x0D, 0x0A, 0x01, 0x40, 0x48},
25 {0x0C, 0x09, 0x02, 0x20, 0x35}, {0x0D, 0x09, 0x01, 0x20, 0x44},
26 {0x0C, 0x08, 0x02, 0x10, 0x31}, {0x0D, 0x08, 0x01, 0x10, 0x40},
27 {0x0C, 0x0A, 0x01, 0x20, 0x34}, {0x0C, 0x09, 0x01, 0x08, 0x32},
28 {0x0B, 0x08, 0x02, 0x08, 0x21}, {0x0C, 0x08, 0x01, 0x08, 0x30},
29 {0x0A, 0x08, 0x02, 0x04, 0x11}, {0x0B, 0x0A, 0x01, 0x10, 0x28},
30 {0x09, 0x08, 0x02, 0x02, 0x01}, {0x0B, 0x09, 0x01, 0x08, 0x24},
31 {0x0B, 0x08, 0x01, 0x04, 0x20}, {0x0A, 0x08, 0x01, 0x02, 0x10},
32 {0x09, 0x08, 0x01, 0x01, 0x00} };
34 static unsigned short XGINew_SDRDRAM_TYPE[13][5] = {
35 { 2, 12, 9, 64, 0x35},
36 { 1, 13, 9, 64, 0x44},
37 { 2, 12, 8, 32, 0x31},
38 { 2, 11, 9, 32, 0x25},
39 { 1, 12, 9, 32, 0x34},
40 { 1, 13, 8, 32, 0x40},
41 { 2, 11, 8, 16, 0x21},
42 { 1, 12, 8, 16, 0x30},
43 { 1, 11, 9, 16, 0x24},
47 { 1, 9, 8, 2, 0x00} };
49 static unsigned short XGINew_DDRDRAM_TYPE[4][5] = {
50 { 2, 12, 9, 64, 0x35},
51 { 2, 12, 8, 32, 0x31},
52 { 2, 11, 8, 16, 0x21},
53 { 2, 9, 8, 4, 0x01} };
55 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
56 { 2, 13, 9, 64, 0x45},
57 { 2, 12, 9, 32, 0x35},
58 { 2, 12, 8, 16, 0x31},
59 { 2, 11, 8, 8, 0x21} };
61 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
62 { 2, 14, 11, 128, 0x5D},
63 { 2, 14, 10, 64, 0x59},
64 { 2, 13, 11, 64, 0x4D},
65 { 2, 14, 9, 32, 0x55},
66 { 2, 13, 10, 32, 0x49},
67 { 2, 12, 11, 32, 0x3D},
68 { 2, 14, 8, 16, 0x51},
69 { 2, 13, 9, 16, 0x45},
70 { 2, 12, 10, 16, 0x39},
73 { 2, 12, 8, 4, 0x31} };
75 void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *, struct vb_device_info *);
76 void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *, struct vb_device_info *);
77 void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
78 void XGINew_SetDRAMModeRegister(struct vb_device_info *);
79 void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension);
80 void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
81 unsigned long, struct vb_device_info *);
82 unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
83 struct vb_device_info *pVBInfo);
84 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension);
86 int XGINew_DDRSizing340(struct xgi_hw_device_info *, struct vb_device_info *);
87 void XGINew_DisableRefresh(struct xgi_hw_device_info *, struct vb_device_info *) ;
88 void XGINew_CheckBusWidth_310(struct vb_device_info *) ;
89 int XGINew_SDRSizing(struct vb_device_info *);
90 int XGINew_DDRSizing(struct vb_device_info *);
91 void XGINew_EnableRefresh(struct xgi_hw_device_info *, struct vb_device_info *);
92 static int XGINew_RAMType; /*int ModeIDOffset,StandTable,CRT1Table,ScreenOffset,REFIndex;*/
94 static unsigned long UNIROM;
96 unsigned char ChkLFB(struct vb_device_info *);
97 void XGINew_Delay15us(unsigned long);
98 void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
99 unsigned long XGI_P3d4Port);
100 void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo);
101 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo);
102 void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension);
103 void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension);
104 void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
105 void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
106 void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
107 unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo);
108 void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo) ;
109 unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo);
111 static void DelayUS(unsigned long MicroSeconds)
113 udelay(MicroSeconds);
117 /* --------------------------------------------------------------------- */
118 /* Function : XGIInitNew */
122 /* --------------------------------------------------------------------- */
123 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
126 struct vb_device_info VBINF;
127 struct vb_device_info *pVBInfo = &VBINF;
128 unsigned char i, temp = 0, temp1 ;
129 // VBIOSVersion[ 5 ] ;
130 volatile unsigned char *pVideoMemory;
132 /* unsigned long j, k ; */
134 struct XGI_DSReg *pSR ;
138 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
140 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
142 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
144 pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
147 // Newdebugcode( 0x99 ) ;
150 /* if ( pVBInfo->ROMAddr == 0 ) */
153 if (pVBInfo->FBAddr == NULL) {
154 printk("\n pVBInfo->FBAddr == 0 ");
158 if (pVBInfo->BaseAddr == 0) {
159 printk("\npVBInfo->BaseAddr == 0 ");
164 XGINew_SetReg3( ( pVBInfo->BaseAddr + 0x12 ) , 0x67 ) ; /* 3c2 <- 67 ,ynlai */
166 pVBInfo->ISXPDOS = 0 ;
169 if ( !HwDeviceExtension->bIntegratedMMEnabled )
174 // VBIOSVersion[ 4 ] = 0x0 ;
176 /* 09/07/99 modify by domao */
178 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
179 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
180 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
181 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
182 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
183 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
184 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
185 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
186 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
187 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
188 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
189 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
190 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
191 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
192 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
193 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
194 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
197 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
198 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
200 InitTo330Pointer( HwDeviceExtension->jChipType, pVBInfo ) ;
203 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
206 XGINew_SetReg1( pVBInfo->P3c4 , 0x05 , 0x86 ) ;
209 /* GetXG21Sense (GPIO) */
210 if ( HwDeviceExtension->jChipType == XG21 )
212 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo) ;
214 if ( HwDeviceExtension->jChipType == XG27 )
216 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo) ;
220 /* 2.Reset Extended register */
222 for( i = 0x06 ; i < 0x20 ; i++ )
223 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
225 for( i = 0x21 ; i <= 0x27 ; i++ )
226 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
228 /* for( i = 0x06 ; i <= 0x27 ; i++ ) */
229 /* XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ; */
233 if(( HwDeviceExtension->jChipType >= XG20 ) || ( HwDeviceExtension->jChipType >= XG40))
235 for( i = 0x31 ; i <= 0x3B ; i++ )
236 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
240 for( i = 0x31 ; i <= 0x3D ; i++ )
241 XGINew_SetReg1( pVBInfo->P3c4 , i , 0 ) ;
245 if ( HwDeviceExtension->jChipType == XG42 ) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
246 XGINew_SetReg1( pVBInfo->P3c4 , 0x3B , 0xC0 ) ;
248 /* for( i = 0x30 ; i <= 0x3F ; i++ ) */
249 /* XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; */
251 for( i = 0x79 ; i <= 0x7C ; i++ )
252 XGINew_SetReg1( pVBInfo->P3d4 , i , 0 ) ; /* shampoo 0208 */
256 if ( HwDeviceExtension->jChipType >= XG20 )
257 XGINew_SetReg1( pVBInfo->P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ;
261 if ( HwDeviceExtension->jChipType >= XG40 )
262 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) ;
264 if ( HwDeviceExtension->jChipType < XG40 )
265 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ; */
269 /* 4.SetDefExt1Regs begin */
270 XGINew_SetReg1( pVBInfo->P3c4 , 0x07 , *pVBInfo->pSR07 ) ;
271 if ( HwDeviceExtension->jChipType == XG27 )
273 XGINew_SetReg1( pVBInfo->P3c4 , 0x40 , *pVBInfo->pSR40 ) ;
274 XGINew_SetReg1( pVBInfo->P3c4 , 0x41 , *pVBInfo->pSR41 ) ;
276 XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , 0x0F ) ;
277 XGINew_SetReg1( pVBInfo->P3c4 , 0x1F , *pVBInfo->pSR1F ) ;
278 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0x20 ) ; */
279 XGINew_SetReg1( pVBInfo->P3c4 , 0x20 , 0xA0 ) ; /* alan, 2001/6/26 Frame buffer can read/write SR20 */
280 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , 0x70 ) ; /* Hsuan, 2006/01/01 H/W request for slow corner chip */
281 if ( HwDeviceExtension->jChipType == XG27 ) /* Alan 12/07/2006 */
282 XGINew_SetReg1( pVBInfo->P3c4 , 0x36 , *pVBInfo->pSR36 ) ;
285 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x11 , SR11 ) ; */
289 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
291 // /* Set AGP Rate */
292 // temp1 = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
294 // if ( temp1 == 0x02 )
296 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
297 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
298 // XGINew_SetReg4( 0xcf8 , 0x8000002C ) ;
299 // VendorID = XGINew_GetReg3( 0x0cfc ) ;
300 // VendorID &= 0x0000FFFF ;
301 // XGINew_SetReg4( 0xcf8 , 0x8001002C ) ;
302 // GraphicVendorID = XGINew_GetReg3( 0x0cfc ) ;
303 // GraphicVendorID &= 0x0000FFFF;
305 // if ( ChipsetID == 0x7301039 )
306 /// XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x09 ) ;
308 // ChipsetID &= 0x0000FFFF ;
310 // if ( ( ChipsetID == 0x700E ) || ( ChipsetID == 0x1022 ) || ( ChipsetID == 0x1106 ) || ( ChipsetID == 0x10DE ) )
312 // if ( ChipsetID == 0x1106 )
314 // if ( ( VendorID == 0x1019 ) && ( GraphicVendorID == 0x1019 ) )
315 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0D ) ;
317 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
320 // XGINew_SetReg1( pVBInfo->P3d4 , 0x5F , 0x0B ) ;
326 if ( HwDeviceExtension->jChipType >= XG40 )
328 /* Set AGP customize registers (in SetDefAGPRegs) Start */
329 for( i = 0x47 ; i <= 0x4C ; i++ )
330 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ i - 0x47 ] ) ;
332 for( i = 0x70 ; i <= 0x71 ; i++ )
333 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 6 + i - 0x70 ] ) ;
335 for( i = 0x74 ; i <= 0x77 ; i++ )
336 XGINew_SetReg1( pVBInfo->P3d4 , i , pVBInfo->AGPReg[ 8 + i - 0x74 ] ) ;
337 /* Set AGP customize registers (in SetDefAGPRegs) End */
338 /*[Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
339 // XGINew_SetReg4( 0xcf8 , 0x80000000 ) ;
340 // ChipsetID = XGINew_GetReg3( 0x0cfc ) ;
341 // if ( ChipsetID == 0x25308086 )
342 // XGINew_SetReg1( pVBInfo->P3d4 , 0x77 , 0xF0 ) ;
344 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x50 , 0 , &Temp ) ; /* Get */
349 XGINew_SetReg1( pVBInfo->P3d4 , 0x48 , 0x20 ) ; /* CR48 */
353 if ( HwDeviceExtension->jChipType < XG40 )
354 XGINew_SetReg1( pVBInfo->P3d4 , 0x49 , pVBInfo->CR49[ 0 ] ) ;
358 XGINew_SetReg1( pVBInfo->P3c4 , 0x23 , *pVBInfo->pSR23 ) ;
359 XGINew_SetReg1( pVBInfo->P3c4 , 0x24 , *pVBInfo->pSR24 ) ;
360 XGINew_SetReg1( pVBInfo->P3c4 , 0x25 , pVBInfo->SR25[ 0 ] ) ;
363 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
366 XGI_UnLockCRT2( HwDeviceExtension, pVBInfo) ;
367 XGINew_SetRegANDOR( pVBInfo->Part0Port , 0x3F , 0xEF , 0x00 ) ; /* alan, disable VideoCapture */
368 XGINew_SetReg1( pVBInfo->Part1Port , 0x00 , 0x00 ) ;
369 temp1 = (unsigned char)XGINew_GetReg1(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
370 temp = (unsigned char)((temp1 >> 4) & 0x0F);
373 XGINew_SetReg1( pVBInfo->Part1Port , 0x02 , ( *pVBInfo->pCRT2Data_1_2 ) ) ;
377 XGINew_SetReg1( pVBInfo->Part1Port , 0x2E , 0x08 ) ; /* use VB */
381 XGINew_SetReg1( pVBInfo->P3c4 , 0x27 , 0x1F ) ;
383 if ( ( HwDeviceExtension->jChipType == XG42 ) && XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo) != 0 ) /* Not DDR */
385 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , ( *pVBInfo->pSR31 & 0x3F ) | 0x40 ) ;
386 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , ( *pVBInfo->pSR32 & 0xFC ) | 0x01 ) ;
390 XGINew_SetReg1( pVBInfo->P3c4 , 0x31 , *pVBInfo->pSR31 ) ;
391 XGINew_SetReg1( pVBInfo->P3c4 , 0x32 , *pVBInfo->pSR32 ) ;
393 XGINew_SetReg1( pVBInfo->P3c4 , 0x33 , *pVBInfo->pSR33 ) ;
397 if ( HwDeviceExtension->jChipType >= XG40 )
398 SetPowerConsume ( HwDeviceExtension , pVBInfo->P3c4); */
400 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
402 if ( XGI_BridgeIsOn( pVBInfo ) == 1 )
404 if ( pVBInfo->IF_DEF_LVDS == 0 )
406 XGINew_SetReg1( pVBInfo->Part2Port , 0x00 , 0x1C ) ;
407 XGINew_SetReg1( pVBInfo->Part4Port , 0x0D , *pVBInfo->pCRT2Data_4_D ) ;
408 XGINew_SetReg1( pVBInfo->Part4Port , 0x0E , *pVBInfo->pCRT2Data_4_E ) ;
409 XGINew_SetReg1( pVBInfo->Part4Port , 0x10 , *pVBInfo->pCRT2Data_4_10 ) ;
410 XGINew_SetReg1( pVBInfo->Part4Port , 0x0F , 0x3F ) ;
413 XGI_LockCRT2( HwDeviceExtension, pVBInfo ) ;
418 if ( HwDeviceExtension->jChipType < XG40 )
419 XGINew_SetReg1( pVBInfo->P3d4 , 0x83 , 0x00 ) ;
422 if (HwDeviceExtension->bSkipSense == 0) {
425 XGI_SenseCRT1(pVBInfo) ;
428 /* XGINew_DetectMonitor( HwDeviceExtension ) ; */
429 pVBInfo->IF_DEF_CH7007 = 0;
430 if ( ( HwDeviceExtension->jChipType == XG21 ) && (pVBInfo->IF_DEF_CH7007) )
433 XGI_GetSenseStatus( HwDeviceExtension , pVBInfo ) ; /* sense CRT2 */
437 if ( HwDeviceExtension->jChipType == XG21 )
441 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
442 temp = GetXG21FPBits( pVBInfo ) ;
443 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x01, temp ) ;
447 if ( HwDeviceExtension->jChipType == XG27 )
449 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x32 , ~Monitor1Sense , Monitor1Sense ) ; /* Z9 default has CRT */
450 temp = GetXG27FPBits( pVBInfo ) ;
451 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x37 , ~0x03, temp ) ;
456 if ( HwDeviceExtension->jChipType >= XG40 )
458 if ( HwDeviceExtension->jChipType >= XG40 )
460 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
463 XGINew_SetDRAMDefaultRegister340( HwDeviceExtension , pVBInfo->P3d4, pVBInfo ) ;
465 if (HwDeviceExtension->bSkipDramSizing == 1) {
466 pSR = HwDeviceExtension->pSR ;
469 while( pSR->jIdx != 0xFF )
471 XGINew_SetReg1( pVBInfo->P3c4 , pSR->jIdx , pSR->jVal ) ;
475 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
476 } /* SkipDramSizing */
482 XGINew_SetDRAMSize_340( HwDeviceExtension , pVBInfo) ;
492 /* SetDefExt2Regs begin */
495 temp =(unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x3A) ;
501 *pVBInfo->pSR21 &= 0xEF ;
503 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
505 *pVBInfo->pSR22 &= 0x20 ;
506 XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
509 // base = 0x80000000 ;
510 // OutPortLong( 0xcf8 , base ) ;
511 // Temp = ( InPortLong( 0xcfc ) & 0xFFFF ) ;
512 // if ( Temp == 0x1039 )
514 XGINew_SetReg1(pVBInfo->P3c4, 0x22, (unsigned char)((*pVBInfo->pSR22) & 0xFE));
518 // XGINew_SetReg1( pVBInfo->P3c4 , 0x22 , *pVBInfo->pSR22 ) ;
521 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , *pVBInfo->pSR21 ) ;
526 XGINew_ChkSenseStatus ( HwDeviceExtension , pVBInfo ) ;
527 XGINew_SetModeScratch ( HwDeviceExtension , pVBInfo ) ;
532 XGINew_SetReg1( pVBInfo->P3d4 , 0x8c , 0x87);
533 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31);
543 /* ============== alan ====================== */
545 /* --------------------------------------------------------------------- */
546 /* Function : XGINew_GetXG20DRAMType */
550 /* --------------------------------------------------------------------- */
551 unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
552 struct vb_device_info *pVBInfo)
554 unsigned char data, temp;
556 if ( HwDeviceExtension->jChipType < XG20 )
558 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
560 data = *pVBInfo->pSoftSetting & 0x07 ;
565 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ;
568 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x3A ) & 0x02 ) >> 1 ;
573 else if ( HwDeviceExtension->jChipType == XG27 )
575 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
577 data = *pVBInfo->pSoftSetting & 0x07 ;
580 temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3B ) ;
582 if (( temp & 0x88 )==0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
588 else if ( HwDeviceExtension->jChipType == XG21 )
590 XGINew_SetRegAND( pVBInfo->P3d4 , 0xB4 , ~0x02 ) ; /* Independent GPIO control */
592 XGINew_SetRegOR( pVBInfo->P3d4 , 0x4A , 0x80 ) ; /* Enable GPIOH read */
593 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ; /* GPIOF 0:DVI 1:DVO */
595 // for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily
596 if ( temp & 0x01 ) /* DVI read GPIOH */
601 XGINew_SetRegOR( pVBInfo->P3d4 , 0xB4 , 0x02 ) ;
606 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) & 0x01 ;
616 /* --------------------------------------------------------------------- */
617 /* Function : XGINew_Get310DRAMType */
621 /* --------------------------------------------------------------------- */
622 static unsigned char XGINew_Get310DRAMType(struct vb_device_info *pVBInfo)
626 /* index = XGINew_GetReg1( pVBInfo->P3c4 , 0x1A ) ; */
629 if ( *pVBInfo->pSoftSetting & SoftDRAMType )
630 data = *pVBInfo->pSoftSetting & 0x03 ;
632 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x3a ) & 0x03 ;
639 /* --------------------------------------------------------------------- */
640 /* Function : XGINew_Delay15us */
644 /* --------------------------------------------------------------------- */
646 void XGINew_Delay15us(unsigned long ulMicrsoSec)
652 /* --------------------------------------------------------------------- */
653 /* Function : XGINew_SDR_MRS */
657 /* --------------------------------------------------------------------- */
658 static void XGINew_SDR_MRS(struct vb_device_info *pVBInfo)
660 unsigned short data ;
662 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
663 data &= 0x3F ; /* SR16 D7=0,D6=0 */
664 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) low */
665 /* XGINew_Delay15us( 0x100 ) ; */
666 data |= 0x80 ; /* SR16 D7=1,D6=0 */
667 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ; /* enable mode register set(MRS) high */
668 /* XGINew_Delay15us( 0x100 ) ; */
672 /* --------------------------------------------------------------------- */
673 /* Function : XGINew_DDR1x_MRS_340 */
677 /* --------------------------------------------------------------------- */
678 static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
680 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
681 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
682 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
683 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
685 if ( *pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C ) /* Samsung F Die */
687 DelayUS( 3000 ) ; /* Delay 67 x 3 Delay15us */
688 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
689 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
690 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
691 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
695 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
696 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
697 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 0 ] ) ;
698 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 1 ] ) ;
700 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
702 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
703 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
704 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 2 ] ) ;
705 XGINew_SetReg1( P3c4 , 0x16 , pVBInfo->SR16[ 3 ] ) ;
706 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
710 /* --------------------------------------------------------------------- */
711 /* Function : XGINew_DDR2x_MRS_340 */
715 /* --------------------------------------------------------------------- */
716 static void XGINew_DDR2x_MRS_340(unsigned long P3c4,
717 struct vb_device_info *pVBInfo)
719 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
720 XGINew_SetReg1( P3c4 , 0x19 , 0x20 ) ;
721 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
722 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
724 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
725 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
726 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
727 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
728 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
730 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
732 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
733 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
734 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
735 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
736 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
737 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
740 /* --------------------------------------------------------------------- */
741 /* Function : XGINew_DDRII_Bootup_XG27 */
745 /* --------------------------------------------------------------------- */
746 static void XGINew_DDRII_Bootup_XG27(
747 struct xgi_hw_device_info *HwDeviceExtension,
749 struct vb_device_info *pVBInfo)
751 unsigned long P3d4 = P3c4 + 0x10 ;
752 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
753 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
755 /* Set Double Frequency */
756 /* XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; */ /* CR97 */
757 XGINew_SetReg1( P3d4 , 0x97 , *pVBInfo->pXGINew_CR97 ) ; /* CR97 */
761 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS2
762 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ; /* Set SR19 */
763 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
765 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
768 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS3
769 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ; /* Set SR19 */
770 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
772 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
775 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS1
776 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
777 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
779 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
782 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Enable
783 XGINew_SetReg1( P3c4 , 0x19 , 0x0A ) ; /* Set SR19 */
784 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
786 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
787 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ; /* Set SR16 */
788 /* DelayUS( 15 ) ; */
790 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B */
792 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* Set SR1B */
794 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* Set SR18 */ //MRS, DLL Reset
795 XGINew_SetReg1( P3c4 , 0x19 , 0x08 ) ; /* Set SR19 */
796 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ; /* Set SR16 */
799 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ; /* Set SR16 */
802 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ) ; /* Set SR18 */ //MRS, ODT
803 XGINew_SetReg1( P3c4 , 0x19 , 0x46 ) ; /* Set SR19 */
804 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
806 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
809 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* Set SR18 */ //EMRS
810 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ; /* Set SR19 */
811 XGINew_SetReg1( P3c4 , 0x16 , 0x20 ) ; /* Set SR16 */
813 XGINew_SetReg1( P3c4 , 0x16 , 0xA0 ) ; /* Set SR16 */
816 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* Set SR1B refresh control 000:close; 010:open */
821 /* --------------------------------------------------------------------- */
822 /* Function : XGINew_DDR2_MRS_XG20 */
826 /* --------------------------------------------------------------------- */
827 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
828 unsigned long P3c4, struct vb_device_info *pVBInfo)
830 unsigned long P3d4 = P3c4 + 0x10 ;
832 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
833 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
835 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
838 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
839 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
840 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
841 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
843 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
844 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
845 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
846 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
848 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
849 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
850 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
851 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
853 // XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS1 */
854 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
855 XGINew_SetReg1( P3c4 , 0x19 , 0x02 ) ;
856 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
857 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
860 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
862 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
865 //XGINew_SetReg1( P3c4 , 0x18 , 0x52 ) ; /* MRS2 */
866 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
867 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
868 XGINew_SetReg1( P3c4 , 0x16 , 0x05 ) ;
869 XGINew_SetReg1( P3c4 , 0x16 , 0x85 ) ;
875 /* --------------------------------------------------------------------- */
876 /* Function : XGINew_DDR2_MRS_XG20 */
880 /* --------------------------------------------------------------------- */
881 static void XGINew_DDR2_MRS_XG27(struct xgi_hw_device_info *HwDeviceExtension,
882 unsigned long P3c4, struct vb_device_info *pVBInfo)
884 unsigned long P3d4 = P3c4 + 0x10 ;
886 XGINew_RAMType = ( int )XGINew_GetXG20DRAMType( HwDeviceExtension , pVBInfo ) ;
887 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
889 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ; /* CR97 */
891 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS2 */
892 XGINew_SetReg1( P3c4 , 0x19 , 0x80 ) ;
894 XGINew_SetReg1( P3c4 , 0x16 , 0x10 ) ;
895 DelayUS( 15 ) ; ////06/11/23 XG27 A0 for CKE enable
896 XGINew_SetReg1( P3c4 , 0x16 , 0x90 ) ;
898 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS3 */
899 XGINew_SetReg1( P3c4 , 0x19 , 0xC0 ) ;
901 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
902 DelayUS( 15 ) ; ////06/11/22 XG27 A0
903 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
906 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ; /* EMRS1 */
907 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
909 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
910 DelayUS( 15 ) ; ////06/11/22 XG27 A0
911 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
913 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
914 XGINew_SetReg1( P3c4 , 0x19 , 0x06 ) ; ////[Billy]06/11/22 DLL Reset for XG27 Hynix DRAM
916 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
917 DelayUS( 15 ) ; ////06/11/23 XG27 A0
918 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
920 DelayUS( 30 ) ; ////06/11/23 XG27 A0 Start Auto-PreCharge
921 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
923 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ; /* SR1B */
926 XGINew_SetReg1( P3c4 , 0x18 , 0x42 ) ; /* MRS1 */
927 XGINew_SetReg1( P3c4 , 0x19 , 0x04 ) ; //// DLL without Reset for XG27 Hynix DRAM
929 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
931 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
933 XGINew_SetReg1( P3c4 , 0x18 , 0x80 ); ////XG27 OCD ON
934 XGINew_SetReg1( P3c4 , 0x19 , 0x46 );
936 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
938 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
940 XGINew_SetReg1( P3c4 , 0x18 , 0x00 );
941 XGINew_SetReg1( P3c4 , 0x19 , 0x40 );
943 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
945 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
947 DelayUS( 15 ) ; ////Start Auto-PreCharge
948 XGINew_SetReg1( P3c4 , 0x1B , 0x04 ) ; /* SR1B */
950 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ; /* SR1B */
955 /* --------------------------------------------------------------------- */
956 /* Function : XGINew_DDR1x_DefaultRegister */
960 /* --------------------------------------------------------------------- */
961 static void XGINew_DDR1x_DefaultRegister(
962 struct xgi_hw_device_info *HwDeviceExtension,
964 struct vb_device_info *pVBInfo)
966 unsigned long P3d4 = Port ,
969 if ( HwDeviceExtension->jChipType >= XG20 )
971 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
972 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
973 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
974 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
976 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
977 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
979 XGINew_DDR1x_MRS_XG20( P3c4 , pVBInfo) ;
983 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
985 switch( HwDeviceExtension->jChipType )
989 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
990 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
991 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
994 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
995 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
996 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
997 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
998 XGINew_GetReg1( P3d4 , 0x86 ) ;
999 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ;
1000 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1001 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1002 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1003 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1004 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1005 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1006 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1010 XGINew_SetReg1( P3d4 , 0x97 , 0x00 ) ;
1011 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1012 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1013 XGINew_DDR1x_MRS_340( P3c4 , pVBInfo ) ;
1018 /* --------------------------------------------------------------------- */
1019 /* Function : XGINew_DDR2x_DefaultRegister */
1023 /* --------------------------------------------------------------------- */
1024 static void XGINew_DDR2x_DefaultRegister(
1025 struct xgi_hw_device_info *HwDeviceExtension,
1027 struct vb_device_info *pVBInfo)
1029 unsigned long P3d4 = Port ,
1030 P3c4 = Port - 0x10 ;
1032 XGINew_SetMemoryClock( HwDeviceExtension , pVBInfo ) ;
1034 /* 20040906 Hsuan modify CR82, CR85, CR86 for XG42 */
1035 switch( HwDeviceExtension->jChipType )
1039 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1040 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1041 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1044 /* keep following setting sequence, each setting in the same reg insert idle */
1045 XGINew_SetReg1( P3d4 , 0x82 , 0x88 ) ;
1046 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1047 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1048 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1049 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1050 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1051 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1052 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1053 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1054 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1055 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1057 XGINew_SetReg1( P3d4 , 0x97 , 0x11 ) ;
1058 if ( HwDeviceExtension->jChipType == XG42 )
1060 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1064 XGINew_SetReg1( P3d4 , 0x98 , 0x03 ) ;
1066 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1068 XGINew_DDR2x_MRS_340( P3c4 , pVBInfo ) ;
1072 /* --------------------------------------------------------------------- */
1073 /* Function : XGINew_DDR2_DefaultRegister */
1077 /* --------------------------------------------------------------------- */
1078 static void XGINew_DDR2_DefaultRegister(
1079 struct xgi_hw_device_info *HwDeviceExtension,
1081 struct vb_device_info *pVBInfo)
1083 unsigned long P3d4 = Port ,
1084 P3c4 = Port - 0x10 ;
1086 /* keep following setting sequence, each setting in the same reg insert idle */
1087 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1088 XGINew_SetReg1( P3d4 , 0x86 , 0x00 ) ;
1089 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1090 XGINew_SetReg1( P3d4 , 0x86 , 0x88 ) ;
1091 XGINew_GetReg1( P3d4 , 0x86 ) ; /* Insert read command for delay */
1092 XGINew_SetReg1( P3d4 , 0x86 , pVBInfo->CR40[ 13 ][ XGINew_RAMType ] ) ; /* CR86 */
1093 XGINew_SetReg1( P3d4 , 0x82 , 0x77 ) ;
1094 XGINew_SetReg1( P3d4 , 0x85 , 0x00 ) ;
1095 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1096 XGINew_SetReg1( P3d4 , 0x85 , 0x88 ) ;
1097 XGINew_GetReg1( P3d4 , 0x85 ) ; /* Insert read command for delay */
1098 XGINew_SetReg1( P3d4 , 0x85 , pVBInfo->CR40[ 12 ][ XGINew_RAMType ] ) ; /* CR85 */
1099 if ( HwDeviceExtension->jChipType == XG27 )
1100 XGINew_SetReg1( P3d4 , 0x82 , pVBInfo->CR40[ 11 ][ XGINew_RAMType ] ) ; /* CR82 */
1102 XGINew_SetReg1( P3d4 , 0x82 , 0xA8 ) ; /* CR82 */
1104 XGINew_SetReg1( P3d4 , 0x98 , 0x01 ) ;
1105 XGINew_SetReg1( P3d4 , 0x9A , 0x02 ) ;
1106 if ( HwDeviceExtension->jChipType == XG27 )
1107 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , P3c4 , pVBInfo) ;
1109 XGINew_DDR2_MRS_XG20( HwDeviceExtension , P3c4, pVBInfo ) ;
1113 /* --------------------------------------------------------------------- */
1114 /* Function : XGINew_SetDRAMDefaultRegister340 */
1118 /* --------------------------------------------------------------------- */
1119 void XGINew_SetDRAMDefaultRegister340(struct xgi_hw_device_info *HwDeviceExtension,
1120 unsigned long Port, struct vb_device_info *pVBInfo)
1122 unsigned char temp, temp1, temp2, temp3 ,
1125 unsigned long P3d4 = Port ,
1126 P3c4 = Port - 0x10 ;
1128 XGINew_SetReg1( P3d4 , 0x6D , pVBInfo->CR40[ 8 ][ XGINew_RAMType ] ) ;
1129 XGINew_SetReg1( P3d4 , 0x68 , pVBInfo->CR40[ 5 ][ XGINew_RAMType ] ) ;
1130 XGINew_SetReg1( P3d4 , 0x69 , pVBInfo->CR40[ 6 ][ XGINew_RAMType ] ) ;
1131 XGINew_SetReg1( P3d4 , 0x6A , pVBInfo->CR40[ 7 ][ XGINew_RAMType ] ) ;
1134 for( i = 0 ; i < 4 ; i++ )
1136 temp = pVBInfo->CR6B[ XGINew_RAMType ][ i ] ; /* CR6B DQS fine tune delay */
1137 for( j = 0 ; j < 4 ; j++ )
1139 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1141 XGINew_SetReg1( P3d4 , 0x6B , temp2 ) ;
1142 XGINew_GetReg1( P3d4 , 0x6B ) ; /* Insert read command for delay */
1149 for( i = 0 ; i < 4 ; i++ )
1151 temp = pVBInfo->CR6E[ XGINew_RAMType ][ i ] ; /* CR6E DQM fine tune delay */
1152 for( j = 0 ; j < 4 ; j++ )
1154 temp1 = ( ( temp >> ( 2 * j ) ) & 0x03 ) << 2 ;
1156 XGINew_SetReg1( P3d4 , 0x6E , temp2 ) ;
1157 XGINew_GetReg1( P3d4 , 0x6E ) ; /* Insert read command for delay */
1164 for( k = 0 ; k < 4 ; k++ )
1166 XGINew_SetRegANDOR( P3d4 , 0x6E , 0xFC , temp3 ) ; /* CR6E_D[1:0] select channel */
1168 for( i = 0 ; i < 8 ; i++ )
1170 temp = pVBInfo->CR6F[ XGINew_RAMType ][ 8 * k + i ] ; /* CR6F DQ fine tune delay */
1171 for( j = 0 ; j < 4 ; j++ )
1173 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1175 XGINew_SetReg1( P3d4 , 0x6F , temp2 ) ;
1176 XGINew_GetReg1( P3d4 , 0x6F ) ; /* Insert read command for delay */
1184 XGINew_SetReg1( P3d4 , 0x80 , pVBInfo->CR40[ 9 ][ XGINew_RAMType ] ) ; /* CR80 */
1185 XGINew_SetReg1( P3d4 , 0x81 , pVBInfo->CR40[ 10 ][ XGINew_RAMType ] ) ; /* CR81 */
1188 temp = pVBInfo->CR89[ XGINew_RAMType ][ 0 ] ; /* CR89 terminator type select */
1189 for( j = 0 ; j < 4 ; j++ )
1191 temp1 = ( temp >> ( 2 * j ) ) & 0x03 ;
1193 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1194 XGINew_GetReg1( P3d4 , 0x89 ) ; /* Insert read command for delay */
1199 temp = pVBInfo->CR89[ XGINew_RAMType ][ 1 ] ;
1200 temp1 = temp & 0x03 ;
1202 XGINew_SetReg1( P3d4 , 0x89 , temp2 ) ;
1204 temp = pVBInfo->CR40[ 3 ][ XGINew_RAMType ] ;
1205 temp1 = temp & 0x0F ;
1206 temp2 = ( temp >> 4 ) & 0x07 ;
1207 temp3 = temp & 0x80 ;
1208 XGINew_SetReg1( P3d4 , 0x45 , temp1 ) ; /* CR45 */
1209 XGINew_SetReg1( P3d4 , 0x99 , temp2 ) ; /* CR99 */
1210 XGINew_SetRegOR( P3d4 , 0x40 , temp3 ) ; /* CR40_D[7] */
1211 XGINew_SetReg1( P3d4 , 0x41 , pVBInfo->CR40[ 0 ][ XGINew_RAMType ] ) ; /* CR41 */
1213 if ( HwDeviceExtension->jChipType == XG27 )
1214 XGINew_SetReg1( P3d4 , 0x8F , *pVBInfo->pCR8F ) ; /* CR8F */
1216 for( j = 0 ; j <= 6 ; j++ )
1217 XGINew_SetReg1( P3d4 , ( 0x90 + j ) , pVBInfo->CR40[ 14 + j ][ XGINew_RAMType ] ) ; /* CR90 - CR96 */
1219 for( j = 0 ; j <= 2 ; j++ )
1220 XGINew_SetReg1( P3d4 , ( 0xC3 + j ) , pVBInfo->CR40[ 21 + j ][ XGINew_RAMType ] ) ; /* CRC3 - CRC5 */
1222 for( j = 0 ; j < 2 ; j++ )
1223 XGINew_SetReg1( P3d4 , ( 0x8A + j ) , pVBInfo->CR40[ 1 + j ][ XGINew_RAMType ] ) ; /* CR8A - CR8B */
1225 if ( ( HwDeviceExtension->jChipType == XG41 ) || ( HwDeviceExtension->jChipType == XG42 ) )
1226 XGINew_SetReg1( P3d4 , 0x8C , 0x87 ) ;
1228 XGINew_SetReg1( P3d4 , 0x59 , pVBInfo->CR40[ 4 ][ XGINew_RAMType ] ) ; /* CR59 */
1230 XGINew_SetReg1( P3d4 , 0x83 , 0x09 ) ; /* CR83 */
1231 XGINew_SetReg1( P3d4 , 0x87 , 0x00 ) ; /* CR87 */
1232 XGINew_SetReg1( P3d4 , 0xCF , *pVBInfo->pCRCF ) ; /* CRCF */
1233 if ( XGINew_RAMType )
1235 //XGINew_SetReg1( P3c4 , 0x17 , 0xC0 ) ; /* SR17 DDRII */
1236 XGINew_SetReg1( P3c4 , 0x17 , 0x80 ) ; /* SR17 DDRII */
1237 if ( HwDeviceExtension->jChipType == XG27 )
1238 XGINew_SetReg1( P3c4 , 0x17 , 0x02 ) ; /* SR17 DDRII */
1242 XGINew_SetReg1( P3c4 , 0x17 , 0x00 ) ; /* SR17 DDR */
1243 XGINew_SetReg1( P3c4 , 0x1A , 0x87 ) ; /* SR1A */
1245 temp = XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) ;
1247 XGINew_DDR1x_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1250 XGINew_SetReg1( P3d4 , 0xB0 , 0x80 ) ; /* DDRII Dual frequency mode */
1251 XGINew_DDR2_DefaultRegister( HwDeviceExtension, P3d4, pVBInfo ) ;
1253 XGINew_SetReg1( P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1257 /* --------------------------------------------------------------------- */
1258 /* Function : XGINew_DDR_MRS */
1262 /* --------------------------------------------------------------------- */
1263 static void XGINew_DDR_MRS(struct vb_device_info *pVBInfo)
1265 unsigned short data ;
1267 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
1269 /* SR16 <- 1F,DF,2F,AF */
1270 /* yriver modified SR16 <- 0F,DF,0F,AF */
1271 /* enable DLL of DDR SD/SGRAM , SR16 D4=1 */
1272 data = pVideoMemory[ 0xFB ] ;
1273 /* data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ; */
1276 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1278 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1280 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1282 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1284 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1286 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1288 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1290 XGINew_SetReg1( pVBInfo->P3c4 , 0x16 , data ) ;
1295 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1297 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1303 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1308 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1309 if (!(pVBInfo->SR15[1][XGINew_RAMType] & 0x10))
1315 XGINew_SetReg1(pVBInfo->P3c4,0x16,data);
1321 /* check if read cache pointer is correct */
1325 /* --------------------------------------------------------------------- */
1326 /* Function : XGINew_VerifyMclk */
1330 /* --------------------------------------------------------------------- */
1331 static void XGINew_VerifyMclk(struct xgi_hw_device_info *HwDeviceExtension,
1332 struct vb_device_info *pVBInfo)
1334 unsigned char *pVideoMemory = pVBInfo->FBAddr ;
1335 unsigned char i, j ;
1336 unsigned short Temp , SR21 ;
1338 pVideoMemory[ 0 ] = 0xaa ; /* alan */
1339 pVideoMemory[ 16 ] = 0x55 ; /* note: PCI read cache is off */
1341 if ( ( pVideoMemory[ 0 ] != 0xaa ) || ( pVideoMemory[ 16 ] != 0x55 ) )
1343 for( i = 0 , j = 16 ; i < 2 ; i++ , j += 16 )
1345 SR21 = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1346 Temp = SR21 & 0xFB ; /* disable PCI post write buffer empty gating */
1347 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , Temp ) ;
1349 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1350 Temp |= 0x01 ; /* MCLK reset */
1353 Temp = XGINew_GetReg1( pVBInfo->P3c4 , 0x3C ) ;
1354 Temp &= 0xFE ; /* MCLK normal operation */
1356 XGINew_SetReg1( pVBInfo->P3c4 , 0x21 , SR21 ) ;
1358 pVideoMemory[ 16 + j ] = j ;
1359 if ( pVideoMemory[ 16 + j ] == j )
1361 pVideoMemory[ j ] = j ;
1372 /* --------------------------------------------------------------------- */
1373 /* Function : XGINew_SetDRAMSize_340 */
1377 /* --------------------------------------------------------------------- */
1378 void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1380 unsigned short data ;
1382 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1383 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1385 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1388 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1389 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1390 XGI_DisplayOff( HwDeviceExtension, pVBInfo );
1392 /*data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;*/
1394 /*XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ;*/ /* Turn OFF Display */
1395 XGINew_DDRSizing340( HwDeviceExtension, pVBInfo ) ;
1396 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1397 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1401 /* --------------------------------------------------------------------- */
1406 /* --------------------------------------------------------------------- */
1407 void XGINew_SetDRAMSize_310(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1409 unsigned short data ;
1410 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ,
1411 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1413 /* XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x40 ) ; */
1416 #ifdef XGI302 /* alan,should change value */
1417 XGINew_SetReg1( pVBInfo->P3d4 , 0x30 , 0x4D ) ;
1418 XGINew_SetReg1( pVBInfo->P3d4 , 0x31 , 0xc0 ) ;
1419 XGINew_SetReg1( pVBInfo->P3d4 , 0x34 , 0x3F ) ;
1422 XGISetModeNew( HwDeviceExtension , 0x2e ) ;
1424 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x21 ) ;
1425 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data & 0xDF)); /* disable read cache */
1427 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1 ) ;
1429 XGINew_SetReg1( pVBInfo->P3c4 , 0x01 , data ) ; /* Turn OFF Display */
1431 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x16 ) ;
1434 XGINew_SetReg1(pVBInfo->P3c4, 0x16, (unsigned short)(data | 0x0F)); /* assume lowest speed DRAM */
1436 XGINew_SetDRAMModeRegister( pVBInfo ) ;
1437 XGINew_DisableRefresh( HwDeviceExtension, pVBInfo ) ;
1438 XGINew_CheckBusWidth_310( pVBInfo) ;
1439 XGINew_VerifyMclk( HwDeviceExtension, pVBInfo ) ; /* alan 2000/7/3 */
1443 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1445 XGINew_SDRSizing( pVBInfo ) ;
1449 XGINew_DDRSizing( pVBInfo) ;
1455 XGINew_SetReg1(pVBInfo->P3c4, 0x16, pVBInfo->SR15[1][XGINew_RAMType]); /* restore SR16 */
1457 XGINew_EnableRefresh( HwDeviceExtension, pVBInfo ) ;
1458 data=XGINew_GetReg1( pVBInfo->P3c4 ,0x21 ) ;
1459 XGINew_SetReg1(pVBInfo->P3c4, 0x21, (unsigned short)(data | 0x20)); /* enable read cache */
1464 /* --------------------------------------------------------------------- */
1465 /* Function : XGINew_SetDRAMModeRegister340 */
1469 /* --------------------------------------------------------------------- */
1471 void XGINew_SetDRAMModeRegister340(struct xgi_hw_device_info *HwDeviceExtension)
1473 unsigned char data ;
1474 struct vb_device_info VBINF;
1475 struct vb_device_info *pVBInfo = &VBINF;
1476 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
1477 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
1478 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
1479 pVBInfo->ISXPDOS = 0 ;
1481 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
1482 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
1483 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
1484 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
1485 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
1486 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
1487 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
1488 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
1489 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
1490 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
1491 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
1492 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
1493 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
1494 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
1495 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
1496 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
1497 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
1498 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
1499 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
1501 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
1503 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
1505 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
1507 data = ( XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) & 0x02 ) >> 1 ;
1509 XGINew_DDR2x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1511 XGINew_DDR1x_MRS_340( pVBInfo->P3c4, pVBInfo ) ;
1514 XGINew_DDR2_MRS_XG20( HwDeviceExtension, pVBInfo->P3c4, pVBInfo);
1516 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
1519 /* --------------------------------------------------------------------- */
1520 /* Function : XGINew_SetDRAMModeRegister */
1524 /* --------------------------------------------------------------------- */
1525 void XGINew_SetDRAMModeRegister(struct vb_device_info *pVBInfo)
1527 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1529 XGINew_SDR_MRS(pVBInfo ) ;
1533 /* SR16 <- 0F,CF,0F,8F */
1534 XGINew_DDR_MRS( pVBInfo ) ;
1539 /* --------------------------------------------------------------------- */
1540 /* Function : XGINew_DisableRefresh */
1544 /* --------------------------------------------------------------------- */
1545 void XGINew_DisableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1547 unsigned short data ;
1550 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x1B ) ;
1552 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , data ) ;
1557 /* --------------------------------------------------------------------- */
1558 /* Function : XGINew_EnableRefresh */
1562 /* --------------------------------------------------------------------- */
1563 void XGINew_EnableRefresh(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
1566 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
1572 /* --------------------------------------------------------------------- */
1573 /* Function : XGINew_DisableChannelInterleaving */
1577 /* --------------------------------------------------------------------- */
1578 static void XGINew_DisableChannelInterleaving(int index,
1579 unsigned short XGINew_DDRDRAM_TYPE[][5],
1580 struct vb_device_info *pVBInfo)
1582 unsigned short data ;
1584 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1587 switch( XGINew_DDRDRAM_TYPE[ index ][ 3 ] )
1604 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1608 /* --------------------------------------------------------------------- */
1609 /* Function : XGINew_SetDRAMSizingType */
1613 /* --------------------------------------------------------------------- */
1614 static void XGINew_SetDRAMSizingType(int index,
1615 unsigned short DRAMTYPE_TABLE[][5],
1616 struct vb_device_info *pVBInfo)
1618 unsigned short data;
1620 data = DRAMTYPE_TABLE[ index ][ 4 ] ;
1621 XGINew_SetRegANDOR( pVBInfo->P3c4 , 0x13 , 0x80 , data ) ;
1623 /* should delay 50 ns */
1627 /* --------------------------------------------------------------------- */
1628 /* Function : XGINew_CheckBusWidth_310 */
1632 /* --------------------------------------------------------------------- */
1633 void XGINew_CheckBusWidth_310(struct vb_device_info *pVBInfo)
1635 unsigned short data ;
1636 volatile unsigned long *pVideoMemory ;
1638 pVideoMemory = (unsigned long *) pVBInfo->FBAddr;
1640 if ( XGINew_Get310DRAMType( pVBInfo ) < 2 )
1642 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1643 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x12 ) ;
1645 XGINew_SDR_MRS( pVBInfo ) ;
1647 XGINew_ChannelAB = 0 ;
1648 XGINew_DataBusWidth = 128 ;
1649 pVideoMemory[ 0 ] = 0x01234567L ;
1650 pVideoMemory[ 1 ] = 0x456789ABL ;
1651 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1652 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1653 pVideoMemory[ 4 ] = 0x55555555L ;
1654 pVideoMemory[ 5 ] = 0x55555555L ;
1655 pVideoMemory[ 6 ] = 0xFFFFFFFFL ;
1656 pVideoMemory[ 7 ] = 0xFFFFFFFFL ;
1658 if ( ( pVideoMemory[ 3 ] != 0xCDEF0123L ) || ( pVideoMemory[ 2 ] != 0x89ABCDEFL ) )
1661 XGINew_DataBusWidth = 64 ;
1662 XGINew_ChannelAB = 0 ;
1663 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1664 XGINew_SetReg1(pVBInfo->P3c4, 0x14, (unsigned short)(data & 0xFD));
1667 if ( ( pVideoMemory[ 1 ] != 0x456789ABL ) || ( pVideoMemory[ 0 ] != 0x01234567L ) )
1670 XGINew_DataBusWidth = 64 ;
1671 XGINew_ChannelAB = 1 ;
1672 data=XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1673 XGINew_SetReg1(pVBInfo->P3c4, 0x14,
1674 (unsigned short)((data & 0xFD) | 0x01));
1681 /* DDR Dual channel */
1682 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x00 ) ;
1683 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x02 ) ; /* Channel A, 64bit */
1685 XGINew_DDR_MRS( pVBInfo ) ;
1687 XGINew_ChannelAB = 0 ;
1688 XGINew_DataBusWidth = 64 ;
1689 pVideoMemory[ 0 ] = 0x01234567L ;
1690 pVideoMemory[ 1 ] = 0x456789ABL ;
1691 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1692 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1693 pVideoMemory[ 4 ] = 0x55555555L ;
1694 pVideoMemory[ 5 ] = 0x55555555L ;
1695 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1696 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1698 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1700 if ( pVideoMemory[ 0 ] == 0x01234567L )
1702 /* Channel A 64bit */
1708 if ( pVideoMemory[ 0 ] == 0x01234567L )
1710 /* Channel A 32bit */
1711 XGINew_DataBusWidth = 32 ;
1712 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x00 ) ;
1717 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x03 ) ; /* Channel B, 64bit */
1718 XGINew_DDR_MRS( pVBInfo);
1720 XGINew_ChannelAB = 1 ;
1721 XGINew_DataBusWidth = 64 ;
1722 pVideoMemory[ 0 ] = 0x01234567L ;
1723 pVideoMemory[ 1 ] = 0x456789ABL ;
1724 pVideoMemory[ 2 ] = 0x89ABCDEFL ;
1725 pVideoMemory[ 3 ] = 0xCDEF0123L ;
1726 pVideoMemory[ 4 ] = 0x55555555L ;
1727 pVideoMemory[ 5 ] = 0x55555555L ;
1728 pVideoMemory[ 6 ] = 0xAAAAAAAAL ;
1729 pVideoMemory[ 7 ] = 0xAAAAAAAAL ;
1731 if ( pVideoMemory[ 1 ] == 0x456789ABL )
1734 if ( pVideoMemory[ 0 ] == 0x01234567L )
1736 /* Channel B 64bit */
1746 if ( pVideoMemory[ 0 ] == 0x01234567L )
1749 XGINew_DataBusWidth = 32 ;
1750 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x01 ) ;
1761 /* --------------------------------------------------------------------- */
1762 /* Function : XGINew_SetRank */
1766 /* --------------------------------------------------------------------- */
1767 static int XGINew_SetRank(int index,
1768 unsigned char RankNo,
1769 unsigned char XGINew_ChannelAB,
1770 unsigned short DRAMTYPE_TABLE[][5],
1771 struct vb_device_info *pVBInfo)
1773 unsigned short data;
1776 if ( ( RankNo == 2 ) && ( DRAMTYPE_TABLE[ index ][ 0 ] == 2 ) )
1779 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] / 2 * XGINew_DataBusWidth / 32 ;
1781 if ( ( RankNo * RankSize ) <= 128 )
1785 while( ( RankSize >>= 1 ) > 0 )
1789 data |= ( RankNo - 1 ) << 2 ;
1790 data |= ( XGINew_DataBusWidth / 64 ) & 2 ;
1791 data |= XGINew_ChannelAB ;
1792 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1794 XGINew_SDR_MRS( pVBInfo ) ;
1802 /* --------------------------------------------------------------------- */
1803 /* Function : XGINew_SetDDRChannel */
1807 /* --------------------------------------------------------------------- */
1808 static int XGINew_SetDDRChannel(int index,
1809 unsigned char ChannelNo,
1810 unsigned char XGINew_ChannelAB,
1811 unsigned short DRAMTYPE_TABLE[][5],
1812 struct vb_device_info *pVBInfo)
1814 unsigned short data;
1817 RankSize = DRAMTYPE_TABLE[index][3]/2 * XGINew_DataBusWidth/32;
1818 /* RankSize = DRAMTYPE_TABLE[ index ][ 3 ] ; */
1819 if ( ChannelNo * RankSize <= 128 )
1822 while( ( RankSize >>= 1 ) > 0 )
1827 if ( ChannelNo == 2 )
1830 data |= ( XGINew_DataBusWidth / 32 ) & 2 ;
1831 data |= XGINew_ChannelAB ;
1832 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1834 XGINew_DDR_MRS( pVBInfo ) ;
1842 /* --------------------------------------------------------------------- */
1843 /* Function : XGINew_CheckColumn */
1847 /* --------------------------------------------------------------------- */
1848 static int XGINew_CheckColumn(int index,
1849 unsigned short DRAMTYPE_TABLE[][5],
1850 struct vb_device_info *pVBInfo)
1853 unsigned long Increment , Position ;
1855 /* Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 1 ) ; */
1856 Increment = 1 << ( 10 + XGINew_DataBusWidth / 64 ) ;
1858 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1860 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1861 Position += Increment ;
1865 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1867 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1868 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1870 Position += Increment;
1876 /* --------------------------------------------------------------------- */
1877 /* Function : XGINew_CheckBanks */
1881 /* --------------------------------------------------------------------- */
1882 static int XGINew_CheckBanks(int index,
1883 unsigned short DRAMTYPE_TABLE[][5],
1884 struct vb_device_info *pVBInfo)
1887 unsigned long Increment , Position ;
1889 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + XGINew_DataBusWidth / 64 + 2 ) ;
1891 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1893 /* pVBInfo->FBAddr[ Position ] = Position ; */
1894 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1895 Position += Increment ;
1898 for( i = 0 , Position = 0 ; i < 4 ; i++ )
1900 /* if (pVBInfo->FBAddr[ Position ] != Position ) */
1901 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1903 Position += Increment;
1909 /* --------------------------------------------------------------------- */
1910 /* Function : XGINew_CheckRank */
1914 /* --------------------------------------------------------------------- */
1915 static int XGINew_CheckRank(int RankNo, int index,
1916 unsigned short DRAMTYPE_TABLE[][5],
1917 struct vb_device_info *pVBInfo)
1920 unsigned long Increment , Position ;
1922 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1923 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1925 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1927 /* pVBInfo->FBAddr[ Position ] = Position ; */
1928 /* *( (unsigned long *)( pVBInfo->FBAddr ) ) = Position ; */
1929 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
1930 Position += Increment;
1933 for( i = 0 , Position = 0 ; i < 2 ; i++ )
1935 /* if ( pVBInfo->FBAddr[ Position ] != Position ) */
1936 /* if ( ( *(unsigned long *)( pVBInfo->FBAddr ) ) != Position ) */
1937 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
1939 Position += Increment;
1945 /* --------------------------------------------------------------------- */
1946 /* Function : XGINew_CheckDDRRank */
1950 /* --------------------------------------------------------------------- */
1951 static int XGINew_CheckDDRRank(int RankNo, int index,
1952 unsigned short DRAMTYPE_TABLE[][5],
1953 struct vb_device_info *pVBInfo)
1955 unsigned long Increment , Position ;
1956 unsigned short data ;
1958 Increment = 1 << ( DRAMTYPE_TABLE[ index ][ 2 ] + DRAMTYPE_TABLE[ index ][ 1 ] +
1959 DRAMTYPE_TABLE[ index ][ 0 ] + XGINew_DataBusWidth / 64 + RankNo ) ;
1961 Increment += Increment / 2 ;
1964 *((unsigned long *)(pVBInfo->FBAddr + Position + 0)) = 0x01234567;
1965 *((unsigned long *)(pVBInfo->FBAddr + Position + 1)) = 0x456789AB;
1966 *((unsigned long *)(pVBInfo->FBAddr + Position + 2)) = 0x55555555;
1967 *((unsigned long *)(pVBInfo->FBAddr + Position + 3)) = 0x55555555;
1968 *((unsigned long *)(pVBInfo->FBAddr + Position + 4)) = 0xAAAAAAAA;
1969 *((unsigned long *)(pVBInfo->FBAddr + Position + 5)) = 0xAAAAAAAA;
1971 if ((*(unsigned long *)(pVBInfo->FBAddr + 1)) == 0x456789AB)
1974 if ((*(unsigned long *)(pVBInfo->FBAddr + 0)) == 0x01234567)
1977 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) ;
1980 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ;
1981 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x15 ) ;
1983 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , data ) ;
1989 /* --------------------------------------------------------------------- */
1990 /* Function : XGINew_CheckRanks */
1994 /* --------------------------------------------------------------------- */
1995 static int XGINew_CheckRanks(int RankNo, int index,
1996 unsigned short DRAMTYPE_TABLE[][5],
1997 struct vb_device_info *pVBInfo)
2001 for( r = RankNo ; r >= 1 ; r-- )
2003 if ( !XGINew_CheckRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2007 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2010 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2017 /* --------------------------------------------------------------------- */
2018 /* Function : XGINew_CheckDDRRanks */
2022 /* --------------------------------------------------------------------- */
2023 static int XGINew_CheckDDRRanks(int RankNo, int index,
2024 unsigned short DRAMTYPE_TABLE[][5],
2025 struct vb_device_info *pVBInfo)
2029 for( r = RankNo ; r >= 1 ; r-- )
2031 if ( !XGINew_CheckDDRRank( r , index , DRAMTYPE_TABLE, pVBInfo ) )
2035 if ( !XGINew_CheckBanks( index , DRAMTYPE_TABLE, pVBInfo ) )
2038 if ( !XGINew_CheckColumn( index , DRAMTYPE_TABLE, pVBInfo ) )
2045 /* --------------------------------------------------------------------- */
2050 /* --------------------------------------------------------------------- */
2051 int XGINew_SDRSizing(struct vb_device_info *pVBInfo)
2056 for( i = 0 ; i < 13 ; i++ )
2058 XGINew_SetDRAMSizingType( i , XGINew_SDRDRAM_TYPE , pVBInfo) ;
2060 for( j = 2 ; j > 0 ; j-- )
2062 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB,
2063 XGINew_SDRDRAM_TYPE, pVBInfo))
2067 if ( XGINew_CheckRanks( j , i , XGINew_SDRDRAM_TYPE, pVBInfo) )
2076 /* --------------------------------------------------------------------- */
2077 /* Function : XGINew_SetDRAMSizeReg */
2081 /* --------------------------------------------------------------------- */
2082 static unsigned short XGINew_SetDRAMSizeReg(int index,
2083 unsigned short DRAMTYPE_TABLE[][5],
2084 struct vb_device_info *pVBInfo)
2086 unsigned short data = 0 , memsize = 0;
2088 unsigned char ChannelNo ;
2090 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 32 ;
2091 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2099 if( XGINew_ChannelAB == 3 )
2102 ChannelNo = XGINew_ChannelAB ;
2104 if ( ChannelNo * RankSize <= 256 )
2106 while( ( RankSize >>= 1 ) > 0 )
2111 memsize = data >> 4 ;
2113 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2114 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2116 /* data |= XGINew_ChannelAB << 2 ; */
2117 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2118 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2121 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2127 /* --------------------------------------------------------------------- */
2128 /* Function : XGINew_SetDRAMSize20Reg */
2132 /* --------------------------------------------------------------------- */
2133 static unsigned short XGINew_SetDRAMSize20Reg(int index,
2134 unsigned short DRAMTYPE_TABLE[][5],
2135 struct vb_device_info *pVBInfo)
2137 unsigned short data = 0 , memsize = 0;
2139 unsigned char ChannelNo ;
2141 RankSize = DRAMTYPE_TABLE[ index ][ 3 ] * XGINew_DataBusWidth / 8 ;
2142 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x13 ) ;
2150 if( XGINew_ChannelAB == 3 )
2153 ChannelNo = XGINew_ChannelAB ;
2155 if ( ChannelNo * RankSize <= 256 )
2157 while( ( RankSize >>= 1 ) > 0 )
2162 memsize = data >> 4 ;
2164 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
2165 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , ( XGINew_GetReg1( pVBInfo->P3c4 , 0x14 ) & 0x0F ) | ( data & 0xF0 ) ) ;
2168 /* data |= XGINew_ChannelAB << 2 ; */
2169 /* data |= ( XGINew_DataBusWidth / 64 ) << 1 ; */
2170 /* XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , data ) ; */
2173 /* XGINew_SetDRAMModeRegister340( pVBInfo ) ; */
2179 /* --------------------------------------------------------------------- */
2180 /* Function : XGINew_ReadWriteRest */
2184 /* --------------------------------------------------------------------- */
2185 static int XGINew_ReadWriteRest(unsigned short StopAddr,
2186 unsigned short StartAddr,
2187 struct vb_device_info *pVBInfo)
2190 unsigned long Position = 0 ;
2192 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
2194 for( i = StartAddr ; i <= StopAddr ; i++ )
2197 *((unsigned long *)(pVBInfo->FBAddr + Position)) = Position;
2200 DelayUS( 500 ) ; /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
2204 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2207 for( i = StartAddr ; i <= StopAddr ; i++ )
2210 if ((*(unsigned long *)(pVBInfo->FBAddr + Position)) != Position)
2217 /* --------------------------------------------------------------------- */
2218 /* Function : XGINew_CheckFrequence */
2222 /* --------------------------------------------------------------------- */
2223 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
2225 unsigned char data ;
2227 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2229 if ( ( data & 0x10 ) == 0 )
2231 data = XGINew_GetReg1( pVBInfo->P3c4 , 0x39 ) ;
2232 data = ( data & 0x02 ) >> 1 ;
2236 return( data & 0x01 ) ;
2240 /* --------------------------------------------------------------------- */
2241 /* Function : XGINew_CheckChannel */
2245 /* --------------------------------------------------------------------- */
2246 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
2247 struct vb_device_info *pVBInfo)
2251 switch( HwDeviceExtension->jChipType )
2255 data = XGINew_GetReg1( pVBInfo->P3d4 , 0x97 ) ;
2257 XGINew_ChannelAB = 1 ; /* XG20 "JUST" one channel */
2259 if ( data == 0 ) /* Single_32_16 */
2262 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x1000000)
2265 XGINew_DataBusWidth = 32 ; /* 32 bits */
2266 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 32bit */
2267 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2270 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2273 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2275 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* 22bit + 1 rank + 32bit */
2276 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2279 if ( XGINew_ReadWriteRest( 23 , 23 , pVBInfo ) == 1 )
2284 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2286 XGINew_DataBusWidth = 16 ; /* 16 bits */
2287 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* 22bit + 2 rank + 16bit */
2288 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ;
2291 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2294 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ;
2299 else /* Dual_16_8 */
2301 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x800000)
2304 XGINew_DataBusWidth = 16 ; /* 16 bits */
2305 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2306 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x41 ) ; /* 0x41:16Mx16 bit*/
2309 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2312 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2314 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2315 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x31 ) ; /* 0x31:8Mx16 bit*/
2318 if ( XGINew_ReadWriteRest( 22 , 22 , pVBInfo ) == 1 )
2324 if (( HwDeviceExtension->ulVideoMemorySize - 1 ) > 0x400000)
2326 XGINew_DataBusWidth = 8 ; /* 8 bits */
2327 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xB1 ) ; /* (0x31:12x8x2) 22bit + 2 rank */
2328 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ; /* 0x30:8Mx8 bit*/
2331 if ( XGINew_ReadWriteRest( 22 , 21 , pVBInfo ) == 1 )
2334 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x31 ) ; /* (0x31:12x8x2) 22bit + 1 rank */
2341 XGINew_DataBusWidth = 16 ; /* 16 bits */
2342 XGINew_ChannelAB = 1 ; /* Single channel */
2343 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x51 ) ; /* 32Mx16 bit*/
2346 if ( XGINew_CheckFrequence(pVBInfo) == 1 )
2348 XGINew_DataBusWidth = 32 ; /* 32 bits */
2349 XGINew_ChannelAB = 3 ; /* Quad Channel */
2350 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2351 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2353 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2356 XGINew_ChannelAB = 2 ; /* Dual channels */
2357 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2359 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2362 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x49 ) ;
2364 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2367 XGINew_ChannelAB = 3 ;
2368 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2369 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2371 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2374 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2376 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2379 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x39 ) ;
2383 XGINew_DataBusWidth = 64 ; /* 64 bits */
2384 XGINew_ChannelAB = 2 ; /* Dual channels */
2385 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2386 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2388 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2391 XGINew_ChannelAB = 1 ; /* Single channels */
2392 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2394 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2397 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x53 ) ;
2399 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2402 XGINew_ChannelAB = 2 ; /* Dual channels */
2403 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2404 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2406 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2409 XGINew_ChannelAB = 1 ; /* Single channels */
2410 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2412 if ( XGINew_ReadWriteRest( 8 , 4 , pVBInfo ) == 1 )
2415 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x43 ) ;
2422 XG42 SR14 D[3] Reserve
2423 D[2] = 1, Dual Channel
2426 It's Different from Other XG40 Series.
2428 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII, DDR2x */
2430 XGINew_DataBusWidth = 32 ; /* 32 bits */
2431 XGINew_ChannelAB = 2 ; /* 2 Channel */
2432 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2433 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x44 ) ;
2435 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2438 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2439 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x34 ) ;
2440 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2443 XGINew_ChannelAB = 1 ; /* Single Channel */
2444 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2445 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x40 ) ;
2447 if ( XGINew_ReadWriteRest( 23 , 22 , pVBInfo ) == 1 )
2451 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2452 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x30 ) ;
2457 XGINew_DataBusWidth = 64 ; /* 64 bits */
2458 XGINew_ChannelAB = 1 ; /* 1 channels */
2459 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2460 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x52 ) ;
2462 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2466 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2467 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x42 ) ;
2475 if ( XGINew_CheckFrequence(pVBInfo) == 1 ) /* DDRII */
2477 XGINew_DataBusWidth = 32 ; /* 32 bits */
2478 XGINew_ChannelAB = 3 ;
2479 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2480 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4C ) ;
2482 if ( XGINew_ReadWriteRest( 25 , 23 , pVBInfo ) == 1 )
2485 XGINew_ChannelAB = 2 ; /* 2 channels */
2486 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x48 ) ;
2488 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2491 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2492 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x3C ) ;
2494 if ( XGINew_ReadWriteRest( 24 , 23 , pVBInfo ) == 1 )
2495 XGINew_ChannelAB = 3 ; /* 4 channels */
2498 XGINew_ChannelAB = 2 ; /* 2 channels */
2499 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x38 ) ;
2504 XGINew_DataBusWidth = 64 ; /* 64 bits */
2505 XGINew_ChannelAB = 2 ; /* 2 channels */
2506 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0xA1 ) ;
2507 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x5A ) ;
2509 if ( XGINew_ReadWriteRest( 25 , 24 , pVBInfo ) == 1 )
2513 XGINew_SetReg1( pVBInfo->P3c4 , 0x13 , 0x21 ) ;
2514 XGINew_SetReg1( pVBInfo->P3c4 , 0x14 , 0x4A ) ;
2522 /* --------------------------------------------------------------------- */
2523 /* Function : XGINew_DDRSizing340 */
2527 /* --------------------------------------------------------------------- */
2528 int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2531 unsigned short memsize , addr ;
2533 XGINew_SetReg1( pVBInfo->P3c4 , 0x15 , 0x00 ) ; /* noninterleaving */
2534 XGINew_SetReg1( pVBInfo->P3c4 , 0x1C , 0x00 ) ; /* nontiling */
2535 XGINew_CheckChannel( HwDeviceExtension, pVBInfo ) ;
2538 if ( HwDeviceExtension->jChipType >= XG20 )
2540 for( i = 0 ; i < 12 ; i++ )
2542 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2543 memsize = XGINew_SetDRAMSize20Reg( i , XGINew_DDRDRAM_TYPE20, pVBInfo ) ;
2547 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2548 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr))
2551 if ( XGINew_ReadWriteRest( addr , 5, pVBInfo ) == 1 )
2557 for( i = 0 ; i < 4 ; i++ )
2559 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2560 memsize = XGINew_SetDRAMSizeReg( i , XGINew_DDRDRAM_TYPE340, pVBInfo ) ;
2565 addr = memsize + ( XGINew_ChannelAB - 2 ) + 20 ;
2566 if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long)(1 << addr))
2569 if ( XGINew_ReadWriteRest( addr , 9, pVBInfo ) == 1 )
2577 /* --------------------------------------------------------------------- */
2578 /* Function : XGINew_DDRSizing */
2582 /* --------------------------------------------------------------------- */
2583 int XGINew_DDRSizing(struct vb_device_info *pVBInfo)
2588 for( i = 0 ; i < 4 ; i++ )
2590 XGINew_SetDRAMSizingType( i , XGINew_DDRDRAM_TYPE, pVBInfo ) ;
2591 XGINew_DisableChannelInterleaving( i , XGINew_DDRDRAM_TYPE , pVBInfo) ;
2592 for( j = 2 ; j > 0 ; j-- )
2594 XGINew_SetDDRChannel( i , j , XGINew_ChannelAB , XGINew_DDRDRAM_TYPE , pVBInfo ) ;
2595 if (!XGINew_SetRank(i, (unsigned char)j, XGINew_ChannelAB,
2596 XGINew_DDRDRAM_TYPE, pVBInfo))
2600 if ( XGINew_CheckDDRRanks( j , i , XGINew_DDRDRAM_TYPE, pVBInfo ) )
2608 /* --------------------------------------------------------------------- */
2609 /* Function : XGINew_SetMemoryClock */
2613 /* --------------------------------------------------------------------- */
2614 void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2618 XGINew_SetReg1( pVBInfo->P3c4 , 0x28 , pVBInfo->MCLKData[ XGINew_RAMType ].SR28 ) ;
2619 XGINew_SetReg1( pVBInfo->P3c4 , 0x29 , pVBInfo->MCLKData[ XGINew_RAMType ].SR29 ) ;
2620 XGINew_SetReg1( pVBInfo->P3c4 , 0x2A , pVBInfo->MCLKData[ XGINew_RAMType ].SR2A ) ;
2624 XGINew_SetReg1( pVBInfo->P3c4 , 0x2E , pVBInfo->ECLKData[ XGINew_RAMType ].SR2E ) ;
2625 XGINew_SetReg1( pVBInfo->P3c4 , 0x2F , pVBInfo->ECLKData[ XGINew_RAMType ].SR2F ) ;
2626 XGINew_SetReg1( pVBInfo->P3c4 , 0x30 , pVBInfo->ECLKData[ XGINew_RAMType ].SR30 ) ;
2628 /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
2629 /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
2630 if ( HwDeviceExtension->jChipType == XG42 )
2632 if ( ( pVBInfo->MCLKData[ XGINew_RAMType ].SR28 == 0x1C ) && ( pVBInfo->MCLKData[ XGINew_RAMType ].SR29 == 0x01 )
2633 && ( ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x1C ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) )
2634 || ( ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2E == 0x22 ) && ( pVBInfo->ECLKData[ XGINew_RAMType ].SR2F == 0x01 ) ) ) )
2635 XGINew_SetReg1(pVBInfo->P3c4, 0x32, ((unsigned char)XGINew_GetReg1(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
2640 /* --------------------------------------------------------------------- */
2641 /* Function : ChkLFB */
2645 /* --------------------------------------------------------------------- */
2646 unsigned char ChkLFB(struct vb_device_info *pVBInfo)
2648 if (LFBDRAMTrap & XGINew_GetReg1(pVBInfo->P3d4 , 0x78))
2655 /* --------------------------------------------------------------------- */
2656 /* input : dx ,valid value : CR or second chip's CR */
2658 /* SetPowerConsume : */
2659 /* Description: reduce 40/43 power consumption in first chip or */
2660 /* in second chip, assume CR A1 D[6]="1" in this case */
2662 /* --------------------------------------------------------------------- */
2663 void SetPowerConsume(struct xgi_hw_device_info *HwDeviceExtension,
2664 unsigned long XGI_P3d4Port)
2666 unsigned long lTemp ;
2667 unsigned char bTemp;
2669 HwDeviceExtension->pQueryVGAConfigSpace( HwDeviceExtension , 0x08 , 0 , &lTemp ) ; /* Get */
2670 if ((lTemp&0xFF)==0)
2672 /* set CR58 D[5]=0 D[3]=0 */
2673 XGINew_SetRegAND( XGI_P3d4Port , 0x58 , 0xD7 ) ;
2674 bTemp = (unsigned char) XGINew_GetReg1(XGI_P3d4Port, 0xCB);
2679 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x20 ) ; /* CR58 D[5]=1 D[3]=0 */
2683 XGINew_SetRegANDOR( XGI_P3d4Port , 0x58 , 0xD7 , 0x08 ) ; /* CR58 D[5]=0 D[3]=1 */
2692 static void XGINew_InitVBIOSData(struct xgi_hw_device_info *HwDeviceExtension,
2693 struct vb_device_info *pVBInfo)
2696 /* unsigned long ROMAddr = (unsigned long)HwDeviceExtension->pjVirtualRomBase; */
2697 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2698 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2699 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2700 pVBInfo->ISXPDOS = 0 ;
2702 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2703 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2704 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2705 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2706 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2707 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2708 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2709 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2710 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2711 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2712 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2713 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2714 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2715 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2716 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2717 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2718 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2719 if ( HwDeviceExtension->jChipType < XG20 ) /* kuku 2004/06/25 */
2720 XGI_GetVBType( pVBInfo ) ; /* Run XGI_GetVBType before InitTo330Pointer */
2722 switch(HwDeviceExtension->jChipType)
2730 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2737 /* --------------------------------------------------------------------- */
2738 /* Function : ReadVBIOSTablData */
2742 /* --------------------------------------------------------------------- */
2743 void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
2745 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
2747 unsigned char j, k ;
2748 /* Volari customize data area end */
2750 if ( ChipType == XG21 )
2752 pVBInfo->IF_DEF_LVDS = 0 ;
2753 if (pVideoMemory[ 0x65 ] & 0x1)
2755 pVBInfo->IF_DEF_LVDS = 1 ;
2756 i = pVideoMemory[ 0x316 ] | ( pVideoMemory[ 0x317 ] << 8 );
2757 j = pVideoMemory[ i-1 ] ;
2763 pVBInfo->XG21_LVDSCapList[k].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2764 pVBInfo->XG21_LVDSCapList[k].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2765 pVBInfo->XG21_LVDSCapList[k].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2766 pVBInfo->XG21_LVDSCapList[k].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2767 pVBInfo->XG21_LVDSCapList[k].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2768 pVBInfo->XG21_LVDSCapList[k].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2769 pVBInfo->XG21_LVDSCapList[k].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2770 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2771 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2772 pVBInfo->XG21_LVDSCapList[k].VCLKData1 = pVideoMemory[ i + 18 ] ;
2773 pVBInfo->XG21_LVDSCapList[k].VCLKData2 = pVideoMemory[ i + 19 ] ;
2774 pVBInfo->XG21_LVDSCapList[k].PSC_S1 = pVideoMemory[ i + 20 ] ;
2775 pVBInfo->XG21_LVDSCapList[k].PSC_S2 = pVideoMemory[ i + 21 ] ;
2776 pVBInfo->XG21_LVDSCapList[k].PSC_S3 = pVideoMemory[ i + 22 ] ;
2777 pVBInfo->XG21_LVDSCapList[k].PSC_S4 = pVideoMemory[ i + 23 ] ;
2778 pVBInfo->XG21_LVDSCapList[k].PSC_S5 = pVideoMemory[ i + 24 ] ;
2783 (k < (sizeof(XGI21_LCDCapList)/sizeof(struct XGI21_LVDSCapStruct))));
2787 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability = pVideoMemory[ i ] | ( pVideoMemory[ i + 1 ] << 8 );
2788 pVBInfo->XG21_LVDSCapList[0].LVDSHT = pVideoMemory[ i + 2 ] | ( pVideoMemory[ i + 3 ] << 8 ) ;
2789 pVBInfo->XG21_LVDSCapList[0].LVDSVT = pVideoMemory[ i + 4 ] | ( pVideoMemory[ i + 5 ] << 8 );
2790 pVBInfo->XG21_LVDSCapList[0].LVDSHDE = pVideoMemory[ i + 6 ] | ( pVideoMemory[ i + 7 ] << 8 );
2791 pVBInfo->XG21_LVDSCapList[0].LVDSVDE = pVideoMemory[ i + 8 ] | ( pVideoMemory[ i + 9 ] << 8 );
2792 pVBInfo->XG21_LVDSCapList[0].LVDSHFP = pVideoMemory[ i + 10 ] | ( pVideoMemory[ i + 11 ] << 8 );
2793 pVBInfo->XG21_LVDSCapList[0].LVDSVFP = pVideoMemory[ i + 12 ] | ( pVideoMemory[ i + 13 ] << 8 );
2794 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC = pVideoMemory[ i + 14 ] | ( pVideoMemory[ i + 15 ] << 8 );
2795 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC = pVideoMemory[ i + 16 ] | ( pVideoMemory[ i + 17 ] << 8 );
2796 pVBInfo->XG21_LVDSCapList[0].VCLKData1 = pVideoMemory[ i + 18 ] ;
2797 pVBInfo->XG21_LVDSCapList[0].VCLKData2 = pVideoMemory[ i + 19 ] ;
2798 pVBInfo->XG21_LVDSCapList[0].PSC_S1 = pVideoMemory[ i + 20 ] ;
2799 pVBInfo->XG21_LVDSCapList[0].PSC_S2 = pVideoMemory[ i + 21 ] ;
2800 pVBInfo->XG21_LVDSCapList[0].PSC_S3 = pVideoMemory[ i + 22 ] ;
2801 pVBInfo->XG21_LVDSCapList[0].PSC_S4 = pVideoMemory[ i + 23 ] ;
2802 pVBInfo->XG21_LVDSCapList[0].PSC_S5 = pVideoMemory[ i + 24 ] ;
2808 /* --------------------------------------------------------------------- */
2809 /* Function : XGINew_DDR1x_MRS_XG20 */
2813 /* --------------------------------------------------------------------- */
2814 void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
2817 XGINew_SetReg1( P3c4 , 0x18 , 0x01 ) ;
2818 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2819 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2820 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2823 XGINew_SetReg1( P3c4 , 0x18 , 0x00 ) ;
2824 XGINew_SetReg1( P3c4 , 0x19 , 0x40 ) ;
2825 XGINew_SetReg1( P3c4 , 0x16 , 0x00 ) ;
2826 XGINew_SetReg1( P3c4 , 0x16 , 0x80 ) ;
2828 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2829 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2830 XGINew_SetReg1( P3c4 , 0x19 , 0x01 ) ;
2831 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2832 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2834 XGINew_SetReg1( P3c4 , 0x1B , 0x03 ) ;
2836 /* XGINew_SetReg1( P3c4 , 0x18 , 0x31 ) ; */
2837 XGINew_SetReg1( P3c4 , 0x18 , pVBInfo->SR15[ 2 ][ XGINew_RAMType ] ) ; /* SR18 */
2838 XGINew_SetReg1( P3c4 , 0x19 , 0x00 ) ;
2839 XGINew_SetReg1( P3c4 , 0x16 , 0x03 ) ;
2840 XGINew_SetReg1( P3c4 , 0x16 , 0x83 ) ;
2841 XGINew_SetReg1( P3c4 , 0x1B , 0x00 ) ;
2844 /* --------------------------------------------------------------------- */
2845 /* Function : XGINew_SetDRAMModeRegister_XG20 */
2849 /* --------------------------------------------------------------------- */
2850 void XGINew_SetDRAMModeRegister_XG20(struct xgi_hw_device_info *HwDeviceExtension)
2852 struct vb_device_info VBINF;
2853 struct vb_device_info *pVBInfo = &VBINF;
2854 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2855 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2856 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2857 pVBInfo->ISXPDOS = 0 ;
2859 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2860 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2861 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2862 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2863 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2864 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2865 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2866 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2867 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2868 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2869 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2870 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2871 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2872 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2873 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2874 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2875 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2877 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2879 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2881 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2882 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2884 XGINew_DDR2_MRS_XG20( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2886 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2889 void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
2891 struct vb_device_info VBINF;
2892 struct vb_device_info *pVBInfo = &VBINF;
2893 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2894 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2895 pVBInfo->BaseAddr = (unsigned long)HwDeviceExtension->pjIOAddress ;
2896 pVBInfo->ISXPDOS = 0 ;
2898 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2899 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2900 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2901 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2902 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2903 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2904 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2905 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2906 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2907 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2908 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2909 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2910 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2911 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2912 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2913 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2914 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2916 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2918 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2920 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2921 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2923 //XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2924 XGINew_DDRII_Bootup_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo) ;
2926 //XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2927 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , pVBInfo->SR15[ 3 ][ XGINew_RAMType ] ) ; /* SR1B */
2931 void XGINew_SetDRAMModeRegister_XG27(struct xgi_hw_device_info *HwDeviceExtension)
2934 unsigned char data ;
2935 struct vb_device_info VBINF;
2936 struct vb_device_info *pVBInfo = &VBINF;
2937 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase ;
2938 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress ;
2939 pVBInfo->BaseAddr = HwDeviceExtension->pjIOAddress ;
2940 pVBInfo->ISXPDOS = 0 ;
2942 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14 ;
2943 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24 ;
2944 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10 ;
2945 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e ;
2946 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12 ;
2947 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a ;
2948 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16 ;
2949 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17 ;
2950 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18 ;
2951 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19 ;
2952 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A ;
2953 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00 ;
2954 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04 ;
2955 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10 ;
2956 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12 ;
2957 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 ;
2958 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2 ;
2960 InitTo330Pointer(HwDeviceExtension->jChipType,pVBInfo);
2962 ReadVBIOSTablData( HwDeviceExtension->jChipType , pVBInfo) ;
2964 if ( XGINew_GetXG20DRAMType( HwDeviceExtension, pVBInfo) == 0 )
2965 XGINew_DDR1x_MRS_XG20( pVBInfo->P3c4, pVBInfo ) ;
2967 XGINew_DDR2_MRS_XG27( HwDeviceExtension , pVBInfo->P3c4 , pVBInfo ) ;
2969 XGINew_SetReg1( pVBInfo->P3c4 , 0x1B , 0x03 ) ;
2972 /* -------------------------------------------------------- */
2973 /* Function : XGINew_ChkSenseStatus */
2977 /* -------------------------------------------------------- */
2978 void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
2980 unsigned short tempbx = 0, temp, tempcx, CR3CData;
2982 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x32 ) ;
2984 if ( temp & Monitor1Sense )
2985 tempbx |= ActiveCRT1 ;
2986 if ( temp & LCDSense )
2987 tempbx |= ActiveLCD ;
2988 if ( temp & Monitor2Sense )
2989 tempbx |= ActiveCRT2 ;
2990 if ( temp & TVSense )
2992 tempbx |= ActiveTV ;
2993 if ( temp & AVIDEOSense )
2994 tempbx |= ( ActiveAVideo << 8 );
2995 if ( temp & SVIDEOSense )
2996 tempbx |= ( ActiveSVideo << 8 );
2997 if ( temp & SCARTSense )
2998 tempbx |= ( ActiveSCART << 8 );
2999 if ( temp & HiTVSense )
3000 tempbx |= ( ActiveHiTV << 8 );
3001 if ( temp & YPbPrSense )
3002 tempbx |= ( ActiveYPbPr << 8 );
3005 tempcx = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3006 tempcx |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ) ;
3008 if ( tempbx & tempcx )
3010 CR3CData = XGINew_GetReg1( pVBInfo->P3d4 , 0x3c ) ;
3011 if ( !( CR3CData & DisplayDeviceFromCMOS ) )
3014 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3023 if ( *pVBInfo->pSoftSetting & ModeSoftSetting )
3030 XGINew_SetReg1( pVBInfo->P3d4, 0x3d , ( tempbx & 0x00FF ) ) ;
3031 XGINew_SetReg1( pVBInfo->P3d4, 0x3e , ( ( tempbx & 0xFF00 ) >> 8 )) ;
3033 /* -------------------------------------------------------- */
3034 /* Function : XGINew_SetModeScratch */
3038 /* -------------------------------------------------------- */
3039 void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3041 unsigned short temp , tempcl = 0 , tempch = 0 , CR31Data , CR38Data;
3043 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x3d ) ;
3044 temp |= XGINew_GetReg1( pVBInfo->P3d4 , 0x3e ) << 8 ;
3045 temp |= ( XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) & ( DriverMode >> 8) ) << 8 ;
3047 if ( pVBInfo->IF_DEF_CRT2Monitor == 1)
3049 if ( temp & ActiveCRT2 )
3050 tempcl = SetCRT2ToRAMDAC ;
3053 if ( temp & ActiveLCD )
3055 tempcl |= SetCRT2ToLCD ;
3056 if ( temp & DriverMode )
3058 if ( temp & ActiveTV )
3060 tempch = SetToLCDA | EnableDualEdge ;
3061 temp ^= SetCRT2ToLCD ;
3063 if ( ( temp >> 8 ) & ActiveAVideo )
3064 tempcl |= SetCRT2ToAVIDEO ;
3065 if ( ( temp >> 8 ) & ActiveSVideo )
3066 tempcl |= SetCRT2ToSVIDEO ;
3067 if ( ( temp >> 8 ) & ActiveSCART )
3068 tempcl |= SetCRT2ToSCART ;
3070 if ( pVBInfo->IF_DEF_HiVision == 1 )
3072 if ( ( temp >> 8 ) & ActiveHiTV )
3073 tempcl |= SetCRT2ToHiVisionTV ;
3076 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3078 if ( ( temp >> 8 ) & ActiveYPbPr )
3079 tempch |= SetYPbPr ;
3086 if ( ( temp >> 8 ) & ActiveAVideo )
3087 tempcl |= SetCRT2ToAVIDEO ;
3088 if ( ( temp >> 8 ) & ActiveSVideo )
3089 tempcl |= SetCRT2ToSVIDEO ;
3090 if ( ( temp >> 8 ) & ActiveSCART )
3091 tempcl |= SetCRT2ToSCART ;
3093 if ( pVBInfo->IF_DEF_HiVision == 1 )
3095 if ( ( temp >> 8 ) & ActiveHiTV )
3096 tempcl |= SetCRT2ToHiVisionTV ;
3099 if ( pVBInfo->IF_DEF_YPbPr == 1 )
3101 if ( ( temp >> 8 ) & ActiveYPbPr )
3102 tempch |= SetYPbPr ;
3107 tempcl |= SetSimuScanMode ;
3108 if ( (!( temp & ActiveCRT1 )) && ( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3109 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3110 if ( ( temp & ActiveLCD ) && ( temp & ActiveTV ) )
3111 tempcl ^= ( SetSimuScanMode | SwitchToCRT2 ) ;
3112 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , tempcl ) ;
3114 CR31Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x31 ) ;
3115 CR31Data &= ~( SetNotSimuMode >> 8 ) ;
3116 if ( !( temp & ActiveCRT1 ) )
3117 CR31Data |= ( SetNotSimuMode >> 8 ) ;
3118 CR31Data &= ~( DisableCRT2Display >> 8 ) ;
3119 if (!( ( temp & ActiveLCD ) || ( temp & ActiveTV ) || ( temp & ActiveCRT2 ) ) )
3120 CR31Data |= ( DisableCRT2Display >> 8 ) ;
3121 XGINew_SetReg1( pVBInfo->P3d4, 0x31 , CR31Data ) ;
3123 CR38Data = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3124 CR38Data &= ~SetYPbPr ;
3125 CR38Data |= tempch ;
3126 XGINew_SetReg1( pVBInfo->P3d4, 0x38 , CR38Data ) ;
3130 /* -------------------------------------------------------- */
3131 /* Function : XGINew_GetXG21Sense */
3135 /* -------------------------------------------------------- */
3136 void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3139 volatile unsigned char *pVideoMemory = (unsigned char *)pVBInfo->ROMAddr;
3141 pVBInfo->IF_DEF_LVDS = 0 ;
3144 if (( pVideoMemory[ 0x65 ] & 0x01 ) ) /* For XG21 LVDS */
3146 pVBInfo->IF_DEF_LVDS = 1 ;
3147 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3148 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS on chip */
3153 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* Enable GPIOA/B read */
3154 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0xC0;
3156 { /* DVI & DVO GPIOA/B pull high */
3157 XGINew_SenseLCD( HwDeviceExtension, pVBInfo ) ;
3158 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3159 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x20 , 0x20 ) ; /* Enable read GPIOF */
3160 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x04 ;
3162 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0x80 ) ; /* TMDS on chip */
3164 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* Only DVO on chip */
3165 XGINew_SetRegAND( pVBInfo->P3d4 , 0x4A , ~0x20 ) ; /* Disable read GPIOF */
3172 /* -------------------------------------------------------- */
3173 /* Function : XGINew_GetXG27Sense */
3177 /* -------------------------------------------------------- */
3178 void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
3180 unsigned char Temp, bCR4A;
3182 pVBInfo->IF_DEF_LVDS = 0 ;
3183 bCR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3184 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x07 , 0x07 ) ; /* Enable GPIOA/B/C read */
3185 Temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) & 0x07;
3186 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , bCR4A ) ;
3190 pVBInfo->IF_DEF_LVDS = 1 ;
3191 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xC0 ) ; /* LVDS setting */
3192 XGINew_SetReg1( pVBInfo->P3d4, 0x30 , 0x21 ) ;
3196 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x38 , ~0xE0 , 0xA0 ) ; /* TMDS/DVO setting */
3198 XGINew_SetRegOR( pVBInfo->P3d4 , 0x32 , LCDSense ) ;
3202 unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
3204 unsigned char CR38, CR4A, temp;
3206 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3207 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x10 , 0x10 ) ; /* enable GPIOE read */
3208 CR38 = XGINew_GetReg1( pVBInfo->P3d4 , 0x38 ) ;
3210 if ( ( CR38 & 0xE0 ) > 0x80 )
3212 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3217 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;
3222 unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
3224 unsigned char CR4A, temp;
3226 CR4A = XGINew_GetReg1( pVBInfo->P3d4 , 0x4A ) ;
3227 XGINew_SetRegANDOR( pVBInfo->P3d4 , 0x4A , ~0x03 , 0x03 ) ; /* enable GPIOA/B/C read */
3228 temp = XGINew_GetReg1( pVBInfo->P3d4 , 0x48 ) ;
3235 temp = ((temp&0x04)>>1) || ((~temp)&0x01);
3237 XGINew_SetReg1( pVBInfo->P3d4, 0x4A , CR4A ) ;